Driving backplane, display panel, and tiled display device

Abstract

The present disclosure provides a driving backplane, a display panel, and a tiled display device. The driving backplane comprises: a base substrate; a pixel driving circuit located on the base substrate; and a wiring layer located on the side of the pixel driving circuit facing away from the base substrate, the wiring layer comprising a potential wire and a pattern of a binding electrode, and the binding electrode being used for binding a micro light emitting diode; wherein the distance between the outermost edge of the wiring layer and the outermost edge of the base substrate is smaller than the distance between the outermost edge of the pixel driving circuit and the outermost edge of the base substrate.

Description

A driving backplane, display panel and spliced ​​display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on July 21, 2023, with application number 202310907539.4 and invention name "A driving backplane, display panel and spliced ​​display device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a driving backplane, a display panel, and a spliced ​​display device. Background Art

[0004] Sub-millimeter light emitting diodes (Mini LED) or micro LEDs (Micro LED) are miniaturized LED array structures that are widely used due to their advantages such as ultra-high contrast, wide color gamut, low power consumption, and splicing capabilities.

[0005] For production, yield is the main factor affecting cost. The high incidence of electrostatic discharge (ESD) during the production process directly leads to a decrease in product yield, which in turn leads to an increase in cost.

[0006] Summary of the Invention

[0007] The present disclosure provides a driving backplane, a display panel, and a spliced ​​display device, the specific solutions of which are as follows:

[0008] An embodiment of the present disclosure provides a driving backplane, comprising:

[0009] substrate;

[0010] a pixel driving circuit located on the substrate;

[0011] a wiring layer located on a side of the pixel driving circuit away from the substrate, the wiring layer including a pattern of potential traces and binding electrodes, the binding electrodes being used to bind the micro-LEDs;

[0012] The distance between the outermost edge of the wiring layer and the same-side edge of the base substrate is smaller than the distance between the outermost edge of the pixel driving circuit and the same-side edge of the base substrate.

[0013] Optionally, in an embodiment of the present disclosure, the driving backplane further includes a switching electrode located between the potential trace and the base substrate and electrically connected to the potential trace and the pixel driving circuit respectively. The orthographic projection of the potential trace on the base substrate and the orthographic projection of the switching electrode on the base substrate are arranged in a mesh structure, and the mesh structure is configured as an electrostatic protection unit.

[0014] Optionally, in an embodiment of the present disclosure, the potential traces include edge traces located at the outermost sides and middle traces located in the middle area, and the line width of the edge traces is smaller than the line width of the middle traces.

[0015] Optionally, in an embodiment of the present disclosure, the binding electrode located at the outermost edge of the wiring layer is arranged flush with the edge trace on the same side.

[0016] Optionally, in an embodiment of the present disclosure, the substrate is divided into a plurality of light zones arranged in an array, and two adjacent light zones in the plurality of light zones are arranged at equal distances, and each of the light zones is configured to be electrically connected to a corresponding micro-light-emitting diode through the potential wiring and the binding electrode in the corresponding area.

[0017] Optionally, in an embodiment of the present disclosure, along a direction away from the base substrate, the conductive layer of the pixel driving circuit includes a first gate layer, an active layer, a second gate layer and a first source-drain electrode layer arranged in sequence; the driving backplane includes an insulating layer and a second source-drain electrode layer arranged in sequence on the side of the first source-drain electrode layer away from the base substrate; the transfer electrode is located in the first source-drain electrode layer, and the potential wiring and the binding electrode are located in the second source-drain electrode layer.

[0018] Optionally, in the embodiment of the present disclosure, the edge routing is discontinuously arranged along the extension direction of the outermost edge of the wiring layer to form a plurality of discontinuous portions, and each of the discontinuous portions is electrically connected through a transfer electrode formed by the first source-drain electrode layer.

[0019] Optionally, in the embodiment of the present disclosure, the orthographic projection of the outermost edge of the pixel driving circuit on the base substrate overlaps with the orthographic projection of the same side edge of the first source / drain electrode layer on the base substrate.

[0020] Optionally, in the embodiment of the present disclosure, the distance between the outermost edge of the wiring layer and the same side edge of the substrate is in the range of 139 μm to 179 μm, and the distance between the outermost edge of the pixel driving circuit and the same side edge of the substrate is in the range of 180 μm to 220 μm.

[0021] Accordingly, an embodiment of the present disclosure provides a display panel, comprising:

[0022] A driving backplane as described in any one of the above items, and a plurality of micro light-emitting diodes bound to the driving backplane.

[0023] Accordingly, an embodiment of the present disclosure provides a spliced ​​display device, comprising:

[0024] A plurality of display panels as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic diagram of a top view of a driving backplane in the related art;

[0026] FIG2 is a schematic diagram of a top view of a driving backplane provided in an embodiment of the present disclosure;

[0027] FIG3 is a schematic diagram of a cross-sectional structure taken along the direction indicated by MM in FIG2 ;

[0028] FIG4 is a schematic diagram of a cross-sectional structure taken along the direction indicated by MM in FIG2 ;

[0029] FIG5 is a schematic top view of one configuration of potential wiring and transfer wiring in a driver backplane according to an embodiment of the present disclosure;

[0030] FIG6 is a schematic diagram of a top view of a potential routing structure in a driving backplane provided by an embodiment of the present disclosure;

[0031] FIG7 is a schematic diagram of a top view of a driving backplane provided in an embodiment of the present disclosure;

[0032] FIG8 is a schematic diagram of a cross-sectional structure taken along the direction indicated by MM in FIG2 ;

[0033] FIG9 is a schematic top view of an edge routing structure of a driver backplane provided by an embodiment of the present disclosure;

[0034] FIG10 is a pattern of the first gate layer in region Q in FIG2 ;

[0035] FIG11 is a pattern of the active layer in region Q in FIG2 ;

[0036] FIG12 is a pattern of the second gate layer in region Q in FIG2 ;

[0037] FIG13 is a pattern of the first source-drain electrode layer in region Q in FIG2 ;

[0038] FIG14 is a pattern of the second source-drain electrode layer in region Q in FIG2 ;

[0039] FIG15 is a pattern of the superposition of relevant conductive layers in region Q in FIG2 ;

[0040] FIG16 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0041] FIG17 is a schematic structural diagram of a spliced ​​display device provided by an embodiment of the present disclosure;

[0042] FIG18 is a schematic diagram of a partial top view of the structure of two display panels spliced ​​together;

[0043] FIG19 is a simplified top view schematic diagram of the structure of a single display panel in FIG18 before part of the pixel driving circuit is moved inward;

[0044] FIG20 is a simplified top view schematic diagram of the structure of a single display panel in FIG18 after part of the pixel driving circuit is moved inward. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0047] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0048] In the related art, a production process is often used to manufacture a driver backplane as shown in Figure 1, where 01 represents the setting area of ​​the pixel circuit, 02 represents the setting area of ​​the top conductive layer, and 03 represents the backplane. The pixel circuit is closer to the edge of the driver backplane than the top conductive layer (such as the Cu layer) coupled to it. In the production process of the driver backplane, the edge of the backplane is the location most prone to ESD. When ESD occurs at the edge of the backplane during the process, since the backplane is not connected to any signal, the pixel circuit is divided into multiple independent units by its corresponding thin film transistors (TFTs), blocking the discharge path of the charge. The ESD will damage the pixel circuit, resulting in defects.

[0049] In view of this, embodiments of the present disclosure provide a driving backplane, a display panel, and a spliced ​​display device for effectively conducting ESD and improving the backplane yield.

[0050] As shown in Figures 2 and 3, Figure 2 is a schematic diagram of a top view of a drive backplane provided by an embodiment of the present disclosure, and Figure 3 is a schematic diagram of a cross-sectional structure along the direction indicated by MM in Figure 2. Specifically, the drive backplane includes:

[0051] Base substrate 10;

[0052] A pixel driving circuit 20 located on the base substrate 10;

[0053] A wiring layer 30 located on a side of the pixel driving circuit 20 away from the base substrate 10 , the wiring layer 30 including a pattern of potential traces 31 and binding electrodes 32 , the binding electrodes 32 being used for binding micro-LEDs;

[0054] The distance between the outermost edge of the wiring layer 30 and the same side edge of the base substrate 10 is smaller than the distance between the outermost edge of the pixel driving circuit 20 and the same side edge of the base substrate 10 .

[0055] In a specific implementation, the driving backplane includes a base substrate 10, a pixel driving circuit 20, and a wiring layer 30. For example, the base substrate 10 can be a rigid substrate, such as a glass substrate, a silicon-based substrate, etc.; it can also be a flexible substrate, such as a polyimide (PI) substrate. Of course, the specific material of the base substrate 10 can also be set according to actual application needs, which is not limited here. Moreover, the pixel driving circuit 20 is provided on the base substrate 10, and the wiring layer 30 is located on the side of the pixel driving circuit 20 facing away from the base substrate 10, wherein the wiring layer 30 includes a pattern of potential traces 31 and binding electrodes 32. For example, the potential traces 31 and the binding electrodes 32 are made of the same conductive layer of the same material. For example, the potential traces 31 can be a constant potential power trace, such as a high potential trace, a low potential trace, etc. In actual applications, the binding electrodes 32 are used to bind the micro-LEDs, and accordingly, the pixel driving circuit 20 is used to drive the micro-LEDs to emit light and display. For example, the micro-LEDs can be Mini LEDs or Micro LEDs, which are not limited here. In practical applications, the specific number and arrangement of the micro-LEDs can be set according to actual needs and are not limited here.

[0056] In addition, the distance between the outermost edge of the wiring layer 30 and the same-side edge of the base substrate 10 is smaller than the distance between the outermost edge of the pixel driving circuit 20 and the same-side edge of the base substrate 10. As shown in FIG2 , a represents the distance between the outermost edge of the wiring layer 30 and the same-side edge of the base substrate 10, and b represents the distance between the outermost edge of the pixel driving circuit 20 and the same-side edge of the base substrate 10, with a < b. In this way, during the production process, even if ESD is generated at the outermost edge of the driver backplane, the ESD can be preferentially directed through the wiring layer 30, thereby avoiding the accumulation of ESD at the pixel driving circuit 20 and improving the production yield of the driver backplane.

[0057] In the embodiment of the present disclosure, the driving backplane also includes a switching electrode 40 located between the potential trace 31 and the base substrate 10, and electrically connected to the potential trace 31 and the pixel driving circuit 20 respectively. The orthographic projection of the potential trace 31 on the base substrate 10 and the orthographic projection of the switching electrode 40 on the base substrate 10 are arranged in a mesh structure, and the mesh structure is configured as an electrostatic protection unit.

[0058] In the specific implementation process, Figure 4 is a schematic diagram of one of the cross-sectional structures along the direction indicated by MM in Figure 2. The driving backplane also includes a transfer electrode 40 located between the potential trace 31 and the base substrate 10, and electrically connected to the potential trace 31 and the pixel driving circuit 20 respectively. In this way, the potential trace 31 and the pixel driving circuit 20 are effectively electrically connected through the transfer electrode 40, ensuring that the pixel driving circuit 20 drives and controls the micro-light-emitting diode. Moreover, the positive projection of the potential trace 31 on the base substrate 10 and the positive projection of the transfer electrode 40 on the base substrate 10 are arranged in a mesh structure. Accordingly, the mesh structure is configured as an electrostatic protection unit, through which static electricity can be effectively derived. In this way, the same signal can be connected to form a corresponding mesh structure. The resistance of the mesh structure is lower and it is easier to derive static electricity, thereby improving the electrostatic protection capability of the driving backplane. Taking the exemplary embodiment shown in Figure 5 as an example, the potential trace 31 is extended in a direction parallel to the outermost edge of the base substrate 10, as shown by the arrow X in Figure 5, and the transfer electrode 40 is extended in a direction perpendicular to the outermost edge of the base substrate 10, as shown by the arrow Y in Figure 5.

[0059] In the embodiment of the present disclosure, the potential trace 31 includes an outermost edge trace 311 and a middle trace 312 in the middle region. The line width of the edge trace 311 is smaller than that of the middle trace 312 .

[0060] In the specific implementation process, as shown in Figure 6, a schematic diagram of a top view of the potential trace 31 is shown. The potential trace 31 includes an edge trace 311 located at the outermost edge and a middle trace 312 located in the middle area, wherein the line width of the edge trace 311 is smaller than the line width of the middle trace 312. In this way, under the premise that the micro-light-emitting diodes are arranged in the same manner, the edge trace 311 occupies less edge space, which provides the possibility for subsequent seamless splicing. Still in combination with the exemplary embodiment shown in Figure 6, the line width of the edge trace 311 is c, and the line width of the middle trace 312 is d, c<d. It should be noted that in actual applications, the maximum line width of the edge trace 311 may still be smaller than the line width of the middle trace 312.

[0061] In the embodiment of the present disclosure, the binding electrode 32 located at the outermost edge of the wiring layer 30 is arranged flush with the edge trace 311 on the same side.

[0062] In a specific implementation, still referring to FIG6 , the binding electrode 32 at the outermost edge of the wiring layer 30 is aligned with the edge trace 311 on the same side. This effectively reduces the space occupied by the edge trace 311 while maintaining the same arrangement of the micro-LEDs. Consequently, the edge trace 311 occupies less edge space, thus enabling subsequent seamless splicing.

[0063] In the embodiment of the present disclosure, the base substrate 10 is divided into a plurality of lamp areas 50 arranged in an array, and adjacent two lamp areas 50 in the plurality of lamp areas 50 are arranged at equal distances, and each of the lamp areas 50 is configured to be electrically connected to the corresponding micro-light-emitting diode through the potential trace 31 and the binding electrode 32 in the corresponding area.

[0064] In a specific implementation, Figure 7 shows a top view of one embodiment of the driver backplane. Specifically, the base substrate 10 is divided into a plurality of light zones 50 arranged in an array, with adjacent light zones 50 arranged equidistantly from each other. It should be noted that the term "equidistant" can mean "approximately" or "substantially" equidistant, and is not limited to this. Furthermore, each light zone 50 is electrically connected to a corresponding micro-LED via a potential trace 31 and a bonding electrode 32 within the corresponding region. Because the outermost edge of the pixel driving circuit 20 is further away from the same side edge of the base substrate 10 than the outermost edge of the wiring layer 30 in the embodiment of the present disclosure, the space occupied by the pixel driving circuit 20 at the edge of the driver backplane is effectively reduced. In particular, when the edge space is reduced and the line width of the edge trace 311 is further reduced, even if the driver backplane is spliced ​​with another driver backplane designed based on the concept of the present disclosure, the distance between the two lamp areas 50 at the outermost edges of the two driver backplanes can still be guaranteed to be equal to the distance between two adjacent lamp areas 50 within a single driver backplane, thereby ensuring display uniformity. The specific number of the multiple lamp areas 50 can be set according to actual application needs and is not limited here.

[0065] In the embodiment of the present disclosure, as shown in Figure 8, along the direction away from the base substrate 10, the conductive layer 21 of the pixel driving circuit 20 includes a first gate layer 211, an active layer 212, a second gate layer 213 and a first source-drain electrode layer 214 arranged in sequence; the driving backplane includes an insulating layer 60 and a second source-drain electrode layer 70 arranged in sequence on the side of the first source-drain electrode layer 214 away from the base substrate 10; the transfer electrode 40 is located in the first source-drain electrode layer 214, and the potential trace 31 and the binding electrode 32 are located in the second source-drain electrode layer 70.

[0066] In a specific implementation, still in conjunction with FIG8 , the driving backplane further includes a buffer layer 80 disposed between the first gate layer 211 and the active layer 212, a gate insulating layer 90 disposed between the active layer 212 and the second gate layer 213; an interlayer insulating layer 91 disposed between the second gate layer 213 and the first source-drain electrode layer 214; an insulating layer 60 disposed between the first source-drain electrode layer 214 and the second source-drain electrode layer 70, including a first flat layer 61 and a first passivation layer 62 disposed sequentially away from the base substrate 10; and a second passivation layer 63, a second flat layer, and a third passivation layer 65 disposed sequentially away from the base substrate 10 on the second source-drain electrode layer 70. Of course, in addition to the aforementioned related film layers, the driving backplane provided in the embodiment of the present disclosure may also include other film layer structures according to actual application requirements, which are not limited here.

[0067] Furthermore, the transfer electrode 40 is located on the first source-drain electrode layer 214, while the potential trace 31 and the binding electrode 32 are located on the second source-drain electrode layer 70. Accordingly, the first source-drain electrode layer 214 can be used to form the pattern of the transfer electrode 40 in the same layer and material, and the second source-drain electrode layer 70 can be used to form the pattern of the potential trace 31 and the binding electrode 32 in the same layer and material. This simplifies the manufacturing process and reduces manufacturing costs.

[0068] In the embodiment of the present disclosure, the edge routing 311 is intermittently arranged along the extension direction of the outermost edge of the wiring layer 30 to form a plurality of discontinuous portions 310 , and each of the discontinuous portions 310 is electrically connected through a transfer electrode 40 formed by the first source-drain electrode layer 214 .

[0069] In a specific implementation, as shown in FIG9 , the edge trace 311 is intermittently arranged along the outermost edge of the wiring layer 30, as indicated by arrow X, to form a plurality of discontinuous portions 310. Each discontinuous portion 310 is electrically connected via a transfer electrode 40 formed by the first source / drain electrode layer 214. This reduces the edge space occupied by the edge trace 311 while ensuring signal transmission performance of the driver backplane.

[0070] In one exemplary embodiment, the orthographic projection of the outermost edge of the pixel driving circuit 20 on the base substrate 10 overlaps with the orthographic projection of the same-side edge of the first source / drain electrode layer 214 on the base substrate 10. In other words, the outermost edge of the first source / drain electrode layer 214 is the outermost edge on the same side of the pixel driving circuit 20.

[0071] In order to clearly illustrate the inventive concept of the present disclosure, a corresponding explanation is provided in conjunction with a specific layout. In one exemplary embodiment, in conjunction with Figures 10 to 15, Figure 10 is a pattern of the first gate layer 211 in region Q in Figure 2, Figure 11 is a pattern of the active layer 212 in region Q in Figure 2, Figure 12 is a pattern of the second gate layer 213 in region Q in Figure 2, Figure 13 is a pattern of the first source-drain electrode layer 214 in region Q in Figure 2, Figure 14 is a pattern of the second source-drain electrode layer 70 in region Q in Figure 2, and Figure 15 is a pattern of the superposition of the relevant conductive layers 21 in region Q in Figure 2. It should be noted that in one of the exemplary embodiments, the structure within the dotted box in Figures 10 to 13 actually corresponds to the minimum repeating unit of the pixel driving circuit 20, which is set corresponding to two sub-pixels. Accordingly, area Q is actually set corresponding to 2*12 sub-pixels. If each pixel includes 3 sub-pixels including a red sub-pixel, a green sub-pixel, and a blue sub-pixel, it is set corresponding to 2*4 pixels. In the actual process, the pixel driving circuit 20 corresponding to 2*12 sub-pixels can be used as the basic inward shift unit, and the center of the pixel driving circuit 20 corresponding to these 24 sub-pixels can be used as the reference for inward shifting. The center position remains unchanged before and after the inward shift. In this way, the space occupied by the driving backplane at the edge is reduced, while taking into account the electrostatic protection capability, it provides the possibility for subsequent splicing. Among them, the cross-sectional structure schematic diagram along the direction indicated by NN in Figure 15 can be as shown in Figure 8. The introduction of the relevant structural film layer refers to the description of the relevant part above and will not be repeated here.

[0072] In the embodiment of the present disclosure, the distance between the outermost edge of the wiring layer 30 and the edge on the same side of the base substrate 10 ranges from 139 μm to 179 μm, and the distance between the outermost edge of the pixel driving circuit 20 and the edge on the same side of the base substrate 10 ranges from 180 μm to 220 μm. For example, the distance between the outermost edge of the wiring layer 30 and the edge on the same side of the base substrate 10 is 159 μm, and the distance between the outermost edge of the pixel driving circuit 20 and the edge on the same side of the base substrate 10 is 200 μm. Of course, the specific distance value between the outermost edge of the wiring layer 30 and the edge on the same side of the base substrate 10, as well as the specific distance value between the outermost edge of the pixel driving circuit 20 and the edge on the same side of the base substrate 10, can also be set according to actual application needs, and are not limited here.

[0073] Based on the same disclosed concept, as shown in FIG16 , an embodiment of the present disclosure further provides a display panel, comprising a driver backplane 100 as described above, and a plurality of micro-LEDs 200 attached to the driver backplane 100. The plurality of micro-LEDs 200 can be configured based on actual application needs and are not limited herein. The principles of solving the problem in this display panel are similar to those of the aforementioned driver backplane 100. Therefore, the implementation of this display panel can refer to the implementation of the aforementioned driver backplane 100, and any repetitions will not be repeated.

[0074] In specific implementations, the display panel provided by the embodiments of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display panel are well understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting the present invention.

[0075] Based on the same disclosed concept, as shown in FIG17 , an embodiment of the present disclosure further provides a spliced ​​display device, which includes a plurality of display panels 1000 as described above. The principles of solving the problem of this spliced ​​display device are similar to those of the aforementioned driving backplane 100 . Therefore, the implementation of this spliced ​​display device can refer to the implementation of the aforementioned driving backplane 100 , and the repeated parts will not be repeated.

[0076] It should be noted that the inventors discovered through actual research that to achieve a narrow bezel design for a single driver backplane, or even seamless splicing between driver backplanes, the design space around the driver backplane edges is often smaller than within the plane. However, during the production process, the driver backplane edges may have cutting paths and grinding lines. If any wiring exists beneath these lines, they can cause film breakage, short circuits, and reliability risks.

[0077] In one of the exemplary embodiments, taking two driving backplanes as an example, as shown in FIG18 , the circular structure represents a single micro-LED. In order to ensure that the distance between the two micro-LEDs at the edge of the two spliced ​​driving backplanes is consistent with the setting distance within the surface of a single driving backplane (i.e., d1=d2), while leaving space for cutting paths and grinding lines, the space left for pixel driving circuits and potential traces will be relatively reduced. In the embodiment of the present disclosure, the gaps between the pixel driving circuits corresponding to multiple sub-pixels can be merged to make more space at the edge of the driving backplane. Moreover, in the embodiment of the present disclosure, the outermost edge of the pixel driving circuit is farther away from the same side edge of the substrate than the edge of the wiring layer, which is equivalent to the pixel driving circuit being moved into the surface of the single driving backplane. As shown in Figures 19 and 20, Figure 19 is a simplified schematic diagram of the top view structure before inward movement, and Figure 20 is a simplified schematic diagram of the top view structure after inward movement. The dotted boxes A and B represent edge space. In one exemplary embodiment, taking the pixel driving circuit corresponding to 2*12 sub-pixels as a basic unit as an example, the edge space before inward movement is small, which can easily damage the circuit during the production process, reducing the production yield. After inward movement, the edge space is effectively improved compared to before inward movement. In the embodiment of the present disclosure, although the edge space is still relatively small and the line width of the edge routing is smaller than the line width of the middle routing, the inward movement of the pixel driving circuit makes the outermost edge of the wiring layer closer to the same side edge of the substrate. The wiring layer can shield the pixel driving circuit to a certain extent, so that ESD can be effectively guided out through the wiring layer, thereby improving the production yield.

[0078] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0079] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A driving backplane, wherein: include: substrate substrate; A pixel driving circuit located on the substrate; A wiring layer located on a side of the pixel driving circuit away from the substrate, the wiring layer comprising a pattern of potential wiring and binding electrodes, the binding electrodes being used to bind the micro light emitting diodes; Wherein, the distance between the outermost edge of the wiring layer and the edge of the substrate on the same side is smaller than the distance between the outermost edge of the pixel driving circuit and the edge of the substrate on the same side.

2. The driving backplane according to claim 1, wherein: It also includes a switching electrode located between the potential wiring and the base substrate and electrically connected to the potential wiring and the pixel driving circuit respectively. The orthographic projection of the potential wiring on the base substrate and the orthographic projection of the switching electrode on the base substrate are arranged in a mesh structure, and the mesh structure is configured as an electrostatic protection unit.

3. The driving backplane according to claim 2, wherein: The potential wiring includes an outermost edge wiring and a middle wiring located in a middle area, and the line width of the edge wiring is smaller than the line width of the middle wiring.

4. The driving backplane according to claim 3, wherein: The binding electrode located at the outermost edge of the wiring layer is arranged flush with the edge wiring on the same side.

5. The driving backplane according to any one of claims 1 to 4, wherein: The base substrate is divided into a plurality of lamp areas arranged in an array, wherein two adjacent lamp areas in the plurality of lamp areas are arranged at equal distances, and each of the lamp areas is configured to be electrically connected to a corresponding micro-LED through the potential wiring and the binding electrode in the corresponding area.

6. The driving backplane according to claim 5, wherein: Along the direction away from the base substrate, the conductive layer of the pixel driving circuit includes a first gate layer, an active layer, a second gate layer and a first source-drain electrode layer arranged in sequence; the driving backplane includes an insulating layer and a second source-drain electrode layer arranged in sequence on the side of the first source-drain electrode layer away from the base substrate; the transfer electrode is located in the first source-drain electrode layer, and the potential routing and the binding electrode are located in the second source-drain electrode layer.

7. The driving backplane according to claim 6, wherein: Along the extension direction of the outermost edge of the wiring layer, the edge routing is discontinuously arranged to form a plurality of discontinuous portions, and each of the discontinuous portions is electrically connected via a transfer electrode formed by the first source-drain electrode layer.

8. The driving backplane according to claim 7, wherein: The orthographic projection of the outermost edge of the pixel driving circuit on the base substrate is overlapped with the orthographic projection of the same side edge of the first source-drain electrode layer on the base substrate.

9. The driving backplane according to any one of claims 1 to 8, wherein: The distance between the outermost edge of the wiring layer and the same side edge of the base substrate ranges from 139 μm to 179 μm, and the distance between the outermost edge of the pixel driving circuit and the same side edge of the base substrate ranges from 180 μm to 220 μm.

10. A display panel, wherein: include: A driving backplane as described in any one of claims 1 to 9, and a plurality of micro light emitting diodes bound to the driving backplane.

11. A spliced ​​display device, wherein: include: A plurality of display panels as claimed in claim 10.

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