Display panel, driving method and display apparatus

Abstract

Provided in the present disclosure are a display panel, a driving method and a display apparatus. The display panel comprises a plurality of rows and columns of sub-pixels, a plurality of columns of data lines, and a data voltage supply circuit, wherein the same data line is electrically connected to sub-pixels of the same color; the data voltage supply circuit is electrically connected to a multiplexing control line, a plurality of data voltage supply ends and the plurality of columns of data lines, respectively, and is used for under the control of a multiplexing control signal supplied by the multiplexing control line, supplying, to at least two columns of data lines in a time-division manner, a data voltage supplied by the same data voltage supply end; and the at least two columns of data lines are electrically connected to sub-pixels of the same color. In the present disclosure, when a solid color screen is displayed, a data voltage supplied by a driving integrated circuit by means of a data voltage supply end is not subjected to high-frequency conversion between data voltages of different colors, thereby greatly reducing the power consumption of a display panel.

Description

Display panel, driving method and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310920178.7 filed in China on July 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel, a driving method, and a display device. Background Art

[0004] In related technologies, with the development of OLED (organic light-emitting diode) display technology and the increasing demand for high refresh rates, a pixel structure with two data lines and a one-to-two Dmux (demultiplexing) circuit has become a common design to provide sufficient sub-pixel charging time. Since RGBG (red, green, blue, and green) is the most common pixel arrangement, connecting red and green sub-pixels on the same data line via a Dmux circuit causes the data voltage provided by the Driver IC (driver integrated circuit) to frequently switch between the red and blue data voltages when displaying a pure red and blue image. This increases the power consumption of the Driver IC.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a display panel including multiple rows and columns of sub-pixels, multiple columns of data lines, and a data voltage supply circuit;

[0007] The same data line is electrically connected to sub-pixels of the same color;

[0008] The data voltage supply circuit is electrically connected to the multiplexing control line, the multiple data voltage supply terminals and the multiple column data lines respectively, and is used to provide the data voltage provided by the same data voltage supply terminal to at least two column data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line;

[0009] The at least two columns of data lines are electrically connected to sub-pixels of the same color.

[0010] Optionally, two columns of data lines are provided between two adjacent columns of sub-pixels;

[0011] The even-numbered columns of sub-pixels included in the display panel are first color sub-pixels;

[0012] The sub-pixels in the 4n-3rd columns of the odd-numbered rows of the display panel are sub-pixels of the second color, and the sub-pixels in the 4n-3rd columns of the even-numbered rows of the display panel are sub-pixels of the third color;

[0013] The sub-pixels in the 4n-1th column of the odd-numbered rows of the display panel are sub-pixels of the third color, and the sub-pixels in the 4n-1th column of the even-numbered rows of the display panel are sub-pixels of the second color;

[0014] n is a positive integer greater than or equal to 1.

[0015] Optionally, the data line in the 8m-7th column is electrically connected to the second color sub-pixel in the 4m-3th column;

[0016] The data line in the 8m-6 column is electrically connected to the third color sub-pixel in the 4m-3 column;

[0017] The data line in the 8m-5 column is electrically connected to a portion of the first color sub-pixels located in the 4m-2 column;

[0018] The data line in the 8m-4 column is electrically connected to another portion of the first color sub-pixels in the 4m-2 column;

[0019] The data line in the 8m-3 column is electrically connected to the third color sub-pixel in the 4m-1 column;

[0020] The data line in the 8m-2 column is electrically connected to the second color sub-pixel in the 4m-1 column;

[0021] The data line in the 8m-1 column is electrically connected to a portion of the first color sub-pixels located in the 4m column;

[0022] The data line in the 8mth column is electrically connected to another portion of the first color sub-pixels in the 4mth column;

[0023] m is a positive integer greater than or equal to 1.

[0024] Optionally, the data voltage supply circuit includes a first supply circuit, a second supply circuit, and a third supply circuit; the multiple data voltage supply terminals include multiple first supply terminals, multiple second supply terminals, and multiple third supply terminals;

[0025] The first supply terminal is a data voltage supply terminal for providing a first color data voltage, the second supply terminal is a data voltage supply terminal for providing a second color data voltage, and the third supply terminal is a data voltage supply terminal for providing a third color data voltage;

[0026] The first providing circuit is electrically connected to the multiplexing control line, the plurality of first providing terminals and the plurality of columns of first data lines respectively, and is used to write the first color data voltage provided by the same first providing terminal into at least two columns of first data lines in a time-sharing manner under the control of the multiplexing control signal;

[0027] The second providing circuit is electrically connected to the multiplexing control line, the plurality of second providing terminals and the plurality of columns of second data lines respectively, and is used to write the second color data voltage provided by the same second providing terminal into at least two columns of second data lines in a time-sharing manner under the control of the multiplexing control signal;

[0028] The third providing circuit is electrically connected to the multiplexing control line, multiple third providing terminals and multiple columns of third data lines respectively, and is used to write the third color data voltage provided by the same third providing terminal into at least two columns of third data lines in a time-sharing manner under the control of the multiplexing control signal;

[0029] The first data line is electrically connected to the first color sub-pixel, the second data line is electrically connected to the second color sub-pixel, and the third data line is electrically connected to the third color sub-pixel.

[0030] Optionally, the multiplexed control line includes a first control line and a second control line;

[0031] The first providing circuit includes a plurality of first providing sub-circuits;

[0032] The ath first providing sub-circuit is electrically connected to the first control line, the second control line, the ath first providing terminal, the 4a-1 column data line, and the 4a column data line, respectively, and is configured to write the first color data voltage provided by the ath first providing terminal into the 4a-1 column data line under the control of a first control signal provided by the first control line, and to write the first color data voltage provided by the ath first providing terminal into the 4a column data line under the control of a second control signal provided by the second control line;

[0033] a is a positive integer greater than or equal to 1.

[0034] Optionally, the ath first providing sub-circuit includes an ath first transistor and an ath second transistor;

[0035] The gate of the a-th first transistor is electrically connected to the first control line, the first electrode of the a-th first transistor is electrically connected to the a-th first supply terminal, and the second electrode of the a-th first transistor is electrically connected to the 4a-1 column data line;

[0036] The gate of the ath second transistor is electrically connected to the second control line, the first electrode of the ath second transistor is electrically connected to the ath first supply terminal, and the second electrode of the ath second transistor is electrically connected to the 4a column data line.

[0037] Optionally, the multiplexed control line includes a first control line and a second control line;

[0038] The first providing circuit includes a plurality of first providing sub-circuits;

[0039] The 2a-1th first providing sub-circuit is electrically connected to the first control line, the second control line, the 2a-1th first providing terminal, the 8a-5th column data line, and the 8a column data line, respectively, and is configured to write the first color data voltage provided by the 2a-1th first providing terminal into the 8a-5th column data line under the control of a first control signal provided by the first control line, and to write the first color data voltage provided by the 2a-1th first providing terminal into the 8a column data line under the control of a second control signal provided by the second control line;

[0040] The 2a first providing sub-circuit is electrically connected to the first control line, the second control line, the 2a first providing terminal, the 8a-4 column data line, and the 8a-1 column data line, respectively, and is configured to write the first color data voltage provided by the 2a first providing terminal into the 8a-1 column data line under the control of a first control signal provided by the first control line, and to write the first color data voltage provided by the 2a first providing terminal into the 8a-4 column data line under the control of a second control signal provided by the second control line;

[0041] a is a positive integer greater than or equal to 1.

[0042] Optionally, the 2a-1th first providing sub-circuit includes a 2a-1th first transistor and a 2a-1th second transistor;

[0043] The gate of the 2a-1th first transistor is electrically connected to the first control line, the first electrode of the 2a-1th first transistor is electrically connected to the 2a-1th first supply terminal, and the second electrode of the 2a-1th first transistor is electrically connected to the 8a-5th column data line;

[0044] The gate of the 2a-1 second transistor is electrically connected to the second control line, the first electrode of the 2a-1 second transistor is electrically connected to the 2a-1 first supply terminal, and the second electrode of the 2a-1 second transistor is electrically connected to the 8a column data line;

[0045] The 2a-th first providing sub-circuit includes a 2a-th first transistor and a 2a-th second transistor;

[0046] The gate of the 2a-th first transistor is electrically connected to the first control line, the first electrode of the 2a-th first transistor is electrically connected to the 2a-th first supply terminal, and the second electrode of the 2a-th first transistor is electrically connected to the 8a-1-th column data line;

[0047] The gate of the 2a-th second transistor is electrically connected to the second control line, the first electrode of the 2a-th second transistor is electrically connected to the 2a-th first supply terminal, and the second electrode of the 2a-th second transistor is electrically connected to the 8a-4 column data line.

[0048] Optionally, the multiplexed control line includes a first control line and a second control line;

[0049] The second providing circuit includes a plurality of second providing sub-circuits;

[0050] The ath second providing sub-circuit is electrically connected to the first control line, the second control line, the ath second providing terminal, the 8a-7th column data line, and the 8a-2nd column data line, respectively, and is configured to write the second color data voltage provided by the ath second providing terminal into the 8a-7th column data line under the control of a first control signal provided by the first control line, and to write the second color data voltage provided by the ath second providing terminal into the 8a-2nd column data line under the control of a second control signal provided by the second control line;

[0051] a is a positive integer greater than or equal to 1.

[0052] Optionally, the ath second providing sub-circuit includes an ath third transistor and an ath fourth transistor;

[0053] The gate of the ath third transistor is electrically connected to the first control line, the first electrode of the ath third transistor is electrically connected to the ath second supply terminal, and the second electrode of the ath third transistor is electrically connected to the 8a-7 column data line;

[0054] The gate of the ath fourth transistor is electrically connected to the second control line, the first electrode of the ath fourth transistor is electrically connected to the ath second supply terminal, and the second electrode of the ath fourth transistor is electrically connected to the 8a-2 column data line.

[0055] Optionally, the multiplexed control line includes a first control line and a second control line;

[0056] The third providing circuit includes a plurality of third providing sub-circuits;

[0057] an ath third providing sub-circuit electrically connected to the first control line, the second control line, the ath third providing terminal, the 8a-6th column data line, and the 8a-3rd column data line, respectively, and configured to write the third color data voltage provided by the ath third providing terminal into the 8a-3th column data line under the control of a first control signal provided by the first control line, and to write the third color data voltage provided by the ath third providing terminal into the 8a-6th column data line under the control of a second control signal provided by the second control line;

[0058] a is a positive integer greater than or equal to 1.

[0059] Optionally, the ath third providing sub-circuit includes an ath fifth transistor and an ath sixth transistor;

[0060] The gate of the ath fifth transistor is electrically connected to the second control line, the first electrode of the ath fifth transistor is electrically connected to the ath third supply terminal, and the second electrode of the ath fifth transistor is electrically connected to the 8a-6 column data line;

[0061] The gate of the ath sixth transistor is electrically connected to the first control line, the first electrode of the ath sixth transistor is electrically connected to the ath third supply terminal, and the second electrode of the ath sixth transistor is electrically connected to the 8a-3 column data line.

[0062] Optionally, the sub-pixels are arranged in an effective display area of ​​the display panel, and the data voltage providing circuit is arranged in a peripheral area of ​​the display panel.

[0063] In a second aspect, an embodiment of the present disclosure further provides a method for driving a display panel, which is applied to the above-mentioned display panel. The method for driving a display panel includes:

[0064] The data voltage supply circuit provides the data voltage provided by the same data voltage supply terminal to at least two columns of data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line;

[0065] The same data line is electrically connected to sub-pixels of the same color;

[0066] The at least two columns of data lines have sub-pixels of the same color.

[0067] In a third aspect, an embodiment of the present disclosure further provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] FIG1 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0069] FIG2 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0070] FIG3 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0071] FIG4 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0072] FIG5 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0073] FIG6 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0074] FIG7A is a layout diagram of a display panel according to at least one embodiment of the present disclosure;

[0075] FIG7B is a layout diagram of the semiconductor layer in FIG7A ;

[0076] FIG7C is a layout diagram of the first gate metal layer in FIG7A ;

[0077] FIG7D is a layout diagram of the second gate metal layer in FIG7A ;

[0078] FIG7E is a layout diagram of the source / drain metal layer in FIG7A ;

[0079] FIG8A is a layout diagram of a display panel according to at least one embodiment of the present disclosure;

[0080] FIG8B is a layout diagram of the semiconductor layer in FIG8A;

[0081] FIG8C is a layout diagram of the first gate metal layer in FIG8A ;

[0082] FIG8D is a layout diagram of the second gate metal layer in FIG8A ;

[0083] FIG. 8E is a layout diagram of the source / drain metal layer in FIG. 8A . DETAILED DESCRIPTION

[0084] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0085] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0086] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0087] The display panel according to the embodiment of the present disclosure includes a plurality of rows and columns of sub-pixels, a plurality of columns of data lines, and a data voltage supply circuit;

[0088] The same data line is electrically connected to sub-pixels of the same color;

[0089] The data voltage supply circuit is electrically connected to the multiplexing control line, the multiple data voltage supply terminals and the multiple column data lines respectively, and is used to provide the data voltage provided by the same data voltage supply terminal to at least two column data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line;

[0090] The at least two columns of data lines are electrically connected to sub-pixels of the same color.

[0091] In related technologies, with the development of OLED (organic light-emitting diode) display technology and the increasing demand for high refresh rates, a pixel structure with two data lines and a one-to-two Dmux (demultiplexing) circuit has become a common design to provide sufficient sub-pixel charging time. Since the RGBG arrangement is predominant, with the red and green sub-pixels connected on the same data line via the Dmux circuit, when displaying a pure red and blue image, the data voltage provided by the Driver IC (driver integrated circuit) undergoes a high-frequency switching between the red and blue data voltages, increasing the power consumption of the Driver IC.

[0092] The one-to-two Dumx circuit means that a data voltage supply terminal of a driving integrated circuit is electrically connected to two columns of data lines through two switches respectively, and provides corresponding data voltages to the two columns of data lines in a time-sharing manner.

[0093] Based on the above problems, in an embodiment of the present disclosure, the same data line is set to be electrically connected to sub-pixels of the same color. Under the control of a multiplexing control signal, the data voltage providing circuit provides the data voltage provided by the same data voltage providing end to at least two columns of data lines in a time-sharing manner, and the at least two columns of data lines are set to be electrically connected to sub-pixels of the same color. In this way, when displaying a pure color picture, the data voltage provided by the driving integrated circuit through the data voltage providing end will not be converted at high frequency between data voltages of different colors, thereby greatly reducing the power consumption of the display panel.

[0094] In at least one embodiment of the present disclosure, two columns of data lines are provided between two adjacent columns of sub-pixels;

[0095] The even-numbered columns of sub-pixels included in the display panel are first color sub-pixels;

[0096] The sub-pixels in the 4n-3rd columns of the odd-numbered rows of the display panel are sub-pixels of the second color, and the sub-pixels in the 4n-3rd columns of the even-numbered rows of the display panel are sub-pixels of the third color;

[0097] The sub-pixels in the 4n-1th column of the odd-numbered rows of the display panel are sub-pixels of the third color, and the sub-pixels in the 4n-1th column of the even-numbered rows of the display panel are sub-pixels of the second color;

[0098] n is a positive integer greater than or equal to 1.

[0099] Optionally, the first color may be green, the second color may be red, and the third color may be blue, but the present invention is not limited thereto. In actual operation, the first color may be green, the second color may be blue, and the third color may be red.

[0100] Optionally, the data line in the 8m-7th column is electrically connected to the second color sub-pixel in the 4m-3th column;

[0101] The data line in the 8m-6 column is electrically connected to the third color sub-pixel in the 4m-3 column;

[0102] The data line in the 8m-5 column is electrically connected to a portion of the first color sub-pixels located in the 4m-2 column;

[0103] The data line in the 8m-4 column is electrically connected to another portion of the first color sub-pixels in the 4m-2 column;

[0104] The data line in the 8m-3 column is electrically connected to the third color sub-pixel in the 4m-1 column;

[0105] The data line in the 8m-2 column is electrically connected to the second color sub-pixel in the 4m-1 column;

[0106] The data line in the 8m-1 column is electrically connected to a portion of the first color sub-pixels located in the 4m column;

[0107] The data line in the 8mth column is electrically connected to another portion of the first color sub-pixels in the 4mth column;

[0108] m is a positive integer greater than or equal to 1.

[0109] In a specific implementation, the first column data line can be electrically connected to the red sub-pixel located in the first column, the second column data line can be electrically connected to the blue sub-pixel located in the first column, the third column data line can be electrically connected to part of the green sub-pixel located in the second column, the fourth column data line can be electrically connected to another part of the green sub-pixel located in the second column, the fifth column data line can be electrically connected to the blue sub-pixel located in the third column, the sixth column data line can be electrically connected to the red sub-pixel located in the third column, the seventh column data line can be electrically connected to part of the green sub-pixel located in the fourth column, the eighth column data line can be electrically connected to another part of the green sub-pixel located in the fourth column, and so on.

[0110] In at least one embodiment of the present disclosure, the data voltage supply circuit includes a first supply circuit, a second supply circuit, and a third supply circuit; the plurality of data voltage supply terminals include a plurality of first supply terminals, a plurality of second supply terminals, and a plurality of third supply terminals;

[0111] The first supply terminal is a data voltage supply terminal for providing a first color data voltage, the second supply terminal is a data voltage supply terminal for providing a second color data voltage, and the third supply terminal is a data voltage supply terminal for providing a third color data voltage;

[0112] The first providing circuit is electrically connected to the multiplexing control line, the plurality of first providing terminals and the plurality of columns of first data lines respectively, and is used to write the first color data voltage provided by the same first providing terminal into at least two columns of first data lines in a time-sharing manner under the control of the multiplexing control signal;

[0113] The second providing circuit is electrically connected to the multiplexing control line, the plurality of second providing terminals and the plurality of columns of second data lines respectively, and is used to write the second color data voltage provided by the same second providing terminal into at least two columns of second data lines in a time-sharing manner under the control of the multiplexing control signal;

[0114] The third providing circuit is electrically connected to the multiplexing control line, multiple third providing terminals and multiple columns of third data lines respectively, and is used to write the third color data voltage provided by the same third providing terminal into at least two columns of third data lines in a time-sharing manner under the control of the multiplexing control signal;

[0115] The first data line is electrically connected to the first color sub-pixel, the second data line is electrically connected to the second color sub-pixel, and the third data line is electrically connected to the third color sub-pixel.

[0116] In a specific implementation, the data voltage providing circuit may include a first providing circuit, a second providing circuit and a third providing circuit. The first providing end provides a first color data voltage, the second providing end provides a second color data voltage, and the third providing end provides a third color data voltage. Under the control of a multiplexing control signal, the first providing circuit controls the provision of the first color data voltage to at least two columns of first data lines. Under the control of a multiplexing control signal, the second providing circuit controls the provision of the second color data voltage to at least two columns of second data lines. Under the control of a multiplexing control signal, the third providing circuit controls the provision of the third color data voltage to at least two columns of third data lines. The first data line is a data line electrically connected to the first color sub-pixel, the second data line is a data line electrically connected to the second color sub-pixel, and the third data line is a data line electrically connected to the third color sub-pixel.

[0117] As shown in FIG1 , the first column data line DL1 is electrically connected to the red sub-pixels located in the first column, the second column data line DL2 is electrically connected to the blue sub-pixels located in the first column, the third column data line DL3 is electrically connected to a portion of the green sub-pixels located in the second column, the fourth column data line DL4 is electrically connected to another portion of the sub-pixels located in the second column, the fifth column data line DL5 is electrically connected to the blue sub-pixels located in the third column, the sixth column data line DL6 is electrically connected to the red sub-pixels located in the third column, the seventh column data line DL7 is electrically connected to a portion of the green sub-pixels located in the fourth column, and the eighth column data line DL8 is electrically connected to another portion of the green sub-pixels located in the fourth column;

[0118] The ninth column data line DL9 is electrically connected to the red sub-pixel located in the fifth column, the tenth column data line DL10 is electrically connected to the blue sub-pixel located in the fifth column, the eleventh column data line DL11 is electrically connected to part of the green sub-pixel located in the sixth column, the twelfth column data line DL12 is electrically connected to another part of the sub-pixel located in the sixth column, the thirteenth column data line DL13 is electrically connected to the blue sub-pixel located in the seventh column, the fourteenth column data line DL14 is electrically connected to the red sub-pixel located in the seventh column, the fifteenth column data line DL15 is electrically connected to part of the green sub-pixel located in the eighth column, and the sixteenth column data line DL16 is electrically connected to another part of the green sub-pixel located in the eighth column.

[0119] In at least one embodiment shown in FIG. 1 , the red subpixel labeled R11 is in the first row and first column, the blue subpixel labeled B21 is in the first row and first column, the red subpixel labeled R31 is in the first row and third column, the blue subpixel labeled B41 is in the first row and fourth column, the red subpixel labeled R51 is in the first row and fifth column, and the blue subpixel labeled B61 is in the first row and sixth column.

[0120] The green sub-pixel labeled G12 is the second column in the first row, the green sub-pixel labeled G22 is the second column in the first row, the green sub-pixel labeled G32 is the second column in the third row, the green sub-pixel labeled G42 is the second column in the fourth row, the green sub-pixel labeled G52 is the second column in the fifth row, and the green sub-pixel labeled G62 is the second column in the sixth row.

[0121] The blue sub-pixel labeled B13 is in the third column of the first row; the red sub-pixel labeled R23 is in the third column of the second row; the blue sub-pixel labeled B33 is in the third column of the third row; the red sub-pixel labeled R43 is in the third column of the fourth row; the blue sub-pixel labeled B53 is in the third column of the fifth row; and the red sub-pixel labeled R63 is in the third column of the sixth row.

[0122] The green sub-pixel labeled G14 is the fourth column in the first row, the green sub-pixel labeled G24 is the fourth column in the first row, the green sub-pixel labeled G34 is the fourth column in the third row, the green sub-pixel labeled G44 is the fourth column in the fourth row, the green sub-pixel labeled G54 is the fourth column in the fifth row, and the green sub-pixel labeled G64 is the fourth column in the sixth row.

[0123] The red subpixel labeled R15 is the fifth column in the first row, the blue subpixel labeled B25 is the fifth column in the second row, the red subpixel labeled R35 is the fifth column in the third row, the blue subpixel labeled B45 is the fifth column in the fourth row, the red subpixel labeled R55 is the fifth column in the fifth row, and the blue subpixel labeled B65 is the fifth column in the sixth row.

[0124] The green sub-pixel labeled G16 is the sixth column in the first row; the green sub-pixel labeled G26 is the sixth column in the first row; the green sub-pixel labeled G36 is the sixth column in the third row; the green sub-pixel labeled G46 is the sixth column in the fourth row; the green sub-pixel labeled G56 is the sixth column in the fifth row; and the green sub-pixel labeled G66 is the sixth column in the sixth row.

[0125] The blue subpixel labeled B17 is in the seventh column of the first row; the red subpixel labeled R27 is in the seventh column of the second row; the blue subpixel labeled B37 is in the seventh column of the third row; the red subpixel labeled R47 is in the seventh column of the fourth row; the blue subpixel labeled B57 is in the seventh column of the fifth row; and the red subpixel labeled R67 is in the seventh column of the sixth row.

[0126] The green sub-pixel labeled G18 is the eighth column in the first row, the green sub-pixel labeled G28 is the eighth column in the first row, the green sub-pixel labeled G38 is the eighth column in the third row, the green sub-pixel labeled G48 is the eighth column in the fourth row, the green sub-pixel labeled G58 is the eighth column in the fifth row, and the green sub-pixel labeled G68 is the eighth column in the sixth row.

[0127] In FIG1 , the first row of gate lines is labeled GL1, the second row of gate lines is labeled GL2, the third row of gate lines is labeled GL3, the fourth row of gate lines is labeled GL4, the fifth row of gate lines is labeled GL5, and the sixth row of gate lines is labeled GL6.

[0128] In at least one embodiment shown in FIG. 1 , R11 is electrically connected to GL1 and DL1 , R31 is electrically connected to GL3 and DL1 , and R51 is electrically connected to GL5 and DL1 .

[0129] B21 is electrically connected to GL2 and DL2 respectively, B41 is electrically connected to GL4 and DL2 respectively, and B61 is electrically connected to GL6 and DL2 respectively;

[0130] G12 is electrically connected to GL1 and DL3, G22 is electrically connected to GL2 and DL4, G32 is electrically connected to GL3 and DL3, G42 is electrically connected to GL4 and DL4, G52 is electrically connected to GL5 and DL3, and G62 is electrically connected to GL6 and DL4;

[0131] B13 is electrically connected to GL1 and DL5, respectively, R23 is electrically connected to GL2 and DL6, respectively, B33 is electrically connected to GL3 and DL5, respectively, R43 is electrically connected to GL4 and DL6, respectively, B53 is electrically connected to GL5 and DL5, respectively, and R63 is electrically connected to GL6 and DL6, respectively;

[0132] G14 is electrically connected to GL1 and DL7, respectively, G24 is electrically connected to GL2 and DL8, respectively, G34 is electrically connected to GL3 and DL7, respectively, G44 is electrically connected to GL4 and DL8, respectively, G54 is electrically connected to GL5 and DL7, respectively, and G64 is electrically connected to GL6 and DL8;

[0133] R15 is electrically connected to GL1 and DL9, R35 is electrically connected to GL3 and DL9, and R55 is electrically connected to GL5 and DL9;

[0134] B25 is electrically connected to GL2 and DL10, B45 is electrically connected to GL4 and DL10, and B65 is electrically connected to GL6 and DL10;

[0135] G16 is electrically connected to GL1 and DL11, G26 is electrically connected to GL2 and DL12, G36 is electrically connected to GL3 and DL11, G46 is electrically connected to GL4 and DL12, G56 is electrically connected to GL5 and DL11, and G66 is electrically connected to GL6 and DL12;

[0136] B17 is electrically connected to GL1 and DL13, R27 is electrically connected to GL2 and DL14, B37 is electrically connected to GL3 and DL13, R47 is electrically connected to GL4 and DL14, B57 is electrically connected to GL5 and DL13, and R67 is electrically connected to GL6 and DL14;

[0137] G18 is electrically connected to GL1 and DL15 respectively, G28 is electrically connected to GL2 and DL16 respectively, G38 is electrically connected to GL3 and DL15 respectively, G48 is electrically connected to GL4 and DL16 respectively, G58 is electrically connected to GL5 and DL15 respectively, and G68 is electrically connected to GL6 and DL16 respectively.

[0138] In at least one embodiment shown in FIG. 1 , the data voltage supply circuit includes a first supply circuit 11, a second supply circuit 12, and a third supply circuit 13; the plurality of data voltage supply terminals include a first first supply terminal P11, a second first supply terminal P21, a third first supply terminal P31, a fourth first supply terminal P41, a first second supply terminal P12, a second second supply terminal P22, a first third supply terminal P13, and a second third supply terminal P23;

[0139] Each first supply terminal is used to provide a green data voltage, each second supply terminal is used to provide a red data voltage, and each third supply terminal is used to provide a blue data voltage;

[0140] The first providing circuit 11 is electrically connected to the multiplexing control line S0, the first first providing terminal P11, the second first providing terminal P21, the third first providing terminal P31, the fourth first providing terminal P41, the third column data line DL3, the fourth column data line DL4, the seventh column data line DL7, the eighth column data line DL8, the eleventh column data line DL11, the twelfth column data line DL12, the fifteenth column data line DL15 and the sixteenth column data line DL16, respectively, and is used to control the first and second columns of the data line DL11 to be connected to the multiplexing control line S0 under the control of the multiplexing control signal provided by the multiplexing control line S0. The first color data voltage provided by the first supply terminal P11 is written into the third column data line DL3 and the fourth column data line DL4 in a time-sharing manner. The first color data voltage provided by the second first supply terminal P21 is controlled to be written into the seventh column data line DL7 and the eighth column data line DL8 in a time-sharing manner. The first color data voltage provided by the third first supply terminal P31 is controlled to be written into the eleventh column data line DL11 and the twelfth column data line DL12 in a time-sharing manner. The first color data voltage provided by the fourth first supply terminal P41 is controlled to be written into the fifteenth column data line DL15 and the sixteenth column data line DL16 in a time-sharing manner.

[0141] The second providing circuit 12 is electrically connected to the multiplexing control line S0, the first second providing terminal P12, the second second providing terminal P22, the first column data line DL1, the sixth column data line DL6, the ninth column data line DL9 and the fourteenth column data line DL14, respectively, and is used to, under the control of the reset control signal, write the red data voltage provided by the first second providing terminal P12 into the first column data line DL1 and the sixth column data line DL6 in a time-sharing manner, and write the red data voltage provided by the second second providing terminal P22 into the ninth column data line DL9 and the fourteenth column data line DL14 in a time-sharing manner;

[0142] The third providing circuit 13 is electrically connected to the multiplexing providing terminal S0, the first third providing terminal P13, the second third providing terminal P23, the second column data line DL2, the fifth column data line DL5, the tenth column data line DL10 and the thirteenth column data line DL13, respectively, and is used to, under the control of the reset control signal, time-share write the blue data voltage provided by the first third providing terminal P13 into the second column data line DL2 and the fifth column data line DL5, and time-share write the blue data voltage provided by the second third providing terminal P23 into the tenth column data line DL10 and the thirteenth column data line DL13.

[0143] As shown in FIG2 , the first column data line DL1 is electrically connected to the red sub-pixels located in the first column, the second column data line DL2 is electrically connected to the blue sub-pixels located in the first column, the third column data line DL3 is electrically connected to a portion of the green sub-pixels located in the second column, the fourth column data line DL4 is electrically connected to another portion of the sub-pixels located in the second column, the fifth column data line DL5 is electrically connected to the blue sub-pixels located in the third column, the sixth column data line DL6 is electrically connected to the red sub-pixels located in the third column, the seventh column data line DL7 is electrically connected to a portion of the green sub-pixels located in the fourth column, and the eighth column data line DL8 is electrically connected to another portion of the green sub-pixels located in the fourth column;

[0144] The ninth column data line DL9 is electrically connected to the red sub-pixel located in the fifth column, the tenth column data line DL10 is electrically connected to the blue sub-pixel located in the fifth column, the eleventh column data line DL11 is electrically connected to part of the green sub-pixel located in the sixth column, the twelfth column data line DL12 is electrically connected to another part of the sub-pixel located in the sixth column, the thirteenth column data line DL13 is electrically connected to the blue sub-pixel located in the seventh column, the fourteenth column data line DL14 is electrically connected to the red sub-pixel located in the seventh column, the fifteenth column data line DL15 is electrically connected to part of the green sub-pixel located in the eighth column, and the sixteenth column data line DL16 is electrically connected to another part of the green sub-pixel located in the eighth column.

[0145] In at least one embodiment shown in FIG. 2 , the red subpixel labeled R11 is the first row and first column, the blue subpixel labeled B21 is the first row and first column, the red subpixel labeled R31 is the first row and first column, the blue subpixel labeled B41 is the first row and first column, the red subpixel labeled R51 is the first row and first column, and the blue subpixel labeled B61 is the first row and first column.

[0146] The green sub-pixel labeled G12 is the second column in the first row, the green sub-pixel labeled G22 is the second column in the first row, the green sub-pixel labeled G32 is the second column in the third row, the green sub-pixel labeled G42 is the second column in the fourth row, the green sub-pixel labeled G52 is the second column in the fifth row, and the green sub-pixel labeled G62 is the second column in the sixth row.

[0147] The blue sub-pixel labeled B13 is in the third column of the first row; the red sub-pixel labeled R23 is in the third column of the second row; the blue sub-pixel labeled B33 is in the third column of the third row; the red sub-pixel labeled R43 is in the third column of the fourth row; the blue sub-pixel labeled B53 is in the third column of the fifth row; and the red sub-pixel labeled R63 is in the third column of the sixth row.

[0148] The green sub-pixel labeled G14 is the fourth column in the first row, the green sub-pixel labeled G24 is the fourth column in the first row, the green sub-pixel labeled G34 is the fourth column in the third row, the green sub-pixel labeled G44 is the fourth column in the fourth row, the green sub-pixel labeled G54 is the fourth column in the fifth row, and the green sub-pixel labeled G64 is the fourth column in the sixth row.

[0149] The red subpixel labeled R15 is the fifth column in the first row, the blue subpixel labeled B25 is the fifth column in the second row, the red subpixel labeled R35 is the fifth column in the third row, the blue subpixel labeled B45 is the fifth column in the fourth row, the red subpixel labeled R55 is the fifth column in the fifth row, and the blue subpixel labeled B65 is the fifth column in the sixth row.

[0150] The green sub-pixel labeled G16 is the sixth column in the first row; the green sub-pixel labeled G26 is the sixth column in the first row; the green sub-pixel labeled G36 is the sixth column in the third row; the green sub-pixel labeled G46 is the sixth column in the fourth row; the green sub-pixel labeled G56 is the sixth column in the fifth row; and the green sub-pixel labeled G66 is the sixth column in the sixth row.

[0151] The blue subpixel labeled B17 is in the seventh column of the first row; the red subpixel labeled R27 is in the seventh column of the second row; the blue subpixel labeled B37 is in the seventh column of the third row; the red subpixel labeled R47 is in the seventh column of the fourth row; the blue subpixel labeled B57 is in the seventh column of the fifth row; and the red subpixel labeled R67 is in the seventh column of the sixth row.

[0152] The green sub-pixel labeled G18 is the eighth column in the first row, the green sub-pixel labeled G28 is the eighth column in the first row, the green sub-pixel labeled G38 is the eighth column in the third row, the green sub-pixel labeled G48 is the eighth column in the fourth row, the green sub-pixel labeled G58 is the eighth column in the fifth row, and the green sub-pixel labeled G68 is the eighth column in the sixth row.

[0153] In FIG1 , the first row of gate lines is labeled GL1, the second row of gate lines is labeled GL2, the third row of gate lines is labeled GL3, the fourth row of gate lines is labeled GL4, the fifth row of gate lines is labeled GL5, and the sixth row of gate lines is labeled GL6.

[0154] In at least one embodiment shown in FIG. 1 , R11 is electrically connected to GL1 and DL1 , R31 is electrically connected to GL3 and DL1 , and R51 is electrically connected to GL5 and DL1 .

[0155] B21 is electrically connected to GL2 and DL2 respectively, B41 is electrically connected to GL4 and DL2 respectively, and B61 is electrically connected to GL6 and DL2 respectively;

[0156] G12 is electrically connected to GL1 and DL3, G22 is electrically connected to GL2 and DL4, G32 is electrically connected to GL3 and DL3, G42 is electrically connected to GL4 and DL4, G52 is electrically connected to GL5 and DL3, and G62 is electrically connected to GL6 and DL4;

[0157] B13 is electrically connected to GL1 and DL5, respectively, R23 is electrically connected to GL2 and DL6, respectively, B33 is electrically connected to GL3 and DL5, respectively, R43 is electrically connected to GL4 and DL6, respectively, B53 is electrically connected to GL5 and DL5, respectively, and R63 is electrically connected to GL6 and DL6, respectively;

[0158] G14 is electrically connected to GL1 and DL7, respectively, G24 is electrically connected to GL2 and DL8, respectively, G34 is electrically connected to GL3 and DL7, respectively, G44 is electrically connected to GL4 and DL8, respectively, G54 is electrically connected to GL5 and DL7, respectively, and G64 is electrically connected to GL6 and DL8;

[0159] R15 is electrically connected to GL1 and DL9, R35 is electrically connected to GL3 and DL9, and R55 is electrically connected to GL5 and DL9;

[0160] B25 is electrically connected to GL2 and DL10, B45 is electrically connected to GL4 and DL10, and B65 is electrically connected to GL6 and DL10;

[0161] G16 is electrically connected to GL1 and DL11, G26 is electrically connected to GL2 and DL12, G36 is electrically connected to GL3 and DL11, G46 is electrically connected to GL4 and DL12, G56 is electrically connected to GL5 and DL11, and G66 is electrically connected to GL6 and DL12;

[0162] B17 is electrically connected to GL1 and DL13, R27 is electrically connected to GL2 and DL14, B37 is electrically connected to GL3 and DL13, R47 is electrically connected to GL4 and DL14, B57 is electrically connected to GL5 and DL13, and R67 is electrically connected to GL6 and DL14;

[0163] G18 is electrically connected to GL1 and DL15 respectively, G28 is electrically connected to GL2 and DL16 respectively, G38 is electrically connected to GL3 and DL15 respectively, G48 is electrically connected to GL4 and DL16 respectively, G58 is electrically connected to GL5 and DL15 respectively, and G68 is electrically connected to GL6 and DL16 respectively.

[0164] In at least one embodiment shown in FIG. 2 , the data voltage supply circuit includes a first supply circuit 11, a second supply circuit 12, and a third supply circuit 13; the plurality of data voltage supply terminals include a first first supply terminal P11, a second first supply terminal P21, a third first supply terminal P31, a fourth first supply terminal P41, a first second supply terminal P12, a second second supply terminal P22, a first third supply terminal P13, and a second third supply terminal P23;

[0165] Each first supply terminal is used to provide a green data voltage, each second supply terminal is used to provide a red data voltage, and each third supply terminal is used to provide a blue data voltage;

[0166] The first providing circuit 11 is electrically connected to the multiplexing control line S0, the first first providing terminal P11, the second first providing terminal P21, the third first providing terminal P31, the fourth first providing terminal P41, the third column data line DL3, the fourth column data line DL4, the seventh column data line DL7, the eighth column data line DL8, the eleventh column data line DL11, the twelfth column data line DL12, the fifteenth column data line DL15 and the sixteenth column data line DL16, respectively, and is used to control the multiplexing control signal provided by the multiplexing control line S0 to control the multiplexing control signal provided by the multiplexing control line S0. The green data voltage provided by the first first supply terminal P11 is written into the third column data line DL3 and the eighth column data line DL8 in a time-sharing manner. The green data voltage provided by the second first supply terminal P21 is controlled to be written into the fourth column data line DL4 and the seventh column data line DL7 in a time-sharing manner. The green data voltage provided by the third first supply terminal P31 is controlled to be written into the eleventh column data line DL11 and the sixteenth column data line DL16 in a time-sharing manner. The green data voltage provided by the fourth first supply terminal P41 is controlled to be written into the twelfth column data line DL12 and the fifteenth column data line DL15 in a time-sharing manner.

[0167] The second providing circuit 12 is electrically connected to the multiplexing control line S0, the first second providing terminal P12, the second second providing terminal P22, the first column data line DL1, the sixth column data line DL6, the ninth column data line DL9 and the fourteenth column data line DL14, respectively, and is used to, under the control of the reset control signal, write the red data voltage provided by the first second providing terminal P12 into the first column data line DL1 and the sixth column data line DL6 in a time-sharing manner, and write the red data voltage provided by the second second providing terminal P22 into the ninth column data line DL9 and the fourteenth column data line DL14 in a time-sharing manner;

[0168] The third providing circuit 13 is electrically connected to the multiplexing providing terminal S0, the first third providing terminal P13, the second third providing terminal P23, the second column data line DL2, the fifth column data line DL5, the tenth column data line DL10 and the thirteenth column data line DL13, respectively, and is used to, under the control of the reset control signal, time-share write the blue data voltage provided by the first third providing terminal P13 into the second column data line DL2 and the fifth column data line DL5, and time-share write the blue data voltage provided by the second third providing terminal P23 into the tenth column data line DL10 and the thirteenth column data line DL13.

[0169] Optionally, the multiplexed control line includes a first control line and a second control line;

[0170] The first providing circuit includes a plurality of first providing sub-circuits;

[0171] The ath first providing sub-circuit is electrically connected to the first control line, the second control line, the ath first providing terminal, the 4a-1 column data line, and the 4a column data line, respectively, and is configured to write the first color data voltage provided by the ath first providing terminal into the 4a-1 column data line under the control of a first control signal provided by the first control line, and to write the first color data voltage provided by the ath first providing terminal into the 4a column data line under the control of a second control signal provided by the second control line;

[0172] a is a positive integer greater than or equal to 1.

[0173] On the basis of at least one embodiment shown in FIG1 , as shown in FIG3 , the multiplexing control line may include a first control line SW1 and a second control line SW2 ;

[0174] The first providing circuit includes a first first providing sub-circuit 211 , a second first providing sub-circuit 221 , a third first providing sub-circuit 231 and a fourth first providing sub-circuit 241 ;

[0175] The first first providing sub-circuit 211 is electrically connected to the first control line SW1, the second control line SW2, the first first providing terminal P11, the third column data line DL3, and the fourth column data line DL4, respectively, and is configured to write the green data voltage provided by the first first providing terminal P11 into DL3 under the control of a first control signal provided by the first control line SW1, and to write the green data voltage provided by the first first providing terminal P11 into DL4 under the control of a second control signal provided by the second control line SW2;

[0176] The second first providing sub-circuit 221 is electrically connected to the first control line SW1, the second control line SW2, the second first providing terminal P21, the seventh column data line DL7, and the eighth column data line DL8, respectively, and is configured to write the green data voltage provided by the second first providing terminal P21 into DL7 under the control of the first control signal provided by the first control line SW1, and to write the green data voltage provided by the second first providing terminal P21 into DL8 under the control of the second control signal provided by the second control line SW2;

[0177] The third first providing sub-circuit 231 is electrically connected to the first control line SW1, the second control line SW2, the third first providing terminal P31, the eleventh column data line DL11, and the twelfth column data line DL12, respectively, and is configured to write the green data voltage provided by the third first providing terminal P31 into DL11 under the control of the first control signal provided by the first control line SW1, and to write the green data voltage provided by the third first providing terminal P31 into DL12 under the control of the second control signal provided by the second control line SW2;

[0178] The fourth first providing sub-circuit 241 is electrically connected to the first control line SW1, the second control line SW2, the fourth first providing terminal P41, the fifteenth column data line DL15 and the sixteenth column data line DL16, respectively, and is used to write the green data voltage provided by the fourth first providing terminal P41 into DL15 under the control of the first control signal provided by the first control line SW1, and to write the green data voltage provided by the fourth first providing terminal P41 into DL16 under the control of the second control signal provided by the second control line SW2.

[0179] Optionally, the ath first providing sub-circuit includes an ath first transistor and an ath second transistor;

[0180] The gate of the a-th first transistor is electrically connected to the first control line, the first electrode of the a-th first transistor is electrically connected to the a-th first supply terminal, and the second electrode of the a-th first transistor is electrically connected to the 4a-1 column data line;

[0181] The gate of the ath second transistor is electrically connected to the second control line, the first electrode of the ath second transistor is electrically connected to the ath first supply terminal, and the second electrode of the ath second transistor is electrically connected to the 4a column data line.

[0182] In at least one embodiment of the present disclosure, the multiplexed control line includes a first control line and a second control line;

[0183] The first providing circuit includes a plurality of first providing sub-circuits;

[0184] The 2a-1th first providing sub-circuit is electrically connected to the first control line, the second control line, the 2a-1th first providing terminal, the 8a-5th column data line, and the 8a column data line, respectively, and is configured to write the first color data voltage provided by the 2a-1th first providing terminal into the 8a-5th column data line under the control of a first control signal provided by the first control line, and to write the first color data voltage provided by the 2a-1th first providing terminal into the 8a column data line under the control of a second control signal provided by the second control line;

[0185] The 2a first providing sub-circuit is electrically connected to the first control line, the second control line, the 2a first providing terminal, the 8a-4 column data line, and the 8a-1 column data line, respectively, and is configured to write the first color data voltage provided by the 2a first providing terminal into the 8a-1 column data line under the control of a first control signal provided by the first control line, and to write the first color data voltage provided by the 2a first providing terminal into the 8a-4 column data line under the control of a second control signal provided by the second control line;

[0186] a is a positive integer greater than or equal to 1.

[0187] Optionally, the 2a-1th first providing sub-circuit includes a 2a-1th first transistor and a 2a-1th second transistor;

[0188] The gate of the 2a-1th first transistor is electrically connected to the first control line, the first electrode of the 2a-1th first transistor is electrically connected to the 2a-1th first supply terminal, and the second electrode of the 2a-1th first transistor is electrically connected to the 8a-5th column data line;

[0189] The gate of the 2a-1 second transistor is electrically connected to the second control line, the first electrode of the 2a-1 second transistor is electrically connected to the 2a-1 first supply terminal, and the second electrode of the 2a-1 second transistor is electrically connected to the 8a column data line;

[0190] The 2a-th first providing sub-circuit includes a 2a-th first transistor and a 2a-th second transistor;

[0191] The gate of the 2a-th first transistor is electrically connected to the first control line, the first electrode of the 2a-th first transistor is electrically connected to the 2a-th first supply terminal, and the second electrode of the 2a-th first transistor is electrically connected to the 8a-1-th column data line;

[0192] The gate of the 2a-th second transistor is electrically connected to the second control line, the first electrode of the 2a-th second transistor is electrically connected to the 2a-th first supply terminal, and the second electrode of the 2a-th second transistor is electrically connected to the 8a-4 column data line.

[0193] As shown in FIG4 , based on at least one embodiment shown in FIG2 , the multiplexed control line includes a first control line SW1 and a second control line SW2 ;

[0194] The first providing circuit includes a first first providing sub-circuit 211, a second first providing sub-circuit 221, a third first providing sub-circuit 231 and a fourth first providing sub-circuit 241;

[0195] The first first providing sub-circuit 211 is electrically connected to the first control line SW1, the second control line SW2, the first first providing terminal P11, the third column data line DL3, and the eighth column data line DL8, respectively, and is configured to write the green data voltage provided by the first first providing terminal P11 into the third column data line DL3 under the control of a first control signal provided by the first control line SW1, and to write the green data voltage provided by the first first providing terminal P11 into the eighth column data line DL8 under the control of a second control signal provided by the second control line SW2;

[0196] The second first providing sub-circuit 221 is electrically connected to the first control line SW1, the second control line SW2, the second first providing terminal P21, the fourth column data line DL4, and the seventh column data line DL7, respectively, and is configured to write the green data voltage provided by the second first providing terminal P21 into the seventh column data line DL7 under the control of the first control signal provided by the first control line SW1, and to write the green data voltage provided by the second first providing terminal P21 into the fourth column data line DL4 under the control of the second control signal provided by the second control line SW2;

[0197] The third first providing sub-circuit 231 is electrically connected to the first control line SW1, the second control line SW2, the third first providing terminal P31, the eleventh column data line DL11, and the sixteenth column data line DL16, respectively, and is configured to write the green data voltage provided by the third first providing terminal P31 into the eleventh column data line DL11 under the control of the first control signal provided by the first control line SW1, and to write the green data voltage provided by the third first providing terminal P31 into the sixteenth column data line DL16 under the control of the second control signal provided by the second control line SW2;

[0198] The fourth first providing sub-circuit 241 is electrically connected to the first control line SW1, the second control line SW2, the fourth first providing terminal P41, the twelfth column data line DL12 and the fifteenth column data line DL15, respectively, and is used to write the green data voltage provided by the fourth first providing terminal P41 into the fifteenth column data line DL15 under the control of the first control signal provided by the first control line SW1, and to write the green data voltage provided by the fourth first providing terminal P41 into the twelfth column data line DL12 under the control of the second control signal provided by the second control line SW2.

[0199] In at least one embodiment of the present disclosure, the multiplexed control line includes a first control line and a second control line;

[0200] The second providing circuit includes a plurality of second providing sub-circuits;

[0201] The ath second providing sub-circuit is electrically connected to the first control line, the second control line, the ath second providing terminal, the 8a-7th column data line, and the 8a-2nd column data line, respectively, and is configured to write the second color data voltage provided by the ath second providing terminal into the 8a-7th column data line under the control of a first control signal provided by the first control line, and to write the second color data voltage provided by the ath second providing terminal into the 8a-2nd column data line under the control of a second control signal provided by the second control line;

[0202] a is a positive integer greater than or equal to 1.

[0203] In at least one embodiment shown in FIG3 , the second providing circuit includes a first second providing subcircuit 212 and a second second providing subcircuit 222 ;

[0204] The first second providing sub-circuit 212 is electrically connected to the first control line SW1, the second control line SW2, the first second providing terminal P12, the first column data line DL1, and the sixth column data line DL6, respectively, and is configured to provide the red data voltage provided by the first second providing terminal P12 to the first column data line DL1 under the control of a first control signal provided by the first control line SW1, and to provide the red data voltage provided by the first second providing terminal P12 to the sixth column data line DL6 under the control of a second control signal provided by the second control line SW2;

[0205] The second second providing sub-circuit 222 is electrically connected to the first control line SW1, the second control line SW2, the second second providing terminal P22, the ninth column data line DL9 and the fourteenth column data line DL14, respectively, and is used to provide the red data voltage provided by the second second providing terminal P22 to the ninth column data line DL9 under the control of the first control signal provided by the first control line SW1, and to provide the red data voltage provided by the second second providing terminal P12 to the fourteenth column data line DL14 under the control of the second control signal provided by the second control line SW2.

[0206] In at least one embodiment shown in FIG4 , the second providing circuit includes a first second providing sub-circuit 212 and a second second providing sub-circuit 222 ;

[0207] The first second providing sub-circuit 212 is electrically connected to the first control line SW1, the second control line SW2, the first second providing terminal P12, the first column data line DL1, and the sixth column data line DL6, respectively, and is configured to provide the red data voltage provided by the first second providing terminal P12 to the first column data line DL1 under the control of a first control signal provided by the first control line SW1, and to provide the red data voltage provided by the first second providing terminal P12 to the sixth column data line DL6 under the control of a second control signal provided by the second control line SW2;

[0208] The second second providing sub-circuit 222 is electrically connected to the first control line SW1, the second control line SW2, the second second providing terminal P22, the ninth column data line DL9 and the fourteenth column data line DL14, respectively, and is used to provide the red data voltage provided by the second second providing terminal P22 to the ninth column data line DL9 under the control of the first control signal provided by the first control line SW1, and to provide the red data voltage provided by the second second providing terminal P12 to the fourteenth column data line DL14 under the control of the second control signal provided by the second control line SW2.

[0209] Optionally, the ath second providing sub-circuit includes an ath third transistor and an ath fourth transistor;

[0210] The gate of the ath third transistor is electrically connected to the first control line, the first electrode of the ath third transistor is electrically connected to the ath second supply terminal, and the second electrode of the ath third transistor is electrically connected to the 8a-7 column data line;

[0211] The gate of the ath fourth transistor is electrically connected to the second control line, the first electrode of the ath fourth transistor is electrically connected to the ath second supply terminal, and the second electrode of the ath fourth transistor is electrically connected to the 8a-2 column data line.

[0212] In at least one embodiment of the present disclosure, the multiplexed control line includes a first control line and a second control line;

[0213] The third providing circuit includes a plurality of third providing sub-circuits;

[0214] an ath third providing sub-circuit electrically connected to the first control line, the second control line, the ath third providing terminal, the 8a-6th column data line, and the 8a-3rd column data line, respectively, and configured to write the third color data voltage provided by the ath third providing terminal into the 8a-3th column data line under the control of a first control signal provided by the first control line, and to write the third color data voltage provided by the ath third providing terminal into the 8a-6th column data line under the control of a second control signal provided by the second control line;

[0215] a is a positive integer greater than or equal to 1.

[0216] In at least one embodiment shown in FIG3 , the third providing circuit includes a first third providing sub-circuit 213 and a second third providing sub-circuit 223 ;

[0217] The first third providing sub-circuit 213 is electrically connected to the first control line SW1, the second control line SW2, the first third providing terminal P13, the second column data line DL2, and the fifth column data line DL5, respectively, and is configured to write the blue data voltage provided by the first third providing terminal P13 into the fifth column data line DL5 under the control of a first control signal provided by the first control line SW1, and write the blue data voltage provided by the first third providing terminal P13 into the second column data line DL2 under the control of a second control signal provided by the second control line SW2;

[0218] The second third providing sub-circuit 223 is electrically connected to the first control line SW1, the second control line SW2, the second third providing terminal P23, the tenth column data line DL10 and the thirteenth column data line DL13, respectively, and is used to write the blue data voltage provided by the second third providing terminal P23 into the thirteenth column data line DL13 under the control of the first control signal provided by the first control line SW1, and to write the blue data voltage provided by the second third providing terminal P23 into the tenth column data line DL10 under the control of the second control signal provided by the second control line SW2.

[0219] In at least one embodiment shown in FIG4 , the third providing circuit includes a first third providing sub-circuit 213 and a second third providing sub-circuit 223 ;

[0220] The first third providing sub-circuit 213 is electrically connected to the first control line SW1, the second control line SW2, the first third providing terminal P13, the second column data line DL2, and the fifth column data line DL5, respectively, and is configured to write the blue data voltage provided by the first third providing terminal P13 into the fifth column data line DL5 under the control of a first control signal provided by the first control line SW1, and write the blue data voltage provided by the first third providing terminal P13 into the second column data line DL2 under the control of a second control signal provided by the second control line SW2;

[0221] The second third providing sub-circuit 223 is electrically connected to the first control line SW1, the second control line SW2, the second third providing terminal P23, the tenth column data line DL10 and the thirteenth column data line DL13, respectively, and is used to write the blue data voltage provided by the second third providing terminal P23 into the thirteenth column data line DL13 under the control of the first control signal provided by the first control line SW1, and to write the blue data voltage provided by the second third providing terminal P23 into the tenth column data line DL10 under the control of the second control signal provided by the second control line SW2.

[0222] Optionally, the ath third providing sub-circuit includes an ath fifth transistor and an ath sixth transistor;

[0223] The gate of the ath fifth transistor is electrically connected to the first control line, the first electrode of the ath fifth transistor is electrically connected to the ath third supply terminal, and the second electrode of the ath fifth transistor is electrically connected to the 8a-3 column data line;

[0224] The gate of the ath sixth transistor is electrically connected to the second control line, the first electrode of the ath sixth transistor is electrically connected to the ath third supply terminal, and the second electrode of the ath sixth transistor is electrically connected to the 8a-6 column data line.

[0225] In at least one embodiment of the present disclosure, the sub-pixels are disposed in an effective display area of ​​the display panel, and the data voltage providing circuit is disposed in a peripheral area of ​​the display panel.

[0226] In a specific implementation, the sub-pixels are arranged in the effective display area, and the data voltage providing circuit is arranged in the peripheral area, for example, at the lower side of the effective display area, but not limited thereto.

[0227] As shown in FIG5 , based on at least one embodiment shown in FIG3 ,

[0228] The first first providing sub-circuit includes a first first transistor T11 and a first second transistor T12;

[0229] The gate of the first first transistor T11 is electrically connected to the first control line SW1, the source of the first first transistor T11 is electrically connected to the first first supply terminal P11, and the drain of the first first transistor T11 is electrically connected to the third column data line DL3;

[0230] The gate of the first second transistor T12 is electrically connected to the second control line SW2, the source of the first second transistor T12 is electrically connected to the first first supply terminal P11, and the drain of the first second transistor T12 is electrically connected to the fourth column data line DL4;

[0231] The second first providing sub-circuit includes a second first transistor T21 and a second second transistor T22;

[0232] The gate of the second first transistor T21 is electrically connected to the first control line SW1, the source of the second first transistor T21 is electrically connected to the second first supply terminal P21, and the drain of the second first transistor T21 is electrically connected to the seventh column data line DL7;

[0233] The gate of the second second transistor T22 is electrically connected to the second control line SW2, the source of the second second transistor T22 is electrically connected to the second first supply terminal P21, and the drain of the second second transistor T22 is electrically connected to the eighth column data line DL8;

[0234] The third first providing sub-circuit includes a third first transistor T31 and a third second transistor T32;

[0235] The gate of the third first transistor T31 is electrically connected to the first control line SW1, the source of the third first transistor T31 is electrically connected to the third first supply terminal P31, and the drain of the third first transistor T31 is electrically connected to the eleventh column data line DL11;

[0236] The gate of the third second transistor T32 is electrically connected to the second control line SW2, the source of the third second transistor T32 is electrically connected to the third first supply terminal P31, and the drain of the third second transistor T32 is electrically connected to the twelfth column data line DL12;

[0237] The gate of the fourth first transistor T41 is electrically connected to the first control line SW1, the source of the fourth first transistor T41 is electrically connected to the fourth first supply terminal P41, and the drain of the fourth first transistor T41 is electrically connected to the fifteenth column data line DL15;

[0238] The gate of the fourth second transistor T42 is electrically connected to the second control line SW2, the source of the fourth second transistor T42 is electrically connected to the fourth first supply terminal P41, and the drain of the fourth second transistor T42 is electrically connected to the sixteenth column data line DL16;

[0239] The first second providing sub-circuit includes a first third transistor T13 and a first fourth transistor T14;

[0240] The gate of the first third transistor T13 is electrically connected to the first control line SW1, the source of the first third transistor T13 is electrically connected to the first second supply terminal P12, and the drain of the first third transistor T13 is electrically connected to the first column data line DL1;

[0241] The gate of the first fourth transistor T14 is electrically connected to the second control line SW2, the source of the first fourth transistor T14 is electrically connected to the first second supply terminal P12, and the drain of the first fourth transistor T14 is electrically connected to the sixth column data line DL6;

[0242] The second second providing sub-circuit includes a second third transistor T23 and a second fourth transistor T24;

[0243] The gate of the second third transistor T23 is electrically connected to the first control line SW1, the source of the second third transistor T23 is electrically connected to the second second supply terminal P22, and the drain of the second third transistor T13 is electrically connected to the ninth column data line DL9;

[0244] The gate of the second fourth transistor T24 is electrically connected to the second control line SW2, the source of the second fourth transistor T24 is electrically connected to the second second supply terminal P22, and the drain of the second fourth transistor T24 is electrically connected to the fourteenth column data line DL14;

[0245] The first third providing sub-circuit includes a first fifth transistor T15 and a first sixth transistor T16;

[0246] The gate of the first fifth transistor T15 is electrically connected to the first control line SW1, the source of the first fifth transistor T15 is electrically connected to the first third supply terminal P13, and the drain of the first fifth transistor T15 is electrically connected to the second column data line DL2;

[0247] The gate of the first sixth transistor T16 is electrically connected to the second control line SW2, the source of the first sixth transistor T16 is electrically connected to the first third supply terminal P13, and the drain of the first sixth transistor T16 is electrically connected to the fifth column data line DL5;

[0248] The second third providing sub-circuit includes a second fifth transistor T25 and a second sixth transistor T26;

[0249] The gate of the second fifth transistor T25 is electrically connected to the first control line SW1, the source of the second fifth transistor T25 is electrically connected to the second third supply terminal P23, and the drain of the second fifth transistor T25 is electrically connected to the tenth column data line DL10;

[0250] The gate of the second sixth transistor T26 is electrically connected to the second control line SW2, the source of the second sixth transistor T26 is electrically connected to the second third supply terminal P23, and the drain of the second sixth transistor T26 is electrically connected to the thirteenth column data line DL13;

[0251] As shown in FIG6 , based on at least one embodiment shown in FIG4 ,

[0252] The first first providing sub-circuit includes a first first transistor T11 and a first second transistor T12;

[0253] The gate of the first first transistor T11 is electrically connected to the first control line SW1, the source of the first first transistor T11 is electrically connected to the first first supply terminal P11, and the drain of the first first transistor T11 is electrically connected to the third column data line DL3;

[0254] The gate of the first second transistor T12 is electrically connected to the second control line SW2, the source of the first second transistor T12 is electrically connected to the first first supply terminal P11, and the drain of the first second transistor T12 is electrically connected to the eighth column data line DL8;

[0255] The second first providing sub-circuit includes a second first transistor T21 and a second second transistor T22;

[0256] The gate of the second first transistor T21 is electrically connected to the first control line SW1, the source of the second first transistor T21 is electrically connected to the second first supply terminal P21, and the drain of the second first transistor T21 is electrically connected to the fourth column data line DL4;

[0257] The gate of the second second transistor T22 is electrically connected to the second control line SW2, the source of the second second transistor T22 is electrically connected to the second first supply terminal P21, and the drain of the second second transistor T22 is electrically connected to the seventh column data line DL7;

[0258] The third first providing sub-circuit includes a third first transistor T31 and a third second transistor T32;

[0259] The gate of the third first transistor T31 is electrically connected to the first control line SW1, the source of the third first transistor T31 is electrically connected to the third first supply terminal P31, and the drain of the third first transistor T31 is electrically connected to the eleventh column data line DL11;

[0260] The gate of the third second transistor T32 is electrically connected to the second control line SW2, the source of the third second transistor T32 is electrically connected to the third first supply terminal P31, and the drain of the third second transistor T32 is electrically connected to the sixteenth column data line DL16;

[0261] The gate of the fourth first transistor T41 is electrically connected to the second control line SW2, the source of the fourth first transistor T41 is electrically connected to the fourth first supply terminal P41, and the drain of the fourth first transistor T41 is electrically connected to the twelfth column data line DL12;

[0262] The gate of the fourth second transistor T42 is electrically connected to the first control line SW1, the source of the fourth second transistor T42 is electrically connected to the fourth first supply terminal P41, and the drain of the fourth second transistor T42 is electrically connected to the fifteenth column data line DL15;

[0263] The first second providing sub-circuit includes a first third transistor T13 and a first fourth transistor T14;

[0264] The gate of the first third transistor T13 is electrically connected to the first control line SW1, the source of the first third transistor T13 is electrically connected to the first second supply terminal P12, and the drain of the first third transistor T13 is electrically connected to the first column data line DL1;

[0265] The gate of the first fourth transistor T14 is electrically connected to the second control line SW2, the source of the first fourth transistor T14 is electrically connected to the first second supply terminal P12, and the drain of the first fourth transistor T14 is electrically connected to the sixth column data line DL6;

[0266] The second second providing sub-circuit includes a second third transistor T23 and a second fourth transistor T24;

[0267] The gate of the second third transistor T23 is electrically connected to the first control line SW1, the source of the second third transistor T23 is electrically connected to the second second supply terminal P22, and the drain of the second third transistor T13 is electrically connected to the ninth column data line DL9;

[0268] The gate of the second fourth transistor T24 is electrically connected to the second control line SW2, the source of the second fourth transistor T24 is electrically connected to the second second supply terminal P22, and the drain of the second fourth transistor T24 is electrically connected to the fourteenth column data line DL14;

[0269] The first third providing sub-circuit includes a first fifth transistor T15 and a first sixth transistor T16;

[0270] The gate of the first fifth transistor T15 is electrically connected to the first control line SW1, the source of the first fifth transistor T15 is electrically connected to the first third supply terminal P13, and the drain of the first fifth transistor T15 is electrically connected to the second column data line DL2;

[0271] The gate of the first sixth transistor T16 is electrically connected to the second control line SW2, the source of the first sixth transistor T16 is electrically connected to the first third supply terminal P13, and the drain of the first sixth transistor T16 is electrically connected to the fifth column data line DL5;

[0272] The second third providing sub-circuit includes a second fifth transistor T25 and a second sixth transistor T26;

[0273] The gate of the second fifth transistor T25 is electrically connected to the first control line SW1, the source of the second fifth transistor T25 is electrically connected to the second third supply terminal P23, and the drain of the second fifth transistor T25 is electrically connected to the tenth column data line DL10;

[0274] The gate of the second sixth transistor T26 is electrically connected to the second control line SW2, the source of the second sixth transistor T26 is electrically connected to the second third supply terminal P23, and the drain of the second sixth transistor T26 is electrically connected to the thirteenth column data line DL13;

[0275] As shown in FIG7A , the first second supply terminal is labeled P12, the first first supply terminal is labeled P11, the first third supply terminal is labeled P13, the second first supply terminal is labeled P21, the second second supply terminal is labeled P22, the third first supply terminal is labeled P31, the third third supply terminal is labeled P23, and the fourth first supply terminal is labeled P41;

[0276] P12, P11, P13, P21, P22, P31, P23 and P41 are all formed in the second gate metal layer;

[0277] The data line labeled DL1 is the first column, the data line labeled DL2 is the second column, the data line labeled DL3 is the third column, and the data line labeled DL4 is the fourth column.

[0278] The fifth data line is labeled DL5, the sixth data line is labeled DL6, the seventh data line is labeled DL7, and the eighth data line is labeled DL8.

[0279] The data line labeled DL9 is the ninth column, the data line labeled DL10 is the tenth column, the data line labeled DL11 is the eleventh column, and the data line labeled DL12 is the twelfth column.

[0280] The data line labeled DL13 is the thirteenth column, the data line labeled DL14 is the fourteenth column, the data line labeled DL15 is the fifteenth column, and the data line labeled DL16 is the sixteenth column;

[0281] P12 and P22 are used to provide red data voltage, P11, P21, P31 and P41 are used to provide green data voltage, and P13 and P23 are used to provide blue data voltage;

[0282] DL1, DL6, DL9 and DL14 are used to provide red data voltage;

[0283] DL2, DL5, DL10, and DL13 are used to provide blue data voltages;

[0284] DL3, DL4, DL7, DL8, DL11, DL12, DL15, and DL16 are used to provide green data voltages;

[0285] DL1, DL3, DL4, DL5, DL7, DL8, DL9, DL11, DL12, DL13, DL15, and DL16 are formed in a second gate metal layer;

[0286] DL2, DL6, DL10 and DL14 are formed in the first gate metal layer;

[0287] The first control line is labeled SW1, and the second control line is labeled SW2;

[0288] SW1 and SW2 are formed in the source and drain metal layers;

[0289] In FIG7A , T1 is a first transistor, T2 is a second transistor, T3 is a third transistor, T4 is a fourth transistor, T5 is a fifth transistor, T6 is a sixth transistor, T7 is a seventh transistor, T8 is an eighth transistor, T9 is a ninth transistor, T10 is a tenth transistor, T11 is an eleventh transistor, T12 is a twelfth transistor, T13 is a thirteenth transistor, T14 is a fourteenth transistor, T15 is a fifteenth transistor, and T16 is a sixteenth transistor.

[0290] The gate of T1 is electrically connected to SW2, and the gate of T2 is electrically connected to SW1;

[0291] The source of T1 is electrically connected to P12, and the drain of T1 is electrically connected to DL6;

[0292] The source of T2 is electrically connected to P12, and the drain of T2 is electrically connected to DL1;

[0293] The gate of T3 is electrically connected to SW1, and the gate of T4 is electrically connected to SW2;

[0294] The source of T3 is electrically connected to P11, and the drain of T3 is electrically connected to DL3;

[0295] The source of T4 is electrically connected to P11, and the drain of T4 is electrically connected to DL4;

[0296] The gate of T5 is electrically connected to SW2, and the gate of T6 is electrically connected to SW1;

[0297] The source of T5 is electrically connected to P13, and the drain of T5 is electrically connected to DL2;

[0298] The source of T6 is electrically connected to P13, and the drain of T6 is electrically connected to DL5;

[0299] The gate of T7 is electrically connected to SW1, and the gate of T8 is electrically connected to SW2;

[0300] The source of T7 is electrically connected to P21, and the drain of T7 is electrically connected to DL7;

[0301] The source of T8 is electrically connected to P21, and the drain of T8 is electrically connected to DL8;

[0302] The gate of T9 is electrically connected to SW2, and the gate of T10 is electrically connected to SW1;

[0303] The source of T9 is electrically connected to P22, and the drain of T9 is electrically connected to DL14;

[0304] The source of T10 is electrically connected to P22, and the drain of T10 is electrically connected to DL9;

[0305] The gate of T11 is electrically connected to SW1, and the drain of T12 is electrically connected to SW2;

[0306] The source of T11 is electrically connected to P31, and the drain of T11 is electrically connected to DL11;

[0307] The gate of T12 is electrically connected to P31, and the drain of T12 is electrically connected to DL12;

[0308] The gate of T13 is electrically connected to SW2, and the gate of T14 is electrically connected to SW1;

[0309] The source of T13 is electrically connected to P23, and the drain of T13 is electrically connected to DL10;

[0310] The source of T14 is electrically connected to P23, and the drain of T14 is electrically connected to DL13;

[0311] The gate of T15 is electrically connected to SW1, and the gate of T16 is electrically connected to SW2;

[0312] The source of T15 is electrically connected to P41, and the drain of T15 is electrically connected to DL15;

[0313] The source of T16 is electrically connected to P51 , and the drain of T16 is electrically connected to DL16 .

[0314] In at least one embodiment shown in FIG. 7A , the gate of each transistor is formed in the first gate metal layer, the source and drain of each transistor are formed in the source-drain metal layer, and the active layer of each transistor is formed in the semiconductor layer.

[0315] 7B is a layout diagram of the semiconductor layer in FIG. 7A , FIG. 7C is a layout diagram of the first gate metal layer in FIG. 7A , FIG. 7D is a layout diagram of the second gate metal layer in FIG. 7A , and FIG. 7E is a layout diagram of the source / drain metal layer in FIG. 7A .

[0316] In FIG7B , A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T5, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0317] In Figure 7C, the gate labeled G1 is T1, the gate labeled G2 is T2, the gate labeled G3 is T3, the gate labeled G4 is T4, the gate labeled G5 is T5, the gate labeled G6 is T6, the gate labeled G7 is T7, the gate labeled G8 is T8, the gate labeled G9 is T9, the gate labeled G10 is T10, the gate labeled G11 is T11, the gate labeled G12 is T12, the gate labeled G13 is T13, the gate labeled G14 is T14, the gate labeled G15 is T15, and the gate labeled G16 is T16.

[0318] As shown in FIG8A , the first second supply terminal is labeled P12, the first first supply terminal is labeled P11, the first third supply terminal is labeled P13, the second first supply terminal is labeled P21, the second second supply terminal is labeled P22, the third first supply terminal is labeled P31, the third third supply terminal is labeled P23, and the fourth first supply terminal is labeled P41;

[0319] P12, P11, P13, P21, P22, P31, P23 and P41 are all formed in the second gate metal layer;

[0320] The data line labeled DL1 is the first column, the data line labeled DL2 is the second column, the data line labeled DL3 is the third column, and the data line labeled DL4 is the fourth column.

[0321] The fifth data line is labeled DL5, the sixth data line is labeled DL6, the seventh data line is labeled DL7, and the eighth data line is labeled DL8.

[0322] The data line labeled DL9 is the ninth column, the data line labeled DL10 is the tenth column, the data line labeled DL11 is the eleventh column, and the data line labeled DL12 is the twelfth column.

[0323] The data line labeled DL13 is the thirteenth column, the data line labeled DL14 is the fourteenth column, the data line labeled DL15 is the fifteenth column, and the data line labeled DL16 is the sixteenth column;

[0324] P12 and P22 are used to provide red data voltage, P11, P21, P31 and P41 are used to provide green data voltage, and P13 and P23 are used to provide blue data voltage;

[0325] DL1 is used to provide a red data voltage, DL2 is used to provide a blue data voltage, DL3 and DL4 are used to provide a green data voltage, DL5 is used to provide a blue data voltage, DL6 is used to provide a red data voltage, DL7 and DL8 are used to provide a green data voltage, DL9 is used to provide a red data voltage, DL10 is used to provide a blue data voltage, DL11 and DL12 are used to provide a green data voltage, DL13 is used to provide a blue data voltage, DL14 is used to provide a red data voltage, and DL15 and DL16 are used to provide a green data voltage;

[0326] DL1, DL3, DL5, DL7, DL9, DL11, DL13, and DL15 are all formed in the second gate metal layer;

[0327] DL2, DL4, DL6, DL8, DL10, DL12, DL14, and DL16 are formed in the first gate metal layer;

[0328] In FIG8A , T1 is a first transistor, T2 is a second transistor, T3 is a third transistor, T4 is a fourth transistor, T5 is a fifth transistor, T6 is a sixth transistor, T7 is a seventh transistor, T8 is an eighth transistor, T9 is a ninth transistor, T10 is a tenth transistor, T11 is an eleventh transistor, T12 is a twelfth transistor, T13 is a thirteenth transistor, T14 is a fourteenth transistor, T15 is a fifteenth transistor, and T16 is a sixteenth transistor;

[0329] The first control line is labeled SW1, and the second control line is labeled SW2; SW1 and SW2 are formed in the source and drain metal layer;

[0330] The gate of T1 is electrically connected to SW2, and the gate of T2 is electrically connected to SW1;

[0331] The source of T1 is electrically connected to P12, and the drain of T1 is electrically connected to DL6;

[0332] The source of T2 is electrically connected to P12, and the drain of T2 is electrically connected to DL1;

[0333] The gate of T3 is electrically connected to SW1, and the gate of T4 is electrically connected to SW2;

[0334] The source of T3 is electrically connected to P11, and the drain of T3 is electrically connected to DL8;

[0335] The source of T4 is electrically connected to P11, and the drain of T4 is electrically connected to DL3;

[0336] The gate of T5 is electrically connected to SW2, and the gate of T6 is electrically connected to SW1;

[0337] The source of T5 is electrically connected to P13, and the drain of T5 is electrically connected to DL2;

[0338] The source of T6 is electrically connected to P13, and the drain of T6 is electrically connected to DL5;

[0339] The gate of T7 is electrically connected to SW1, and the gate of T8 is electrically connected to SW2;

[0340] The source of T7 is electrically connected to P21, and the drain of T7 is electrically connected to DL4;

[0341] The source of T8 is electrically connected to P21, and the drain of T8 is electrically connected to DL7;

[0342] The gate of T9 is electrically connected to SW2, and the gate of T10 is electrically connected to SW1;

[0343] The source of T9 is electrically connected to P22, and the drain of T9 is electrically connected to DL14;

[0344] The source of T10 is electrically connected to P22, and the drain of T10 is electrically connected to DL9;

[0345] The gate of T11 is electrically connected to SW1, and the gate of T12 is electrically connected to SW2;

[0346] The source of T11 is electrically connected to P31, and the drain of T11 is electrically connected to DL16;

[0347] The source of T12 is electrically connected to P31, and the drain of T12 is electrically connected to DL12;

[0348] The gate of T13 is electrically connected to SW2, and the gate of T14 is electrically connected to SW1;

[0349] The source of T13 is electrically connected to P23, and the drain of T13 is electrically connected to DL10;

[0350] The source of T14 is electrically connected to P23, and the drain of T14 is electrically connected to DL13;

[0351] The gate of T15 is electrically connected to SW1, and the gate of T16 is electrically connected to SW2;

[0352] The source of T15 is electrically connected to P41, and the drain of P15 is electrically connected to DL12;

[0353] The source of T16 is electrically connected to P41, and the drain of P16 is electrically connected to DL15;

[0354] The gate of each transistor is formed in the first gate metal layer, the source of each transistor and the drain of each transistor are formed in the source-drain metal layer, and the active layer of each transistor is formed in the semiconductor layer.

[0355] 8B is a layout diagram of the semiconductor layer in FIG. 8A , FIG. 8C is a layout diagram of the first gate metal layer in FIG. 8A , FIG. 8D is a layout diagram of the second gate metal layer in FIG. 8A , and FIG. 8E is a layout diagram of the source / drain metal layer in FIG. 8A .

[0356] In FIG8B , A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T5, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0357] In Figure 8C, the gate labeled G1 is T1, the gate labeled G2 is T2, the gate labeled G3 is T3, the gate labeled G4 is T4, the gate labeled G5 is T5, the gate labeled G6 is T6, the gate labeled G7 is T7, the gate labeled G8 is T8, the gate labeled G9 is T9, the gate labeled G10 is T10, the gate labeled G11 is T11, the gate labeled G12 is T12, the gate labeled G13 is T13, the gate labeled G14 is T14, the gate labeled G15 is T15, and the gate labeled G16 is T16.

[0358] The display panel driving method according to the embodiment of the present disclosure is applied to the above-mentioned display panel, and the display panel driving method includes:

[0359] The data voltage supply circuit provides the data voltage provided by the same data voltage supply terminal to at least two columns of data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line;

[0360] The same data line is electrically connected to sub-pixels of the same color;

[0361] The at least two columns of data lines are electrically connected to sub-pixels of the same color.

[0362] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0363] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display panel comprising a plurality of rows and columns of sub-pixels, a plurality of columns of data lines and a data voltage supply circuit; The same data line is electrically connected to sub-pixels of the same color; The data voltage supply circuit is electrically connected to the multiplexing control line, the multiple data voltage supply terminals and the multiple columns of data lines respectively, and is used to provide the data voltage provided by the same data voltage supply terminal to at least two columns of data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line; The at least two columns of data lines are electrically connected to sub-pixels of the same color.

2. The display panel according to claim 1, wherein: Two columns of data lines are arranged between two adjacent columns of sub-pixels; The even-numbered columns of sub-pixels included in the display panel are first color sub-pixels; The sub-pixels in the 4n-3rd columns of the odd-numbered rows of the display panel are sub-pixels of the second color, and the sub-pixels in the 4n-3rd columns of the even-numbered rows of the display panel are sub-pixels of the third color; The sub-pixel in the 4n-1th column of the odd-numbered row included in the display panel is a sub-pixel of the third color, and the sub-pixel in the 4n-1th column of the even-numbered row included in the display panel is a sub-pixel of the second color; n is a positive integer greater than or equal to 1.

3. The display panel according to claim 2, wherein: The data line in the 8m-7th column is electrically connected to the second color sub-pixel located in the 4m-3th column; The data line in the 8m-6th column is electrically connected to the third color sub-pixel in the 4m-3th column; The data line in the 8m-5th column is electrically connected to a portion of the first color sub-pixels located in the 4m-2th column; The data line in the 8m-4 column is electrically connected to another portion of the first color sub-pixels located in the 4m-2 column; The data line in the 8m-3 column is electrically connected to the third color sub-pixel in the 4m-1 column; The data line in the 8m-2 column is electrically connected to the second color sub-pixel located in the 4m-1 column; The data line in the 8m-1th column is electrically connected to a portion of the first color sub-pixels located in the 4mth column; The data line in the 8mth column is electrically connected to another portion of the first color sub-pixels located in the 4mth column; m is a positive integer greater than or equal to 1.

4. The display panel according to claim 3, wherein: The data voltage supply circuit includes a first supply circuit, a second supply circuit and a third supply circuit; the plurality of data voltage supply terminals include a plurality of first supply terminals, a plurality of second supply terminals and a plurality of third supply terminals; The first supply terminal is a data voltage supply terminal for providing a first color data voltage, the second supply terminal is a data voltage supply terminal for providing a second color data voltage, and the third supply terminal is a data voltage supply terminal for providing a third color data voltage; The first providing circuit is electrically connected to the multiplexing control line, the plurality of first providing terminals and the plurality of columns of first data lines respectively, and is used to write the first color data voltage provided by the same first providing terminal into at least two columns of first data lines in a time-sharing manner under the control of the multiplexing control signal; The second providing circuit is electrically connected to the multiplexing control line, the plurality of second providing terminals and the plurality of columns of second data lines respectively, and is used to write the second color data voltage provided by the same second providing terminal into at least two columns of second data lines in a time-sharing manner under the control of the multiplexing control signal; The third providing circuit is electrically connected to the multiplexing control line, a plurality of third providing terminals and a plurality of columns of third data lines respectively, and is used to write the third color data voltage provided by the same third providing terminal into at least two columns of third data lines in a time-sharing manner under the control of the multiplexing control signal; The first data line is electrically connected to the first color sub-pixel, the second data line is electrically connected to the second color sub-pixel, and the third data line is electrically connected to the third color sub-pixel.

5. The display panel according to claim 4, wherein: The multiplexed control line includes a first control line and a second control line; The first providing circuit includes a plurality of first providing sub-circuits; The ath first providing subcircuit is electrically connected to the first control line, the second control line, the ath first providing terminal, the 4a-1th column data line and the 4a column data line respectively, and is used to write the first color data voltage provided by the ath first providing terminal into the 4a-1th column data line under the control of the first control signal provided by the first control line, and write the first color data voltage provided by the ath first providing terminal into the 4a column data line under the control of the second control signal provided by the second control line; a is a positive integer greater than or equal to 1.

6. The display panel according to claim 5, wherein: The ath first providing subcircuit comprises an ath first transistor and an ath second transistor; The gate of the ath first transistor is electrically connected to the first control line, the first electrode of the ath first transistor is electrically connected to the ath first supply terminal, and the second electrode of the ath first transistor is electrically connected to the 4a-1th column data line; The gate of the ath second transistor is electrically connected to the second control line, the first electrode of the ath second transistor is electrically connected to the ath first supply terminal, and the second electrode of the ath second transistor is electrically connected to the 4ath column data line.

7. The display panel according to claim 4, wherein: The multiplexed control line includes a first control line and a second control line; The first providing circuit includes a plurality of first providing sub-circuits; The 2a-1th first providing subcircuit is electrically connected to the first control line, the second control line, the 2a-1th first providing terminal, the 8a-5th column data line and the 8a column data line respectively, and is used to write the first color data voltage provided by the 2a-1th first providing terminal into the 8a-5th column data line under the control of the first control signal provided by the first control line, and write the first color data voltage provided by the 2a-1th first providing terminal into the 8a column data line under the control of the second control signal provided by the second control line; The 2a first providing subcircuit is electrically connected to the first control line, the second control line, the 2a first providing terminal, the 8a-4 column data line and the 8a-1 column data line respectively, and is used for providing the first control line provided by the first control line. Under the control of the second control signal provided by the second control line, the first color data voltage provided by the 2a first supply terminal is written into the 8a-1 column data line, and under the control of the second control signal provided by the second control line, the first color data voltage provided by the 2a first supply terminal is written into the 8a-4 column data line; a is a positive integer greater than or equal to 1.

8. The display panel according to claim 7, wherein: The 2a-1th first providing subcircuit comprises a 2a-1th first transistor and a 2a-1th second transistor; The gate of the 2a-1th first transistor is electrically connected to the first control line, the first electrode of the 2a-1th first transistor is electrically connected to the 2a-1th first supply terminal, and the second electrode of the 2a-1th first transistor is electrically connected to the 8a-5th column data line; The gate of the 2a-1 second transistor is electrically connected to the second control line, the first electrode of the 2a-1 second transistor is electrically connected to the 2a-1 first supply terminal, and the second electrode of the 2a-1 second transistor is electrically connected to the 8a column data line; The 2ath first providing subcircuit comprises a 2ath first transistor and a 2ath second transistor; The gate of the 2a-th first transistor is electrically connected to the first control line, the first electrode of the 2a-th first transistor is electrically connected to the 2a-th first supply terminal, and the second electrode of the 2a-th first transistor is electrically connected to the 8a-1-th column data line; The gate of the 2a second transistor is electrically connected to the second control line, the first electrode of the 2a second transistor is electrically connected to the 2a first supply terminal, and the second electrode of the 2a second transistor is electrically connected to the 8a-4 column data line.

9. The display panel according to claim 4, wherein: The multiplexed control line includes a first control line and a second control line; The second providing circuit includes a plurality of second providing sub-circuits; The ath second providing subcircuit is electrically connected to the first control line, the second control line, the ath second providing terminal, the 8a-7th column data line and the 8a-2nd column data line respectively, and is used for writing the second color data voltage provided by the ath second providing terminal into the 8a-7th column data line under the control of the first control signal provided by the first control line, and writing the second color data voltage provided by the ath second providing terminal into the 8a-2nd column data line under the control of the second control signal provided by the second control line; a is a positive integer greater than or equal to 1.

10. The display panel according to claim 9, wherein: The ath second providing subcircuit comprises an ath third transistor and an ath fourth transistor; The gate of the ath third transistor is electrically connected to the first control line, the first electrode of the ath third transistor is electrically connected to the ath second supply terminal, and the second electrode of the ath third transistor is electrically connected to the 8a-7th column data line; The gate of the ath fourth transistor is electrically connected to the second control line, the first electrode of the ath fourth transistor is electrically connected to the ath second supply terminal, and the second electrode of the ath fourth transistor is electrically connected to the 8a-2 column data line. catch.

11. The display panel according to claim 4, wherein: The multiplexed control line includes a first control line and a second control line; The third providing circuit includes a plurality of third providing sub-circuits; The ath third providing subcircuit is electrically connected to the first control line, the second control line, the ath third providing terminal, the 8a-6th column data line and the 8a-3th column data line respectively, and is used for writing the third color data voltage provided by the ath third providing terminal into the 8a-3th column data line under the control of the first control signal provided by the first control line, and writing the third color data voltage provided by the ath third providing terminal into the 8a-6th column data line under the control of the second control signal provided by the second control line; a is a positive integer greater than or equal to 1.

12. The display panel according to claim 11, wherein: The ath third providing subcircuit comprises an ath fifth transistor and an ath sixth transistor; The gate of the ath fifth transistor is electrically connected to the second control line, the first electrode of the ath fifth transistor is electrically connected to the ath third supply terminal, and the second electrode of the ath fifth transistor is electrically connected to the 8a-6th column data line; The gate of the ath sixth transistor is electrically connected to the first control line, the first electrode of the ath sixth transistor is electrically connected to the ath third supply terminal, and the second electrode of the ath sixth transistor is electrically connected to the 8a-3 column data line.

13. The display panel according to any one of claims 1 to 12, wherein: The sub-pixels are arranged in an effective display area of ​​the display panel, and the data voltage providing circuit is arranged in a peripheral area of ​​the display panel.

14. A method for driving a display panel, applied to the display panel according to any one of claims 1 to 13, the method for driving a display panel comprising: The data voltage supply circuit provides the data voltage provided by the same data voltage supply terminal to at least two columns of data lines in a time-sharing manner under the control of the multiplexing control signal provided by the multiplexing control line; The same data line is electrically connected to sub-pixels of the same color; The at least two columns of data lines have sub-pixels of the same color.

15. A display device comprising the display panel according to any one of claims 1 to 13.

Images