Data modulation and coding method and apparatus

Abstract

Provided in the present application are a data modulation and coding method and apparatus. The method comprises: splitting first data into multiple paths of second data; interpolating a polarity control bit into each path of second data after splitting, wherein the numerical value borne by the polarity control bit is used for adjusting the number of first numerical values in the corresponding path of second data, such that the parity of the preset sum of the number of first numerical values is realized; and performing modulation and coding on the multiple paths of second data according to the parity of the preset sum of the number of first numerical values. The data modulation and coding speed can be increased.

Description

Data modulation and coding method and device Technical Field

[0001] The present application relates to the field of data processing, and in particular to a method and device for data modulation and coding. Background Art

[0002] As the demand for high-density optical discs continues to increase, the requirements for the read and write speed of data on high-density optical discs are getting higher and higher, which also puts higher requirements on the processing rate of channel encoding and decoding. Modulation coding is an important part of channel encoding and decoding. Improving the efficiency of modulation coding is an effective way to improve the read and write speed of data on high-density optical discs.

[0003] How to increase the modulation and coding speed of data becomes a problem that needs to be solved.

[0004] Summary of the Invention

[0005] The present application provides a method and apparatus for data modulation and coding, which can improve the modulation and coding speed of data.

[0006] In a first aspect, the present application provides a method for data modulation and coding, comprising: splitting first data into multiple paths of second data; inserting a polarity control bit into each path of the second data after the split, and the value carried by the polarity control bit is used to adjust the number of first values ​​in the corresponding path of the second data to comply with the parity of the preset sum of the first value numbers; and modulating and coding the multiple paths of second data according to the parity of the preset sum of the first value numbers.

[0007] Based on the characteristics of the modulation code with parity retention characteristics, by splitting the first data into multiple channels of second data, adjusting the value on the polarity control bit so that the parity of the sum of the number of first numerical values ​​in each channel of second data conforms to the parity of the preset sum of the number of first numerical values, it is equivalent to being able to determine whether the starting state of the data to be encoded is the first state or the second state based on the known parity of the sum of the preset number of first numerical values, and then starting encoding based on the determined state. Therefore, parallel modulation and coding of multiple channels of second data can be achieved, effectively solving the low-speed problem caused by only serial modulation and coding of the first data, and effectively improving the data modulation and coding rate.

[0008] Optionally, the first data can be split into multiple channels of second data according to a preset first data splitting rule, such as dividing the first data into two, four or six channels of second data, etc., or the first data splitting rule can be set according to actual usage requirements, and the data in the split multiple channels of second data can be the same or different, so that different modulation and coding requirements can be flexibly responded to.

[0009] Optionally, a polarity control bit is inserted into the last bit of each channel of second data. After determining the parity of the first value in each channel of split second data, the value of the corresponding polarity control bit is adjusted so that the parity of the first value in each channel of second data matches the parity of the sum of the preset number of first values. This ensures that the initial state of the data to be modulated and coded is a fixed value, thereby enabling modulation and coding to begin on multiple channels of data.

[0010] Optionally, performing modulation and coding on multiple channels of data simultaneously can maximize the speed of modulation and coding.

[0011] In one possible implementation, after simultaneously modulating and encoding the multiple channels of second data, the modulated and encoded data are merged to obtain the required data, such as obtaining a sequence to be recorded on a disc and recording it on the disc.

[0012] In a possible implementation, the modulation and encoding of the plurality of second data according to the parity of the sum of the number of the preset first values ​​includes: splitting each of the second data into a plurality of direct current components (Direct Current (DC) control blocks are provided, and a DC component control bit is inserted into each of the DC component control blocks, wherein each of the second data includes multiple rows, and each row includes a synchronization code; during modulation, each of the DC component control blocks is judged to determine whether the value of the DC component control bit of each DC component control block is the first value; if the parity of the sum of the preset first values ​​is odd, encoding the multiple second data is started from a first state, and adjusting whether the value of the polarity control bit is the first value so that the sum of the first values ​​in each parallel region is an odd number, the parallel region including the corresponding second data, the synchronization code, the multiple DC component control bits, and the polarity control bit; if the parity of the sum of the preset first values ​​is even, encoding the multiple second data is started from a second state, and adjusting whether the value of the polarity control bit is the first value so that the sum of the first values ​​in each parallel region is an even number.

[0013] Optionally, after the first data is split, multiple parallel second data are obtained, each of which is equivalent to a parallel region, each parallel region contains multiple rows of second data, and a synchronization code (SYNC) can be inserted at the beginning of each row. In each region, the second data can be split into multiple DC component control blocks, and a DC component control bit is inserted at the end of each DC component control block, and a polarity control bit is inserted at the end of each second data. When comparing whether the parity of the sum of the number of first values ​​in each parallel region meets the parity of the preset sum of the number of first values, the parity of the sum of the first number of values ​​in each second data, the first number of values ​​in the synchronization code, the first number of values ​​on the multiple DC component control bits, and the first number of values ​​on the polarity control bit should be compared with the parity of the preset sum of the number of first values.

[0014] In one possible implementation, it also includes: setting a sliding window including multiple DC component control blocks, the sliding window contains the current DC component control block being modulated; setting a weight for each DC component control block in the sliding window, the weight of each DC component control block is determined according to the position of each corresponding DC component control block in the sliding window; obtaining a current total digital sum value according to the digital sum value (DSV) of the sliding window and the global digital sum value, wherein the current total digital sum value is used for the modulation, the digital sum value of the sliding window is obtained according to the weight of each DC component control block in the sliding window, and the global digital sum value is obtained according to the current DC component control block.

[0015] Optionally, the weight of each DC component control block can be pre-set, and then adjusted in real time according to current resources, delay and other requirements during modulation and coding, so that the digital sum value calculated based on the weight is more accurate.

[0016] In one possible implementation, the plurality of DC component control blocks included in the sliding window are determined based on the current DC component block. The DC component control block included in the sliding window changes as the currently modulated DC component control block changes. Optionally, the currently modulated DC component control block can be set in the middle of the sliding window.

[0017] Optionally, the weights of each DC component control block in the sliding window can be set so that the weights of the first half of the sliding window increase from 0 to 1 and the weights of the second half decrease from 1 to 0. Since the weights of other DC component blocks close to the current DC component block are high and the weights of other DC component blocks farther away are close to zero, the calculated digital sum value can be made more stable.

[0018] In one possible implementation, obtaining the current total digital sum value based on the weights of the DC component control blocks in the sliding window and the global digital sum value includes: calculating the current total digital sum value for the first part of each parallel region according to a first preset algorithm; and calculating the current total digital sum value for the second part of each parallel region according to a second preset algorithm.

[0019] The first and second parts of each parallel region can be configured according to usage requirements, and the second parts of each parallel region can be configured to be the same or different. Optionally, the second part can be set to the last K DC component control blocks in each parallel region (K is a positive integer), and the first part is the DC component control blocks in each parallel region excluding the first part. A weighted sliding window is used to assist in the calculation of the total digital sum value, and different weights are assigned to DC component control blocks at different positions in the sliding window during the modulation process. This can reduce the drastic changes that may occur in the calculation of the total digital sum value when multiple parallel channels are used, thereby achieving better control effects of the component control blocks.

[0020] In a second aspect, the present application provides a device, comprising: a first splitting module, configured to split first data into multiple paths of second data;

[0021] a first inserting module, configured to insert a polarity control bit into each path of the split second data, wherein the value carried by the polarity control bit is used to adjust the number of first values ​​in the corresponding path of the second data to conform to the parity of a preset sum of the number of first values, the value of which is determined by the processing module;

[0022] The modulation and coding module is used to modulate and code the multiple channels of second data according to the parity of the sum of the preset first numerical quantities.

[0023] In one possible implementation, the present invention further includes: a second splitting module, configured to split each path of the second data into a plurality of DC component control blocks; a second inserting module, configured to insert a DC component control bit into each of the DC component control blocks, wherein each path of the second data includes a plurality of rows, and each row includes a synchronization code; a DC component judgment module, configured to judge each of the DC component control blocks during modulation to determine whether the value on the DC component control bit of each DC component control block is the first value; and the modulation coding module, specifically configured to, if the parity of the sum of the number of the preset first values ​​is an odd number, The first state starts to encode the multiple second data, and by adjusting whether the value on the polarity control bit is the first value, the sum of the number of the first values ​​in each parallel area is an odd number, and the parallel area includes the second data of the corresponding path, the synchronization code, the multiple DC component control bits and the polarity control bit; if the parity of the sum of the preset first value number is an even number, the second state starts to encode the multiple second data, and by adjusting whether the value on the polarity control bit is the first value, the sum of the number of the first values ​​in each parallel area is an even number.

[0024] In one possible implementation, it also includes: a sliding window digital sum value calculation module, used to set a sliding window including multiple DC component control blocks, the sliding window contains the current DC component control block being modulated; setting a weight for each DC component control block in the sliding window, the weight of each DC component control block is determined according to the position of each corresponding DC component control block in the sliding window; the DC component judgment module, specifically used to obtain a current total digital sum value based on the digital sum value of the sliding window and the global digital sum value, wherein the current total digital sum value is used for the modulation, the digital sum value of the sliding window is obtained according to the weight of each DC component control block in the sliding window, and the global digital sum value is obtained according to the current DC component control block.

[0025] In a possible implementation, the multiple DC component control blocks included in the sliding window are determined according to the current DC component block.

[0026] In one possible implementation, the DC component judgment module is specifically configured to calculate the current total digital sum value for the first part of each parallel region according to a first preset algorithm; and calculate the current total digital sum value for the second part of each parallel region according to a second preset algorithm.

[0027] In a third aspect, the present application provides a device comprising at least one processing unit and a transceiver unit, wherein the at least one processing unit and the transceiver unit are coupled, and when the at least one processing unit executes a program or instruction, the device implements part or all of the operations of the first aspect and any possible implementation of the first aspect. The device may be a device or a chip in a device.

[0028] In a fourth aspect, the present application provides a device comprising a communication port and a processor, wherein the communication port is used to perform the transceiver operations involved in the method described in any of the aforementioned aspects and any possible implementation of any of the aforementioned aspects, and the processor is used to perform other operations other than the transceiver operations involved in the method described in any of the aforementioned aspects and any possible implementation of any of the aforementioned aspects. For example, when the device is used as an apparatus to perform the method described in the first aspect, the processor is used to split the first data into multiple paths of second data; insert a polarity control bit into each path of the split second data, and the value carried by the polarity control bit is used to adjust the number of first values ​​in the corresponding path of the second data to comply with the parity of the preset sum of the number of first values; and modulate and encode the multiple paths of second data according to the parity of the preset sum of the number of first values.

[0029] In a fifth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements part or all of the operations included in the method described in any of the aforementioned aspects and any possible implementation method of any of the aforementioned aspects.

[0030] In a sixth aspect, the present application provides a computer program product comprising instructions which, when executed on a processor, implement the method described in any of the foregoing aspects and part or all of the operations included in any possible implementation of any of the foregoing aspects.

[0031] In a seventh aspect, the present application provides a chip comprising: a port circuit and a processor. The port circuit is connected to the processor, and the processor is configured to cause the chip to perform some or all of the operations included in the method described in any of the aforementioned aspects and any possible implementation of any of the aforementioned aspects.

[0032] It should be understood that the second to seventh aspects of the present application are consistent with or correspond to the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] FIG1 is a schematic flow chart of a data modulation and coding method provided in an embodiment of the present application;

[0035] FIG2 is a schematic diagram of a data structure of two paths of second data obtained after splitting according to an embodiment of the present application;

[0036] FIG3 is a schematic diagram of a DC judgment process provided by an embodiment of the present application;

[0037] FIG4 is a schematic flow chart of a DSV calculation method provided in an embodiment of the present application;

[0038] FIG5 is a schematic diagram of the structure of a sliding window provided in an embodiment of the present application;

[0039] FIG6 is a flow chart of a total DSV calculation method provided in an embodiment of the present application;

[0040] FIG7 is a schematic structural diagram of another device provided in an embodiment of the present application;

[0041] FIG8 is a flow chart of another method for data modulation and coding provided in an embodiment of the present application;

[0042] FIG9 is a schematic structural diagram of another device provided in an embodiment of the present application;

[0043] FIG10 is a schematic structural diagram of a device 20 according to an embodiment of the present application;

[0044] FIG11 is a schematic structural diagram of a device 30 according to an embodiment of the present application;

[0045] FIG12 is a schematic structural diagram of a device 40 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to enable people in this technical field to better understand the solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in combination with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0047] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0048] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0049] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0050] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0051] For ease of understanding, the following first explains the relevant nouns or terms used in the embodiments of this application:

[0052] 1. Error Correction Code (ECC) cluster

[0053] A single data block obtained by error correction coding of a data stream is defined as an ECC cluster. In the embodiment of the present application, the ECC cluster can be used as the original data input for modulation.

[0054] 2. Non-Return to Zero Inverting (NRZI) encoding

[0055] This coding method is for modulation coding, and a jump occurs every time a "1" signal is encountered; it remains unchanged when a "0" signal is encountered.

[0056] 3.DSV

[0057] For NRZI-encoded data, DSV increases by 1 each time a "1" is encountered, and decreases by 1 each time a "0" is encountered.

[0058] 4. DC control bit

[0059] The DC control bit is used to be inserted into the ECC cluster. Its value can be "0" or "1". Its function is to help control DSV through its value.

[0060] 5. DC control block: 45 bits of original data and 1 DC control bit form a DC control block. During modulation, the data of a DC control block is sent to the modulation unit together.

[0061] 6. Polarity control bit: replaces the function of part of the DC control bit. Its value can be "0" or "1". Its function is to control the parity of the number of "1" in the modulated original data.

[0062] 7. Synchronous code

[0063] It is a special 30-bit code used to identify the start of a data frame.

[0064] 8. Parity

[0065] It indicates whether the number of "1"s in the data is an odd number or an even number, or it indicates whether the number of "0"s in the data is an odd number or an even number.

[0066] The data modulation and coding method provided in the embodiments of the present application can be applied in different data modulation and coding scenarios. The embodiments of the present application illustrate the case where the data to be modulated and coded is the first data, and when performing modulation and coding, encoding is started based on the parity of the number of "0"s or "1"s in the data (e.g., modulation and coding using NRZI encoding). Figure 1 is a flow chart of a data modulation and coding method provided in the embodiments of the present application. As shown in Figure 1, the method includes but is not limited to steps S101 to S103.

[0067] Optionally, the subject that performs the following operations can be a device, equipment, chip, etc. The embodiment of the present application is explained using the subject as an example of a device. When other forms of subjects perform operations, they can refer to this example and are not limited to the example.

[0068] S101. The device splits first data into multiple channels of second data.

[0069] Optionally, the first data may be various types of data that need to be modulated and coded, for example, the first data may be an ECC cluster.

[0070] In some examples, first data, such as an ECC cluster, can be split according to a first data splitting rule to obtain multiple paths of second data. For example, the first data splitting rule can be to divide the ECC cluster into two equal-sized areas, each area including the same amount of data. Assume that an ECC cluster includes 496 rows, each row includes N bits of data, where N is a positive integer greater than 1. According to the first data splitting rule, the ECC cluster can be evenly divided into two areas. The first area includes rows 1 to 298, each row includes N bits of data, and the second area includes rows 299 to 496, each row includes N bits of data. This is equivalent to splitting the first data to obtain two parallel paths of second data. The first second data can be recorded as second data A, including data in the first area, and the second second data can be recorded as second data B, including data in the second area. Alternatively, the first preset rule may be to divide the ECC cluster into four areas of equal size, each area including the same amount of data, or the first preset rule may be to divide the ECC cluster into six areas of different sizes, each two areas including the same amount of data, etc. The first data splitting rule may be set according to actual usage requirements and is not limited to the examples in the embodiments of the present application.

[0071] S102: The device inserts a polarity control bit into each split second data path. The value carried by the polarity control bit is used to adjust the number of first values ​​in the corresponding second data path to meet the parity of the preset sum of the first values.

[0072] In some actual usage scenarios, the first data is serially processed and modulated and encoded. The method of serial modulation and encoding includes: before the modulation starts, the unmodulated original data (such as the first data provided in the embodiment of the present application) can be divided into multiple DC control blocks, and a DC control bit is inserted at the end of each DC control block. If each DC control block includes 45 bits of first data, it is necessary to insert a 1-bit DC control bit after every 45 bits of data, and the value carried by the DC control bit can be 0 or 1. Taking one of the DC control blocks as an example, if the DC control block is recorded as DC control block 1, and DC control block 2 is included before DC control block 1, the value carried by the DC control bit of DC control block 1 is first taken as 0 and 1 respectively, and the DSV of DC control block 1 when the value of the DC control bit of DC control block 1 is 0, and the DSV of DC control block 1 when the value of the DC control bit of DC control block 1 is 1 are calculated respectively, and then the obtained DSV of DC control block 1 is summed with the total DSV obtained previously, and the DC control bit value corresponding to the value with the smallest absolute value in the summation result is selected as the value result of the DC control bit, and the total DSV is updated. For example, after calculating the DSV of DC control block 2, the total DSV obtained is -7. When the value of the DC control bit of DC control block 1 is 0, the DSV of DC control block 1 is 5. When the value of the DC control bit of DC control block 1 is 1, the DSV is 3. After summing with the total DSV of -7, -2 and -4 are obtained respectively. The value of DC control block 1 with the smaller absolute value, i.e., -2, is selected. That is, the value of the DC control bit of DC control block 1 is confirmed to be 0 after DC judgment, and the total DSV is updated to -2. This is repeated until the calculation of the first data is completed. Since the calculation result of the total DSV in this method depends on the DSV calculation result of the previous DC control block, when performing modulation coding in this way, all data in the first data must be processed in serial order (i.e., during modulation coding, only one NRZI encoder can be used to serially process the entire first data). If the processing of the previous data is not completed, the subsequent data cannot be calculated, and the first data cannot be processed in parallel, resulting in slow processing speed and low efficiency. In order to solve this problem, the embodiment of the present application splits the first data into multiple second data according to the method of S101, and inserts a polarity control bit into each second data, such as at the end of the second data, so as to adjust the parity of the sum of the number of first values ​​in the corresponding second data to conform to the parity of the sum of the number of first values ​​by adjusting the value on each polarity control bit to 0 or 1, so that after splitting, modulation and coding of multiple second data are realized. Furthermore, the device can realize modulation and coding of multiple parallel second data at the same time based on the value on the modulation polarity control bit to improve the speed of modulation and coding.

[0073] For example, if an ECC cluster is split into two parallel second data according to the first data splitting rule, parallel regions (including parallel region A and parallel region B) are obtained. Figure 2 is a data structure diagram of the two parallel regions obtained after splitting provided by an embodiment of the present application. As shown in Figure 2, each parallel region (including parallel region A and parallel region B) includes multiple rows of second data, a synchronization code (SYNC) can be inserted into the first bit of each row, and each row includes several DC control blocks, each DC control block includes bits carrying the second data and a DC control bit (simply referred to as DC bit in Figure 2), and a polarity control bit (simply referred to as X bit in Figure 2) is inserted at the end of the second data in parallel region A and the second data in parallel region B.

[0074] S103: The device presets the parity of the sum of the first numerical quantities and performs modulation and coding on the multiple channels of second data.

[0075] In some examples, a modulation code with a parity-preserving property, such as a 17PP modulation code, is used to modulate and encode the second data. The parity of the number of "1s" in the second data is the same as the parity of the number of "1s" after modulation and encoding, and the parity of the number of "0s" in the second data is also the same as the parity of the number of "0s" after modulation and encoding. Based on the characteristics of this parity-preserving modulation code, whether the polarity control bit is the first value (i.e., the polarity control bit is the first value or the second value; when the first value is 1, the second value is 0, and when the second value is 0, the first value is 1) can be adjusted to ensure that the parity of the sum of the number of first values ​​in each parallel region meets the parity of the preset sum of the number of first values. The sum of the number of first values ​​in the parallel region includes: the sum of the first value in the second data, the number of first values ​​in the DC control bit inserted in the second data, the number of first values ​​in the synchronization code, and the number of first values ​​in the polarity control bit. For example, if the second data originally has 100 "1s", after modulation and encoding, it still has 100 "1s". If NRZI encoding is used, based on the characteristic of NRZI encoding that it transitions every time it encounters a "1" signal and remains unchanged when encountering a "0", it is only necessary to determine whether the sum of the number of "1"s or "0"s in each channel of second data is an odd or even number to determine the number of transitions to be performed on the NRZI encoding. If the sum of the number of "1"s is an odd number, the NRZI encoding can be set to start from the first state, which can be a transition, that is, the NRZI encoding starts from the transition. If the sum of the number of "1"s is an even number, the NRZI encoding can be set to start from the second state, which can be unchanged, that is, the NRZI encoding starts from the unchanged state. For example, if the current input voltage is low and encounters a "1", the next NRZI encoding will start from a transition, that is, a transition to a high voltage. Conversely, if a "0" is encountered, it will remain at a low voltage. Based on this feature, the device can set the preset sum of the first numerical values ​​in advance, and by adjusting the value on the polarity control bit of each second data, make the parity of the sum of the first numerical values ​​in each parallel area the same as the preset sum of the first numerical values. This can ensure that each NRZI encoding starts from a jump, or start from keeping the current voltage unchanged. Based on the known starting state of NRZI encoding for each data channel, each second data channel can start modulation encoding at the same time.For example, if the first value is set to 1, each NRZI encoding operation must begin by maintaining the current voltage unchanged. The parity of the sum of the first value is preset to be an even number, that is, the sum of the number of "1s" is an even number. Therefore, the sum of the number of "1s" in each channel of second data should be an even number. Assuming that second data A includes 100 "1s" and the number of "1s" inserted in the synchronization code and DC control bit is an odd number, then to ensure that the parity of the sum of the preset first value is even, the value of the polarity control bit of second data A is determined to be 1. Second data B includes 102 "1s" and the number of "1s" inserted in the synchronization code and DC control bit is an even number. To ensure that the parity of the sum of the preset first value is even, the value of the polarity control bit of second data B is determined to be 0. The same applies to cases where the first value is set to 0 or the parity is determined to be even, and is not further described.

[0076] In one possible implementation, the device determines the sum of the number of first values ​​in each parallel region and also needs to determine the value carried by the DC control bit of each DC control block, wherein the DC control bit can be inserted at the end of each DC control block. That is, the device inserts 0 or 1 into the DC control bit of each DC block in each channel of second data to determine the value of the DC control bit of each DC block, that is, performs a DC judgment to determine whether the value of the DC control bit is the first value (that is, the DC control bit is the first value or the second value, when the first value is 1, the second value is 0, and when the second value is 0, the first value is 1). If the first data is split into parallel region A and parallel region B with reference to FIG2, the value of the DC control bit of each DC block can be determined by referring to the following example: Taking parallel region A as an example for explanation, the modulation coding of the data in parallel region B refers to the first data A and will not be expanded. On each DC control bit in parallel region A, data "0" and data "1" are written respectively to perform DC judgment. For example, when judging DC control block 1, the DC control bit of DC control block 1 takes the values ​​of 0 and 1 respectively, corresponding to the first data stream with the DC control bit of "0" and the second data stream with the DC control bit of "1". DSV calculation is then performed on the first data stream and the second data stream respectively. The DSV calculation result includes the sum of the current first data stream and the current total DSV. For example, a DC control block can be composed of 45 bits of pre-modulation data (i.e., the second data of the corresponding path) and 1 bit of DC control bit. Each 46-bit DC control block is the minimum unit for DC judgment. Referring to the parallel area A in Figure 2, the DC control block currently performing DC judgment (including DSV calculation) is defined as the DC control block performing modulation within the current window, and the first DC control block in the parallel area A is defined as DC control block 1. Similarly, if the current window is calculating DC control block 298, the DVS of the first data stream with a DC control bit of 0 is 10, and the DVS of the second data stream with a DC control bit of 1 is -6, the current total DSV calculated previously (i.e., the sum of the DSVs of DC control block 1 to DC control block 297, such as -7) is added together, and the DSV with the smallest absolute value of the sum of DSVs is selected to update the current total DSV, and the corresponding value on the DC control bit is determined. For example, the sum of the DVS of the first data stream and the current total DSV is 3, and the sum of the DSV of the second data stream and the current total DSV is -13. No further details are given. During modulation, in order to make the number of "1" and "0" in the data finally encoded by NRZI as close as possible, the absolute value of the sum of DSVs with the smallest value is selected as the value on the DC control bit. Therefore, the absolute value with the smallest value, i.e. -13, is selected as the current total DSV, and the value on the DC control bit of DC control block 298 is judged to be 0, and the judgment of other DC control blocks is similar.

[0077] In one possible implementation, the device inserts 0 or 1 into the DC control bit of each DC block in each channel of second data, and determines which modulation code is used when the DC control bit of a DC control block is inserted with "0", and which modulation code is used when the DC control bit of a DC control block is inserted with "1". The process of making a DC decision can refer to Figure 3, which is a flow chart of a DC decision provided by an embodiment of the present application. As shown in Figure 3, the device can make a decision on each DC control block under different DC control bit values, that is, make a variable length code decision on each DC control block, and determine the modulation code suitable for each DC control block. For example, referring to the modulation code table, it is determined which modulation code is used when the DC control bit of a DC control block is inserted with "1" and "0". After calculating the DSV and determining the value with reference to the above example, the DC control block is encoded according to the modulation code used for "1" or "0". For example, the DC decision can be made with reference to the 17PP modulation code table. Table 1 is an example of a 17PP modulation code table.

[0078] Table 1

[0079] For example, if a judgment is made on DC control block 1, DC control block 1 includes 45 bits of data and 1 DC control bit, and the DC control bit takes the value of "1" or "0", the DC judgment can be made from short to long. For example, referring to Table 1, the data in DC control block 1 before modulation and coding, called original data (including the second data obtained by splitting previously and the "1" or "0" carried on the DC control bit), is converted into a modulation code. Referring to Figure 3, the 2-bit original data can be converted into a 3-bit modulation code in sequence. If the first two bits of original data in DC control block 1 meet the requirements of the 2-bit original data being converted into a 3-bit modulation code, 2-to-3 encoding can be performed, such as modulating and encoding the second data in DC control block 1 through a 2-3 encoder. If the original data in control block 1 does not meet the requirements of the 2-bit original data being converted into a 3-bit modulation code, the replacement table is used to replace whether it meets the requirements of the 6-bit original data being converted into a 9-bit modulation code. If it does not meet the requirements, the next two bits are looked back, that is, the judgment is made through the first four bits of data in DC control block 1 until the corresponding modulation code is found, and so on. This judgment can refer to Figure 3, or it can be made according to the code table of other variable-length codes, such as 4 to 6, 6 to 8, or 8 to 12, until the modulation code of DC control block 1 is found, and then the judgment of the next DC control block is made to obtain the modulation code of each DC control block, and then NRZI encoding is performed according to the modulation code corresponding to the final DC control bit value of each DC control block.

[0080] Optionally, based on the fact that the parity of the sum of the first numerical values ​​in each channel of second data meets the parity of the preset sum of the first numerical values, multiple channels of second data can be NRZI-encoded. For example, after splitting the first data into two channels of second data, the two channels of second data are NRZI-encoded simultaneously, and the two channels of encoded data are finally merged to obtain the data required for use, such as a sequence recorded on an optical disc. Alternatively, after splitting the first data into four channels of second data, the four channels of second data are NRZI-encoded simultaneously, and the four channels of encoded data are finally merged to obtain the data required for use. When merging data, the order of splitting can be referred to for restoration and merging. For example, if the first data is split into parallel region A and parallel region B as shown in FIG2 , and parallel region A is the first half of the first data and parallel region B is the second half of the first data, then when merging, the data modulated and encoded according to parallel region A is placed in front, and the data modulated and encoded according to parallel region B is placed in the back.

[0081] By splitting the first data into multiple channels of second data, and adjusting the value of the polarity control bit, the parity of the sum of the number of first values ​​in each channel of second data is made to conform to the parity of the preset sum of the number of first values. When each channel of second data uses the preset sum of the first values ​​to determine the start of NRZI encoding, although it is impossible to determine the exact number and position of the first value ("1" or "0") appearing in each channel of second data, by knowing the parity of the number of first values ​​in each channel of second data, it is possible to know whether the NRZI encoding will jump before and after the second data, and then start modulation encoding with a determined starting state (whether it jumps or remains unchanged). Therefore, multiple parallel channels of second data can be modulated and encoded at the same time, which effectively improves the speed of modulation encoding. When used in scenarios such as high-density optical disc reading and writing, it can also effectively improve the reading and writing rate of data on high-density optical discs.

[0082] In one possible implementation, based on the method provided in an embodiment of the present application, the data after multi-channel parallel modulation and encoding also needs to be written in a serial order. For example, with reference to the method provided in Figure 1, the data is finally merged to obtain a record sequence after modulation and encoding, and the record sequence needs to be written into the optical disc in a serial order. Therefore, when performing DSV calculation, an embodiment of the present application provides a DSV calculation and selection strategy, which can obtain output data with a smaller DSV in the serial sequence when multi-channel parallel modulation and encoding is performed, thereby ensuring that after multi-channel parallel modulation and encoding, the overall data fluctuation is not large when serially written, and maintains good writing stability.

[0083] FIG4 is a flow chart of a DSV calculation method provided in an embodiment of the present application. As shown in FIG4 , the method includes: S201 to S203 .

[0084] S201. The device sets a sliding window including multiple DC control blocks, where the sliding window includes a current DC control block being modulated.

[0085] In some examples, the size of the sliding window, i.e., the number of DC control blocks included in the sliding window, can be determined according to the first data splitting rule. If the first data splitting rule is to split the first data into two parallel regions as shown in FIG2 , then the size of the sliding window can be set to the size of each parallel region, or the sliding window can include the size of the partial data included in the parallel region A or the parallel region B as shown in FIG2 , etc. For example, the sliding window can include the synchronization code of each row in the parallel region A, the inserted DC control bit, and the second data in the region.

[0086] For example, if an ECC cluster is split into four parallel paths of second data according to the first data splitting rule, the size of the sliding window is 1 / 4 of the length of the ECC cluster, that is, when an ECC cluster includes 13888 DC control blocks, a sliding window includes 3472 DC control blocks. If the current DC control block is the 3000th DC control block in each path of second data, then the first sliding window can be set to a window including the 3000th DC control block in the first path of second data, as shown in FIG5 (the number of DC control blocks in FIG5 is an example, not all of them are shown, and FIG5 takes the first sliding window in the first path of second data as an example, and the other three sliding windows are on the corresponding paths of second data and at corresponding positions of the first sliding window, not shown in FIG5). The first sliding window includes a total of 1736 DC control blocks before the 3000th DC control block and 1735 control blocks after the 3000th DC control block. The second sliding window in the second path of second data, the third sliding window in the third path of second data, and the fourth sliding window in the fourth path of second data may all refer to the first sliding window and will not be described in detail.

[0087] Optionally, the DC control blocks included in the sliding window will change with the change of the currently modulated DC control block. For example, when the modulation reaches the Mth DC control block, the sliding window contains the (M-1736) DC control blocks before the current DC control block and the (M-1735) DC control blocks after the current DC control block, where M is a positive integer determined according to the size of the sliding window, 1736 and 1735 are examples, and the size of the sliding window is determined according to the first data splitting rule and the size of the first data. Taking the currently modulated DC control block as the center of the sliding window is an example, but it is not limited to this.

[0088] S202: The device sets a weight for each DC control block in the sliding window. The weight of each DC control block is determined according to the position of each DC control block in the sliding window.

[0089] Optionally, when setting the device, the weight of the first half of the sliding window (i.e., the DC control block before the current DC control block) can be increased from 0 to 1, and the weight of the second half (i.e., the DC control block after the current DC control block) can be decreased from 1 to 0. For example, in the first half of the sliding window, the weight of the p-th DC control block is p / 1736 according to the position, and in the second half of the sliding window, the weight of the q-to-last DC control block is q / 1735 according to the position, where 0≤p≤1736 and 0≤q≤1735. Alternatively, in the front part of the sliding window, the weight changes from 0 to 1 times, while in the second half of the sliding window, the weight decreases from 2 times to 1 times. Setting the weight of each DC control block in the sliding window in this way can reduce the dependence on the calculation results of the DC control block before the current DC control block. That is, whether the DVS value of the DC control block before the current DC control block is well controlled or poorly controlled, it is a calculated value and does not require excessive reference. Therefore, the weight is set smaller. After the current DC control block, the DSV of the DC control block that has not yet been modulated needs to be better controlled, so the weight of the second half of the sliding window is increased. Setting the weight of each DC control block in the sliding window in this way is conducive to better control of the DSV of the sliding window.

[0090] Optionally, the weights of the DC control blocks at each position in the sliding window can be pre-determined before modulation, and then adjusted and determined during real-time calculation based on current resource, latency, and other requirements. When the current DC control block changes, since the total number of DC control blocks in the sliding window remains unchanged, the weights of each DC control block in the sliding window are still determined based on the pre-determined and changed positions of the current DC control block to perform DSV calculation.

[0091] S203. The device obtains a current total DSV according to the DSV of the sliding window and the global DSV, wherein the DSV of the sliding window is obtained according to the weight of each DC control block in the sliding window, and the global DSV is obtained according to the current DC control block.

[0092] For example, the total DSV can be obtained by referring to FIG6 and formula 1. Total DSV = sliding window DSV * weight + global DSV * weight Formula 1

[0093] Among them, the DC control blocks included in the sliding window and their weights are determined with reference to the S202 example. If there are 3472 DC control blocks in the sliding window, the sliding window DSV is obtained by multiplying the 3472 DC control blocks by their corresponding weights and then adding them together, that is, the sliding window DSV is obtained by multiplying each DC control block in the sliding window by its weight and finally adding them together. The global DSV is obtained based on the current DC control block of each parallel region, which means the DSV of all DC control blocks starting from the first DC control block of the second data of the first path to the current DC control block of each path. For example, if there are four parallel paths of second data, for each path of second data, the DC control block currently being modulated is the 3000th DC control block of the path. For the first path of second data, the global DSV refers to the sum of the DSVs from the 1st DC control block in the first path of second data to the 3000th DC control block of the first path of second data. For the second path of second data, the global DSV It refers to the sum of DSVs from the 1st DC control block in the first-path second data to the 3000th DC control block in the second-path second data. Optionally, the DSV value of the DC control block that has not yet started modulation is taken as 0. Assuming that there are 3472 DC control blocks in each path of second data, then the global DSV of the second data of the second path should be the sum of the DSVs of the first 3000 DC control blocks of the first path, the sum of the 3001st DC control block of the first path to the 3472nd DC control block of the first path (that is, the DSV of the DC control block that has not started modulation is 0) and the sum of the DSVs of the first 3000 DC control blocks of the second path.

[0094] Optionally, in order to better balance the smooth change of DSV within and between parallel regions, the total DSV of different parts of the data in each parallel region can also be calculated according to the first preset algorithm or the second preset algorithm. As shown in the above example, the first data is split into four channels of second data, and four channels of parallel second data are obtained. Each channel of parallel second data and the data on the inserted DC control bit (i.e., "1" or "0" value) are taken as a parallel region. For the first part of each parallel region, the total DSV is obtained according to the first preset algorithm. The first preset algorithm includes formula two. For the second part of each parallel region, the total DSV can be obtained according to the second preset algorithm. The second preset algorithm includes formula three. Total DSV = sliding window DSV*90% + global DSV*10% Formula two Total DSV = sliding window DSV*50% + global DSV*50% Formula three

[0095] Optionally, the first and second parts in each parallel region can be set according to usage requirements, and the second part in each parallel region can be set to be the same or different. In the embodiment of the present application, the second part is the last K (positive integer), such as 70 DC control blocks, in each parallel region, and the first part is the DC control blocks in each parallel region other than the first part. If the sliding window is as shown in Figure 5, in the first sliding window of the first parallel region, in the second half of the first parallel region, the total DSV belonging to the last 70 DC control blocks is calculated according to Formula 3, and the total DSV not belonging to the last 70 DC control blocks is calculated according to Formula 2.

[0096] Optionally, if the second half of the sliding window includes the last DC control block of a parallel region, such as the last 70 DC control blocks of the first parallel region, the weights of the DC control blocks in the second half gradually decrease from 1 to 0. If the second half of the sliding window includes the first DC control blocks of a parallel region, such as the first 1000 DC control blocks of the second parallel region, the weights of the DC control blocks in the second half of the sliding window gradually decrease from 2 to 1. By calculating the DSV according to different budget algorithms and assigning different weights to each DC control block based on the position of the sliding window, better DC control effects can be achieved.

[0097] In the embodiment of the present application, a total DSV is obtained by jointly calculating a sliding window DSV and a global DSV, which can ensure that the values ​​of each channel of second data are relatively stable and do not undergo drastic changes when modulation and coding are performed in parallel on multiple channels. For example, after splitting the first data, two parallel channels of second data are obtained, and four DC control blocks are divided into each channel of second data. That is, the first data includes a total of eight DC control blocks. Assuming that the DSV of each DC control block of the first channel of second data is -2, -1, 3, or 0, the total DSV is 0, and the DSV of each DC control block of the second channel of second data is 4, 2, -3, or -3, the total DSV is still 0. However, when serially writing to a disc, the first channel of second data is written first, and then the second channel of second data is written. Near the end of the first channel of second data and the beginning of the second channel of second data, the total DSV may be the last two DC control blocks of the first channel of second data and the first two DC control blocks of the second channel of second data, that is, 3+0+4+2=9. This means that the number of "1"s in this interval is much greater than the number of "0"s. The total DSV control is poor during writing of this section, which affects writing. Therefore, the total DSV is obtained by jointly calculating the sliding window DSV and the global DSV. Based on the continuously sliding sliding window, the total DSV of the DC control block in each path and the total DSV when each path intersect can be taken into account, so that the total DSV of each part of the parallel area is relatively smoothly controlled within a smaller absolute value range, that is, when calculating the total DSV, the global situation of the entire first data (such as the entire ECC cluster) can be perceived, avoiding the situation where the DSV control in one parallel area is very good, but the DSV control between the second data from the entire multi-path parallel is poor due to the inability to perceive the global situation. The embodiment of the present application assists in the calculation of the total DSV through a sliding window with weights, and during the modulation process, according to the changes in the current DC control block being modulated, the weights of the DC control blocks at different positions in the sliding window are changed in real time, so that the calculation of the total DSV can assist in obtaining a better DC control effect, thereby ensuring that after the multi-path parallel modulation encoding, the efficiency of serial writing is higher.

[0098] FIG7 is a schematic structural diagram of a device provided in an embodiment of the present application. As shown in FIG7 , the device 10 includes: a first splitting module 101 , a first inserting module 102 , a processing module 103 and a modulation and coding module 104 .

[0099] The first splitting module 101 is configured to split the first data into multiple paths of second data.

[0100] For example, the first splitting module 101 may split the first data into multiple paths of second data according to a first data splitting rule.

[0101] The first insertion module 102 is used to insert a polarity control bit into each path of second data after splitting. The value carried by the polarity control bit is used to adjust the number of first values ​​in the second data of the corresponding path to meet the parity of the preset sum of the number of first values. The value is determined by the processing module 103.

[0102] The value of the polarity control bit of each path is determined by the processing module 103 based on the parity of the sum of the preset first numerical values, the number of first numerical values ​​in the second data of the corresponding path, and the number of first numerical values ​​in the synchronization code. The adjustment method is referred to S103 and will not be expanded here.

[0103] Optionally, the first inserting module 102 inserts a polarity control bit at the end of each channel of second data.

[0104] The modulation and coding module 104 is configured to perform modulation and coding on the multiple channels of second data according to the parity of the sum of the preset first numerical quantities.

[0105] Optionally, the modulation and coding module 104 may include multiple modulation submodules and coding submodules to modulate and code each path of second data respectively, or multiple modulation and coding modules 104 are provided in the device to modulate and code each path of second data respectively.

[0106] The modulation and coding module 104 can perform modulation and coding on multiple channels of second data simultaneously.

[0107] Referring to the method of steps S101 to S103 in Figure 1, combined with the device 10 in Figure 7, an embodiment of the present application provides a flow chart of another method of data modulation and coding. As shown in Figure 8, after the first data enters the first splitting module 101, it is split into multiple channels of second data, and each channel of second data is inserted with a polarity control bit by a first insertion module 102. The multiple channels of second data enter the modulation and coding module 104 for modulation and coding, and the polarity control bit value of each channel of second data is determined by the processing module 103 according to the parity of the sum of the preset first numerical quantity.

[0108] It should be understood that the modules shown in Figure 7 are only examples. The first splitting module 101, the first insertion module 102, the processing module 103 and the modulation and coding module 104 can refer to the method part in the embodiment of the present application to perform their operations, or perform variations of their operations. The first trusted node includes a pure trusted node and a terminal trusted node, both of which can be applied in the method provided in Figure 1 or Figure 4 as a device to perform its operations, or perform variations of its operations.

[0109] In one possible implementation, Figure 9 is a structural diagram of another device provided in an embodiment of the present application. As shown in Figure 9, the device 10, based on Figure 7, also includes: a second splitting module 105, a second insertion module 106, a DC component judgment module 107, and a sliding window digital sum value calculation module 108.

[0110] The second splitting module 105 is configured to split each channel of second data into multiple DC control blocks.

[0111] The second inserting module 106 is configured to insert a DC control bit into each DC control block, wherein each channel of second data includes multiple rows, and each row includes a synchronization code.

[0112] Optionally, the second inserting module 106 inserts a DC control bit at the end of each DC control block.

[0113] The DC component determination module 107 is configured to determine whether the value of the DC control bit of each DC control block is the first value during modulation.

[0114] The modulation and coding module 104 is specifically used to encode multiple channels of second data starting from the first state if the parity of the sum of the preset first numerical quantities is an odd number, and adjust the numerical value on the polarity control bit to be the first numerical value through the processing module 103, so that the sum of the number of first numerical values ​​in each parallel area is an odd number, and the parallel area includes the second data of the corresponding path, a synchronization code, multiple DC control bits and a polarity control bit; if the parity of the sum of the preset first numerical quantities is an even number, then encode multiple channels of second data starting from the second state, and adjust the value on the polarity control bit to be the first numerical value through the processing module 103, so that the sum of the number of first numerical values ​​in each parallel area is an even number.

[0115] In one possible implementation, the sliding window digital sum value calculation module 108 is used to set a sliding window containing multiple DC control blocks, where the sliding window includes a sliding window of the current DC control block being modulated; a weight is set for each DC control block in the sliding window, and the weight of each DC control block is determined according to the position of each corresponding DC control block in the sliding window.

[0116] The DC component determination module 107 is specifically configured to obtain a current total DSV based on the DSV of the sliding window and the global DSV, wherein the current total DSV is used to determine the DC control block during modulation, the DSV of the sliding window is obtained based on the weights of the DC control blocks in the sliding window, and the global DSV is obtained based on the current DC control block.

[0117] In one possible implementation, the sliding window includes multiple DC control blocks, and the multiple DC control blocks included are determined based on the current DC control block. When the current DC control block changes, the DC control blocks included in the sliding window also change accordingly. The number of DC control blocks included in the sliding window can be determined based on the first data splitting rule.

[0118] In one possible implementation, the DC component determination module 107 is specifically configured to calculate the current total DSV for the first portion of each parallel region according to a first preset algorithm; and calculate the current total DSV for the second portion of each parallel region according to a second preset algorithm.

[0119] It should be understood that the modules shown in FIG9 are merely examples, including the first splitting module 101, the first insertion module 102, the processing module 103, the modulation and coding module 104, the second splitting module 105, the second insertion module 106, the DC component determination module 107, and the sliding window digital sum value calculation module 108. The operations thereof, or variations thereof, may be performed with reference to the method described in the embodiments of the present application. For example, the apparatus 10 may be adapted to perform the operations thereof, or variations thereof, in the method provided in FIG1 or FIG4 , and further description thereof will be omitted.

[0120] In addition, as shown in Figure 10, Figure 10 is a schematic diagram of the structure of a device 20 according to an embodiment of the present application. The device 20 shown in Figure 10 includes a transceiver unit 201 and a processing unit 202. The device 20 can be used to perform methods S101 to S103 or S201 to S203 in the above embodiments. When the device 20 is used to perform methods S101 to S103 or S201 to S203 in the above embodiments, the device 20 is equivalent to the apparatus exemplified in the method.

[0121] It should be noted that the division of units in the embodiments of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. For example, in the above embodiment, the transceiver unit 201 and the processing unit 202 can be the same unit or different units; the transceiver unit 201 and the processing unit 202 can be the same unit or different units. The above-mentioned integrated units can be implemented in the form of hardware, such as a chip, or in the form of software functional units.

[0122] In addition, an embodiment of the present application further provides a device 30, as shown in Figure 11, which is a structural diagram of the device 30 of an embodiment of the present application. The device 30 includes a communication interface 301 and a processor 302 connected to the communication interface 301. The communication interface 301 can be a device such as a transceiver. The communication interface 301 can be used to execute the method in the above embodiment, and the processor 302 can be used to split the first data into multiple second data; insert a polarity control bit into each second data after the split, and the value carried on the polarity control bit is used to adjust the number of first values ​​in the second data of the corresponding path to meet the parity of the preset sum of the first value number; according to the parity of the preset sum of the first value number, the multiple second data are modulated and encoded. Specifically, the communication interface 301 executes the operations for sending and receiving data in the method, and the processor 302 is used to perform operations other than the sending and receiving operations performed in the method provided in the above embodiment.

[0123] Optionally, the device may further include an encoder for performing modulation coding with reference to S103 and S201 - S203 .

[0124] In addition, an embodiment of the present application further provides a device 40, as shown in FIG12 , which is a schematic diagram of the structure of a device 40 provided in an embodiment of the present application. As shown in FIG12 , the device 40 may include a processor 401, a memory 402 coupled to the processor 401, and a transceiver 403. The transceiver 403 may be a communication interface, an optical module, etc., for receiving messages or data information. The processor 401 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and a NP, and is configured to execute the forwarding processing steps in the device exemplified in the above embodiment. The processor may also be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 401 may be a single processor or may include multiple processors. The memory 402 may include a volatile memory, such as a random-access memory (RAM); the memory may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the memory 402 may also include a combination of the above types of memory. The memory 402 may refer to a single memory or may include multiple memories for storing program instructions. In one embodiment, the memory 402 stores computer-readable instructions, which include multiple software modules, such as a sending module, a processing module, and a receiving module. After executing each software module, the processor 401 may perform corresponding operations according to the instructions of each software module. In this embodiment, the operation performed by a software module actually refers to the operation performed by the processor 401 according to the instructions of the software module. Optionally, the processor 401 may also store program codes or instructions for executing the embodiments of the present application. In this case, the processor 401 does not need to read the program codes or instructions from the memory 402.

[0125] The device 40 can be used to execute the method in the above embodiment. Specifically, the device 40 can be used as an apparatus to execute the operations of methods S101 to S103, or the device 40 can be used as an apparatus to execute the operations performed by the apparatus in methods S101 to S203. For example, the device 40 is used to split the first data into multiple channels of second data; insert a polarity control bit into each channel of the split second data, and the value carried by the polarity control bit is used to adjust the number of first values ​​in the second data of the corresponding channel to meet the parity of the preset sum of the number of first values; and modulate and encode the multiple channels of second data according to the parity of the preset sum of the number of first values.

[0126] An embodiment of the present application also provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is executed on a processor, it implements part or all of the operations in any of the methods in any of the aforementioned embodiments.

[0127] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed on a processor, implements part or all of the operations in any of the methods in any of the aforementioned embodiments.

[0128] The present application also provides a chip including an interface circuit and a processor connected to each other, wherein the processor is configured to cause the chip to execute part or all of the operations in any of the methods in any of the aforementioned embodiments.

[0129] An embodiment of the present application also provides a chip system, including: a processor, the processor is coupled to a memory, the memory is used to store programs or instructions, when the program or instructions are executed by the processor, the chip system implements part or all of the operations of any one of the methods of any one of the embodiments described above.

[0130] Optionally, there may be one or more processors in the chip system. The processor may be implemented in hardware or software. When implemented in hardware, the processor may be a logic circuit, an integrated circuit, etc. When implemented in software, the processor may be a general-purpose processor implemented by reading software code stored in a memory.

[0131] Optionally, the memory in the chip system may be one or more. The memory may be integrated with the processor or may be provided separately from the processor, which is not limited in the embodiments of the present application. For example, the memory may be a non-transient processor, such as a read-only memory (ROM), which may be integrated with the processor on the same chip or provided on different chips. The embodiments of the present application do not specifically limit the type of memory or the configuration of the memory and the processor.

[0132] Exemplarily, the chip system can be an FPGA, an ASIC, a system on chip (SoC), a CPU, an NP, a digital signal processing circuit (DSP), a microcontroller (MCU), a programmable logic device (PLD), or other integrated chips.

[0133] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0134] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0135] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical business division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0136] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0137] In addition, each business unit in each embodiment of the present application can be integrated into a processing unit, each unit can exist physically separately, or two or more units can be integrated into a single unit. The above-mentioned integrated units can be implemented in the form of hardware or software business units.

[0138] If the integrated unit is implemented in the form of a software business unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the technical solution of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, ROM, RAM, Random Access Memory, disk or optical disk, etc. Various media that can store program code.

[0139] Those skilled in the art will appreciate that, in one or more of the examples above, the services described herein may be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these services may be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one location to another. Storage media may be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0140] The above specific implementation methods further describe the purpose, technical solutions and beneficial effects of this application in detail. It should be understood that the above are only specific implementation methods of this application.

[0141] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for data modulation and coding, characterized in that: include: Splitting the first data into multiple second data; Inserting a polarity control bit into each of the split second data, wherein the value carried by the polarity control bit is used to adjust the number of first values ​​in the second data of the corresponding path to meet the parity of the sum of the preset first value number; The multiple channels of second data are modulated and encoded according to the parity of the sum of the preset first numerical quantities.

2. The method according to claim 1, characterized in that: The modulating and encoding the multiple paths of second data according to the parity of the sum of the preset first numerical quantities comprises: Splitting each of the second data into a plurality of DC component control blocks, and inserting a DC component control bit into each of the DC component control blocks, wherein each of the second data includes a plurality of rows, and each row includes a synchronization code; During modulation, a judgment is made on each of the DC component control blocks to determine whether the value on the DC component control bit of each of the DC component control blocks is the first value; If the parity of the sum of the number of the preset first values ​​is an odd number, the plurality of second data are encoded starting from the first state, and by adjusting whether the value on the polarity control bit is the first value, the sum of the number of the first values ​​in each parallel region is an odd number, and the parallel region includes the second data of the corresponding path, the synchronization code, the plurality of DC component control bits and the polarity control bit; If the parity of the sum of the preset first numerical values ​​is an even number, the multiple second data are encoded starting from the second state, and by adjusting whether the value on the polarity control bit is the first numerical value, the sum of the first numerical values ​​in each parallel area is an even number.

3. The method according to claim 1 or 2, characterized in that: Also includes: Setting a sliding window including a plurality of DC component control blocks, wherein the sliding window includes the DC component control block currently being modulated; Setting a weight for each of the DC component control blocks in the sliding window, wherein the weight of each of the DC component control blocks is determined according to a position of each of the corresponding DC component control blocks in the sliding window; A current total digital sum value is obtained according to the digital sum value of the sliding window and the global digital sum value, wherein the current total digital sum value is used for the modulation, the digital sum value of the sliding window is obtained according to the weights of each DC component control block in the sliding window, and the global digital sum value is obtained according to the current DC component control block.

4. The method according to claim 3, characterized in that The plurality of DC component control blocks included in the sliding window are determined according to the current DC component block.

5. The method according to claim 3 or 4, characterized in that: The step of obtaining the current total digital sum value according to the weight of each DC component control block in the sliding window and the global digital sum value comprises: For the first part of each parallel region, the current total digital sum value is calculated according to a first preset algorithm; for the second part of each parallel region, the current total digital sum value is calculated according to a second preset algorithm.

6. A device, characterized in that: include: A first splitting module, used for splitting the first data into multiple second data; A first inserting module, used for inserting a polarity control bit into each of the split second data, wherein the value carried by the polarity control bit is used for adjusting the number of first values ​​in the second data of the corresponding path to meet the parity of the sum of the preset first value number, and the value is determined by the processing module; The modulation and coding module is used to modulate and code the multiple channels of second data according to the parity of the sum of the preset first numerical quantities.

7. The device according to claim 6, characterized in that Also includes: A second splitting module, used for splitting each channel of the second data into a plurality of DC component control blocks; A second inserting module, configured to insert a DC component control bit into each of the DC component control blocks, wherein each of the second data includes a plurality of rows, and each row includes a synchronization code; a DC component determination module, used for determining each of the DC component control blocks during modulation to determine whether the value on the DC component control bit of each of the DC component control blocks is the first value; The modulation and coding module is specifically used to encode the multiple second data from the first state if the parity of the sum of the preset first numerical quantities is an odd number, and to adjust whether the numerical value on the polarity control bit is the first numerical value so that the sum of the first numerical quantities in each parallel region is an odd number, and the parallel region includes the second data of the corresponding path, the synchronization code, the multiple DC component control bits and the polarity control bit; if the parity of the sum of the preset first numerical values ​​is an even number, the multiple second data are encoded starting from the second state, and by adjusting whether the value on the polarity control bit is the first numerical value, the sum of the first numerical values ​​in each parallel area is an even number.

8. The device according to claim 6 or 7, characterized in that Also includes: A sliding window digital sum value calculation module, used for setting a sliding window including a plurality of DC component control blocks, wherein the sliding window includes the DC component control block currently being modulated; Setting a weight for each of the DC component control blocks in the sliding window, wherein the weight of each of the DC component control blocks is determined according to a position of each of the corresponding DC component control blocks in the sliding window; The DC component judgment module is specifically used to obtain a current total digital sum value based on the digital sum value of the sliding window and the global digital sum value, wherein the current total digital sum value is used for the modulation, the digital sum value of the sliding window is obtained based on the weights of each DC component control block in the sliding window, and the global digital sum value is obtained based on the current DC component control block.

9. The device according to claim 8, characterized in that The plurality of DC component control blocks included in the sliding window are determined according to the current DC component block.

10. The device according to claim 8 or 9, characterized in that The DC component determination module is specifically used to calculate the first part of each parallel region according to a first preset algorithm to obtain the current total digital sum value; For the second part of each parallel region, the current total digital sum value is calculated according to a second preset algorithm.

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