Data interaction system and method, large-scale operation processing method, device and medium

Abstract

The present application relates to the technical field of communications, and in particular relates to a data interaction system and method, a large-scale operation processing method, a device and a medium. The system comprises: a first processor and a second processor, configured to respectively execute different data operations so as to generate operation results and operation completion indications; a first memory, configured to store the operation results; and a read / write controller, connected to the first processor, the second processor and the first memory, the read / write controller being internally provided with a second memory configured to store the operation completion indications and storage information of the operation results in the first memory. The read / write controller is configured to gate the first memory to communicate with a processor generating an operation result, such that the processor writes the operation result into the first memory, and when the read / write controller detects that an operation completion indication and storage information are written into the second memory, to gate the first memory to communicate with the other processor so as to read the operation result from the first memory. The solution of the present application significantly improves data interaction efficiency.

Description

Data interaction system, method, large-scale computing processing method, device and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 25, 2023, with application number 202310915197.0, and application name “Data interaction system, method, large-scale computing processing method, equipment and medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of communication technology, and in particular to a data interaction system, method, large-scale computing processing method, device and medium. Background Art

[0004] With the rapid development of new technologies, algorithms in fields such as artificial intelligence and genetic analysis are becoming increasingly large in scale. Due to resource constraints, these algorithms are being split across multiple processors. This split reduces the complexity of implementing the algorithm on each processor and improves overall efficiency. For confidential algorithms, these algorithms are also split across multiple processors to maintain confidentiality. Because different algorithms may utilize data generated by other algorithms, data exchange between different processors is necessary.

[0005] Currently, the traditional method for processor data exchange is to insert a dual-port RAM (Random Access Memory) chip (also known as DPRAM) between the two processors, as shown in Figure 1. The implementation principle is as follows: CPU (Central Processing Unit) 1 and CPU2 agree that a portion of the DPRAM space is designated as control space (the gray area in Figure 1), and the remainder is designated as data space. CPU1 / CPU2 monitors information in the control space to understand the data in the data space, thereby ensuring proper operation. For example, if CPU1 wants to transfer some data to CPU2, CPU1 first writes the data to a section of the DPRAM address space, then writes a 1 to the CPU1 output control register and the starting address and data length to the corresponding register. After CPU2 detects the 1 written to the control register, it reads the starting address and data length information and, based on this information, reads the data from the corresponding address space in the DPRAM. However, this traditional processor data exchange method has the following drawbacks: due to the limited capacity of the DPRAM, the amount of data exchanged is relatively small. When the amount of data that needs to be exchanged is relatively large, the processor needs to write data and control information to DPRAM multiple times, which is not only inefficient but also wastes processor resources. Therefore, improvement is urgently needed.

[0006] Summary of the Invention

[0007] In view of this, it is necessary to provide a data interaction system, method, large-scale computing processing method, device and medium to address the above technical problems.

[0008] According to a first aspect of the present application, a data interaction system is provided, the system comprising:

[0009] A first processor and a second processor, the first processor and the second processor are configured to respectively perform data operations to generate operation results and operation completion indications;

[0010] a first memory configured to store operation results;

[0011] A read-write controller, the read-write controller is connected to the first processor, the second processor and the first memory respectively, and the read-write controller has a built-in second memory, and the second memory is configured to store an operation completion indication and storage information of the operation result in the first memory;

[0012] The read-write controller is configured to enable the first memory to communicate with the processor that generates the operation result, wherein the processor that generates the operation result is configured to write the operation result to the first memory after the communication with the first memory is enabled; and to enable the first memory to communicate with another processor when the read-write controller detects an operation completion indication and storage information is written to the second memory, wherein the other processor is configured to read the operation result from the first memory based on the storage information in the second memory after the communication with the first memory is enabled.

[0013] In some embodiments, the read / write controller includes a first PCIe endpoint and a second PCIe endpoint;

[0014] The first PCIe endpoint is connected to the PCIe root complex of the first processor, and the second PCIe endpoint is connected to the PCIe root complex of the second processor.

[0015] In some embodiments, the read / write controller further includes a strobe control unit;

[0016] The gating control unit is connected to the first PCIe endpoint, the second PCIe endpoint and the first memory respectively. The gating control unit is configured to enable the first processor to access the first memory through the first PCIe endpoint, or to enable the second processor to access the first memory through the second PCIe endpoint.

[0017] In some embodiments, the read / write controller further comprises an internal logic unit, and the second memory comprises a first port, a second port, and a third port;

[0018] The first port is connected to the first PCIe endpoint, the second port is connected to the second PCIe endpoint, the third port is connected to the internal logic unit, and the internal logic unit is further connected to the first PCIe endpoint and the second PCIe endpoint respectively.

[0019] In some embodiments, the first processor is configured to:

[0020] executing a first operation to generate a first operation result, and generating a first operation completion indication when the execution of the first operation is completed, wherein the data operation executed by the first processor includes the first operation;

[0021] Sending a communication request to the gating control unit to write the first operation result into the first memory through the first PCIe endpoint, and obtaining the starting address and data length of the first operation result in the first memory to obtain first storage information;

[0022] The first storage information and the first operation completion indication are respectively written into the preset addresses of the second memory.

[0023] In some embodiments, the internal logic unit is configured to:

[0024] Performing cyclic detection on a preset address of the second memory;

[0025] In response to writing the first operation completion indication into the preset address, a communication request is sent to the gating control unit to send a first interrupt to the second processor through the second PCIe endpoint.

[0026] In some embodiments, the second processor is configured to:

[0027] In response to receiving the first interrupt, checking the interrupt source of the first interrupt to read the starting address and data length of the first operation result from a preset address in the second memory;

[0028] A communication request is sent to the gating control unit to read the first operation result from the first memory through the second PCIe endpoint based on the start address and data length of the first operation result.

[0029] In some embodiments, the second processor is further configured to:

[0030] performing a second operation on the first operation result to generate a second operation result, and generating a second operation completion indication when the second operation is completed, wherein the data operation performed by the second processor includes the second operation;

[0031] Sending a communication request to the gating control unit to write the second operation result into the first memory through the second PCIe endpoint, and obtaining the starting address and data length of the second operation result in the first memory to obtain second storage information;

[0032] The second storage information and the second operation completion indication are respectively written into the preset addresses of the second memory.

[0033] In some embodiments, the internal logic unit is further configured to:

[0034] In response to writing the second operation completion indication into the preset address, a second interrupt is sent to the first processor through the first PCIe endpoint.

[0035] In some embodiments, the first processor is further configured to:

[0036] In response to receiving the second interrupt, checking the interrupt source of the second interrupt to read the starting address and data length of the second operation result from a preset address in the second memory;

[0037] A communication request is sent to the gating control unit to read the second operation result from the first memory through the first PCIe endpoint based on the start address and data length of the second operation result, and a subsequent operation is performed based on the second operation result.

[0038] In some embodiments, the gating control unit is configured to:

[0039] placing the communication requests sent by the first processor and the second processor into a queue in chronological order;

[0040] Communication requests are sequentially taken out from the queue, and based on the communication requests, the first memory is connected to the first PCIe endpoint or the first memory is connected to the second PCIe endpoint.

[0041] In some embodiments, the gating control unit is further configured to:

[0042] In response to the sender of the communication request being the first processor, enabling the connection between the first memory and the first PCIe endpoint;

[0043] In response to the second processor being the sender of the communication request, the first memory is enabled to be connected to the second PCIe endpoint.

[0044] In some embodiments, the read / write controller is implemented using a field programmable gate array.

[0045] In some embodiments, the gating control unit is a crossbar switching unit.

[0046] In some embodiments, the first processor and the second processor are both selected from any one of a central processing unit, a graphics processing unit, and an application-specific integrated circuit.

[0047] In some embodiments, the first memory is a double data rate synchronous dynamic random access memory (DDRSDRAM), and the second memory is a random access memory (RAM).

[0048] In some embodiments, the system further comprises a third memory;

[0049] The third memory is connected to the first processor. The third memory is a double data rate synchronous dynamic random access memory and is configured to store data involved in calculation when the first processor performs operations.

[0050] In some embodiments, the system further includes a fourth memory;

[0051] The fourth memory is connected to the second processor. The fourth memory is a double data rate synchronous dynamic random access memory and is configured to store data involved in calculation when the second processor performs operations.

[0052] According to a second aspect of the present application, a data interaction method is provided, the data interaction method comprising:

[0053] performing data operations using the first processor and the second processor;

[0054] In response to a processor generating an operation result and an operation completion indication, sending a communication request to the read-write controller;

[0055] The read / write controller selects the first memory to communicate with the processor that generates the operation result based on the communication request;

[0056] The processor generating the operation result is configured to store the operation result in the first memory after communication with the first memory is enabled, and store the operation completion indication and the storage information of the operation result in the first memory in the second memory built into the read-write controller; and

[0057] In response to the read / write controller detecting an operation completion indication and storage information being written to the second memory, the first memory is enabled to communicate with another processor, wherein the other processor is configured to read the operation result from the first memory based on the storage information in the second memory after communication with the first memory is enabled.

[0058] According to a third aspect of the present application, a large-scale operation processing method is provided, wherein the large-scale operation includes a first operation and a second operation that uses the result of the first operation to participate in the calculation, and the method includes:

[0059] The first processor and the second processor of the above data interaction system process the first operation and the second operation respectively, and exchange operation results between the two to perform subsequent operations based on the exchanged operation results.

[0060] According to a fourth aspect of the present application, an electronic device is further provided, comprising:

[0061] at least one processor; and

[0062] The memory stores a computer program that can be run on the processor, and the processor executes the above-mentioned data interaction method when executing the program.

[0063] According to a fifth aspect of the present application, a computer non-volatile readable storage medium is further provided, wherein the computer non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the aforementioned data interaction method is executed.

[0064] The above-mentioned data interaction system sets a read-write controller between the first processor and the second processor, uses the read-write controller to mount the first processor to store the calculation results, and uses the second memory built into the read-write controller to store the storage information of the calculation results and the calculation completion indication. By detecting the calculation completion indication, the first processor and the second processor are alternately connected to the first memory, and there is no need for the first processor and the second processor to perform data read and write control operations, which saves computing resources, significantly improves data interaction efficiency, and has better versatility.

[0065] In addition, the present application also provides a data interaction method, a large-scale computing processing method, an electronic device and a computer non-volatile readable storage medium, which can also achieve the above-mentioned technical effects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0067] Figure 1 is a schematic diagram of a traditional processor data interaction implementation method;

[0068] FIG2 is a schematic diagram of the structure of a data interaction system provided by one embodiment of the present application;

[0069] FIG3 is a schematic diagram of the structure of another data interaction system provided by an embodiment of the present application;

[0070] FIG4 is a schematic diagram showing the connection of a second memory built into a read / write controller according to an embodiment of the present application;

[0071] FIG5 is a schematic structural diagram of a data interaction system with dual central processing units provided by one embodiment of the present application;

[0072] FIG6 is a schematic diagram of algorithm allocation for dual central processing units provided in one embodiment of the present application;

[0073] FIG7 is a flow chart of a data interaction method provided in another embodiment of the present application;

[0074] FIG8 is a diagram showing the internal structure of an electronic device provided in another embodiment of the present application;

[0075] FIG9 is a structural diagram of a computer non-volatile readable storage medium provided in another embodiment of the present application. DETAILED DESCRIPTION

[0076] In order to make the objectives, technical solutions and advantages of this application more clear, the embodiments of this application are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0077] It should be noted that all expressions using "first" and "second" in the embodiments of this application are for the purpose of distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of this application. Subsequent embodiments will not explain this one by one.

[0078] In one embodiment, as shown in FIG2 , the present application provides a data interaction system 100 , which includes:

[0079] The first processor 110 and the second processor 120 are configured to respectively perform different data operations to generate operation results and operation completion indications;

[0080] In this embodiment, the first processor and the second processor can be existing chips configured to perform data operations, such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor / micro controller unit (MPU / MCU), a neural network processor (NPU), a tensor processing unit (TPU), and an application-specific integrated circuit (ASIC). It should be noted that the first processor 110 and the second processor 120 can be the same chip or different chips, such as the first processor 110 and the second processor 120 can both be CPUs, or the first processor 110 is a CPU and the second processor 120 is an ASIC. In this embodiment, the data operation can be data addition, data multiplication, data inversion, etc. The data operation can also be a certain data processing operation in the encryption and decryption process. In the specific implementation process, the data operations performed by the first processor 110 and the second processor 120 can be allocated according to the application scenario and processing tasks. The data operations performed by the above-mentioned first processor and the second processor are different data operations.

[0081] The first memory 130 is configured to store calculation results; wherein the first memory 130 is preferably a direct access memory (Direct Memory Assess, abbreviated as DAM). The capacity of the first memory can be selected according to the size of the calculated interaction data or the interaction scenario requirements. For example, the capacity size can be set according to the maximum data that needs to be transmitted by the first processor 110 and the second processor 120 during data interaction. In order to ensure that the exchanged data can be completed in one interaction, the capacity of the first memory can usually be set relatively large.

[0082] A read / write controller 140, which is connected to the first processor 110, the second processor 120, and the first memory 130, respectively. The read / write controller 140 has a built-in second memory 141, which is configured to store a calculation completion indication and storage information of the calculation result in the first memory 130;

[0083] In this embodiment, second memory 142 is preferably a random access memory (RAM). Since second memory 141 stores information related to computation results, the capacity of second memory 141 can be smaller than that of first memory 130. The computation completion indication can be represented by a single binary number. For example, after the processor completes the computation, it generates a signal and assigns a value of "1" to indicate computation completion. It should be noted that the specific form and value assignment of the computation completion indication in this embodiment are for illustrative purposes only.

[0084] The read-write controller 140 is configured to enable the first memory 130 to communicate with the processor that generates the operation result (referred to as the target processor), wherein the target processor is configured to write the operation result to the first memory 130 after the communication with the first memory is enabled; and to enable the first memory to communicate with another processor when the read-write controller 140 detects the operation completion indication and the storage information is written to the second memory 141, wherein the other processor is configured to read the operation result from the first memory 130 based on the storage information in the second memory 141 after the communication with the first memory is enabled.

[0085] In this embodiment, the target processor refers to the processor that generates the operation result, that is, the processor that generates the data to be exchanged, and the other processor refers to the processor that needs to obtain the exchanged data. The first processor 110 and the second processor 120 can both become target processors. For example, three operations 1, 2, and 3 are executed sequentially. The three operations are executed in sequence. Operation 2 requires the execution result of Operation 1, and Operation 3 requires the execution result of Operation 2. It is assumed that the first processor 110 executes Operation 1 and Operation 3, and the second processor 120 executes Operation 2. Then when the first processor 110 completes Operation 1, the first processor 110 is the target processor. Similarly, when the second processor 120 obtains the execution result of Operation 1 and executes Operation 2 and completes it, the second processor becomes the new target processor.

[0086] The above-mentioned data interaction system sets a read-write controller between the first processor and the second processor, uses the read-write controller to mount the first processor to store the calculation results, and uses the second memory built into the read-write controller to store the storage information of the calculation results and the calculation completion indication. By detecting the calculation completion indication, the first processor and the second processor are alternately connected to the first memory, and there is no need for the first processor and the second processor to perform data read and write control operations, which saves computing resources, significantly improves data interaction efficiency, and has better versatility.

[0087] In some embodiments, referring to FIG. 3 , the read / write controller 140 is constructed using a field programmable gate array.

[0088] In some embodiments, in order to facilitate understanding of the solution of the present application, the read-write controller using a field programmable gate array (FPGA) is used as an example for explanation. The connection relationship and function of the first controller 210, the second controller 220, and the first memory 240 refer to the definitions of the first processor 110, the second processor 120, and the first memory 140 in Figure 2. The read-write controller 140 of this embodiment has a built-in second memory 241 (refer to the definition of the second memory 130 in Figure 2), and the read-write controller 240 includes a first PCIe endpoint 242 and a second PCIe endpoint 243; wherein the PCIe endpoint is the End Point (EP for short).

[0089] The first PCIe endpoint 242 is connected to the PCIe root complex 211 of the first processor, and the second PCIe endpoint 243 is connected to the PCIe root complex 221 of the second processor. The PCIe root complex is also known as Root Complex (RC).

[0090] In some embodiments, please continue to refer to FIG. 3 , the read / write controller 240 further includes a strobe control unit 244 ;

[0091] The gating control unit 244 is connected to the first PCIe endpoint 242, the second PCIe endpoint 243 and the first memory 230 respectively. The gating control unit 244 is configured to enable the first processor 210 to access the first memory 230 through the first PCIe endpoint 242, or to enable the second processor 220 to access the first memory 230 through the second PCIe endpoint 243.

[0092] In some embodiments, as shown in FIG. 4 , the read / write controller 240 further includes an internal logic unit 245 , and the second memory includes a first port 2411 , a second port 2412 , and a third port 2413 ;

[0093] The first port 2411 is connected to the first PCIe endpoint 242 , the second port 2412 is connected to the second PCIe endpoint 243 , and the third port 2413 is connected to the internal logic unit 245 . The internal logic unit 245 is also connected to the first PCIe endpoint 242 and the second PCIe endpoint 243 , respectively.

[0094] In some embodiments, referring to FIG. 3 and FIG. 4 , the first processor 210 is configured to:

[0095] executing a first operation to generate a first operation result, and generating a first operation completion indication when the execution of the first operation is completed, wherein the data operation executed by the first processor includes the first operation;

[0096] Sending a communication request to the gating control unit 244 to write the first operation result into the first memory 230 through the first PCIe endpoint 242, and obtaining the starting address and data length of the first operation result in the first memory 230 to obtain first storage information;

[0097] The first storage information and the first operation completion indication are written into preset addresses of the second memory 241 respectively.

[0098] In some embodiments, referring to FIG. 3 and FIG. 4 , the internal logic unit 250 is configured as follows:

[0099] Performing cyclic detection on the preset address of the second memory 230;

[0100] In response to writing the first operation completion indication into the preset address, a communication request is sent to the strobe control unit 244 to send a first interrupt to the second processor 220 through the second PCIe endpoint 243 .

[0101] In some embodiments, referring to FIG. 3 and FIG. 4 , the second processor 220 is configured to:

[0102] In response to receiving the first interrupt, checking the interrupt source of the first interrupt to read the starting address and data length of the first operation result from a preset address in the second memory 230;

[0103] A communication request is sent to the gating control unit 244 to read the first operation result from the first memory 230 through the second PCIe endpoint 243 based on the start address and data length of the first operation result.

[0104] In some embodiments, as shown in FIG. 3 , the second processor 220 is further configured to:

[0105] performing a second operation on the first operation result to generate a second operation result, and generating a second operation completion indication when the second operation is completed, wherein the data operation performed by the second processor includes the second operation;

[0106] Sending a communication request to the gating control unit 244 to write the second operation result into the first memory 230 through the second PCIe endpoint 243, and obtaining the starting address and data length of the second operation result in the first memory 230 to obtain second storage information;

[0107] The second storage information and the second operation completion indication are written into the preset addresses of the second memory 241 respectively.

[0108] In some embodiments, as shown in FIG3 , the internal logic unit 245 is further configured as follows:

[0109] In response to the second operation completion indication being written into the preset address, a second interrupt is sent to the first processor 210 via the first PCIe endpoint 242 .

[0110] In some embodiments, the first processor 210 is further configured to:

[0111] In response to receiving the second interrupt, checking the interrupt source of the second interrupt to read the starting address and data length of the second operation result from a preset address in the second memory 230;

[0112] A communication request is sent to the gating control unit 244 to read the second operation result from the first memory through the first PCIe endpoint 242 based on the start address and data length of the second operation result, and subsequent operations are performed based on the second operation result.

[0113] In some embodiments, the gating control unit 244 is configured to:

[0114] Put the communication requests sent by the first processor 210 and the second processor 220 into a queue in chronological order;

[0115] The communication requests are sequentially taken out from the queue, and based on the communication request, the first memory 230 is selected to be connected to the first PCIe endpoint 242 or the first memory 230 is selected to be connected to the second PCIe endpoint 243 .

[0116] In some embodiments, the gating control unit 244 is further configured to:

[0117] In response to the sender of the communication request being the first processor 210, the first memory 230 is enabled to connect to the first PCIe endpoint 242;

[0118] In response to the second processor 220 sending the communication request, the first memory 230 is enabled to connect to the second PCIe endpoint 243 .

[0119] In some embodiments, the gating control unit is a Crossbar switching unit, wherein the Crossbar is generally provided by an FPGA manufacturer and is an IP module capable of connecting multiple AXI-4 interfaces.

[0120] In some embodiments, the first processor and the second processor are both selected from any one of a central processing unit, a graphics processing unit, and an application-specific integrated circuit.

[0121] In some embodiments, the first memory is a double data rate synchronous dynamic random access memory, and the second memory is a random access memory. Preferably, the first memory can be DDR4

[0122] In some embodiments, please refer to FIG5 , the system further includes a third memory 250 ;

[0123] The third memory 250 is connected to the first processor 210. The third memory 250 is a double data rate synchronous dynamic random access memory and is configured to store data involved in calculation when the first processor 210 performs operations.

[0124] In some embodiments, please continue to refer to FIG. 5 , the system further includes a fourth memory 260 ;

[0125] The fourth memory 260 is connected to the second processor 220. The fourth memory 260 is a double data rate synchronous dynamic random access memory and is configured to store data involved in calculation when the second processor 220 performs operations.

[0126] In another embodiment, to facilitate understanding of the solution of the present application, the following example uses a dual-CPU encryption operation scenario as an example. Referring again to FIG5 , this embodiment proposes a data exchange system that uses an FPGA PCIe channel combined with DDR4 to solve the dual-CPU data exchange problem. The overall architecture of the system includes the following parts:

[0127] CPU1 and CPU2, the PCIe Root Complex ends carried by CPU1 and CPU2 are denoted as RC1 and RC2 respectively;

[0128] FPAG includes the following components: two PCIe endpoints with DMA functions provided by the FPGA manufacturer, denoted as EP1 and EP2, respectively. EP1 is connected to RC1, and EP2 is connected to RC2; a triple-port random access memory (TPRAM), which can support three independent read and write ports and is used to control the data exchange process; an internal logic unit, which is configured with the FPGA's internal processing logic for the CPU algorithm; and a crossbar, which is an IP module that can connect multiple AXI-4 interfaces. The crossbar can be provided by the FPGA manufacturer. The three ports of the TPRAM are connected to EP1, EP2, and the internal logic unit, respectively. The internal logic unit is also connected to EP1 and EP2.

[0129] Three DDR4s, one DDR4 is mounted on the FPGA through the Crossbar and is recorded as DDR4 1. The Crossbar is also connected to EP1 and EP2 respectively. DDR41 can be connected to both the CPU and CPU2. The other two DDR4s are mounted on CPU1 and CPU2 respectively and are recorded as DDR4 2 and DDR4 3.

[0130] The following describes in detail how the system works:

[0131] In step 1, CPU1 and CPU2 determine the algorithm partitioning and data interaction process, as shown in Figure 6. Assuming that the encryption algorithm includes 2n operations executed sequentially, and the subsequent operations all depend on the results of the previous operations, the operations in odd order can be assigned to CPU1 for execution, and the operations in even order can be assigned to CPU2 for execution. In this way, CPU1 and CPU2 will repeatedly perform data interaction.

[0132] Step 2: After the algorithm completes node 1, CPU1 transfers the intermediate data completed by the algorithm to DDR4 1 connected to the FPGA through the DMA process.

[0133] Step 3: CPU 1 writes the instruction information completed by algorithm node 1, the starting position of the processed data stored in DDR4 1, and the total data length into the predefined address of TPRAM.

[0134] Step 4: After detecting the completion indication information of CPU1 node 1, the internal logic unit sets the corresponding interrupt indication information and sends an interrupt to CPU2.

[0135] Step 5: After receiving the interrupt, CPU2 checks the interrupt source, reads the starting address and data length of CPU1 node 1 data in TPRAM, and reads the data into CPU2 through DMA for processing or application.

[0136] Step 6: After CPU2 completes data processing, it transfers the data completed by CPU2 algorithm node 1 to DDR4 1 connected to FPGA through DMA.

[0137] In step seven, CPU2 writes the completion indication of algorithm node 1, the starting position of the data on DDR4 1, and the total length of the data into the corresponding position of CPU2 node 1 in TPRAM.

[0138] Step 8: After detecting the completion indication information of CPU2 node 1, the internal logic unit sets corresponding interrupt indication information and sends an interrupt to CPU1.

[0139] Step 9: After receiving the interrupt, CPU1 checks the interrupt source, reads the starting address and data length of CPU2 node 1 data in TPRAM, and reads the data into CPU1 through DMA for processing or application.

[0140] Step 10: Based on the division of the algorithms, the above steps can be repeated until all algorithms are executed.

[0141] A data interaction system of this embodiment has at least the following beneficial technical effects: through a dual-port PCIe FPGA device, two CPU systems can work together, with good versatility; in addition, data interaction efficiency is improved through DMA interaction data, and at the same time, the large DDR4 capacity on the FPGA can exchange large amounts of data at one time, which can be applied to large algorithm models or used to protect algorithms.

[0142] In another embodiment, referring to FIG. 7 , this embodiment provides a data interaction method 300, which includes the following steps:

[0143] Step 301, using a first processor and a second processor to perform different data operations;

[0144] Step 302, in response to a processor generating a calculation result and a calculation completion indication, sending a communication request to the read / write controller;

[0145] Step 303: The read / write controller enables the first memory to communicate with the processor that generates the operation result based on the communication request;

[0146] Step 304: The processor generating the operation result is configured to store the operation result in the first memory after communication with the first memory is enabled, and store the operation completion indication and storage information of the operation result in the first memory in the second memory built into the read-write controller;

[0147] Step 305, in response to the read-write controller detecting the operation completion indication and the storage information being written to the second memory, the first memory is enabled to communicate with another processor, wherein the other processor is configured to read the operation result from the first memory based on the storage information in the second memory after the communication with the first memory is enabled.

[0148] The above-mentioned data interaction method sets a read-write controller between the first processor and the second processor, uses the read-write controller to mount the first processor to store the calculation results, and uses the second memory built into the read-write controller to store the storage information of the calculation results and the calculation completion indication. By detecting the calculation completion indication, the first processor and the second processor are alternately connected to the first memory, and there is no need for the first processor and the second processor to perform data read and write control operations, which saves computing resources, significantly improves data interaction efficiency, and has better versatility.

[0149] It should be noted that the specific limitations on the data interaction method can be found in the above limitations on the data interaction system, which will not be repeated here.

[0150] In another embodiment, the present application also provides a large-scale operation processing method, the large-scale operation includes a first operation and a second operation that uses the execution result of the first operation to participate in the calculation, the method includes: the first processor and the second processor of the data interaction system of the above embodiment respectively process the first operation and the second operation, and exchange the operation results between the two to perform subsequent operations based on the exchanged operation results.

[0151] According to another aspect of the present application, an electronic device is provided, which may be a server, and its internal structure diagram is shown in FIG8 . The electronic device includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the electronic device is configured to provide computing and control capabilities. The memory of the electronic device includes a non-volatile readable storage medium and an internal memory. The non-volatile readable storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile readable storage medium. The database of the electronic device is configured to store data. The network interface of the electronic device is configured to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the above data interaction method is implemented, including the following steps:

[0152] performing different data operations using the first processor and the second processor;

[0153] In response to a processor generating an operation result and an operation completion indication, sending a communication request to the read-write controller;

[0154] The read / write controller selects the first memory to communicate with the target processor generating the operation result based on the communication request;

[0155] The target processor stores the operation result in the first memory, and stores the operation completion indication and the storage information of the operation result in the first memory in the second memory built into the read-write controller;

[0156] In response to the read / write controller detecting an operation completion indication and storage information being written to the second memory, the first memory is enabled to communicate with another processor, wherein the other processor is configured to read the operation result from the first memory based on the storage information in the second memory after communication with the first memory is enabled.

[0157] According to another aspect of the present application, a computer-readable non-volatile storage medium is provided, as shown in FIG9 , on which a computer program is stored. When the computer program is executed by a processor, the above data interaction method is implemented, including performing the following steps:

[0158] performing different data operations using the first processor and the second processor;

[0159] In response to a processor generating an operation result and an operation completion indication, sending a communication request to the read-write controller;

[0160] The read / write controller selects the first memory to communicate with the target processor generating the operation result based on the communication request;

[0161] The target processor stores the operation result in the first memory, and stores the operation completion indication and the storage information of the operation result in the first memory in the second memory built into the read-write controller;

[0162] In response to the read / write controller detecting an operation completion indication and storage information being written to the second memory, the first memory is enabled to communicate with another processor, wherein the other processor is configured to read the operation result from the first memory based on the storage information in the second memory after communication with the first memory is enabled.

[0163] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0164] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0165] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A data interaction system, characterized in that: The system comprises: A first processor and a second processor, wherein the first processor and the second processor are configured to respectively perform data operations to generate operation results and operation completion indications; a first memory, wherein the first memory is configured to store the operation result; A read-write controller, the read-write controller is connected to the first processor, the second processor and the first memory respectively, the read-write controller has a built-in second memory, and the second memory is configured to store the operation completion indication and storage information of the operation result in the first memory; The read-write controller is configured to: enable the first memory to communicate with the processor that generates the operation result, wherein the processor that generates the operation result is configured to write the operation result to the first memory after the communication with the first memory is enabled; and enable the first memory to communicate with another processor when the read-write controller detects the operation completion indication and the storage information is written to the second memory, wherein the other processor is configured to read the operation result from the first memory based on the storage information in the second memory after the communication with the first memory is enabled.

2. The data interaction system according to claim 1, characterized in that: The read / write controller includes a first PCIe endpoint and a second PCIe endpoint; The first PCIe endpoint is connected to a PCIe root complex of a first processor, and the second PCIe endpoint is connected to a PCIe root complex of a second processor.

3. The data interaction system according to claim 2, characterized in that: The read-write controller also includes a gating control unit; The gating control unit is connected to the first PCIe endpoint, the second PCIe endpoint and the first memory respectively, and the gating control unit is configured to enable the first processor to access the first memory through the first PCIe endpoint, or to enable the second processor to access the first memory through the second PCIe endpoint.

4. The data interaction system according to claim 3, characterized in that: The read-write controller further includes an internal logic unit, and the second memory includes a first port, a second port, and a third port; The first port is connected to the first PCIe endpoint, the second port is connected to the second PCIe endpoint, the third port is connected to the internal logic unit, and the internal logic unit is also connected to the first PCIe endpoint and the second PCIe endpoint respectively.

5. The data interaction system according to claim 4, characterized in that: The first processor is configured to: executing a first operation to generate a first operation result, and generating a first operation completion indication when the first operation is completed, wherein the data operation performed by the first processor includes the first operation; Sending a communication request to the gating control unit to write the first operation result into the first memory through the first PCIe endpoint, and acquiring a starting address and a data length of the first operation result in the first memory to obtain first storage information; The first storage information and the first operation completion indication are respectively written into preset addresses of the second memory.

6. The data interaction system according to claim 5, characterized in that: The internal logic unit is configured as: Performing cyclic detection on the preset address of the second memory; In response to writing a first operation completion indication into the preset address, sending a communication request to the gating control unit to send a first interrupt to the second processor through the second PCIe endpoint.

7. The data interaction system according to claim 6, characterized in that: The second processor is configured to: In response to receiving a first interrupt, checking an interrupt source of the first interrupt to read a starting address and a data length of the first operation result from a preset address of the second memory; A communication request is sent to the gating control unit to read the first operation result from the first memory through the second PCIe endpoint based on the starting address and data length of the first operation result.

8. The data interaction system according to claim 7, characterized in that: The second processor is further configured to: performing a second operation on the first operation result to generate a second operation result, and generating a second operation completion indication when the second operation is completed, wherein the data operation performed by the second processor includes the second operation; Sending a communication request to the gating control unit to write the second operation result into the first memory through the second PCIe endpoint, and acquiring a starting address and a data length of the second operation result in the first memory to obtain second storage information; The second storage information and the second operation completion indication are respectively written into preset addresses of the second memory.

9. The data interaction system according to claim 8, characterized in that: The internal logic unit is further configured to: In response to writing a second operation completion indication into the preset address, sending a second interrupt to the first processor through the first PCIe endpoint.

10. The data interaction system according to claim 9, characterized in that: The first processor is further configured to: In response to receiving a second interrupt, checking an interrupt source of the second interrupt to read a starting address and a data length of the second operation result from a preset address of the second memory; A communication request is sent to the gating control unit to read the second operation result from the first memory through the first PCIe endpoint based on the starting address and data length of the second operation result, and a subsequent operation is performed based on the second operation result.

11. The data interaction system according to claim 10, characterized in that: The gating control unit is further configured to: Put the communication requests sent by the first processor and the second processor into a queue in chronological order; The communication requests are taken out from the queue in sequence, and based on the communication requests, the first memory is enabled to be connected to the first PCIe endpoint or the first memory is enabled to be connected to the second PCIe endpoint.

12. The data interaction system according to claim 11, characterized in that: The gating control unit is further configured to: In response to the sender of the communication request being the first processor, enabling the first memory to be connected to the first PCIe endpoint; In response to the sender of the communication request being the second processor, the first memory is enabled to be connected to the second PCIe endpoint.

13. The data interaction system according to claim 4, characterized in that: The read-write controller is constructed using a field programmable logic gate array.

14. The data interaction system according to claim 13, characterized in that: The gating control unit is a Crossbar switching unit.

15. The data interaction system according to any one of claims 1 to 14, characterized in that: The first processor and the second processor are both selected from any one of a central processing unit, a graphics processing unit, and a dedicated integrated circuit.

16. The data interaction system according to any one of claims 1 to 14, characterized in that: The first memory is a double rate synchronous dynamic random access memory, and the second memory is a random access memory.

17. The data interaction system according to any one of claims 1 to 14, characterized in that: The system also includes a third memory; The third memory is connected to the first processor, and the third memory is a double rate synchronous dynamic random access memory, and is configured to store data involved in calculation when the first processor performs operations.

18. The data interaction system according to any one of claims 1 to 14, characterized in that: The system further includes a fourth memory; The fourth memory is connected to the second processor, and the fourth memory is a double rate synchronous dynamic random access memory, which is configured to store data involved in calculation when the second processor performs operations.

19. A data interaction method, characterized in that: The data interaction method comprises: Performing data operations using the first processor and the second processor; In response to a processor generating a calculation result and a calculation completion indication, sending a communication request to a read-write controller; The read / write controller selects the first memory to communicate with the processor generating the operation result based on the communication request; The processor generating the operation result is configured to store the operation result in the first memory after communication with the first memory is enabled, and store the operation completion indication and storage information of the operation result in the first memory in a second memory built into the read-write controller; and In response to the read / write controller detecting the operation completion indication and the storage information being written to the second memory, the first memory is enabled to communicate with another processor, wherein the other processor is configured to read the operation result from the first memory based on the storage information in the second memory after communication with the first memory is enabled.

20. A large-scale computing processing method, characterized in that: The large-scale operation includes a first operation and a second operation using the result of the first operation to participate in the calculation, and the method includes: The first processor and the second processor of the data interaction system described in any one of claims 1-18 process the first operation and the second operation respectively, and exchange the operation results between the two to perform subsequent operations based on the exchanged operation results.

21. An electronic device, characterized in that: include: at least one processor; as well as A memory storing a computer program executable in the processor, wherein the processor executes the data interaction method according to claim 19 when executing the program.

22. A computer non-volatile readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the data interaction method according to claim 19 is executed.

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