Method and apparatus for reverse conversion in rns
The method and apparatus for reverse conversion in RNS address the inefficiencies of supporting multiple integer size types by using a core function-based algorithm, achieving reduced hardware costs, power consumption, and processing time while enabling efficient multi-size type support.
Patent Information
- Application Number
- PCT/RU2023/000232
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-07-27
- Publication Date
- 2025-01-30
AI Technical Summary
Existing solutions for supporting different integer size types in hardware, such as matrix multiplication accelerators, require dedicated multiply accumulator (MAC) units for each size type, leading to inefficient hardware usage, higher power consumption, and increased costs.
A method and apparatus for reverse conversion in a residue number system (RNS) that enables reconfigurable multi-size support using a core function based on a RNS reverse conversion algorithm, replacing heavy mod operations with subtraction and a multiplexor, thereby reducing hardware costs, power consumption, and processing time.
The proposed solution achieves high hardware efficiency by supporting multi-size types with reduced hardware area, lower power consumption, and faster processing times, while also allowing for efficient reconstruction of different size types of numbers.
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Figure RU2023000232_30012025_PF_FP_ABST
Abstract
Description
METHOD AND APPARATUS FOR REVERSE CONVERSION IN RNSTECHNICAL FIELD
[0001] Embodiments of the present application relate to the field of a residue number system (RNS), and more specifically, to a method and an apparatus for reverse conversion in the RNS.BACKGROUND
[0002] A dedicated matrix multiplication acceleration is widely used in high performance computing (HPC) and artificial intelligence (Al), but these two areas have different requirements for size types — integer32 (int32) / integer64 (int64) is mainly used in the HPC, while int8 / int 16 is commonly used in the Al. For hardware manufacturers, this provides two strategic directions — creating dedicated accelerators for the Al and HPC or minimizing development costs by creating accelerators suitable for the two areas. A common way to support different size types in the hardware is to implement a separate multiply accumulator (MAC) unit for every data type. However, due to partially unused hardware and higher power consumption, this usually makes a final product less competitive compared with the matrix multiplication accelerator dedicated for a particular area. Having dedicated MACs for every size type is not hardware efficient especially when only large size or small size integer computations are only needed.SUMMARY
[0003] Embodiments of the present application provide a method and an apparatus for reverse conversion in a RNS, which provide a reconfigurable multi-size support in a reverse conversion unit of the RNS, and have high hardware efficiency in terms of reduced hardware costs, saved power consumption and saved processing time.
[0004] According to a first aspect, there is provided a method for reverse conversion in a residue number system (RNS), including: receiving a control signal, where the control signal is configured to indicate one of a reconstruction of a single 128- bit result, a reconstruction of two 64-bit results and a reconstruction of four 32-bit results, and the indicated reconstruction is a reconstruction of a result of matrix multiplication; andperforming the indicated reconstruction of the result of matrix multiplication according to a core function, where the core function is based on a RNS reverse conversion algorithm for enabling multi-size type support.
[0005] According to the present application, RNS reverse conversion is performed according to a core function which is based on a RNS reverse conversion algorithm for enabling multi-size type support. Besides, the proposed RNS reverse conversion algorithm replaces heavy mod operations by subtraction and a multiplexor, -which has high hardware efficiency in terms of reduced hardware costs, saved power consumption and saved processing time, etc.
[0006] In an embodiment, the core function is a core function C(Z) of a binary number Z, and the core function is defined as:where is the core function, is a weight that corresponds to mhmt belongs to amoduli set of the RNS, zfis the / -th residue of a RNS representation of Z underthe RNS, M is a dynamic range based on the moduli set, and a symbol [ J indicates rounding down.
[0007] In an embodiment, the binary number Z is determined according to an equation below:, CMis computed in a way that andis chosen as a power of 2, and
[0008] In an embodiment, the moduli set is a moduli set g64, and moduli of the moduli set g64are used to produce a single 128-bit number in a case that the control signal indicates a first value, andare sixteen moduli included in the moduli set;where moduli of moduli groups and are used to produce two 64-bit numbers respectively in a case thatthe control signal indicates a second value, andor, where moduli of moduli group gj6are used to produce four 32-bit numbers respectively in a case that the control signal indicates a third value, andwhere requirements for grouping of the moduli need to be meet as follows: and
[0009] According to this embodiment, the proposed RNS reverse conversion based on the core function allows the reconstruction of values of different size types by grouping the moduli properly.
[0010] In an embodiment, an output oof the RNS reverse conversion is computed as follows:where cntif cm2= cm3= cm4= 0 in the case that the control signal indicates the first value;, andin the case that the control signal indicates the second value; and in the case that the control signal indicates the third value;where
[0011] According to this embodiment, the proposed RNS reverse conversion allows reconstructing of different size types of numbers using efficient hierarchical controlled accumulation. As a result, the proposed RNS reverse conversion reconstructs a single 128-bit result, two 64-bit results or four 32-bit results respectively depending on a control signal. The proposed RNS reverse conversion unit requires only a small additional area to support multi-size types in matrix multiplication hardware acceleration.
[0012] In an embodiment, the output o£trlis the result of matrix multiplication, and a size type of numbers in input matrices is 64-bit, and a size type of numbers in an output matrix is 128-bit in the case that the control signal indicates the first value; a size type of numbers in input matrices is 32-bit, and a size type of numbers in an output matrix is 64-bit in the case that the control signal indicates the second value; or a size type of numbers in input matrices is 16-bit, and a size type of numbers in an output matrix is 32-bit in the case that the control signal indicates the third value.
[0013] According to this embodiment, the proposed solution supports reconstruction of a result of matrix multiplication of which elements are 64-bit, 32-bit or 16-bit.
[0014] According to a second aspect, there is provided an apparatus for reverse conversion in a residue number system (RNS). The apparatus has a function of implementing the method in the first aspect and any possible implementation manners of the first aspect. The function may be implemented by hardware. The hardware includes one or more circuits corresponding to the foregoing function.
[0015] According to a third aspect, there is provided a chip (or a chip system). The chip may include multiplexers, multipliers, adders, subtractors and shifters. The chip has a function of implementing the method in the first aspect and any embodiment of the first embodiment. The function may be implemented by using the foregoing hardware structures.DESCRIPTION OF DRAWINGS
[0016] One or more embodiments are exemplarily described by corresponding accompanying drawings, and these exemplary illustrations and accompanying drawings constitute no limitation on the embodiments. Elements with the same reference numerals in the accompanying drawings are illustrated as similar elements, and the drawings are not limited to scale, in which:
[0017] FIG. 1 is a schematic block diagram of a method for RNS reverse conversion according to the present application.
[0018] FIG. 2 is an example of a moduli set and groups forming the moduli set for reconstruction of binary number system (BNS) numbers according to the present application.
[0019] FIG. 3 is an architecture of a modular arithmetic (MAC) unit of the RNS according to the present application.
[0020] FIG. 4 is an architecture diagram which represents a reconstruction mechanism of a single 64-bit binary value, two 32-bit binary values and four 16-bit binary values from residues using a core function depending on a control signal according to the present application.
[0021] FIG. 5 is an example of a schematic block diagram of a chip (or chip system) proposed by the present application.DESCRIPTION OF EMBODIMENTS
[0022] In order to understand features and technical contents of embodiments of the present application in detail, implementations of the embodiments of the present application will be described in detail below with reference to the accompanying drawings, and the attached drawings are only for reference and illustration purposes, and are not intended to limit the embodiments of the present application. In the following technical descriptions, for ease of explanation, numerous details are set forth to provide a thorough understanding of the disclosed embodiments. One or more embodiments, however, may be practiced without these details. In other cases, well-known structures and apparatuses may be shown simplified in order to simplify the drawings.
[0023] 1. Residue Number System (RNS)
[0024] A RNS is defined by a set of n moduli called a moduli set. The n moduli are generallysupposed to be pairwise coprime, i.e., be a product henan integer x in a range ofis represented in the RNS by a set of its residues under Euclideandivision by the moduli; that is,
[0025] One of the greatest RNS features is that addition and multiplication between pairs of corresponding residues areindependent and can be performed in parallel. As what is described in the background section, support for various integer size types in RNS reverse unit is needed in many cases. A common solution to support various integer size types is to add dedicated MAC units for each size type. An advantage of the solution is that it can perform calculations of various integer types and sizes in parallel. Areconfigurable low-power high-performance matrix multiplier design proposes to implement 64-bit multiplication via 4x32-bit multiplications and lxl28-bit accumulator as follows:
[0026] A method and a system for multi-precision computation have a similar idea for enabling multi-precision support for floating point (FP) numbers focusing on multiplication of mantissa with different size. It proposes to use FP16 mantissa multiplication as a basement for creating FP32 and FP64 mantissa multiplication. As a result, it needs 4xFP16 in order to implement a single FP32 mantissa multiplication and 16XFP16 for a single FP16.
[0027] Besides, there are also other ways to build a DxD multiplier by multipliers, specifically, using Boothmultiplication or Vedic multiplication as a way to produce a final Dmultiplication result by intermediate resultsmultipliers.
[0028] In view of this, a method and an apparatus for RNS reverse conversion are proposed by the present application. The main problem to be solved is to support reconfigurable multi-size type RNS reverse conversion with a smaller hardware area and lower power consumption compared with the known solutions above. Further, data types of int64, int32, inti 6 and int8 are supported by the present application.
[0029] The present application reconstructs binary numbers on the whole dynamic range The solutionproposed by the present application is supposed to be used in matrix multiplication hardware accelerators switching all the multiplication and accumulation operations inAlthough switching operations from BNS to RNS has an additional cost of forward and reverse conversion, it is neglected in the case of matrix multiplication since the number of conversion operations is 1 order of magnitude less than the number of multiplication and additions.
[0030] FIG. 1 is a schematic block diagram of a method (200) for RNS reverse conversion according to the present application. The method (200) can be applied in areas where various data size types are required to be supported, for example, the method (200) can be applied in hardware matrix multiplication accelerators used in HPC and Al, and it allows reduction in hardware costs and power consumption. The method (200) includes the following steps.
[0031] Step 210. Receiving a control signal, where the control signal is configured to indicate one of a reconstruction of a single 128-bit result, a reconstruction of two 64-bit results and a reconstruction of four 32-bit results, where the indicatedreconstruction is a reconstruction of a result of matrix multiplication.
[0032] In other words, the control signal indicates an operation mode, and the operation mode can be a reconstruction of a single 128-bit result, a reconstruction of two 64-bit results, or a reconstruction of four 32-bit results.
[0033] It should be understood that RNS reverse conversion transforms the result of the matrix multiplication of two numbers represented in RNS into a result of matrix multiplication represented in BNS. Therefore, the reconstruction of the single 128-bit result is performed in a case that a size type of numbers in input matrices is 64-bit, the reconstruction of the two 64-bit results is performed in a case that a size type of numbers in input matrices is 32-bit, and the reconstruction of the four 32-bit results is performed in a case that a size type of numbers in input matrices is 16-bit.
[0034] Step 220. Performing the indicated reconstruction of the result of matrix multiplication according to a core function, where the core fiinction is based on a RNS reverse conversion algorithm for enabling multi-size type support.
[0035] All related contents of steps in the method (200) will be described in detail in combination with a proposed architecture of a RNS reverse conversion unit below.
[0036] In the present application, the proposed architecture of the RNS reverse conversion unit replaces heavy modulo operation at the end by subtraction and a multiplexor.
[0037] The proposed RNS reverse conversion is based on hierarchical accumulation of intermediate values where a 64- bit size type value requires accumulation across all the layers, while a 32-bit size type value skips accumulation of the last level, a 16-bit size type skips the last 2 levels of accumulation, and an 8-bit size type bypasses reverse conversion.
[0038] FIG. 2 is an example of a moduli set and groups forming the moduli set for reconstruction of BNS numbers according to the present application. It can be seen that the moduli set given by the present application isthat is to say, the moduli set contains sixteen moduli. Specificall. In addition, moduli from the moduli set are grouped as follows:
[0039] The above grouping of moduli is for example purposes only, and other groupings are possible. General requirements for grouping of the moduli that need to be met are: and
[0040] FIG. 3 is an architecture of a modular arithmetic (MAC) unit of the RNS according to the present application.Specifically, the architecture shows a reconstruction mechanism of a single 128-bit binary value, two 64-bit binary values and four 32-bit binary values, and the reconstruction mechanism is based on a core function and a control signal. It can be seen that the architecture contains 16 RNS modulo adders and multipliers which are 9x9 and 8x8 adders and multipliers with modulo reduction. Since modulo operations can be executed independently, there is no additional multi-size support required in the RNS MAC unit except dedicated mode for 8-bit addition and multiplication which is supposed to bypass reduction. RNS multipliers / adders implicitly form groups based on an operation mode that depends on a control signal, that is, so-called CTRL signal. Specifically, RNS multipliers / adders process a single 64-bit value, two 32-bit values or four 16-bit values according to the operation mode. Every modulo multiplier performs a calculation of and every adder performs acalculation of
[0041] Next, the core function proposed by the present application will be described in detail.
[0042] Math description of the core function is based on an algorithm for reverse conversion, i.e., RNS to BNS, with multi-size type support. Consider an RNS representation,of a BNS number Z, the core function is a core function of the BNS number Z, and is defined as an equation (1):where C is the core function, is a weight corresponding to belongs to a moduliof the RNS, zfis the z-th residue of a RNS representation { of Z under the RNS,M is a dynamic range based on the moduli set, and a symbol [ J indicates rounding down.
[0043] The equation (1) can also be substituted as an equation (2) below:where C
[0044] The core value of number Z by modulo CM, that is can be computed usingthe RNS representationof number Z.
[0045] Choose a number sh in such a way that and The numbersh satisfying these conditions always exists. Values do not depend on z, and can be precomputed for allThen
[0046] The number Z can be reconstructed by an equation (4) below:
[0047] Choosingas a power of 2 is thing of the present application, because it significantly simplifiescomputation logic of the core value and also transforms the final division to a bit shift operation.
[0048] In order to support different size types, subsets of the moduli set between different size types are different, and constants are different for every subset of the moduli set. However, in order to effectively support multi-size typemode via hierarchical accumulation,Mhas to be the same for all the subsets of the moduli set
[0049] The present application has advantages over a CRT-based method, such as the final modulo-M operation requires just a single multiplexor since and reconstructs all the numbers from the whole dynamic range ofwithouterror.
[0050] FIG. 4 is an architecture diagram which represents a reconstruction mechanism of a single 64-bit binary number, two 32-bit binary numbers and four 16-bit numbers from residues using the core fiinction depending on the control signal according to the present application. The architecture diagram is shown by (a), (b) and (c) of FIG. 4 in order to make it clearly to be seen.
[0051] As described above is chosen in such a way that nd
[0052] Inputs for the RNS reverse conversion unit are residuesin a case that the control signal indicates a first value, all the residues forming the group g64are used to produce a single 128-bit number; in a case that the control signal indicates a second value, residues from the group are used to produce a low64-bit part of a 128-bit number, and residues from the group are used to produce a high 64-bit part of the 128-bit number;or in a case that the control signal indicates a third value, residues from the groups gj6are used to produce the ith32-bit part of a 128-bit number, respectively, where
[0053] Outputs of the RNS reverse conversion units also correspondingly depend on the control signal like this:1) if the control signal indicates the first value, a single 128-bit number is outputted, and the single 128-bit number is represented as A[127:0]. The single 128-bit number is also represented as2) if the control signal indicates the second value, two 64-bit numbers are outputted, and the two 64-bit numbers are represented as The two 64-bit numbers are also represented as andrespectively in (c) of FIG. 4.3) if the control signal indicates the third value, four 32-bit numbers are outputted, and the four 32-bit numbers arerepresented as {A[127:96], A[95:64], A[63:32], A[31 :0]}. The four 32-bit numbers are also represented asrespectively in (c) of FIG. 4.
[0054] The precomputed constants:where a symbol “Ctrl” is equal to 64 if the control signal indicates the first value, the symbol “Ctrl” is equal to 32 if the control signal indicates the second value, and the symbol “ctrC is equal to 16 if the control signal indicates the third value.
[0055] For example, if the first value is “0”, the second value is “1”, and the third value is “2”, the values of the symbol“Ctrl” are determined according to an equation below:
[0056] Note that, in (a) of FIG. 4, a notation of “x&” means operationwhere “&” is a logical AND operation. Similarly, a notation of “+&” means operation ), where “&” is alogical AND operation.
[0057] Besides, in FIG. 4, a notation of “MUX” represents a multiplexor, a notation of “+” represents an adder, a notation of “x” represents a multiplier, a notation of represents a subtractor, and a notation of “»” represents a shifter.
[0058] Hardware flow will be described below.
[0059] Step 1 : computation of the core values ofSpecifically, core values are computed according an equation (6):At the beginning, values of the above constants are selected based on the value of the control signal.wheref in above computation.Thenandare used to compute and C
[0060] Operation of modulo power of 2 is performed to compute core values based on an equation (7) below:
[0061] An output value is computed in the following way:where is the output value.
[0062] Step 2: operation of multiplying of cIf the control signal indicates the first value, and cm2= cm3= cm4= 0; if the control signalindicates the second value, or if the control signal indicates thethird value,
[0063] Step 3: A sum oi gis computed the same way aswherein above calculation of step 3.
[0064] Step 4: computing of the final outputSpecifically,kis computed in the following way:where a symbo ” refers to a shift operation.
[0065] The final outputis outputted as follows:
[0066] If the control signal indicates the first value, the final output is outputted asthat means a single 128- bit number, and the single 128-bit number is represented as A[127:0]; if the control signal indicates the second value, the final output is outputted as and respectively, which means two 64-bit results of multiplying two 32-bit numbers,and the two 64-bit numbers are represented a andif the control signal indicates the third value, the finaloutput is outputted as, and respectively, which means four 32-bit results of multiplying two 16-bitnumbers, and the four 32-bit numbers are represented as A
[0067] For example, the first value, the second value and the third value are “0”, “1” and “2” respectively, the final output can be expressed as follows:
[0068] Note that, a size of numbers in an output matrix is two times the size of the numbers in an input matrix, for example, a size of 128-bit of the numbers in the output matrix is a result of multiplying two input matrices of which number is a size of 64-bit. This way can be used to properly handle overflows or implement numbers of fixed-point data types.
[0069] Specifically, the final output is a result of multiplying two 64-bit numbers in the case that the control signal indicates the first value, two results of multiplying 32-bit numbers in the case that the control signal indicates the second value, and four results of multiplying two 16-bit numbers in the case that the control signal indicates the third value, respectively.
[0070] The final set of multiplexers forms correct final output depending on the control signal, specifically, the single 128-bit number, the two 64-bit numbers or the four 32-bit numbers, all cases of which supply 128 bits output.
[0071] The present application proposes to use independent computation feature of the RNS in order to provide multisize support for RNS reverse conversion. In the present application, splitting 64-bit multiplication into 16 modular multiplications has a set of advantages. For example, the same set of modular multipliers and adders can be used to enable one 64-bit, two 32-bit, four 16-bit and eight (or sixteen) 8-bit MAC units by proper grouping of moduli. The number of 8-bit MAC units depends on the actual MAC implementation. Separate multiplication followed by moduli reduction allows using of multipliers as 8-bit BNS multipliers enabling dedicated RNS free mode for 8-bit size type. While this MAC implementation provides sixteen 8-bit MAC units, the overall hardware area and power consumption will be higher than the case of efficient modulo multipliers implementation without dedicated modulo reduction step. In this case, 8-bit MAC units will utilize two MAC units with the total eight 8-bit MAC units.
[0072] Hardware area and power consumption of sixteen 8 / 9-bit modular multipliers (which need to cover a binaryrange of [0; 2128-1]) is less than hardware area and power consumption of a single 64-bit multiplier due to complex carry propagation logic for 64-bit adders and multipliers.
[0073] There is no any dedicated multi-size support needed in the MAC units except dedicated handling of integer 8- bit type which can simply disable modulo reduction by bypassing a RNS arithmetic. Other size types support is only required within converters for converting numbers in RNS and BNS to and from each other.
[0074] The proposed RNS reverse conversion supporting multi-size types allows achieving of up to 21% less hardware area and up to 19% less power consumption than a CRT-based multi-size types reverse conversion unit. In addition, the proposed solution by the present application is 16% faster than the CRT-based multi-size types reverse conversion unit.
[0075] Besides, the core function based RNS reverse conversion algorithm in the present application properly reconstructs binary numbers on the whole dynamic range of , while for CRT-based methods approximation for %Moperation does not guarantee proper binary number reconstruction on the whole dynamic range of RNS.
[0076] An extension for the RNS reverse conversion unit based on a core function allows reconstructing of different size types of numbers using efficient hierarchical controlled accumulation. As a result, the proposed RNS reverse conversion requires only a small additional area for enabling support of multi-size types.
[0077] The above is an introduction to the embodiments of the method, and embodiments of an apparatus is described below.
[0078] As an embodiment of the present application, a chip (or chip system) is provided. The chip may include one or more circuits. The one or more circuits are configured to implement the method for reversion conversion proposed by the present application. In other words, the one or more circuits as a whole have a function of implementing the method proposed by the present application.
[0079] FIG. 5 is an example of a schematic block diagram of a chip (or chip system) proposed by the present application. As shown in FIG. 5, the chip (or chip system) may include multiplexers 11, multipliers 12, adders 13, subtractors 14 and shifters 15, and so on. Specifically, these devices included in the chip form the one or more circuits, and are configured to perform RNS reverse conversion proposed by the present application. For the connection relationships between these devices and the operation of each of these devices, reference can be made to the above embodiment in FIG. 4, and it will not be repeated herein.
[0080] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.
Claims
CLAIMSWhat is claimed is:
1. A method for reverse conversion in a residue number system (RNS), comprising: receiving a control signal, wherein the control signal is configured to indicate one of a reconstruction of a single 128-bit result, a reconstruction of two 64-bit results and a reconstruction of four 32-bit results, and the indicated reconstruction is a reconstruction of a result of matrix multiplication; and performing the indicated reconstruction of the result of matrix multiplication according to a core function, wherein the core function is based on a RNS reverse conversion algorithm for enabling multi-size type support.
2. The method according to claim 1, wherein the core function is a core function C(Z) of a binaiy number Z, and the core function is defined as:wherein C(Z) is the core function, is a weight that corresponds to m,, mtbelongs to a moduli setof the RNS, z(is the z-th residue of a RNS representation } of Z underthe RNS, Mis a dynamic range based on the moduli set, and a symbol [ ] indicates rounding down.
3. The method according to claim 2, wherein the binary number Z is determined according to an equation below:wherein jscomputed in a way that and ischosen as a power of 2, and4. The method according to claim 2 or 3, wherein the moduli set is a moduli set, and moduli of the moduli set are used to produce a single 128-bit number in a case that the control signal indicates a first value,are sixteen moduli comprised in the moduli set;wherein moduli of moduli groups2and are used to produce two 64-bit numbers respectively in a case that thecontrol signal indicates a second value,andor, wherein moduli of moduli group g}6are used to produce four 32-bit numbers respectively in a case that the controlsignal indicates a third value, ndwherein requirements for grouping of the moduli need to be meet as follows:
5. The method according to claim 4, an outputof the RNS reverse conversion is computed as follows:wherein ol;whereinand cm2= cm3= cm4= 0 in the case that the control signal indicates the first value; and in the case that the control signal indicates the second value; andin the case that the control signal indicates the third value;whereinwherein M6. The method according to claim 5, wherein the output o is the result of matrix multiplication, anda size type of numbers in input matrices is 64-bit, and a size type of numbers in an output matrix is 128-bit in the case that the control signal indicates the first value; a size type of numbers in input matrices is 32-bit, and a size type of numbers in an output matrix is 64-bit in the case that the control signal indicates the second value; or a size type of numbers in input matrices is 16-bit, and a size type of numbers in an output matrix is 32-bit in the case that the control signal indicates the third value.
7. An apparatus for reverse conversion in a residue number system (RNS), comprising: one or more circuits, configured to: receive a control signal, wherein the control signal is configured to indicate one of a reconstruction of a single 128-bit result, a reconstruction of two 64-bit results and a reconstruction of four 32-bit results, and the indicated reconstruction is a reconstruction of a result of matrix multiplication; and perform the indicated reconstruction of the result of matrix multiplication according to a core function, wherein the core function is based on a RNS reverse conversion algorithm for enabling multi-size type support.
8. The apparatus according to claim 7, wherein the core function is a core function C(Z) of a binary number Z, and the core function is defined as:wherein C(Z) is the core function, is a weight that corresponds to belongs to a moduli setofthe RNS, ztis the z-th residue of a RNS representation } of Z under the RNS, Mis a dynamic range based on the moduli set, and a symbol L J indicates rounding down.
9. The apparatus according to claim 8, wherein the binary number Z is determined according to an equation below:wherein jscomputed in a way that and ischosen as a power of 2, and10. The apparatus according to claim 8 or 9, wherein the moduli set is a moduli set4, and moduli of the moduli setare used to produce a single 128-bit number in a case that the control signal indicates a first value,and are sixteen moduli comprised in the moduli set;wherein moduli of moduli groups and are used to produce two 64-bit numbers respectively in a case that thecontrol signal indicates a second value, andor, wherein moduli of moduli group g}bare used to produce four 32-bit numbers respectively in a case that the control signal indicates a third value, }, andwherein requirements for grouping of the moduli need to be meet as follows:
11. The apparatus according to claim 10, an output oktrlof the RNS reverse conversion is computed by the one or more circuits as follows:whereinwhereinandin the case that the control signal indicates the first value;andn the case that the control signal indicates the second value; andin the case that the control signal indicates the third value;whereinwhereinia£12. The apparatus according to claim 9 or 10, wherein the outputlis the result of matrix multiplication, and a size type of numbers in input matrices is 64-bit, and a size type of numbers in an output matrix is 128-bit in the case that the control signal indicates the first value; a size type of numbers in input matrices is 32-bit, and a size type of numbers in an output matrix is 64-bit in the case that the control signal indicates the second value; ora size type of numbers in input matrices is 16-bit, and a size type of numbers in an output matrix is 32-bit in the case that the control signal indicates the third value.
13. Achip or a chip system, comprising an apparatus according to any one of claims 7 to 12.