Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises: a base substrate (1) and a plurality of sub-pixels (P) located on one side of the base substrate (1). The plurality of sub-pixels (P) comprise sub-pixel rows extending in a first direction and arranged in a second direction. At least one sub-pixel (P) comprises a main pixel part (PA) and an auxiliary pixel part (PB) distributed in the second direction, wherein the brightness of the main pixel part (PA) is greater than that of the auxiliary pixel part (PB). In the sub-pixel rows, the main pixel parts (PA) and the auxiliary pixel parts (PB) are alternately arranged.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light and the VA method of the liquid crystal panel. This technology can precisely manipulate the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in its use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light. This accuracy is measured in picometers (one trillionth of a meter). UV2A's advantage lies in its simple LCD panel structure, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, thanks to the availability of new materials, production equipment, and a refined processing process, this dream has become a reality. This simple LCD panel structure not only improves production efficiency but also offers numerous advantages in image quality.

[0004] High-resolution products, such as 8K and 16K display products, are the main direction of subsequent products. However, the current 8K products using vertical alignment liquid crystal (VA) have problems with low transmittance and poor color deviation.

[0005] Summary of the Invention

[0006] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0007] substrate;

[0008] A plurality of sub-pixels are located on one side of the substrate, the plurality of sub-pixels comprising: a sub-pixel row extending along a first direction and arranged along a second direction; at least one of the sub-pixels comprises: a main pixel portion distributed along the second direction, and an auxiliary pixel portion, wherein the brightness of the main pixel portion is greater than the brightness of the auxiliary pixel portion, and in the sub-pixel row, the main pixel portion and the auxiliary pixel portion are alternately arranged.

[0009] In a possible embodiment, the array substrate includes: gate lines extending along the first direction, data lines extending along the second direction, and first common lines distributed on one side of the gate lines and extending along the first direction, and second common lines distributed on the other side of the gate lines and extending along the first direction;

[0010] The subpixel includes: a first subpixel electrode, a second subpixel electrode, a first transistor electrically connected to the first subpixel electrode, a second transistor electrically connected to the second subpixel electrode, and a third transistor electrically connected to one of the first transistor and the second transistor; the first subpixel electrode and the first common wiring are located on the same side of the gate line, and the second subpixel electrode and the second common wiring are located on the same side of the gate line;

[0011] On the sub-pixel row, the third transistors of the plurality of sub-pixels are alternately distributed in a first area and a second area in the orthographic projection of the substrate; wherein the first area includes: the gate line, the first common routing, and the area between the gate line and the first common routing; the second area includes: the gate line, the second common routing, and the area between the gate line and the second common routing.

[0012] In a possible implementation, on the sub-pixel row, the third transistors of a plurality of the sub-pixels are alternately electrically connected to the first common wiring and the second common wiring.

[0013] In one possible implementation, the first transistor includes: a first transistor gate, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor gate, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor gate, a third transistor first electrode, and a third transistor second electrode;

[0014] In the sub-pixel row, the second electrodes of the first transistors and the second electrodes of the second transistors of a plurality of the sub-pixels are alternately reused as the first electrodes of the third transistors.

[0015] In one possible embodiment, the plurality of first transistor second electrodes include: a first type second electrode and a second type second electrode; the first type second electrode includes: a first type first portion extending along the first direction, a first type second portion extending from one end of the first type first portion toward one side of the gate line, and a first type third portion extending from the other end of the first type first portion toward one side of the gate line; the second type second electrode includes: a second type first portion extending along the first direction, and a second type second portion extending from one end of the second type first portion toward one side of the gate line 2;

[0016] On the sub-pixel row, the first type of second poles and the second type of second poles are alternately distributed.

[0017] In one possible implementation, the second electrode of the second transistor includes: a third type second electrode and a fourth type second electrode; the third type second electrode includes: a third type first portion extending along the first direction, a third type second portion extending from one end of the third type first portion toward one side of the gate line, and a third type third portion extending from the other end of the third type first portion toward one side of the gate line; the fourth type second electrode includes: a fourth type first portion extending along the first direction, and a fourth type second portion extending from one end of the fourth type first portion toward one side of the gate line;

[0018] On the sub-pixel row, the third type of second poles and the fourth type of second poles are alternately distributed.

[0019] In one possible embodiment, the first common routing line has a first common protrusion facing the gate line, and an orthographic projection of the second electrode of the third transistor on the substrate overlaps with the orthographic projection of the first common protrusion on the substrate; the second common routing line has a second common protrusion facing the gate line, and an orthographic projection of the second electrode of the third transistor on the substrate overlaps with the orthographic projection of the second common protrusion on the substrate;

[0020] In the sub-pixel row, there is one sub-pixel between adjacent first common convex portions, and there is one sub-pixel between adjacent second common convex portions. The first common convex portions and the second common convex portions are staggered in distribution.

[0021] In a possible implementation, the first sub-pixel electrode is an integrated structure, and the second sub-pixel electrode is an integrated structure.

[0022] In a possible implementation, the first sub-pixel electrode includes: a first electrode portion and a second electrode portion sequentially distributed along the second direction; the second sub-pixel electrode includes: a third electrode portion and a fourth electrode portion sequentially distributed along the second direction;

[0023] The first electrode portion has a plurality of first slits, the second electrode portion has a plurality of second slits, the third electrode portion has a plurality of third slits, and the fourth electrode portion has a plurality of fourth slits;

[0024] An extending direction of the first slit is the same as an extending direction of the second slit, an extending direction of the third slit is the same as an extending direction of the fourth slit, and an extending direction of the first slit is different from an extending direction of the third slit.

[0025] In a possible implementation manner, a fifth slit is further provided between the first electrode portion and the second electrode portion, and an extending direction of the fifth slit is different from an extending direction of the first slit;

[0026] A sixth slit is further provided between the third electrode portion and the fourth electrode portion, and an extending direction of the sixth slit is different from an extending direction of the third slit.

[0027] In a possible implementation manner, the fifth slit extends along the second direction, and the sixth slit extends along the second direction.

[0028] In a possible implementation manner, the fifth slit and the third slit extend in the same direction, and the sixth slit and the first slit extend in the same direction.

[0029] In one possible embodiment, the side of the first electrode portion facing the second electrode portion is a semi-closed structure, the side of the second electrode portion facing the first electrode portion is a semi-closed structure, and the closed position of the first electrode portion facing the second electrode portion is opposite to the open position of the second electrode portion facing the first electrode portion, and the open position of the first electrode portion facing the second electrode portion is opposite to the closed position of the second electrode portion facing the first electrode portion.

[0030] In a possible implementation, the first slit of the first electrode portion and the second slit of the second electrode portion are an integrated structure; the third slit of the third electrode portion and the fourth slit of the fourth electrode portion are an integrated structure.

[0031] In a possible implementation, the array substrate includes: gate lines extending along the first direction, data lines extending along the second direction, and first common lines distributed on one side of the gate lines, and second common lines distributed on the other side of the gate lines;

[0032] The sub-pixel includes: a first transistor, a second transistor, a third transistor electrically connected to one of the first transistor and the second transistor, and a first electrode portion, a second electrode portion, a third electrode portion, and a fourth electrode portion sequentially distributed along the second direction; the first electrode portion is electrically connected to one of the third electrode portion and the fourth electrode portion to form a first connected sub-pixel electrode; the second electrode portion is electrically connected to the other of the third electrode portion and the fourth electrode portion to form a second connected sub-pixel electrode;

[0033] In which, on the sub-pixel row, the first connecting sub-pixel electrodes of multiple sub-pixels are alternately electrically connected to the first transistor and the second transistor; the second connecting sub-pixel electrodes of multiple sub-pixels are alternately electrically connected to the first transistor and the second transistor; and in the same sub-pixel, the first connecting sub-pixel electrode and the second connecting sub-pixel electrode are electrically connected to different transistors.

[0034] In a possible implementation manner, the first electrode portion is electrically connected to the fourth electrode portion, and the second electrode portion is electrically connected to the third electrode portion.

[0035] In a possible implementation, the array substrate further includes: a first connecting portion extending along the second direction, and a second connecting portion;

[0036] One end of the first connection portion is electrically connected to the first electrode portion, and the other end is electrically connected to the fourth electrode portion; one end of the second connection portion is electrically connected to the second electrode portion, and the other end is electrically connected to the third electrode portion.

[0037] In a possible implementation manner, the array substrate further includes: a first connecting protruding portion connected to the first connecting portion and protruding toward a side of the third transistor;

[0038] On the sub-pixel row, the first connection protrusions are electrically connected to the first transistors and the second transistors alternately.

[0039] In a possible implementation, on the sub-pixel row, outer edge extension lines of adjacent first connecting outer protrusions along the first direction do not overlap.

[0040] In a possible implementation manner, the first electrode portion is electrically connected to the third electrode portion, and the second electrode portion is electrically connected to the fourth electrode portion.

[0041] In a possible implementation, the array substrate further includes: a third connecting portion extending along the second direction, and a fourth connecting portion;

[0042] The orthographic projection of the third connecting portion on the substrate is located on the side of the orthographic projection of the first sub-pixel electrode on the substrate, and one end of the third connecting portion is electrically connected to the first electrode portion, and the other end of the third connecting portion is electrically connected to the side of the third electrode portion facing the second electrode portion;

[0043] One end of the fourth connection portion is electrically connected to the second electrode portion, and the other end is electrically connected to the fourth electrode portion.

[0044] In a possible implementation, the plurality of sub-pixels include: sub-pixel columns extending along the second direction and arranged along the first direction; in the sub-pixel columns, the main pixel portions and the auxiliary pixel portions are alternately arranged.

[0045] In a possible implementation, the plurality of sub-pixels include: a sub-pixel column extending along the second direction and arranged along the first direction; in the sub-pixel column, two main pixel portions and two auxiliary pixel portions are alternately arranged.

[0046] In a possible implementation manner, the array substrate further includes: a first electrode layer; the first electrode layer includes: a first electrode connecting portion, a first hollow, and a second hollow;

[0047] The orthographic projection of the first hollow on the substrate at least partially overlaps with the orthographic projection of the first sub-pixel electrode on the substrate; the orthographic projection of the second hollow on the substrate at least partially overlaps with the orthographic projection of the second sub-pixel electrode on the substrate.

[0048] In a possible implementation manner, the orthographic projection of the first electrode connecting portion on the substrate covers the orthographic projection of the data line on the substrate.

[0049] The present disclosure also provides a display panel, which includes the array substrate provided in the present disclosure and an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

[0050] In a possible implementation manner, the first electrode layer and the common electrode layer are loaded with the same signal.

[0051] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG1A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0053] FIG1B is a schematic diagram of a single film layer of the gate line layer in FIG1A;

[0054] FIG1C is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0055] FIG1D is a schematic diagram of a single film layer of the data line layer in FIG1A ;

[0056] FIG1E is a schematic diagram of a single film layer of the first insulating layer in FIG1A ;

[0057] FIG1F is a schematic diagram of a single film layer of the pixel electrode layer in FIG1A ;

[0058] FIG1G is a schematic diagram of light effect simulation corresponding to the array substrate of FIG1A ;

[0059] FIG1H is a schematic cross-sectional view at point EF in FIG1A ;

[0060] FIG2A is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0061] FIG2B is a schematic diagram of a single film layer of the gate line layer in FIG2A ;

[0062] FIG2C is a schematic diagram of a single film layer of the active layer in FIG2A ;

[0063] FIG2D is a schematic diagram of a single film layer of the data line layer in FIG2A ;

[0064] FIG2E is a schematic diagram of a single film layer of the first insulating layer in FIG2A ;

[0065] FIG2F is a schematic diagram of a single film layer of the pixel electrode layer in FIG2A ;

[0066] FIG2G is a schematic diagram of light effect simulation corresponding to the array substrate of FIG2A ;

[0067] FIG3A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0068] FIG3B is a schematic diagram of a single film layer of the gate line layer in FIG3A ;

[0069] FIG3C is a schematic diagram of a single film layer of the active layer in FIG3A ;

[0070] FIG3D is a schematic diagram of a single film layer of the data line layer in FIG3A ;

[0071] FIG3E is a schematic diagram of a single film layer of the first insulating layer in FIG3A ;

[0072] FIG3F is a schematic diagram of a single film layer of the pixel electrode layer in FIG3A ;

[0073] FIG3G is a schematic diagram of light effect simulation corresponding to the array substrate in FIG3A ;

[0074] FIG4A is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0075] FIG4B is a schematic diagram of a single film layer of the gate line layer in FIG4A;

[0076] FIG4C is a schematic diagram of a single film layer of the active layer in FIG4A ;

[0077] FIG4D is a schematic diagram of a single film layer of the data line layer in FIG4A ;

[0078] FIG4E is a schematic diagram of a single film layer of the first insulating layer in FIG4A ;

[0079] FIG4F is a schematic diagram of a single film layer of the pixel electrode layer in FIG4A ;

[0080] FIG4G is a schematic diagram of light effect simulation corresponding to the array substrate in FIG4A ;

[0081] FIG5A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0082] FIG5B is a schematic diagram of a single film layer of the gate line layer in FIG5A;

[0083] FIG5C is a schematic diagram of a single film layer of the active layer in FIG5A;

[0084] FIG5D is a schematic diagram of a single film layer of the data line layer in FIG5A ;

[0085] FIG5E is a schematic diagram of a single film layer of the first insulating layer in FIG5A ;

[0086] FIG5F is a schematic diagram of a single film layer of the pixel electrode layer in FIG5A ;

[0087] FIG5G is a schematic diagram of light effect simulation corresponding to the array substrate in FIG5A ;

[0088] FIG6A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0089] FIG6B is a schematic diagram of a single film layer of the gate line layer in FIG6A;

[0090] FIG6C is a schematic diagram of a single film layer of the active layer in FIG6A;

[0091] FIG6D is a schematic diagram of a single film layer of the data line layer in FIG6A ;

[0092] FIG6E is a schematic diagram of a single film layer of the first insulating layer in FIG6A ;

[0093] FIG6F is a schematic diagram of a single film layer of the pixel electrode layer in FIG6A ;

[0094] FIG7 is a seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0095] FIG8 is an eighth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0096] FIG9A is a ninth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0097] FIG9B is a schematic diagram of a single film layer of the gate line layer in FIG9A;

[0098] FIG9C is a schematic diagram of a single film layer of the active layer in FIG9A;

[0099] FIG9D is a schematic diagram of a single film layer of the data line layer in FIG9A ;

[0100] FIG9E is a schematic diagram of a single film layer of the first insulating layer in FIG9A ;

[0101] FIG9F is a schematic diagram of a single film of the first electrode layer in FIG9A ;

[0102] FIG9G is a schematic diagram of a single film layer of the second insulating layer in FIG9A ;

[0103] FIG9H is a schematic diagram of a single film layer of the pixel electrode layer in FIG9A ;

[0104] FIG9I is a schematic diagram of a black matrix corresponding to the array substrate shown in FIG9A ;

[0105] FIG9J is a schematic diagram of light effect simulation corresponding to the array substrate shown in FIG9A ;

[0106] FIG10 is a schematic diagram of a sub-pixel equivalent circuit provided by an embodiment of the present disclosure;

[0107] FIG11 is a schematic cross-sectional view of a display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0108] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0109] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0110] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0111] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0112] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0113] 1A to 1F, 2A to 2F, 3A to 3F, 4A to 4F, 5A to 5F, and 6A to 6F, wherein FIG1A is one of the schematic top views of the array substrate provided in the embodiment of the present disclosure, FIG1B is a schematic diagram of a single film layer of the gate line layer in FIG1A, FIG1C is a schematic diagram of a single film layer of the active layer in FIG1A, FIG1D is a schematic diagram of a single film layer of the data line layer in FIG1A, FIG1E is a schematic diagram of a single film layer of the first insulating layer in FIG1A, FIG1F is a schematic diagram of a single film layer of the pixel electrode layer in FIG1A, and FIG2A is a schematic diagram of a top view of the array substrate provided in the embodiment of the present disclosure. FIG2B is a schematic diagram of a single film layer of the gate line layer in FIG2A, FIG2C is a schematic diagram of a single film layer of the active layer in FIG2A, FIG2D is a schematic diagram of a single film layer of the data line layer in FIG2A, FIG2E is a schematic diagram of a single film layer of the first insulating layer in FIG2A, FIG2F is a schematic diagram of a single film layer of the pixel electrode layer in FIG2A, and FIG3A is a top view of the array substrate provided in an embodiment of the present disclosure. FIG3B is a schematic diagram of a single film layer of the gate line layer in FIG3A, FIG3C is a schematic diagram of a single film layer of the active layer in FIG3A, FIG3D is a schematic diagram of a single film layer of the data line layer in FIG3A, and FIG3E is a schematic diagram of a single film layer of the first insulating layer in FIG3A. FIG3F is a schematic diagram of a single film layer of the pixel electrode layer in FIG3A , FIG4A is a fourth schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure, FIG4B is a schematic diagram of a single film layer of the gate line layer in FIG4A , FIG4C is a schematic diagram of a single film layer of the active layer in FIG4A , FIG4D is a schematic diagram of a single film layer of the data line layer in FIG4A , FIG4E is a schematic diagram of a single film layer of the first insulating layer in FIG4A , FIG4F is a schematic diagram of a single film layer of the pixel electrode layer in FIG4A , FIG5A is a fifth schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure, FIG5B is a schematic diagram of a single film layer of the gate line layer in FIG5A , and FIG5C is a schematic diagram of a single film layer of the active layer in FIG5A 5A , FIG5D is a schematic diagram of a single film layer of the data line layer in FIG5A , FIG5E is a schematic diagram of a single film layer of the first insulating layer in FIG5A , FIG5F is a schematic diagram of a single film layer of the pixel electrode layer in FIG5A , FIG6A is a sixth schematic diagram of a top view of an array substrate provided in an embodiment of the present disclosure, FIG6B is a schematic diagram of a single film layer of the gate line layer in FIG6A , FIG6C is a schematic diagram of a single film layer of the active layer in FIG6A , FIG6D is a schematic diagram of a single film layer of the data line layer in FIG6A , FIG6E is a schematic diagram of a single film layer of the first insulating layer in FIG6A , and FIG6F is a schematic diagram of a single film layer of the pixel electrode layer in FIG6A . An embodiment of the present disclosure provides an array substrate, comprising:

[0114] Substrate 1;

[0115] Multiple sub-pixels P are located on one side of the substrate 1, and the multiple sub-pixels P include: sub-pixel rows extending along the first direction X and arranged along the second direction Y; at least one sub-pixel P includes: a main pixel portion PA distributed along the second direction Y, and a subsidiary pixel portion PB, wherein the brightness of the main pixel portion PA is greater than the brightness of the subsidiary pixel portion PB, and in the sub-pixel row, the main pixel portion PA and the subsidiary pixel portion PB are alternately arranged.

[0116] In the disclosed embodiment, at least one sub-pixel P includes: a main pixel portion PA distributed along a second direction Y, and a subsidiary pixel portion PB, wherein the brightness of the main pixel portion PA is greater than the brightness of the subsidiary pixel portion PB, and in a sub-pixel row, the main pixel portion PA and the subsidiary pixel portion PB are alternately arranged, that is, the main pixel portion PA and the subsidiary pixel portion PB are divided vertically and arranged in an interlaced manner. The two sub-pixels in the first direction X can form a 2P8D (2 sub-pixels and 8 sub-pixels) effect in which brightness and darkness compensate for each other, while the second direction Y can also form a brightness and darkness compensation effect. Moreover, the two sub-pixels in the first direction X can also form a viewing angle compensation effect, while the second direction Y can also form a viewing angle compensation effect. This 2P8D design can achieve the effect of both improving transmittance and improving color shift.

[0117] It can be understood that the brightness of the main pixel portion PA being greater than the brightness of the auxiliary pixel portion PB refers to the brightness comparison within one sub-pixel P when the display panel is powered on and illuminated.

[0118] In a possible embodiment, referring to Figures 1A to 1F, Figures 2A to 2F, Figures 3A to 3F, and Figures 4A to 4F, the array substrate includes: a gate line 2 extending along a first direction X, a data line 3 extending along a second direction Y, and a first common trace 25 extending along the first direction X on one side of the gate line 2, and a second common trace 26 extending along the first direction X on the other side of the gate line 2; the sub-pixel includes: a first sub-pixel electrode 41, a second sub-pixel electrode 42, a first transistor T1 electrically connected to the first sub-pixel electrode 41, a second transistor T2 electrically connected to the second sub-pixel electrode, and a third transistor T3 electrically connected to one of the first transistor T1 and the second transistor T2; the first sub-pixel electrode 4 1 and the first common wiring 25 are located on the same side of the gate line 2, and the second sub-pixel electrode 42 and the second common wiring 26 are located on the same side of the gate line 2. For example, as in 1A, the first sub-pixel electrode 41 and the first common wiring 25 are both located on the upper side of the gate line 2, and the second sub-pixel electrode 42 and the second common wiring 26 are both located on the lower side of the gate line 2; wherein, on the sub-pixel row, the orthographic projections of the third transistors T3 of the plurality of sub-pixels P on the substrate 1 are alternately distributed in the first area S1 and the second area S2; wherein the first area S1 includes: the gate line 2, the first common wiring 25, and the area between the gate line 2 and the first common wiring 25; the second area S2 includes: the gate line 2, the second common wiring 26, and the area between the gate line 2 and the second common wiring 26.

[0119] In the embodiment of the present disclosure, the third transistors T3 of the plurality of sub-pixels P are alternately distributed in the first region S1 and the second region S2 in their orthographic projections on the substrate 1. In this way, the third transistors T3 are alternately electrically connected to the first common wiring 25 and the second common wiring 26, thereby achieving an alternating arrangement of the main pixel portion PA and the auxiliary pixel portion PB.

[0120] Specifically, the orthographic projection of the first transistor T1 on the substrate 1 can be distributed in the first area S1 (the first area S1 may include: the gate line 2, the first common routing line 25, and the area between the gate line 2 and the first common routing line 25), that is, the orthographic projection of the first transistor T1 on the substrate 1 may overlap with the orthographic projection of the gate line 2 on the substrate 1, overlap with the orthographic projection of the first common routing line 25 on the substrate 1, and overlap with the orthographic projection of the area between the gate line 2 and the first common routing line 25 on the substrate 1; the orthographic projection of the second transistor T2 on the substrate 1 may be distributed in the second area S2 (the second area S2 may include: the gate line 2, the second common routing line 26, and the area between the gate line 2 and the second common routing line 26), that is, the orthographic projection of the first transistor T1 on the substrate 1 may overlap with the orthographic projection of the gate line 2 on the substrate 1, overlap with the orthographic projection of the second common routing line 26 on the substrate 1, and overlap with the orthographic projection of the area between the gate line 2 and the second common routing line 26 on the substrate 1.

[0121] It can be understood that, along the first direction X, the first sub-pixel electrode 41 of each sub-pixel P is a sub-pixel electrode located on one side of the gate line 2, for example, the sub-pixel electrode is located on the upper side of the gate line 2, and the second sub-pixel electrode 42 is a sub-pixel electrode located on the other side of the gate line 2, for example, the sub-pixel electrode is located on the lower side of the gate line 2; and along the first direction X, the positions of the main pixel portions PA of the sub-pixels P are alternately distributed, that is, of the main pixel portions PA of two adjacent sub-pixels P in the first direction X, one is located on the upper side of the gate line 2, and the other is located on the lower side of the gate line 2. Similarly, along the first direction X, the positions of the auxiliary pixel portions PB of the sub-pixels P are also alternately distributed, that is, of the auxiliary pixel portions PB of two adjacent sub-pixels P in the first direction X, one is located on the upper side of the gate line 2, and the other is located on the lower side of the gate line 2.

[0122] In one possible implementation, referring to Figures 1A-1F, 2A-2F, 3A-3F, and 4A-4F, in a sub-pixel row, the third transistors T3 of multiple sub-pixels P are alternately electrically connected to the first common routing line 25 and the second common routing line 26. This allows for an alternating arrangement of the primary pixel portion PA and the secondary pixel portion PB. Specifically, the third transistor T3 may be alternately electrically connected to the first common routing line 25 or the second common routing line 26 via a third via K3.

[0123] In a possible embodiment, referring to Figures 1A to 1F, Figures 2A to 2F, Figures 3A to 3F, and Figures 4A to 4F, the first transistor T1 includes: a first transistor gate (not shown in the figure, specifically may be part of the multiplexing gate line 2), a first transistor first electrode T1a, and a first transistor second electrode T1b; the second transistor T2 includes: a second transistor gate (not shown in the figure, specifically may be part of the multiplexing gate line 2), a second transistor first electrode T2a, and a second transistor second electrode T2b; the third transistor T3 includes: a third transistor gate (not shown in the figure, specifically may be part of the multiplexing gate line 2), a third transistor first electrode T3a, and a third transistor second electrode T3b; on the sub-pixel row, the first transistor second electrode T1b and the second transistor second electrode T2b of multiple sub-pixels P are alternately multiplexed as the third transistor first electrode T3a.

[0124] In a possible embodiment, referring to Figures 1A to 1F, Figures 2A to 2F, Figures 3A to 3F, and Figures 4A to 4F, the plurality of first transistor second electrodes T1b include: a first type second electrode T1bX and a second type second electrode T1bY; the first type second electrode T1bX includes: a first type first portion T1bX1 extending along the first direction X, a first type second portion T1bX2 extending from one end of the first type first portion T1bX toward one side of the gate line 2, and a first type third portion T1bX3 extending from the other end of the first type first portion T1bX toward one side of the gate line 2; the second type second electrode T1bY includes: a second type first portion T1bY1 extending along the first direction X, and a second type second portion T1bY2 extending from one end of the second type first portion T1bY1 toward one side of the gate line; on the sub-pixel row, the first type second electrode and the second type second electrode are alternately distributed.

[0125] In a possible embodiment, referring to Figures 1A to 1F, Figures 2A to 2F, Figures 3A to 3F, and Figures 4A to 4F, the second electrode T2b of the second transistor includes: a third-type second electrode T2bX and a fourth-type second electrode T2bY; the third-type second electrode T2bX includes: a third-type first portion T2bX1 extending along the first direction X, a third-type second portion T2bX2 extending from one end of the third-type first portion T2bX1 toward one side of the gate line 2, and a third-type third portion T2bX3 extending from the other end of the third-type first portion T2bX1 toward one side of the gate line 2; the fourth-type second electrode T2bY includes: a fourth-type first portion T2bY1 extending along the first direction X, and a fourth-type second portion T2bY2 extending from one end of the fourth-type first portion T2bY1 toward one side of the gate line 2; on the sub-pixel row, the third-type second electrode and the fourth-type second electrode are alternately distributed.

[0126] In a possible embodiment, referring to Figures 1A to 1F, Figures 2A to 2F, Figures 3A to 3F, and Figures 4A to 4F, the first common wiring 25 has a first common convex portion 25a facing the side of the gate line 2, and the orthographic projection of the second pole T3b of the third transistor on the substrate 1 and the orthographic projection of the first common convex portion 25a on the substrate 1 have an overlapping area, and the first common wiring 25 can be connected to the second pole T3b of the third transistor through the third via K3 at the first common convex portion 25a; the second common wiring 26 has a second common convex portion 26a facing the side of the gate line 2, and the orthographic projection of the second pole T3b of the third transistor on the substrate 1 and the orthographic projection of the second common convex portion 26a on the substrate have an overlapping area, and the second common wiring 26 has a second common convex portion 26a facing the side of the gate line 2. The wiring 26 can be connected to the second common convex portion 26a and the second electrode T3b of another third transistor through another third via K3; on the sub-pixel row, there is a sub-pixel P between adjacent first common convex portions 25a, that is, a first common convex portion 25a can be set for each sub-pixel P; there is a sub-pixel between adjacent second common convex portions 26a, that is, a second common convex portion 26a can be set for each sub-pixel P, and the first common convex portion 25a and the second common convex portion 26a are staggered. Specifically, as shown in Figure 1B, the first straight line k1 extending along the second direction Y and passing through the center of the first common convex portion 25a does not overlap with the second straight line k2 extending along the second direction Y and passing through the center of the first common convex portion 25a.

[0127] In one possible embodiment, referring to Figures 1F and 1H, Figure 1H is a schematic cross-sectional view along the dotted line EF in Figure 1A, the array substrate may further include a bonding electrode 43. Optionally, the bonding electrode 43 may be provided in the same layer and material as the pixel electrode. The third via K3 may be a semi-via, wherein the third via K3 partially exposes the first common wiring 25 (or the second common wiring 26) and partially exposes the second electrode T3b of the third transistor. The bonding electrode 43 partially contacts the first common wiring 25 (or the second common wiring 26) at the third via K3 and partially contacts the second electrode T3b of the third transistor, thereby electrically connecting the first common wiring 25 (or the second common wiring 26) to the second electrode T3b of the third transistor via the bonding electrode 43. Specifically, the design of the third via K3 as a semi-via can form a step structure inside the third via K3, thereby draining the alignment liquid and avoiding the occurrence of moiré patterns on the screen.

[0128] Specifically, referring to FIG10 , FIG10 may be an equivalent circuit diagram of the second sub-pixel P from the left in FIG1A , wherein S is the data line on the left side of the pixel, that is, the signal line for transmitting the data signal to the current sub-pixel P, that is, the data line electrically connected to the current sub-pixel P, S is the data line on the right side of the pixel, and is also the data line of the horizontally adjacent pixels. The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor Cpd_ming, a second capacitor Cgp_ming, a third capacitor Cst_ming, and a fourth capacitor Clc_ming. The first sub-pixel electrode 41 and the data line 3 form a first capacitor Cpd_bright, a second capacitor Cgp_bright is formed between the first sub-pixel electrode 41 and the gate line 2, and the overlapping area of ​​the first sub-pixel electrode 41 and the first common wiring 25 can form a first capacitor Cpd_bright. The three capacitors Cst_bright, the first sub-pixel electrode 41 and the common electrode on the opposite substrate side can form a fourth capacitor Clc_bright, a fifth capacitor Cpp(n+1) can be formed between the first sub-pixel electrode 41 of the current sub-pixel P and the second sub-pixel electrode 42 of the previous sub-pixel P, a sixth capacitor Cpd_bright can be formed between the first sub-pixel electrode 41 and the adjacent data line 3; a seventh capacitor Cpd_dark is formed between the second sub-pixel electrode 42 and the data line 3, an eighth capacitor Cgp_dark is formed between the second sub-pixel electrode 42 and the gate line 2, and the second sub-pixel electrode 41 is connected to the gate line 2. The overlapping region of the pixel electrode 42 and the second common wiring 26 can form a ninth capacitor Cst_dark. The second sub-pixel electrode 42 and the common electrode on the opposite substrate side can form a tenth capacitor Clc_dark. An eleventh capacitor Cpp(n-1) can be formed between the second sub-pixel electrode 42 of the current sub-pixel P and the first sub-pixel electrode 41 of the next sub-pixel P. A twelfth capacitor Cpd_dark can be formed between the second sub-pixel electrode 42 and the adjacent data line 3. A thirteenth capacitor Cgcs can be formed between the gate line 2 and the second electrode T3b of the third transistor.Specifically, in combination with FIG1A and FIG11, since the third transistor T3 is connected to the second transistor T2, the voltage loaded on the second sub-pixel electrode 42 will be partially distributed to the thirteenth capacitor Cgcs through the third transistor T3, and / or, on the common wiring (the first common wiring 25 or the second common wiring 26) for transmission, so that the voltage obtained by the second sub-pixel electrode 42 is lower than the voltage obtained by the first sub-pixel electrode 41, and thus the luminance of the second sub-pixel electrode 42 is lower than the luminance of the first sub-pixel electrode 41. The second sub-pixel electrode 42 serves as the auxiliary pixel portion PB, the first sub-pixel electrode 41 serves as the main pixel portion PA, and for the adjacent sub-pixel P (For example, in the first subpixel P from the left in Figure 1A ), because the third transistor T3 is connected to the first transistor T1, the voltage applied to the first subpixel electrode 41 is partially distributed through the third transistor T3 to the gate line 2 and the second electrode T3b of the third transistor, forming a fourteenth capacitor (not shown in Figure 11 ). This causes the voltage applied to the first subpixel electrode 41 to be lower than the voltage applied to the second subpixel electrode 42. Consequently, the luminance of the first subpixel electrode 41 is lower than that of the second subpixel electrode 42. The first subpixel electrode 41 functions as the auxiliary pixel portion PB, and the second subpixel electrode 42 functions as the main pixel portion PA, creating an alternating light and dark distribution effect across the subpixel row.

[0129] In a possible embodiment, referring to Figures 1A to 1F, Figures 2A to 2F, Figures 3A to 3F, and Figures 4A to 4F, the array substrate may further include a third common trace 27 electrically connecting the first common trace 25 and the second common trace 26. The third common trace 27 is located on both sides of the orthographic projection of the data line 3 on the substrate 1, which can improve the coupling capacitance between the data line 3 and the first sub-pixel electrode 41 (or the second sub-pixel electrode 42).

[0130] In a possible implementation, referring to FIG. 1A to FIG. 1F , FIG. 2A to FIG. 2F , FIG. 3A to FIG. 3F , and FIG. 4A to FIG. 4F , the first sub-pixel electrode 41 is an integrated structure, and the second sub-pixel electrode 42 is an integrated structure.

[0131] In one possible embodiment, referring to FIG. 1F , FIG. 2F , FIG. 3F , and FIG. 5A to FIG. 5F , the first sub-pixel electrode 41 includes: a first electrode portion P1 and a second electrode portion P2 sequentially distributed along the second direction Y; the second sub-pixel electrode 42 includes: a third electrode portion P3 and a fourth electrode portion P4 sequentially distributed along the second direction Y; the first electrode portion P1 has a plurality of first slits F1, the second electrode portion P2 has a plurality of second slits F2, the third electrode portion P3 has a plurality of third slits F3, and the fourth electrode portion P4 has a plurality of fourth slits F4; in one possible embodiment, 1F , 2F , and 3F , the extension direction of the first slit F1 is the same as the extension direction of the second slit F2, the extension direction of the third slit F3 is the same as the extension direction of the fourth slit F4, and the extension direction of the first slit F1 is different from the extension direction of the third slit F3; in a possible embodiment, referring to FIG. 5F , the extension direction of the first slit F1 is the same as the extension direction of the fourth slit F4, the extension direction of the second slit F2 is the same as the extension direction of the third slit F3, and the extension direction of the first slit F1 is different from the extension direction of the second slit F2.

[0132] Specifically, referring to Figure 1F, Figure 2F, and Figure 3F, the angle formed by the extension direction of the first slit F1 and the first direction X can be 40° to 50°, for example, 45°; the angle formed by the extension direction of the second slit F2 and the first direction X can be 40° to 50°, for example, 45°; the angle formed by the extension direction of the third slit F3 and the first direction X can be 130° to 140°, for example, 135°; the angle formed by the extension direction of the fourth slit F4 and the first direction X can be 130° to 140°, for example, 135°.

[0133] 5F , the angle formed by the extension direction of the first slit F1 and the first direction X may be 40° to 50°, for example, 45°; the angle formed by the extension direction of the second slit F2 and the first direction X may be 130° to 140°, for example, 135°; the angle formed by the extension direction of the third slit F3 and the first direction X may be 130° to 140°, for example, 135°; the angle formed by the extension direction of the fourth slit F4 and the first direction X may be 40° to 50°, for example, 45°.

[0134] In one possible embodiment, as shown in Figures 1F and 2F , a fifth slit F5 is further provided between the first electrode portion P1 and the second electrode portion P2, extending in a direction different from that of the first slit F1. A sixth slit F6 is further provided between the third electrode portion P3 and the fourth electrode portion P4, extending in a direction different from that of the third slit F3. In the disclosed embodiment, the fifth slit F5 provided between the first electrode portion P1 and the second electrode portion P2 can improve horizontal dark lines in the center of the first sub-pixel electrode 41. The sixth slit F6 provided between the third electrode portion P3 and the fourth electrode portion P4 can improve horizontal dark lines in the center of the second sub-pixel electrode 42, thereby increasing the aperture ratio of the display panel.

[0135] In a possible implementation, as shown in FIG. 1F , the fifth slit F5 extends along the second direction Y, and the sixth slit F6 extends along the second direction Y.

[0136] In a possible implementation, as shown in FIG. 2F , the fifth slit F5 extends in the same direction as the third slit F3 , and the sixth slit F6 extends in the same direction as the first slit F1 .

[0137] In one possible embodiment, as shown in FIG3F , the side of the first electrode portion P1 facing the second electrode portion P2 is a semi-enclosed structure, and the side of the second electrode portion P2 facing the first electrode portion P1 is a semi-enclosed structure. The closed position of the first electrode portion P1 facing the second electrode portion P2 is opposite to the open position of the second electrode portion P2 facing the first electrode portion P1. The open position of the first electrode portion P1 facing the second electrode portion P2 is opposite to the closed position of the second electrode portion P2 facing the first electrode portion P1. The closed position of the second electrode portion P2 facing the first electrode portion P1 is connected to the closed position of the first electrode portion P1 facing the second electrode portion P2, and the connection position is located in the middle area of ​​the first electrode portion P1 (or the second electrode portion P2) in the first direction X.

[0138] In a possible embodiment, referring to FIG. 4A to FIG. 4F , the first slit F1 of the first electrode portion P1 and the second slit F2 of the second electrode portion P2 are an integrated structure; the third slit F3 of the third electrode portion P3 and the fourth slit F4 of the fourth electrode portion P4 are an integrated structure.

[0139] In a possible embodiment, referring to FIG. 5A to FIG. 5F , the array substrate includes: a gate line 2 extending along a first direction X, a data line 3 extending along a second direction Y, and a first common wiring 25 distributed on one side of the gate line 2, and a second common wiring 26 distributed on the other side of the gate line 2; the sub-pixel P includes: a first transistor T1, a second transistor T2, a third transistor T3 electrically connected to one of the first transistor T1 and the second transistor T2, and a first electrode portion P1, a second electrode portion P2, a third electrode portion P3, and a fourth electrode portion P4 sequentially distributed along the second direction Y; the first electrode portion P1 is electrically connected to one of the third electrode portion P3 and the fourth electrode portion P4 to form a first connected sub-pixel electrode P11. For example, as shown in FIG. 5A , the first electrode portion P 1 is electrically connected to the fourth electrode portion P4 to form a first connected sub-pixel electrode P11; the second electrode portion P2 is electrically connected to the other of the third electrode portion P3 and the fourth electrode portion P4 to form a second connected sub-pixel electrode P12. For example, as shown in FIG5A , the second electrode portion P2 is electrically connected to the third electrode portion P3 to form the second connected sub-pixel electrode P12; wherein, on a sub-pixel row, the first connected sub-pixel electrodes P11 of a plurality of sub-pixels P are alternately electrically connected to the first transistor T1 and the second transistor T2; the second connected sub-pixel electrodes P12 of a plurality of sub-pixels P are alternately electrically connected to the first transistor T1 and the second transistor T2; and in the same sub-pixel, the first connected sub-pixel electrode P11 and the second connected sub-pixel electrode P12 are electrically connected to different transistors.

[0140] In the embodiment of the present disclosure, the connection position of the third transistor T3 is fixed. By adjusting the connection relationship between the first connection sub-pixel electrode P11 and the first transistor T1 and the second transistor T2, and the connection relationship between the second connection sub-pixel electrode P1 and the first transistor T1 and the second transistor T2, it is possible to make the first connection sub-pixel electrode P11 the main pixel portion PA or the auxiliary pixel portion PB, and make the second connection sub-pixel electrode P12 the main pixel portion PA or the auxiliary pixel portion PB, and the first connection sub-pixel electrode P11 is alternately electrically connected to the first transistor T1 and the second transistor T2, and the second connection sub-pixel electrodes P12 of multiple sub-pixels P are alternately electrically connected to the first transistor T1 and the second transistor T2, so that the main pixel portion PA and the auxiliary pixel portion PB are alternately arranged, thereby achieving the effect of both improving transmittance and improving color deviation.

[0141] Specifically, the orthographic projection of the first transistor T1 on the substrate 1 can be distributed in the first area S1 (the first area S1 may include: the gate line 2, the first common routing line 25, and the area between the gate line 2 and the first common routing line 25), that is, the orthographic projection of the first transistor T1 on the substrate 1 may overlap with the orthographic projection of the gate line 2 on the substrate 1, overlap with the orthographic projection of the first common routing line 25 on the substrate 1, and overlap with the orthographic projection of the area between the gate line 2 and the first common routing line 25 on the substrate 1; the orthographic projection of the second transistor T2 on the substrate 1 may be distributed in the second area S2 (the second area S2 may include: the gate line 2, the second common routing line 26, and the area between the gate line 2 and the second common routing line 26), that is, the orthographic projection of the first transistor T1 on the substrate 1 may overlap with the orthographic projection of the gate line 2 on the substrate 1, overlap with the orthographic projection of the second common routing line 26 on the substrate 1, and overlap with the orthographic projection of the area between the gate line 2 and the second common routing line 26 on the substrate 1.

[0142] Specifically, in a sub-pixel row, the third transistor T3 may be electrically connected only to the second transistor T2 , as shown in FIG5A . In another possible implementation, the third transistor T3 may also be electrically connected only to the first transistor T1 .

[0143] In one possible embodiment, referring to Figures 5A to 5F , the first electrode portion P1 is electrically connected to the fourth electrode portion P4, and the second electrode portion P2 is electrically connected to the third electrode portion P3. In another possible embodiment, referring to Figures 6A to 6F , the first electrode portion P1 is electrically connected to the third electrode portion P3, and the second electrode portion P2 is electrically connected to the fourth electrode portion P4.

[0144] In one possible embodiment, as shown in Figures 5A-5F , the array substrate further includes: a first connection portion P5 and a second connection portion P6 extending along the second direction Y; one end of the first connection portion P5 is electrically connected to the first electrode portion P1 and the other end is electrically connected to the fourth electrode portion P4; one end of the second connection portion P6 is electrically connected to the second electrode portion P2 and the other end is electrically connected to the third electrode portion P3. In this manner, the first electrode portion P1 is electrically connected to the fourth electrode portion P4, and the second electrode portion P2 is electrically connected to the third electrode portion P3.

[0145] Specifically, referring to Figures 5A-5F, the first connection portion P5 extends along the second direction Y, and its orthographic projection on the substrate 1 is located on the side of the second electrode portion P2 and the third electrode portion P3; the second connection portion P5 extends along the second direction Y, and its orthographic projection on the substrate 1 is located in the area between the first common routing line 25 and the second common routing line 26.

[0146] In a possible implementation manner, referring to FIG. 5A to FIG. 5F , the array substrate further includes: a first connecting protruding portion P7 connected to the first connecting portion P5 and protruding toward a side of the third transistor T3 ;

[0147] On the sub-pixel row, the first connection protrusions P7 are alternately electrically connected to the first transistor T1 and the second transistor T2, so that the first connection sub-pixel electrode P11 and the second connection sub-pixel electrode P12 are alternately electrically connected to the first transistor T1 and the second transistor T2.

[0148] In a possible implementation, referring to FIG. 5A to FIG. 5F , in a sub-pixel row, the outer edge extension lines of adjacent first connection protrusions P7 along the first direction X do not overlap.

[0149] In a possible implementation, referring to FIG. 6A to FIG 6F , the first electrode portion P1 is electrically connected to the third electrode portion P3 to form a first connected sub-pixel electrode P11 ; the second electrode portion P2 is electrically connected to the fourth electrode portion P4 to form a second connected sub-pixel electrode P12 .

[0150] In one possible embodiment, referring to Figures 6A-6F , the array substrate further includes: a third connection portion P8 extending along the second direction Y, and a fourth connection portion P9; one end of the third connection portion P8 is electrically connected to the first electrode portion P1, and the other end is electrically connected to the side of the third electrode portion P3 facing the second electrode portion P2; one end of the fourth connection portion P9 is electrically connected to the second electrode portion P2, and the other end is electrically connected to the fourth electrode portion P4. Optionally, as shown in Figures 6A, 6D, and 6F , the orthographic projection of the fourth connection portion P9 on the substrate 1 overlaps with the second electrode T2b of the second transistor; the orthographic projection of the fourth connection portion P9 on the substrate 1 at least partially overlaps with the orthographic projection of the third common trace 27 on the substrate 1; and the orthographic projection of the third connection portion P8 on the substrate 1 overlaps with the orthographic projection of the third common trace 27 on the substrate 1.

[0151] In a possible embodiment, in combination with Figures 6A, 6D, and 6F, in a sub-pixel P (such as the left sub-pixel P in Figure 6F), one end of the third connection portion P8 is electrically connected to the end of the first electrode portion P1 facing the second electrode portion P2, bypasses one side of the second electrode portion P2, and is electrically connected to the end of the third electrode portion P3 facing the second electrode portion P2, that is, the third connection portion P8 is located at the right edge of the sub-pixel P; in another adjacent sub-pixel P (such as the middle sub-pixel P in Figure 6F), one end of the third connection portion P8 is electrically connected to the end of the first electrode portion P1 facing the second electrode portion P2, passes through the area between the first transistor T1 and the third transistor T3, bypasses one side of the second electrode portion P2 and is electrically connected to the third electrode portion P3, that is, the third connection portion P8 is located at the left edge of the sub-pixel P.

[0152] In a possible embodiment, in combination with Figures 6A, 6D, and 6F, in a sub-pixel P (such as the left sub-pixel P in Figure 6F), one end of the fourth connection portion P9 is electrically connected to one end of the second electrode portion P2 facing the third electrode portion P3, passes through the area between the first transistor T1 and the third transistor T3, bypasses one side of the third electrode portion P3, and is electrically connected to the fourth electrode portion P4, that is, the fourth connection portion P9 is located at the left edge of the sub-pixel P; in another adjacent sub-pixel P (such as the middle sub-pixel P in Figure 6F), one end of the fourth connection portion P9 is electrically connected to one end of the second electrode portion P2 facing the third electrode portion P3, bypasses one side of the third electrode portion P3, and is electrically connected to one end of the fourth electrode portion P4 facing the third electrode portion P3, that is, the fourth connection portion P9 is located at the right edge of the sub-pixel P.

[0153] Specifically, referring to Figures 6A to 6F, the third connection portion P8 extends along the second direction Y, and is located on the side of the second electrode portion P2 in the orthographic projection of the substrate 1; the fourth connection portion P9 is located in the orthographic projection of the substrate 1, partially in the area between the first common wiring 25 and the second common wiring 26, and partially on the side of the third electrode portion P3.

[0154] In one possible embodiment, as shown in FIG. 7 , the plurality of sub-pixels include: a sub-pixel column extending along a second direction Y and arranged along a first direction X; within the sub-pixel column, primary pixel portions PA and secondary pixel portions PB are alternately arranged. In the disclosed embodiment, the alternating arrangement of primary pixel portions PA and secondary pixel portions PB within the sub-pixel column can create a 2P8D effect, whereby the two sub-pixels in the first direction X compensate for each other's brightness and darkness. Simultaneously, a bright / dark compensation effect can also be achieved in the second direction Y, thereby achieving both improved transmittance and improved color shift.

[0155] In one possible embodiment, as shown in FIG8 , the plurality of sub-pixels include: a sub-pixel column extending along a second direction Y and arranged along the first direction; within the sub-pixel column, two primary pixel portions PA and two secondary pixel portions PB are alternately arranged. In the disclosed embodiment, the alternating arrangement of the two primary pixel portions PA and two secondary pixel portions PB within the sub-pixel column can also create a 2P8D effect in which light and dark compensate for each other in the first direction X, while also creating a light and dark compensation effect in the second direction Y, thereby achieving both improved transmittance and improved color cast.

[0156] In a possible embodiment, referring to Figures 9A to 9H, the array substrate further includes: a first electrode layer 7; the first electrode layer 7 includes: a first electrode connecting portion 71, a first hollow 72, and a second hollow 73; the orthographic projection of the first hollow 72 on the substrate 1 at least partially overlaps with the orthographic projection of the first sub-pixel electrode 41 on the substrate 1; the orthographic projection of the second hollow 73 on the substrate 1 at least partially overlaps with the orthographic projection of the second sub-pixel electrode 42 on the substrate 1. In the embodiment of the present disclosure, for a display panel in a VA display mode in which an array substrate is provided with a pixel electrode layer and a counter substrate is provided with a common electrode layer, the same pixel electrode has a first hollow 72 and a second hollow 73, and the pressure difference is different from that in the position without the first hollow 72 and the second hollow 73, so that the liquid crystal twisting can be more uniform, the dark lines corresponding to the pixel electrode can be reduced, the width of the black matrix can be reduced, and the transmittance of the display panel can be improved; in addition, in addition to the vertical electric field formed by the pixel electrode and the common electrode in the array substrate, the pixel electrode and the first electrode layer 7 will form a lateral electric field, which can increase the deflection direction of the liquid crystal and improve the color deviation problem of the display panel.

[0157] In a possible embodiment, referring to Figures 9A to 9H, the first electrode layer 7 further includes: a third hollow 74, so that the first sub-pixel electrode 41 (or the second sub-pixel electrode 42, or the first electrode portion P1, or the second electrode portion P2, or the third electrode portion P3, or the fourth electrode portion P4) above the first electrode layer 7 is conductively connected to the second electrode T1b of the first transistor or the second electrode T2b of the second transistor below the first electrode layer 7 at the third hollow 74.

[0158] Specifically, the first electrode layer 7 can be located between the substrate 1 and the pixel electrode layer. Specifically, the first electrode layer 7 can carry the same signal as the common electrode layer of the opposite substrate. Specifically, the first electrode layer 7 can be a transparent electrode layer, and the material of the first electrode layer 7 can be indium tin oxide.

[0159] In one possible implementation, referring to Figures 9A-9G , the orthographic projection of the first electrode connecting portion 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1. In the disclosed embodiment, the orthographic projection of the first electrode connecting portion 71 on the substrate 1 covers the orthographic projection of the data line 3 on the substrate 1. The first electrode connecting portion 71 can shield the coupling capacitance between the pixel electrode and the data line 3, thereby avoiding the need to provide the third common trace 27, and thereby increasing the transmittance of the display panel.

[0160] In a possible embodiment, a first electrode layer 7 may be provided in the array substrate structure shown in FIG5A and FIG6A , and the orthographic projection of the first hollow 72 of the first electrode layer 7 on the substrate may overlap with the orthographic projection of the first electrode portion P1 and the second electrode portion P2 on the substrate 1, and the orthographic projection of the second hollow 73 of the first electrode layer 7 on the substrate may overlap with the orthographic projection of the third electrode portion P3 and the fourth electrode portion P4 on the substrate 1.

[0161] 1G , 2G , 3G , 4G , 5G and 9J , the disclosed embodiment performs optical simulations on different array substrate structures. By comparing the horizontal dark stripes in the center of the sub-pixels, it can be clearly seen that for the array substrate structures corresponding to FIG. 1G , 2G , 3G , 4G and 5G without the first electrode layer 7 , the transmittance corresponding to the structure of FIG. 1A is the highest, and the simulated value can be 6.34%; and for the corresponding array substrate structure with the first electrode layer 7 , as shown in FIG. 9J , the transmittance is even higher, and the simulated value can be 6.95%.

[0162] Based on the same inventive concept, an embodiment of the present disclosure also provides a display panel, as shown in Figure 11, including an array substrate as provided in an embodiment of the present disclosure, and also including an opposing substrate arranged opposite to the array substrate, and the opposing substrate is provided with a common electrode layer 8 on the side facing the array substrate.

[0163] Specifically, the first common wiring 25 , the second common wiring 26 , the third common wiring 27 , and the first electrode layer 7 may be loaded with the same signal as the common electrode layer 8 of the opposite substrate.

[0164] In a possible embodiment, in combination with Figures 9A to 9G and Figure 11, the data line 3 can be located on the side of the gate line 2 away from the substrate 1, the first electrode layer 7 can be located on the side of the data line 3 away from the gate line 2, the pixel electrode (including the first electrode portion P1, the second electrode portion P2, the third electrode portion P3, and the fourth electrode portion P4) can be located on the side of the first electrode layer 7 away from the data line 3, and a gate insulating layer can be provided between the layer where the gate line 2 is located and the layer where the data line 3 is located. An active layer can be provided between the gate insulating layer and the data line 3 (the active layer can include an active pattern 5, and the active layer material can be amorphous silicon, low-temperature polycrystalline silicon, metal oxide, etc., which is not limited here). A first insulating layer 91 can be provided between the data line 3 and the first electrode layer 7, and a second insulating layer 92 can be provided between the first electrode layer 7 and the pixel electrode.

[0165] In one possible implementation, as shown in conjunction with Figures 9A to 9I and Figure 11 , the display panel may further be provided with a black matrix 6, and the orthographic projection of the black matrix 6 on the substrate 1 may cover the orthographic projection of the gate line 2 on the substrate 1, and cover the orthographic projection of the data line 3 on the substrate 1. Specifically, the counter substrate may include a counter substrate 80, and the black matrix 6 may be located between the counter substrate 80 and the common electrode layer 8 (not shown in Figure 11 ).

[0166] In a possible embodiment, as shown in Figure 11, the first electrode layer 7 is located on the side of the pixel electrode (including the first electrode portion P1, the second electrode portion P2, the third electrode portion P3, and the fourth electrode portion P4) away from the opposite substrate. In this public embodiment, the first electrode layer 7 is located on the side of the pixel electrode away from the opposite substrate, which can isolate (or shield) the first overlapping capacitance between the pixel electrode and the gate line 2 and the second overlapping capacitance between the pixel electrode and the data line 3, greatly reducing the risk of crosstalk. At the same time, due to the presence of the first electrode layer 7, the distance between the pixel electrodes can be reduced, so that the pixel electrode and the gate line 2 overlap (overlap), the pixel electrode and the data line 3 overlap (overlap), reducing the risk of liquid crystal light leakage, thereby reducing the width of the black matrix, increasing the pixel aperture ratio, and improving the pixel transmittance.

[0167] Based on the same inventive concept, the present disclosure also provides a display device, which includes the display panel provided in the present disclosure. The implementation of the display device can refer to the above-mentioned display panel embodiment, and the repeated parts are not repeated here.

[0168] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0169] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0170] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of sub-pixels are located on one side of the substrate, the plurality of sub-pixels include: a sub-pixel row extending along a first direction and arranged along a second direction; at least one of the sub-pixels includes: a main pixel portion distributed along the second direction, and an auxiliary pixel portion, wherein the brightness of the main pixel portion is greater than the brightness of the auxiliary pixel portion, and in the sub-pixel row, the main pixel portion and the auxiliary pixel portion are alternately arranged.

2. The array substrate according to claim 1, wherein: The array substrate comprises: a gate line extending along the first direction, a data line extending along the second direction, a first common line distributed on one side of the gate line and extending along the first direction, and a second common line distributed on the other side of the gate line and extending along the first direction; The sub-pixel comprises: a first sub-pixel electrode, a second sub-pixel electrode, a first transistor electrically connected to the first sub-pixel electrode, a second transistor electrically connected to the second sub-pixel electrode, and a third transistor electrically connected to one of the first transistor and the second transistor; the first sub-pixel electrode and the first common wiring are located on the same side of the gate line, and the second sub-pixel electrode and the second common wiring are located on the same side of the gate line; On the sub-pixel row, the third transistors of the plurality of sub-pixels are alternately distributed in a first area and a second area in the orthographic projection of the substrate; wherein the first area includes: the gate line, the first common routing line, and an area between the gate line and the first common routing line; and the second area includes: the gate line, the second common routing line, and an area between the gate line and the second common routing line.

3. The array substrate according to claim 1 or 2, wherein: In the sub-pixel row, the third transistors of a plurality of the sub-pixels are alternately electrically connected to the first common wiring and the second common wiring.

4. The array substrate according to any one of claims 1 to 3, wherein: The first transistor includes: a first transistor gate, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor gate, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor gate, a third transistor first electrode, and a third transistor second electrode; In the sub-pixel row, the second electrodes of the first transistors and the second electrodes of the second transistors of a plurality of the sub-pixels are alternately reused as the first electrodes of the third transistors.

5. The array substrate according to claim 4, wherein: The plurality of first transistor second electrodes include: a first type second electrode and a second type second electrode; the first type second electrode includes: a first type first portion extending along the first direction, a first type second portion extending from one end of the first type first portion toward one side of the gate line, and a first type third portion extending from the other end of the first type first portion toward one side of the gate line; the second type second electrode includes: a second type first portion extending along the first direction, and a second type second portion extending from one end of the second type first portion toward one side of the gate line; On the sub-pixel row, the first-type second poles and the second-type second poles are alternately distributed.

6. The array substrate according to claim 4 or 5, wherein: The second electrode of the second transistor includes: a third type second electrode and a fourth type second electrode; the third type second electrode includes: a third type first portion extending along the first direction, a third type second portion extending from one end of the third type first portion toward one side of the gate line, and a third type third portion extending from the other end of the third type first portion toward one side of the gate line; the fourth type second electrode includes: a fourth type first portion extending along the first direction, and a fourth type second portion extending from one end of the fourth type first portion toward one side of the gate line; On the sub-pixel row, the third type of second poles and the fourth type of second poles are alternately distributed.

7. The array substrate according to any one of claims 4 to 6, wherein: The first common routing line has a first common outer protrusion facing one side of the gate line, and the orthographic projection of the second electrode of the third transistor on the substrate and the orthographic projection of the first common outer protrusion on the substrate have an overlapping area; the second common routing line has a second common outer protrusion facing one side of the gate line, and the orthographic projection of the second electrode of the third transistor on the substrate and the orthographic projection of the second common outer protrusion on the substrate have an overlapping area; In the sub-pixel row, one sub-pixel is spaced between adjacent first common outer protrusions, one sub-pixel is spaced between adjacent second common outer protrusions, and the first common outer protrusions and the second common outer protrusions are staggered in distribution.

8. The array substrate according to any one of claims 2 to 7, wherein: The first sub-pixel electrode is an integrated structure, and the second sub-pixel electrode is an integrated structure.

9. The array substrate according to claim 8, wherein: The first sub-pixel electrode comprises: a first electrode portion and a second electrode portion sequentially distributed along the second direction; the second sub-pixel electrode comprises: a third electrode portion and a fourth electrode portion sequentially distributed along the second direction; The first electrode portion has a plurality of first slits, the second electrode portion has a plurality of second slits, the third electrode portion has a plurality of third slits, and the fourth electrode portion has a plurality of fourth slits; An extending direction of the first slit is the same as an extending direction of the second slit, an extending direction of the third slit is the same as an extending direction of the fourth slit, and an extending direction of the first slit is different from an extending direction of the third slit.

10. The array substrate according to claim 9, wherein: A fifth slit is further provided between the first electrode portion and the second electrode portion, and an extending direction of the fifth slit is different from an extending direction of the first slit; A sixth slit is further provided between the third electrode portion and the fourth electrode portion, and an extending direction of the sixth slit is different from an extending direction of the third slit.

11. The array substrate according to claim 10, wherein: The fifth slit extends along the second direction, and the sixth slit extends along the second direction.

12. The array substrate according to claim 10, wherein: The fifth slit extends in the same direction as the third slit, and the sixth slit extends in the same direction as the first slit.

13. The array substrate according to claim 9, wherein: The side of the first electrode portion facing the second electrode portion is a semi-closed structure, the side of the second electrode portion facing the first electrode portion is a semi-closed structure, and the closed position of the first electrode portion facing the second electrode portion is opposite to the open position of the second electrode portion facing the first electrode portion, and the open position of the first electrode portion facing the second electrode portion is opposite to the closed position of the second electrode portion facing the first electrode portion.

14. The array substrate according to claim 9, wherein: The first slit of the first electrode portion and the second slit of the second electrode portion are an integral structure; the third slit of the third electrode portion and the fourth slit of the fourth electrode portion are an integral structure.

15. The array substrate according to claim 1, wherein: The array substrate comprises: a gate line extending along the first direction, a data line extending along the second direction, a first common line distributed on one side of the gate line, and a second common line distributed on the other side of the gate line; The sub-pixel comprises: a first transistor, a second transistor, a third transistor electrically connected to one of the first transistor and the second transistor, and a first electrode portion, a second electrode portion, a third electrode portion, and a fourth electrode portion sequentially distributed along the second direction; the first electrode portion is electrically connected to one of the third electrode portion and the fourth electrode portion to form a first connected sub-pixel electrode; the second electrode portion is electrically connected to the other of the third electrode portion and the fourth electrode portion to form a second connected sub-pixel electrode; Among them, on the sub-pixel row, the first connected sub-pixel electrodes of multiple sub-pixels are alternately electrically connected to the first transistor and the second transistor; the second connected sub-pixel electrodes of multiple sub-pixels are alternately electrically connected to the first transistor and the second transistor; and in the same sub-pixel, the first connected sub-pixel electrode and the second connected sub-pixel electrode are electrically connected to different transistors.

16. The array substrate according to claim 15, wherein: The first electrode portion is electrically connected to the fourth electrode portion, and the second electrode portion is electrically connected to the third electrode portion.

17. The array substrate according to claim 16, wherein: The array substrate further includes: a first connecting portion extending along the second direction, and a second connecting portion; One end of the first connection portion is electrically connected to the first electrode portion, and the other end is electrically connected to the fourth electrode portion; one end of the second connection portion is electrically connected to the second electrode portion, and the other end is electrically connected to the third electrode portion.

18. The array substrate according to claim 17, wherein: The array substrate further includes: a first connecting outer protrusion connected to the first connecting portion and protruding toward one side of the third transistor; On the sub-pixel row, the first connection protrusions are electrically connected to the first transistors and the second transistors alternately.

19. The array substrate according to claim 18, wherein: In the sub-pixel row, outer edge extension lines of adjacent first connecting outer protrusions along the first direction do not overlap.

20. The array substrate according to claim 15, wherein: The first electrode portion is electrically connected to the third electrode portion, and the second electrode portion is electrically connected to the fourth electrode portion.

21. The array substrate according to claim 20, wherein: The array substrate further includes: a third connection portion extending along the second direction, and a fourth connection portion; The third connection portion has an orthographic projection of the substrate located on one side of the orthographic projection of the first sub-pixel electrode on the substrate, and one end of the third connection portion is electrically connected to the first electrode portion, and the other end of the third connection portion is electrically connected to a side of the third electrode portion facing the second electrode portion; One end of the fourth connection portion is electrically connected to the second electrode portion, and the other end thereof is electrically connected to the fourth electrode portion.

22. The array substrate according to any one of claims 1 to 21, wherein: The plurality of sub-pixels include: a sub-pixel column extending along the second direction and arranged along the first direction; in the sub-pixel column, the main pixel portion and the auxiliary pixel portion are alternately arranged.

23. The array substrate according to any one of claims 1 to 21, wherein: The plurality of sub-pixels include: a sub-pixel column extending along the second direction and arranged along the first direction; in the sub-pixel column, two main pixel portions and two auxiliary pixel portions are alternately arranged.

24. The array substrate according to any one of claims 2 to 14, wherein: The array substrate further includes: a first electrode layer; the first electrode layer includes: a first electrode connecting portion, a first hollowing, and a second hollowing; The orthographic projection of the first hollow on the substrate at least partially overlaps with the orthographic projection of the first sub-pixel electrode on the substrate; the orthographic projection of the second hollow on the substrate at least partially overlaps with the orthographic projection of the second sub-pixel electrode on the substrate.

25. The array substrate according to claim 24, wherein: The orthographic projection of the first electrode connecting portion on the substrate covers the orthographic projection of the data line on the substrate.

26. A display panel, wherein: It comprises the array substrate as claimed in any one of claims 1 to 25, and further comprises an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

27. The display panel according to claim 26, wherein: The first electrode layer and the common electrode layer are loaded with the same signal.

28. A display device, wherein: Comprising the display panel as claimed in claim 26 or 27.

Images