Wiring substrate, light-emitting substrate, and display device

Abstract

Disclosed in the present disclosure are a wiring substrate, a light-emitting substrate, and a display device, which are used to avoid poor brightness of a last-stage lamp area in a cascade lamp area. The wiring substrate comprises a base substrate, and the base substrate is divided into a functional area and a binding area. The functional area comprises a bonding pad unit, and the bonding pad unit comprises a first bonding pad area and a second bonding pad area. The functional area comprises a plurality of wires arranged on the same layer, and the wires comprise a first input line, a first output line, a second input line, and a cascade line. A plurality of input bonding pads arranged in a first direction are connected to the same first input line, a plurality of output bonding pads arranged in the first direction are connected to the same first output line, two first bonding pad areas adjacent to each other in the first direction are connected by means of the cascade line, and input ends of a plurality of second bonding pad areas arranged in the first direction are connected to the same second input line. In the functional area, in a second direction, one side of the first output line is arranged adjacent to the first input line, and the other side of the first output line is arranged adjacent to another first output line or the second input line.

Description

Wiring substrate, light-emitting substrate, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on July 31, 2023, with application number 202310960565.3 and invention name "Wiring substrate, light-emitting substrate and display device", the entire content of which is incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a wiring substrate, a light-emitting substrate, and a display device. Background Art

[0004] Micro light-emitting diodes have a significant increase in usage in the display field due to their smaller size, ultra-high brightness, and long life.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a wiring substrate, a light-emitting substrate, and a display device to avoid poor brightness of the last-stage lamp area in the cascade lamp area.

[0007] An embodiment of the present disclosure provides a wiring substrate, including a substrate, wherein the substrate is divided into a functional area and a binding area;

[0008] The functional area includes a plurality of pad units arranged along a first direction and a second direction respectively, the pad unit including: a first pad area and a second pad area electrically connected to the first pad area; the second direction intersects the first direction;

[0009] The functional area also includes a plurality of routing lines arranged on the same layer, the plurality of routing lines including a plurality of first input lines, a plurality of first output lines, a plurality of second input lines and a plurality of cascade lines;

[0010] The input pads of the plurality of first pad areas arranged along the first direction are connected to the same first input line, the output pads of the plurality of first pad areas arranged along the first direction are connected to the same first output line, two adjacent first pad areas along the first direction are connected via a cascade line, and the input ends of the plurality of second pad areas arranged along the first direction are connected to the same second input line;

[0011] In the functional area, in the second direction, one side of the first output line is adjacent to the first input line, and the other side of the first output line is adjacent to another first output line or the second input line.

[0012] In some embodiments, each first pad area includes a channel pad and an address pad, and multiple cascaded first pad areas, the channel pad of the i-th level first pad area and the address pad of the (i+1)-th level first pad area are connected through a cascade line; where i is a positive integer.

[0013] In some embodiments, a plurality of pad units arranged along the first direction constitute a pad unit column, and a plurality of first pad regions in each pad unit column are sequentially cascaded along the first direction;

[0014] Multiple traces also include multiple feedback lines;

[0015] In at least part of the pad unit columns, the channel pad of the last stage of the plurality of cascaded first pad areas is connected to a feedback line, and the feedback line is not disposed adjacent to the first output line.

[0016] In some embodiments, in adjacent pad unit columns, the cascading directions of the plurality of first pad regions are opposite.

[0017] In some embodiments, the second input line and the first output line connected to the same pad unit column are respectively located on both sides of the pad unit column.

[0018] In some embodiments, the second direction includes 2N pad unit columns;

[0019] The first output line connected to the (2n-1)th pad unit column is adjacent to the first output line connected to the 2nth pad unit column;

[0020] The second input line connected to the 2nth pad unit column is adjacent to the second input line connected to the (2n+1)th pad unit column;

[0021] Wherein, N is a positive integer, and n is a positive integer not greater than N.

[0022] In some embodiments, the plurality of cascade lines include a plurality of first cascade lines and a plurality of second cascade lines;

[0023] The first cascade line is used to connect the pad units that are cascaded in sequence in the pad unit column;

[0024] The second connection line is used to connect the last-level first pad region in the (2n-1)th pad unit column to the first-level first pad region in the 2nth pad unit column.

[0025] In some embodiments, the second cascade line includes: a first portion, a second portion, and a third portion connected in sequence;

[0026] At least a portion of the first portion and the third portion extends along a first direction, and the second portion extends along a second direction;

[0027] The first part is connected to the channel pad of the last first pad area in the (2n-1)th pad unit column, and the third part is connected to the address pad of the first first pad area in the 2nth pad unit column.

[0028] In some embodiments, in the first direction, the second portion is located on a side of the first output line away from the bonding area, the first portion is located on a side of the first output line electrically connected to the (2n-1)th pad unit column away from the bonding area, and the third portion is located on a side of the first output line electrically connected to the 2nth pad unit column away from the bonding area;

[0029] The first output line electrically connected to the (2n-1)th pad unit column is not adjacent to the first portion, and the first output line electrically connected to the 2nth pad unit column is not adjacent to the third portion.

[0030] In some embodiments, the second direction includes 2N pad unit columns;

[0031] The plurality of routing lines further include a plurality of address lines and a plurality of transfer lines, the address lines are connected to the address pads of the first level first pad area in each pad unit column, and the channel pads of the last level first pad area in each pad unit column are connected to a feedback line;

[0032] The plurality of adapter cables include a plurality of first adapter cables and a plurality of second adapter cables;

[0033] The first transfer line is used to electrically connect the feedback line connected to the (2n-1)th pad unit column and the address line connected to the 2nth pad unit column;

[0034] The second transfer line is used to electrically connect the feedback line connected to the 2nth pad unit column and the address line connected to the (2n+1)th pad unit column;

[0035] Wherein, N is a positive integer, and n is a positive integer not greater than N.

[0036] In some embodiments, the feedback line connected to the (2n-1)th pad unit column is located on a side of the first output line connected to the (2n-1)th pad unit column away from the bonding area;

[0037] The first transfer line includes: a fourth portion extending along the second direction, and a fifth portion extending along the first direction in the functional area; a feedback line connected to the (2n-1)th pad unit column is connected to one end of the fourth portion, and the fifth portion is connected to the other end of the fourth portion;

[0038] The second input line connected to the (2n-1)th pad unit column is adjacent to the fifth portion.

[0039] In some embodiments, the address line connected to the 2nth pad unit column is located on a side of the first output line connected to the 2nth pad unit column away from the bonding area;

[0040] The second transfer line includes: a sixth portion extending along the second direction, and a seventh portion extending along the first direction in the functional area; the address line connected to the 2nth pad unit column is connected to one end of the sixth portion, and the seventh portion is connected to the other end of the sixth portion;

[0041] The second input line connected to the 2nth pad unit column is adjacent to the seventh portion.

[0042] In some embodiments, the fifth portion is adjacent to the seventh portion in a region between the second input line connected to the 2nth pad unit column and the second input line connected to the (2n-1)th pad unit column.

[0043] In some embodiments, the first pad area includes address pads, input pads, channel pads, and output pads;

[0044] The address pads and the input pads are located in the same row in the first direction, and the channel pads and the output pads are located in the same row in the first direction; the channel pads and the address pads are located in the same column in the second direction, and the output pads and the input pads are located in the same column in the second direction;

[0045] In the (2n-1)th pad unit column, the address pad and the input pad are located on the side of the channel pad and the output pad close to the binding area in the first direction; after the first pad area in the 2nth pad unit column is rotated 180°, the arrangement method of the first pad area in the (2n-1)th pad unit column is the same; wherein N is a positive integer and n is a positive integer not greater than N.

[0046] In some embodiments, among the address line, the first input line, and the first output line electrically connected to the (2n-1)th pad unit column, in the second direction, the first input line is located between the address line and the first output line;

[0047] Among the feedback line, the first input line, and the first output line corresponding to the 2n-th pad unit column, in the second direction, the first input line is located between the feedback line and the first output line.

[0048] In some embodiments, the second pad region has a center line extending along the first direction;

[0049] The first pad area in the (2n-1)th pad unit column is located on the side of the midline toward the 2nth pad unit column, and the first pad area in the 2nth pad unit column is located on the side of the midline toward the (2n-1)th pad unit column.

[0050] An embodiment of the present disclosure provides a light-emitting substrate, which includes: a wiring substrate provided by an embodiment of the present disclosure, a driving element bound one-to-one with a first pad area, and a light-emitting element bound one-to-one with pad groups in a plurality of second pad areas.

[0051] In some embodiments, the light emitting substrate further comprises:

[0052] The circuit board is bound to the wiring substrate in the binding area; the circuit board includes a plurality of first circuit structures and a plurality of second circuit structures; the wiring substrate includes: a pad unit column, a first transfer line, a second transfer line, an address line, and a feedback line;

[0053] The first transfer line corresponding to the (2n-1)th pad unit column is electrically connected to the address line connected to the 2nth pad unit column through the first circuit structure;

[0054] The second transfer line corresponding to the 2nth pad unit column is electrically connected to the feedback line connected to the 2nth pad unit column through the second circuit structure.

[0055] In some embodiments, the light emitting element is a micro-sized inorganic light emitting diode.

[0056] A display device provided by an embodiment of the present disclosure includes the light-emitting substrate provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0058] FIG1 is a schematic structural diagram of a light-emitting substrate provided by the related art;

[0059] FIG2 is a schematic diagram of a light-emitting substrate feedback line FB and a first output line GND in the related art, in which the feedback line FB is adjacent to the first output line GND and is weakly conductive;

[0060] FIG3 is a schematic structural diagram of a wiring substrate provided in an embodiment of the present disclosure;

[0061] FIG4 is a schematic diagram of the enlarged structure of area A in FIG3 ;

[0062] FIG5 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0063] FIG6 is an enlarged structural diagram of area C in FIG5 ;

[0064] FIG7 is a schematic structural diagram of another wiring substrate provided in an embodiment of the present disclosure;

[0065] FIG8 is a schematic diagram of the enlarged structure of the D area in FIG7;

[0066] FIG9 is a schematic structural diagram of a light-emitting substrate provided in an embodiment of the present disclosure;

[0067] FIG10 is a schematic structural diagram of another light-emitting substrate provided in an embodiment of the present disclosure;

[0068] FIG11 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0070] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0071] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0072] In the related art, a column of lamp areas of a light-emitting substrate constitutes an address loop, that is, a plurality of lamp areas in a column of lamp areas are cascaded, and each lamp area includes a first pad area and a second pad area, the first pad area is bound to the driving element, and the second pad area is bound to the light-emitting device. As shown in FIG1 , the first output line GND is connected to the output pad gnd of the first pad area 201, the first pad area 201 and the second pad area 202 of the cascaded final lamp area are connected to the feedback line FB, the feedback line FB and the first output line GND, and the feedback line FB and the first output line GND are arranged on the same layer. Usually, an insulating layer is provided between the feedback line FB and the first output line GND to insulate the feedback line FB from the first output line GND. However, since the feedback line FB is adjacent to the first output line GND and the distance between the two is very close, when the insulation resistance between the feedback line FB and the first output line GND is less than 10 9 If the voltage is ohmic (Ω), the feedback line FB and the first output line GND will form a weak conduction. When the input end of the second pad area is connected to the second input line VLED, but the driver element does not provide voltage, the light-emitting device will not emit light under normal circumstances. However, in the cascaded final lamp area, the feedback line FB is adjacent to the first output line GND and forms a weak conduction. The second input line VLED second pad area 202, the light-emitting device 8, the feedback line FB, and the first output line GND will form a conduction path, namely the path shown by the dotted line 7 in Figure 2. The conduction current can reach the lighting current of the light-emitting device. Therefore, the light-emitting device in the final lamp area of ​​the cascade emits light. Although the brightness is low, it is still noticeable. In other words, the light-emitting substrate has a weak brightness problem in the final lamp area, affecting the display effect and the user experience.

[0073] The embodiment of the present disclosure provides a wiring substrate, as shown in FIG3 to FIG8 , including a substrate 1 , which is divided into a functional area 101 and a binding area 102 ;

[0074] The functional area 101 includes a plurality of pad units 2 arranged along a first direction Y and a second direction X, respectively. The pad unit 2 includes: a first pad area 201 and a second pad area 202 electrically connected to the first pad area 201; the second direction X intersects the first direction Y;

[0075] The functional area 101 further includes a plurality of traces 3 provided on the same layer, the plurality of traces 3 including a plurality of first input lines PWR, a plurality of first output lines GND, a plurality of second input lines VLED and a plurality of cascade lines 301;

[0076] The input pads pwr of the plurality of first pad areas 201 arranged along the first direction Y are connected to the same first input line PWR, the output pads gnd of the plurality of first pad areas 201 arranged along the first direction Y are connected to the same first output line GND, two adjacent first pad areas 201 along the first direction Y are connected via a cascade line 301, and the input ends of the plurality of second pad areas 202 arranged along the first direction Y are connected to the same second input line VLED;

[0077] In the functional area 101 , in the second direction X, one side of the first output line GND is adjacent to the first input line PWR, and the other side of the first output line GND is adjacent to another first output line GND or the second input line VLED.

[0078] It should be noted that the wiring substrate provided in the embodiments of the present disclosure can be applied to a light-emitting substrate. Each second pad area includes at least one pad group, each pad group includes a positive pad and a negative pad, and each pad group is bound to a light-emitting device. The first pad area includes multiple pads, and the multiple pads are bound to a driver chip, so that the light-emitting device can be driven to emit light under the control of the driver chip. For example, a driver chip can control each light-emitting device in a corresponding second pad area to emit light. The area occupied by multiple pads bound to a driver chip is the first pad area, and the pad group corresponding to the light-emitting device controlled by the driver chip and the area surrounded by it are the second pad area.

[0079] In the wiring substrate provided by the embodiments of the present disclosure, one side of the first output line is adjacent to the first input line PWR, and the other side is adjacent to another first output line or a second input line. That is, the first output line is not adjacent to the feedback line. Therefore, when the wiring substrate is used in a light-emitting substrate, this can prevent weak conduction between the feedback line and the first output line, which would cause the light-emitting device, the pad group, the feedback line, and the first output line to be connected, thereby preventing the light-emitting device from being illuminated and the phenomenon of the light-emitting area corresponding to the second pad area of ​​the final cascade stage being weak and poorly illuminated, thereby improving the display effect and enhancing the user experience.

[0080] It should be noted that FIG4 is an enlarged schematic diagram of area A in FIG3 , FIG6 is an enlarged schematic diagram of area C in FIG5 , and FIG8 is an enlarged schematic diagram of area D in FIG7 .

[0081] In some embodiments, as shown in Figures 3 and 4, the second pad area 202 includes multiple pad groups 2021; for example, multiple pad groups 2021 are connected in series; each pad group 2021 includes a positive pad 20211 and a negative pad 20212. Of two connected pad groups 2021, the positive pad 20211 of one pad group 2021 is connected to the negative pad 20212 of the other pad group 2021. Figures 3 to 8 illustrate an example in which the second pad area 202 includes four pad groups 2021 connected in series. As shown in Figures 4, 6, and 8, the four pad groups 2021 are B1, B2, B3, and B4, respectively. The negative pad 20212 of the B1 pad group 2021 is connected to the positive pad 20211 of the B2 pad group 2021 , the negative pad 20212 of the B2 pad group 2021 is connected to the positive pad 20211 of the B3 pad group 2021 , and the negative pad 20212 of the B3 pad group 2021 is connected to the positive pad 20211 of the B4 pad group 2021 .

[0082] It should be noted that the input end of the second pad area refers to the positive pad of one of the pad groups included in the second pad area. As shown in Figures 3 to 8, when multiple pad groups 2021 included in the second pad area 202 are connected in series, the positive pad 20211 of the first second pad group 2021 in the multiple series-connected second pad groups 2021, i.e., the B1 pad group 2021 in Figure 4, is connected to the second input line VLED, and the negative pad 20212 of the last second pad group 2021 in the multiple series-connected second pad groups 2021, i.e., the B4 pad group 2021 in Figures 4, 6, and 8, is connected to the first pad area 201.

[0083] Of course, in specific implementation, multiple pad groups can also be connected in parallel.

[0084] In some embodiments, as shown in FIG. 3 , FIG. 5 , and FIG. 7 , a plurality of pad units 2 arranged along the first direction Y constitute a pad unit column 4 , and a plurality of first pad regions 201 in each pad unit column 4 are sequentially cascaded along the first direction Y.

[0085] It should be noted that only four pad unit columns 4 are shown for illustration in Figures 3, 5 and 7. In a specific implementation, the number of pad unit columns included in the wiring substrate can be set according to actual needs.

[0086] In some embodiments, as shown in Figures 3 to 5, each first pad area 201 includes a channel pad OT and an address pad Di, and multiple cascaded first pad areas 201, the channel pad OT of the i-th level first pad area 201 and the address pad Di of the (i+1)-th level first pad area 201 are connected through a cascade line 301; wherein i is a positive integer.

[0087] In a specific implementation, the binding area further includes a binding pad electrically connected to at least part of the traces; the binding pad is used for binding to the circuit board.

[0088] It should be noted that a plurality of first pad areas cascaded by cascading lines constitute an addressing loop. In a specific implementation, at least one pad unit column constitutes an addressing loop. In the related art, the first-pole first pad area of ​​each pad unit column is connected to the address line, and the channel pad of the last-level first pad area of ​​each pad unit column is connected to the feedback line. The address line and the feedback line are both electrically connected to the binding pad, so that different address lines and / or feedback lines can be electrically connected through the circuit board, so that multiple columns of first pad groups are cascaded through the feedback line and the circuit board, so that the cascaded multiple columns of first pad groups constitute an addressing loop. Usually, the last-level first pad area of ​​each pad unit column is the first pad area farthest from the binding area in a pad unit column. In order to facilitate wiring, the feedback line extends through the area between the first output line and the second input line to the binding area and is electrically connected to the binding pad, so the feedback line needs to be adjacent to the first output line.

[0089] In some embodiments, as shown in FIG. 3 , a plurality of cascaded first pad regions 201 in each pad unit column 4 constitute an addressing loop, and different pad unit columns 4 constitute different addressing loops.

[0090] That is, in some embodiments, as shown in Figures 3 and 4, the wiring substrate does not include a feedback line. In Figure 3, among the multiple first pad areas 201 cascaded via cascade line 301, the channel pad OT of the last first pad area 201 is connected solely via second output line 303 to the negative electrode pad 20212 of the last second pad group 2021 in the multiple series-connected second pad groups 2021, namely, the B4 pad group 2021 in Figure 4. Therefore, as shown in Figure 3, in functional area 101, in the second direction X, one side of the first output line GND is adjacent to the first input line PWR, and the other side of the first output line GND is adjacent to the second input line VLED.

[0091] It should be noted that, as shown in FIG3 , the substrate 1 further includes: a first border region 103 located away from the binding region 102 in the first direction Y from the functional region 101; and a second border region 104 and a third border region 105 located on either side of the functional region in the second direction X. Among the multiple pad unit columns 4 arranged in the second direction X, the second input line VLED of the first pad unit column 4 is located in the third border region 105, and the first output line GND of the last pad unit column 4 is located in the second border region 104.

[0092] In some embodiments, as shown in FIG3 , trace 3 further includes an electrostatic shielding line 304, which extends from one side of the binding area 102 to the third border area 105, the first border area 103, the second border area 104, and then back to the other side of the binding area 102. In the third border area 105, the second input line VLED is adjacent to the electrostatic shielding line 304, and the electrostatic shielding line 304 is located on the side of the second input line VLED that faces away from the functional area 101. In the second border area 104, the first output line GND is adjacent to the electrostatic shielding line 304, and the electrostatic shielding line 304 is located on the side of the first output line GND that faces away from the functional area 101.

[0093] That is, the wiring substrate provided in the embodiment of the present disclosure removes the feedback line, thereby avoiding the light-emitting device, the pad group, the feedback line and the first output line being connected and lit due to the weak conduction between the feedback line and the first output line without changing the pad unit and wiring layout of the wiring substrate, and avoiding the phenomenon of weak brightness of the light-emitting area corresponding to the second pad area of ​​the last stage of the cascade, thereby improving the display effect and enhancing the user experience.

[0094] Alternatively, in some embodiments, a plurality of pad unit columns constitute an addressing loop.

[0095] In some embodiments, as shown in FIG5 and FIG7 , the plurality of traces 3 further include a plurality of feedback lines FB;

[0096] In at least part of the pad unit columns, the channel pad OT of the last stage of the plurality of cascaded first pad areas 201 is connected to a feedback line FB, and the feedback line FB is not disposed adjacent to the first output line GND.

[0097] In the wiring substrate provided by the embodiment of the present disclosure, in at least some of the pad unit columns, the channel pads of the last-stage first pad area in the plurality of cascaded first pad areas are connected to a feedback line, so that different pad unit columns can be cascaded through the feedback line. Moreover, since the feedback line is not adjacent to the first output line, even if the feedback line is provided, it will not cause weak conduction between the feedback line and the first output line. As a result, the light-emitting device, the pad group, the feedback line and the first output line will not be connected and illuminated, avoiding the phenomenon of weak brightness of the light-emitting area corresponding to the last-stage second pad area of ​​the cascade, thereby improving the display effect and enhancing the user experience.

[0098] In some embodiments, as shown in FIG5 and FIG7 , the plurality of traces 3 further include a plurality of address lines addr;

[0099] In at least part of the pad unit columns, the address pads Di of the first-stage first pad areas 201 in the plurality of cascaded first pad areas 201 are connected to an address line addr.

[0100] In some embodiments, as shown in FIG. 5 and FIG. 7 , in adjacent pad unit columns 4 , the cascading directions of the plurality of first pad regions 201 are opposite.

[0101] This facilitates cascading between two adjacent pad unit columns. Furthermore, since the cascading directions of the multiple first pad areas in adjacent pad unit columns are opposite, the final first pad area of ​​some pad unit columns can be set to be located in the area closest to the binding area in the pad unit column, so that the feedback line connected to the final first pad area of ​​some pad unit columns extends directly from the functional area to the binding area without passing through the area between adjacent pad unit columns to extend to the binding area, thereby eliminating the need for the feedback line FB to be adjacent to the first output line GND. This can prevent the feedback line and the first output line from being weakly conductive, which would cause the light-emitting device, pad group, feedback line, and first output line to be conductive and illuminated, and avoid the phenomenon of the light-emitting area corresponding to the final second pad area of ​​the cascade being weak and poorly lit, thereby improving the display effect and user experience.

[0102] During specific implementation, as shown in Figures 5 and 7, in the odd-numbered pad unit columns 4, the first-level first pad area 201 is the first pad area 201 in the pad unit column 4 closest to the binding area 102, and the last-level first pad area 201 is the first pad area 201 in the pad unit column 4 farthest from the binding area 102; in the even-numbered pad unit columns 4, the first-level first pad area 201 is the first pad area 201 in the pad unit column 4 farthest from the binding area 102, and the last-level first pad area 201 is the first pad area 201 in the pad unit column 4 close to the binding area 102.

[0103] In some embodiments, as shown in FIG. 5 and FIG. 7 , the second input line VLED and the first output line GND connected to the same pad unit column 4 are respectively located on both sides of the pad unit column 4 .

[0104] In some embodiments, the second direction X includes 2N pad unit columns.

[0105] In some embodiments, as shown in FIG6 and FIG8 , the first pad area 201 includes an address pad Di, an input pad pwr, a channel pad OT, and an output pad gnd;

[0106] The address pad Di and the input pad pwr are located in the same row in the first direction Y, and the channel pad OT and the output pad gnd are located in the same row in the first direction Y; the channel pad OT and the address pad Di are located in the same column in the second direction X, and the output pad gnd and the input pad pwr are located in the same column in the second direction X;

[0107] In the (2n-1)th pad unit column 4, the address pad Di and the input pad pwr are located on the side of the channel pad OT and the output pad gnd close to the binding area 102 in the first direction Y; the first pad area 201 in the 2nth pad unit column 4 is rotated 180° and has the same arrangement as the first pad area 201 in the (2n-1)th pad unit column 4; wherein N is a positive integer and n is a positive integer not greater than N.

[0108] That is, in the wiring substrate provided by the embodiments of the present disclosure, the arrangement sequence of the pads in the first pad area of ​​the odd-numbered pad unit columns is different from the arrangement of the pads in the first pad area of ​​the even-numbered pad unit columns. Accordingly, the positions of the traces corresponding to the even-numbered columns are different from the positions of the traces corresponding to the odd-numbered columns. Compared to the prior art, the embodiments of the present disclosure can change the trace arrangement position of the wiring substrate by changing the arrangement of the pads in the first pad area of ​​the even-numbered pad unit columns, thereby preventing the feedback line from being adjacent to the first output line.

[0109] In some embodiments, as shown in FIG5 and FIG7 , the second pad area 202 has a dividing line 9 extending along the first direction Y. It is understandable that the second pad area 202 includes a plurality of pad groups 2021, and a closed figure can be obtained by sequentially connecting the geometric centers of the plurality of pad groups 2021 located at the edge of the second pad area 202. The dividing line 9 can divide the area of ​​the closed figure into two and along the dividing line, or the dividing line 9 coincides with the axis of symmetry of the closed figure, or the second pad area 202 is divided into two sub-areas with the dividing line 9 as the boundary, and each sub-area includes the same number of pad groups 2021.

[0110] The first pad area 201 in the (2n-1)th pad unit column 4 is located on the side of the dividing line 9 toward the 2nth pad unit column 4, and the first pad area 201 in the 2nth pad unit column 4 is located on the side of the dividing line 9 toward the (2n-1)th pad unit column 4. That is, the first pad area 201 in the (2n-1)th pad unit column 4 is located at the edge of the (2n-1)th pad unit column 4 on the side close to the 2nth pad unit column 4, and the first pad area 201 in the 2nth pad unit column 4 is located at the edge of the 2nth pad unit column 4 on the side close to the (2n-1)th pad unit column 4. The first pad area 201 in the pad unit columns 4 in the odd-numbered columns is located on the left side of the dividing line 9, and the first pad area 201 in the pad unit columns 4 in the even-numbered columns is located on the right side of the dividing line 9.

[0111] In some embodiments, as shown in FIG5 and FIG7 , the first output line GND connected to the (2n-1)th pad unit column 4 and the first output line GND connected to the 2nth pad unit column 4 are adjacent;

[0112] Between the 2nth pad unit column 4 and the (2n+1)th pad unit column 4, the second input line VLED connected to the 2nth pad unit column 4 and the second input line VLED connected to the (2n+1)th pad unit column 4 are arranged opposite to each other;

[0113] Wherein, N is a positive integer, and n is a positive integer not greater than N.

[0114] In the wiring substrate provided by the embodiment of the present disclosure, the arrangement sequence of the pads in the first pad area of ​​the odd-numbered pad unit column is different from the arrangement sequence of the pads in the first pad area of ​​the even-numbered pad unit column. After the first pad area in the even-numbered pad unit column is rotated 180°, the arrangement sequence is the same as the first pad area in the odd-numbered pad unit column, and the first pad area in the odd-numbered pad unit column is located at the left edge of the pad unit column, and the first pad area in the even-numbered pad unit column is located at the right edge of the pad unit column. Accordingly, the first output line GND connected to the odd-numbered pad unit column is located on the right side of the pad unit column, the second input line VLED connected to the odd-numbered pad unit column is located on the left side of the pad unit column, the first output line GND connected to the even-numbered pad unit column is located on the left side of the pad unit column, and the second input line VLED connected to the even-numbered pad unit column is located on the right side of the pad unit column. Thus, between the (2n-1)th pad unit column and the 2nth pad unit column, the first output line GND connected to the (2n-1)th pad unit column and the first output line GND connected to the 2nth pad unit column are adjacent; between the 2nth pad unit column and the (2n+1)th pad unit column, the second input line VLED connected to the 2nth pad unit column and the second input line VLED connected to the (2n+1)th pad unit column are arranged opposite each other. Compared to the prior art, the embodiment of the present disclosure changes the arrangement of each pad in the first pad area of ​​the even-numbered pad unit columns, thereby changing the wiring arrangement position of the wiring substrate, so that the first output line GND connected to the (2n-1)th pad unit column and the first output line GND connected to the 2nth pad unit column are adjacent, thereby preventing the first output line from being adjacent to the feedback line, thereby avoiding weak conduction between the feedback line and the first output line. As a result, the light-emitting device, the pad group, the feedback line and the first output line will not be turned on by being connected, and the phenomenon of the light-emitting area corresponding to the second pad area of ​​the last stage of the cascade being weak and poorly lit can be avoided, thereby improving the display effect and enhancing the user experience.

[0115] In some embodiments, as shown in Figures 6 and 8, the address pad Di and the input pad pwr are located in the same row in the first direction Y, and in the odd-numbered pad unit column 4, the address pad Di is located to the left of the input pad pwr, and in the even-numbered pad unit column 4, the address pad Di is located to the right of the input pad pwr; the channel pad OT and the output pad gnd are located in the same row in the first direction Y, and in the odd-numbered pad unit column 4, the channel pad OT is located to the left of the output pad gnd, and in the even-numbered pad unit column 4, the channel pad OT is located to the right of the output pad gnd; the channel pad OT and the address pad Di are located in the same column in the second direction X, and in the odd-numbered pad unit column 4, the channel pad OT is located far from the address pad Di. On the side away from the binding area (not shown in Figures 6 and 8), in the even-numbered pad unit column 4, the channel pad OT is located on the side of the address pad Di close to the binding area; the output pad gnd and the input pad pwr are located in the same column in the second direction X, in the odd-numbered pad unit column 4, the output pad gnd is located on the side of the input pad pwr away from the binding area, and in the even-numbered pad unit column 4, the output pad gnd is located on the side of the input pad pwr close to the binding area; since the first output line GND is connected to the output pad gnd, the first input line PWR is connected to the input pad pwr, the channel pad OT of the i-th level first pad area 201 is connected to the address pad Di of the (i+1)-th level first pad area 201 through the cascade line 301.

[0116] Accordingly, in some embodiments, as shown in Figures 5 and 7, among the address line addr, the first input line PWR, and the first output line GND electrically connected to the (2n-1)th pad unit column 4, in the second direction X, the first input line PWR is located between the address line addr and the first output line GND; among the feedback line FB, the first input line PWR, and the first output line GND corresponding to the 2nth pad unit column 4, in the second direction X, the first input line PWR is located between the feedback line FB and the first output line GND. Specifically, in the second direction X, the cascade line 301 corresponding to the (2n-1)th pad unit column is located on the side of the first output line GND electrically connected to the (2n-1)th pad unit column away from the 2nth pad unit column, and the first input line PWR is located between the cascade line 301 and the first output line GND, that is, in the odd-numbered pad unit columns 4, the first input line PWR of the level is located on the left side of the first output line GND, and the cascade line 301 is located on the left side of the first input line PWR; the cascade line 301 corresponding to the 2nth pad unit column is located on the side of the first output line GND electrically connected to the 2nth pad unit column away from the (2n-1)th pad unit column, and the first input line PWR is located between the cascade line 301 and the first output line GND, that is, in the even-numbered pad unit columns 4, the first input line PWR of the level is located on the right side of the first output line GND, and the cascade line 301 is located on the right side of the first input line PWR.

[0117] In some embodiments, 2N pad unit columns include M addressing loops, where M is a positive integer greater than 1 and less than or equal to N, and 2N / M is a positive integer greater than 1. That is, 2N / M pad unit columns constitute one addressing loop. In one addressing loop, different pad unit columns are cascaded, that is, all first pad regions in the 2N / M pad unit columns are cascaded.

[0118] In some embodiments, as shown in Figure 5, the address pad Di of the first level first pad area 201 in the multiple cascaded first pad areas 201 is connected to an address line addr, and the channel pad OT of the last level first pad area 201 in the multiple cascaded first pad areas 201 is connected to a feedback line FB.

[0119] In some embodiments, for the wiring substrate shown in FIG. 5 , for example, M=N, that is, 2N pad unit columns 4 constitute N addressing loops, and two pad unit columns constitute one addressing loop.

[0120] In some embodiments, as shown in FIG5 and FIG6 , the (2n-1)th pad unit column 4 is cascaded with the 2nth pad unit column 4. The first-level first pad area 201 in the 2n-1th pad unit column 4 is the first-level first pad area 201 in the multiple cascaded first pad areas 201, and the last-level first pad area 201 in the 2nth pad unit column 4 is the last-level first pad area 201 in the multiple cascaded first pad areas 201. That is, the address pad Di of the first-level first pad area 201 in the 2n-1th pad unit column 4 is connected to an address line addr, and the channel pad OT of the last-level first pad area 201 in the 2nth pad unit column 4 is connected to a feedback line FB.

[0121] In a specific implementation, as shown in Figure 5, the first-level first pad area 201 in the 2n-1th pad unit column 4 is the first pad area 201 in the 2n-1th pad unit column 4 that is closest to the binding area 102, and the address line addr connected to the address pad Di of the first-level first pad area 201 in the 2n-1th pad unit column 4 extends directly from the functional area 101 to the binding area 102, and the address line addr is adjacent to the first input line PWR, and the address line addr is located on the side of the first input line PWR away from the first output line GND, that is, the address line addr is located on the left side of the first input line PWR. The last-level first pad area 201 in the 2n-th pad unit column 4 is the first pad area 201 in the 2n-th pad unit column 4 that is closest to the binding area 102. The feedback line FB connected to the channel pad OT of the last-level first pad area 201 in the 2n-th pad unit column 4 extends directly from the functional area 101 to the binding area 102. The feedback line FB is adjacent to the first input line PWR, and the feedback line FB is located on the side of the first input line PWR that is away from the first output line GND, that is, the feedback line FB is located on the right side of the first input line PWR.

[0122] In some embodiments, as shown in FIG5 , the plurality of cascade lines 301 include a plurality of first cascade lines 301 - 1 and a plurality of second cascade lines 301 - 2 ;

[0123] The first cascade line 301 - 1 is used to connect the pad units 2 that are cascaded in sequence in the pad unit column 4 ;

[0124] The second connecting line 301 - 2 is used to connect the last-level first pad region 201 in the (2n−1)th pad unit column 4 with the first-level first pad region 201 in the 2nth pad unit column 4 .

[0125] In the wiring substrate provided by the embodiment of the present disclosure, the (2n-1)th pad unit column and the 2nth pad unit column are connected by a second cascade line, so that the (2n-1)th pad unit column and the 2nth pad unit column are cascaded to form an addressing loop.

[0126] In some embodiments, as shown in Figures 5 and 6, the last-level first pad area 201 in the (2n-1)th pad unit column 4 (the first pad area 201 marked as E1 in Figure 6) is the first pad area 201 in the (2n-1)th pad unit column 4 that is farthest from the binding area 102; the first-level first pad area 201 in the 2nth pad unit column 4 (the first pad area 201 marked as E2 in Figure 6) is the first pad area 201 in the 2nth pad unit column 4 that is farthest from the binding area 102; the second cascade line 301-2 connects the first pad area 201 marked as E1 and the first pad area 201 marked as E2. That is, in the first direction Y, the second cascade line 301-2 is closer to the second border area 103, and the second cascade line 301-2 is located at the edge of the functional area 101 away from the binding area 101. The second cascade line 301-2 connects the last-level first pad area 201 in the (2n-1)th pad unit column 4 (the first pad area 201 marked as E1 in Figure 6) with the first-level first pad area 201 in the 2nth pad unit column 4 (the first pad area 201 marked as E2 in Figure 6) in the area away from the binding area 102.

[0127] The wiring substrate provided by the embodiment of the present disclosure designs the arrangement position of each pad in the first pad area in the even-numbered pad unit column, so that the arrangement position of each pad in the first pad area in the even-numbered pad unit column is different from the arrangement position of each pad in the first pad area in the odd-numbered pad unit column. Accordingly, the position of each routing line corresponding to the even-numbered column is different from the position of each routing line corresponding to the odd-numbered column. Moreover, since the cascade directions of multiple first pad areas in adjacent pad unit columns are opposite, in an addressing loop, it can be set that the first-level and last-level first pad areas of multiple cascaded first pad areas are both in the area closest to the binding area in the pad unit column, so that the feedback line connected to the last-level first pad area extends directly from the functional area to the binding area without passing through the area between adjacent pad unit columns to extend to the binding area, so that the feedback line FB does not need to be adjacent to the first output line GND. Since the cascade directions of multiple first pad areas in adjacent pad unit columns are opposite, the two first pad areas that need to be cascaded between the (2n-1)th pad unit column and the 2nth pad unit column are both located in the area farthest from the binding area in the pad unit column. Therefore, setting a second cascade line at the edge away from the binding area can achieve the cascade of the (2n-1)th pad unit column and the 2nth pad unit column. That is, the wiring and provided by the embodiment of the present disclosure can achieve the cascade of the (2n-1)th pad unit column and the 2nth pad unit column without setting a feedback line FB adjacent to the first output line GND, thereby avoiding weak conduction between the feedback line and the first output line. As a result, the light-emitting device, the pad group, the feedback line and the first output line will not be turned on due to conduction, thereby avoiding the phenomenon of weak brightness of the light-emitting area corresponding to the second pad area of ​​the last stage of the cascade, thereby improving the display effect and enhancing the user experience.

[0128] In some embodiments, as shown in FIG5 and FIG6 , the second cascade line 301 - 2 includes: a first portion 3011 , a second portion 3012 , and a third portion 3013 that are sequentially connected;

[0129] At least parts of the first portion 3011 and the third portion 3013 extend along the first direction Y, and the second portion 3012 extends along the second direction X;

[0130] The first part 3011 is connected to the channel pad OT of the last level first pad area 201 (the first pad area 201 marked as E1 in the figure in Figure 6) in the (2n-1)th pad unit column 4, and the third part 3013 is connected to the address pad Di of the first level first pad area 201 (the first pad area 201 marked as E2 in the figure in Figure 6) of the 2nth pad unit column 4.

[0131] In some embodiments, as shown in FIG5 and FIG6 , in the first direction Y, the second portion 3012 is located on a side of the first output line GND away from the bonding area 102, the first portion 3011 is located on a side of the first output line GND electrically connected to the (2n-1)th pad unit column 4 away from the bonding area 102, and the third portion 3013 is located on a side of the first output line GND electrically connected to the 2nth pad unit column 4 away from the bonding area 102;

[0132] The first output line GND electrically connected to the (2n−1)th pad unit column 4 is not adjacent to the first portion 3011 , and the first output line GND electrically connected to the 2nth pad unit column 4 is not adjacent to the third portion 3013 .

[0133] As shown in FIG6 , the wiring substrate provided by the embodiment of the present disclosure has a first portion 3011 connected to the channel pad OT of the last-level first pad area 201 (the first pad area 201 marked as E1 in FIG6 ) in the (2n-1)th pad unit column 4, and the first portion 3011 is also connected to the negative electrode pad 20212 of the B4 pad group 2021 in the second pad area 202. Therefore, the first output line GND electrically connected to the (2n-1)th pad unit column 4 is not adjacent to the first portion 3011, which can avoid the first output line GND electrically connected to the (2n-1)th pad unit column 4. There is weak conduction between the first output line GND and the first portion 3011; the third portion 3013 is connected to the address pad Di of the first-level first pad area 201 (the first pad area 201 labeled E2 in FIG6 ) in the 2nth pad unit column 4. The third portion 3013 is also connected to the negative electrode pad 20212 of the B4 pad group 2021 in the second pad area 202. The first output line GND electrically connected to the 2nth pad unit column 4 is not adjacent to the third portion 3013, thereby avoiding weak conduction between the first output line GND electrically connected to the 2nth pad unit column 4 and the third portion 3013. This prevents the light-emitting device, the pad group, the second-level cascade line, and the first output line from being electrically connected and illuminated, thus avoiding the phenomenon of weak brightness of the light-emitting area, improving the display effect, and enhancing the user experience.

[0134] It should be noted that the two lines involved in the embodiment of the present disclosure are adjacent, which means that there is no other line between the two lines and the distance between the two lines in the second direction X is greater than 0 and less than a first preset value, and the first preset value is, for example, 1 mm. In the related art, in the second direction X, the feedback line FB is adjacent to the first output line GND, and the distance between the two is less than 1 mm, which makes it easy for weak conduction to occur. However, the wiring substrate provided by the embodiment of the present disclosure, as shown in Figures 5 and 6, has a length in the first direction Y of the first output line GND electrically connected to the (2n-1)th pad unit column 4 that is less than the length in the first direction Y of the first output line GND electrically connected to the 2nth pad unit column 4. Since the first output line GND electrically connected to the (2n-1)th pad unit column 4 and the first output line GND electrically connected to the 2nth pad unit column 4 are adjacent, the first output line GND electrically connected to the 2nth pad unit column 4 and the first part 301 are arranged relative to each other in the second direction X. However, in the second direction X, the distance h1 between the first output line GND electrically connected to the 2nth pad unit column 4 and the first portion 301 is greater than 1 mm. That is, the first output line GND electrically connected to the 2nth pad unit column 4 and the first portion 301 are not adjacent to each other. Since h1 is large, weak conduction between the first output line GND electrically connected to the 2nth pad unit column 4 and the first portion 301 does not occur.

[0135] That is, the wiring substrate provided by the embodiment of the present disclosure, the setting of the second connecting line will not cause weak conduction between the second connecting line and the first output line, so that the light-emitting device, the pad group, the first part and the first output line will not be connected and lit, avoiding the phenomenon of weak brightness of the light-emitting area, improving the display effect, and enhancing the user experience.

[0136] In some embodiments, as shown in FIG. 5 , the second input line VLED connected to the 2nth pad unit column 4 is adjacent to the second input line VLED connected to the (2n+1)th pad unit column 4 .

[0137] In some embodiments, as shown in Figure 5, the second input line VLED connected to the first pad unit column 4 includes a portion located in the third border area 105, and the second input line VLED connected to the 2Nth pad unit column 4 includes a portion located in the second border area 104; in the second border area 104 and the third border area 105, the electrostatic shielding line 304 is located on the side of the second input line VLED away from the functional area 101, and the electrostatic shielding line 304 is adjacent to the second input line VLED.

[0138] It should be noted that FIG5 is illustrated by taking an example where two pad unit columns form an addressing loop.

[0139] In a specific implementation, when the wiring substrate includes 2N pad unit columns, more pad unit columns may form an addressing loop, that is, more pad unit columns may be cascaded. For the wiring substrate shown in FIG5 , the feedback line FB connected to the 2nth pad unit column 4 may be electrically connected to the address line addr connected to the 2n+1th pad unit column 4 via a circuit board, that is, more pad unit columns may be cascaded via the circuit board.

[0140] Of course, other configurations may be used to make multiple columns of pad units form an addressing loop.

[0141] In some embodiments, as shown in FIG7 , the plurality of traces 3 further include a plurality of transfer lines 302 , the address line addr is connected to the address pad Di of the first-level first pad area 201 in each pad unit column 4 , and the channel pad OT of the last-level first pad area 201 in each pad unit column 4 is connected to a feedback line FB;

[0142] The plurality of patch cables 302 include a plurality of first patch cables 302-1 and a plurality of second patch cables 302-2;

[0143] The first transfer line 302-1 is used to electrically connect the feedback line FB connected to the (2n-1)th pad unit column 4 and the address line addr connected to the 2nth pad unit column 4;

[0144] The second transfer line 302-2 is used to electrically connect the feedback line FB connected to the 2nth pad unit column 4 and the address line addr connected to the (2n+1)th pad unit column 4;

[0145] Wherein, N is a positive integer, and n is a positive integer not greater than N.

[0146] It should be noted that the adapter wire extends to the binding area and is electrically connected to the binding pad, and then is electrically connected to the circuit board. The first adapter wire is used to electrically connect the feedback line FB connected to the (2n-1)th pad unit column and the address line addr connected to the 2nth pad unit column, which means that the feedback line FB connected to the (2n-1)th pad unit column is electrically connected to the address line addr connected to the 2nth pad unit column through the first adapter wire, the binding pad, and the circuit board. The second adapter wire is used to electrically connect the feedback line FB connected to the 2nth pad unit column and the address line addr connected to the (2n+1)th pad unit column, which means that the feedback line FB connected to the 2nth pad unit column is electrically connected to the address line addr connected to the (2n+1)th pad unit column through the second adapter wire, the binding pad, and the circuit board.

[0147] The wiring substrate provided by the embodiment of the present disclosure realizes electrical connection between more than two adjacent pad unit columns through the first adapter wire and the second adapter wire, that is, more than two adjacent pad unit columns are cascaded to form an addressing loop.

[0148] In some embodiments, 2N pad unit columns include M' addressing loops, where M' is a positive integer greater than 1 and less than N, and 2N / M' is a positive integer greater than 2. That is, 2N / M' pad unit columns constitute one addressing loop. In one addressing loop, different pad unit columns are cascaded, that is, all first pad regions in the 2N / M' pad unit columns are cascaded.

[0149] In some embodiments, for the wiring substrate shown in FIG. 7 , for example, M′=N / 2, that is, 2N pad unit columns 4 constitute N / 2 addressing loops, and 4 pad unit columns constitute one addressing loop.

[0150] In some embodiments, as shown in Figures 7 and 8, the last level first pad area 201 in the odd-numbered pad unit column 4 (the first pad area 201 marked as E1 in Figure 8) is the first pad area 201 in the pad unit column 4 that is farthest from the binding area 102; the first level first pad area 201 in the even-numbered pad unit column 4 (the first pad area 201 marked as E2 in Figure 8) is the first pad area 201 in the pad unit column 4 that is farthest from the binding area 102; the address pad Di of the first level first pad area 201 in the odd-numbered pad unit column 4 is the first pad area 201 in the pad unit column 4 that is farthest from the binding area 102. The address line addr is connected, and the address line addr extends directly to the binding area 101. The channel pad OT of the last-level first pad area 201 is connected to a feedback line FB, and the feedback line FB is connected to the first transfer line 302-1; in the even-numbered column pad unit column 4, the channel pad OT of the last-level first pad area 201 is connected to a feedback line FB, and the feedback line FB extends directly to the binding area 101. The address pad Di of the first-level first pad area 201 is connected to the address line addr, and the address line addr is connected to the second transfer line 302-2.

[0151] In some embodiments, as shown in FIG. 7 , the feedback line FB connected to the (2n−1)th pad unit column 4 is located on a side of the first output line GND connected to the (2n−1)th pad unit column 4 away from the bonding area 102 .

[0152] This will prevent the feedback line and the first output line from being weakly conductive, and the light-emitting device, the pad group, the feedback line and the first output line from being conductive and lit, thus avoiding the phenomenon of weak brightness in the light-emitting area, improving the display effect and enhancing the user experience.

[0153] In some embodiments, as shown in FIG7 , the first patch line 302-1 includes: a fourth portion 3021 extending along the second direction X, and a fifth portion 3022 extending along the first direction Y in the functional area 101; a feedback line FB connected to the (2n-1)th pad unit column 4 is connected to one end of the fourth portion 3021, and the fifth portion 3022 is connected to the other end of the fourth portion 3021;

[0154] The second input line VLED connected to the (2n−1)th pad unit column 4 is adjacent to the fifth portion 3022 .

[0155] In some embodiments, the address line addr connected to the 2nth pad unit column 4 is located on a side of the first output line GND connected to the 2nth pad unit column 4 away from the bonding area 102 ;

[0156] The second patch line 302-2 includes a sixth portion 3023 extending along the second direction X, and a seventh portion 3024 extending along the first direction Y in the functional area 101. The address line addr connected to the 2nth pad unit column 4 is connected to one end of the sixth portion 3023, and the seventh portion 3024 is connected to the other end of the sixth portion 3023.

[0157] The second input line VLED connected to the 2n-th pad unit column 4 is adjacent to the seventh portion 3024 .

[0158] In some embodiments, the fifth portion 3022 is adjacent to the seventh portion 3024 in a region between the second input line VLED connected to the 2nth pad unit column 4 and the second input line VLED connected to the (2n−1)th pad unit column 4 .

[0159] In some embodiments, as shown in FIG7 , the fifth portion 3022 of the first transfer line 302-1 corresponding to the first pad unit column 4 includes a portion located in the third border area 105, and in the third border area 105, the fifth portion 3022 is located between the second input line VLED and the electrostatic shielding line 304. The fifth portion 3022 of the first transfer line 302-1 corresponding to the 2Nth pad unit column 4 includes a portion located in the second border area 104, and in the second border area 104, the fifth portion 3022 is located between the second input line VLED and the electrostatic shielding line 304.

[0160] The wiring substrate provided by the embodiment of the present disclosure designs the arrangement position of each pad in the first pad area in the even-numbered pad unit column, so that the arrangement position of each pad in the first pad area in the even-numbered pad unit column is different from the arrangement position of each pad in the first pad area in the odd-numbered pad unit column. Accordingly, the position of each routing line corresponding to the even-numbered column is different from the position of each routing line corresponding to the odd-numbered column. Moreover, since the cascade directions of multiple first pad areas in adjacent pad unit columns are opposite, in an addressing loop, it can be set that the first-level and last-level first pad areas of multiple cascaded first pad areas are both in the area closest to the binding area in the pad unit column, so that the feedback line connected to the last-level first pad area extends directly from the functional area to the binding area without passing through the area between adjacent pad unit columns to extend to the binding area, so that the feedback line FB does not need to be adjacent to the first output line GND. Since the cascade directions of multiple first pad areas in adjacent pad unit columns are opposite, the two first pad areas that need to be cascaded between the (2n-1)th pad unit column and the 2nth pad unit column are both located in the area farthest from the binding area in the pad unit column. Therefore, setting a second cascade line at the edge away from the binding area can achieve the cascade of the (2n-1)th pad unit column and the 2nth pad unit column. That is, the wiring and provided by the embodiment of the present disclosure can achieve the cascade of the (2n-1)th pad unit column and the 2nth pad unit column without setting a feedback line FB adjacent to the first output line GND, thereby avoiding weak conduction between the feedback line and the first output line. As a result, the light-emitting device, the pad group, the feedback line and the first output line will not be turned on due to conduction, thereby avoiding the phenomenon of weak brightness of the light-emitting area corresponding to the second pad area of ​​the last stage of the cascade, thereby improving the display effect and enhancing the user experience.

[0161] The wiring substrate provided by the embodiment of the present disclosure designs the arrangement positions of the pads in the first pad area in the even-numbered pad unit columns, so that the arrangement positions of the pads in the first pad area in the even-numbered pad unit columns are different from the arrangement positions of the pads in the first pad area in the odd-numbered pad unit columns. Accordingly, the positions of the traces corresponding to the even-numbered columns are different from the positions of the traces corresponding to the odd-numbered columns. Between the (2n-1)th pad unit column and the 2nth pad unit column, the two first output lines GND are adjacent, and between the 2nth pad unit column and the (2n+1)th pad unit column, the two first output lines GND are adjacent. The second input lines VLED are arranged relative to each other, and the feedback line FB connected to the last-stage first pad area in the odd-numbered pad unit columns is electrically connected to the binding terminal of the binding area via a first adapter line extending between the two second input lines VLED. The address line addr connected to the first-stage first pad area in the even-numbered pad unit columns is electrically connected to the binding terminal of the binding area via a second adapter line extending between the two second input lines VLED. As a result, the adapter lines of the cascaded multiple pad unit columns are not adjacent to the first output line GND, which can prevent the feedback line and the first output line from being weakly conductive. As a result, the light-emitting device, pad group, feedback line and first output line will not be conductively connected and illuminated, and the phenomenon of the light-emitting area corresponding to the last-stage second pad area of ​​the cascade being weakly illuminated is avoided, thereby improving the display effect and user experience.

[0162] In some embodiments, the traces, positive pads, negative pads, address pads, channel pads, output pads, and input pads are arranged on the same layer. The traces, positive pads, negative pads, address pads, channel pads, output pads, and input pads are made of the same material, for example, copper. In a specific implementation, a copper conductive layer can be formed on one side of the substrate, and then the copper conductive layer is patterned to form patterns for the traces and pads.

[0163] In some embodiments, the wiring substrate further includes a first insulating layer located on a side of the traces, positive pads, negative pads, address pads, channel pads, output pads, and input pads facing away from the substrate. The first insulating layer has a plurality of openings. It is understood that, in the patterned copper conductive layer, the portions exposed by the insulating layer openings are the pads, and the areas covered by the insulating layer are the traces. The electronic component and the driver component include at least two pins, and each pad is used to secure and connect to a pin of the electronic component or driver component.

[0164] Based on the same inventive concept, the embodiment of the present disclosure also provides a light-emitting substrate, as shown in Figure 9, the light-emitting substrate includes: the wiring substrate 11 provided in the embodiment of the present disclosure, the driving element IC bound one-to-one with the first pad area (not shown), and the light-emitting element bound one-to-one with the pad groups (not shown) in multiple second pad areas (not shown).

[0165] In some embodiments, as shown in FIG9 , the light emitting substrate further includes:

[0166] The circuit board is bonded to the wiring substrate in the bonding area 102 .

[0167] In some embodiments, as shown in FIG10 , the circuit board 14 includes a plurality of first circuit structures 1401 and a plurality of second circuit structures 1402 ; the wiring substrate includes: a pad unit column 4 , a first transfer line 302 - 1 , a second transfer line 302 - 2 , an address line addr , and a feedback line FB ;

[0168] The first transfer line 302-1 corresponding to the (2n-1)th pad unit column 4 is electrically connected to the address line addr connected to the 2nth pad unit column 4 through the first circuit structure 1401;

[0169] The second transfer line 302 - 2 corresponding to the 2nth pad unit column 4 is electrically connected to the feedback line FB connected to the 2nth pad unit column 4 through the second circuit structure 1402 .

[0170] It should be noted that, in Figure 10, the first transfer line 302-1 corresponding to the (2n-1)th pad unit column 4 is electrically connected to the address line addr connected to the 2nth pad unit column 4 through the first circuit structure 1401; the first transfer line 302-1 corresponding to the (2n+1)th pad unit column 4 is electrically connected to the address line addr connected to the (2n+2)th pad unit column 4 through the first circuit structure 1401; the second transfer line 302-2 corresponding to the 2nth pad unit column 4 is electrically connected to the feedback line FB connected to the 2nth pad unit column 4 through the second circuit structure 1402. Thus, the (2n-1)th pad unit column 4, the 2nth pad unit column 4, the (2n+2)th pad unit column 4, and the (2n+2)th pad unit column 4 are cascaded via the feedback line FB, the first transfer line 302-1, the address line addr, the second transfer line 302-2, and the first circuit structure 1401 and the second circuit structure 1402 of the circuit board, so that the (2n-1)th pad unit column 4, the 2nth pad unit column 4, the (2n+2)th pad unit column 4, and the (2n+2)th pad unit column 4 form an addressing loop. The first circuit structure and the second circuit structure can be connecting line structures made on the circuit board 14. The circuit board 14 can be either a rigid printed circuit board or a flexible printed circuit board.

[0171] In some embodiments, the light emitting element is a micro-sized inorganic light emitting diode.

[0172] In a specific implementation, the micro-sized inorganic light-emitting diode is, for example, a mini light-emitting diode (Mini Light Emitting Diode, Mini-LED) or a micro light-emitting diode (Micro Light Emitting Diode, Micro-LED). Mini-LED and Micro-LED are small in size and high in brightness, and can be widely used in display devices or their backlight modules. For example, the typical size (e.g., length) of Micro-LED is less than 100 microns, such as 10 microns to 80 microns; the typical size (e.g., length) of Mini-LED is 80 microns to 350 microns, such as 80 microns to 120 microns. The electronic component can be at least one of Micro-LED or Mini-LED.

[0173] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, as shown in FIG11 , comprising a light-emitting substrate 12 provided in an embodiment of the present disclosure.

[0174] In some embodiments, as shown in FIG11 , the display device further includes:

[0175] The display panel 13 is located on the light emitting side of the light emitting substrate 12 .

[0176] That is, the light-emitting substrate serves as the backlight source of the display panel.

[0177] In a specific implementation, as shown in FIG11 , the display panel 13 is, for example, a liquid crystal display panel, including: an array substrate 1301 and an opposite substrate 1302 arranged opposite to each other, and a liquid crystal layer 1303 located between the array substrate 1301 and the opposite substrate 1302 .

[0178] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the aforementioned embodiments of the wiring substrate and light-emitting substrate, and any repetitive details will be omitted.

[0179] In summary, in the wiring substrate, light-emitting substrate, and display device provided by the embodiments of the present disclosure, one side of the first output line is adjacent to the first input line, and the other side is adjacent to another first output line or a second input line, that is, the first output line is not adjacent to the feedback line. Therefore, when the wiring substrate is used in a light-emitting substrate, this can prevent weak conduction between the feedback line and the first output line, which would cause the light-emitting device, the pad group, the feedback line, and the first output line to be connected, thereby preventing the light-emitting device from being illuminated and preventing the light-emitting area corresponding to the second pad area of ​​the final cascade stage from being weakly illuminated, thereby improving the display effect and enhancing the user experience.

[0180] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0181] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A wiring substrate, wherein: It includes a substrate, which is divided into a functional area and a binding area. The functional area includes a plurality of pad units arranged along a first direction and a second direction respectively, the pad unit includes: a first pad area, and a second pad area electrically connected to the first pad area; the second direction intersects the first direction; The functional area further includes a plurality of routing lines arranged on the same layer, wherein the plurality of routing lines include a plurality of first input lines, a plurality of first output lines, a plurality of second input lines, and a plurality of cascade lines; The input pads of the plurality of first pad areas arranged along the first direction are connected to the same first input line, the output pads of the plurality of first pad areas arranged along the first direction are connected to the same first output line, two adjacent first pad areas along the first direction are connected via the cascade line, and the input ends of the plurality of second pad areas arranged along the first direction are connected to the same second input line; In the functional area, in the second direction, one side of the first output line is disposed adjacent to the first input line, and the other side of the first output line is disposed adjacent to another first output line or a second input line.

2. The wiring substrate according to claim 1, wherein: Each of the first pad areas includes a channel pad and an address pad. Among the multiple cascaded first pad areas, the channel pad of the i-th first pad area and the address pad of the (i+1)-th first pad area are connected via the cascade line; wherein i is a positive integer.

3. The wiring substrate according to claim 2, wherein: A plurality of the pad units arranged along the first direction constitute a pad unit column, and a plurality of the first pad areas in each pad unit column are sequentially cascaded along the first direction; The plurality of routing lines also include a plurality of feedback lines; In at least part of the pad unit columns, the channel pad of the last stage of the first pad area among a plurality of cascaded first pad areas is connected to one of the feedback lines, and the feedback line is not disposed adjacent to the first output line.

4. The wiring substrate according to claim 3, wherein: In adjacent pad unit columns, the cascading directions of the plurality of first pad regions are opposite.

5. The wiring substrate according to claim 4, wherein: The second input line and the first output line connected to the same pad unit column are respectively located at two sides of the pad unit column.

6. The wiring substrate according to claim 5, wherein: The second direction includes 2N pad unit columns; The first output line connected to the (2n-1)th pad unit column is adjacent to the first output line connected to the 2nth pad unit column; The second input line connected to the 2nth pad unit column and the second input line connected to the (2n+1)th pad unit column are arranged relatively between the 2nth pad unit column and the (2n+1)th pad unit column; Wherein, N is a positive integer, and n is a positive integer not greater than N.

7. The wiring substrate according to claim 6, wherein: The plurality of cascade lines include a plurality of first cascade lines and a plurality of second cascade lines; The first cascading line is used to connect the pad units that are cascaded in sequence in the pad unit column; The second-stage connection line is used to connect the last-stage first pad region in the (2n-1)th pad unit column with the first-stage first pad region in the 2nth pad unit column.

8. The wiring substrate according to claim 7, wherein: The second-stage cascade line includes: a first part, a second part, and a third part connected in sequence; At least a portion of the first portion and the third portion extend along the first direction, and the second portion extends along the second direction; The first part is connected to the channel pad of the last level of the first pad area in the (2n-1)th pad unit column, and the third part is connected to the address pad of the first level of the first pad area in the 2nth pad unit column.

9. The wiring substrate according to claim 8, wherein: In the first direction, the second portion is located at a side of the first output line away from the binding area, the first portion is located at a side of the first output line electrically connected to the (2n-1)th pad unit column away from the binding area, and the third portion is located at a side of the first output line electrically connected to the 2nth pad unit column away from the binding area; The first output line electrically connected to the (2n-1)th pad unit column is not adjacent to the first portion, and the first output line electrically connected to the 2nth pad unit column is not adjacent to the third portion.

10. The wiring substrate according to claim 6, wherein: The second direction includes 2N pad unit columns; The plurality of routing lines further include a plurality of address lines and a plurality of transfer lines, the address lines are connected to the address pads of the first pad area of ​​the first level in each pad unit column, and the channel pads of the first pad area of ​​the last level in each pad unit column are connected to a feedback line; The plurality of adapter wires include a plurality of first adapter wires and a plurality of second adapter wires; The first transfer line is used to electrically connect the feedback line connected to the (2n-1)th pad unit column and the address line connected to the 2nth pad unit column; The second transfer line is used to electrically connect the feedback line connected to the 2nth pad unit column and the address line connected to the (2n+1)th pad unit column; Wherein, N is a positive integer, and n is a positive integer not greater than N.

11. The wiring substrate according to claim 10, wherein: The feedback line connected to the (2n-1)th pad unit column is located at a side of the first output line connected to the (2n-1)th pad unit column away from the binding area; The first transfer line includes: a fourth portion extending along the second direction, and a fifth portion extending along the first direction in the functional area; the feedback line connected to the (2n-1)th pad unit column is connected to one end of the fourth portion, and the fifth portion is connected to the other end of the fourth portion; The second input line connected to the (2n-1)th pad unit column is adjacent to the fifth portion.

12. The wiring substrate according to claim 11, wherein The address line connected to the 2nth pad unit column is located at a side of the first output line connected to the 2nth pad unit column away from the binding area; The second transfer line includes: a sixth portion extending along the second direction, and a seventh portion extending along the first direction in the functional area; the address line connected to the 2nth pad unit column is connected to one end of the sixth portion, and the seventh portion is connected to the other end of the sixth portion; The second input line connected to the 2nth pad unit column is adjacent to the seventh portion.

13. The wiring substrate according to claim 12, wherein: The fifth portion is adjacent to the seventh portion in a region between the second input line connected to the 2nth pad unit column and the second input line connected to the (2n-1)th pad unit column.

14. The wiring substrate according to any one of claims 6 to 12, wherein: The first pad area includes an address pad, an input pad, a channel pad and an output pad; The address pad and the input pad are located in the same row in the first direction, and the channel pad and the output pad are located in the same row in the first direction; the channel pad and the address pad are located in the same column in the second direction, and the output pad and the input pad are located in the same column in the second direction; In the (2n-1)th pad unit column, the address pad and the input pad are located on the side of the channel pad and the output pad close to the binding area in the first direction; the first pad area in the 2nth pad unit column is arranged in the same manner as the first pad area in the (2n-1)th pad unit column after being rotated 180°; wherein N is a positive integer and n is a positive integer not greater than N.

15. The wiring substrate according to claim 14, wherein: Among the address lines, the first input lines and the first output lines electrically connected to the (2n-1)th pad unit column, in the second direction, the first input line is located between the address lines and the first output line; Among the feedback line, the first input line, and the first output line corresponding to the 2nth pad unit column, in the second direction, the first input line is located between the feedback line and the first output line.

16. The wiring substrate according to claim 14, wherein: The second pad area has a center dividing line extending along the first direction; The first pad area in the (2n-1)th pad unit column is located on the side of the dividing line toward the 2nth pad unit column, and the first pad area in the 2nth pad unit column is located on the side of the dividing line toward the (2n-1)th pad unit column.

17. A light-emitting substrate, wherein: The light-emitting substrate comprises: the wiring substrate according to any one of claims 1 to 16, a driving element bound to the first pad area in a one-to-one correspondence, and a light-emitting element bound to a plurality of pad groups in the second pad area in a one-to-one correspondence.

18. The light emitting substrate according to claim 17, wherein: The light-emitting substrate further comprises: A circuit board is bound to the wiring substrate in the binding area; the circuit board includes a plurality of first circuit structures and a plurality of second circuit structures; the wiring substrate includes: a pad unit column, a first transfer line, a second transfer line, an address line, and a feedback line; The first transfer line corresponding to the (2n-1)th pad unit column is electrically connected to the address line connected to the 2nth pad unit column through the first circuit structure; The second transfer line corresponding to the 2nth pad unit column is electrically connected to the feedback line connected to the 2nth pad unit column through the second circuit structure.

19. The light-emitting substrate according to claim 17 or 18, wherein: The light emitting element is a micro-sized inorganic light emitting diode.

20. A display device, wherein: It comprises the light emitting substrate according to any one of claims 17 to 19.

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