Pixel circuit and driving method therefor, and display apparatus

Abstract

The present disclosure belongs to the technical field of displays. Provided are a pixel circuit and a driving method therefor, and a display apparatus. The pixel circuit of the present disclosure comprises: a first transistor, a first initialization unit, a second initialization unit, a data writing unit, a threshold compensation unit, a first storage unit, a first light-emission control unit, a second light-emission control unit and a light-emitting device, wherein the data writing unit is configured to write a data signal into a first node in response to a first scan signal; the threshold compensation unit is configured to write a threshold voltage into a third node in response to a second scan signal and a first light-emission control signal; the first light-emission control unit is configured to transmit a first power source voltage to a driving transistor in response to the first light-emission control signal, so as to convert a first voltage into a driving current; and the second light-emission control unit is configured to write, into a first electrode of the light-emitting device in response to a second light-emission control signal, the driving current, which is generated by the driving transistor.

Description

Pixel circuit, driving method thereof, and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a pixel circuit and a driving method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) is a light-emitting device that uses organic solid-state semiconductors as light-emitting materials. It has broad application prospects due to its advantages such as simple preparation process, low cost, low power consumption, high luminous brightness, and wide operating temperature adaptability.

[0003] OLED light-emitting devices are typically driven to emit light through pixel circuits, which include components such as driver transistors and storage capacitors. Because the threshold voltage (Vth) of the driver transistor changes over time, it is necessary to compensate for the threshold voltage (Vth) of the driver transistor in the pixel circuit. During high-frequency displays, the short charging time for each row of pixels and the unstable voltages at certain nodes in the pixel circuit degrade the quality of the threshold voltage (Vth) compensation, which can easily lead to display issues such as unevenness.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a pixel circuit and a driving method thereof, and a display device.

[0006] In a first aspect, an embodiment of the present disclosure provides a pixel circuit, wherein the pixel circuit includes: a first transistor, a first initialization unit, a second initialization unit, a data writing unit, a threshold compensation unit, a first storage unit, a first light emitting control unit, a second light emitting control unit, and a light emitting device;

[0007] The control electrode of the first transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node;

[0008] The first electrode of the light emitting device is connected to the fourth node, and the second electrode is connected to the second power supply voltage terminal;

[0009] The data writing unit is configured to write a data signal into the first node in response to a first scan signal;

[0010] The first initialization unit is configured to reset the voltage of the first node using the first initialization signal in response to the second scan signal;

[0011] The second initialization unit is configured to reset the voltages of the second node, the third node, and the fourth node using a second initialization signal in response to the third scan signal;

[0012] The threshold compensation unit is configured to write a threshold voltage into the third node in response to the second scan signal and the first light emitting control signal;

[0013] The first storage unit is configured to store voltages of the first node and the third node;

[0014] The first light emitting control unit is configured to transmit a first power supply voltage to the driving transistor in response to a first light emitting control signal to convert the first voltage into a driving current;

[0015] The second light emitting control unit is configured to write the driving current generated by the driving transistor into the first electrode of the light emitting device in response to a second light emitting control signal.

[0016] Optionally, the data writing unit includes: a second transistor;

[0017] The control electrode of the second transistor is connected to the first scanning signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the first node.

[0018] Optionally, the first initialization unit includes: a fourth transistor;

[0019] The control electrode of the fourth transistor is connected to the second scanning signal line, the first electrode is connected to the first initialization signal line, and the second electrode is connected to the first node.

[0020] Optionally, the second initialization unit includes: a third transistor;

[0021] The control electrode of the third transistor is connected to the third scan signal line, the first electrode is connected to the second initialization signal line, and the second electrode is connected to the fourth node.

[0022] Optionally, the second initialization unit includes: a third transistor;

[0023] The control electrode of the third transistor is connected to the third scan signal line, the first electrode is connected to the second initialization signal line, and the second electrode is connected to the third node.

[0024] Optionally, the first light emitting control unit includes: a fifth transistor;

[0025] The control electrode of the fifth transistor is connected to the first light emitting control signal line, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the second node.

[0026] Optionally, the second light emitting control unit includes: a sixth transistor;

[0027] The control electrode of the sixth transistor is connected to the second light emitting control signal line, the first electrode is connected to the third node, and the second electrode is connected to the fourth node.

[0028] Optionally, the first storage unit includes: a first storage capacitor;

[0029] One end of the first storage capacitor is connected to the first node, and the other end is connected to the third node.

[0030] Optionally, the fourth transistor and the fifth transistor are multiplexed as the threshold compensation unit.

[0031] Optionally, the second transistor is multiplexed as the first initialization unit.

[0032] Optionally, the pixel circuit further includes: a second storage unit;

[0033] The second storage unit is configured to store a voltage of the third node.

[0034] Optionally, the second storage unit includes: a second storage capacitor;

[0035] One end of the second storage capacitor is connected to the third node, and the other end is connected to the first power supply voltage end.

[0036] In a second aspect, an embodiment of the present disclosure provides a display device, wherein the display device includes a pixel circuit as provided above.

[0037] In a third aspect, an embodiment of the present disclosure provides a method for driving a pixel circuit, wherein the method for driving a pixel circuit includes:

[0038] In the first stage, in response to the second scan signal, the voltage of the first node is reset using the first initialization signal; and in response to the third scan signal, the voltages of the second node, the third node, and the fourth node are reset using the second initialization signal;

[0039] In the second phase, a threshold voltage is written into the third node in response to the second scan signal and the first light emitting control signal;

[0040] In the third stage, in response to the first scan signal, a data signal is written into the first node;

[0041] In the fourth stage, in response to a first light-emitting control signal, a first power supply voltage is transmitted to the driving transistor to convert the first voltage into a driving current; and in response to a second light-emitting control signal, the driving current generated by the driving transistor is written into the first electrode of the light-emitting device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic structural diagram of an exemplary pixel circuit.

[0043] FIG2 is a schematic structural diagram of a first pixel circuit provided by an embodiment of the present disclosure.

[0044] FIG3 is an operation timing diagram of the pixel circuit shown in FIG2 .

[0045] FIG4 is a schematic structural diagram of a second pixel circuit provided by an embodiment of the present disclosure.

[0046] FIG5 is a schematic structural diagram of a third pixel circuit provided by an embodiment of the present disclosure.

[0047] FIG6 is a schematic structural diagram of a fourth pixel circuit provided by an embodiment of the present disclosure.

[0048] FIG7 is a schematic structural diagram of a fifth pixel circuit provided by an embodiment of the present disclosure.

[0049] FIG8 is a schematic structural diagram of a sixth pixel circuit provided by an embodiment of the present disclosure.

[0050] FIG9 is a schematic structural diagram of a seventh pixel circuit provided by an embodiment of the present disclosure.

[0051] FIG10 is a schematic structural diagram of an eighth pixel circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0053] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0054] The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode and the other electrode is called the second electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first electrode is the source of the N-type transistor, and the second electrode is the drain of the N-type transistor. When the gate input is a high level, the source and drain are turned on. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present disclosure. The first power supply voltage terminal can be a high-level power supply voltage terminal, and the second power supply terminal can be a low-level power supply voltage terminal.

[0055] The light-emitting device in the embodiments of the present invention is a current-type light-emitting device, and further, can be a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), or an organic light-emitting diode (OLED). In the embodiments of the present disclosure, the light-emitting device is an OLED as an example, and the first electrode and the second electrode of the light-emitting device are the anode and cathode of the OLED, respectively.

[0056] FIG1 is a schematic structural diagram of an exemplary pixel circuit. As shown in FIG1 , the pixel circuit includes: a first transistor T1, a second transistor T2, a third transistor T4, a first storage capacitor C1, and a light-emitting device D; wherein the first transistor T1 is a driving transistor, the gate of the first transistor T1 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3; the second transistor T2 is a data writing transistor, the gate of the second transistor T2 is connected to the first scan signal line G1, the source is connected to the data signal line Data, and the drain is connected to the first node N1; the third transistor T4 is a driving transistor, the gate of the second transistor T2 is connected to the first scan signal line G1, the source is connected to the data signal line Data, and the drain is connected to the first node N1; The transistor T3 is an initialization transistor, the gate of the third transistor T3 is connected to the second scan signal line G2, the source is connected to the first initialization signal Vinit1, and the drain is connected to the third node N3; the fourth transistor T4 is a light-emitting control transistor, the gate of the fourth transistor T4 is connected to the first light-emitting control signal line EM1, the source is connected to the high-level power supply voltage terminal VDD, and the drain is connected to the second node N2; one end of the first storage capacitor C1 is connected to the first node N1, and the other end is connected to the third node N3; the anode of the light-emitting device D is connected to the third node N3, and the cathode is connected to the low-level power supply voltage terminal VSS.

[0057] The working process of the pixel circuit is divided into: a first stage t1, a second stage t2 and a third stage t3.

[0058] In the first stage t1, the second scanning signal line G2 inputs a high-level signal, the third transistor T3 is turned on, and the first initialization signal can be transmitted to the third node N3, that is, the anode of the light-emitting device D, through the third transistor T3. The first initialization signal is generally a low-level signal, which can initialize the anode of the light-emitting device D to avoid the signal of the previous frame display process interfering with the current display and affecting the display effect.

[0059] In the second stage t2, the first scan signal line G1 inputs a high-level signal, the second transistor T2 is turned on, and the data signal can be transmitted to the first node N1, that is, the gate of the first transistor T1 (driving transistor) through the second transistor T2 to control the opening degree of the first transistor T1, so that the first transistor T1 is turned on.

[0060] In the third stage t3, a high-level signal is input to the first light-emitting control signal line EM1, the fourth transistor T4 is turned on, and a driving current loop is formed between the high-level power supply voltage terminal VDD and the low-level power supply voltage terminal VSS. The driving current can pass through the light-emitting device D, causing the light-emitting device D to emit light.

[0061] Because the threshold voltage Vth of the driving transistor (first transistor T1) changes over time, it is necessary to compensate for the threshold voltage Vth of the driving transistor in the pixel circuit. During high-frequency display, the charging time of each row of pixels is short, and the voltage of certain nodes in the pixel circuit is unstable, which reduces the quality of the threshold voltage Vth compensation, easily leading to display unevenness and other defects.

[0062] In order to solve at least one of the above-mentioned technical problems, the embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device. The pixel circuit, a driving method thereof, and a display device provided by the embodiments of the present disclosure will be further described in detail below in combination with the accompanying drawings and specific implementation methods.

[0063] In a first aspect, an embodiment of the present disclosure provides a pixel circuit. FIG2 is a schematic structural diagram of the first pixel circuit provided by an embodiment of the present disclosure. As shown in FIG2 , the pixel circuit includes: a first transistor T1, a first initialization unit 301, a second initialization unit 302, a data writing unit 303, a threshold compensation unit 304, a first storage unit 305, a first light-emitting control unit 306, a second light-emitting control unit 307, and a light-emitting device D. The first transistor T1 is a driving transistor, whose gate is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3; the anode of the light-emitting device D is connected to the fourth node N4, and the cathode is connected to the low-level power supply voltage terminal VSS; the data writing unit 303 is configured to write a data signal to the first node N1 in response to a first scan signal; the first initialization unit 301 is configured to reset the voltage of the first node N1 using the first initialization signal in response to the second scan signal; the second initialization unit 302 is configured to reset the voltage of the second node N2 and the third node N3 in response to the third scan signal using the second initialization signal. The voltages of the node N3 and the fourth node N4 are reset; the threshold compensation unit 304 is configured to write the threshold voltage into the third node N3 in response to the second scan signal and the first light-emitting control signal; the first storage unit 305 is configured to store the voltages of the first node N1 and the third node N3; the first light-emitting control unit 306 is configured to transmit the first power supply voltage to the first transistor T1 in response to the first light-emitting control signal to convert the first voltage into a driving current; the second light-emitting control unit 307 is configured to write the driving current generated by the first transistor T1 into the anode of the light-emitting device D in response to the second light-emitting control signal.

[0064] In the pixel circuit provided by the present disclosure, the threshold compensation unit 304 is configured to write the threshold voltage to the third node N3 in response to the second scan signal and the first light-emitting control signal to compensate for the threshold voltage Vth of the first transistor T, thereby avoiding display abnormalities caused by the threshold voltage Vth offset of the first transistor T1. The data writing unit 303 is configured to write the data signal to the first node N1 in response to the first scan signal. The control signals of the data writing unit 303 and the threshold compensation unit 304 are the first scan signal and the second scan signal, respectively. The locations where the signals are written by the two are the first node N1 and the third node N3, respectively. The working states of the data writing unit 303 and the threshold compensation unit 304 are not affected by each other, and the data writing process and the threshold compensation process can be separated. The threshold compensation time can be infinitely extended to ensure that a good compensation effect can be achieved even when using processes with low electron mobility such as oxide transistors and high-frequency displays, thereby improving the display effect. In some embodiments, as shown in Figure 2, the data writing unit 303 includes: a second transistor T2; the gate of the second transistor T2 is connected to the first scan signal line G1, the source is connected to the data signal line Data, and the drain is connected to the first node N1. The first initialization unit 301 includes a fourth transistor T4; the gate of the fourth transistor T4 is connected to the second scan signal line G2, the source is connected to the first initialization signal line Vref, and the drain is connected to the first node N1. The second initialization unit 302 includes a third transistor T3; the gate of the third transistor T3 is connected to the third scan signal line G3, the source is connected to the second initialization signal line Var, and the drain is connected to the fourth node N4. The first light-emission control unit 306 includes a fifth transistor T5; the gate of the fifth transistor T5 is connected to the first light-emission control signal line EM1, the source is connected to the first power supply voltage terminal, and the drain is connected to the second node N2. The second light-emission control unit 307 includes a sixth transistor T6; the gate of the sixth transistor T6 is connected to the second light-emission control signal line, the source is connected to the third node N3, and the drain is connected to the fourth node N4. The first storage unit 305 includes a first storage capacitor C1; one end of the first storage capacitor C1 is connected to the first node N1 and the other end is connected to the third node N3. The fourth transistor T4 and the fifth transistor T5 are multiplexed into the threshold compensation unit 304.

[0065] FIG3 is a working timing diagram of the pixel circuit shown in FIG2 . As shown in FIG3 , the working process of the pixel circuit is divided into: a first stage t1 , a second stage t2 , a third stage t3 and a fourth stage t4 .

[0066] In the first phase t1, the second scan signal, the third scan signal, and the second light-emitting control signal are high, while the first scan signal and the first light-emitting control signal are low. At this point, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned on. The second initialization signal is written to and resets the fourth node N4, the third node N3, and the second node N2. The first initialization signal is written to and resets the first node N1. The first node N1, the second node N2, the third node N3, and the fourth node N4 are all reset to their initial voltages, and the first storage capacitor C1 is also initialized.

[0067] In the second phase t2, the third scanning signal and the first light emitting control signal are high level, the first transistor T1 and the fifth transistor T5 are turned on, and the gate-source voltage Vgs of the fourth transistor T4 is V ref -V ar , is also in the on state, the third node N3 is charged to The first node N1 remains in a stable state due to the input of the second initialization signal.

[0068] In the third stage t3, the first scanning signal is high, the second scanning signal, the third scanning signal, the first light-emitting control signal, and the second light-emitting control signal are low, the second transistor T2 is turned on, and the voltage of the first node N1 is V ref Pull up to V data The voltage of the third node N3 is coupled by the first storage capacitor C1, and its voltage rises by V data -V ref , at this time the gate-source voltage of the first transistor T1

[0069] In the fourth stage t4, the first light-emitting control signal and the second light-emitting control signal are at a high level, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on, and the driving current drives the light-emitting device D to emit light. The driving current formula is: The driving current formula does not include Vth _T1 The factor represents that the pixel circuit can perform threshold voltage compensation on the first transistor T1 to bring about better display uniformity.

[0070] Moreover, the data writing process and the threshold compensation process are separated, which can infinitely extend the threshold compensation time to ensure that a better compensation effect can be achieved when using processes with low electron mobility such as oxide transistors and high-frequency displays, thereby improving the display effect.

[0071] FIG4 is a schematic diagram of the structure of a second pixel circuit provided in an embodiment of the present disclosure. As shown in FIG4 , the structure of the pixel circuit is similar to that of the pixel circuit shown in FIG2 , wherein the first transistor T1, the first initialization unit 301, the second initialization unit 302, the data writing unit 303, the threshold compensation unit 304, the first storage unit 305, the first light-emitting control unit 306, the second light-emitting control unit 307, and the light-emitting device D are all the same as those shown in FIG2 , except that the pixel circuit further includes a second storage unit 308; the second storage unit 308 is configured to store the voltage of the third node N3. The second storage unit 308 includes a second storage capacitor C2; one end of the second storage capacitor C2 is connected to the third node N3, and the other end is connected to the high-level power supply voltage terminal VDD.

[0072] The operation process of the pixel circuit shown in FIG4 may also refer to the operation timing diagram shown in FIG3 .

[0073] In the first phase t1, the second scan signal, the third scan signal, and the second light-emitting control signal are high, while the first scan signal and the first light-emitting control signal are low. At this point, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned on. The second initialization signal is written to and resets the fourth node N4, the third node N3, and the second node N2. The first initialization signal is written to and resets the first node N1. The first node N1, the second node N2, the third node N3, and the fourth node N4 are all reset to their initial voltages, and the first storage capacitor C1 is also initialized.

[0074] In the second phase t2, the third scanning signal and the first light emitting control signal are high level, the first transistor T1 and the fifth transistor T5 are turned on, and the gate-source voltage Vgs of the fourth transistor T4 is V ref -V ar , is also in the on state, the third node N3 is charged to The first node N1 remains in a stable state due to the input of the second initialization signal.

[0075] In the third stage t3, the first scanning signal is high, the second scanning signal, the third scanning signal, the first light-emitting control signal, and the second light-emitting control signal are low, the second transistor T2 is turned on, and the voltage of the first node N1 is V ref Pull up to V data The voltage of the third node N3 is coupled by the first storage capacitor C1, and its voltage rises At this time, the gate-source voltage of the first transistor T1 is

[0076] In the fourth stage t4, the first light-emitting control signal and the second light-emitting control signal are at a high level, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on, and the driving current drives the light-emitting device D to emit light. The driving current formula is: The driving current formula does not include Vth _T1 The factor indicates that the pixel circuit can compensate the threshold voltage of the first transistor T1 to achieve better display uniformity. In addition, its driving current is also related to the first storage capacitor C1 and the second storage capacitor C2. By controlling the capacitance values ​​of the first storage capacitor C1 and the second storage capacitor C2, the range of the data signal can be adjusted to achieve brightness adjustment of the light-emitting device D.

[0077] Figure 5 is a structural schematic diagram of the third pixel circuit provided in an embodiment of the present disclosure. As shown in Figure 5, the structure of the pixel circuit is similar to that of the pixel circuit shown in Figure 4, wherein the first transistor T1, the second initialization unit 302, the data writing unit 303, the threshold compensation unit 304, the first storage unit 305, the first light-emitting control unit 306, the second light-emitting control unit 307, the second storage unit 308 and the light-emitting device D are all the same as the structure shown in Figure 4, except that, in the pixel circuit shown in Figure 5, the fourth transistor T4 is not provided, and the second transistor T2 is reused as the first initialization unit 301.

[0078] The data signal line Data connected to the gate of the second transistor T2 can transmit a first reset signal in the first phase t1 and a data signal in the third phase t3, to ensure that the first reset signal and the data signal can be written to the first node N1 in a time-sharing manner. This can reduce the number of transistors, which is beneficial for improving the pixel aperture ratio and enhancing the display effect. In practical applications, the first reset signal and the data signal can be provided to the data signal line Data in a time-sharing manner by adjusting the driver chip. The operation process of the pixel circuit shown in Figure 5 can also be referred to the operation timing diagram shown in Figure 3, and will not be repeated here.

[0079] FIG6 is a schematic structural diagram of a fourth pixel circuit provided in an embodiment of the present disclosure. As shown in FIG6 , the structure of the pixel circuit is similar to that of the pixel circuit shown in FIG4 , wherein the first transistor T1, the first initialization unit 301, the second initialization unit 302, the data writing unit 303, the threshold compensation unit 304, the first storage unit 305, the first light-emitting control unit 306, the second light-emitting control unit 307, the second storage unit 308, and the light-emitting device D are all the same as those shown in FIG4 , except that, in the pixel circuit shown in FIG6 , the drain of the third transistor T3 is connected to the third node N3. The operation process of the pixel circuit shown in FIG6 can also refer to the operation timing diagram shown in FIG3 , which will not be described in detail here.

[0080] FIG7 is a schematic structural diagram of a fifth pixel circuit provided in an embodiment of the present disclosure. As shown in FIG7 , the structure of the pixel circuit is similar to that of the pixel circuit shown in FIG4 , wherein the first transistor T1, the second initialization unit 302, the data writing unit 303, the threshold compensation unit 304, the first storage unit 305, the first light-emitting control unit 306, the second light-emitting control unit 307, the second storage unit 308, and the light-emitting device D are all the same as those shown in FIG4 , except that, in the pixel circuit shown in FIG7 , the fourth transistor T4 is not provided, the second transistor T2 is reused as the first initialization unit 301, and the drain of the third transistor T3 is connected to the third node N3. The operation process of the pixel circuit shown in FIG7 can also refer to the operation timing diagram shown in FIG3 , and will not be described in detail here.

[0081] FIG8 is a schematic structural diagram of a sixth pixel circuit provided in an embodiment of the present disclosure. As shown in FIG8 , the structure of the pixel circuit is similar to that of the pixel circuit shown in FIG4 , wherein the first transistor T1, the second initialization unit 302, the data writing unit 303, the threshold compensation unit 304, the first storage unit 305, the first light-emitting control unit 306, the second light-emitting control unit 307, the second storage unit 308, and the light-emitting device D are all the same as those shown in FIG4 , except that, in the pixel circuit shown in FIG8 , the second storage capacitor C2 is not provided, and the drain of the third transistor T3 is connected to the third node N3. The operation process of the pixel circuit shown in FIG7 can also refer to the operation timing diagram shown in FIG3 , and will not be described in detail here.

[0082] FIG9 is a schematic diagram of the structure of the seventh pixel circuit provided by an embodiment of the present disclosure. As shown in FIG9 , the structure of the pixel circuit is similar to that of the pixel circuit shown in FIG2 . The first transistor T1 serves as a driving transistor and can adopt a dual-gate structure. In addition to the gate (top gate) shown in each of the above-mentioned pixel circuits, it also includes another gate (bottom gate) arranged opposite to the gate. The other gate can be connected to the third node N3. In this way, the first transistor T1 can form a source-connected structure, and the characteristics of the first transistor T1 can be adjusted by changing the voltage of the other gate (bottom gate). In addition to being connected to the third node N3, the other gate (bottom gate) of the first transistor T1 can also be connected to the first node N1, that is, the two gates of the first transistor T are connected to the same signal to form a bottom-top dual-gate structure. It can also be connected to the high-level power supply voltage terminal VDD, the low-level power supply voltage terminal VSS, the first initialization signal line Vref, the second initialization signal line Var, the ground terminal Gnd, and other possible stable signal sources. At the same time, for array substrates of different frequencies, different bottom gate potentials can be used for high-frequency (120 Hz) display and low-frequency (60 Hz) display. For example, during high-frequency display, the other gate (bottom gate) of the first transistor T1 can adopt a high-level potential, which can be connected to a high-level potential terminal such as the high-level power supply voltage terminal VDD or the first initialization signal line Vref. During low-frequency display, the other gate (bottom gate) of the first transistor T1 can adopt a low-level potential, for example, during low-frequency display, the other gate (bottom gate) of the first transistor T1 can be connected to a low-level potential terminal such as the low-level power supply voltage terminal VSS, the second initialization signal line Var, or the ground terminal Gnd. This allows the bottom gate potential to be dynamically adjusted, which is beneficial to the display uniformity of the display device under different display modes.

[0083] Figure 10 is a structural schematic diagram of the eighth pixel circuit provided in an embodiment of the present disclosure. As shown in Figure 10, the structure of the pixel circuit is similar to the structure of the pixel circuit shown in Figure 2. Since the second light-emitting control signal line EM2 is a low-level signal most of the time, the sixth transistor T6 is in a normally-on state, and the voltages of the third node N3 and the fourth node N4 are basically the same. Therefore, the other gate (bottom gate) of the first transistor T1 can also be connected to the fourth node N4.

[0084] It should be further explained that, in addition to the first transistor T1 mentioned above, other transistors (the second transistor T2 to the sixth transistor T6) may also adopt a top-bottom double-gate structure in addition to the single-gate structure in the above embodiments, or some transistors may adopt a top-bottom double-gate structure, which will not be described in detail here.

[0085] The pixel circuit provided by the embodiment of the present disclosure can be used not only for high-frequency display, but also for low-frequency display. When the gate drive signal output by some shift registers in the gate drive circuit is low-frequency, it can be matched with a pause function (the first clock signal CLK no longer jumps at low frequency) to achieve lower power consumption. The first gate line G1 and the second gate line G2 can pause and maintain a low-level signal to save energy. The third gate line G3 can reduce the frequency as needed in order to reset the fourth node N4 and improve the flicker (Flicker) of the display device. The second light-emitting control signal line EM2 can pause and maintain a high-level signal to save power. If the first light-emitting control signal line EM1 considers pulse width modulation (PWM) dimming, it is consistent with high-frequency drive. If PWM dimming is not considered, the second light-emitting control signal line EM2 can pause and maintain a low-level signal to save energy.

[0086] Second, embodiments of the present disclosure provide a display device comprising a pixel circuit as provided in any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a television, mobile phone, monitor, laptop computer, digital photo frame, or navigation system. The implementation principles of the display device are similar to those of the aforementioned pixel circuits and will not be further elaborated here.

[0087] In a third aspect, an embodiment of the present disclosure provides a method for driving a pixel circuit, which can drive a pixel circuit as provided in any of the above embodiments. The method for driving a pixel circuit includes the following steps.

[0088] In the first phase, the voltage of the first node N1 is reset by the first initialization signal in response to the second scan signal; and the voltages of the second node N2, the third node N3 and the fourth node N4 are reset by the second initialization signal in response to the third scan signal.

[0089] In the second phase, the threshold voltage is written to the third node N3 in response to the second scan signal and the first light emitting control signal.

[0090] In the third phase, a data signal is written into the first node N1 in response to the first scan signal.

[0091] In the fourth stage, in response to the first light emitting control signal, the first power supply voltage is transmitted to the first transistor T1 to convert the first voltage into a driving current; and in response to the second light emitting control signal, the driving current generated by the first transistor T1 is written into the anode of the light emitting device D.

[0092] The driving method of the pixel circuit provided by the embodiment of the present disclosure is further described in detail below by taking the specific pixel circuit shown in FIG. 4 as an example.

[0093] In the first phase t1, the second scan signal, the third scan signal, and the second light-emitting control signal are high, while the first scan signal and the first light-emitting control signal are low. At this point, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned on. The second initialization signal is written to and resets the fourth node N4, the third node N3, and the second node N2. The first initialization signal is written to and resets the first node N1. The first node N1, the second node N2, the third node N3, and the fourth node N4 are all reset to their initial voltages, and the first storage capacitor C1 is also initialized.

[0094] In the second phase t2, the third scanning signal and the first light emitting control signal are high level, the first transistor T1 and the fifth transistor T5 are turned on, and the gate-source voltage Vgs of the fourth transistor T4 is V ref -V ar , is also in the on state, the third node N3 is charged to The first node N1 remains in a stable state due to the input of the second initialization signal.

[0095] In the third stage t3, the first scanning signal is high, the second scanning signal, the third scanning signal, the first light-emitting control signal, and the second light-emitting control signal are low, the second transistor T2 is turned on, and the voltage of the first node N1 is V ref Pull up to V data The voltage of the third node N3 is coupled by the first storage capacitor C1, and its voltage rises At this time, the gate-source voltage of the first transistor T1 is

[0096] In the fourth stage t4, the first light-emitting control signal and the second light-emitting control signal are at a high level, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on, and the driving current drives the light-emitting device D to emit light. The driving current formula is: The driving current formula does not include Vth _T1 The factor indicates that the pixel circuit can compensate the threshold voltage of the first transistor T1 to achieve better display uniformity. In addition, its driving current is also related to the first storage capacitor C1 and the second storage capacitor C2. By controlling the capacitance values ​​of the first storage capacitor C1 and the second storage capacitor C2, the range of the data signal can be adjusted to achieve brightness adjustment of the light-emitting device D.

[0097] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A pixel circuit, wherein: The pixel circuit comprises: a first transistor, a first initialization unit, a second initialization unit, a data writing unit, a threshold compensation unit, a first storage unit, a first light emitting control unit, a second light emitting control unit and a light emitting device; The control electrode of the first transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; The first electrode of the light emitting device is connected to the fourth node, and the second electrode is connected to the second power supply voltage terminal; The data writing unit is configured to write a data signal into the first node in response to a first scanning signal; The first initialization unit is configured to reset the voltage of the first node using the first initialization signal in response to the second scan signal; The second initialization unit is configured to reset the voltages of the second node, the third node, and the fourth node using a second initialization signal in response to the third scan signal; The threshold compensation unit is configured to write a threshold voltage into a third node in response to a second scan signal and a first light emitting control signal; The first storage unit is configured to store voltages of the first node and the third node; The first light emitting control unit is configured to transmit a first power supply voltage to the driving transistor in response to a first light emitting control signal to convert the first voltage into a driving current; The second light emitting control unit is configured to write the driving current generated by the driving transistor into the first electrode of the light emitting device in response to a second light emitting control signal.

2. The pixel circuit according to claim 1, wherein: The data writing unit comprises: a second transistor; The control electrode of the second transistor is connected to the first scanning signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the first node.

3. The pixel circuit according to claim 2, wherein: The first initialization unit includes: a fourth transistor; The control electrode of the fourth transistor is connected to the second scanning signal line, the first electrode is connected to the first initialization signal line, and the second electrode is connected to the first node.

4. The pixel circuit according to claim 3, wherein: The second initialization unit includes: a third transistor; The control electrode of the third transistor is connected to the third scanning signal line, the first electrode is connected to the second initialization signal line, and the second electrode is connected to the fourth node.

5. The pixel circuit according to claim 3, wherein: The second initialization unit includes: a third transistor; The control electrode of the third transistor is connected to the third scanning signal line, the first electrode is connected to the second initialization signal line, and the second electrode is connected to the third node.

6. The pixel circuit according to claim 4 or 5, wherein: The first light emitting control unit comprises: a fifth transistor; The control electrode of the fifth transistor is connected to the first light emitting control signal line, the first electrode is connected to the first power supply voltage terminal, and the second electrode is connected to the second node.

7. The pixel circuit according to claim 6, wherein: The second light emitting control unit comprises: a sixth transistor; The control electrode of the sixth transistor is connected to the second light emitting control signal line, the first electrode is connected to the third node, and the second electrode is connected to the fourth node.

8. The pixel circuit according to claim 7, wherein: The first storage unit includes: a first storage capacitor; One end of the first storage capacitor is connected to the first node, and the other end is connected to the third node.

9. The pixel circuit according to claim 8, wherein: The fourth transistor and the fifth transistor are multiplexed as the threshold compensation unit.

10. The pixel circuit according to claim 9, wherein: The second transistor is multiplexed as the first initialization unit.

11. The pixel circuit according to claim 1, wherein: The pixel circuit further includes: a second storage unit; The second storage unit is configured to store a voltage of the third node.

12. The pixel circuit according to claim 11, wherein: The second storage unit includes: a second storage capacitor; One end of the second storage capacitor is connected to the third node, and the other end is connected to the first power supply voltage terminal.

13. A display device, wherein: The display device comprises the pixel circuit according to any one of claims 1 to 12.

14. A method for driving a pixel circuit, wherein: The driving method of the pixel circuit comprises: In the first stage, in response to the second scan signal, the voltage of the first node is reset using the first initialization signal; and in response to the third scan signal, the voltages of the second node, the third node and the fourth node are reset using the second initialization signal; In the second stage, in response to the second scan signal and the first light emitting control signal, a threshold voltage is written into the third node; In the third stage, in response to the first scan signal, a data signal is written into the first node; In the fourth stage, in response to the first light emitting control signal, the first power supply voltage is transmitted to the driving transistor to convert the first voltage into a driving current; and in response to the second light emitting control signal, the driving current generated by the driving transistor is written into the first electrode of the light emitting device.

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