Information processing method, information processing system, calculation quantum circuit, method for generating calculation quantum circuit, and program

Abstract

One aspect of the present invention provides an information processing method. The information processing method includes the following steps. In an acquisition step, information related to an input state that is represented by n calculation quantum bits, information related to a Hamiltonian, and the number K of repetitions (K is an integer of 2 or more) of an operation that is based on the Hamiltonian are acquired. In an allocation step, plurality of auxiliary bits are allocated in accordance with the number K of repetitions. The states of the n calculation quantum bits and the plurality of auxiliary bits are configured to be expressable with use of at least a first state and a second state which are observable. In a generation step, a calculation quantum circuit is generated on the basis of the acquisition result in the acquisition step. The calculation quantum circuit is configured to cause a first reflection operation, a first operation quantum circuit, a second reflection operation, and a second operation quantum circuit to act in this order. The first reflection operation is configured to act on the plurality of auxiliary bits so as to change the phase of a first reflection state, which is one of a first state component and a second state component included in the plurality of auxiliary bits. The first operation quantum circuit is configured to act on n calculation quantum bits corresponding to an input state, and includes unit gate operations corresponding to the auxiliary bits. The unit gate operations are each configured such that one of a plurality of differing auxiliary bits is a control bit, a calculation quantum bit is a target bit, and the mode of acting on the calculation quantum bit is changed in accordance with the state of an auxiliary bit. The second reflection operation is configured to act on a calculation quantum bit and an auxiliary bit so as to change the phase of a second reflection state, which is one of a first state component and a second state component included in the calculation quantum bit and the auxiliary bit. The second operation quantum circuit is configured to enable conversion into a Hermite-coupled circuit of the first operation quantum circuit using a prescribed unitary gate operation.

Description

Information processing method, information processing system, computational quantum circuit, computational quantum circuit generation method, and program

[0001] The present invention relates to an information processing method, a computational quantum circuit, a method for generating a computational quantum circuit as set forth in claim 10, an information processing system, and a program.

[0002] Quantum information processing, which uses quantum mechanics for information processing, has been proposed. Quantum computers based on such quantum information processing have also been extensively studied. For example, Patent Document 1 discloses conventional techniques for quantum information processing. Non-patent documents are reference documents.

[0003] Japanese Patent Application Laid-Open No. 2015-135377

[0004] H. Nishi, K. Hamada, Y. Nishiya, T. Kosugi, and Y. ichiro Matsushita, Analyzing computational cost of probabilistic imaginary-time evolution method (2023), arXiv:2305.04600 [quant-ph].

[0005] However, there is still room for improvement in the technique for obtaining a desired state, such as the ground state, of a Hamiltonian.

[0006] According to one aspect of the present invention, there is provided an information processing method. This information processing method includes the following steps: in the acquisition step, information on an input state represented by n computational quantum bits, information on a Hamiltonian, and the number of iterations K (where K is an integer equal to or greater than 2) of an operation based on the Hamiltonian are acquired; in the allocation step, multiple auxiliary bits are assigned according to the number of iterations K, where each state of the n computational quantum bits and the multiple auxiliary bits is configured to be representable using at least a first state and a second state that are observable; in the generation step, a computational quantum circuit is generated based on the results acquired in the acquisition step; the computational quantum circuit is configured to sequentially apply a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit; the first reflection operation is configured to act on the multiple auxiliary bits so as to change the phase of a first reflection state, which is one of the first state component and the second state component included in each of the multiple auxiliary bits. The first operational quantum circuit is configured to operate on n computation qubits corresponding to an input state and includes a unit gate operation corresponding to each of the ancillary bits. Each of the unit gate operations is configured to use one of a plurality of different ancillary bits as a control bit, the computation qubit as a target bit, and to change the manner of operation on the computation qubit depending on the state of the ancillary bit. The second reflection operation is configured to operate on the computation qubit and the ancillary bit so as to change the phase of a second reflection state, which is one of the first state component and the second state component contained in each of the computation qubit and the ancillary bit. The second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

[0007] This makes it possible to provide a quantum algorithm that makes it easier to obtain a desired state more efficiently.

[0008] 1 is a configuration diagram showing an information processing system 1. FIG. 2 is a block diagram showing the hardware configuration of an information processing device 2. FIG. 3 is a block diagram showing the hardware configuration of a quantum computer 3. FIG. 4 is a block diagram showing the hardware configuration of a user terminal 4. FIG. 5 is a block diagram showing the functional configuration of a processor 23. FIG. 6 is a diagram showing an example of a quantum circuit QC1 of a probabilistic algorithm for preparing the ground state of a Hamiltonian. FIG. 7 is a diagram showing an example of a computational quantum circuit 5. ＲＴＥ FIG. 1 is a diagram showing an example of ＲＴＥ 1 is a diagram showing a modified example of the above. 2 is a flowchart showing an overview of information processing executed in the information processing system 1. 3 is a diagram showing simulation results of the relationship between computational cost and infidelity δK in each method for generating the ground state of Hamiltonian H. 4 is a diagram showing simulation results of the relationship between the probability weight |c1|-1 of the ground state of the input state |ψ> and computational cost using each method. 5 is a quantum circuit that implements a time evolution operator exp(LΔt) with a general operator L as a generator. 6 is a quantum circuit that implements an imaginary time evolution operator exp(-HΔτ) with a general Hermitian operator H as a generator. 7 is an example of a quantum circuit QC2 corresponding to a cosine function operator cos(tkH). 8 is a diagram showing an example of a computational quantum circuit when a cosine function operator cos(tkH) is adopted as a probabilistic operation.

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. Various features shown in the following embodiments can be combined with each other.

[0010] Incidentally, the program for realizing the software appearing in this embodiment may be provided as a non-transitory computer-readable recording medium, or may be provided so as to be downloadable from an external server, or may be provided so that the program is started on an external computer and its functions are realized on a client terminal (so-called cloud computing).

[0011] In this embodiment, the term "unit" may include, for example, a combination of hardware resources implemented by a circuit in the broad sense and software information processing that can be specifically realized by these hardware resources. In addition, various types of information are handled in this embodiment, and this information may be represented by, for example, physical values ​​of signal values ​​representing voltages and currents, high and low signal values ​​as a binary bit set consisting of 0 or 1, or quantum superposition (so-called quantum bits), and communication and calculations may be performed on a circuit in the broad sense.

[0012] Furthermore, a circuit in the broad sense is a circuit realized by at least an appropriate combination of a circuit, circuitry, a processor, a memory, etc. That is, it includes an application specific integrated circuit (ASIC), a programmable logic device (e.g., a simple programmable logic device (SPLD), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA)), etc.

[0013] 1. Hardware Configuration In this section, the hardware configuration of an information processing system 1 according to this embodiment will be described. <Information Processing System 1> FIG. 1 is a configuration diagram showing the information processing system 1. The information processing system 1 includes an information processing device 2, at least one quantum computer 3, and a user terminal 4. The information processing device 2, the quantum computer 3, and the user terminal 4 are configured to be able to communicate with each other via a telecommunications line. In one embodiment, the information processing system 1 is made up of one or more devices or components. For example, if the information processing system 1 is made up of only the information processing device 2, the information processing system 1 can be the information processing device 2. These components will be described below.

[0014] 2 is a block diagram showing the hardware configuration of the information processing device 2. The information processing device 2 includes a communication unit 21, a storage unit 22, and a processor 23, and these components are electrically connected via a communication bus 20 inside the information processing device 2. Each component will be further described.

[0015] <Communication Unit 21> The communication unit 21 is preferably a wired communication means such as USB, IEEE 1394, Thunderbolt (registered trademark), or wired LAN network communication, but may also include wireless LAN network communication, mobile communication such as 3G / LTE / 5G, or BLUETOOTH (registered trademark) communication as needed. In other words, it is more preferable to implement the communication unit 21 as a collection of multiple communication means. In other words, the information processing device 2 may communicate various information from the outside via the communication unit 21 and the network.

[0016] <Storage Unit 22> The storage unit 22 stores various pieces of information defined above. This may be implemented, for example, as a storage device such as a solid state drive (SSD) that stores various programs and the like related to the information processing device 2 executed by the processor 23, or as a memory such as a random access memory (RAM) that stores temporarily required information (arguments, arrays, etc.) related to program calculations. The storage unit 22 stores various programs, variables, etc. related to the information processing device 2 executed by the processor 23.

[0017] <Processor 23> The processor 23 processes and controls the overall operations related to the information processing device 2. The processor 23 is, for example, a central processing unit (CPU) not shown. The processor 23 realizes various functions related to the information processing device 2 by reading out predetermined programs stored in the storage unit 22. In other words, information processing by software stored in the storage unit 22 is specifically realized by the processor 23, which is an example of hardware, and can be executed as each functional unit included in the processor 23. These will be described in more detail in the next section. Note that the processor 23 is not limited to being single, and multiple processors 23 may be provided for each function. A combination of these may also be used.

[0018] <Quantum Computer 3> Fig. 3 is a block diagram showing the hardware configuration of the quantum computer 3. As shown in Fig. 3, the quantum computer 3 has a communication unit 31, a quantum memory 32, and a quantum processor 33, and these components are connected via a communication bus 30 inside the quantum computer 3. Note that the quantum computer 3 may include an error-tolerant quantum computer, an NISQ device, or both. The quantum computer 3 of this embodiment is a gate type. Each component will be further described below.

[0019] <Communication Unit 31> The communication unit 31 is used by the quantum computer 3 to communicate information with other information processing devices (including classical computers, quantum computers, or computers that combine these) or peripheral devices.

[0020] <Quantum Memory 32> The quantum memory 32 stores various pieces of information defined above. In particular, the quantum memory 32 stores various programs that can be read by the quantum processor 33, which will be described next. The quantum memory 32 also stores, as necessary, information on the physical properties of specific materials related to the calculations of the quantum computer 3. The quantum memory 32 includes a plurality of quantum bits 320. The quantum bits 320 can be implemented using any method, such as nuclear spins, photons, ions, atoms, quantum dots, or superconducting Josephson devices. The quantum bits 320 include a computational quantum bit 321 and an ancillary bit 322. The quantum memory 32 may also include a classical memory device.

[0021] The quantum bit 320 can take any state within a state space represented by at least two basis vectors. Each state of the quantum bit 320 in this embodiment is represented by a superposition of a basis vector |1> representing a first state and a basis vector |0> representing a second state. Each of the basis vectors |0>, |1> is configured to be observable. For convenience, the quantum bit 320 includes a computation quantum bit 321 and an auxiliary bit 322. In other words, each state of the n computation quantum bits 321 and the K auxiliary bits 322 is configured to be expressible using at least the first state |0> and the second state |1>, which are observable.

[0022] <Quantum Processor 33> The quantum processor 33 processes and controls the overall operations related to the quantum computer 3. The quantum processor 33 realizes various functions related to the quantum computer 3 by reading out a program stored in the quantum memory 32 or a predetermined program input via the communication unit 31. Note that while Fig. 3 shows a single quantum processor 33, in practice this is not limited to this, and multiple quantum processors 33 may be implemented for each function. A combination of these may also be used.

[0023] The quantum processor 33 is configured to be able to perform various quantum operations that can be implemented on a quantum circuit on the quantum bit 320. For example, the quantum circuit is configured to define a series of quantum operations on the quantum bit 320. The quantum operations include, for example, a quantum gate operation and an observation operation. A quantum gate operation corresponds to a unitary operation on the quantum state of the quantum bit 320. An observation operation corresponds to a projection operation on the quantum state of the quantum bit 320. In other words, a quantum circuit such as the computational quantum circuit 5 described below can be considered a type of program that causes the quantum computer 3 to execute a series of quantum operations.

[0024] <User Terminal 4> Next, the hardware configuration of the user terminal 4 will be described. Fig. 4 is a block diagram showing the hardware configuration of the user terminal 4. The user terminal 4 includes a communication unit 41, a memory 42, a processor 43, a display unit 44, and an input unit 45, and these components are electrically connected via a communication bus 40 inside the user terminal 4. The description of the communication unit 41, the memory 42, and the processor 43 is omitted because they are the same as the description of each unit in the information processing device 2.

[0025] <Display Unit 44> The display unit 44 may be included in the housing of the user terminal 4 or may be externally attached. The display unit 44 displays a graphical user interface (GUI) screen that can be operated by the user. This is preferably implemented by selectively using display devices such as a CRT display, a liquid crystal display, an organic EL display, or a plasma display depending on the type of user terminal 4.

[0026] <Input Unit 45> The input unit 45 may be included in the housing of the user terminal 4, or may be externally attached. For example, the input unit 45 may be implemented as a touch panel integrated with the display unit 44. A touch panel allows the user to input tapping, swiping, and the like. Of course, a switch button, a mouse, a QWERTY keyboard, or the like may be used instead of a touch panel. That is, the input unit 45 accepts an operation input made by the user. The input is transferred as a command signal to the processor 43 via the communication bus 40, and the processor 43 can execute predetermined control or calculation as necessary.

[0027] 2. Functional Configuration of the Processor 23 In this section, the functional configuration of the processor 23 of the information processing device 2 according to this embodiment will be described. Fig. 5 is a block diagram showing the functional configuration of the processor 23. The processor 23 includes an acquisition unit 231, an allocation unit 232, a generation unit 233, a quantum operation unit 234, and an output unit 235.

[0028] <Acquisition unit 231> As an acquisition step, the acquisition unit 231 is configured to be able to acquire various pieces of information related to quantum computing from the quantum computer 3 and the user terminal 4. The acquisition unit 231 is configured to be able to acquire various pieces of information by reading out various pieces of information stored in a storage area that is at least a part of the memory unit 22 and writing the read out information to a working area that is at least a part of the memory unit 22. The storage area is, for example, an area of ​​the memory unit 22 that is implemented as a storage device such as an SSD. The working area is, for example, an area that is implemented as a memory such as a RAM.

[0029] <Allocating Unit 232 > The allocating unit 232 is configured to allocate at least some of the quantum bits 320 as computation quantum bits 321 and auxiliary bits 322 as an allocating step.

[0030] <Generation unit 233> The generation unit 233 is configured to generate various information such as quantum circuits such as the computational quantum circuit 5 based on acquired information, etc. A quantum circuit such as the computational quantum circuit 5 is a type of program and is an instruction related to a series of quantum operations that the quantum processor 33 performs on the quantum bit 320. Details of the computational quantum circuit 5 will be described later.

[0031] <Quantum Operation Unit 234> The quantum operation unit 234 is configured to be able to perform various quantum operations on the quantum bits 320. For example, the quantum operation unit 234 causes the quantum processor 33 to perform a series of quantum operations on the quantum bits 320 based on the computational quantum circuit 5 generated by the generation unit 233. The quantum operation unit 234 may be configured to perform quantum operations directly on the quantum bits 320, or may be configured to send a command to cause the quantum processor 33 to perform a quantum operation. The quantum operation unit 234 of this embodiment causes the quantum processor 33 to perform quantum operations by sending various quantum circuits, such as the computational quantum circuit 5 described below, to the quantum processor 33.

[0032] <Output Unit 235> The output unit 235 is configured to output, as an output step, the calculation result of the quantum operation by the quantum operation unit 234, for example, the state of the calculation qubit 321 operated by the quantum circuit.

[0033] 3. About the theory This section provides an overview of the theory behind this information processing.

[0034] 3.1 Quantum Algorithm for Obtaining a Desired State Here, we discuss a non-unitary operation f(H) based on a Hamiltonian H in a system consisting of n computational qubits 321. The non-unitary operation f(H) is incorporated into the following extended unitary matrix U by introducing one auxiliary bit 322.

[0035] Here, the non-unitary matrix U is expressed as a submatrix related to a desired state and a state orthogonal to it. The desired state is, for example, a state in which the auxiliary bit 322 is observed as the |0> state. The state orthogonal to it is, for example, a state in which it is observed as the |1> state. When an input state |ψ>*|0> is input, the action of the unitary matrix U leads to the following state. In this specification, the operation symbol "*" generally represents a Kronecker product.

[0036] Any unitary matrix U can be decomposed to at least the first order of the Hamiltonian H, and the forward real-time evolution operator U ＲＴＥ and the inverse real-time evolution operator U ＲＴＥ † and one-qubit gate operations.

[0037] FIG. 6 is a diagram showing an example of a quantum circuit QC1 of a probabilistic algorithm for preparing the ground state of a Hamiltonian. The quantum circuit QC1 of this embodiment is configured to operate on an n+1 quantum bit system consisting of n computation quantum bits 321 and one auxiliary bit 322. The initial state of the n quantum bit system is a predetermined input state |ψ>, and the initial state of the auxiliary bit 322 is the |0> state. The quantum circuit QC1 first performs a predetermined unitary operation (e.g., a Hadamard gate operation and a W gate operation) on the auxiliary bit 322 to generate the auxiliary bit 322 in a superposition state of the |0> state and the |1> state. The quantum circuit QC1 then performs different operations on the input state |ψ> depending on the state of the auxiliary bit 322. For example, when the auxiliary bit 322 is in the |0> state, the quantum circuit QC1 performs a forward real-time evolution operator U ＲＴＥ When the auxiliary bit 322 is in the |1> state, the inverse real-time evolution operator U ＲＴＥ †The quantum circuit QC1 is configured to operate on the input state |ψ> by f(H). Such an operation can be implemented, for example, using a control gate operation in which the ancillary bit 322 is used as a control bit and the n computation qubits 321 are used as target bits. The quantum circuit QC1 is then configured to perform a further predetermined unitary operation (e.g., a W-gate operation; the W-gate operation is defined in Equation 24, which will be described later) on the ancillary bit 322, and then to perform an observation operation on the ancillary bit 322. A quantum operation that probabilistically changes the operation mode when performing a certain operation is sometimes called a probabilistic quantum operation. When the ancillary bit 322 is observed as being in the |0> state, the state of the computation qubit 321 can be a state in which f(H) has operated on the input state |ψ>. This makes it possible to extract a state in which f(H) has successfully operated on the input state |ψ> using the quantum circuit QC1.

[0038] When the unitary operation U is operated multiple times, the unitary operation U includes various parameters such as the size of the imaginary time step Δτ. These parameters can be arbitrarily selected in each step in which the unitary operation U is operated. Hereinafter, for convenience of explanation, the unitary operation U in the kth step will be referred to as U ｋ Using K auxiliary bits, U ｋ , and perform the unitary operation U ｋ When the above is executed in order from k=1 to k, the input state |ψ> and the state |0> of the K auxiliary bits 322 are ＊Ｋ changes as follows:

[0039] F Ｋ (H) is f ｋ (H) in order and is expressed as follows:

[0040] The fact that the k-th auxiliary bit 322 is observed in the |0> state is due to f ｋ Therefore, the |0> state in the auxiliary bit 322 means that the operation of f ｋThis means a successful state in which (H) has been successfully calculated on a quantum bit system consisting of the computation quantum bit 321. Hereinafter, for convenience of explanation, the |0> state of the auxiliary bit 322 may be referred to as a successful state. Note that, by observing and initializing the auxiliary bit 322 used in the previous step, and then reusing the initialized auxiliary bit 322, such repeated processing can be performed with a smaller number of auxiliary bits 322. Note that, ｋ An example of (H) is the approximate imaginary time evolution operator exp(-Δτ ｋ H) and the cosine function operator cos(t ｋ H) and the like. ｋ is the time step width for real-time evolution. Using such a quantum circuit QC1, the state of the computation qubit 321 can be guided to an energy eigenstate of the Hamiltonian H, and a desired state for the problem to be solved can be obtained using the computation qubit 321. For example, when solving a problem for finding the minimum energy or ground state of the Hamiltonian H, the desired state of the computation qubit 321 is the ground state. At this time, such a problem can be solved by the operation f ｋ By repeatedly applying (H), it is possible to decay components of states other than the desired state (hereinafter, for convenience of explanation, sometimes referred to as undesired states) contained in the computation qubit 321. The undesired state may be, for example, an excited state. Such quantum information processing can also be used as a method for expressing a decay function having a peak at a certain state. The certain state may be, for example, an eigenstate of the Hamiltonian H, and may be either the ground state or an excited state other than the ground state (e.g., a first excited state).

[0041] By observing all K ancillary bits 322 as |0> states, the entangled wave function converges to the following state:

[0042] P Ｋ indicates the total success probability. The total success probability is the probability that the ancillary bit 322 is observed in the |0> state in all steps from k=1 to K. The input state |ψ> is the i-th eigenstate |λ of the Hamiltonian H. ｉIt can be expanded using > as follows:

[0043] c ｉ is the i-th eigenstate |λ ｉ For the sake of convenience, we will treat each eigenstate as non-degenerate, but the same discussion will hold even if there are degenerate eigenstates. ｉ are set in ascending order of i with respect to their energy eigenvalues.

[0044] F Ｋ If (H) is configured to attenuate undesired states, then the overall success probability P Ｋ is expressed as follows:

[0045] δ Ｋ is the infidelity that indicates the calculation accuracy, and is expressed as follows:

[0046] Here, for convenience of explanation, F Ｋ (λ １ ) = 1. Ｋ can be realized by, for example, performing a certain energy shift in the stochastic imaginary time evolution method. The energy shift is implemented by R ｚ Gate operation rotation angle 2θ ｋ , given energy value E ｋ and the parameter s introduced in the approximation of the stochastic imaginary time evolution operator ｋ Using 2(θ ｋ +Δτ ｋ s ｋ E ｋ ) to improve the overall success rate of quantum amplitude amplification. For details of the energy shift, please refer to Non-Patent Document 1. ｋ Infidelity δ by (H) Ｋ A quantum algorithm that decays unwanted states to reduce the amount of Ｋ is O(|c １ | ２) scales with the total success probability P Ｋ The scaling of ｋ The type of (H), the number of auxiliary bits 322, and the non-unitary operation f ｋ This holds true regardless of the quantum circuit or the like for implementing (H). For example, when the approximate ground state is unknown, for example, |c ｉ | ２ If = 1 / N, the non-unitary operation {f ｋ The computational cost of successfully applying at least one of the non-unitary operations f(H)} to the input state |ψ> scales as O(N). This tendency is seen in so-called stochastic operations, in which applying the non-unitary operation f(H) to the computation qubit 321 is probabilistically successful, particularly depending on the state of the ancillary bit 322. In other words, the operation is a stochastic operation whose success or failure can be expressed depending on the state of the ancillary bit 322.

[0047] When the above-mentioned probabilistic method is used in a CRTE gate (controlled real-time evolution gate), the computational cost remains polynomial, and quantum acceleration can be effectively promoted. For example, n ｅ Circuit depth d required for CRTE gates in an electronic system ＣＲＴＥ scales in the following order:

[0048] Here, Δx represents the grid spacing of the discretized space. The calculation cost at this time is expressed as follows:

[0049] 3.2 Method of Combining a Multi-Step Scheme for a Probabilistic Algorithm with Quantum Amplitude Amplification (QAA) One way to achieve further quantum acceleration in the above-mentioned operations (particularly stochastic operations) is to increase the probability of observing a successful state by quantum amplitude amplification. In this section, we will explain a method of combining a multi-step scheme for a probabilistic algorithm for obtaining the ground state of the Hamiltonian H with quantum amplitude amplification (QAA). Note that the following method is not limited to the ground state, but can also be used as appropriate to obtain any state, for example, an eigenstate other than the ground state or a superposition thereof. Furthermore, the following method is not limited to operations corresponding to a probabilistic algorithm, but can be applied to operations corresponding to any algorithm.

[0050] The multi-step scheme is a method of repeating an operation based on the Hamiltonian H a predetermined number of times. In the following description, the number of repetitions of the operation is assumed to be K. At this time, a number of auxiliary bits 322 corresponding to the number of repetitions K are used. The number of auxiliary bits 322 used in quantum amplitude amplification is arbitrary, and may be 2 or more, or K or more. Here, the number of auxiliary bits 322 is assumed to be K, which is equal to the number of repetitions K. This makes it possible to reduce the number of required quantum bits while suppressing an increase in the quantum circuit depth when performing quantum amplitude amplification. For convenience of explanation, the following description will be given of a case where K auxiliary bits 322 are used.

[0051] Each auxiliary bit 322 is associated with a step of the probabilistic algorithm (operation). After the probabilistic algorithm is executed, an observation operation is performed on all of the auxiliary bits as the final step. The output state |Ψ~> of the (n+K) quantum bit system consisting of n computation quantum bits 321 and K auxiliary bits 322 before the observation operation is expressed as follows: where a is a real number greater than 0 and less than 1.

[0052] Also, |Ψ ｂａｄ > is |Ψ ｇｏｏｄ >. Note that these "good" and "bad" are merely symbols for convenience, and |Ψｂａｄ The states contained in |Ψ are also available to the algorithm depending on the allowable error. ｇｏｏｄ |0> is an example of a second reflection state, and indicates that a state in which K operations on the computation quantum bit 321 are successful and a state in which all of the auxiliary bits 322 are in the |0> state are separable states.

[0053] In one embodiment, quantum amplitude amplification is achieved by applying the amplitude amplification operator m times to the desired state |Ψ ｇｏｏｄ The coefficient of > can be amplified. The amplitude amplification operator is defined as follows:

[0054] where Q(φ ２ｉ－１ , φ ２ｉ ) is defined as follows:

[0055] Here, S χ is an oracle operation, and S ０ is a zero-reflection operation, and U ＲＥＦ （Ｋ） is defined as follows:

[0056] Rotation angle {φ ｉ} is arbitrary and can be selected from, for example, +π or −π. More preferably, the rotation angle {φ ｉ} is determined so that the success probability increases as an approximate sign function. Specifically, it is determined as follows:

[0057] In the above equation, δ represents the calculation accuracy of the success probability, and a smaller δ is preferable. The smaller the ratio of successful states included in the input state |ψ>, the larger the number of iterations m of the amplitude amplification operator needs to be. In other words, the rotation angle {φ ｉ} can be determined based on the number of iterations m of the amplitude amplification operator.

[0058] Zero Reflection S ０ （ｎ） (φ) and the oracle operation S χ (φ) means |Ψ ｇｏｏｄ > and |Ψ ｂａｄIn the effective two-dimensional space with the basis vectors |Ψ~>, the output state |Ψ~> of the (n+K) qubit system is rotated. ０ （ｎ） (φ) and the oracle operation S χ (φ) are expressed as follows:

[0059] The circuit depth of the zero reflection operation scales in the order of O(n) by introducing a new auxiliary bit 322 .

[0060] 3.3 Computational Quantum Circuit 5 In this section, we will explain the computational quantum circuit 5 as a quantum circuit for combining quantum amplitude amplification (QAA) with a multi-step scheme related to the stochastic imaginary time evolution method (PITE method), which is the above-mentioned probabilistic algorithm. FIG. 7 is a diagram showing an example of the computational quantum circuit 5. The computational quantum circuit 5 of this embodiment is also an expression of equation (9) as a quantum circuit, and functions as an amplitude amplification operator in a probabilistic algorithm for outputting the ground state of a predetermined Hamiltonian H. The probabilistic algorithm in this embodiment is the stochastic imaginary time evolution method (PITE method).

[0061] The computational quantum circuit 5 is configured to operate on at least one computational quantum bit 321 and at least K auxiliary bits 322 that are input. The number of computational quantum bits 321 can be set arbitrarily depending on the specific aspect of the computation, and is set to n here. The number of auxiliary bits 322 is set to K so as to correspond to the number of iterations K of the computation. Therefore, the computational quantum circuit 5 is configured to cause the quantum processor 33 to execute a series of operations based on a Hamiltonian on the (n+K)-qubit system, along with quantum amplitude amplification. The computational quantum circuit 5 is configured to operate, in order, on a first reflection operation 51, a first operational quantum circuit 52, a second reflection operation 53, and a second operational quantum circuit 54.

[0062] The first reflection operation 51 is configured to act on the plurality of auxiliary bits 322 so as to change the phase of a first reflection state, which is either one of a component of the first state |0> and a component of the second state |1>, included in each of the plurality of auxiliary bits 322. The first reflection operation 51 may be configured to act individually on each of the plurality of auxiliary bits 322. Also, for example, the first reflection operation 51 may be configured to act on |Ψ as the first reflection state. ｇｏｏｄ The first reflection operation 51 may be configured to rotate, for example, invert, the phase of the entire (n+K) qubit system (global phase). The first reflection operation 51 may be configured to rotate, for example, invert, the phase of the entire (n+K) qubit system (global phase). The first reflection operation 51 may be configured to rotate, for example, invert, the phase of the oracle operation S χ (φ ２ｉ In this embodiment, the |0> state is inverted, which can be said to be zero reflection with respect to the auxiliary bit 322. In this embodiment, the rotation angles of the first reflection operation 51 are φ, φ ２ｉ = π.

[0063] The first operational quantum circuit 52 is configured to operate on n computational qubits 321 corresponding to the input state |ψ>. The first operational quantum circuit 52 receives as input the input state |ψ> and the qubit states of the K ancillary bits 322 on which the first reflection operation 51 has been performed. The first operational quantum circuit 52 operates by (U ＲＥＦ （Ｋ） ) † The first operational quantum circuit 52 includes K unit gate operations 522. The first operational quantum circuit 52 may further include an input transformation operation 521 and an output transformation operation 523.

[0064] The input transformation operation 521 is a one-qubit operation configured to act on each ancillary bit 322 and configured to appropriately superpose the |0> state and the |1> state of each ancillary bit 322. For example, the input transformation operation 521 may be a W-gate operation and a z-rotation gate operation R Ｚ † The z rotary gate operation R Ｚ † The rotation angle 2θｋ is expressed as, for example, Equation 23 described later, and may be determined depending on the expansion mode of the non-unitary operator.

[0065] After the input transformation operation 521 is performed on each of the auxiliary bits 322, a unit gate operation 522 is performed for each auxiliary bit 322. ＲＴＥ Each of the unit gate operations 522 of the first operational quantum circuit 52 is configured to use one of a plurality of different auxiliary bits 322 as a control bit, the computation quantum bit 321 as a target bit, and change the mode of action on the computation quantum bit 321 depending on the state of the auxiliary bit 322. In this embodiment, the unit gate operation 522 is configured to use the forward real-time evolution operator U ＲＴＥ or the inverse real-time evolution operator U ＲＴＥ † In FIG. 7, V ＲＴＥ † (V ＲＴＥ It is expressed as the Hermitian conjugate of V. ＲＴＥ is a forward real-time evolution operator U ＲＴＥ When the control bit (ancillary bit 322) is in an undesired state (|1> state), the forward real-time evolution operator U ＲＴＥ V ＲＴＥ The desired state of is constructed to coincide with the reflection state of the reflection operation that is performed immediately before it. Such a desired state is constructed by applying the forward real-time evolution operator U ＲＴＥ This indicates that the operation of V has been successful, and is also called a successful state. ＲＴＥ Hermitian conjugate of V ＲＴＥ † Therefore, when the corresponding auxiliary bit 322 is in the desired state |0>, the inverse real-time evolution operator U ＲＴＥ † When the corresponding auxiliary bit 322 is in the undesired state |1>, the forward real-time evolution operator UＲＴＥ to the computation qubit 321. In other words, each of the unit gate operations 522 is configured to operate as a unit operation or a Hermitian conjugate operation of the unit operation, U ＲＴＥ or the inverse real-time evolution operator U ＲＴＥ † may be configured to act on the computation qubit 321. ＲＴＥ (or the inverse real-time evolution operator U ＲＴＥ † ) is configured to correspond to performing the operation once, where the desired state of the unit gate operation 522 may coincide with the first reflected state of the first reflected operation 51.

[0066] 7, after a total of K unit gate operations 522, an output transformation operation 523 is performed. The output transformation operation 523 performs a Hermitian operation of a W gate (W † The hologram is configured to sequentially perform a hologram operation (H) and a Hadamard gate operation (H).

[0067] The first operational quantum circuit 52 is a reference circuit 524 (specifically, a reference circuit 524 (U ｒｅｆ ) Hermitian operation reference circuit U ｒｅｆ †). The reference circuit 524 is configured to act on the computation qubits 321 and to output an input state |ψ> based on the initialized state of the computation qubits 321. The states of the n computation qubits 321 after K unit gate operations 522 have been performed in accordance with the state of the ancillary bit 322 are input to the reference circuit 524. In particular, the states of the n computation qubits 321 output from the first operational quantum circuit 52 other than the reference circuit 524 are input to the reference circuit 524. Hereinafter, for convenience of explanation, the initialized states of the n computation qubits 321 may be simply referred to as the initial state. The reference circuit 524 is a quantum circuit for generating an input state |ψ> from the overall state of the n computation qubits 321 of the (n+K) quantum bits 320 input to the first operational quantum circuit 52. In particular, the reference circuit 524 generates an input state |ψ> from the overall state of the n computation qubits 321 of the (n+K) quantum bits 320 input to the first operational quantum circuit 52. In particular, the reference circuit 524 generates an input state |ψ> from the initial state |0> ＊ｎ By inputting |ψ>, an n-qubit system composed of the desired input state |ψ> is generated. This generates a state of an (n+K) qubit system composed of the input state |ψ> and K ancillary bits 322 set to |0>.

[0068] The reference circuit 524 can be set appropriately depending on the input state |ψ> to be generated. For example, the reference circuit 524 is configured to calculate, for each of the computation qubits 321, quantum gate operations corresponding to the difference in amplitude and phase difference of the component of the first state |0> between the initial state and the input state |ψ>, and the difference in amplitude and phase difference of the component of the second state |1> between the initial state and the input state |ψ>. The reference circuit 524 outputs |ψ>*|0> to the computation quantum circuit 5 (more specifically, the first operational quantum circuit 52). ＊Ｋ The reference circuit 524 functions as a quantum circuit for inputting the state of an (n+K) quantum bit system represented by |ψ>. With this configuration, by setting an appropriate input state |ψ> for the Hamiltonian H in advance, it is possible to obtain accurate calculation results with a smaller number of operations. The reference circuit 524 is configured to be executed before the first operational quantum circuit 52.

[0069] The state output from the first operational quantum circuit 52 is input to the second reflection operation 53. The second reflection operation 53 is configured to act on the computation quantum bit 321 and the ancillary bit 322 so as to change the phase of a second reflection state, which is one of the components of the first state |0> and the components of the second state |1> contained in each of the computation quantum bit 321 and the ancillary bit 322. The state of the ancillary bit 322 contained in the first reflection state and the state of the ancillary bit 322 contained in the second reflection state are a common state. In other words, a K-qubit state |0> constituted by K ancillary bits 322 as the first reflection state is ＊Ｋ and a state |0> of a K-qubit system, which is a subset of the (n+K)-qubit system configured by n computation qubits 321 and K auxiliary bits 322 as the second reflection state. ＊Ｋ Therefore, the "common state" does not mean that the states of the entire system input to each of the first reflection operation 51 and the second reflection operation 53 are the same.

[0070] The second reflection operation 53 is the zero reflection S in equation (9). ０ ｎ＋Ｋ (φ ２ｉ＋１ ) It should be noted that the first reflection state and the second reflection state do not need to be identical, as long as there is a correspondence based on a predetermined unitary operation. For example, the first reflection state may be the |0> state, and the second reflection state may be the |1> state. The phase of the first reflection operation 51 may be inverted with respect to the phase of the second reflection operation 53. With this configuration, quantum acceleration can be further promoted by achieving phase matching. In this embodiment, the rotation angle (global phase) φ of the second reflection operation 53 ２ｉ＋１=0, the phase of the first reflection operation 51 and the rotation angle (phase) of the second reflection operation 53 are inverted. Note that the reference circuit 544 may be incorporated into the second reflection operation 53, rather than the first operational quantum circuit 52. In this case, the second reflection operation 53 may be configured to perform zero reflection, which changes the input state |ψ> to the computational quantum circuit 5 into a |0> state, by appropriately unitarily transforming the state output from the first operational quantum circuit 52 by the reference circuit 544.

[0071] The state output from the second reflection operation 53 is input to the second operational quantum circuit 54. The second operational quantum circuit 54 is configured so as to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit 52 using a predetermined unitary gate operation. For example, the second operational quantum circuit 54 is configured to be Hermitian conjugate with the first operational quantum circuit 52, and U in equation (9) ＲＥＦ （Ｋ） The second operational quantum circuit 54, like the first operational quantum circuit 52, includes an input transformation operation 541, K unit gate operations 542, an output transformation operation 543, and a reference circuit 544. The input transformation operation 541 is the Hermitian conjugate of the output transformation operation 523. The unit gate operation 542 is the Hermitian conjugate of the unit gate operation 522. The output transformation operation 543 is the Hermitian conjugate of the input transformation operation 521. The reference circuit 544 (U ｒｅｆ ) is the Hermitian conjugate of the reference circuit 524. Of the state output from the second reflection operation 53, the portion of the auxiliary bit 322 is input to the input transformation operation 541, and the portion of the computation quantum bit 321 is input to the reference circuit 544. Thereafter, the states output from the input transformation operation 541 and the reference circuit 544 are input to K unit gate operations 542. After the K unit gate operations 542 are operated, the output state is output from the second operational quantum circuit 54 via the output transformation operation 543. Here, only the unit gate operation 542 will be described, and the explanations of the input transformation operation 541, unit gate operation 542, and reference circuit 544 will be omitted as they are the same as those for the first operational quantum circuit 52.

[0072] The unit gate operation 542 of the second operational quantum circuit 54 is configured to be Hermitian conjugate with the unit gate operation 522 of the first operational quantum circuit 52. In this embodiment, the unit gate operation 542 is configured to be Hermitian conjugate with the unit gate operation 522 of the first operational quantum circuit 52. In this embodiment, the unit gate operation 542 is configured to be Hermitian conjugate with the forward real-time evolution operator U ＲＴＥ or the inverse real-time evolution operator U ＲＴＥ † It is configured so that either one of the above functions. ＲＴＥ is configured to match the reflected state of the reflection operation performed immediately before it. Here, the desired state of unit gate operation 542 is configured to match the second reflected state (|0> state) of second reflection operation 53. With this configuration, the computational quantum circuit 5 can be further simplified and the number of operations included in the computational quantum circuit 5 can be reduced.

[0073] The computational quantum circuit 5 may further include an observation operation 55. The observation operation 55 is configured to observe the state of each ancillary bit 322 that functions as a control bit for the unit gate operation 522. With this configuration, a final state in which time evolution has been appropriately performed by each time-evolution gate operation can be output as the computation result. The observation operation 55 is performed on the portion of the ancillary bit 322 among the states output from the second computational quantum circuit 54. As a result, the state of the ancillary bit 322 is projected onto the state observed by the observation operation 55, and the state of the computational quantum bit 321 is accordingly contracted to the state that would result if K operations were successful a predetermined number of times or more. Here, the number of ancillary bits 322 in which the second reflection state (|0> state) is observed indicates the number of times that the operation has acted on the input state |ψ>. For example, observing the |0> state for all K ancillary bits 322 means that all K operations have been performed on the input state |ψ>.

[0074] In this way, the state output from the computational quantum circuit 5 is a state in which an operation has been applied to the input state |ψ> in accordance with the observation result of the auxiliary bit 322. For convenience of explanation, the state of the n computational quantum bits 321 output from the computational quantum circuit 5 will be referred to as the final state below.

[0075] In summary, the computational quantum circuit 5 is configured to repeat an operation based on a Hamiltonian K times on an input state |ψ> represented by n computational quantum bits 321 (where K is an integer greater than or equal to 2), and is configured to act on the n computational quantum bits 321 and multiple auxiliary bits 322 according to K. Here, the states of the computational quantum bits 321 and the auxiliary bits 322 are configured to be representable using at least an observable first state and a second state. The computational quantum circuit 5 is configured to sequentially act on a first reflection operation 51, a first operational quantum circuit 52, a second reflection operation 53, and a second operational quantum circuit 54. The first reflection operation 51 is configured to act on the multiple auxiliary bits 322 so as to change the phase of a first reflection state, which is one of the first state components and the second state components included in each of the multiple auxiliary bits 322. The first operational quantum circuit 52 is configured to operate on n computation qubits 321 corresponding to the input state |ψ>, and includes unit gate operations 522 corresponding to each of the ancillary bits 322. Each of the unit gate operations 522 is configured to use one of a different plurality of ancillary bits 322 as a control bit, the computation qubit 321 as a target bit, and change the manner of operation on the computation qubit 321 according to the state of the ancillary bit 322. The second reflection operation is configured to operate on the computation qubit and the ancillary bit so as to change the phase of a second reflection state, which is one of the first state components and second state components included in each of the computation qubit and the ancillary bit. The second operational quantum circuit 54 is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

[0076] According to this configuration, quantum amplitude amplification can be performed with at least one different auxiliary bit 322 assigned to each step of time evolution, and therefore, it is possible to suppress an increase in the depth of the quantum circuit that accompanies an increase in the number of iterations, compared to when quantum amplitude amplification is performed using one auxiliary bit 322. Therefore, quantum acceleration can be promoted.

[0077] 3.4 Modifications of the Computational Quantum Circuit 5 The computational quantum circuit 5 described above is merely an example, and its specific form is not limited to that shown in FIG. 6 or the like.

[0078] The phase φ of the first reflection operation 51 and the second reflection operation 53 ２ｉ , φ ２ｉ＋１ is optional.

[0079] The first reflection state and the second reflection state are arbitrary as long as they can be associated by a unitary transformation or the like. In other words, the first operational quantum circuit 52 and the second operational quantum circuit 54 are not limited to being Hermitian conjugates to each other, and may include various arbitrary elements such as arbitrariness of the global topology and arbitrariness of the selection of the basis. In other words, the first operational quantum circuit 52 and the second operational quantum circuit 54 may be constructed to be Hermitian conjugates according to various arbitrary elements.

[0080] In the above embodiment, the unit gate operations 522 and 542 are implemented by using the stochastic operator V ＲＴＥ † and V ＲＴＥ However, it is not limited to this and any probabilistic operator or even a general operator can be used.

[0081] The construction method of the probabilistic operator is V ＲＴＥ In addition, different operation modes (e.g., U ＲＴＥ and forward operators such as U ＲＴＥ † ) to act on the computation qubit 321. ＲＴＥ 9 is a diagram showing a modified example of the V shown in FIG. ＲＴＥ , as shown in FIG. ＲＴＥ To distinguish it from V ＲＴＥ It is sometimes written as '. ＲＴＥ ' is a forward real-time evolution operator U ＲＴＥ is applied to the computation qubit 321. Then, V ＲＴＥWhen the auxiliary bit 322 is in the |0> state, no operation is performed (in other words, an identity operation is performed), and when the auxiliary bit 322 is in the |1> state, the inverse real-time evolution operator U ＲＴＥ † This causes the V shown in FIG. ＲＴＥ The same calculation can be performed.

[0082] 4. Information Processing Method This chapter describes the flow of information processing executed in the information processing system 1 based on the above-mentioned theory. The results of the processing in each step included in the information processing described below can be output in a manner that can be recognized by the user using the display unit 44 or the like, as appropriate. Note that the information processing may include any exception processing not shown. Exception processing includes the interruption of the information processing or the omission of each process. The selection or input performed in the information processing may be based on a user operation or may be performed automatically without relying on a user operation. FIG. 10 is a flowchart showing an overview of the information processing executed in the information processing system 1.

[0083] [Step S1] First, in step S1, the acquisition unit 231 executes an acquisition process to acquire information about the input state, information about the Hamiltonian H, and the number of iterations K of the calculation based on the Hamiltonian H. In this embodiment, K is an integer equal to or greater than 2. The information about the input state |ψ> includes, for example, information about the components of the system described by the Hamiltonian H. The components of the system include, for example, the particle species included in the system, the number of each particle species, the position resolution of each particle, etc.

[0084] [Step S2] Next, in step S2, the allocation unit 232 allocates the computational qubits 321 and auxiliary bits 322 to be used in the quantum computation based on the results obtained in step S1. For example, the allocation unit 232 calculates the number n of computational qubits 321 required to express the input state |ψ> based on information about the input state |ψ>, and allocates n computational qubits 321 from among the qubits 320 based on this number n. As a result, the input state |ψ> in this embodiment is expressed by n computational qubits 321. Also, for example, the allocation unit 232 allocates at least K auxiliary bits 322 from among the qubits 320 used in the operation of the computational quantum circuit 5, which will be described later, based on the number of iterations K. In this embodiment, the allocation unit 232 allocates K auxiliary bits 322.

[0085] [Step S3] Next, the process proceeds to step S3, where the processor 23 executes an initialization process and performs preprocessing for generating an input state |ψ> to be input to the computational quantum circuit 5, which will be described later.

[0086] First, the quantum operation unit 234 transmits to the quantum processor 33 a command to initialize the states of the allocated n computation quantum bits 321 and K auxiliary bits 322 to a predetermined initial state. Based on the command, the quantum processor 33 initializes the n computation quantum bits 321 and the K auxiliary bits 322. The initial state may be defined as, for example, a state in which the respective states of the n computation quantum bits 321 and the K auxiliary bits 322 both take the first state |0>, but is not limited to this and may be any state.

[0087] [Step S4] Next, in step S4, the generation unit 233 performs a generation process to generate a computational quantum circuit 5 based on the result acquired by the acquisition unit 231. The computational quantum circuit 5 of this embodiment is generated as an instruction to cause the quantum computer 3 to perform a quantum operation. Here, an example of the process for generating the computational quantum circuit 5 will be described.

[0088] First, the generating unit 233 is initialized (in this embodiment, |0> ＊（ｎ＋Ｋ） ) and the input state |ψ>, the reference circuit U ｒｅｆFor example, the generation unit 233 compares each component of the initialization state with the input state |ψ>, and generates the reference circuit U by combining unitary gate operations to perform an operation on each of the computation qubits 321 based on the phase difference and amplitude difference between these states. ｒｅｆ can be generated.

[0089] Furthermore, the generation unit 233 generates V that defines the unit gate operations 522 and 542 that act on the (n+K) quantum bit system based on the acquired Hamiltonian H. ＲＴＥ (For details, see U ＲＴＥ and its Hermitian conjugate U ＲＴＥ † The generating unit 233 generates the generated V ＲＴＥ , and sets a success state for each of the two types of unit gate operations 522, 542. This defines the unit gate operations 522, 542. The generation unit 233 sets the unit gate operations 522, 542 defined in this way, using each of the K auxiliary bits 322 as a control bit. Note that the input conversion operations 521, 541 and the output conversion operations 523, 543 may be preset, or may be parameters adjusted appropriately based on the obtained results. The generation unit 233 generates the first operational quantum circuit 52 using the input conversion operation 521, unit gate operation 522, output conversion operation 523, and reference circuit 524 defined in this way. Similarly, the generation unit 233 generates the second operational quantum circuit 54.

[0090] Next, the generation unit 233 generates a first reflection operation 51 so that the success state of the unit gate operation 522 corresponds to the first reflection state. The generation unit 233 also generates a second reflection operation 53 so that the success state of the unit gate operation 542 corresponds to the second reflection state. The generation unit 233 also generates an observation operation 55 so as to observe the state output from the second operational quantum circuit 54 for each of the K auxiliary bits 322.

[0091] The generation unit 233 generates a computational quantum circuit 5 as shown in FIG. 7 based on the first reflection operation 51, first operational quantum circuit 52, second reflection operation 53, second operational quantum circuit 54, and observation operation 55 generated in this manner. In other words, the information processing method includes a method for generating a computational quantum circuit 5. The generation method is a method for generating a computational quantum circuit 5. In the acquisition step, information on the input state |ψ>, information on the Hamiltonian, and the number of iterations K of an operation based on the Hamiltonian are acquired. The number of iterations K corresponds to K, which is the number of unit gate operations 522. In the allocation step, a plurality of auxiliary bits 322 corresponding to the number of iterations are allocated. In the generation step, a computational quantum circuit 5 configured to repeatedly perform an operation on a computational quantum bit 321 is generated based on the result acquired in the acquisition step. The method for generating a computational quantum circuit 5 is a method for generating a so-called program, which is an instruction code for causing the quantum processor 33 to execute a specified quantum operation.

[0092] [Step S5] Next, the process proceeds to step S5, where the quantum operation unit 234 causes the quantum processor 33 to execute a series of quantum operations based on the computational quantum circuit 5, etc. As a result, a series of quantum operations defined by the computational quantum circuit 5, etc. are executed on the assigned computational quantum bit 321 and auxiliary bit 322, causing the portion of the computational quantum bit 321 in the initialization state to transition to the input state |ψ>, and K operations are repeated while quantum amplitude amplification is performed. Thereafter, the final state output from the computational quantum circuit 5 is observed by the observation operation 55. At this time, the quantum operation unit 234 counts the number of successful states (|0> states) observed in the portion of the auxiliary bit 322, among the final states output from the computational quantum circuit 5.

[0093] [Step S6] The process then proceeds to step S7, where the processor 23 determines whether the observed state of the ancillary bit 322 satisfies a predetermined output condition. The output condition is a condition for determining whether to output the final state as a calculation result, and is defined, for example, by the degree of success of the repeated calculations performed on the calculation quantum bit 321. For example, the output condition is configured to be satisfied when the number of observed successful states is equal to or greater than a predetermined value. The predetermined value is set appropriately depending on, for example, the required calculation accuracy, calculation time, etc., and is up to K (when successful states are observed in all ancillary bits 322). The successful state may correspond to the desired state (|0> state) in the second calculation quantum circuit 54, i.e., the second reflection state. Correspondence of a state to another state means, for example, that they can be mutually converted by unitary operations, etc.

[0094] [Step S7] If the determination result in step S6 is positive, i.e., if it is determined that the output condition is satisfied, the process proceeds to step S7, and the states (final states) of the n computation qubits 321 after observation by the observation operation 55 are output as the computation result. In other words, the output unit 235 outputs the states of the computation qubits 321 as the computation result based on the observation result of the ancillary bits 322 (after the second operational quantum circuit 54 has been operated on).

[0095] Thereafter, the information processing system 1 terminates this information processing. The output calculation result may be used in any manner. For example, the calculation result may be used to identify the final state through an observation operation, or may be used as an input state to another quantum circuit. Furthermore, information regarding the calculation result (such as the observation result of the calculation qubit 321) may be stored in the storage unit 22 or the like as appropriate.

[0096] [Step S8] On the other hand, if the determination result in step S6 is negative, that is, if it is determined that the output condition is not satisfied, the process proceeds to step S8, where the processor 23 discards the final state.

[0097] [Step S9] The processor 23 then determines whether or not to perform recalculation. Whether or not to perform recalculation can be determined appropriately based on, for example, the time available for calculation, the upper limit of the number of calculations, etc. If it is determined that recalculation is not necessary, the information processing system 1 ends this information processing.

[0098] [Step S10] On the other hand, if the determination result in step S10 is positive, the quantum operation unit 234 initializes the computational quantum bit 321 and the auxiliary bit 322. Thereafter, the process returns to step S6, and the quantum operation unit 234 causes the quantum processor 33 to again perform quantum operations based on the computational quantum circuit 5, etc. In this way, the information processing system 1 generates and stores computation results based on the computational quantum circuit 5, and performs various quantum computations.

[0099] According to the information processing described above, quantum amplitude amplification can be performed with at least one different auxiliary bit 322 assigned to each step of time evolution, and therefore, an increase in the depth of the quantum circuit with an increase in the number of iterations can be suppressed compared to when quantum amplitude amplification is performed using one auxiliary bit 322. Therefore, quantum acceleration can be promoted.

[0100] 5. Simulation Results Based on the Computational Quantum Circuit 5 This section describes the results of a simulation of the above-described computational quantum circuit 5. Note that the simulation was performed using Qiskit on a classical computer.

[0101] In this simulation, the following Hamiltonian of the Heisenberg spin model was used as the Hamiltonian H:

[0102] where σ ｊ = (σ ｊ ｘ , σ ｊ ｙ , σ ｊ ｚ) is an operator that represents three-dimensional spin. j, k are indices that indicate the site number where the spin is located. <j, k> indicates the combination of the nearest sites on a closed one-dimensional chain. A spin system is formed. h ｊ denotes the uniform magnetic field strength at the j-th site. The magnetic field has a strength h ｊ was randomly selected from a uniform distribution ranging from -1 to 1. The CRTE gate is implemented by performing a fourth-order Trotter decomposition on the even-odd group of the Hamiltonian H. Multi-step PITE (a method of repeatedly executing the PITE method) was adopted as a probabilistic algorithm to generate the ground state of the Hamiltonian H. The PITE method introduces a constant energy shift to improve the overall success probability, and employs scheduling of the size of the imaginary time step Δτ. For details of the scheduling, please refer to Non-Patent Document 1.

[0103] In this simulation, the inventors performed simulations using three methods to generate the ground state of the Hamiltonian H: a method of repeatedly applying the single-step PITE method, a method using quantum phase estimation (QPE), and the present information processing method. Simulations were performed using these three methods, and the performance of these methods was evaluated. The present information processing method is a calculation method based on a quantum computing algorithm that combines the multi-step PITE method with quantum amplitude amplification, and is denoted as "PITE+QAA" in FIG. 11 . Hereinafter, for convenience of explanation, in the explanation of the results of this simulation, the method of repeatedly applying the single-step PITE method will be referred to as "PITE," the method using quantum phase estimation will be referred to as QPE, and the present information processing method will be referred to as "PITE+QAA."

[0104] FIG. 11 shows the computational cost and infidelity δ for each method for generating the ground state of Hamiltonian H. Ｋ As described above, the infidelity δ Ｋ = (1-F Ｋ ) For convenience of explanation, infidelity δ Ｋ is simply denoted as δ.

[0105] This simulation was performed using a one-dimensional Heisenberg model with eight spins. Each eigenstate |λ of the Hamiltonian H ｉ The inventors used a state in which the N eigenstates {|λ ｉ >} coefficient {c ｉ} is |c ｉ | ２ = 1 / N. For each method, as the number of steps (K) of PITE, the number of digits (the number K of auxiliary bits 322 in multi-step PITE), the resolution of the QPE, and the like increase, the infidelity δ decreases and the computational cost increases. As the infidelity δ decreases, the probability of success of the operation decreases and tends to approach 1 / N. Therefore, the increase in computational cost corresponds to the increase in the number of iterations K of the stochastic operation in PITE and the resolution of the QPE. As shown in FIG. 11 , in all methods, a tendency was confirmed where the infidelity δ decreases as the computational cost (i.e., the number of iterations K, etc.) increases. On the other hand, when the infidelity δ is about 10 －７ The computational cost when reaching １０ In contrast, PITE is 10 ６ ~10 ７ and 10 for PITE+QAA. ６ This result suggests that PITE can reduce infidelity δ at a lower computational cost than QPE. Furthermore, this result suggests that PITE + QAA can reduce errors at a lower computational cost than PITE. Therefore, in terms of computational cost and the rate of infidelity reduction, the usefulness of PITE as a probabilistic operation and the usefulness of this information processing method incorporating QAA into PITE are demonstrated.

[0106] FIG. 12 shows the weights |c １ | －１10 is a diagram showing the simulation results of the relationship between the infidelity δ and the calculation cost. Ｋ is 10 －４ The probability of the input state |ψ> is weighted using a Gaussian distribution of the eigenstate function whose average value is the ground state energy. １ | －１ As |c> increases, the computational cost tends to increase. This indicates that the smaller the component of the ground state contained in the input state |ψ>, the more difficult it is to generate the ground state. As shown in Figure 12, the computational cost of PITE and PITE+QAA increases with increasing |c １ | －１ This suggests that the probabilistic algorithm PITE is effective for QPE. １ | －１ < 1 / 2, the computational cost of PITE was smaller than that of PITE + QAA, but |c １ | －１ The computational cost of PITE+QAA is lower than that of PITE for |ψ>1 / 2. This suggests that this information processing (PITE+QAA) is more useful than PITE, especially when the desired state (here, the ground state) is difficult to observe in the input state |ψ>.

[0107] The above simulation results demonstrate the usefulness of this information processing method.

[0108] 6. Appendix Overview of the Stochastic Field Imaginary Time Evolution Method This section provides an overview of the stochastic imaginary time evolution method (PITE) used in the above information processing. Note that although the symbols of operators differ from those in the above information processing, they can be appropriately related. Figure 13 shows a quantum circuit that implements the time evolution operator exp(LΔt) with a general operator L as a generator. Figure 14 shows a quantum circuit that implements the imaginary time evolution operator exp(-HΔτ) with a general Hermitian operator H as a generator.

[0109] 6.1 Quantum Circuit for a Time Evolution Operator with a General Operator as a Generator When a general operator L for an n-qubit system consisting of n computation qubits 321 is given, consider configuring a quantum circuit that implements a time evolution operator exp(LΔt) with this as a generator. For convenience of explanation, the n-qubit system consisting of n computation qubits 321 will be simply referred to as an n-qubit system, and the overall state of the n-qubit system consisting of n computation qubits 321 may be referred to as an n-qubit state. Δt is a small real number representing a time step. If the time evolution operator exp(LΔt) can be configured as a quantum circuit, it is possible to execute the time evolution operator exp(LNΔt) for any natural number N by repeating this.

[0110] A non-unitary Hermitian operator M from a real constant m0 ​​is defined as in Expression 18. Also, a non-Hermitian unitary operator U is defined as in Expression 19.

[0111] Furthermore, the Hermitian operator Θ for an n-qubit system is defined as follows:

[0112] When κ and d0 are defined as in Equations 21 and 22, respectively, θ0 is defined as in Equation 23 using these.

[0113] The quantum circuit shown in Fig. 13 is defined as a quantum circuit for n+2 quantum bits. The gate W included in this is a single quantum bit transformation defined by equation 24. Ry in Fig. 13 is a y-rotation gate.

[0114] 13, the overall state changes within a first order range of Δt as shown in Expression 25 until just before measurement. As can be seen from the right-hand side of the expression, if two ancillary bits 322 are measured and the |0>*|0> state, which is the state of the two ancillary bits 322, is obtained, then immediately thereafter the n-qubit state consisting of computation qubit 321 will become the desired state exp(LΔt)|ψ>, apart from a physically insignificant constant factor.

[0115] This means that the operator exp(LΔt) for n qubits can be probabilistically implemented using quantum circuit QC1. Furthermore, because the operators exp(iκΘ) and exp(-iκΘ) for n qubits are unitary operators, they can be implemented as unitary gates for n+2 qubits by combining ancillary bits 322.

[0116] In other words, this information processing method includes the following steps: In the conversion step, an operator for n quantum bits is converted into a unitary gate using less than (n / 2) auxiliary bits. The unitary gate is a form in which the operator can be directly implemented. In the circuit generation step, a quantum circuit that functions as a desired time evolution operator when the auxiliary bits are observed as a predetermined state is generated based on the unitary gate. According to this aspect, the number of exponential measurements of the quantum bits can be further reduced.

[0117] 6.2 Quantum Circuit for Imaginary Time Evolution Operator with General Hermitian Operator as Generator Regarding the quantum circuit shown in Fig. 13, as a special case, when L is a Hermitian operator, a desired operation can be implemented with a smaller number of auxiliary bits. Here, in order to explicitly indicate that the operator L is Hermitian, the Hermitian operator H will be used hereinafter instead of L. Furthermore, examples of Hermitian operators include an electron Hamiltonian and an Ising Hamiltonian, but these are merely examples and are not limited to these.

[0118] Suppose a Hermitian operator H for an n-qubit system is given. Consider this and the imaginary time evolution operator exp(-HΔτ) specified by a real number Δτ. From this and a real constant m0, a non-unitary Hermitian operator M is defined as shown in Equation 26.

[0119] Also, the Hermitian operator Θ for an n-qubit system is defined as in Equation 27.

[0120] Consider constructing a quantum circuit that obtains M|ψ> when given any n-qubit state |ψ>. To implement operator M, consider the quantum circuit shown in Figure 14 as a quantum circuit for n+1 qubits.

[0121] 14, when an n+1 qubit state consisting of an arbitrary n-qubit state |ψ> consisting of n computation qubits 321 and an ancillary bit 322 in the |0> state is input, the overall state changes as shown in Equation 28 just before measurement. As can be seen from the right-hand side of the equation, if the |0> state is obtained by measuring the ancillary bit 322 and performing the observation operation, then immediately thereafter the n-qubit state becomes the desired state M|ψ> (apart from a physically insignificant constant factor).

[0122] This means that the imaginary time evolution operator M for n quantum bits can be implemented probabilistically by using the quantum circuit shown in Fig. 14. In addition, since the operators exp(iκΘ) and exp(-iκΘ) for n quantum bits are unitary operators (more specifically, real time evolution operators), they can be implemented as a unitary gate for n+1 quantum bits by combining ancillary bits 322.

[0123] In other words, preferably, in the conversion step, the conversion unit converts the operator into a format that uses only a time evolution operator and other unitary operators. The time evolution operator includes a Hermitian operator. In particular, in the conversion step, the conversion unit converts the operator into a format that uses only a real time evolution operator and other unitary operators. The real time evolution operator includes a unitary operator. Furthermore, the time evolution operator is configured to be able to be generated by a Hermitian operator H. Note that the format of the time evolution operator is not limited to this and is arbitrary. For example, the format of the time evolution operator may be a format in which the operator appears in the expression, or a format in which the operator belongs as an element of a set.

[0124] 6.3 Equivalent transformation of quantum circuits when Hermitian operators are used as generators Since exp(iκΘ) and exp(-iκΘ) included in the quantum circuit shown in Figure 14 are unitary operators, they can in principle be implemented as unitary gates. However, it is not obvious how to implement the definition of Θ in Equation 27 as a unitary gate as is. Therefore, if the quantum circuit shown in Figure 13 can be approximated by another circuit that performs the same calculation (transformed into a circuit that is strictly equivalent within a finite-order range of mathematical expansion), that circuit would be useful for practical quantum computing. The equivalent transformation is explained below.

[0125] s １ is defined as in Equation 29. Using this, the unitary operator U ＲＴＥ is defined as in Equation 30.

[0126] When an N+1 quantum bit state consisting of n computation quantum bits 321 taking any n-qubit state |ψ> and one auxiliary bit 322 in the |0> state is input to the quantum circuit shown in Figure 14, the overall state changes as shown in Equation 31 within a first order range of Δτ by the time of measurement. The state after this change coincides with the state in Equation 28 within a first order range of Δτ. This means that the quantum circuit QC1 shown in Figure 6 is equivalent to the quantum circuit shown in Figure 14 within a first order range of Δτ.

[0127] exp(is １ HΔτ) and exp(-is １ HΔτ) is a unitary real-time evolution operator, and various methods have already been proposed to efficiently implement it as a quantum gate. Therefore, these existing methods can be used as is for this method.

[0128] By implementing the imaginary time evolution operator as a quantum circuit and repeating it, the time evolution operator exp(LNΔt) can be executed for a desired natural number N. Here, to correctly calculate each imaginary time step, the auxiliary bit 322 must output the |0> state. By amplifying the amplitude (probability) that the auxiliary bit 322 takes the |0> state at each imaginary time evolution step, the time evolution operator exp(LΔt) can be executed with higher probability.

[0129] One method for amplifying the amplitude when the ancillary bit 322 is in the |0> state is to insert a quantum amplitude amplifier circuit. That is, preferably, the quantum circuit may further include a quantum amplitude amplifier circuit that can improve the probability that the ancillary bit is observed in a predetermined state. For a general operator L, the operator exp(LNΔt) can be implemented on a quantum computer, and a quantum circuit that applies the operator exp(LNΔt) to an arbitrary initial state can be realized.

[0130] However, in the case of a general operator L, the lowest eigenvalue does not necessarily have to be a real number; it is only guaranteed that the eigenvalue will be a real number if the operator L is a Hermitian operator. If the operator L is a regular non-Hermitian operator, when the imaginary time evolution operator exp(LNΔt) is applied to an arbitrary initial state with a sufficiently large number N, it will converge to an eigenstate corresponding to the eigenvalue of L with the smallest real part. However, it should be noted that a quantum circuit representing the operator exp(LNΔt) can be realized even if L is not regular.

[0131] Based on this theory, the forward real-time evolution operator U ＲＴＥ is defined and the PITE method is implemented.

[0132] 7. Others The information processing system 1 may be further improved in the following manner.

[0133] The stochastic operation is the cosine function operator cos(t ｋ H). FIG. 15 shows the cosine function operator cos(t ｋ Quantum circuit QC2 is an example of a quantum circuit QC2 corresponding to (H). Quantum circuit QC2 is configured to first perform a Hadamard gate operation on auxiliary bit 322. Next, quantum circuit QC2 is configured to perform a CRTE gate operation with auxiliary bit 322 as the control bit and computation qubit 321 as the target bit. This CRTE gate operation does not perform an operation on computation qubit 321 (in other words, performs an identity operation) when auxiliary bit 322 is in the |0> state, and performs a forward real-time evolution operator U ＲＴＥ The parameter corresponding to the size of the real time step of the CRTE gate is arbitrary, but for example, 2t ｋ Then, the quantum circuit QC2 is configured to perform a phase gate operation on the auxiliary bit 322. The phase gate operation is an operation for rotating the phase of the auxiliary bit 322. The phase rotation angle is arbitrary, but for example, when an energy shift of a shift amount E is used, the phase rotation angle is 2Et ｋ is.

[0134] FIG. 16 shows the cosine function operator cos(t ｋ16 is a diagram showing an example of a computational quantum circuit when the computational quantum circuit 5a employs a Hadamard gate operation H and a phase gate operation P. Hereinafter, for convenience of explanation, the computational quantum circuit 5 shown in FIG. 16 will be referred to as a computational quantum circuit 5a to distinguish it from the computational quantum circuit 5 shown in FIG. 7. The computational quantum circuit 5a differs from the computational quantum circuit 5 in the specific aspects of the first operational quantum circuit 52 and the second operational quantum circuit 54, but has in common the first reflection operation 51, the second reflection operation 53, and the observation operation 55. Hereinafter, for convenience of explanation, the same component numbers will be used to designate components common to the computational quantum circuit 5 and the computational quantum circuit 5a, and descriptions thereof will be omitted, and components different between the computational quantum circuit 5 and the computational quantum circuit 5a will be designated by adding "a" to the end of each component number of the computational quantum circuit 5. The input transformation operation 521a of the first operational quantum circuit 52a is a Hermitian conjugate operation P of the Hadamard gate operation H and the phase gate operation P. † The unit gate operation 522a is composed of one CRTE gate operation, and when the corresponding ancillary bit 322 is in the |0> state, no operation is performed on the computation quantum bit 321, and when the corresponding ancillary bit 322 is in the |1> state, the Hermitian conjugate operator U ＲＴＥ † on the computation quantum bit 321. The output transformation operation 523a is constituted by a Hadamard gate operation H. The second operational quantum circuit 54a is configured to be the Hermitian conjugate of the first operational quantum circuit 52a. Specifically, the input transformation operation 541a, the unit gate operation 542a, and the output transformation operation 543a are configured to be the Hermitian conjugate of the output transformation operation 543a, the Hermitian conjugate of the unit gate operation 522a, and the Hermitian conjugate of the input transformation operation 541a, respectively. Therefore, the operations repeatedly performed by the computation quantum circuit 5 are not limited to stochastic imaginary time operations.

[0135] In the above information processing, the allocating unit 232 allocates K auxiliary bits 322 when repeating the operation K times, but it may allocate more than K auxiliary bits 322. For example, the allocating unit 232 may allocate two or more auxiliary bits 322 per operation. This allows for more diverse operations to be realized by using auxiliary bits 322 that can express more diverse states as control bits, etc. Furthermore, the allocating unit 232 may set the number of repetitions K to a number greater than or equal to two, for example, K １ and K. ２ and multiple iterations K １ , K ２ and by serially combining these computational quantum circuits 5, a quantum circuit that repeats an operation K times as a whole may be generated as a computational quantum circuit. In this case, the allocation unit 232 may allocate less than K, for example, １ and K. ２ In this case, for example, the quantum operation unit 234 may allocate the auxiliary bits 322 when the number of iterations is K １ After executing the quantum operation based on the computation quantum circuit corresponding to ２ and a quantum operation based on a computational quantum circuit corresponding to the input state, the operation may be repeated K times overall for the initial input state to obtain a final state. Therefore, when the number of repetitions K is divided into multiple numbers, quantum circuits based on the divided numbers are also included in the computational quantum circuit 5 related to this information processing.

[0136] The computational quantum circuit 5 does not need to have a function related to so-called quantum amplitude amplification. The function related to quantum amplitude amplification can be realized, for example, by a first reflection operation 51, a first operational quantum circuit 52, and a second reflection operation 53. In this case, the generation unit 233 may generate a computational quantum circuit 5 including the second operational quantum circuit 54 as an operational quantum circuit according to the number of iterations K of an operation based on the Hamiltonian H. In other words, the information processing method may include the following steps. In the acquisition step, information on the input state |ψ> represented by n computational qubits 321, information on the Hamiltonian, and the number of iterations K (where K is an integer equal to or greater than 2) of an operation based on the Hamiltonian are acquired. In the allocation step, multiple auxiliary bits 322 are assigned according to the number of iterations K. In the generation step, the computational quantum circuit 5 is generated based on the results acquired in the acquisition step. The computational quantum circuit 5 is configured to operate the operational quantum circuit on the computational qubits 321 and the auxiliary bits 322. The operational quantum circuit is configured to act on n computation qubits 321 corresponding to the input state |ψ>, and includes unit gate operations corresponding to each of the assigned auxiliary bits 322. Each unit gate operation is configured to use one of a plurality of different auxiliary bits 322 as a control bit, the computation qubit 321 as a target bit, and change the mode of action on the computation qubit 321 according to the state of the auxiliary bit 322. In the output step, the state of the computation qubit 321 is output as the computation result based on the observation result of the auxiliary bit 322.

[0137] Furthermore, the generation unit 233 may generate the computational quantum circuit 5 further including an observation operation 55. In this case, for example, the computational quantum circuit 5 is configured to apply the operational quantum circuit to the computational quantum bit 321 and the auxiliary bit 322, and then perform an observation operation 55 on at least one of the multiple auxiliary bits 322. The observation operation 55 is configured to observe the state of the auxiliary bit 322 that functions as a control bit for the unit gate operation.

[0138] The information processing system 1 may be realized by a program that causes a computer to function as the information processing system 1. This program may be downloadable from a server, may be executed or distributed on a cloud computer, or may be stored in a non-volatile or volatile storage medium and distributed.

[0139] The processor 23 does not need to actually execute the quantum computation by the computational quantum circuit 5 using the quantum computer 3. For example, the processor 23 may convert the quantum computation algorithm defined by the generated computational quantum circuit 5 into a computational algorithm executable by a classical computer, and then cause the classical computer to execute the computational algorithm. For example, the processor 23 may convert the quantum operation expressed by the computational quantum circuit 5 into a computational algorithm executable by a classical computer by replacing it with a matrix computation problem.

[0140] A part of the processing of the processor 23 may be converted into a calculation algorithm that can be executed by a quantum computer, and then the quantum computer 3 may be made to execute the calculation algorithm.

[0141] The quantum computer 3 may function as a quantum measurement device. Each of the above information processing methods may independently constitute a technical concept. For example, the method may be used to perform any information processing that can be processed using a quantum algorithm, such as processing other than processing for obtaining calculation results related to physical phenomena, such as calculation results for combinatorial optimization problems or traveling salesman problems. In other words, the above information processing method is applicable to any problem mathematically described as a Hamiltonian (e.g., an eigenvalue problem of a Hamiltonian).

[0142] A part of the processing of the processor 23 may be converted into a calculation algorithm that can be executed by a quantum computer, and then the quantum computer 3 may be made to execute the calculation algorithm.

[0143] The quantum computer 3 may function as a quantum measurement device. For example, in this case, the computational quantum circuit 5 may be used as a unitary operation for generating an initial state. In other words, the computational quantum circuit 5 may be configured to represent a quantum algorithm executed by at least one quantum measurement device. With such a configuration, for example, when the quantum measurement device is configured to use a specific state (e.g., a ground state) of a Hamiltonian as a probe state of quantum measurement, the computational quantum circuit 5 may be configured to repeatedly perform operations based on a Hamiltonian H such that the specific state is an eigenstate, thereby outputting the specific state based on the input state |ψ>. With such a configuration, measurements that are more robust against quantum measurement noise can be performed.

[0144] The information processing device 2 may be a classical computer, a quantum computer, or a combination thereof.

[0145] The information processing system 1 can be applied to various information processes related to quantum computation, such as quantum measurement and quantum communication.

[0146] The above-described embodiment is not limited to the information processing system 1, and may be an information processing method or an information processing program. The information processing method includes each step of the information processing system 1. The information processing program causes at least one computer to execute each step of the information processing system 1.

[0147] The information processing system 1 and the like may be provided in the following aspects.

[0148] (1) An information processing method, comprising the following steps: in an acquisition step, information on an input state represented by n computational quantum bits, information on a Hamiltonian, and a number K of iterations of an operation based on the Hamiltonian (where K is an integer equal to or greater than 2), are acquired; in an allocation step, a plurality of auxiliary bits are allocated according to the number K of iterations, wherein the states of the n computational quantum bits and the plurality of auxiliary bits are configured to be representable using at least a first state and a second state that are observable; in a generation step, a computational quantum circuit is generated based on a result acquired in the acquisition step, wherein the computational quantum circuit is configured to sequentially apply a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit, wherein the first reflection operation is a first reflection state that is one of a component of the first state and a component of the second state included in each of the plurality of auxiliary bits. the first operational quantum circuit is configured to operate on the n computation qubits corresponding to the input state and includes a unit gate operation corresponding to each of the ancillary bits, each of the unit gate operations having one of the plurality of ancillary bits as a control bit and the computation qubit as a target bit, and being configured to change a mode of operation on the computation qubit according to the state of the ancillary bit; the second reflection operation is configured to operate on the computation qubit and the ancillary bit so as to change a phase of a second reflection state which is one of the first state component and the second state component contained in each of the computation qubit and the ancillary bit; and the second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

[0149] According to this configuration, quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each step of time evolution, so that the increase in the depth of the quantum circuit with an increase in the number of repetitions can be suppressed compared to when an operation and quantum amplitude amplification are repeatedly performed using one auxiliary bit, thereby facilitating quantum acceleration.

[0150] (2) In the information processing method described in (1) above, the computational quantum circuit includes a reference circuit configured to act on the computational quantum bit, and the reference circuit is configured to output the input state based on an initialized state of the computational quantum bit.

[0151] According to this configuration, by setting an appropriate input state for the Hamiltonian in advance, it is possible to obtain highly accurate calculation results with a smaller number of operations.

[0152] (3) In the information processing method described in (1) or (2) above, the computational quantum circuit further includes an observation operation, and the observation operation is configured to observe the state of each of the auxiliary bits that function as control bits of the unit gate operation, and further, in the output step, the state of the computational quantum bit is output as the calculation result based on the observation result of the auxiliary bit.

[0153] According to this configuration, a final state in which time evolution has been appropriately performed by operating each time evolution gate can be output as a calculation result.

[0154] (4) In the information processing method according to any one of (1) to (3) above, the state of the ancillary bit included in the first reflection state and the state of the ancillary bit included in the second reflection state are a common state, and the second operational quantum circuit is configured to be Hermitian conjugate with the first operational quantum circuit.

[0155] With this configuration, the computational quantum circuit can be further simplified, and the number of operations included in the computational quantum circuit can be reduced.

[0156] (5) In the information processing method according to any one of (1) to (4) above, the phase of the first reflection operation is inverted relative to the phase of the second reflection operation.

[0157] With this configuration, phase matching can be achieved, thereby further promoting quantum acceleration.

[0158] (6) An information processing method according to any one of (1) to (5) above, wherein the operation is a probabilistic operation that can express whether or not the operation will be successful depending on the state of the auxiliary bit.

[0159] (7) In the information processing method described in any one of (1) to (6) above, each of the unit gate operations is configured to apply either a unit operation or an operation that is a Hermitian conjugate of the unit operation to the computation quantum bit depending on the state of the auxiliary bit, and the unit operation is configured to correspond to performing the operation once.

[0160] (8) An information processing method, comprising the following steps: in the acquisition step, information on an input state represented by n computational quantum bits, information on a Hamiltonian, and a number of iterations K (where K is an integer equal to or greater than 2) of an operation based on the Hamiltonian are acquired; in the allocation step, a plurality of auxiliary bits are assigned according to the number of iterations K; in the generation step, a computational quantum circuit is generated based on the results acquired in the acquisition step, the computational quantum circuit is configured to operate an operational quantum circuit on the computational quantum bits and the auxiliary bits; the operational quantum circuit is configured to operate on the n computational quantum bits corresponding to the input state and includes unit gate operations corresponding to each of the assigned auxiliary bits, each of the unit gate operations having one of the plurality of different auxiliary bits as a control bit, having the computational quantum bit as a target bit, and being configured to change a mode of operation on the computational quantum bit according to a state of the auxiliary bit; and in the output step, the state of the computational quantum bit is output as a computation result based on a result of observation of the auxiliary bit.

[0161] (9) In the information processing method described in (8) above, the computational quantum circuit is configured to, after applying the operational quantum circuit to the computational quantum bit and the auxiliary bit, further perform an observation operation on at least one of the plurality of auxiliary bits, and the observation operation is configured to observe the state of the auxiliary bit that functions as a control bit for the unit gate operation.

[0162] (10) A computational quantum circuit configured to repeat an operation based on a Hamiltonian K times on an input state represented by n computational quantum bits (where K is an integer equal to or greater than 2), and configured to act on the n computational quantum bits and a plurality of auxiliary bits according to K, wherein the states of the computational quantum bits and the auxiliary bits are configured to be representable using at least a first state and a second state that are observable, and the computational quantum circuit is configured to sequentially act on a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit, and the first reflection operation is configured to act on the plurality of auxiliary bits so as to change the phase of a first reflection state, which is one of the components of the first state and the components of the second state included in each of the plurality of auxiliary bits. the first operational quantum circuit is configured to operate on the n computation qubits corresponding to the input state and includes a unit gate operation corresponding to each of the ancillary bits, each of the unit gate operations having one of the plurality of different ancillary bits as a control bit and the computation qubit as a target bit, and being configured to change a mode of operation on the computation qubit according to a state of the ancillary bit; the second reflection operation is configured to operate on the computation qubit and the ancillary bit so as to change a phase of a second reflection state which is one of the components of the first state and the components of the second state contained in each of the computation qubit and the ancillary bit; and the second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

[0163] According to this configuration, quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each time step, so that the increase in the depth of the quantum circuit with an increase in the number of iterations can be suppressed compared to when quantum amplitude amplification is performed using one auxiliary bit, thereby facilitating quantum acceleration.

[0164] (11) A method for generating a computational quantum circuit according to (10) above, wherein in the acquisition step, information on the input state, information on the Hamiltonian, and the number of iterations of an operation based on the Hamiltonian are acquired, where the number of iterations corresponds to K, which is the number of unit gate operations; in the allocation step, the plurality of auxiliary bits corresponding to the number of iterations are allocated; and in the generation step, a computational quantum circuit configured to repeatedly perform the operation on the computational quantum bits is generated based on the results acquired in the acquisition step.

[0165] According to this configuration, quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each time step, so that the increase in the depth of the quantum circuit with an increase in the number of iterations can be suppressed compared to when quantum amplitude amplification is performed using one auxiliary bit, thereby facilitating quantum acceleration.

[0166] (12) An information processing system consisting of at least one device, the information processing system having at least one processor capable of executing a program to perform each step of the information processing method described in any one of (1) to (9) above.

[0167] According to this configuration, quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each time step, so that the increase in the depth of the quantum circuit with an increase in the number of iterations can be suppressed compared to when quantum amplitude amplification is performed using one auxiliary bit, thereby facilitating quantum acceleration.

[0168] (13) A program that causes at least one computer to execute each step of the information processing method described in any one of (1) to (9) above.

[0169] According to this configuration, quantum amplitude amplification can be performed with at least one different auxiliary bit assigned to each time step, so that the increase in the depth of the quantum circuit with an increase in the number of iterations can be suppressed compared to when quantum amplitude amplification is performed using one auxiliary bit. Therefore, quantum acceleration can be promoted. Of course, this is not limited to this.

[0170] Finally, while various embodiments of the present invention have been described, they are presented by way of example only and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents.

[0171] 1: Information processing system 2: Information processing device 20: Communication bus 21: Communication unit 22: Storage unit 23: Processor 231: Acquisition unit 232: Allocation unit 233: Generation unit 234: Quantum operation unit 235: Output unit 3: Quantum computer 30: Communication bus 31: Communication unit 32: Quantum memory 320: Quantum bit 321: Computational quantum bit 322: Auxiliary bit 33: Quantum processor 4: User terminal 40: Communication bus 41: Communication unit 42: Memory 43: Processor 44: Display unit 45: Input unit 5: Computational quantum circuit 51: First reflection operation 52: First operational quantum circuit 521: Input conversion operation 522: Unit gate operation 523: Output conversion operation 524 : Reference circuit 53 : Second reflection operation 54 : Second operational quantum circuit 541 : Input conversion operation 542 : Unit gate operation 543 : Output conversion operation 544 : Reference circuit 55 : Observation operation 5a : Computational quantum circuit 52a : First operational quantum circuit 521a : Input conversion operation 522a : Unit gate operation 523a : Output conversion operation 54a : Second operational quantum circuit 541a : Input conversion operation 542a : Unit gate operation 543a : Output conversion operation QC1 : Quantum circuit QC2 : Quantum circuit P : Phase gate operation R Ｚ : z rotating gate operation S ０ : Zero reflection S χ : Oracle operation

Claims

1. An information processing method comprising the following steps: in an acquisition step, information on an input state represented by n computational quantum bits, information on a Hamiltonian, and a number K of iterations of an operation based on the Hamiltonian (wherein K is an integer equal to or greater than 2); in an allocation step, a number of auxiliary bits are allocated according to the number K of iterations, wherein the states of the n computational quantum bits and the plurality of auxiliary bits are configured to be representable using at least a first state and a second state that are observable; in a generation step, a computational quantum circuit is generated based on a result acquired in the acquisition step, wherein the computational quantum circuit is configured to sequentially apply a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit, and the first reflection operation is configured to act on the plurality of auxiliary bits so as to change the phase of a first reflection state, which is one of the components of the first state and the components of the second state included in each of the plurality of auxiliary bits; an ancillary bit; and a control bit for each of the plurality of ancillary bits, the control bit being a first component of the computation quantum bit and a target bit for each of the plurality of ancillary bits. The method of this invention relates to an information processing method, and further relates to a computation quantum bit and an ancillary bit. The computation quantum bit and an ancillary bit are configured to operate on the computation quantum bit and the ancillary bit so as to change a phase of a second reflection state, the second reflection state being one of the components of the first state and the components of the second state contained in each of the computation quantum bit and the ancillary bit.

2. An information processing method according to claim 1, wherein the computational quantum circuit includes a reference circuit configured to act on the computational quantum bit, and the reference circuit is configured to output the input state based on an initialized state of the computational quantum bit.

3. An information processing method according to claim 1 or 2, wherein the computational quantum circuit further includes an observation operation, the observation operation being configured to observe the states of the auxiliary bits functioning as control bits for the unit gate operation, and further wherein, in an output step, the states of the computational quantum bits are output as the computation result based on the observation results of the auxiliary bits.

4. An information processing method according to any one of claims 1 to 3, wherein the state of the ancillary bit included in the first reflection state and the state of the ancillary bit included in the second reflection state are a common state, and the second operational quantum circuit is configured to be Hermitian conjugate with the first operational quantum circuit.

5. An information processing method according to any one of claims 1 to 4, wherein the phase of the first reflection operation is inverted with respect to the phase of the second reflection operation.

6. An information processing method according to any one of claims 1 to 5, wherein the calculation is a probabilistic calculation capable of expressing whether or not the calculation will be successful depending on the state of the auxiliary bit.

7. An information processing method according to any one of claims 1 to 6, wherein each of the unit gate operations is configured to apply either a unit operation or an operation that is a Hermitian conjugate of the unit operation to the computation quantum bit depending on the state of the auxiliary bit, and the unit operation is configured to correspond to performing the operation once.

8. An information processing method comprising the following steps: in an acquisition step, information on an input state represented by n computational quantum bits, information on a Hamiltonian, and a number of iterations K (where K is an integer equal to or greater than 2) of an operation based on the Hamiltonian are acquired; in an allocation step, a number of auxiliary bits are assigned according to the number of iterations K; in a generation step, a computational quantum circuit is generated based on a result acquired in the acquisition step, the computational quantum circuit is configured to operate on the computational quantum bits and the auxiliary bits, the computational quantum circuit is configured to operate on the n computational quantum bits corresponding to the input state and includes unit gate operations corresponding to each of the assigned auxiliary bits, each of the unit gate operations being configured to use one of the multiple different auxiliary bits as a control bit, use the computational quantum bit as a target bit, and change the mode of operation on the computational quantum bit depending on the state of the auxiliary bit; and in an output step, the state of the computational quantum bit is output as a computation result based on the observation result of the auxiliary bit.

9. An information processing method according to claim 8, wherein the computational quantum circuit is configured to, after applying the operational quantum circuit to the computational quantum bit and the auxiliary bit, further perform an observation operation on at least one of the plurality of auxiliary bits, and the observation operation is configured to observe the state of the auxiliary bit that functions as a control bit for the unit gate operation.

10. A computational quantum circuit configured to repeat an operation based on a Hamiltonian K times for an input state represented by n computational quantum bits (where K is an integer equal to or greater than 2), and configured to operate on the n computational quantum bits and a plurality of auxiliary bits according to K, wherein the states of the computational quantum bits and the auxiliary bits are configured to be representable using at least a first state and a second state that are observable, the computational quantum circuit configured to operate in sequence on a first reflection operation, a first operational quantum circuit, a second reflection operation, and a second operational quantum circuit, the first reflection operation configured to operate on the plurality of auxiliary bits so as to change the phase of a first reflection state, which is one of the components of the first state and the components of the second state contained in each of the plurality of auxiliary bits, the first operational quantum circuit configured to operate on the n computational quantum bits corresponding to the input state, and including unit gate operations corresponding to each of the auxiliary bits, A computational quantum circuit, wherein each of the unit gate operations is configured to have one of the plurality of different auxiliary bits as a control bit, the computation quantum bit as a target bit, and to change the manner of action on the computation quantum bit depending on the state of the auxiliary bit, the second reflection operation is configured to act on the computation quantum bit and the auxiliary bit so as to change the phase of a second reflection state which is one of the first state components and second state components contained in each of the computation quantum bit and the auxiliary bit, and the second operational quantum circuit is configured to be convertible into a Hermitian conjugate circuit of the first operational quantum circuit using a predetermined unitary gate operation.

11. A method for generating a computational quantum circuit as set forth in claim 10, comprising: an acquisition step of acquiring information on the input state, information on the Hamiltonian, and the number of iterations of an operation based on the Hamiltonian, wherein the number of iterations corresponds to K which is the number of unit gate operations; an allocation step of allocating the plurality of auxiliary bits corresponding to the number of iterations; and a generation step of generating a computational quantum circuit configured to repeatedly apply the operation to the computational quantum bits based on the results acquired in the acquisition step.

12. An information processing system comprising at least one device, the information processing system having at least one processor capable of executing a program to perform each step of the information processing method according to any one of claims 1 to 9.

13. A program that causes at least one computer to execute each step of the information processing method according to any one of claims 1 to 9.

Images