Light-emitting element and display device

Abstract

This light-emitting element comprises: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; an active layer disposed between the first semiconductor layer and the second semiconductor layer; a first insulating film at least partially surrounding the first semiconductor layer, the second semiconductor layer, and the active layer; a second insulating film surrounding the first insulating film; and a third insulating film surrounding the second insulating film, wherein the bond dissociation energy of the second insulating film is smaller than the bond dissociation energy of the first insulating film and the bond dissociation energy of the third insulating film.

Description

Light-emitting elements and display devices

[0001] The present invention relates to a light-emitting element and a display device.

[0002] As interest in information display devices has recently increased, research and development on display devices are continuously being conducted.

[0003] The problem that the present invention seeks to solve is to improve the reliability of a light-emitting device.

[0004] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] According to an embodiment for solving the above problem, a light-emitting device includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, an active layer disposed between the first semiconductor layer and the second semiconductor layer, a first insulating film at least partially surrounding the first semiconductor layer, the second semiconductor layer, and the active layer, a second insulating film surrounding the first insulating film, and a third insulating film surrounding the second insulating film, wherein a bond dissociation energy of the second insulating film may be smaller than each of a bond dissociation energy of the first insulating film and a bond dissociation energy of the third insulating film.

[0006] The bond dissociation energy of the first insulating film may be about 7.0 eV to about 9.0 eV.

[0007] The bond dissociation energy of the second insulating film may be about 6.0 eV to about 8.5 eV.

[0008] The bond dissociation energy of the third insulating film may be about 7.0 eV to about 9.0 eV.

[0009] The first insulating film and the third insulating film may contain the same material.

[0010] The thickness of the first insulating film may be thicker than the thickness of the second insulating film.

[0011] The thickness of the first insulating film may be about 1 nm to about 5 nm, and the thickness of the second insulating film may be about 1 nm to about 3 nm.

[0012] The thickness of the third insulating film may be thicker than the thickness of the second insulating film.

[0013] The thickness of the third insulating film may be about 1 nm to about 5 nm, and the thickness of the second insulating film may be about 1 nm to about 3 nm.

[0014] The light emitting element may further include a fourth insulating film surrounding the third insulating film.

[0015] A display device according to an embodiment for solving the above problem includes a plurality of electrodes spaced apart from each other, and a plurality of light-emitting elements arranged between the plurality of electrodes, wherein each of the plurality of light-emitting elements includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, an active layer between the first semiconductor layer and the second semiconductor layer, a first insulating film at least partially surrounding the first semiconductor layer, the second semiconductor layer, and the active layer, a second insulating film surrounding the first insulating film, and a third insulating film surrounding the second insulating film, wherein a bond dissociation energy of the second insulating film may be smaller than each of a bond dissociation energy of the first insulating film and a bond dissociation energy of the third insulating film.

[0016] The bond dissociation energy of the first insulating film may be about 7.0 eV to about 9.0 eV.

[0017] The bond dissociation energy of the second insulating film may be about 6.0 eV to about 8.5 eV.

[0018] The bond dissociation energy of the third insulating film may be about 7.0 eV to about 9.0 eV.

[0019] The first insulating film and the third insulating film may contain the same material.

[0020] The thickness of the first insulating film may be thicker than the thickness of the second insulating film.

[0021] The thickness of the first insulating film may be about 1 nm to about 5 nm, and the thickness of the second insulating film may be about 1 nm to about 3 nm.

[0022] The thickness of the third insulating film may be thicker than the thickness of the second insulating film.

[0023] The thickness of the third insulating film may be about 1 nm to about 5 nm, and the thickness of the second insulating film may be about 1 nm to about 3 nm.

[0024] The display device may further include a plurality of connecting electrodes arranged on the plurality of light-emitting elements and electrically connected to the plurality of light-emitting elements.

[0025] Specific details of other embodiments may be included in the detailed description and drawings.

[0026] According to an embodiment of the present invention, by forming the bond dissociation energy of the second insulating film to be lower than the bond dissociation energy of the first insulating film and the bond dissociation energy of the third insulating film, damage to the active layer can be minimized, thereby improving the reliability of the light-emitting device.

[0027] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects may be included in the present specification.

[0028] The foregoing and other aspects, features, and advantages of specific embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0029] Fig. 1 is a perspective view showing a light-emitting element according to an embodiment.

[0030] Figures 2 and 3 are schematic cross-sectional views showing a light-emitting element according to an embodiment.

[0031] Fig. 4 is a plan view showing a display device according to an embodiment.

[0032] Fig. 5 is a schematic equivalent circuit diagram of a pixel according to an embodiment.

[0033] Figures 6 and 7 are plan views showing pixels according to an embodiment.

[0034] Figure 8 is a schematic cross-sectional view taken along line AA' of Figure 6.

[0035] Figure 9 is a schematic cross-sectional view taken along the BB' line of Figure 6.

[0036] Fig. 10 is a schematic cross-sectional view taken along line CC' of Fig. 7.

[0037] Fig. 11 is a schematic cross-sectional view taken along line DD' of Fig. 7.

[0038] Fig. 12 is a schematic cross-sectional view showing first to third pixels according to an embodiment.

[0039] Fig. 13 is a schematic cross-sectional diagram showing a pixel according to an embodiment.

[0040] In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, the terms "embodiments" and "implementations" are interchangeable terms, which are non-limiting examples of the devices or methods disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. It should be understood that the various embodiments are neither exclusive nor limiting of the disclosure. For example, specific features, configurations, and characteristics of one embodiment may be used or implemented in another embodiment.

[0041] Unless otherwise specified, the illustrated embodiments are to be understood as providing features of the present invention. Accordingly, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or rearranged without departing from the concepts of the present invention.

[0042] The use of crosshatching and / or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of crosshatching or shading, unless otherwise specified, conveys or indicates any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements, and / or any other characteristics, properties, or attributes of the elements. Furthermore, in the accompanying drawings, the dimensions and relative sizes of elements may be exaggerated for clarity and / or technical purposes. Where the embodiments can be implemented differently, the order of certain processes may be performed differently from the order described. For example, two processes described in succession may be performed substantially simultaneously or in an order reversed from the order described. Furthermore, like reference numbers and / or reference letters represent like elements.

[0043] When a component or layer is referred to as being "on," "connected," or "coupled" to another component or layer, it includes both cases where the component or layer is directly on top of the other component or layer or there are other intervening layers or elements. However, when a component or layer is referred to as being "directly on," "directly connected," or "directly coupled" to another component or layer, it does not include the other layer or element being directly on top of the other component or layer or there are other intervening layers or elements. Like reference numerals refer to like components throughout the specification. For this purpose, the term "connected" may mean a physical, electrical, and / or fluidic connection, with or without intervening elements. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, such as the x-axis, y-axis, and z-axis, and may be interpreted in a broad sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0044] For purposes of the present invention, “at least one of A and B” can be interpreted as one A, one B, or any combination of A and B. Additionally, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as one X, one Y, one Z, or a combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0046] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features are now positioned "above" the other elements or features. Thus, in one embodiment, the term "below" may encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the invention. As used herein, the singular also includes the plural unless the context clearly dictates otherwise. The terms "comprises" and / or "comprising," as used herein, do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups stated therein. Furthermore, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation rather than terms of degree, and as such, are utilized to account for inherent variations in measurements, calculations, and / or values ​​provided that would be recognizable to one of ordinary skill in the art.

[0048] Various embodiments are described with reference to drawings schematically illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0049] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries, such as terms defined in such dictionaries, should be interpreted consistent with their meaning in the context of the relevant art and disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0051] Fig. 1 is a perspective view showing a light-emitting element according to an embodiment. Figs. 2 and 3 are schematic cross-sectional views showing a light-emitting element according to an embodiment. In Figs. 1 to 3, a columnar light-emitting element (LD) is illustrated, but the type and / or shape of the light-emitting element (LD) may not be limited thereto.

[0052] Referring to FIGS. 1 to 3, the light emitting element (LD) may include a first semiconductor layer (11), an active layer (12), a second semiconductor layer (13), and / or an electrode layer (14).

[0053] The light emitting element (LD) may be formed in a columnar shape extending in one direction. The light emitting element (LD) may have a first end (EP1) and a second end (EP2). One of the first and second semiconductor layers (11, 13) may be disposed at the first end (EP1) of the light emitting element (LD). The other of the first and second semiconductor layers (11, 13) may be disposed at the second end (EP2) of the light emitting element (LD). For example, the first semiconductor layer (11) may be disposed at the first end (EP1) of the light emitting element (LD), and the second semiconductor layer (13) may be disposed at the second end (EP2) of the light emitting element (LD).

[0054] According to an embodiment, the light emitting element (LD) may be a light emitting element manufactured in a columnar shape through an etching method or the like. In the present specification, the columnar shape includes a rod-like shape or a bar-like shape having an aspect ratio greater than 1, such as a circular column or a polygonal column, and the shape of the cross-section of the light emitting element (LD) is not limited.

[0055] The light emitting element (LD) may have a size as small as a nanometer scale to a micrometer scale. The light emitting element (LD) may have a diameter (D) (or width) and / or a length (L) in the nanometer scale to a micrometer scale, respectively. For example, the length of the light emitting element (LD) may be about 4 um or less. However, the size of the light emitting element (LD) is not limited thereto, and the size of the light emitting element (LD) may be variously changed depending on the design conditions of various devices that use a light emitting device using the light emitting element (LD) as a light source, such as a display device.

[0056] The first semiconductor layer (11) may be a semiconductor layer of the first conductivity type. For example, the first semiconductor layer (11) may include a p-type semiconductor layer. For example, the first semiconductor layer (11) may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, or AlN, and may include a p-type semiconductor layer doped with a first conductivity type dopant such as Mg. However, the material constituting the first semiconductor layer (11) is not limited thereto, and various other materials may also constitute the first semiconductor layer (11).

[0057] The active layer (12) may be disposed between the first semiconductor layer (11) and the second semiconductor layer (13). The active layer (12) may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure, but is not necessarily limited thereto. The active layer (12) may include GaN, InGaN, InAlGaN, AlGaN, AlN, or a combination thereof, and in addition, various materials may form the active layer (12). When a voltage higher than the threshold voltage is applied to both ends of the light-emitting element (LD), electron-hole pairs combine in the active layer (12) and the light-emitting element (LD) emits light. By controlling the light emission of the light-emitting element (LD) using this principle, the light-emitting element (LD) can be used as a light source for various light-emitting devices including pixels of a display device.

[0058] The second semiconductor layer (13) is disposed on the active layer (12) and may include a semiconductor layer of a different type from the first semiconductor layer (11). The second semiconductor layer (13) may include an n-type semiconductor layer. For example, the second semiconductor layer (13) may include a semiconductor material of any one of InAlGaN, GaN, AlGaN, InGaN, AlN, or a combination thereof, and may include an n-type semiconductor layer doped with a second conductive dopant such as Si, Ge, Sn, or a combination thereof. However, the material constituting the second semiconductor layer (13) is not limited thereto, and the second semiconductor layer (13) may be composed of various other materials.

[0059] The electrode layer (14) may be disposed on the first end (EP1) and / or the second end (EP2) of the light emitting element (LD). In FIGS. 2 and 3, an example in which the electrode layer (14) may be formed on the first semiconductor layer (11) is illustrated, but the present invention is not necessarily limited thereto. For example, a separate electrode layer may be further disposed on the second semiconductor layer (13).

[0060] The electrode layer (14) may include a transparent metal or a transparent metal oxide. For example, the electrode layer (14) may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and zinc tin oxide (ZTO), but is not necessarily limited thereto. In this way, when the electrode layer (14) is made of a transparent metal or a transparent metal oxide, light generated in the active layer (12) of the light-emitting element (LD) can pass through the electrode layer (14) and be emitted to the outside of the light-emitting element (LD).

[0061] A first insulating film (INF1) may be provided on the light emitting element (LD). The first insulating film (INF1) may at least partially surround the first semiconductor layer (11), the active layer (12), the second semiconductor layer (13), and / or the electrode layer (14). The first insulating film (INF1) may be disposed (e.g., directly disposed) on the surface of the first semiconductor layer (11), the active layer (12), the second semiconductor layer (13), and / or the electrode layer (14). The first insulating film (INF1) may expose first and second ends (EP1, EP2) of the light emitting element (LD) having different polarities.

[0062] The first insulating film (INF1) can improve the lifespan and luminous efficiency of the light emitting elements (LD) by minimizing surface defects of the light emitting elements (LD). In general, oxygen may be separated from the first insulating film (INF1) due to heat generated during operation, and the oxygen separated from the first insulating film (INF1) may penetrate into the active layer (12) and damage the active layer (12), thereby causing a decrease in reliability. Therefore, in order to suppress the separation of oxygen from the first insulating film (INF1), the first insulating film (INF1) may be formed of a material having a high bond dissociation energy. For example, the bond dissociation energy of the first insulating film (INF1) may be about 7.0 eV to about 9.0 eV, but is not necessarily limited thereto.

[0063] A second insulating film (INF2) may be provided on the first insulating film (INF1). The second insulating film (INF2) may surround the first insulating film (INF1). The second insulating film (INF2) may be disposed (for example, directly disposed) on the surface of the first insulating film (INF1). The second insulating film (INF2) may expose first and second ends (EP1, EP2) of a light-emitting element (LD) having different polarities.

[0064] The second insulating film (INF2) can improve the reliability of the light emitting element (LD) by compensating for defects in the first insulating film (INF1). For example, even if an oxygen vacancy is formed due to deterioration of the first insulating film (INF1), oxygen can be supplied from the second insulating film (INF2) to compensate for the defects in the first insulating film (INF1). For this purpose, the bond dissociation energy of the second insulating film (INF2) may be lower than the bond dissociation energy of the first insulating film (INF1). For example, the bond dissociation energy of the second insulating film (INF2) may be about 6.0 eV to about 8.5 eV, but is not necessarily limited thereto.

[0065] A third insulating film (INF3) may be provided on the second insulating film (INF2). The third insulating film (INF3) may surround the second insulating film (INF2). The third insulating film (INF3) may be disposed (e.g., directly disposed) on the surface of the second insulating film (INF2). The third insulating film (INF3) may expose first and second ends (EP1, EP2) of the light-emitting element (LD) having different polarities.

[0066] The third insulating film (INF3) can improve the reliability of the light-emitting element (LD) by blocking oxygen from entering from the outside. For example, the third insulating film (INF3) is an insulating film formed on the outside of the light-emitting element (LD) and can be exposed to the outside. The third insulating film (INF3) can block a path for oxygen to enter the first insulating film (INF1) and the second insulating film (INF2) formed inside, thereby preventing oxygen from diffusing into the active layer (12). To this end, the third insulating film (INF3) can be formed of a material having a high bond dissociation energy. The bond dissociation energy of the third insulating film (INF3) can be greater than the bond dissociation energy of the second insulating film (INF2). The bond dissociation energy of the third insulating film (INF3) can be the same as the bond dissociation energy of the first insulating film (INF1). For example, the bond dissociation energy of the third insulating film (INF3) may be, but is not necessarily limited to, about 7.0 eV to about 9.0 eV. In an embodiment, the third insulating film (INF3) may include, but is not necessarily limited to, the same material as the first insulating film (INF1).

[0067] In an embodiment, the thickness of the first insulating film (INF1) may be thicker than the thickness of the second insulating film (INF2). For example, the thickness of the first insulating film (INF1) may be about 1 nm to about 5 nm, and the thickness of the second insulating film (INF2) may be about 1 nm to about 3 nm, but is not necessarily limited thereto. The thickness of the third insulating film (INF3) may be thicker than the thickness of the second insulating film (INF2). The thickness of the third insulating film (INF3) may be the same as the thickness of the first insulating film (INF1). For example, the thickness of the third insulating film (INF3) may be about 1 nm to about 5 nm, and the thickness of the second insulating film (INF2) may be about 1 nm to about 3 nm, but is not necessarily limited thereto.

[0068] According to an embodiment, a fourth insulating film (INF4) may be further provided on the third insulating film (INF3) as illustrated in FIG. 3. The fourth insulating film (INF4) may surround the third insulating film (INF3). The fourth insulating film (INF4) may be disposed (e.g., directly disposed) on a surface of the third insulating film (INF3). The fourth insulating film (INF4) may expose first and second ends (EP1, EP2) of the light-emitting element (LD) having different polarities. According to an embodiment, the fourth insulating film (INF4) may be omitted.

[0069] The first insulating film (INF1), the second insulating film (INF2), the third insulating film (INF3), and / or the fourth insulating film (INF4) may be formed of an inorganic insulating material. For example, the first insulating film (INF1), the second insulating film (INF2), the third insulating film (INF3), and / or the fourth insulating film (INF4) may include various types of inorganic materials, including silicon oxide (SiOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), tantalum oxide (TaOx), lanthanum oxide (LaOx), or combinations thereof. However, the materials forming the first insulating film (INF1), the second insulating film (INF2), the third insulating film (INF3), and / or the fourth insulating film (INF4) are not necessarily limited thereto, and may be variously changed within a range satisfying the above-described bond dissociation energy range.

[0070] The light-emitting device including the above-described light-emitting element (LD) can be used in various types of devices that require a light source, including display devices. For example, light-emitting elements (LD) can be arranged in each pixel of a display panel and used as a light source for each pixel. However, the application fields of the light-emitting element (LD) are not limited to the examples described above. For example, the light-emitting element (LD) can also be used in other types of devices that require a light source, such as lighting devices.

[0071] Fig. 4 is a plan view showing a display device according to an embodiment.

[0072] FIG. 4 illustrates an example of an electronic device that can use the light emitting element (LD) described in the embodiments of FIGS. 1 to 3 as a light source, and in particular, a display panel (PNL) provided in a display device.

[0073] For convenience of explanation, the structure of the display panel (PNL) is briefly illustrated in FIG. 4, focusing on the display area (DA). However, depending on the embodiment, at least one driving circuit unit (for example, at least one of a scan driving unit and a data driving unit), wires, and / or pads that are not illustrated may be further arranged on the display panel (PNL).

[0074] Referring to FIG. 4, a display panel (PNL) and a base layer (BSL) for forming the same may include a display area (DA) for displaying an image, and a non-display area (NDA) excluding the display area (DA). The display area (DA) may constitute a screen on which an image is displayed, and the non-display area (NDA) may be an area remaining excluding the display area (DA).

[0075] A pixel unit (PXU) may be arranged in the display area (DA). The pixel unit (PXU) may include a first pixel (PXL1), a second pixel (PXL2), and / or a third pixel (PXL3). Hereinafter, when at least one of the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) is arbitrarily referred to, or when two or more types of pixels are comprehensively referred to, the term "pixel (PXL)" or "pixels (PXL)" will be used.

[0076] The pixels (PXL) may be arranged regularly according to a stripe or pentile array structure, etc. However, the array structure of the pixels (PXL) is not limited thereto, and the pixels (PXL) may be arranged in the display area (DA) in various structures and / or methods.

[0077] According to an embodiment, two or more types of pixels (PXL) that emit light of different colors may be arranged in the display area (DA). For example, first pixels (PXL1) that emit light of a first color, second pixels (PXL2) that emit light of a second color, and third pixels (PXL3) that emit light of a third color may be arranged in the display area (DA). At least one of the first to third pixels (PXL1, PXL2, PXL3) that are arranged adjacent to each other may constitute one pixel unit (PXU) that can emit light of various colors. For example, the first to third pixels (PXL1, PXL2, PXL3) may each be a pixel that emits light of a color (e.g., a predetermined color or a selectable color). According to an embodiment, the first pixel (PXL1) may be a red pixel that emits red light, the second pixel (PXL2) may be a green pixel that emits green light, and the third pixel (PXL3) may be a blue pixel that emits blue light, but is not limited thereto.

[0078] In an embodiment, a first pixel (PXL1), a second pixel (PXL2), and a third pixel (PXL3) may have light-emitting elements that emit light of the same color, and may include color conversion layers and / or color filter layers of different colors disposed on each of the light-emitting elements, thereby emitting light of a first color, a second color, and a third color, respectively. In an embodiment, the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) may have light-emitting elements of a first color, a light-emitting element of a second color, and a light-emitting element of a third color, respectively, as light sources, thereby emitting light of a first color, a second color, and a third color, respectively. However, the color, type, and / or number of the pixels (PXL) constituting each pixel unit (PXU) are not particularly limited. For example, the color of the light emitted by each pixel (PXL) may be varied.

[0079] A pixel (PXL) may include at least one light source driven by a control signal (e.g., a scan signal and a data signal) and / or a power source (e.g., a first power source and a second power source). In an embodiment, the light source may include at least one light emitting element (LD) according to any one of the embodiments of FIGS. 1 to 3, for example, ultra-small columnar light emitting elements (LD) having a size as small as a nanometer scale or a micrometer scale. However, the present invention is not necessarily limited thereto, and various types of light emitting elements (LD) may be used as the light source of the pixel (PXL).

[0080] In an embodiment, each pixel (PXL) may be configured as an active pixel. However, the type, structure, and / or driving method of the pixels (PXL) applicable to the display device is not particularly limited. For example, each pixel (PXL) may be configured as a pixel of a passive or active light-emitting display device with various structures and / or driving methods.

[0081] Fig. 5 is a schematic equivalent circuit diagram of a pixel according to an embodiment.

[0082] The pixel (PXL) illustrated in FIG. 5 may be any one of the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) provided in the display panel (PNL) of FIG. 4. The first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) may have substantially the same or similar structures.

[0083] Referring to FIG. 5, each pixel (PXL) may further include an emission unit (EMU) for generating light of a brightness corresponding to a data signal and a pixel circuit (PXC) for driving the emission unit (EMU).

[0084] A pixel circuit (PXC) may be electrically connected between a first power supply (VDD) and a light-emitting unit (EMU). The pixel circuit (PXC) may be electrically connected to a scan line (SL) and a data line (DL) of a corresponding pixel (PXL), and may control the operation of the light-emitting unit (EMU) in response to scan signals and data signals supplied from the scan line (SL) and the data line (DL). The pixel circuit (PXC) may be further electrically connected selectively to a sensing signal line (SSL) and a sensing line (SENL).

[0085] The pixel circuit (PXC) may include at least one transistor and a capacitor. For example, the pixel circuit (PXC) may include a first transistor (M1), a second transistor (M2), a third transistor (M3), and a storage capacitor (Cst).

[0086] A first transistor (M1) may be electrically connected between a first power source (VDD) and a first connection electrode (ELT1). A gate electrode of the first transistor (M1) may be electrically connected to a first node (N1). The first transistor (M1) may control a driving current supplied to a light emitting unit (EMU) in response to a voltage of the first node (N1). For example, the first transistor (M1) may be a driving transistor that controls a driving current of a pixel (PXL).

[0087] In an embodiment, the first transistor (M1) may optionally include a lower conductive layer (BML) (also referred to as a “lower electrode,” a “back gate electrode,” or a “lower shading layer”). The gate electrode of the first transistor (M1) and the lower conductive layer (BML) may overlap each other with an insulating layer therebetween. In an embodiment, the lower conductive layer (BML) may be electrically connected to one electrode of the first transistor (M1), for example, a source or drain electrode.

[0088] When the first transistor (M1) includes a lower conductive layer (BML), a back-biasing technique (or sync technique) may be applied to apply a back-biasing voltage to the lower conductive layer (BML) of the first transistor (M1) when driving a pixel (PXL) to shift the threshold voltage of the first transistor (M1) in the negative or positive direction. For example, by applying the source-sink technique by connecting the lower conductive layer (BML) to the source electrode of the first transistor (M1), the threshold voltage of the first transistor (M1) may be shifted in the negative or positive direction. When the lower conductive layer (BML) is arranged under the semiconductor pattern forming the channel of the first transistor (M1), the lower conductive layer (BML) may function as a light-shielding pattern and stabilize the operating characteristics of the first transistor (M1). However, the function and / or utilization method of the lower conductive layer (BML) is not limited thereto.

[0089] The second transistor (M2) may be electrically connected between the data line (DL) and the first node (N1). In addition, the gate electrode of the second transistor (M2) may be electrically connected to the scan line (SL). The second transistor (M2) may be turned on when a scan signal of a gate-on voltage (e.g., a high level voltage) is supplied from the scan line (SL), thereby connecting the data line (DL) and the first node (N1).

[0090] For each frame period, a data signal of the corresponding frame is supplied to a data line (DL), and the data signal can be transmitted to a first node (N1) through a second transistor (M2) that is turned on during a period in which a scan signal of a gate-on voltage is supplied. For example, the second transistor (M2) can be a switching transistor for transmitting each data signal to the interior of a pixel (PXL).

[0091] One electrode of the storage capacitor (Cst) may be electrically connected to a first node (N1), and the other electrode of the storage capacitor (Cst) may be electrically connected to a second electrode of the first transistor (M1). The storage capacitor (Cst) may be charged with a voltage corresponding to a data signal supplied to the first node (N1) during each frame period.

[0092] A third transistor (M3) may be electrically connected between a first connection electrode (ELT1) (or a second electrode of the first transistor (M1)) and a sensing line (SENL). A gate electrode of the third transistor (M3) may be electrically connected to a sensing signal line (SSL). The third transistor (M3) may transmit a voltage value applied to the first connection electrode (ELT1) to the sensing line (SENL) according to a sensing signal supplied to the sensing signal line (SSL). The voltage value transmitted through the sensing line (SENL) may be provided to an external circuit (for example, a timing control unit), and the external circuit may extract characteristic information of each pixel (PXL) (for example, a threshold voltage of the first transistor (M1)) based on the provided voltage value. The extracted characteristic information may be used to convert image data so that a characteristic deviation between pixels (PXL) is compensated for.

[0093] In Fig. 5, all transistors included in the pixel circuit (PXC) are depicted as n-type transistors, but this is not necessarily limited to them. For example, at least one of the first, second, and third transistors (M1, M2, M3) may be changed to a p-type transistor.

[0094] The structure and driving method of the pixel (PXL) can be varied in various ways. For example, the pixel circuit (PXC) can be composed of pixel circuits having various structures and / or driving methods in addition to the embodiment illustrated in FIG. 5.

[0095] For example, the pixel circuit (PXC) may not include the third transistor (M3). The pixel circuit (PXC) may further include other circuit elements, such as a compensation transistor for compensating for a threshold voltage of the first transistor (M1), an initialization transistor for initializing the voltage of the first node (N1) and / or the first connection electrode (ELT1), a light emission control transistor for controlling a period of time during which a driving current is supplied to the light emitting unit (EMU), and / or a boosting capacitor for boosting the voltage of the first node (N1).

[0096] The light emitting unit (EMU) may include at least one light emitting element (LD), for example, a plurality of light emitting elements (LD), electrically connected between a first power supply (VDD) and a second power supply (VSS).

[0097] For example, the light emitting unit (EMU) may include a first connection electrode (ELT1) electrically connected to a first power source (VDD) via a pixel circuit (PXC) and a first power line (PL1), a fifth connection electrode (ELT5) electrically connected to a second power source (VSS) via a second power line (PL2), and a plurality of light emitting elements (LD) electrically connected between the first and fifth connection electrodes (ELT1, ELT5).

[0098] The first power supply (VDD) and the second power supply (VSS) can have different potentials so that the light emitting elements (LD) can emit light. For example, the first power supply (VDD) can be set to a high potential power supply, and the second power supply (VSS) can be set to a low potential power supply.

[0099] In an embodiment, the light emitting unit (EMU) may include at least one series unit. Each series unit may include a pair of electrodes (for example, two electrodes) and at least one light emitting element (LD) electrically connected in a forward direction between the pair of electrodes. Here, the number of series units constituting the light emitting unit (EMU) and the number of light emitting elements (LD) constituting each series unit are not particularly limited. For example, the number of light emitting elements (LD) constituting each series unit may be the same as or different from each other, and the number of light emitting elements (LD) is not particularly limited.

[0100] For example, the light emitting unit (EMU) may include a first series stage including at least one first light emitting element (LD1), a second series stage including at least one second light emitting element (LD2), a third series stage including at least one third light emitting element (LD3), and a fourth series stage including at least one fourth light emitting element (LD4).

[0101] The first series circuit may include a first connection electrode (ELT1) and a second connection electrode (ELT2), and at least one first light-emitting element (LD1) electrically connected between the first and second connection electrodes (ELT1, ELT2). Each first light-emitting element (LD1) may be electrically connected in a forward direction between the first and second connection electrodes (ELT1, ELT2). For example, a first end (EP1) of the first light-emitting element (LD1) may be electrically connected to the first connection electrode (ELT1), and a second end (EP2) of the first light-emitting element (LD1) may be electrically connected to the second connection electrode (ELT2).

[0102] The second series circuit may include a second connection electrode (ELT2) and a third connection electrode (ELT3), and at least one second light-emitting element (LD2) electrically connected between the second and third connection electrodes (ELT2, ELT3). Each second light-emitting element (LD2) may be electrically connected in a forward direction between the second and third connection electrodes (ELT2, ELT3). For example, a first end (EP1) of the second light-emitting element (LD2) may be electrically connected to the second connection electrode (ELT2), and a second end (EP2) of the second light-emitting element (LD2) may be electrically connected to the third connection electrode (ELT3).

[0103] The third series circuit may include a third connection electrode (ELT3) and a fourth connection electrode (ELT4), and at least one third light-emitting element (LD3) electrically connected between the third and fourth connection electrodes (ELT3, ELT4). Each third light-emitting element (LD3) may be electrically connected in a forward direction between the third and fourth connection electrodes (ELT3, ELT4). For example, a first end (EP1) of the third light-emitting element (LD3) may be electrically connected to the third connection electrode (ELT3), and a second end (EP2) of the third light-emitting element (LD3) may be electrically connected to the fourth connection electrode (ELT4).

[0104] The fourth series circuit may include a fourth connection electrode (ELT4) and a fifth connection electrode (ELT5), and at least one fourth light-emitting element (LD4) electrically connected between the fourth and fifth connection electrodes (ELT4, ELT5). Each fourth light-emitting element (LD4) may be electrically connected in a forward direction between the fourth and fifth connection electrodes (ELT4, ELT5). For example, a first end (EP1) of the fourth light-emitting element (LD4) may be electrically connected to the fourth connection electrode (ELT4), and a second end (EP2) of the fourth light-emitting element (LD4) may be electrically connected to the fifth connection electrode (ELT5).

[0105] The first electrode of the light emitting unit (EMU), for example, the first connecting electrode (ELT1), may be the anode electrode of the light emitting unit (EMU). The last electrode of the light emitting unit (EMU), for example, the fifth connecting electrode (ELT5), may be the cathode electrode of the light emitting unit (EMU).

[0106] The remaining electrodes of the light emitting unit (EMU), for example, the second connection electrode (ELT2), the third connection electrode (ELT3), and / or the fourth connection electrode (ELT4), may each constitute an intermediate electrode. For example, the second connection electrode (ELT2) may constitute a first intermediate electrode (IET1), the third connection electrode (ELT3) may constitute a second intermediate electrode (IET2), and the fourth connection electrode (ELT4) may constitute a third intermediate electrode (IET3).

[0107] When light emitting elements (LD) are electrically connected in a series / parallel structure, power efficiency can be improved compared to when the same number of light emitting elements (LD) are only connected in parallel. In a pixel (PXL) in which light emitting elements (LD) are electrically connected in a series / parallel structure, even if a short circuit defect occurs in some of the series stages, a predetermined brightness can be expressed through the light emitting elements (LD) of the remaining series stages, so the possibility of a dark spot defect in the pixel (PXL) can be reduced. However, it is not necessarily limited thereto, and the light emitting elements (LD) can be electrically connected only in series to form a light emitting unit (EMU), or can be connected only in parallel to form a light emitting unit (EMU).

[0108] The light emitting elements (LD) may each include a first end (EP1) (e.g., a p-type end) electrically connected to a first power source (VDD) via at least one electrode (e.g., a first connection electrode (ELT1)), a pixel circuit (PXC) and / or a first power line (PL1), and a second end (EP2) (e.g., an n-type end) connected to a second power source (VSS) via at least one other electrode (e.g., a fifth connection electrode (ELT5)) and a second power line (PL2). For example, the light emitting elements (LD) may be electrically connected in a forward direction between the first power source (VDD) and the second power source (VSS). The light emitting elements (LD) electrically connected in the forward direction may constitute effective light sources of the light emitting unit (EMU).

[0109] The light-emitting elements (LD) can emit light with a brightness corresponding to the driving current when the driving current is supplied through the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply the driving current corresponding to the grayscale value to be expressed in the corresponding frame to the light-emitting unit (EMU). Accordingly, the light-emitting elements (LD) emit light with a brightness corresponding to the driving current, and the light-emitting unit (EMU) can express a brightness corresponding to the driving current.

[0110] Figures 6 and 7 are plan views showing pixels according to embodiments. Figure 8 is a schematic cross-sectional view taken along line AA' of Figure 6. Figure 9 is a schematic cross-sectional view taken along line BB' of Figure 6. Figure 10 is a schematic cross-sectional view taken along line CC' of Figure 7. Figure 11 is a schematic cross-sectional view taken along line DD' of Figure 7.

[0111] For example, FIGS. 6 and 7 may be any one of the first to third pixels (PXL1, PXL2, PXL3) constituting the pixel unit (PXU) of FIG. 4, and the first to third pixels (PXL1, PXL2, PXL3) may have substantially the same or similar structures to each other. FIGS. 6 and 7 disclose an embodiment in which each pixel (PXL) includes light-emitting elements (LD) arranged in four serial stages, as illustrated in FIG. 5, but the number of serial stages of each pixel (PXL) may vary depending on the embodiment.

[0112] Hereinafter, when referring to one or more light-emitting elements among the first to fourth light-emitting elements (LD1, LD2, LD3, LD4) arbitrarily, or when referring to two or more types of light-emitting elements comprehensively, it will be referred to as “light-emitting element (LD)” or “light-emitting elements (LD)”. When referring to at least one electrode among the electrodes including the first to third electrodes (ALE1, ALE2, ALE3), it will be referred to as “electrode (ALE)” or “electrodes (ALE)”, and when referring to at least one electrode among the electrodes including the first to fifth connection electrodes (ELT1, ELT2, ELT3, ELT4, ELT5), it will be referred to as “connection electrode (ELT)” or “connection electrodes (ELT)”.

[0113] Referring to FIGS. 6 and 7, each pixel (PXL) may include an emissive area (EA) and a non-emissive area (NEA). The emissive area (EA) may be an area capable of emitting light, including light-emitting elements (LD). The non-emissive area (NEA) may be arranged to surround the emissive area (EA). The non-emissive area (NEA) may be an area in which a first bank (BNK1) surrounding the emissive area (EA) is provided. The first bank (BNK1) may be arranged to be provided in the non-emissive area (NEA) and at least partially surround the emissive area (EA).

[0114] The first bank (BNK1) may include an opening overlapping the light-emitting area (EA). The opening of the first bank (BNK1) may provide a space in which light-emitting elements (LD) may be supplied to each pixel (PXL) during the step of supplying the light-emitting elements (LD). For example, a desired type and / or amount of light-emitting element ink may be supplied to the space defined by the opening of the first bank (BNK1).

[0115] The first bank (BNK1) may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylenesulfide resin, a benzocyclobutene (BCB), or a combination thereof. However, the first bank (BNK1) is not necessarily limited thereto, and the first bank (BNK1) may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium oxide (TiOx), various types of inorganic materials, or a combination thereof.

[0116] According to an embodiment, the first bank (BNK1) may include at least one light-shielding and / or reflective material, thereby preventing light leakage between adjacent pixels (PXL). For example, the first bank (BNK1) may include at least one black pigment.

[0117] Each pixel (PXL) may include barrier walls (WL), electrodes (ALE), light emitting elements (LD), and / or connecting electrodes (ELT).

[0118] The partition walls (WL) may overlap the emitting area (EA) and be spaced apart from each other. The partition walls (WL) may be at least partially disposed in the non-emitting area (NEA). The partition walls (WL) may extend along the second direction (Y-axis direction) and be spaced apart from each other along the first direction (X-axis direction).

[0119] The partition walls (WL) may each partially overlap at least one electrode (ALE) at least in the light-emitting area (EA). For example, the partition walls (WL) may be provided below each of the electrodes (ALE). As the partition walls (WL) are provided below each region of the electrodes (ALE), each region of the electrodes (ALE) may protrude upwardly of the pixel (PXL), for example, in the third direction (Z-axis direction), in the region where the partition walls (WL) are formed. When the partition walls (WL) and / or the electrodes (ALE) include a reflective material, a reflective wall structure may be formed around the light-emitting elements (LD). Accordingly, light emitted from the light-emitting elements (LD) may be emitted upwardly of the pixel (PXL) (for example, toward the front of the display panel (PNL) including a viewing angle range), thereby improving the light emission efficiency of the display panel (PNL).

[0120] Electrodes (ALE) may be provided at least in the light-emitting area (EA). The electrodes (ALE) may extend along the second direction (Y-axis direction) and may be spaced apart from each other along the first direction (X-axis direction).

[0121] The first to third electrodes (ALE1, ALE2, ALE3) may extend along the second direction (Y-axis direction) and may be sequentially arranged spaced apart from each other along the first direction (X-axis direction). Some of the electrodes (ALE) may be electrically connected to a pixel circuit (PXC in FIG. 5) and / or a power line (e.g., a predetermined or selectable power line) through a contact hole. For example, the first electrode (ALE1) may be electrically connected to the pixel circuit (PXC) and / or the first power line (PL1) through the contact hole, and the second electrode (ALE2) may be electrically connected to the second power line (PL2) through the contact hole.

[0122] According to an embodiment, some of the electrodes (ALE) may be electrically connected to some of the connection electrodes (ELT) through contact holes. For example, a first electrode (ALE1) may be electrically connected to a first connection electrode (ELT1) through a contact hole, and a second electrode (ALE2) may be electrically connected to a fifth connection electrode (ELT5) through a contact hole.

[0123] A pair of adjacent electrodes (ALE) can be supplied with different signals during the alignment step of the light emitting elements (LD). For example, when the first to third electrodes (ALE1, ALE2, ALE3) are sequentially arranged along the first direction (X-axis direction), the first electrode (ALE1) and the second electrode (ALE2) can be supplied with different alignment signals, and the second electrode (ALE2) and the third electrode (ALE3) can be supplied with different alignment signals.

[0124] The light emitting elements (LD) may be aligned between a pair of electrodes (ALE) in each light emitting area (EA). The light emitting elements (LD) may be electrically connected between a pair of connecting electrodes (ELT).

[0125] The first light-emitting element (LD1) can be aligned between the first and second electrodes (ALE1, ALE2). The first light-emitting element (LD1) can be electrically connected between the first and second connection electrodes (ELT1, ELT2). For example, the first light-emitting element (LD1) is aligned in a first region (for example, an upper region) of the first and second electrodes (ALE1, ALE2), a first end (EP1) of the first light-emitting element (LD1) can be electrically connected to the first connection electrode (ELT1), and a second end (EP2) of the first light-emitting element (LD1) can be electrically connected to the second connection electrode (ELT2).

[0126] The second light-emitting element (LD2) can be aligned between the first and second electrodes (ALE1, ALE2). The second light-emitting element (LD2) can be electrically connected between the second and third connection electrodes (ELT2, ELT3). For example, the second light-emitting element (LD2) is aligned in a second region (for example, a lower region) of the first and second electrodes (ALE1, ALE2), a first end (EP1) of the second light-emitting element (LD2) can be electrically connected to the second connection electrode (ELT2), and a second end (EP2) of the second light-emitting element (LD2) can be electrically connected to the third connection electrode (ELT3).

[0127] The third light-emitting element (LD3) may be aligned between the second and third electrodes (ALE2, ALE3). The third light-emitting element (LD3) may be electrically connected between the third and fourth connection electrodes (ELT3, ELT4). For example, the third light-emitting element (LD3) may be aligned in a second region (for example, a lower region) of the second and third electrodes (ALE2, ALE3), a first end (EP1) of the third light-emitting element (LD3) may be electrically connected to the third connection electrode (ELT3), and a second end (EP2) of the third light-emitting element (LD3) may be electrically connected to the fourth connection electrode (ELT4).

[0128] The fourth light-emitting element (LD4) may be aligned between the second and third electrodes (ALE2, ALE3). The fourth light-emitting element (LD4) may be electrically connected between the fourth and fifth connection electrodes (ELT4, ELT5). For example, the fourth light-emitting element (LD4) may be aligned in a first region (for example, an upper region) of the second and third electrodes (ALE2, ALE3), a first end (EP1) of the fourth light-emitting element (LD4) may be electrically connected to the fourth connection electrode (ELT4), and a second end (EP2) of the fourth light-emitting element (LD4) may be electrically connected to the fifth connection electrode (ELT5).

[0129] For example, a first light emitting element (LD1) may be positioned in the upper left region of the light emitting area (EA), and a second light emitting element (LD2) may be positioned in the lower left region of the light emitting area (EA). A third light emitting element (LD3) may be positioned in the lower right region of the light emitting area (EA), and a fourth light emitting element (LD4) may be positioned in the upper right region of the light emitting area (EA). However, the arrangement and / or connection structure of the light emitting elements (LD) may be variously changed depending on the structure of the light emitting unit (EMU) and / or the number of serial stages.

[0130] The connecting electrodes (ELT) are each provided at least in the light-emitting area (EA) and can be arranged to overlap at least one electrode (ALE) and / or light-emitting element (LD). For example, the connecting electrodes (ELT) can be formed on the electrodes (ALE) and / or light-emitting elements (LD) so as to overlap with the electrodes (ALE) and / or light-emitting elements (LD), and can be electrically connected to the light-emitting elements (LD).

[0131] The first connecting electrode (ELT1) is disposed on the first region (e.g., the upper region) of the first electrode (ALE1) and the first ends (EP1) of the first light-emitting elements (LD1), and can be electrically connected to the first ends (EP1) of the first light-emitting elements (LD1).

[0132] The second connection electrode (ELT2) may be disposed on a first region (e.g., an upper region) of the second electrode (ALE2) and the second ends (EP2) of the first light-emitting elements (LD1), and may be electrically connected to the second ends (EP2) of the first light-emitting elements (LD1). The second connection electrode (ELT2) may be disposed on a second region (e.g., a lower region) of the first electrode (ALE1) and the first ends (EP1) of the second light-emitting elements (LD2), and may be electrically connected to the first ends (EP1) of the second light-emitting elements (LD2). For example, the second connection electrode (ELT2) may electrically connect the second ends (EP2) of the first light-emitting elements (LD1) and the first ends (EP1) of the second light-emitting elements (LD2) in the light-emitting area (EA). For this purpose, the second connecting electrode (ELT2) may have a curved shape. For example, the second connecting electrode (ELT2) may have a structure that is bent or curved at the boundary between the area where at least one first light-emitting element (LD1) is arranged and the area where at least one second light-emitting element (LD2) is arranged.

[0133] The third connection electrode (ELT3) may be disposed on the second region (e.g., the lower region) of the second electrode (ALE2) and the second ends (EP2) of the second light-emitting elements (LD2), and may be electrically connected to the second ends (EP2) of the second light-emitting elements (LD2). The third connection electrode (ELT3) may be disposed on the second region (e.g., the lower region) of the third electrode (ALE3) and the first ends (EP1) of the third light-emitting elements (LD3), and may be electrically connected to the first ends (EP1) of the third light-emitting elements (LD3). For example, the third connection electrode (ELT3) may electrically connect the second ends (EP2) of the second light-emitting elements (LD2) and the first ends (EP1) of the third light-emitting elements (LD3) in the light-emitting area (EA). For this purpose, the third connecting electrode (ELT3) may have a curved shape. For example, the third connecting electrode (ELT3) may have a structure that is bent or curved at the boundary between the area where at least one second light-emitting element (LD2) is arranged and the area where at least one third light-emitting element (LD3) is arranged.

[0134] The fourth connection electrode (ELT4) may be disposed on the second region (e.g., the lower region) of the second electrode (ALE2) and the second ends (EP2) of the third light-emitting elements (LD3), and may be electrically connected to the second ends (EP2) of the third light-emitting elements (LD3). The fourth connection electrode (ELT4) may be disposed on the first region (e.g., the upper region) of the third electrode (ALE3) and the first ends (EP1) of the fourth light-emitting elements (LD4), and may be electrically connected to the first ends (EP1) of the fourth light-emitting elements (LD4). For example, the fourth connection electrode (ELT4) may electrically connect the second ends (EP2) of the third light-emitting elements (LD3) and the first ends (EP1) of the fourth light-emitting elements (LD4) in the light-emitting area (EA). For this purpose, the fourth connecting electrode (ELT4) may have a curved shape. For example, the fourth connecting electrode (ELT4) may have a structure that is bent or curved at the boundary between the area where at least one third light-emitting element (LD3) is arranged and the area where at least one fourth light-emitting element (LD4) is arranged.

[0135] The fifth connecting electrode (ELT5) is disposed on the first region (e.g., the upper region) of the second electrode (ALE2) and the second ends (EP2) of the fourth light-emitting elements (LD4), and can be electrically connected to the second ends (EP2) of the fourth light-emitting elements (LD4).

[0136] The first connection electrode (ELT1), the third connection electrode (ELT3), and / or the fifth connection electrode (ELT5) may be formed of the same conductive layer. The second connection electrode (ELT2) and the fourth connection electrode (ELT4) may be formed of the same conductive layer. For example, as illustrated in FIG. 6, the connection electrodes (ELT) may be formed of a plurality of conductive layers. For example, the first connection electrode (ELT1), the third connection electrode (ELT3), and / or the fifth connection electrode (ELT5) may be formed of a first conductive layer, and the second connection electrode (ELT2) and the fourth connection electrode (ELT4) may be formed of a second conductive layer different from the first conductive layer. As illustrated in FIG. 7, the first to fifth connection electrodes (ELT1, ELT2, ELT3, ELT4, ELT5) may be formed of the same conductive layer.

[0137] In the above-described manner, the light-emitting elements (LD) aligned between the electrodes (ALE) can be electrically connected in a desired shape using the connecting electrodes (ELT). For example, the first light-emitting elements (LD1), the second light-emitting elements (LD2), the third light-emitting elements (LD3), and the fourth light-emitting elements (LD4) can be electrically connected sequentially in series using the connecting electrodes (ELT).

[0138] Hereinafter, the cross-sectional structure of a pixel (PXL) will be described in detail with reference to FIGS. 8 to 11. FIGS. 8 to 11 illustrate a first transistor (M1) among various circuit elements constituting a pixel circuit (PXC of FIG. 5), and when there is no need to distinguish between the first to third transistors (M1, M2, M3), they will be referred to collectively as “transistors (M).” The structure and / or layer-by-layer positions of the transistors (M) are not limited to the embodiments illustrated in FIGS. 8 and 10, and may be variously changed depending on the embodiment.

[0139] Pixels (PXL) according to an embodiment may include circuit elements including transistors (M) arranged on a base layer (BSL) and various types of wires electrically connected thereto. Electrodes (ALE), light-emitting elements (LD), connection electrodes (ELT), a first bank (BNK1), and / or a second bank (BNK2) constituting a light-emitting unit (EMU) may be arranged on the circuit elements.

[0140] The base layer (BSL) constitutes a base member and may be a rigid or flexible substrate or film. For example, the base layer (BSL) may be a rigid substrate made of glass or tempered glass, a flexible substrate (or thin film) made of plastic or metal, or at least one insulating layer. The material and / or properties of the base layer (BSL) are not particularly limited. In an embodiment, the base layer (BSL) may be substantially transparent. Here, substantially transparent may mean that light can be transmitted more than the transmittance. In an embodiment, the base layer (BSL) may be translucent or opaque. The base layer (BSL) may also include a reflective material depending on the embodiment.

[0141] A lower conductive layer (BML) and a first power conductive layer (PL2a) may be disposed on the base layer (BSL). The lower conductive layer (BML) and the first power conductive layer (PL2a) may be disposed on the same layer. For example, the lower conductive layer (BML) and the first power conductive layer (PL2a) may be formed simultaneously in the same process, but this is not necessarily limited thereto. The first power conductive layer (PL2a) may form the second power line (PL2) described with reference to FIG. 5 and the like.

[0142] The lower conductive layer (BML) and the first power conductive layer (PL2a) may be formed as a single layer or multiple layers, each made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), oxides thereof, alloys thereof, or combinations thereof.

[0143] A buffer layer (BFL) may be disposed on the lower conductive layer (BML) and the first power conductive layer (PL2a). The buffer layer (BFL) can prevent diffusion of impurities into the circuit elements. The buffer layer (BFL) may be formed as a single layer, but may also be formed as multiple layers, including at least two layers. When the buffer layer (BFL) is formed as multiple layers, each layer may be formed of the same material or different materials.

[0144] A semiconductor pattern (SCP) may be arranged on the buffer layer (BFL). For example, the semiconductor pattern (SCP) may include a first region contacting a first transistor electrode (TE1), a second region contacting a second transistor electrode (TE2), and a channel region positioned between the first and second regions. In some embodiments, one of the first and second regions may be a source region, and the other of the first and second regions may be a drain region.

[0145] According to an embodiment, the semiconductor pattern (SCP) may be formed of polysilicon, amorphous silicon, an oxide semiconductor, or a combination thereof. The channel region of the semiconductor pattern (SCP) may be an intrinsic semiconductor, that is, a semiconductor pattern that is not doped with impurities, and the first and second regions of the semiconductor pattern (SCP) may each be a semiconductor doped with a predetermined impurity.

[0146] A gate insulating layer (GI) may be disposed on the buffer layer (BFL) and the semiconductor pattern (SCP). For example, the gate insulating layer (GI) may be disposed between the semiconductor pattern (SCP) and the gate electrode (GE). The gate insulating layer (GI) may be disposed between the buffer layer (BFL) and the second power conductive layer (PL2b). The gate insulating layer (GI) may be composed of a single layer or multiple layers, and may include various types of inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx), or a combination thereof.

[0147] A gate electrode (GE) of a transistor (M) and a second power conductive layer (PL2b) may be disposed on a gate insulating layer (GI). The gate electrode (GE) and the second power conductive layer (PL2b) may be disposed on the same layer. For example, the gate electrode (GE) and the second power conductive layer (PL2b) may be formed simultaneously in the same process, but are not necessarily limited thereto. The gate electrode (GE) may be disposed on the gate insulating layer (GI) to overlap with the semiconductor pattern (SCP) in a third direction (Z-axis direction). The second power conductive layer (PL2b) may be disposed on the gate insulating layer (GI) to overlap with the first power conductive layer (PL2a) in a third direction (Z-axis direction). The second power conductive layer (PL2b) may form a second power line (PL2) described with reference to FIG. 5 or the like together with the first power conductive layer (PL2a).

[0148] The gate electrode (GE) and the second power conductive layer (PL2b) may be formed as a single layer or multiple layers each made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), oxides thereof, alloys thereof, or combinations thereof. For example, the gate electrode (GE) and the second power conductive layer (PL2b) may be formed as multiple layers each made of titanium (Ti), copper (Cu), and / or indium tin oxide (ITO) sequentially or repeatedly stacked.

[0149] An interlayer insulating layer (ILD) may be disposed on the gate electrode (GE) and the second power conductive layer (PL2b). For example, the interlayer insulating layer (ILD) may be disposed between the gate electrode (GE) and the first and second transistor electrodes (TE1, TE2). The interlayer insulating layer (ILD) may be disposed between the second power conductive layer (PL2b) and the third power conductive layer (PL2c).

[0150] The interlayer dielectric (ILD) may be composed of a single layer or multiple layers and may include various types of inorganic materials or combinations thereof, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0151] First and second transistor electrodes (TE1, TE2) of a transistor (M) and a third power conductive layer (PL2c) may be disposed on an interlayer insulating layer (ILD). The first and second transistor electrodes (TE1, TE2) and the third power conductive layer (PL2c) may be disposed on the same layer. For example, the first and second transistor electrodes (TE1, TE2) and the third power conductive layer (PL2c) may be formed simultaneously in the same process, but are not necessarily limited thereto.

[0152] The first and second transistor electrodes (TE1, TE2) may be arranged to overlap the semiconductor pattern (SCP) in a third direction (Z-axis direction). The first and second transistor electrodes (TE1, TE2) may be electrically connected to the semiconductor pattern (SCP). For example, the first transistor electrode (TE1) may be electrically connected to a first region of the semiconductor pattern (SCP) through a contact hole penetrating an interlayer insulating layer (ILD). The first transistor electrode (TE1) may be electrically connected to a lower conductive layer (BML) through a contact hole penetrating the interlayer insulating layer (ILD) and a buffer layer (BFL). The second transistor electrode (TE2) may be electrically connected to a second region of the semiconductor pattern (SCP) through a contact hole penetrating the interlayer insulating layer (ILD). According to an embodiment, one of the first and second transistor electrodes (TE1, TE2) may be a source electrode, and the other of the first and second transistor electrodes (TE1, TE2) may be a drain electrode.

[0153] The third power conductive layer (PL2c) may be arranged to overlap the first power conductive layer (PL2a) and / or the second power conductive layer (PL2b) in a third direction (Z-axis direction). The third power conductive layer (PL2c) may be electrically connected to the first power conductive layer (PL2a) and / or the second power conductive layer (PL2b). For example, the third power conductive layer (PL2c) may be electrically connected to the first power conductive layer (PL2a) through a contact hole penetrating the interlayer insulating layer (ILD) and the buffer layer (BFL). The third power conductive layer (PL2c) may be electrically connected to the second power conductive layer (PL2b) through a contact hole penetrating the interlayer insulating layer (ILD). The third power conductive layer (PL2c) can form the second power line (PL2) described with reference to FIG. 5, etc., together with the first power conductive layer (PL2a) and / or the second power conductive layer (PL2b).

[0154] The first and second transistor electrodes (TE1, TE2) and the third power conductive layer (PL2c) can be formed as a single layer or multiple layers made of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), oxides thereof, alloys thereof, or combinations thereof.

[0155] A protective layer (PSV) may be disposed on the first and second transistor electrodes (TE1, TE2) and the third power conductive layer (PL2c). The protective layer (PSV) may be composed of a single layer or multiple layers, and may include various types of inorganic materials or combinations thereof, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0156] A via layer (VIA) may be disposed on the protective layer (PSV). The via layer (VIA) may be formed of an organic material to planarize the lower step. For example, the via layer (VIA) may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylenesulfide resin, or benzocyclobutene (BCB), or a combination thereof. However, it is not necessarily limited thereto, and the via layer (VIA) may include various types of inorganic materials including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0157] Barriers (WL) may be arranged on the via layer (VIA). The barriers (WL) may serve to form steps to facilitate alignment of light-emitting elements (LD) within the light-emitting area (EA).

[0158] The partition walls (WL) may have various shapes depending on the embodiment. In an embodiment, the partition walls (WL) may have a shape that protrudes in a third direction (Z-axis direction) on the base layer (BSL). The partition walls (WL) may be formed to have an inclined surface inclined at an angle (for example, a predetermined or selectable angle) with respect to the base layer (BSL). However, the present invention is not necessarily limited thereto, and the partition walls (WL) may have side walls such as a curved surface or a stepped shape. For example, the partition walls (WL) may have a cross-section such as a semicircle or a semi-ellipse shape.

[0159] The bulkheads (WL) may include at least one organic material and / or inorganic material. For example, the bulkheads (WL) may include organic materials such as acrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylenesulfide resin, benzocyclobutene (BCB), or a combination thereof. However, the bulkheads (WL) are not necessarily limited thereto, and the bulkheads (WL) may include various types of inorganic materials, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0160] Electrodes (ALE) may be arranged on the via layer (VIA) and the barrier ribs (WL). The electrodes (ALE) may at least partially cover the side surfaces and / or upper surfaces of the barrier ribs (WL). The electrodes (ALE) arranged on the upper surfaces of the barrier ribs (WL) may have a shape corresponding to the shape of the barrier ribs (WL). For example, the electrodes (ALE) arranged on the barrier ribs (WL) may include an inclined surface or a curved surface having a shape corresponding to the shape of the barrier ribs (WL). In this case, the barrier ribs (WL) and the electrodes (ALE) may serve as reflective members to reflect light emitted from the light-emitting elements (LD) and guide it toward the front surface of the pixel (PXL), for example, in the third direction (Z-axis direction), so that the light emission efficiency of the display panel (PNL) may be improved.

[0161] The electrodes (ALE) may be arranged so as to be spaced apart from each other. The electrodes (ALE) may be arranged in the same layer. For example, the electrodes (ALE) may be formed simultaneously in the same process, but this is not necessarily limited to this.

[0162] The electrodes (ALE) can receive alignment signals during the alignment step of the light-emitting elements (LD). Accordingly, an electric field is formed between the electrodes (ALE), so that the light-emitting elements (LD) provided to each pixel (PXL) can be aligned between the electrodes (ALE).

[0163] The electrodes (ALE) may include at least one conductive material. For example, the electrodes (ALE) may include at least one conductive material selected from the group consisting of, but not limited to, an alloy including at least one metal selected from the group consisting of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), and the like, or combinations thereof, a conductive oxide selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), and gallium tin oxide (GTO), or a combination thereof, and a conductive polymer selected from the group consisting of PEDOT.

[0164] A first electrode (ALE1) can be electrically connected to a first transistor electrode (TE1) of a transistor (M) through a contact hole penetrating a via layer (VIA) and a protective layer (PSV). A second electrode (ALE2) can be electrically connected to a third power conductive layer (PL2c) through a contact hole penetrating a via layer (VIA) and a protective layer (PSV).

[0165] A first insulating layer (INS1) may be disposed on the electrodes (ALE). The first insulating layer (INS1) may be composed of a single layer or multiple layers, and may include various types of inorganic materials or combinations thereof, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0166] A first bank (BNK1) may be arranged on the first insulating layer (INS1). The first bank (BNK1) may include an opening overlapping the light-emitting area (EA). The opening of the first bank (BNK1) may provide a space in which light-emitting elements (LD) may be provided in a step of supplying the light-emitting elements (LD) to each pixel (PXL). For example, a desired type and / or amount of light-emitting element ink may be supplied to the space defined by the opening of the first bank (BNK1).

[0167] The first bank (BNK1) may include organic materials such as acrylates resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylenesulfide resin, benzocyclobutene (BCB), or a combination thereof. However, the present invention is not limited thereto, and the first bank (BNK1) may include various types of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium oxide (TiOx), or a combination thereof.

[0168] Light-emitting elements (LD) may be arranged between the electrodes (ALE). The light-emitting elements (LD) may be biasedly aligned between the electrodes (ALE). For example, the light-emitting elements (LD) may be biasedly aligned so that the first end (EP1) (or the first semiconductor layer) overlaps the first electrode (ALE1) and the second end (EP2) (or the second semiconductor layer) overlaps the second electrode (ALE2).

[0169] Light-emitting elements (LD) may be provided in the opening of the first bank (BNK1) and arranged between the partition walls (WL). The light-emitting elements (LD) may be prepared in a form dispersed in light-emitting element ink and supplied to each pixel (PXL) through an inkjet printing method or the like. For example, the light-emitting elements (LD) may be dispersed in a volatile solvent and supplied to each pixel (PXL). Then, when an alignment signal is supplied to the electrodes (ALE), an electric field is formed between the electrodes (ALE), so that the light-emitting elements (LD) may be aligned between the electrodes (ALE). After the light-emitting elements (LD) are aligned, the solvent may be evaporated or removed by another method, so that the light-emitting elements (LD) may be stably arranged between the electrodes (ALE).

[0170] A second insulating layer (INS2) may be disposed on the light emitting elements (LD). For example, the second insulating layer (INS2) may be partially provided on the light emitting elements (LD) and may expose first and second ends (EP1, EP2) of the light emitting elements (LD). When the second insulating layer (INS2) is formed on the light emitting elements (LD) after the alignment of the light emitting elements (LD) is completed, the light emitting elements (LD) may be prevented from being displaced from the aligned position.

[0171] The second insulating layer (INS2) may be composed of a single layer or multiple layers, and may include various types of inorganic materials or combinations thereof, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0172] Connection electrodes (ELT) may be arranged on the first and second ends (EP1, EP2) of the light-emitting elements (LD) exposed by the second insulating layer (INS2). The first connection electrode (ELT1) may be arranged (e.g., directly arranged) on the first end (EP1) of the first light-emitting elements (LD1) and may be in contact with the first end (EP1) (or the first semiconductor layer) of the first light-emitting elements (LD1).

[0173] The second connection electrode (ELT2) may be disposed (e.g., directly disposed) on the second end (EP2) (or the second semiconductor layer) of the first light-emitting elements (LD1) so as to be in contact with the second end (EP2) (or the second semiconductor layer) of the first light-emitting elements (LD1). The second connection electrode (ELT2) may be disposed (e.g., directly disposed) on the first end (EP1) (or the first semiconductor layer) of the second light-emitting elements (LD2) so as to be in contact with the first end (EP1) (or the first semiconductor layer) of the second light-emitting elements (LD2). For example, the second connection electrode (ELT2) may electrically connect the second end (EP2) (or the second semiconductor layer) of the first light-emitting elements (LD1) and the first end (EP1) (or the first semiconductor layer) of the second light-emitting elements (LD2).

[0174] Similarly, the third connection electrode (ELT3) may be disposed (e.g., directly disposed) on the second end (EP2) (or the second semiconductor layer) of the second light-emitting elements (LD2) so as to be in contact with the second end (EP2) (or the second semiconductor layer) of the second light-emitting elements (LD2). The third connection electrode (ELT3) may be disposed (e.g., directly disposed) on the first end (EP1) (or the first semiconductor layer) of the third light-emitting elements (LD3) so as to be in contact with the first end (EP1) (or the first semiconductor layer) of the third light-emitting elements (LD3). For example, the third connection electrode (ELT3) may electrically connect the second end (EP2) (or the second semiconductor layer) of the second light-emitting elements (LD2) and the first end (EP1) (or the first semiconductor layer) of the third light-emitting elements (LD3).

[0175] Similarly, the fourth connection electrode (ELT4) may be disposed (e.g., directly disposed) on the second end (EP2) (or the second semiconductor layer) of the third light-emitting elements (LD3) so as to be in contact with the second end (EP2) (or the second semiconductor layer) of the third light-emitting elements (LD3). The fourth connection electrode (ELT4) may be disposed (e.g., directly disposed) on the first end (EP1) (or the first semiconductor layer) of the fourth light-emitting elements (LD4) so ​​as to be in contact with the first end (EP1) (or the first semiconductor layer) of the fourth light-emitting elements (LD4). For example, the fourth connection electrode (ELT4) may electrically connect the second end (EP2) (or the second semiconductor layer) of the third light-emitting elements (LD3) and the first end (EP1) (or the first semiconductor layer) of the fourth light-emitting elements (LD4).

[0176] Similarly, the fifth connecting electrode (ELT5) may be disposed (e.g., directly disposed) on the second end (EP2) (or the second semiconductor layer) of the fourth light-emitting elements (LD4) so ​​as to be in contact with the second end (EP2) (or the second semiconductor layer) of the fourth light-emitting elements (LD4).

[0177] The first connecting electrode (ELT1) can be electrically connected to the first electrode (ALE1) through a contact hole penetrating the first insulating layer (INS1). The fifth connecting electrode (ELT5) can be electrically connected to the second electrode (ALE2) through a contact hole penetrating the first insulating layer (INS1).

[0178] In an embodiment, the connecting electrodes (ELT) may include a plurality of conductive layers. For example, as illustrated in FIGS. 8 and 9, the first connecting electrode (ELT1), the third connecting electrode (ELT3), and the fifth connecting electrode (ELT5) may be disposed on the same layer. The second connecting electrode (ELT2) and the fourth connecting electrode (ELT4) may be disposed on the same layer. The first connecting electrode (ELT1), the third connecting electrode (ELT3), and the fifth connecting electrode (ELT5) may be disposed on the second insulating layer (INS2). A third insulating layer (INS3) may be disposed on the first connecting electrode (ELT1), the third connecting electrode (ELT3), and the fifth connecting electrode (ELT5). The second connecting electrode (ELT2) and the fourth connecting electrode (ELT4) may be disposed on the third insulating layer (INS3).

[0179] In this way, when the third insulating layer (INS3) is placed between the connecting electrodes (ELT) made of different conductive layers, the connecting electrodes (ELT) can be stably separated by the third insulating layer (INS3), so that electrical stability between the first and second ends (EP1, EP2) of the light-emitting elements (LD) can be secured.

[0180] The third insulating layer (INS3) may be composed of a single layer or multiple layers, and may include various types of inorganic materials or combinations thereof, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0181] In an embodiment, the connecting electrodes (ELT) may be formed of the same conductive layer. For example, as illustrated in FIGS. 10 and 11 , the first to fifth connecting electrodes (ELT1, ELT2, ELT3, ELT4, and ELT5) may be disposed on the same layer. For example, the first to fifth connecting electrodes (ELT1, ELT2, ELT3, ELT4, and ELT5) may be formed simultaneously in the same process. In this way, when the connecting electrodes (ELT) are formed simultaneously, the number of masks can be reduced and the manufacturing process can be simplified.

[0182] The connecting electrodes (ELT) can be composed of various transparent conductive materials. For example, the connecting electrodes (ELT) include at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), or a combination thereof, and can be implemented to be substantially transparent or translucent so as to satisfy a light transmittance (e.g., a predetermined or selectable light transmittance). Accordingly, light emitted from the first and second ends (EP1, EP2) of the light emitting elements (LD) can pass through the connecting electrodes (ELT) and be emitted to the outside of the display panel (PNL).

[0183] A second bank (BNK2) may be arranged on the first bank (BNK1). The second bank (BNK2) may be arranged in a non-emitting area (NEA).

[0184] The second bank (BNK2) may include an opening that overlaps the light-emitting area (EA). The opening of the second bank (BNK2) may provide a space in which a color conversion layer, as described below, may be provided. For example, a desired type and / or amount of color conversion layer may be supplied to the space defined by the opening of the second bank (BNK2).

[0185] The second bank (BNK2) may include an organic material such as an acrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylenesulfides resin, or benzocyclobutene (BCB), or a combination thereof. However, the present invention is not necessarily limited thereto, and the second bank (BNK2) may include various types of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium oxide (TiOx), or a combination thereof.

[0186] In some embodiments, the second bank (BNK2) may include at least one light-shielding and / or reflective material, thereby preventing light leakage between adjacent pixels (PXL). For example, the second bank (BNK2) may include at least one black pigment.

[0187] Fig. 12 is a schematic cross-sectional view showing first to third pixels according to an embodiment. Fig. 13 is a schematic cross-sectional view showing a pixel according to an embodiment.

[0188] Fig. 12 illustrates a color conversion layer (CCL), an optical layer (OPL), and / or a color filter layer (CFL). In Fig. 12, for convenience of explanation, a discussion of the configuration excluding the base layer (BSL) and the second bank (BNK2) of Figs. 8 to 11 is omitted. Fig. 13 illustrates in detail the stacked structure of a pixel (PXL) in relation to the color conversion layer (CCL), the optical layer (OPL), and / or the color filter layer (CFL).

[0189] Referring to FIGS. 12 and 13, the second bank (BNK2) is positioned between or at the boundary of the first to third pixels (PXL1, PXL2, PXL3) and may include openings that overlap the first to third pixels (PXL1, PXL2, PXL3), respectively. The openings of the second bank (BNK2) may provide a space in which a color conversion layer (CCL) may be provided.

[0190] A color conversion layer (CCL) may be disposed on the light emitting elements (LD) within the opening of the second bank (BNK2). The color conversion layer (CCL) may include a first color conversion layer (CCL1) disposed in a first pixel (PXL1), a second color conversion layer (CCL2) disposed in a second pixel (PXL2), and a scattering layer (LSL) disposed in a third pixel (PXL3).

[0191] In an embodiment, the first to third pixels (PXL1, PXL2, PXL3) may include light emitting elements (LD) that emit light of the same color. For example, the first to third pixels (PXL1, PXL2, PXL3) may include light emitting elements (LD) that emit light of a third color (or blue). By arranging a color conversion layer (CCL) including color conversion particles on each of the first to third pixels (PXL1, PXL2, PXL3), a full-color image can be displayed.

[0192] The first color conversion layer (CCL1) may include first color conversion particles that convert light of a third color emitted from the light emitting element (LD) into light of a first color. For example, the first color conversion layer (CCL1) may include a plurality of first quantum dots (QD1) dispersed within a matrix material (e.g., a predetermined or selectable matrix material) such as a base resin.

[0193] In an embodiment, when the light-emitting element (LD) is a blue light-emitting element that emits blue light and the first pixel (PXL1) is a red pixel, the first color conversion layer (CCL1) may include a first quantum dot (QD1) that converts the blue light emitted from the blue light-emitting element into red light. The first quantum dot (QD1) may absorb blue light and shift the wavelength according to energy transition to emit red light. When the first pixel (PXL1) is a pixel of a different color, the first color conversion layer (CCL1) may include a first quantum dot (QD1) corresponding to the color of the first pixel (PXL1).

[0194] The second color conversion layer (CCL2) may include second color conversion particles that convert light of a third color emitted from the light emitting element (LD) into light of a second color. For example, the second color conversion layer (CCL2) may include a plurality of second quantum dots (QD2) dispersed within a matrix material (e.g., a predetermined or selectable matrix material) such as a base resin.

[0195] In an embodiment, when the light-emitting element (LD) is a blue light-emitting element that emits blue light and the second pixel (PXL2) is a green pixel, the second color conversion layer (CCL2) may include a second quantum dot (QD2) that converts the blue light emitted from the blue light-emitting element into green light. The second quantum dot (QD2) may absorb blue light and shift the wavelength according to energy transition to emit green light. When the second pixel (PXL2) is a pixel of a different color, the second color conversion layer (CCL2) may include a second quantum dot (QD2) that corresponds to the color of the second pixel (PXL2).

[0196] In an embodiment, by incident blue light having a relatively short wavelength in the visible light range onto the first quantum dot (QD1) and the second quantum dot (QD2), respectively, the absorption coefficients of the first quantum dot (QD1) and the second quantum dot (QD2) can be increased. Accordingly, the efficiency of light emitted from the first pixel (PXL1) and the second pixel (PXL2) can be improved, and excellent color reproducibility can be achieved. By configuring the light-emitting units (EMUs) of the first to third pixels (PXL1, PXL2, PXL3) using light-emitting elements (LD) of the same color (for example, blue light-emitting elements), the manufacturing efficiency of the display device can be increased.

[0197] The scattering layer (LSL) may be provided to efficiently utilize the third color (or blue) light emitted from the light emitting element (LD). For example, when the light emitting element (LD) is a blue light emitting element that emits blue light and the third pixel (PXL3) is a blue pixel, the scattering layer (LSL) may include at least one type of scatterer (SCT) to efficiently utilize the light emitted from the light emitting element (LD). For example, the scatterer (SCT) of the scattering layer (LSL) may include at least one of barium sulfate (BaSO4), calcium carbonate (CaCO3), titanium oxide (TiO2), silicon oxide (SiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and zinc oxide (ZnO). The scatterer (SCT) is not only positioned in the third pixel (PXL3), but may also be optionally included within the first color conversion layer (CCL1) or the second color conversion layer (CCL2). In some embodiments, the scatterer (SCT) may be omitted, making the scattering layer (LSL) transparent.

[0198] A first capping layer (CPL1) may be disposed on the color conversion layer (CCL). The first capping layer (CPL1) may be provided across the first to third pixels (PXL1, PXL2, PXL3). The first capping layer (CPL1) may cover the color conversion layer (CCL). The first capping layer (CPL1) may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion layer (CCL).

[0199] The first capping layer (CPL1) is an inorganic layer and may include silicon nitride (SiNx), aluminum nitride (AlNx), titanium nitride (TiNx), silicon oxide (SiOx), aluminum oxide (AlOx), titanium oxide (TiOx), silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), or a combination thereof.

[0200] An optical layer (OPL) may be disposed on the first capping layer (CPL1). The optical layer (OPL) may serve to improve light extraction efficiency by recycling light provided from the color conversion layer (CCL) through total reflection. To this end, the optical layer (OPL) may have a relatively lower refractive index than the color conversion layer (CCL). For example, the refractive index of the color conversion layer (CCL) may be about 1.6 to about 2.0, and the refractive index of the optical layer (OPL) may be about 1.1 to about 1.3.

[0201] A second capping layer (CPL2) may be disposed on the optical layer (OPL). The second capping layer (CPL2) may be provided across the first to third pixels (PXL1, PXL2, PXL3). The second capping layer (CPL2) may cover the optical layer (OPL). The second capping layer (CPL2) may prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the optical layer (OPL).

[0202] The second capping layer (CPL2) is an inorganic layer and may include silicon nitride (SiNx), aluminum nitride (AlNx), titanium nitride (TiNx), silicon oxide (SiOx), aluminum oxide (AlOx), titanium oxide (TiOx), silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), or a combination thereof.

[0203] A planarization layer (PLL) may be disposed on the second capping layer (CPL2). The planarization layer (PLL) may be provided across the first to third pixels (PXL1, PXL2, PXL3).

[0204] The planarization layer (PLL) may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylenesulfide resin, benzocyclobutene (BCB), or a combination thereof. However, the planarization layer (PLL) is not necessarily limited thereto, and may include various types of inorganic materials or a combination thereof, including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx).

[0205] A color filter layer (CFL) may be arranged on the planarization layer (PLL). The color filter layer (CFL) may include color filters (CF1, CF2, CF3) that correspond to the color of each pixel (PXL). By arranging the color filters (CF1, CF2, CF3) that correspond to the color of each of the first to third pixels (PXL1, PXL2, PXL3), a full-color image can be displayed.

[0206] The color filter layer (CFL) may include a first color filter (CF1) arranged in a first pixel (PXL1) to selectively transmit light emitted from the first pixel (PXL1), a second color filter (CF2) arranged in a second pixel (PXL2) to selectively transmit light emitted from the second pixel (PXL2), and a third color filter (CF3) arranged in a third pixel (PXL3) to selectively transmit light emitted from the third pixel (PXL3).

[0207] In the embodiment, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may be a red color filter, a green color filter, and a blue color filter, respectively, but are not necessarily limited thereto. Hereinafter, when referring to any color filter among the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3), or when referring to two or more types of color filters inclusively, the term "color filter (CF)" or "color filters (CF)" will be used.

[0208] The first color filter (CF1) may overlap the first color conversion layer (CCL1) in the third direction (Z-axis direction). The first color filter (CF1) may include a color filter material that selectively transmits light of the first color (or red). For example, when the first pixel (PXL1) is a red pixel, the first color filter (CF1) may include a red color filter material.

[0209] The second color filter (CF2) may overlap with the second color conversion layer (CCL2) in the third direction (Z-axis direction). The second color filter (CF2) may include a color filter material that selectively transmits light of a second color (or green). For example, when the second pixel (PXL2) is a green pixel, the second color filter (CF2) may include a green color filter material.

[0210] The third color filter (CF3) may overlap the scattering layer (LSL) in a third direction (Z-axis direction). The third color filter (CF3) may include a color filter material that selectively transmits light of a third color (or blue). For example, when the third pixel (PXL3) is a blue pixel, the third color filter (CF3) may include a blue color filter material.

[0211] According to an embodiment, a light-blocking layer (BM) may be further disposed between the first to third color filters (CF1, CF2, CF3). In this way, when the light-blocking layer (BM) is formed between the first to third color filters (CF1, CF2, CF3), color mixing defects that are visible from the front or side of the display device can be prevented. The material of the light-blocking layer (BM) is not particularly limited and may be composed of various light-blocking materials. For example, the light-blocking layer (BM) may be implemented by stacking the first to third color filters (CF1, CF2, CF3) on each other.

[0212] An overcoat layer (OC) may be disposed on the color filter layer (CFL). The overcoat layer (OC) may be provided across the first to third pixels (PXL1, PXL2, PXL3). The overcoat layer (OC) may cover the lower member including the color filter layer (CFL). The overcoat layer (OC) may prevent moisture or air from penetrating into the lower member of the overcoat layer (OC). The overcoat layer (OC) may protect the above-described lower member from foreign substances such as dust.

[0213] The overcoat layer (OC) may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylenesulfide resin, benzocyclobutene (BCB), or a combination thereof. However, the overcoat layer (OC) is not necessarily limited thereto, and may include various types of inorganic materials including silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0214] Those skilled in the art will appreciate that the present invention can be implemented in modified forms without departing from the essential characteristics of the above-described description. Therefore, the disclosed methods should be considered illustrative rather than restrictive. The scope of the present invention is set forth in the claims, not the foregoing description, and all differences within the scope equivalent thereto should be construed as being encompassed by the present invention.

Claims

1. First semiconductor layer; A second semiconductor layer disposed on the first semiconductor layer; An active layer disposed between the first semiconductor layer and the second semiconductor layer; A first insulating film at least partially surrounding the first semiconductor layer, the second semiconductor layer, and the active layer; A second insulating film surrounding the first insulating film; and A third insulating film is included surrounding the second insulating film, A light emitting element wherein the bond dissociation energy of the second insulating film is smaller than each of the bond dissociation energy of the first insulating film and the bond dissociation energy of the third insulating film.

2. In paragraph 1, A light emitting device wherein the bond dissociation energy of the first insulating film is about 7.0 eV to about 9.0 eV.

3. In paragraph 1, A light emitting device wherein the bond dissociation energy of the second insulating film is about 6.0 eV to about 8.5 eV.

4. In paragraph 1, A light emitting device wherein the bond dissociation energy of the third insulating film is about 7.0 eV to about 9.0 eV.

5. In paragraph 1, A light-emitting element wherein the first insulating film and the third insulating film contain the same material.

6. In paragraph 1, A light emitting element wherein the thickness of the first insulating film is thicker than the thickness of the second insulating film.

7. In paragraph 6, A light emitting element wherein the thickness of the first insulating film is about 1 nm to about 5 nm, and the thickness of the second insulating film is about 1 nm to about 3 nm.

8. In paragraph 1, A light emitting element in which the thickness of the third insulating film is thicker than that of the second insulating film.

9. In paragraph 8, A light emitting element wherein the thickness of the third insulating film is about 1 nm to about 5 nm, and the thickness of the second insulating film is about 1 nm to about 3 nm.

10. In paragraph 1, A light emitting element further comprising a fourth insulating film surrounding the third insulating film.

11. A plurality of electrodes spaced apart from each other; and It comprises a plurality of light-emitting elements arranged between the plurality of electrodes, Each of the above plurality of light-emitting elements is, First semiconductor layer; A second semiconductor layer disposed on the first semiconductor layer; An active layer disposed between the first semiconductor layer and the second semiconductor layer; A first insulating film at least partially surrounding the first semiconductor layer, the second semiconductor layer, and the active layer; A second insulating film surrounding the first insulating film; and A third insulating film is included surrounding the second insulating film, A display device wherein the bond dissociation energy of the second insulating film is smaller than the bond dissociation energy of the first insulating film and the bond dissociation energy of the third insulating film, respectively.

12. In paragraph 11, A display device wherein the bond dissociation energy of the first insulating film is about 7.0 eV to about 9.0 eV.

13. In paragraph 11, A display device wherein the bond dissociation energy of the second insulating film is about 6.0 eV to about 8.5 eV.

14. In paragraph 11, A display device wherein the bond dissociation energy of the third insulating film is about 7.0 eV to about 9.0 eV.

15. In paragraph 11, A display device wherein the first insulating film and the third insulating film contain the same material.

16. In paragraph 11, A display device wherein the thickness of the first insulating film is thicker than the thickness of the second insulating film.

17. In paragraph 16, A display device wherein the thickness of the first insulating film is about 1 nm to about 5 nm, and the thickness of the second insulating film is about 1 nm to about 3 nm.

18. In paragraph 11, A display device in which the thickness of the third insulating film is thicker than the thickness of the second insulating film.

19. In paragraph 18, A display device wherein the thickness of the third insulating film is about 1 nm to about 5 nm, and the thickness of the second insulating film is 1 nm to 3 nm.

20. In paragraph 11, A display device further comprising connecting electrodes arranged on the plurality of light-emitting elements and electrically connected to the plurality of light-emitting elements.

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