Base graph-based parallel LDPC decoding method and apparatus, device, and medium

Abstract

A base graph-based parallel LDPC decoding method and apparatus, a device, and a medium. The method comprises: in response to a decoding request for target data, on the basis of a preset instruction set, generating an LDPC decoding code adapted to the current processor (S110); on the basis of an expansion factor corresponding to the decoding request, determining a target subgraph corresponding to a base graph, and generating a check matrix matching the target subgraph (S120); performing grouping on the check matrix by row according to a preset grouping rule, and obtaining decoding block sequences by division on the basis of the expansion factor (S130); and executing the LDPC decoding code, and on the basis of the decoding block sequences, performing, in parallel, loop iteration and update on check nodes in a tanner graph obtained by transforming the check matrix, so as to obtain a decoding result of the target data (S140).

Description

Parallel LDPC decoding method, device, equipment and medium based on basic graph

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 10, 2023, with application number 202311008816.4. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of data processing technology, for example, to a parallel LDPC decoding method, apparatus, device and medium based on a basic graph. Background Art

[0003] Low-Density Parity-Check (LDPC) codes are essentially a type of linear block code used to correct errors that occur during transmission. The error correction capability of LDPC codes is very close to the Shannon limit.

[0004] Although LDPC codes have great advantages in performance, the decoding implementation method of LDPC codes is highly complex and requires a large number of nodes, resulting in high cost and difficulty in hardware circuit implementation.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a parallel LDPC decoding method, apparatus, device, and medium based on a basic graph, and propose a method for implementing LDPC decoding by combining software and hardware. Code development is relatively flexible and low-cost. Combined with a hierarchically scheduled node update method, efficient and high-performance LDPC decoding is achieved.

[0007] This application provides a parallel LDPC decoding method based on a basic graph, including:

[0008] In response to a decoding request for target data, generating an LDPC decoding code adapted to the current processor according to a preset instruction set;

[0009] Determining a target subgraph corresponding to a basic graph according to an expansion factor corresponding to the decoding request, and generating a check matrix matching the target subgraph;

[0010] Grouping the check matrix by row according to a preset grouping rule, and dividing the decoding group sequence according to the expansion factor;

[0011] The LDPC decoding code is executed, and according to the decoding group sequence, the check nodes in the Tanner graph converted from the check matrix are updated in parallel in a cyclic iterative manner to obtain an LDPC decoding result of the target data.

[0012] The present application provides a parallel LDPC decoding device based on a basic graph, comprising:

[0013] a decoding code acquisition module configured to generate an LDPC decoding code adapted to the current processor according to a preset instruction set in response to a decoding request for target data;

[0014] a check matrix generation module configured to determine a target subgraph corresponding to a basic graph according to an expansion factor corresponding to the decoding request, and to generate a check matrix matching the target subgraph;

[0015] a matrix grouping module, configured to group the check matrix by row according to a preset grouping rule, and divide the decoding group sequence according to the expansion factor;

[0016] The node update module is configured to execute the LDPC decoding code, and in parallel, perform cyclic iterative updates on the check nodes in the Tanner graph converted from the check matrix according to the decoding group sequence to obtain the LDPC decoding result of the target data.

[0017] The present application provides an electronic device, comprising:

[0018] at least one processor; and

[0019] a memory communicatively coupled to the at least one processor;

[0020] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the parallel LDPC decoding method based on the basic graph described in any embodiment of the present application.

[0021] The present application provides a computer-readable storage medium storing computer instructions, which are used to enable a processor to implement the basic graph-based parallel LDPC decoding method described in any embodiment of the present application when executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a flowchart of a parallel LDPC decoding method based on a basic graph provided according to Embodiment 1 of the present application;

[0023] FIG2 is a schematic diagram of a check matrix obtained by expanding a basic graph according to the first embodiment of the present application;

[0024] FIG3 is a schematic diagram of a check matrix grouped by rows according to the first embodiment of the present application;

[0025] FIG4 is a schematic diagram of a Tanner graph provided according to Example 1 of the present application;

[0026] FIG5 is a flowchart of another parallel LDPC decoding method based on a basic graph provided in accordance with the second embodiment of the present application;

[0027] FIG6 is a schematic structural diagram of a parallel LDPC decoding device based on a basic graph according to Embodiment 3 of the present application;

[0028] FIG7 is a schematic diagram of the structure of an electronic device for implementing the basic graph-based parallel LDPC decoding method according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] The terms "target", "first", "second" etc. of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprise" and "comprising" and any of their variations are intended to cover non-exclusive inclusions, for example, in addition to comprising the process, method, system, product or equipment of a series of steps or units shown in the embodiments of the present application, other processes, methods, systems, products or equipment of this series of steps or units not clearly listed may also be included, or other steps or units inherent to these processes, methods, systems, products or equipment.

[0030] Example 1

[0031] FIG1 is a flowchart of a parallel LDPC decoding method based on a basic graph according to the first embodiment of the present application. This embodiment is applicable to the case where efficient LDPC decoding is performed on the data to be decoded by combining software and hardware. The method can be performed by a parallel LDPC decoding device based on a basic graph. The device can be implemented in the form of hardware and / or software and can be configured in an electronic device. As shown in FIG1 , the method includes:

[0032] S110 , in response to a decoding request for target data, generating an LDPC decoding code adapted to the current processor according to a preset instruction set.

[0033] The target data may be data received by the device and to be subjected to LDPC decoding. The preset instruction set is an instruction set designed for an optimized parallel LDPC decoding algorithm using a specified vector processor.

[0034] Optionally, in response to a decoding request for target data, generating an LDPC decoding code adapted to the current processor according to a preset instruction set, includes: in response to a decoding request for target data, obtaining decoding instructions adapted to the current processor from a preset instruction set generated based on a vector processor; and converting a pre-written high-level language decoding code into an LDPC decoding code adapted to the current processor according to the decoding instructions.

[0035] In this embodiment, a corresponding decoding code is pre-written in a high-level coding language for the optimized basic graph-based parallel LDPC decoding algorithm, i.e., a high-level language decoding code. Upon receiving a decoding request for target data, a decoding instruction compatible with the current processor in the device is retrieved from a preset instruction set. The high-level language decoding code is then converted using this decoding instruction into an LDPC decoding code executable by the current processor, which may be a vector processor.

[0036] S120 : Determine a target subgraph corresponding to the basic graph according to the expansion factor corresponding to the decoding request, and generate a check matrix matching the target subgraph.

[0037] The parity check matrix (PCM) is obtained by expanding the base graph (BG) using an expansion factor. The PCM is determined based on the target subgraph corresponding to the expansion factor. Depending on the setting, the target subgraph can be a subgraph of base graph 1 (BG1) or a subgraph of base graph 2 (BG2). BG1 and BG2 are each divided into 8 subgraphs, but for a specific decoder, the base graph is a fixed graph. When the base graph is set to BG1, the target subgraph is a subgraph of BG1 determined by the expansion factor; when the base graph is set to BG2, the target subgraph is a subgraph of BG2 determined by the expansion factor.

[0038] The LDPC codes involved in this embodiment are actually Quasi-Cyslic Low-Density Parity-Check Codes (QC-LDPC). The parity check matrix of a QC-LDPC code is obtained by expanding each element in the basic graph (BG) into a unit matrix and performing specific cyclic shifts. Both the encoding and decoding processes of the QC-LDPC code are completed through operations based on the parity check matrix. PCM can be represented using two basic graph subgraphs: the BG1 subgraph and the BG2 subgraph. This embodiment uses the BG1 subgraph as an example to represent PCM, i.e., the parity check matrix.

[0039] Optionally, determining the target subgraph corresponding to the basic graph based on the expansion factor corresponding to the decoding request and generating a check matrix matching the target subgraph includes: obtaining the expansion factor corresponding to the decoding request; querying a mapping relationship table between preset expansion factors and subgraphs of the basic graph to obtain the target subgraph matching the expansion factor; and expanding each element in the target subgraph by a multiple of the expansion factor to obtain a check matrix.

[0040] In this embodiment, taking BG1 as an example, considering that BG1 is divided into 8 different sub-graphs, and these BG1 sub-graphs support a total of 51 different expansion factors, therefore, in order to facilitate the query of the BG1 sub-graph corresponding to the specified expansion factor, the mapping relationship table between the expansion factor and the BG1 sub-graph can be queried in advance.

[0041] Table 1

[0042] It is understandable that since BG2 is also divided into 8 different subgraphs, and these BG2 subgraphs also support multiple different expansion factors, you can refer to Table 1 to pre-establish a mapping relationship table between the expansion factor and the BG2 subgraph to facilitate the query of the BG2 subgraph corresponding to the specified expansion factor.

[0043] After receiving a decoding request for the target data, the expansion factor Z set by the user for this decoding is obtained, for example, the expansion factor Z is extracted from the decoding request. Then, according to whether the set basic graph is BG1 or BG2, the expansion factor Z is used to query the mapping relationship table between the corresponding expansion factor and the basic graph subgraph, and the target subgraph that matches the expansion factor Z is found. Each element in the target subgraph is expanded by Z times so that each element becomes a Z×Z cyclic shift matrix, and the corresponding PCM (parity check matrix) is obtained. For example, as shown in Figure 2, assuming that the target subgraph Hb includes 3 rows * 6 columns of elements, and the expansion factor Z is equal to 6, then the check matrix obtained by expanding Hb(3*6) by Z=6 is H[3*6][6*6], that is, each element becomes a 6×6 cyclic shift matrix.

[0044] S130: Group the check matrix by row according to a preset grouping rule, and divide the decoding group sequence according to the expansion factor.

[0045] In this embodiment, as can be seen from Table 1, the range of the expansion factor is [2,384]. That is, each row in the target subgraph is expanded to a matrix with a maximum of 384 rows. Due to the processing bit width limitation of the processor, it is impossible to load and process a maximum of 384 soft bits at a time. Therefore, after obtaining the check matrix, it is necessary to group the check matrix by row to reduce the data processing pressure of the processor.

[0046] Optionally, grouping the check matrix by row according to a preset grouping rule and dividing the decoding group sequence according to the expansion factor includes: obtaining a grouping granularity; the grouping granularity represents the number of data rows included in each data group; taking each expansion factor row data in the check matrix as a unit, and grouping each unit according to the grouping granularity; and adding all data groups corresponding to the same unit to the corresponding decoding group sequence in ascending order of row number.

[0047] In this embodiment, a pre-defined grouping granularity can be obtained, or a user-set grouping granularity can be obtained in real time. As shown in Figure 3, since each Z row in the check matrix H corresponds to a row in the target subgraph, each Z row of data in the check matrix can be regarded as a whole, called a unit, and each unit is grouped according to the grouping granularity. The number of data groups divided by each unit is equal to the result of rounding up (Z / grouping granularity). For example, assuming Z = 6 and grouping granularity = 2, each Z row in the check matrix H is divided into 3 groups as shown in Figure 3, each group containing 2 rows of data. Then, all data groups corresponding to the same unit are added to a decoding group sequence in order from small to large row numbers. For example, the 1-1 data group, the 1-2 data group, and the 1-3 data group in Figure 3 are sequentially added to the decoding group sequence 1, which facilitates the subsequent execution of the LDPC code and the cyclic iterative update of the data groups in the decoding group sequence in sequence.

[0048] S140 , executing the LDPC decoding code, and performing cyclic iterative updates on the check nodes in the Tanner graph (bipartite graph) converted from the check matrix in parallel according to the decoding group sequence, to obtain an LDPC decoding result of the target data.

[0049] In this embodiment, in order to perform iterative decoding using the Normalized Min Sum-Belief Propagation (NMS-BP) algorithm, the check matrix needs to be converted into a Tanner graph. The Tanner graph includes two types of nodes: variable nodes and check nodes. As shown in Figure 4, each variable node c1-c6 corresponds to a column of the check matrix, corresponding to each code bit of the error correction code; each check node s1-s3 corresponds to a row of the check matrix, responsible for receiving and processing data, and outputting a result. During the iteration process, the reliability message, that is, the corresponding target data received by each variable node, is passed back and forth between the variable nodes and the check nodes via the edges on the Tanner graph. After multiple iterations, it tends to a stable value, and then the optimal decision is made based on this value to obtain the LDPC decoding result of the target data.

[0050] In this embodiment, due to the execution delay problem of LDPC instructions, in order to improve the decoding efficiency as much as possible, every two data groups are used as a loop during the decoding implementation process to save as much invalid time overhead as possible during the iteration process. Based on this loop method, this embodiment proposes two node update methods. One is to divide the number of data groups included in the decoding group sequence into three cases: the number of data groups is 1, the number of data groups is not 1 and is an odd number, and the number of data groups is not 1 and is an even number. A corresponding node loop update process is set for each case; the other is to cyclically update the data groups in each decoding group sequence in sequence, and at the same time, with the help of the instructions provided by the vector processor, set the instruction enable judgment condition for the node update instruction, and enable the next node update instruction in each loop. You can choose one of the methods according to your needs, and cyclically iterate the check nodes in the tanner graph converted from the check matrix to obtain the LDPC decoding result.

[0051] The technical solution of the embodiment of the present application generates an LDPC decoding code adapted to the current processor according to a preset instruction set in response to a decoding request for target data; determines a target subgraph corresponding to a basic graph according to an expansion factor corresponding to the decoding request, and generates a check matrix matching the target subgraph; groups the check matrix by row according to a preset grouping rule, and divides the decoding group sequence according to the expansion factor; executes the LDPC decoding code, and in parallel, iteratively updates the check nodes in the Tanner graph converted from the check matrix according to the decoding group sequence, to obtain the LDPC decoding result of the target data. The technical solution of the embodiment of the present application proposes a method of realizing LDPC decoding by combining software and hardware. The code development is relatively flexible, the hardware circuit implementation cost is low, and the difficulty is relatively low. Combined with the node update method of hierarchical scheduling, efficient and high-performance LDPC decoding is realized.

[0052] Example 2

[0053] FIG5 is a flowchart of another parallel LDPC decoding method based on a basic graph according to the second embodiment of the present application, which provides two implementation steps: executing the LDPC decoding code, and in parallel, iteratively updating the check nodes in the Tanner graph converted from the check matrix according to the decoding group sequence, to obtain the LDPC decoding result of the target data. As shown in FIG5, the method includes:

[0054] S510 : In response to a decoding request for target data, generate an LDPC decoding code adapted to the current processor according to a preset instruction set.

[0055] S520: Determine a target subgraph corresponding to the basic graph according to the expansion factor corresponding to the decoding request, and generate a check matrix matching the target subgraph.

[0056] S530: Group the check matrix by row according to a preset grouping rule, and divide the decoding group sequence according to the expansion factor.

[0057] S540 , executing the LDPC decoding code, and performing cyclic iterative updates on the check nodes in the Tanner graph converted from the check matrix in parallel according to the decoding group sequence, to obtain an LDPC decoding result of the target data.

[0058] In an optional embodiment, the LDPC decoding code is executed, and for each decoding group sequence, two data groups to be updated are sequentially obtained from the decoding group sequence in each cycle as the current processing group; wherein, if there is only one data group to be updated in the decoding group sequence, the data group is used as the current processing group; in the Tanner graph converted from the check matrix, calculation update operations are performed in parallel on the check nodes corresponding to the current processing group in each decoding group sequence; completing a calculation update operation for all data groups in all decoding group sequences is regarded as an iterative update, and by performing multiple iterative updates on the check nodes in the Tanner graph, the check node update results that meet the preset conditions are used as the LDPC decoding results of the target data.

[0059] In this embodiment, when the check nodes in the Tanner graph are updated in parallel according to the decoding group sequence, the number q of data groups included in each decoding group sequence can be divided into three cases: q is 1, q is not 1 and q is an odd number, and q is not 1 and q is an even number. A corresponding node cyclic update process is set for each case:

[0060] 1) When q = 1, meaning each decoded block sequence contains only one data group, each loop executes a computational update operation by extracting a single data group from the decoded block sequence as the current processing group. In this case, the computational code does not need to be called repeatedly within the LDPC decoding code. Each execution of one group completes the node update corresponding to a row of the check matrix. A computational update is performed on one data group in each decoded block sequence, completing a traversal of all rows of the check matrix and completing one iteration. The code segment size for this iteration is denoted as codesize1. The pseudocode corresponding to the node update for the i-th row of the check matrix is: soft bit loading + node update.

[0061] 2) When q is not 1 and q is an odd number, each loop sequentially obtains two data groups from the decoding packet sequence as the current processing group and performs a calculation update operation. When there is only one unupdated data group left in the sequence, the loop ends, and the data group is used as the current processing group to continue the calculation update operation. In this case, for each decoding packet sequence, the LDPC decoding code completes the node update of 2 data groups in the sequence in each loop, and the loop is executed (q-1) / 2 times, and an additional node update of one data group is performed outside the loop to complete the traversal update of all data groups in a decoding packet sequence. If a calculation update operation is completed for all data groups in each decoding packet sequence in parallel, the traversal of all rows of the check matrix is ​​completed, that is, an iteration is completed. The code segment size of the iterative process in this case is denoted as codesize2, then codesize2≈codesize1*3. The pseudo code corresponding to the update of the node in the i-th row of the check matrix is:

[0062] Where j is the group number of the data group:

[0063] Update of the qth group of nodes

[0064] 3) When q is not 1 and q is an even number, each loop sequentially obtains two data groups from the decoding group sequence as the current processing group and performs a calculation update operation. In this case, for each decoding group sequence, the LDPC decoding code completes the node update of two data groups in the sequence in each loop. The loop is executed q / 2 times to complete the traversal update of all data groups in a decoding group sequence. If a calculation update operation is completed once for all data groups in each decoding group sequence in parallel, the traversal of all rows of the check matrix is ​​completed, that is, an iteration is completed. The code segment size of the iterative process in this case is denoted as codesize3, then codesize3≈codesize1*2. The pseudo code corresponding to the update of the node in the i-th row of the check matrix is:

[0065] Where j is the group number of the data group:

[0066] In this embodiment, this node update method maximizes the compression of the execution time of the iterative process during decoding. The total length of the code segments required for the iterative process is approximately codesize_seperate ≈ codesize1 * 6. In some cases, the codesize_seperate of this method may be considered too large, making it difficult to allocate memory properly, thus proposing a need to compress the code segments.

[0067] To further compress the code segments, this embodiment proposes another node update method, namely, sequentially updating the data groups in each decoding group sequence in a loop. Simultaneously, with the help of instructions provided by the vector processor, instruction enable determination conditions are set for the node update instructions, and an enable determination is performed on the last node update instruction in each loop, thereby flexibly controlling the update of the data groups in each loop under different q values.

[0068] In another optional embodiment, the LDPC decoding code is executed to determine the total number of data groups contained in each of the decoding group sequences; the ratio of the total number of data groups to 2 is rounded up to obtain the total number of cycles M contained in one iteration of each of the decoding group sequences; for the j-th cycle, j<=M, in the tanner graph converted from the check matrix, the check nodes corresponding to the j*2-1-th data group in each of the decoding group sequences are calculated and updated in parallel, and when j meets the instruction enable judgment condition, the check nodes corresponding to the j*2-th data group in each of the decoding group sequences are calculated and updated in parallel; the calculation update operation of completing M cycles of all decoding group sequences is regarded as one iterative update, and by performing multiple iterative updates on the check nodes in the tanner graph, the check node update results that meet the preset conditions are used as the LDPC decoding results of the target data.

[0069] For this node update method, since each iteration sequentially acquires two data groups from the decoding block sequence for node update, when the total number of data groups q in the decoding block sequence is an odd number, one data group will remain unupdated. To ensure that all data groups in the decoding block sequence can be updated, the ratio of the total number of data groups q to 2 is rounded up to the nearest integer, representing the total number of iterations for each decoding block sequence. For each decoding block sequence, when q is an odd number, the LDPC decoding code completes node updates for two data groups in each iteration, executing ceil(q / 2) times. The node update instruction for the last group (i.e., the q+1th data group) in the final iteration is disabled. When q is an even number, the LDPC decoding code completes node updates for two data groups in each iteration, executing q / 2 times in total, with all code enabled during the iterations. If the update operation is completed for all data groups in each decoding block sequence in parallel, all rows of the parity check matrix are traversed, completing one iteration. The code size of the iterative process in this case is recorded as codesize_combine, then codesize_combine≈codesize1*2. The pseudo code corresponding to the update of the node in the i-th row of the check matrix is:

[0070] Where j is the group number of the data group:

[0071] Optionally, determining whether j satisfies the instruction enable determination condition includes: when the total number of data groups contained in the decoding group sequence is an even number, any value of j less than or equal to M satisfies the instruction enable determination condition; when the total number of data groups contained in the decoding group sequence is an odd number, then when j is equal to M, the instruction enable determination condition is not satisfied, and when j is less than M, the instruction enable determination condition is satisfied.

[0072] In this embodiment, when the total number q of data groups included in the decoded packet sequence is an even number, M = q / 2. At this point, after q / 2 cycles, a calculation update operation is completed for all data groups in the sequence. Therefore, when j takes any value between 1 and M, the second set of node update instructions in the cycle is enabled. When q is an odd number, M = ceil(q / 2). At this time, for the last cycle, that is, when j = M, since the cycle actually includes only one data group and there is no q+1th data group, the second set of node update instructions in the cycle is not enabled.

[0073] In this embodiment, the second node update method gives full play to the instruction function of the algebraic processor (Mathematics Processing Unit, MaPU) (vector processor), and uses smaller code to implement all decoding functions corresponding to BG1. The size of the optimized decoding iteration code segment is approximately codesize_combine≈codesize1*2. Compared with the first node update scheme of splitting different q values, the iterative part code saves about 67%, and the total code segment saving ratio is close to this, which reduces the memory planning work. According to actual tests, compared with splitting according to different q values, the total execution time of the decoding program that supports all Z values ​​has no obvious increase.

[0074] The technical solution of the embodiment of the present application generates an LDPC decoding code adapted to the current processor according to a preset instruction set in response to a decoding request for target data; determines the target subgraph corresponding to the basic graph according to the expansion factor corresponding to the decoding request, and generates a check matrix matching the target subgraph; groups the check matrix by row according to a preset grouping rule, and divides the decoding group sequence according to the expansion factor; executes the LDPC decoding code, and in parallel, iteratively updates the check nodes in the tanner graph converted from the check matrix according to the decoding group sequence, to obtain the LDPC decoding result of the target data. The technical solution of the embodiment of the present application proposes a method of realizing LDPC decoding by combining software and hardware, which is more flexible in code development, low in hardware circuit implementation cost, and relatively low in difficulty. Combined with the node update method of hierarchical scheduling, efficient and high-performance LDPC decoding is achieved.

[0075] Example 3

[0076] FIG6 is a schematic diagram of the structure of a parallel LDPC decoding device based on a basic graph according to the third embodiment of the present application. As shown in FIG6, the device includes: a decoding code acquisition module 610, configured to generate an LDPC decoding code adapted to the current processor according to a preset instruction set in response to a decoding request for target data; a check matrix generation module 620, configured to determine a target subgraph corresponding to the basic graph according to an expansion factor corresponding to the decoding request, and generate a check matrix matching the target subgraph; a matrix grouping module 630, configured to group the check matrix by row according to a preset grouping rule, and divide the decoding group sequence according to the expansion factor; and a node update module 640, configured to execute the LDPC decoding code and, in parallel, perform cyclic iterative updates on the check nodes in the Tanner graph converted from the check matrix according to the decoding group sequence to obtain the LDPC decoding result of the target data.

[0077] The technical solution of the embodiment of the present application generates an LDPC decoding code adapted to the current processor according to a preset instruction set in response to a decoding request for target data; determines a target subgraph corresponding to a basic graph according to an expansion factor corresponding to the decoding request, and generates a check matrix matching the target subgraph; groups the check matrix by row according to a preset grouping rule, and divides the decoding group sequence according to the expansion factor; executes the LDPC decoding code, and in parallel, iteratively updates the check nodes in the Tanner graph converted from the check matrix according to the decoding group sequence, to obtain the LDPC decoding result of the target data. The technical solution of the embodiment of the present application proposes a method of realizing LDPC decoding by combining software and hardware. The code development is relatively flexible, the hardware circuit implementation cost is low, and the difficulty is relatively low. Combined with the node update method of hierarchical scheduling, efficient and high-performance LDPC decoding is realized.

[0078] Optionally, the decoding code acquisition module 610 is configured to: in response to a decoding request for target data, obtain decoding instructions adapted to the current processor from a preset instruction set generated based on a vector processor; and convert a pre-written high-level language decoding code into an LDPC decoding code adapted to the current processor according to the decoding instructions.

[0079] Optionally, the check matrix generation module 620 is configured to: obtain an expansion factor corresponding to the decoding request; query a mapping relationship table between a preset expansion factor and a subgraph of a basic graph to obtain a target subgraph that matches the expansion factor; and expand each element in the target subgraph by a multiple of the expansion factor to obtain a check matrix.

[0080] Optionally, the matrix grouping module 630 is configured to: obtain a grouping granularity; the grouping granularity represents the number of data rows included in each data group; take each expansion factor row data in the check matrix as a unit, and group each unit according to the grouping granularity; and add all data groups corresponding to the same unit to the corresponding decoding group sequence in order of row numbers from small to large.

[0081] Optionally, the node update module 640 includes: a first update unit, configured to execute the LDPC decoding code, and for each decoding group sequence, sequentially obtaining two data groups to be updated from the decoding group sequence in each cycle as the current processing group; wherein, when there is only one data group to be updated in the decoding group sequence, the data group is used as the current processing group; in the Tanner graph converted from the check matrix, a calculation update operation is performed in parallel on the check nodes corresponding to the current processing group in each decoding group sequence; completing a calculation update operation on all data groups in all decoding group sequences is regarded as an iterative update, and by performing multiple iterative updates on the check nodes in the Tanner graph, the check node update results that meet the preset conditions are used as the LDPC decoding results of the target data.

[0082] Optionally, the node update module 640 includes: a second update unit, configured to execute the LDPC decoding code to determine the total number of data groups contained in each of the decoding group sequences; rounding up the ratio of the total number of data groups to 2 to obtain the total number of cycles M contained in one iteration of each of the decoding group sequences; for the j-th cycle, j<=M, in the tanner graph converted from the check matrix, performing calculation update operations on the check nodes corresponding to the j*2-1-th data group in each decoding group sequence in parallel, and when j meets the instruction enable judgment condition, performing calculation update operations on the check nodes corresponding to the j*2-th data group in each decoding group sequence in parallel; the calculation update operations of completing M cycles of all decoding group sequences are regarded as one iterative update, and by performing multiple iterative updates on the check nodes in the tanner graph, the check node update results that meet the preset conditions are used as the LDPC decoding results of the target data.

[0083] Optionally, the second update unit is configured to determine whether j meets the instruction enable determination condition in the following manner: when the total number of data groups included in the decoding group sequence is an even number and j is less than or equal to M, it is determined that j meets the instruction enable determination condition; when the total number of data groups included in the decoding group sequence is an odd number and j is equal to M, it is determined that j does not meet the instruction enable determination condition; when j is less than M, it is determined that j meets the instruction enable determination condition.

[0084] The basic graph-based parallel LDPC decoding device provided in the embodiments of the present application can execute the basic graph-based parallel LDPC decoding method provided in any embodiment of the present application, and has the corresponding functional modules and effects of the execution method.

[0085] Example 4

[0086] FIG7 shows a block diagram of an electronic device 10 that can be used to implement an embodiment of the present application. The electronic device can be various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or required herein.

[0087] As shown in FIG7 , the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 and a random access memory (RAM) 13, that is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the ROM 12 or the computer program loaded from the storage unit 18 into the RAM 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0088] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0089] The processor 11 can be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the parallel LDPC decoding method based on the basic graph.

[0090] In some embodiments, the parallel LDPC decoding method based on the basic graph can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the parallel LDPC decoding method based on the basic graph described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the parallel LDPC decoding method based on the basic graph by any other appropriate means (e.g., by means of firmware).

[0091] Various implementations of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0092] Computer programs for implementing the methods of the present application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0093] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. A machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0094] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD) monitor) configured to display information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be configured to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0095] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0096] A computing system may include a client and a server. The client and server are generally remote from each other and typically interact via a communication network. The client-server relationship arises through computer programs running on the respective computers and establishing a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, a host product within a cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosts and virtual private server (VPS) services.

Claims

1. A parallel LDPC decoding method based on a basic graph, comprising: In response to a decoding request for target data, a low-density parity check (LDPC) decoding code adapted to a current processor is generated according to a preset instruction set; Determine a target subgraph corresponding to a basic graph according to an extension factor corresponding to the decoding request, and generate a check matrix matching the target subgraph; Grouping the check matrix by rows according to a preset grouping rule, and dividing the decoding group sequence according to the expansion factor; The LDPC decoding code is executed, and according to the decoding group sequence, the check nodes in the Tanner graph converted from the check matrix are updated in parallel in a cyclic iterative manner to obtain the LDPC decoding result of the target data.

2. The method according to claim 1, wherein: The step of generating, in response to a decoding request for target data, an LDPC decoding code adapted to a current processor according to a preset instruction set comprises: In response to a decoding request for target data, a decoding instruction adapted to the current processor is obtained from a preset instruction set generated based on a vector processor; According to the decoding instruction, the pre-written high-level language decoding code is converted into an LDPC decoding code adapted to the current processor.

3. The method according to claim 1, wherein: The step of determining a target subgraph corresponding to a basic graph according to an extension factor corresponding to the decoding request, and generating a check matrix matching the target subgraph, comprises: Obtaining an expansion factor corresponding to the decoding request; Querying a mapping relationship table between a preset expansion factor and a subgraph of a basic graph, and obtaining a target subgraph matching the expansion factor; Each element in the target subgraph is expanded by a multiple of the expansion factor to obtain a check matrix.

4. The method according to claim 1, wherein: The step of grouping the check matrix by rows according to a preset grouping rule and dividing the decoding group sequence according to the expansion factor includes: Acquire a grouping granularity; the grouping granularity indicates the number of data rows included in each data group; Taking each row of extension factor data in the check matrix as a unit, and grouping each unit according to the grouping granularity; All data groups corresponding to the same unit are added to the corresponding decoding group sequence in order of row numbers from small to large.

5. The method according to claim 4, wherein: The executing the LDPC decoding code, according to the decoding group sequence, and in parallel, cyclically iteratively updating the check nodes in the Tanner graph converted from the check matrix to obtain the LDPC decoding result of the target data, comprises: Executing the LDPC decoding code, for each decoding group sequence, sequentially obtaining two data groups to be updated from the decoding group sequence as current processing groups in each cycle; Wherein, when there is only one data group to be updated in the decoding group sequence, the data group is used as the current processing group; In the Tanner graph converted from the check matrix, performing calculation and updating operations on the check nodes corresponding to the current processing group in each decoding group sequence in parallel; Completing a calculation update operation on all data groups in all decoding group sequences is regarded as an iterative update, and by performing multiple iterative updates on the check nodes in the tanner graph, the update results of the check nodes that meet the preset conditions are used as the LDPC decoding results of the target data.

6. The method according to claim 4, wherein: The executing the LDPC decoding code, according to the decoding group sequence, and in parallel, cyclically iteratively updating the check nodes in the Tanner graph converted from the check matrix to obtain the LDPC decoding result of the target data, comprises: Executing the LDPC decoding code to determine the total number of data groups included in each of the decoding packet sequences; Rounding up the ratio of the total number of data groups to 2 to obtain the total number of cycles M included in one iteration of each decoding packet sequence; For the j-th cycle, j<=M, in the tanner graph converted from the check matrix, the check nodes corresponding to the j*2-1-th data group in each decoding group sequence are calculated and updated in parallel, and when j meets the instruction enable determination condition, the check nodes corresponding to the j*2-th data group in each decoding group sequence are calculated and updated in parallel; The calculation update operation of completing M cycles of all decoding group sequences is regarded as an iterative update, and the check nodes in the tanner graph are iteratively updated multiple times, and the check node update results that meet the preset conditions are used as the LDPC decoding results of the target data.

7. The method according to claim 6, wherein: Determine whether j meets the instruction enable determination conditions, including: When the total number of data groups included in the decoded packet sequence is an even number and j is less than or equal to M, it is determined that j satisfies the instruction enable determination condition; When the total number of data groups included in the decoding packet sequence is an odd number and j is equal to M, it is determined that j does not meet the instruction enable determination condition; when j is less than M, it is determined that j meets the instruction enable determination condition.

8. A parallel LDPC decoding device based on a basic graph, comprising: A decoding code acquisition module, configured to generate an LDPC decoding code adapted to a current processor according to a preset instruction set in response to a decoding request for target data; A check matrix generation module, configured to determine a target subgraph corresponding to a basic graph according to an expansion factor corresponding to the decoding request, and generate a check matrix matching the target subgraph; A matrix grouping module, configured to group the check matrix by row according to a preset grouping rule, and divide the decoding group sequence according to the expansion factor; The node update module is configured to execute the LDPC decoding code, and according to the decoding group sequence, cyclically iteratively update the check nodes in the Tanner graph converted from the check matrix in parallel to obtain the LDPC decoding result of the target data.

9. An electronic device, comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the basic graph-based parallel LDPC decoding method described in any one of claims 1-7.

10. A computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a processor to implement the basic graph-based parallel LDPC decoding method according to any one of claims 1 to 7 when executed.

Images