Interleaver

Abstract

An embodiment provides an interleaver for interleaving an LDPC-encoded bit sequence, wherein the interleaver includes: a segmentation stage configured to segment the LDPC-encoded bit sequence into a plurality of chunks, the plurality of chunks including a first chunk and one or more other chunks; a first interleaver stage configured to interleave the one or more other chunks or a concatenated version thereof; a second interleaver stage configured to perform block-by-block interleaving between the first chunk in the plurality of chunks and the interleaved bit sequence provided by the first interleaver stage to obtain an interleaved version of the LDPC-encoded bit sequence, wherein the first chunk in the plurality of chunks is composed of a first type of bits, and the first type of bits are error correction bits of the LDPC-encoded bit sequence, repeated accumulation bits of the LDPC-encoded bit sequence, and / or represented by variable nodes including non-random connections with at least two error correction check nodes and represented by a Tanner graph of the LDPC-encoded bit sequence.

Description

Technical Field

[0001] The embodiments relate to an interleaver, and more particularly, to an interleaver for coded words encoded by LDPC (LDPC = Low-Density Parity-Check code). Other embodiments relate to a hybrid block-by-block random interleaver for iterative decision directed channel estimation of LDPC coded words with a staircase node distribution. Background Art

[0002] Low-Density Parity-Check Codes (LDPC) are regarded as a breakthrough in the field of digital communications due to their amazing performance and relatively low complexity. Their capacity approaching performance enables their use in many applications that require robustness and reliability. In addition, their sparse nature facilitates belief propagation (BP) decoding on Tanner graphs.

[0003] The starting point of an LDPC decoder involves the calculation of the a priori Log Likelihood Ratio (LLR). For this purpose, the channel fading coefficient should be estimated with the aid of a known preamble sequence and fed to the LDPC decoder. However, the preamble can only provide short-term information about the fading channel. This means that only the first adjacent coefficients can be estimated. As a result, the remaining symbols will not have Channel State Information (CSI). In other words, the LDPC decoder will be able to calculate the a priori LLR of the first few symbols, while the remaining symbols will be treated as erasure terms. These erasure terms make it impossible to trigger the BP decoding of LDPC.

[0004] On the one hand, increasing the number of pilot symbols will result in a longer channel estimation span. Therefore, more fading coefficients can be estimated and provided to the LDPC decoder, which can achieve better performance. On the other hand, this enhanced performance will come at the cost of a reduced effective data rate due to the transmission of more non-data pilot symbols.

[0005] An LDPC code can be described by its Tanner graph. An (n, k) LDPC code has n variable nodes representing n encoded bits and n - k check nodes representing parity check equations. A systematic LDPC code maps its k information bits to the first k variable nodes. The remaining n - k variable nodes are analogous to n - k parity check bits. The connections between variable nodes and check nodes are made according to the parity check matrix of the given LDPC code.

[0006] A class of LDPC codes, such as those proposed for the upcoming IEEE 802.15.4w[1] and those adopted in the DVB-NGH standard, are characterized by a stepped node distribution. This means that, except for the first k variable nodes representing the systematic information part, the connection of variable nodes to check nodes follows a stepped form. In other words, each variable node is connected to two consecutive check nodes. The (k + 1)-th variable node is connected to the first and second check nodes. The (k + 2)-th variable node is connected to the second and third check nodes, and so on. The n-th variable node is connected to the (n - k)-th check node.

[0007] Figure 1 Shows the Tanner Figure 10 example of the (736, 184) LDPC code proposed in [3], with a code rate of r = 1 / 4. It has n = 736 variable nodes 12, and n - k = 552 check nodes 14. The first k variable nodes 12 correspond to the systematic information part. Their node degree reaches d = 10, and they have random connections 16 to the check nodes 14. Except for the last variable node, the remaining 551 variable nodes exhibit stepped connections to the check nodes 14 corresponding to them, and have a degree, d = 2.

[0008] When the channel estimator provides CSI for a small number of symbols, LDPC codes with a stepped node distribution are prone to decoding failure. The reason behind this performance degradation comes from the connection pattern of check nodes to the corresponding variable nodes. For example, for the (736, 184) code, except for the first check node, each has a degree d = 4. Each check node randomly connects to two variable nodes from the first k variable nodes. The remaining two edges follow a stepped structure via consecutive variable node connections. This means that a short preamble sequence will only provide information about the first few bits of the systematic part. This causes all check nodes in the Tanner graph to have at least two erased LLRs received from their corresponding variable nodes. Therefore, the BP decoding algorithm will not be able to start. Summary of the Invention

[0009] Therefore, the object of the present invention is to provide the following concept: allowing the feasibility of the belief propagation (BP) decoding algorithm for LDPC, even in the case of a limited number of estimated fading coefficients.

[0010] This object is solved by the independent claims.

[0011] Advantageous embodiments are set forth in the dependent claims.

[0012] An embodiment provides an interleaver for interleaving an LDPC encoded bit sequence, wherein the interleaver includes: a segmentation stage configured to segment [e.g., divide] the LDPC encoded bit sequence into [e.g., equal length] chunks, the chunks including a first chunk and one or more other chunks [e.g., a second chunk and optionally a third chunk]; a first interleaver stage configured to interleave the one or more other chunks or a concatenated version thereof [e.g., interleave the second chunk and optionally the third chunk, or interleave a concatenated version of the second chunk and the third chunk]; a second interleaver stage configured to interleavingly combine the first chunk in the chunks with the interleaved bit sequence provided by the first interleaver stage block by block to obtain an interleaved version of the LDPC encoded bit sequence, wherein the first chunk in the chunks consists of bits of a first type [e.g., includes only bits of the first type], and the bits of the first type

[0013] - are error correction bits of the LDPC encoded bit sequence,

[0014] - are repetition accumulation bits of the LDPC encoded bit sequence, and / or

[0015] - are represented by variable nodes including non-random connections to at least two error correction check nodes [e.g., each of the variable nodes is connected to two consecutive check nodes] in a Tanner graph representation of the LDPC encoded bit sequence.

[0016] In an embodiment, the first chunk bypasses the first interleaver stage [e.g., the first chunk is not interleaved by the first interleaver stage].

[0017] In an embodiment, one of the one or more other chunks [e.g., the second chunk] consists of bits of a second type, and the bits of the second type

[0018] - are information bits of the LDPC encoded bit sequence [and e.g., the remaining error correction bits of the LDPC encoded bit sequence], and / or

[0019] - are represented by variable nodes including pseudo-random connections to error correction check nodes in a Tanner graph representation of the LDPC encoded bit sequence.

[0020] In an embodiment, the one or more other blocks are two or more other blocks, wherein another block among the two or more other blocks [e.g., the third block] is composed of bits of the first type.

[0021] In an embodiment, the first interleaver stage is a pseudo-random interleaver.

[0022] In an embodiment, the pseudo-random interleaver is based on a linear shift register.

[0023] In an embodiment, the pseudo-random interleaver is a block-by-block interleaver.

[0024] In an embodiment, the first interleaver stage is configured to interleave the one or more other blocks [e.g., the concatenated version of the other blocks] based on the following syntax:

[0025] for j = 0:((N chunks -1)N bits / chunk )-1

[0026]

[0027] end

[0028] where j represents a control variable, where N chunks represents the number of blocks into which the LDPC-encoded bit sequence is segmented, where N bits / chunk represents the number of bits per block, where represents the interleaved bit sequence [e.g., the interleaved version (concatenated version) of one or more other blocks], where represents the concatenated version of one or more other blocks, where π represents the permutation index vector of the linear feedback shift register.

[0029] In an embodiment, the second interleaver stage is a block-by-block interleaver.

[0030] In an embodiment, the second interleaver stage is configured to distribute the interleaved version of the LDPC-encoded bit sequence over a plurality of sub-data packets.

[0031] In an embodiment, the second interleaver stage is configured to distribute the bits of the first block among the plurality of blocks over the plurality of sub-data packets in at least two rounds [e.g., such that in the first round, consecutive blocks of the bits of the first block [e.g., two bits] are cyclically mapped to the plurality of sub-data packets, and in the second round, other consecutive blocks of the bits of the first block [e.g., two bits] are cyclically mapped to the plurality of sub-data packets].

[0032] In an embodiment, the second interleaver stage is configured to evenly distribute, block by block, the bits of the interleaved bit sequence provided by the first interleaver stage over the plurality of sub-data packets [e.g., the plurality of sub-data packets are evenly filled with the bits of the interleaved bit sequence provided by the first interleaver stage].

[0033] In an embodiment, the second interleaver stage is configured to interleave the first block with the interleaved bit sequence provided by the first interleaver stage based on the following syntax:

[0034]

[0035] Output:

[0036] where i represents a control variable, where j represents a control variable, where k represents a control variable, where N chunks represents the number of blocks into which the LDPC-encoded bit sequence is segmented, where N hops represents the number of sub-data packets on which the interleaved version of the LDPC-encoded bit sequence is distributed, where represents the number of bits taken from the first block in each round and distributed over the plurality of sub-data packets, where N bits / hop represents the number of bits per sub-data packet, where represents the interleaved version of the LDPC-encoded bit sequence, where ch1 represents the first block, where represents the interleaved bit sequence [e.g., the interleaved version (cascaded version) of one or more other blocks].

[0037] In an embodiment, the number of the plurality of blocks into which the LDPC-encoded bit sequence is segmented is equal to one divided by the code rate of the LDPC-encoded bit sequence [Nchunks = 1 / r].

[0038] In an embodiment, the segmentation stage is configured to segment the LDPC-encoded bit sequence 102 into the plurality of blocks based on the following syntax:

[0039]

[0040] where i represents a control variable, where j represents a control variable, where N chunks represents the number of blocks into which the LDPC-encoded bit sequence is segmented, where N bits / chunk represents the number of bits per block, where Ch i represents each of the plurality of blocks, and where v represents the LDPC-encoded bit sequence.

[0041] In an embodiment, the one or more other blocks are two or more other blocks, and the first interleaver stage is configured to interleave a concatenated version of the two or more other blocks.

[0042] In an embodiment, the interleaver includes a concatenation stage configured to concatenate the two or more other blocks to obtain a concatenated version of the two or more other blocks.

[0043] In an embodiment, the concatenation stage is configured to concatenate the one or more other blocks among the plurality of blocks based on the following syntax:

[0044]

[0045]

[0046] where k represents a control variable, where i represents a control variable, where j represents a control variable, and where N bits / chunk represents the number of bits per block, and where represents a concatenated version of the one or more other blocks, and where Ch i represents each of the plurality of blocks.

[0047] In an embodiment, the interleaver is configured to interleave the LDPC-encoded bit sequence based on the following syntax to obtain an interleaved version of the LDPC-encoded bit sequence:

[0048] Input: v, r, n, N hops , π

[0049]

[0050]

[0051] Output:

[0052] where i represents a control variable,

[0053] where j represents a control variable,

[0054] where n represents the number of bits (e.g., information bits + redundancy bits) of the LDPC-encoded bit sequence,

[0055] where k represents a control variable,

[0056] where r represents the code rate,

[0057] where N chunks represents the number of blocks into which the LDPC-encoded bit sequence is segmented.

[0058] where N hops represents the number of sub - data packets of the interleaved version of the LDPC - encoded bit sequence distributed thereon,

[0059] where represents the number of rounds required to distribute the bits of the first block,

[0060] where represents the number of bits taken from the first block per round and distributed over the plurality of sub - data packets,

[0061] where represents the number of bits taken from the other block per round and distributed over the plurality of sub - data packets,

[0062] where N bits / hop represents the number of bits per sub - data packet,

[0063] where N bits / chunk represents the number of bits per block,

[0064] where N bits / chunk / hop represents the number of bits per block per hop,

[0065] where v represents the LDPC - encoded bit sequence,

[0066] where represents the interleaved version of the LDPC - encoded bit sequence,

[0067] where Ch i represents each of the plurality of blocks,

[0068] where Ch1 represents the first block,

[0069] where represents the interleaved bit sequence [e.g., the interleaved version [cascaded version] of one or more other blocks].

[0070] A further embodiment provides an interleaver for interleaving an LDPC-encoded codeword, the LDPC-encoded codeword including a bit sequence having 736 FEC-encoded bits, wherein the interleaver includes: a segmentation stage configured to segment the bit sequence z having 736 FEC-encoded bits into four equal-sized chunks, the four chunks including a chunk numbered one, a chunk numbered two, a chunk numbered three, and a chunk numbered four; a first interleaver stage configured to pseudo-randomly scramble a bit sequence y composed of the chunk numbered one, the chunk numbered three, and the chunk numbered four to obtain a scrambled version y' of the bit sequence, wherein the sequence y is pseudo-randomly scrambled using a scrambling vector u that is derived from a bit random sequence v generated by a 10-bit Galois LFSR with a generating polynomial g(x)=x 10 +x 7 +1; a second interleaver stage configured to distribute each bit c of the chunk numbered two (110_1) over L radio bursts by depending on an index n according to the following syntax n 、a radio burst index l, and a position i within the radio burst:

[0071]

[0072] where n∈{0, 1, 2…183}, where n = 0 refers to the first bit c0 of the chunk numbered two (110_1),

[0073] where the second interleaver stage (108) is configured to distribute the scrambled version y' (112) of the bit sequence over the L radio bursts by depending on an index m to assign the radio burst index l and the position i according to the following syntax:

[0074]

[0075] i(m)=8+(m mod 24),

[0076] where m∈{0, 1, 2…551}, where m = 0 refers to the first bit y'0 of the scrambled version y' (112) of the bit sequence.

[0077] Other embodiments provide a transmitter including: an interleaver according to one of the embodiments described herein; an LDPC encoder configured to provide an LDPC-encoded bit sequence; and a transmitting unit configured to transmit an interleaved version of the LDPC-encoded bit sequence using a plurality of sub-data packets, wherein the plurality of sub-data packets are transmitted non-simultaneously [e.g., using a time-hopping and / or frequency-hopping pattern].

[0078] Other embodiments provide a deinterleaver for deinterleaving an interleaved version of an LDPC-encoded bit sequence, the deinterleaver comprising: a first deinterleaver stage configured to deinterleave the interleaved version of the LDPC-encoded bit sequence block by block to obtain a first sub-block and an interleaved bit sequence [e.g., an interleaved version of one or more other sub-blocks [e.g., a second sub-block and optionally a third sub-block] or a concatenated version of two or more other sub-blocks [e.g., a second sub-block and a third sub-block]]; a second deinterleaver stage configured to deinterleave the interleaved bit sequence to obtain the one or more other sub-blocks [e.g., the second sub-block and optionally the third sub-block]; a concatenation stage configured to concatenate the first sub-block with the one or more other sub-blocks to obtain the LDPC-encoded bit sequence, wherein the first sub-block of the plurality of sub-blocks consists of bits of a first type [e.g., includes only bits of the first type], wherein the bits of the first type

[0079] - are error correction bits of the LDPC-encoded bit sequence,

[0080] - are repeat accumulate bits of the LDPC-encoded bit sequence, and / or

[0081] - are represented in a Tanner graph representation of the LDPC-encoded bit sequence by variable nodes including non-random connections to at least two error correction check nodes [e.g., each of the variable nodes is connected to two consecutive check nodes].

[0082] In an embodiment, the first sub-block bypasses the second deinterleaver stage [e.g., the first sub-block is not deinterleaved by the second deinterleaver stage].

[0083] In an embodiment, one of the one or more other sub-blocks [e.g., the second sub-block] consists of bits of a second type, wherein the bits of the second type

[0084] - are information bits of the LDPC-encoded bit sequence [and e.g., the remaining error correction bits of the LDPC-encoded bit sequence], and / or

[0085] - are represented in a Tanner graph representation of the LDPC-encoded bit sequence by variable nodes including pseudo-random connections to error correction check nodes.

[0086] In an embodiment, the one or more other sub-blocks are two or more other sub-blocks, wherein another of the two or more other sub-blocks [e.g., the third sub-block] consists of bits of the first type.

[0087] In an embodiment, the first deinterleaver stage is a block-by-block deinterleaver.

[0088] In an embodiment, the second deinterleaver stage is a pseudo-random deinterleaver.

[0089] In an embodiment, the pseudo-random deinterleaver is based on a linear shift register.

[0090] In an embodiment, the pseudo-random deinterleaver is a block-by-block deinterleaver.

[0091] In an embodiment, the interleaved bit sequence is an interleaved version of a concatenated version of two or more other blocks, wherein the second deinterleaver stage is configured to deinterleave the interleaved version of the concatenated version of the two or more other blocks.

[0092] Other embodiments provide a receiver, wherein the receiver comprises: a receiving unit configured to receive a plurality of sub-data packets sent from a transmitter to the receiver non-simultaneously [e.g., using a time-hopping and / or frequency-hopping pattern]; a deinterleaver according to one of the foregoing technical solutions, wherein the deinterleaver is configured to iteratively deinterleave a faded version of an LDPC-encoded bit sequence transmitted using the plurality of sub-data packets by using channel state information describing a channel between the transmitter and the receiver; and an iterative decoder configured to iteratively decode the LDPC-encoded bit sequence iteratively provided by the deinterleaver, wherein the channel state information is iteratively updated based on the decoded bit sequence provided by the iterative decoder.

[0093] Other embodiments provide a method for interleaving an LDPC-encoded bit sequence. The method includes the steps of: segmenting the LDPC-encoded bit sequence into a plurality of blocks, the plurality of blocks including a first block and one or more other blocks. Additionally, the method includes the steps of: interleaving the one or more other blocks or a concatenated version thereof to obtain an interleaved bit sequence. Additionally, the method includes the steps of: interleaving the first block in the plurality of blocks with the interleaved bit sequence block by block to obtain an interleaved version of the LDPC-encoded bit sequence. Thus, the first block in the plurality of blocks is composed of a first type of bits, wherein the first type of bits

[0094] - are error correction bits of the LDPC-encoded bit sequence,

[0095] - are repeated accumulation bits of the LDPC-encoded bit sequence, and / or

[0096] - Represented by a Tanner graph representation of the LDPC - encoded bit sequence by including variable nodes with non - random connections to at least two error - correction check nodes.

[0097] Other embodiments provide a method for interleaving an LDPC - encoded codeword, the LDPC - encoded codeword including a bit sequence having 736 FEC - encoded bits. The method includes the steps of: segmenting the bit sequence z having 736 FEC - encoded bits into four equal - sized blocks, the four blocks including a block numbered one, a block numbered two, a block numbered three, and a block numbered four. Additionally, the method includes the steps of: pseudo - randomly scrambling the bit sequence y composed of the block numbered one, the block numbered three, and the block numbered four to obtain a scrambled version y′ of the bit sequence, where the sequence y is pseudo - randomly scrambled using a scrambling vector u, the scrambling vector u being derived from a bit - random sequence v generated by a 10 - bit Galois LFSR with a generating polynomial g(x)=x 10 +x 7 +1. Additionally, the method includes the steps of: distributing each bit c n of the block numbered two (110_1) over L radio bursts based on the following syntax depending on an index n

[0098]

[0099]

[0100] where n ∈ {0, 1, 2…183}, where n = 0 refers to the first bit c0 of the block numbered two (110_1). Additionally, the method includes the steps of: distributing the scrambled version y′(112) of the bit sequence over the L radio bursts by assigning a radio - burst index l and a position i based on the following syntax depending on an index m

[0101]

[0102] i(m)=8+(m mod 24),

[0103] where m ∈ {0, 1, 2…551}, where m = 0 refers to the first bit y'0 of the scrambled version y′(112) of the bit sequence.

[0104] Other embodiments provide a method for deinterleaving an interleaved version of an LDPC-encoded bit sequence. The method includes the steps of: deinterleaving the interleaved version of the LDPC-encoded bit sequence block by block to obtain a first block and interleaved versions of one or more other blocks. Additionally, the method includes the steps of: deinterleaving the interleaved versions of the one or more other blocks to obtain the one or more other blocks. Additionally, the method includes the steps of: concatenating the first block with the one or more other blocks to obtain the LDPC-encoded bit sequence. Thus, the first block among the plurality of blocks consists of bits of a first type, where the bits of the first type

[0105] - are error correction bits of the LDPC-encoded bit sequence,

[0106] - are repeated accumulation bits of the LDPC-encoded bit sequence, and / or

[0107] - are represented in a Tanner graph representation of the LDPC-encoded bit sequence by variable nodes including non-random connections with at least two error correction check nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] Embodiments of the present invention are described herein with reference to the accompanying drawings.

[0109] Figure 1 A schematic diagram showing a Tanner graph representation of the LDPC code proposed in [3],

[0110] Figure 2 A schematic block diagram showing an interleaver according to an embodiment of the present invention,

[0111] Figure 3 A schematic block diagram showing a system including a transmitter and a receiver according to an embodiment,

[0112] Figure 4 A schematic block diagram showing an interleaver for interleaving an LDPC-encoded bit sequence provided by an LDPC encoder according to an embodiment of the present invention,

[0113] Figure 5 A schematic block diagram showing an interleaver for interleaving an LDPC-encoded bit sequence provided by an LDPC encoder according to an embodiment of the present invention,

[0114] Figure 6 A flowchart showing a segmentation method performed at a segmentation stage according to an embodiment of the present invention,

[0115] Figure 7 A flowchart showing a concatenation method performed at a concatenation stage according to an embodiment of the present invention,

[0116] Figure 8 A schematic block diagram showing a 10-bit Galois linear feedback shift register (LFSR).

[0117] Figure 9 A flowchart showing a method for generating a pseudo-random index based on an LFSR according to an embodiment of the present invention.

[0118] Figure 10 A flowchart showing a random interleaving method performed by a first interleaver stage according to an embodiment of the present invention.

[0119] Figure 11 A flowchart showing a block-by-block interleaving method performed by a second interleaver stage according to an embodiment of the present invention.

[0120] Figure 12 A schematic block diagram showing a deinterleaver for deinterleaving an interleaved version of an LDPC-encoded bit sequence according to an embodiment of the present invention.

[0121] Figure 13 A schematic block diagram showing an iterative decoder according to an embodiment of the present invention.

[0122] Figure 14 A flowchart showing a decoding method according to an embodiment of the present invention.

[0123] Figure 15 A flowchart showing a method for interleaving an LDPC-encoded bit sequence according to an embodiment of the present invention.

[0124] Figure 16 A flowchart showing a method for deinterleaving an interleaved version of an LDPC-encoded bit sequence according to an embodiment of the present invention, and

[0125] Figure 17 A schematic block diagram showing a 10-bit Galois linear feedback shift register (LFSR) in an initial state.

[0126] Equal or equivalent elements or elements having equal or equivalent functionality are indicated by equal or equivalent reference numerals in the following description. Detailed Description

[0127] In the following description, numerous specific details are set forth to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to one of ordinary skill in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present invention. Additionally, unless otherwise specifically noted, the features of the different embodiments described below may be combined with each other.

[0128] Figure 2 FIG. 4 shows a schematic block diagram of an interleaver 100 for interleaving an LDPC - encoded bit sequence 102 according to an embodiment of the present invention. The interleaver 100 includes a segmentation stage 104, a first interleaver stage 106, and a second interleaver stage 108.

[0129] The segmentation stage 104 may be configured to segment (e.g., divide) the LDPC - encoded bit sequence 102 into a plurality of blocks 110_0 to 110_N (e.g., of equal length). chunks -1, N chunks ≥2, where the plurality of blocks includes a first block 110_1 and one or more other blocks, such as a zeroth block 110_0 and a second block 110_2 as needed.

[0130] Thus, (e.g., the segmentation stage 104 may be configured to segment the LDPC - encoded bit sequence 102 into a plurality of blocks 110_0 to 110_N in the following manner chunks -1) the first block 110_1 consists of bits of a first type (e.g., includes only bits of the first type), where the bits of the first type are at least one of the following:

[0131] - are error - correction bits of the LDPC - encoded bit sequence 102,

[0132] - are repetition - accumulation bits of the LDPC - encoded bit sequence 102,

[0133] - are represented in the Tanner graph representation of the LDPC - encoded bit sequence 102 by variable nodes that include non - random connections to at least two error - correction check nodes [e.g., each of the variable nodes is connected to two consecutive check nodes].

[0134] The first interleaver stage 106 may be configured to interleave one or more other blocks (such as the zeroth block 110_0 and the second block 110_2 as needed) provided by the segmentation stage 104, or in the case where two or more other blocks are provided by the segmentation stage 104, interleave a concatenated version of the two or more other blocks (e.g., a concatenated version of the zeroth block 110_0 and the second block 110_2) to obtain an interleaved bit sequence 112.

[0135] The second interleaver stage 110 may be configured to interleave in blocks the first chunk 110_1 provided by the segmentation stage 104 and the interleaved bit sequence 112 provided by the first interleaver stage 106 to obtain an interleaved version 116 of the LDPC-coded bit sequence.

[0136] As Figure 2 shown, the first chunk 110_1 bypasses the first interleaver stage 106, or in other words, the first chunk 110_1 is not interleaved by the first interleaver stage 106.

[0137] It can be observed that in an embodiment, the first chunk 110_1 does not refer to a particular chunk in the order (or sequence) of multiple chunks, e.g., not to a numbered first chunk which is the start or origin of the order (or sequence) of multiple chunks, i.e., followed by a numbered second chunk and optionally a numbered third chunk, as Figure 2 indicated by the numbers 1, 2, and 3 within the chunks. Instead, the first chunk 110_1 refers to a chunk composed of bits of a first type among multiple chunks, i.e., error correction bits of the LDPC-coded bit sequence, repeated accumulated bits of the LDPC-coded bit sequence, and / or bits represented by variable nodes including non-random connections to at least two error correction check nodes and represented in the Tanner graph of the LDPC-coded bit sequence. For example, referring to the (736, 184) LDPC code proposed in [3] and assuming that the LDPC code is segmented into four equal-sized chunks: a numbered first chunk (e.g., having bits 1 to 184 out of bits 1 to 736), followed by a numbered second chunk (e.g., having bits 185 to 368 out of bits 1 to 736), followed by a numbered third chunk (e.g., having bits 369 to 552 out of bits 1 to 736), followed by a numbered fourth chunk (e.g., having bits 553 to 736 out of bits 1 to 736); this first chunk 110_1 represents (or refers to) the numbered second chunk because the numbered second chunk is composed of error correction bits of the LDPC-coded bit sequence, repeated accumulated bits of the LDPC-coded bit sequence, and / or bits represented by variable nodes including non-random connections to at least two error correction check nodes and represented in the Tanner graph of the LDPC-coded bit sequence.

[0138] In an embodiment, (e.g., the segmentation stage 104 may be configured to segment the LDPC-coded bit sequence 102 into multiple chunks 110_0 to 110_N chunks -1) one of the one or more other chunks (such as the zero-th chunk 110_0) is composed of bits of a second type, where the second type of bits is at least one of the following cases:

[0139] - is the information bit of the LDPC - encoded bit sequence, and / or

[0140] - is represented by a Tanner graph representation of the LDPC - encoded bit sequence through variable nodes including pseudo - random connections to error - correction check nodes.

[0141] In an embodiment, (e.g., the segmentation stage 104 may be configured to segment the LDPC - encoded bit sequence 102 into multiple blocks 110_0 to 110_N in the following manner chunks - 1) Another block among the other blocks (such as the second block 110_2) consists of bits of a first type (e.g., includes only bits of the first type), i.e., is at least one of the following cases:

[0142] - is an error - correction bit of the LDPC - encoded bit sequence 102,

[0143] - is a repeat - accumulate bit of the LDPC - encoded bit sequence 102,

[0144] - is represented by a Tanner graph representation of the LDPC - encoded bit sequence 102 through variable nodes including non - random connections to at least two error - correction check nodes [e.g., each of the variable nodes is connected to two consecutive check nodes].

[0145] In an embodiment, the first interleaver stage 106 may be a pseudo - random interleaver, such as an interleaver based on a linear feedback shift register or a block interleaver.

[0146] In an embodiment, the second interleaver stage 108 may be a block - by - block interleaver. The block - by - block interleaver 108 may be configured to distribute the interleaved version of the LDPC - encoded bit sequence 116 over multiple sub - data packets 120_0 to 120_N hops - 1 (N hops ≥2).

[0147] Thus, the block - by - block interleaver 108 may be configured to distribute the bits of the first block 110_1 of the multiple blocks block - by - block over the multiple sub - data packets 120_0 to 120_N hops - 1 in at least two rounds. For example, in the first round, consecutive blocks of bits [e.g., two consecutive bits] of the first block 110_1 are cyclically mapped to the multiple sub - data packets 120_0 to 120_N hop - 1, and in the second round, other consecutive blocks of bits [e.g., two consecutive bits] of the first block 110_1 are cyclically mapped to the multiple sub - data packets 120_0 to 120_N hop-1, and so on until all bits of the first block 110_1 are distributed block by block among a plurality of sub-data packets 120_0 to 120_N hop -1.

[0148] For example, illustratively assume that an interleaved version 116 of a bit sequence encoded by LDPC is distributed among three sub-data packets 120_0 to 120_2. The block-by-block interleaver 108 can be configured to map the zero-th and first bits of the first block 110_1 to the zero-th sub-data packet 120_0 in the first round, map the second and third bits of the first block 110_1 to the first sub-data packet 120_1, and map the fourth and fifth bits of the first block 110_1 to the second sub-data packet 120_2. Additionally, the block-by-block interleaver 108 can be configured to map the sixth and seventh bits of the first block 110_1 to the zero-th sub-data packet 120_0 in the second round, map the eighth and ninth bits of the first block 110_1 to the first sub-data packet 120_1, and map the tenth and eleventh bits of the first block 110_1 to the second sub-data packet 120_2. This procedure can be repeated until all bits of the first block 110_1 are distributed among the plurality of sub-data packets.

[0149] Additionally, the block-by-block interleaver 108 can be configured to evenly distribute block by block the bits of the interleaved bit sequence 112 provided by the first interleaver stage 106 over the plurality of sub-data packets (e.g., the plurality of sub-data packets 120_0 to 120_N hops -1) by filling the plurality of sub-data packets 120_0 to 120_N evenly with the bits of the interleaved bit sequence 112 provided by the first interleaver stage 106.

[0150] For example, continuing with the example where the interleaved version 116 of the LDPC-encoded bit sequence is distributed among three sub-data packets 110_0 to 110_2, the block-by-block interleaver 108 can be configured to fill the zero-th sub-data packet 120_0 by mapping the zero-th block of the bits of the interleaved bit sequence 112 to the zero-th sub-data packet 120_0, fill the first sub-data packet 120_1 by mapping the first block of the bits of the interleaved bit sequence 112 to the first sub-data packet 120_1, and fill the second sub-data packet 120_2 by mapping the second block of the bits of the interleaved bit sequence 112 to the second sub-data packet 120_2.

[0151] Subsequently, embodiments of the interleaver 100 are described in more detail.

[0152] 1. Mixed Block-by-Block Random Interleaver

[0153] To overcome the adverse effects of limited channel knowledge as described in the introduction section of this patent application, in an embodiment, the bits of an LDPC codeword are sorted in a way that can improve (e.g., optimize) the use of the initially estimated fading coefficients. This means that the BP algorithm of the LDPC decoder can still be triggered even in the case of having a small number of estimated fading coefficients. For example, this can be used to guide channel estimation (DDCE) [2] with the help of an initially decoded LDPC codeword start decision. The iterative decoder can continuously traverse the information between the channel estimator and the LDPC decoder until the entire LDPC codeword is successfully decoded.

[0154] The embodiment provides an interleaver 100, which aims to reconstruct the Tanner graph of an LDPC code with a code rate r≤1 / 2 showing a ladder structure. The purpose of the interleaver 100 according to the embodiment is to allow the feasibility of the BP decoding algorithm with a finite number of estimated fading coefficients. Since the preamble sequence can only estimate the first few adjacent symbols, the interleaver 100 sorts the LDPC bits such that the initially estimated fading coefficients satisfy the minimum trigger threshold value of the LDPC decoder. In other words, the interleaver 100 makes it possible to increase the probability that a check node has only one erased LLR received from its corresponding variable node.

[0155] In an embodiment, two strategies are adopted. The first strategy is to swap k variable nodes showing random connections with the first k variable nodes having ladder connections. This is done for a systematic code that maps its k information bits to the first k bits of the encoded codeword. In the case where the systematic information bits are not placed at the start of the codeword, this swapping step is not required. In other words, the aim is to start with k variable nodes having ladder connections. The second strategy is to distribute the bits over transmission hops. For the swapped ladder blocks, a block-by-block interleaver is used. This block-by-block interleaver distributes the bits of the ladder block over hops in consecutive rounds. Each round places two consecutive positions on one hop. The remaining codeword bits are interleaved by a random interleaver. Finally, they are distributed over hops after the block-by-block distributed bits.

[0156] The essence of the hybrid interleaver according to the embodiment lies in two aspects: First, it decomposes the ladder structure of the encoded codeword. Second, it distributes the systematic part over hops. This means that the first estimated fading coefficients will be scrambled across the codeword instead of being stacked in one block. Therefore, the LDPC decoder can be triggered even in the case of having the least estimated fading coefficients.

[0157] Figure 3 FIG. shows a schematic block diagram of a system 200 including a transmitter 202 and a receiver 204 according to an embodiment.

[0158] The transmitter 202 includes: an LDPC encoder 206 configured to provide an LDPC-encoded codeword 102 (e.g., an LDPC-encoded bit sequence), an interleaver 100 configured to interleave the LDPC-encoded codeword 102 to obtain an interleaved version 116 of the LDPC-encoded codeword; and a pilot sequence insertion unit 208 configured to add (e.g., append) a pilot sequence 210 to the interleaved version 116 of the LDPC-encoded codeword.

[0159] The receiver 204 includes a channel estimator 212, a deinterleaver 140, an iterative LDPC decoder 214, and an interleaver 100, where the interleaver 100 and the deinterleaver are complementary to each other.

[0160] In other words, Figure 3 FIG. shows a system model of a (hybrid) interleaver 100 according to an embodiment. An information vector of length k bits is encoded by an LDPC encoder 206 at a rate r to produce an output codeword v = [v0 v1 … v n-1 102, where n = k / r. Then, according to an embodiment, the encoded codeword 102 is interleaved by the interleaver 100 to produce an interleaved codeword of the same length )116. Thereafter, a preamble sequence 210 of length L p is appended to the interleaved vector 116. Finally, the data is modulated and transmitted over a fading channel.

[0161] At the receiver 204 side, the preamble sequence 210 is extracted and fed to the channel estimator 212. Since the preamble size is limited, the channel estimator 212 can initially provide CSI only for the first adjacent symbols. Both the received sequence and the partially estimated fading vector are deinterleaved and fed to the LDPC decoder 214. Although the CSI is initially scarce, the proposed interleaver design allows the LDPC decoder 214 to be triggered. Thus, the LDPC decoder 214 can still provide extrinsic information. This decoded information is then interleaved and fed back to the channel estimator 212 as supplementary pilot symbols. This allows more fading coefficients to be estimated in order to trigger the belief propagation decoding of the LDPC with additional a priori probabilities. The iterative decoding process is continuously repeated until the entire LDPC codeword is decoded.

[0162] Figure 4 FIG. shows a schematic block diagram of an interleaver for interleaving an LDPC-encoded bit sequence 102 provided by an LDPC encoder 206 according to an embodiment of the present invention. The interleaver 100 includes a segmentation stage 104, a concatenation stage 105, a first interleaver stage 106, and a second interleaver stage 108.

[0163] Segmentation stage 104 may be configured to segment (e.g., divide) the LDPC-encoded bit sequence 102 into multiple blocks 110_0 to 110_N (e.g., of equal length). chunks -1, N chunks ≥ 2, where the multiple blocks include a first block 110_1 and two or more other blocks 110_0, 110_2 to N chunks -1.

[0164] Thus, (e.g., segmentation stage 104 may be configured to segment the LDPC-encoded bit sequence 102 into multiple blocks 110_0 to 110_N in the following manner chunks -1) the first block 110_1 consists of bits of a first type (e.g., includes only bits of the first type), where the bits of the first type are at least one of the following cases:

[0165] - are error correction bits of the LDPC-encoded bit sequence 102,

[0166] - are repeated accumulation bits of the LDPC-encoded bit sequence 102,

[0167] - are represented by variable nodes that include non-random connections to at least two error correction check nodes [e.g., each of the variable nodes is connected to two consecutive check nodes] in the Tanner graph representation of the LDPC-encoded bit sequence 102.

[0168] The concatenation stage is configured to concatenate the two or more other blocks 110_0, 110_2 to 110_N chunks -1 to obtain a concatenated version 111 of the two or more other blocks 110_0, 110_2 to 110_N chunks -1.

[0169] A first interleaver stage 106, such as a (pseudo) random interleaver, may be configured to interleave, for example, based on a linear feedback shift register (LFSR) 107, the concatenated version 111 of the two or more other blocks 110_0, 110_2 to 110_N chunks -1.

[0170] A second interleaver stage 108, such as a block-by-block interleaver, may be configured to interleave block by block the first block 110_1 provided by the segmentation stage 104 and the interleaved bit sequence 112 provided by the first interleaver stage 106 to obtain an interleaved version 116 of the LDPC-encoded bit sequence.

[0171] In other words, Figure 4A block diagram showing a hybrid block-by-block random interleaver 100 according to an embodiment. The interleaver 100 takes an LDPC-encoded codeword v102 of length n bits and outputs an interleaved version of the same length 116. The interleaving process involves four steps: segmentation (performed, for example, by the segmentation stage 104), concatenation (performed, for example, by the concatenation stage 105), random permutation (performed, for example, by the first interleaver stage 106), and block-by-block distribution (performed, for example, by the second interleaver stage 108). First, the segmentation step means splitting the n-bit codeword 102 into N chunks = 1 / r blocks 110_0 to 110_N chunks -1, where r is the code rate. The first block 110_1 is put aside, and the remaining (N chunks -1) blocks 110_0, 110_2 to 110_N chunks -1 are concatenated again. Thereafter, a pseudo-random interleaver 106 that can be generated by means of a linear feedback shift register (LFSR) 107 is applied to the concatenated sequence 111. This results in a new sequence 112, where the elements of the concatenated sequence 111 are placed according to the permutation index of the LFSR 107. Finally, the interleaved sequence 112 together with the separated block 110_1 is fed into the block-by-block interleaver 108. The purpose of the latter is to distribute the bits evenly over the transmitted hops (or sub-data packets 120_0 to 120_N hops -1). It starts by placing two positions from the separated block 110_1 on each hop 120_0 to 120_N hops -1.

[0172] After traversing all the hops 120_0 to 120_N hops -1, the next round is started by distributing two more bits on each hop. This process is repeated until all the bits of the separated block 110_1 are used up. At the same time, the randomly interleaved sequence 112 is evenly distributed over the hops 120_0 to 120_N hops -1. This means that each hop will include bits from the separated block 110_1 in a block-by-block manner at a ratio of 1:N chunks -1, followed by bits from the randomly interleaved block. These four steps will be described in detail in the following sections.

[0173] Figure 5 A schematic block diagram showing an interleaver for interleaving an LDPC-encoded bit sequence 102 provided by an LDPC encoder 206 according to an embodiment of the present invention. The interleaver 100 includes a segmentation stage 104, a concatenation stage 105, a first interleaver stage 106, and a second interleaver stage 108.

[0174] The segmentation stage 104 may be configured to segment (e.g., divide) the LDPC-encoded bit sequence 102 into four chunks 110_0 to 110_3 (e.g., of equal length), where the four chunks include a first chunk 110_1 and three other chunks 110_0, 110_2, 110_3.

[0175] Thus, (e.g., the segmentation stage 104 may be configured to segment the LDPC-encoded bit sequence 102 into four chunks 110_0 to 110_3 in the following manner) the first chunk 110_1 consists of bits of a first type (e.g., includes only bits of the first type), where the bits of the first type are at least one of the following:

[0176] - are error correction bits of the LDPC-encoded bit sequence 102,

[0177] - are repetition accumulation bits of the LDPC-encoded bit sequence 102,

[0178] - are represented by variable nodes including non-random connections to at least two error correction check nodes [e.g., each of the variable nodes is connected to two consecutive check nodes] in the Tanner graph representation of the LDPC-encoded bit sequence 102.

[0179] The concatenation stage 105 may be configured to concatenate the three other chunks 110_0, 110_2, 110_3 to obtain a concatenated version 111 of the three other chunks 110_0, 110_2, 110_3.

[0180] A first interleaver stage 106, such as a (pseudo) random interleaver, may be configured to interleave the concatenated version 111 of the three other chunks 110_0, 110_2, 110_3, e.g., based on a linear feedback shift register (LFSR) 107.

[0181] A second interleaver stage 108, such as a block-by-block interleaver, may be configured to perform block-by-block interleaving on the first chunk 110_1 provided by the segmentation stage 104 and the interleaved bit sequence 112 provided by the first interleaver stage 106 to obtain an interleaved version 116 of the LDPC-encoded bit sequence.

[0182] In other words, Figure 5 An example of a (hybrid) interleaver 100 is depicted according to an embodiment applied to the (736, 184) LDPC code given in [3]. Since the code rate is 1 / 4, the LDPC codeword 102 should be segmented into N chunks = 4 chunks. Each chunk has n / N chunks= 184 bits. The first block 110_1 is separated, while the zero, second, and third blocks 110_0, 110_2, 110_3 are recascaded to form a vector 111 of length 3 × 184 = 552 bits. This cascaded vector 111 is randomly interleaved (e.g., by the first interleaver stage 106), and together with the separated first block 110_1 is fed to the block interleaver 108. Assuming that the data has to be transmitted on N hops = 23, the block interleaver 108 maps the data to 23 hops 120_0 to 120_22 in a block-by-block manner. It starts by mapping two bits from the first block 110_1 onto each hop. After 23 hops 120_0 to 120_22, 46 bits of the first block 110_1 will have been mapped. To map all 184 bits of the first block 110_1, this process can be repeated four times. Thereafter, the 552 bits of the randomly interleaved vector 112 can be mapped to the hops 120_0 to 120_22, where each hop contains 24 bits taken in one round.

[0183] 1.1 Segmentation

[0184] Figure 6 Shows a flowchart of a segmentation method 400 performed by the segmentation stage 104 according to an embodiment of the present invention.

[0185] In a first step 402, an input is provided, where the input includes an LDPC-encoded bit sequence v, the number n of bits of the LDPC-encoded bit sequence (e.g., information bits + redundant bits), the number k of information bits of the LDPC-encoded bit sequence, the code rate r, and the number N of blocks into which the LDPC-encoded bit sequence is segmented chunks .

[0186] In a second step 404, based on the equation N bits / chunk = n / N chunks the number N of bits per block is determined bits / chunk .

[0187] In a third step 406, the control variable i is set to zero, i = 0.

[0188] In a fourth step 408, the control variable j is set to zero, j = 0.

[0189] In a fifth step 410, based on the equation Ch i (j) = v(j + iN bits / chunk ) the bits of the LDPC-encoded bit sequence v are assigned to the i-th block Ch i .

[0190] In a sixth step 412, the control variable j is incremented by one, j = j + 1.

[0191] In the seventh step 414, check whether the control variable j is less than the number of bits per block N bits / chunk , j < N bits / chunk , and if so, continue with the fifth step 410, otherwise, continue with the eighth step 416.

[0192] In the eighth step 416, increment the control variable i by one, i = i + 1.

[0193] In the ninth step 418, check whether the control variable i is less than the number of blocks N into which the LDPC - encoded bit sequence is to be segmented chunks , i < N chunks , and if so, continue with the fourth step 408, otherwise, continue with the tenth step 420.

[0194] In the tenth step 420, provide a plurality of blocks as output.

[0195] In an embodiment, the first step ( = the segmentation step performed, for example, by the segmentation stage 104) divides the LDPC - encoded codeword 102 into N chunks equal - length blocks 110_0 to 110_N chunks -1. Figure 6 A flowchart showing the segmentation process. The segmentation block 104 takes as input a codeword v102 of length n bits and outputs N chunks blocks 110_0 to 110_N chunks -1, where N chunks = 1 / r, and r = k / n is the code rate. Each block has N bits / chunk = n / N chunks consecutive bits taken from (the LDPC - encoded codeword 102) v. Each block Ch i is given by:[[]]

[0196]

[0197] Taking the (736, 184) LDPC code as an example, the encoded codeword 102 is divided into four blocks 110_0 to 110_3 of length N bits / chunk = 736 / 4 = 184 bits.

[0198] In an embodiment, the segmentation stage 104 may be configured to segment the LDPC - encoded bit sequence 102 into a plurality of blocks based on the following grammar (e.g., by executing the following pseudocode):

[0199]

[0200] where i represents a control variable, where j represents a control variable, and where N chunks represents the number of blocks into which the LDPC-encoded bit sequence is segmented, where N bits / chunk represents the number of bits per block, and where Ch i represents each of the plurality of blocks, and where v represents the LDPC-encoded bit sequence.

[0201] 1.2 Cascade

[0202] Figure 7 Shows a flowchart of a concatenation method 500 performed by the concatenation stage 105 according to an embodiment of the present invention.

[0203] In a first step 502, an input is provided, where the input includes one or more other blocks n bits (e.g., information bits + redundant bits) of the LDPC-encoded bit sequence and the number of blocks N into which the LDPC-encoded bit sequence is to be segmented chunks .

[0204] In a second step 504, based on the equation N bits / chunk = n / N chunks the number of bits per block N is determined bits / chunk .

[0205] In a third step 506, the control variable i is set to zero, i = 0.

[0206] In a fourth step 508, the control variable k is set to zero, k = 0.

[0207] In a fifth step 510, the control variable j is set to zero, j = 0.

[0208] In a sixth step 512, based on the equation one or more other blocks are concatenated.

[0209] In a seventh step 514, the control variable j is incremented by one, j = j + 1.

[0210] In an eighth step 516, it is checked whether the control variable j is less than the number of bits per block N bits / chunk , j < N bits / chunk , and if so, the sixth step 512 to the eighth step 516 are repeated, otherwise, proceed to a ninth step 518.

[0211] In a ninth step 518, the control variable i is incremented by one, i = i + 1.

[0212] In the tenth step 520, check whether the control variable i is less than the number N of blocks into which the LDPC-encoded bit sequence is to be segmented chunks , i < N chunks , and if so, continue with the eleventh step 522, otherwise, continue with the twelfth step 524.

[0213] In the eleventh step 522, check whether the control variable i is equal to one, i == 1, and if so, continue with the ninth step 518, otherwise, continue with the thirteenth step 526.

[0214] In the thirteenth step 526, increment the control variable k by one, k = k + 1, and continue with the fifth step 510.

[0215] In the twelfth step 524, provide a concatenated version of one or more other blocks as output.

[0216] In an embodiment, after segmenting the LDPC codeword 102 into N chunks blocks 110_0 to 110_N chunks -1, the first block 110_1 is separated, while the remaining N chunks -1 blocks 110_0, 110_2 to 110_N chunks -1 can be re-concatenated together. Figure 7 Depict the concatenation process. The concatenator will take (i.e., one or more other blocks 110_0, 110_2 to 110_N chunks -1), and concatenate them into a composite vector chunks of length (N bits / chunk )×N 111. The concatenated vector is given by:

[0217]

[0218] In an embodiment, the concatenation stage 105 can be configured to concatenate one or more other blocks (110_0 - 110_N chunks -1) 110_0 to 110_N chunks- 1 in 1 based on the following grammar (e.g., by executing the following pseudocode): chunks- 1:

[0219]

[0220] where k represents a control variable, where i represents a control variable, where j represents a control variable, where N chunksrepresents the number of blocks into which the LDPC - encoded bit sequence is segmented, where N bits / chunk represents the number of bits per block, where represents the concatenated version of the one or more other blocks, where Ch i represents each of the plurality of blocks.

[0221] 1.3 Random Interleaver

[0222] In an embodiment, the next step ( = random interleaver step, e.g., performed by the first interleaver stage 106) randomizes the concatenated vector 111. For this purpose, one possibility is to use a linear feedback shift register (LFSR) 107 to generate pseudo - random indices. The number of registers N R of the deployed LFSR 107 must satisfy the following inequality:

[0223]

[0224] For the (736, 184) LDPC example, the concatenated vector Ch 0→3\1 111 has 3×184 bits. This means that an LFSR 107 with at least N R = 10 registers is required to provide unique permutation indices. Cyclic redundancy check (CRC) may be a valid potential candidate for initializing such an LFSR 107. It is calculated by shifting the concatenated vector Ch 0→3\1 111 successively behind the LFSR followed by N R zeros.

[0225] Figure 8 Shows an example of a 10 - bit Galois LFSR 107 whose generating polynomial g(x)=x 10 +x 7 +1 = 0x240, and the initial state corresponds to a checksum of 0x2D7. The LFSR 107 iterates through all states except the all - zero state. The next state of such an LFSR is 0x32B, which is equal to the decimal index 811. This index value is greater than the number of required permutation indices. Therefore, the index is discarded, and the LFSR enters the next iteration.

[0226] Figure 9 Shows a flowchart of a method 600 for generating pseudo - random indices based on an LFSR according to an embodiment of the present invention.

[0227] In a first step 602, inputs are provided, wherein the inputs include a generator polynomial gen, an initial state initial of the LFSR, the number n of bits (e.g., information bits + redundant bits) of the LDPC-coded bit sequence, and the number N of blocks into which the LDPC-coded bit sequence is to be segmented. chunks .

[0228] In the second step 604, based on the equation N bits / chunk =n / N chunks Determine the number of bits per block N bits / chunk , and based on the equation L = (N chunks -1)×N bits / chunk Determine the length L of the required index.

[0229] In a third step 606, the control variable j is set to zero, j=0.

[0230] In the fourth step 608, the feedback of the LFSR is set to the initial state initial&1, feedback=initial&1, that is, the last bit (least significant bit) of the initial state is provided as feedback.

[0231] In the fifth step 610, the initial state initial of the LFSR is shifted right by one position, inital>>1.

[0232] In the sixth step 612 , it is checked whether the feedback of the LFSR is equal to 1, feedback=1, and if so, continue with the seventh step 614 , otherwise continue with the eighth step 616 .

[0233] In the seventh step 614, the initial state initial of the LFSR is XORed with the generator polynomial of the LFSR to obtain a new initial state initial=initial⊕gen.

[0234] In an eighth step 616 , it is checked whether the decimal equivalent of the initial state initial of the LFSR is equal to or smaller than the length L of the required index, and if so, continue with a ninth step 618 , otherwise continue with the fourth step 608 .

[0235] In a ninth step 618, the permutation index vector π at position j is set to initial minus one, π(j)=initial-1.

[0236] In the tenth step 620, the control variable j is increased by one, j=j+1.

[0237] In the eleventh step 622, check whether the control variable j is less than L, j < L, and if so, continue with the fourth step 608, otherwise continue with the twelfth step 624.

[0238] In the twelfth step 624, provide the permutation index vector π as the output.

[0239] In other words, Figure 9 The flowchart of the pseudo-random index generator using the LFSR 107 is shown in. The LFSR 107 is generated by the original generating polynomial of degree N R and initialized by the CRC checksum or any initial state within its cycle span. After each iteration, the LFSR exhibits a new state corresponding to the candidate permutation index. This index must be compared with the required index length L = (N chunks -1)×N bits / chunk If the generated index is less than L, it is appended to the permutation index vector π. Otherwise, the state is discarded, and the LFSR enters the next state. When the number of generated indexes in π reaches L, the algorithm stops.

[0240] Figure 10 The flowchart of the method 700 for random interleaving performed by the first interleaver stage 106 (e.g., LFSR random interleaver) according to an embodiment of the present invention is shown.

[0241] In the first step 702, provide an input, where the input includes the concatenated version of other blocks the permutation index vector π, the number of n bits of the LDPC-encoded bit sequence (e.g., information bits + redundant bits), and the number of blocks N into which the LDPC-encoded bit sequence is to be segmented chunks .

[0242] In the second step 704, based on the equation N bits / chunk = n / N chunks determine the number of bits per block N bits / chunk , and based on the equation L = (N chunks -1)×N bits / chunk determine the length L of the required index.

[0243] In the third step 706, set the control variable j to zero, j = 0.

[0244] In the fourth step 708, perform pseudo-random interleaving on other blocks based on the permutation index vector π to obtain the interleaved bit sequence (e.g., the interleaved version of the concatenated version of other blocks),

[0245] In the fifth step 710, increment the control variable j by one, j = j + 1.

[0246] In the sixth step 712, check if the control variable j is less than L, j < L, and if so, continue with the fourth step 708, otherwise continue with the seventh step 714.

[0247] In the seventh step 714, the interleaved bit sequence is provided as the output.

[0248] In an embodiment, after generating the pseudo - random index, it can be used to permute the concatenated (N chunk -1) block vectors (i.e., the concatenated version of one or more other blocks 110_0, 110_2 to 110_N chunks -1). The random interleaver 106 receives the permutation vector π and the concatenated vector 111. It generates an interleaved vector 112 of the same length as . The mapping from the elements of to is completed according to the permutation indices in π such that:

[0249]

[0250] where = (N chunks -1)×N bits / chunk is the length of the concatenated index. Figure 10 illustrates the random interleaving process.

[0251] In an embodiment, the first interleaver stage 106 can be configured to interleave the concatenated version of the other blocks 110_0, 110_2 to 110_N chunks -1 among the plurality of blocks 110_0 to 110_N chunks -1 based on the following grammar (e.g., by executing the following pseudocode):

[0252] for j = 0:((N chunks -1)N bits / chunk )-1

[0253]

[0254] end

[0255] where j represents the control variable, where N chunks represents the number of blocks into which the LDPC - encoded bit sequence is segmented, where N bits / chunk represents the number of bits per block, where represents the interleaved bit sequence (e.g., the interleaved version (cascaded version) of the one or more other blocks), wherein represents the cascaded version of the one or more other blocks, where π represents the permutation index vector of a linear feedback shift register.

[0256] 1.4 Block-by-Block Interleaver

[0257] Figure 11 shows a flowchart of a block-by-block interleaving method 800 performed by a second interleaver stage 108 according to an embodiment of the present invention.

[0258] In a first step 802, an input is provided, where the input includes a first block Ch1, the interleaved bit sequence the number of n bits of the LDPC-encoded bit sequence (e.g., information bits + redundant bits), the number N of blocks into which the LDPC-encoded bit sequence is segmented chunks (which is equal to 1 / r), the number N of sub-data packets on which the LDPC-encoded bit sequence is to be distributed hops , and the number of bits taken from the first block in each round and distributed over a plurality of sub-data packets

[0259] In a second step 804, based on the equation N bits / chunk = n / N chunks determine the number of bits N per block bits / chunk , based on the equation N bits / hop = n / N hops determine the number of bits N per sub-data packet bits / hop , based on the equation N bits / chunk / hop = N bits / chunk / N hops determine the number of bits N per block per sub-data packet bits / chunk / hop , based on the equation determine the number of rounds required to distribute the bits of the first block and based on the equation determine the number of bits taken from the other blocks in each round and distributed over a plurality of sub-data packets

[0260] In a third step 806, set the control variable i to zero, i = 0.

[0261] In a fourth step 808, set the control variable j to zero, j = 0.

[0262] In a fifth step 810, set the control variable k to zero, k = 0.

[0263] In a sixth step 812, based on the equation Map the bits of the first chunk Ch1 to the interleaved version of the LDPC-coded bit sequence

[0264] In the seventh step 814, increment the control variable k by one, k = k + 1.

[0265] In the eighth step 816, check if k is less than the number of rounds required to distribute the bits of the determined first chunk and if so, continue with the sixth step 812, otherwise continue with the ninth step 818.

[0266] In the ninth step 818, increment the control variable j by one, j = j + 1.

[0267] In the tenth step 820, check if j is less than the number of bits taken from the first chunk per round and distributed over multiple sub-data packets and if so, continue with the fifth step 810, otherwise continue with the eleventh step 822.

[0268] In the eleventh step 822, set the control variable j to zero, j = 0.

[0269] In the twelfth step 824, based on the equation Map the interleaved bit sequence to the interleaved version of the LDPC-coded bit sequence

[0270] In the thirteenth step 826, increment the control variable j by one, j = j + 1.

[0271] In the fourteenth step 828, check if the control variable j is less than the number of bits taken from other chunks per round and distributed over multiple sub-data packets and if so, continue with the twelfth step 824, otherwise continue with the fifteenth step 830.

[0272] In the fifteenth step 830, increment the control variable i by one, i = i + 1.

[0273] In the sixteenth step 832, check if the control variable i is less than the number N of sub-data packets on which the interleaved version of the LDPC-coded bit sequence is to be distributed hops , and if so, continue with the fourth step 808, otherwise continue with the seventeenth step 834.

[0274] In the seventeenth step 834, provide the interleaved version of the LDPC-coded bit sequence as output.

[0275] In an embodiment, the last step ( = second interleaving step, e.g., performed by the second interleaver stage 108) involves the extracted chunk Ch1 (i.e., the first chunk 110_1) and the random interleaved vector )(i.e., interleaving of the interleaved bit sequence 112 in a chunk-by-chunk manner. The idea is to evenly distribute the encoded bits over the transmitted jumps 120_1 to 120_N hops -1. Each jump includes bits from (the first chunk 110_1) Ch1 and (the other chunks 110_0, 110_2 to 110_N chunks -1) in a ratio of 1:N chunks -1. This means that if n data bits are to be transmitted over N hops (N bits / hop = n / N hops ), then 1 / N chunks of the bits are taken from (the first chunk 110_1) Ch1, while the remaining (N chunks -1) / N are taken from (the other chunks 110_0, 110_2 to 110_N chunks -1) chunks . Further, the bits of (the first chunk 110_1) Ch1 mapped on each jump are obtained in a per-jump cyclic manner . This means that the first two bits of (the first chunk 110_1) Ch1 are mapped to the first jump 120_0. The next two bits are placed on the second jump 120_1, and so on. After N hops , another round starts with mapping two bits of (the first chunk 110_1) ch1 on each jump. After , all N bits / chunk bits of (the first chunk 110_1) Ch1 are fully mapped to N hops . Finally, within one round, the bits of the interleaved vector 112 are mapped to the jumps 120_0 to 120_N hops -1, where one round includes bits on each jump.

[0276] In Figure 11 is shown the flow chart of the per-chunk random interleaver. (The first chunk 110_1) Ch1 and (the interleaved bit sequence 112) are fed into the interleaver 108, resulting in the output vector 116, which corresponds to the interleaved version of the LDPC encoded vector v 102. The interleaver 108 cycles over N hops and assigns Nbits / hop The units digit. It first starts with mapping the units digit from (the first block 110_1) Ch1 onto each transition in a number of rounds. This can be expressed as:

[0277]

[0278] where

[0279] N hops is the number of transitions,

[0280] N bits / hop = n / N hops is the number of bits sent on each transition,

[0281] is the number of bits mapped from Ch1 to each transition in each round,

[0282] is the total number of rounds required to exhaust all bits in Ch1,

[0283] i = 0,..., N hops - 1 is the transition index,

[0284] is the bit index within the round, and

[0285] is the round index.

[0286] After that, each transition will have the units digit from (the first block 110_1) Ch1. The remaining N bits / hop units digits on each transition should be taken from (the interleaved bit sequence 112) because (the interleaved bit sequence 112) has been pseudo - randomly interleaved, so the bits will be distributed over transitions 120_1 to 120_N hops - 1 in a round (i.e., ). This means that for each transition, should be taken the units digits from (the interleaved bit sequence 112). This can be described by the following formula:

[0287]

[0288] where,

[0289] N bits / chunk / hop = N bits / chunk / N hopsRoughly the bit count sent from each block on each transition,

[0290] is the number of bits sent from the mapped bits on each transition,

[0291] i = 0, …, N hops -1 is the transition index, and

[0292] is the bit index within.

[0293] In an embodiment, the second interleaver stage 108 may be configured to interleave the first block 110_1 with the interleaved bit sequence 112 based on the following syntax (e.g., by executing the following pseudocode):

[0294]

[0295]

[0296] Output:

[0297] where i represents a control variable, where j represents a control variable, where k represents a control variable, where N chunks represents the number of blocks into which the LDPC-encoded bit sequence is segmented, where N hops represents the number of sub-data packets on which the interleaved version of the LDPC-encoded bit sequence is distributed, where represents the number of bits taken from the first block in each round and distributed over the plurality of sub-data packets, where N bits / hop represents the number of bits per sub-data packet, where represents the interleaved version of the LDPC-encoded bit sequence, where Ch1 represents the first block, where represents the interleaved bit sequence (e.g., the interleaved version (cascaded version) of the one or more other blocks).

[0298] 2. De-Interleaver

[0299] Figure 12 FIG. shows a schematic block diagram of a deinterleaver 140 for deinterleaving an interleaved version of an LDPC-encoded bit sequence according to an embodiment of the present invention. The deinterleaver 140 includes a first deinterleaver stage 142, a second deinterleaver stage 144, and a cascading stage 146.

[0300] The first de - interleaver stage 142 can be configured to de - interleave, block - by - block, an interleaved version 116 of the LDPC - encoded bit sequence to obtain a first block 110_1 and an interleaved bit sequence 112, such as an interleaved version of one or more other blocks or a concatenated version of two or more other blocks.

[0301] Thus, the first block 110_1 consists of bits of a first type, where the first type of bits is at least one of the following:

[0302] - are error - correction bits of the LDPC - encoded bit sequence,

[0303] - are repetition - accumulation bits of the LDPC - encoded bit sequence,

[0304] - are represented in the Tanner graph representation of the LDPC - encoded bit sequence by variable nodes that include non - random connections to at least two error - correction check nodes (e.g., each of the variable nodes is connected to two consecutive check nodes).

[0305] The second de - interleaver stage 144 can be configured to de - interleave the interleaved bit sequence 112 to obtain one or more other blocks, such as a zero - th block 110_0 and, as needed, a second block 110_2.

[0306] The concatenation stage 146 can be configured to concatenate the first block 110_1 with one or more other blocks, such as the zero - th block 110_0 and, as needed, the second block 110_2, to obtain the LDPC - encoded bit sequence 102.

[0307] As Figure 12 shown, the first block 110_1 bypasses the second de - interleaver stage 144, or in other words, the first block 110_1 is not de - interleaved by the second de - interleaver stage 144.

[0308] In an embodiment, one of the one or more other blocks (such as the zero - th block 110_0) consists of bits of a second type, where the second type of bits is at least one of the following:

[0309] - are information bits of the LDPC - encoded bit sequence, and / or

[0310] - are represented in the Tanner graph representation of the LDPC - encoded bit sequence by variable nodes that include pseudo - random connections to error - correction check nodes.

[0311] In an embodiment, another of the other blocks (such as the second block 110_2) consists of bits of the first type (e.g., consists only of bits of the first type), i.e., is at least one of the following:

[0312] - is an error correction bit of the LDPC-encoded bit sequence 102,

[0313] - is a repetition accumulation bit of the LDPC-encoded bit sequence 102,

[0314] - is represented by a Tanner graph of the LDPC-encoded bit sequence 102 through a variable node including non-random connections to at least two error correction check nodes [e.g., each of the variable nodes is connected to two consecutive check nodes].

[0315] In an embodiment, the first deinterleaver stage 142 can be a block-by-block deinterleaver. For example, the first deinterleaver stage 142 can be complementary to the second interleaver stage 108 (see Figure 2 ).

[0316] In an embodiment, the second deinterleaver stage 144 can be a pseudo-random deinterleaver, such as a linear feedback shift register-based deinterleaver or a block-by-block deinterleaver.

[0317] 3. Iterative Decoder

[0318] Figure 13 Shows a schematic block diagram of an iterative decoder according to an embodiment of the present invention. The iterative decoder 204 includes a channel estimator, the above-mentioned deinterleaver 140, an LDPC decoder 214, and the above-mentioned interleaver 100.

[0319] In other words, Figure 11 Depicts a block diagram of an iterative decoder 204 for an interleaved LDPC codeword 116. The signal received at the receiver side includes a faded version of the transmitted signal, the transmitted signal including a preamble 210 and an interleaved LDPC codeword 116. The preamble 210 is fed to a channel estimator 212, which in turn produces an estimate of the first D L fading coefficients. The remaining n-D L coefficients remain unknown. Both the received codeword 116 and the partially estimated fading vector are deinterleaved (e.g., by the deinterleaver 140) and fed to the LDPC decoder 214, which calculates the prior LLRs of the symbols corresponding to the estimated coefficients while treating the remaining coefficients as erasure terms. These prior LLRs trigger the belief propagation decoding of the LDPC.

[0320] Since the interleaver 100 destroys the ladder structure of the LDPC codeword 102, even if only D LWith one available estimated fading coefficient, the LDPC decoder 214 can still be triggered. This results in a preliminarily decoded vector, which serves as an additional pilot signal for the channel estimator 212. Then, another decoding iteration is triggered by interleaving the partially decoded vector and passing it back to the channel estimator 212 together with the original preamble. As a result, a longer block with 2D L fading coefficients can be estimated. The newly estimated fading vector is deinterleaved once again and passed to the LDPC decoder 214, enabling it to decode a larger block of the received codeword. This process is iteratively repeated until all n bits of the received codeword are decoded.

[0321] Figure 14 FIG. 6 shows a flowchart of a decoding method 900 according to an embodiment of the present invention.

[0322] In a first step 902, an input is provided, where the input includes a reference pilot sequence (e.g., preamble) p ref , a received pilot sequence (e.g., preamble) p rec , a code rate r, the number n of bits of the LDPC-encoded bit sequence (e.g., information bits + redundant bits), and the number D of estimated coefficients at iteration . L .

[0323] In a second step 904, based on the equation N iter = n / D L the number of iterations N iter is determined, the fading estimation vector is initialized to zero, the decoded codeword is initialized to zero,

[0324] In a third step 906, a control variable i is set to zero, i = 0.

[0325] In a fourth step 908, based on the equation the fading estimation vector

[0326] is estimated. In a fifth step 910, the fading estimation vector is updated to include

[0327] In a sixth step 912, both r and are deinterleaved and fed to the LDPC decoder, where the LDPC decoder first calculates the a priori LLR and then triggers the belief propagation algorithm to attempt to partially decode the received codeword.

[0328] In the seventh step 914, the reference prefix is updated to include the interleaved decoded LDPC blocks.

[0329]

[0330] In the eighth step 916, the received version of the reference prefix is updated to include the faded received version of the decoded LDPC blocks, p rec = [p rec r(i×D L :((i + 1)×D L ) - 1)].

[0331] In the ninth step 918, the control variable i is incremented by one, i = i + 1.

[0332] In the tenth step 920, it is checked whether the control variable i is less than the determined number of iterations N iter , and if so, continue with the fourth step 908, otherwise continue with the eleventh step 922.

[0333] In the eleventh step 922, the decoded codeword is provided as the output.

[0334] In other words, a detailed description of the decoding mechanism is given in Figure 14 . In the first decoding iteration, the prefix is initialized to the received prefix sequence, and both the fading estimation vector and the decoded codeword are initialized to zero. Let represent the vector of D estimated coefficients at iteration L , where N iter is the number of decoding iterations. The estimation vector is updated to include such that:

[0335]

[0336] Thereafter, both and r are deinterleaved and fed to the LDPC decoder 214. The decoder first calculates the a priori LLR, and then triggers the belief propagation algorithm to attempt to partially decode the received codeword.

[0337] After each iteration, both the reference prefix and its received version are updated to include the interleaved decoded LDPC blocks and their faded received versions, respectively. This can be described by the following equation:

[0338]

[0339] p rec = [p rec r(i×D L :((i + 1)×D L ) - 1)], (9)

[0340] where

[0341] ξ(x), ξ -1 (x) correspond to the interleaved version and the de - interleaved version of the vector x, respectively,

[0342] ξ(x(a:b)), ξ -1 (x(a:b)) correspond to the values of the a - th index to the b - th index of the interleaved and de - interleaved versions of x, respectively.

[0343] p ref and p rec represent the reference and the received preambles, respectively.

[0344] 3. Other Embodiments

[0345] Figure 15 FIG. 38 shows a flowchart of a method 300 for interleaving an LDPC - encoded bit sequence according to an embodiment of the present invention. Method 300 includes step 302: segmenting the LDPC - encoded bit sequence into a plurality of blocks, the plurality of blocks including a first block and one or more other blocks, wherein the first block among the plurality of blocks is composed of a first type of bits, and the first type of bits

[0346] - are the error - correction bits of the LDPC - encoded bit sequence,

[0347] - are the repeated - accumulation bits of the LDPC - encoded bit sequence, and / or

[0348] - are represented by variable nodes including non - random connections to at least two error - correction check nodes in the Tanner graph representation of the LDPC - encoded bit sequence.

[0349] In addition, method 300 includes step 304: interleaving the one or more other blocks or their concatenated versions to obtain an interleaved bit sequence. In addition, method 300 includes step 303: interleaving the first block among the plurality of blocks and the interleaved bit sequence block - by - block to obtain an interleaved version of the LDPC - encoded bit sequence.

[0350] Figure 16A flowchart of a method 320 for deinterleaving an interleaved version of an LDPC-encoded bit sequence according to an embodiment of the present invention is shown. Method 320 includes step 322: deinterleaving the interleaved version of the LDPC-encoded bit sequence block by block to obtain a first block and interleaved versions of one or more other blocks, wherein the first block among the plurality of blocks is composed of bits of a first type, and the bits of the first type

[0351] - are error correction bits of the LDPC-encoded bit sequence,

[0352] - are repeat accumulation bits of the LDPC-encoded bit sequence, and / or

[0353] - are represented by variable nodes including non-random connections to at least two error correction check nodes in a Tanner graph representation of the LDPC-encoded bit sequence.

[0354] In addition, method 320 includes step 324: deinterleaving the interleaved versions of the one or more other blocks to obtain the one or more other blocks. In addition, method 320 includes step 326: concatenating the first block with the one or more other blocks to obtain the LDPC-encoded bit sequence.

[0355] Subsequently, other embodiments of the present invention are described, which can be implemented alone or in combination with any of the embodiments described in this patent application.

[0356] Embodiments provide a hybrid interleaver for LDPC codes (such as the codes proposed for the upcoming IEEE802.15.4w [1] and the codes adopted in the DVB-NGH standard) that exhibit a stepped node distribution. The interleaver makes it possible to provide additional pilot symbols to a channel estimator in order to provide a decision-directed channel estimation (DDCE) method [2]. The interleaver decomposes an LDPC codeword into N_chunks blocks. It starts with a block that marks the start of a stepped structure. This stepped block is distributed block by block over the jumps. Thereafter, the remaining N chunks - 1 blocks are randomly interleaved and placed on the jumps following the block-by-block interleaved stepped bits. The essence of the hybrid block-by-block random interleaver according to the embodiment is that even in the presence of a finite number of estimated fading coefficients, a new structured LDPC codeword can be used to trigger a belief propagation (BP) decoding algorithm. This means that the LDPC decoder will still be able to decode some bits. These bits will act as additional pilot symbols, which can be fed back to the channel estimator together with the original preamble sequence. This in turn will allow the detection of additional fading coefficients that will be fed back to the LDPC decoder. The process of traversing information back and forth between the LDPC decoder and the decision-directed channel estimator will continue until the entire LDPC codeword is decoded.

[0357] The embodiments reconstruct the Tanner graph of a LDPC code exhibiting a ladder structure at a code rate r ≤ 1 / 2.

[0358] The embodiments reorder the LDPC codewords in a way that maximizes the decoding ability of the LDPC codewords (e.g., even with a limited number of estimated fading coefficients).

[0359] The embodiments sort the LDPC bits such that the initially estimated fading coefficients will satisfy the minimum trigger threshold value of the LDPC decoder.

[0360] The embodiments increase the probability that a check node has only one erased LLR received from its corresponding variable node.

[0361] The embodiments decompose the ladder structure of the encoded codewords.

[0362] The embodiments distribute non-ladder systematic information bits over the jumps.

[0363] The embodiments indirectly scramble the initially estimated fading coefficients across codewords (e.g., rather than stacking them in one block).

[0364] The embodiments allow the feasibility of the belief propagation decoding algorithm of LDPC in the case of a limited number of estimated fading coefficients.

[0365] The embodiments assign the LDPC decoded bits to act as additional pilot symbols, which can be fed back to the channel estimator together with the original preamble sequence.

[0366] The embodiments allow the detection of additional fading coefficients to be fed back to the LDPC decoder.

[0367] The embodiments traverse information back and forth between the LDPC decoder and the decision-directed channel estimator.

[0368] The embodiments facilitate enhancing the channel estimation with a relatively short preamble sequence.

[0369] The embodiments eliminate the need to transmit a long non-data preamble sequence to ensure a specific reliability threshold value.

[0370] Compared with traditional pilot-assisted channel estimation, the embodiments relatively enhance the effective data rate while meeting the same reliability level.

[0371] Compared with traditional pilot-assisted channel estimation, the embodiments alternatively provide a higher level of robustness while using the same preamble size.

[0372] In an embodiment, an interleaver (e.g., a hybrid block - by - block random interleaver) involves four stages (or blocks): (1) segmentation, (2) concatenation, (3) pseudo - random interleaving, and (4) block - by - block interleaving.

[0373] In an embodiment, a codeword v of length n bits in a partitioned block region is input, and N chunks blocks are output, chunks where N bits / chunk = 1 / r, and r = k / n is the code rate, and each block has N chunks = n / N i bits taken consecutively from v, where each block Ch

[0374]

[0375] In an embodiment, the concatenator takes and concatenates them into a composite vector of length (N chunks - 1)×N bits / chunk where the concatenated vector is given by: where the concatenated vector is given by:

[0376]

[0377] In an embodiment, the random interleaver takes the permutation vector π generated by an LFSR and the concatenated vector where the random interleaver produces an interleaved vector where the mapping from the elements of to is done according to the permutation indices in π such that:

[0378]

[0379] where L = (N chunks - 1)×N bits / chunk is the length of the concatenated vector.

[0380] In an embodiment, both Ch1 and are fed into the block - by - block interleaver, resulting in an output vector which corresponds to the interleaved version of the LDPC - encoded vector v. The interleaver cycles through N hops and assigns N bits / hop bits to each jump. It starts by mapping the N bits from Ch1 to each jump in the first round. This can be represented by:

[0381]

[0382] Among them,

[0383] N hops is the number of transitions,

[0384] N bits / hop = n / N hops is the number of bits sent on each transition,

[0385] is the number of bits mapped from Ch1 on each transition per round,

[0386] is the total number of rounds required to exhaust all the bits of Ch1,

[0387] i = 0, …, N hops -1 is the transition index,

[0388] is the bit index within the round, and

[0389] is the round index.

[0390] In an embodiment, after each transition will have a bits from Ch1. The remaining N bits / hop a bits on each transition should be taken from This means that for each transition, should be taken in sequence from a bits. This can be described by the following formula:

[0391]

[0392] Among them,

[0393] N bits / chunk / hop = N bits / chunk / N hops is roughly the bit count sent from each block on each transition,

[0394] is the number of bits mapped from on each transition,

[0395] i = 0, …, N hops -1 is the transition index, and

[0396] is the bit index within.

[0397] Other embodiments provide an interleaver for interleaving an LDPC-encoded bit sequence to obtain an interleaved version of the LDPC-encoded bit sequence, where the interleaver is configured to interleave the LDPC-encoded bit sequence based on the following grammar (e.g., by executing the following pseudocode):

[0398] Input: v, r, n, N hops , π

[0399]

[0400]

[0401] Output:

[0402] where i represents a control variable, where j represents a control variable, where n represents the number of bits (e.g., information bits + redundant bits) of the LDPC-encoded bit sequence, where k represents a control variable, where r represents the code rate, where N chunks represents the number of blocks into which the LDPC-encoded bit sequence is segmented, where N hops represents the number of sub-data packets on which the interleaved version of the LDPC-encoded bit sequence is distributed, where represents the number of rounds required to distribute the bits of the first block, where represents the number of bits taken from the first block per round and distributed over multiple sub-data packets, where N bits / hop represents the number of bits per sub-data packet, where N bits / chunk represents the number of bits per block, where N bits / chunk / hop represents the number of bits per block per transition, where v represents the LDPC-encoded bit sequence, where represents the interleaved version of the LDPC-encoded bit sequence, where Ch i represents each of the multiple blocks, where Ch1 represents the first block, where represents the interleaved bit sequence (e.g., the interleaved version (cascaded version) of the one or more other blocks).

[0403] Channel estimation is a key factor for successful decoding of LDPC codewords. To provide sufficient channel estimation, a long preamble sequence is required. This in turn reduces the effective data rate. On the other hand, if a short preamble is inserted, the LDPC decoder will lack a sufficient number of estimated fading coefficients. As a result, the LDPC decoder will treat the symbols corresponding to the non-estimated coefficients as erasure terms. Therefore, this will make it impossible to trigger the LDPC decoder.

[0404] Embodiments provide a hybrid interleaver aimed at solving the rate-reliability trade-off dilemma. The hybrid interleaver processes LDPC codes exhibiting a stepped node structure, such as the codes proposed for the upcoming IEEE 802.15.4w and those adopted in the DVB-NGH standard. The aim is to reconstruct the LDPC codeword in a way that maximizes its decoding ability even when the estimated fading coefficients are limited. The interleaver decomposes the LDPC codeword into N chunks blocks. It starts with the block that marks the start of the stepped structure. This stepped block is distributed over the jumps in a block-by-block manner. Thereafter, the remaining (N chunks -1) blocks are pseudo-randomly interleaved and placed on the jumps following the step bits interleaved block-by-block.

[0405] The essence of the hybrid block-random interleaver according to embodiments is that it can use the new structured LDPC codeword to trigger the BP decoding algorithm even in the presence of a limited number of estimated fading coefficients. This means that the LDPC decoder will still be able to decode some bits. These bits will act as additional pilot symbols, which can be fed back to the channel estimator together with the original preamble sequence. This, in turn, will allow the detection of additional fading coefficients to be fed back to the LDPC decoder. The process of traversing information back and forth between the LDPC decoder and the decision-guided channel estimator will continue until the entire LDPC codeword is decoded.

[0406] Other embodiments provide an interleaver (100) for interleaving an LDPC-encoded codeword, the LDPC-encoded codeword including a bit sequence z (102) having 736 FEC-encoded bits (FEC = forward error correction).

[0407] The sequence z of 736 FEC-encoded bits of a single codeword (102) of the LDPC encoder should be segmented into 4 equal-sized blocks C i :

[0408] z = {C0, C1, C2, C3} = {z0, z1, z2,...., z 735},

[0409] C i = {z i·184 , z i·184+1 , z i·184+2 ,…, z (i+1)·184-1}.

[0410] The second block C1 (110_1) should be removed from the sequence [e.g., the numbered second block of the sequence of four blocks 110_0 to 110_3 is designated as the first block 110_1 herein (e.g., in line with Figure 2Comparison). The remaining sequence y(111) [e.g., the concatenated version of (three other blocks 110_0, 110_2, and 110_3), i.e., the first numbered block, the second numbered block, and the fourth numbered block (e.g., in comparison with Figure 2 Comparison) is given by:

[0411] y = {C0, C2, C3} = {y0, y1, y2,...., y 551}

[0412] The sequence y(111) should be pseudo-randomly scrambled using the scrambling vector u, which is derived from the pseudo-random sequence v generated by a 10-bit Galois LFSR with a generating polynomial g(x) = x 10 + x 7 + 1. The initial value of the LFSR shift register (107) at iteration 0 should be v0 = 469, where the feedback output of the LFSR (107) represents the least significant bit. The LFSR (107) in its initial state at iteration 0 is shown in Figure 17 in.

[0413] The value of iteration v is derived by iterating the shift register again. i+1 If the value of this iteration of the LFSR exceeds 552, then the value is skipped, and the LFSR is iterated again until the value does not exceed 552. Then the value is assigned to v i+1 .

[0414] An example of the first value of v is given in Table 1:

[0415] Table 1 Example of scrambling vector generation

[0416] LFSR Iteration LFSR Value (Interval) LFSR Value (Bits) Validity Allocated to v 0 469 01 1101 0101 Yes <![CDATA[v0]]> 1 682 10 1010 1010 No - 2 341 01 0101 0101 Yes <![CDATA[v1]]> 3 746 10 1110 1010 No - 4 373 01 0111 0101 Yes <![CDATA[v2]]> 5 … … … …

[0417] The vector u is given by u i = v i - 1, and the scrambled version y'(112) of y [e.g., the interleaved bit sequence 112] is given by:

[0418]

[0419] The second block C1(110_1) should be distributed over L radio bursts [e.g., sub-data packets] by assigning each bit c of the block depending on the index n n , the radio burst index l, and the position i within the radio burst.

[0420]

[0421] where n ∈ {0, 1, 2…183}, where n = 0 refers to the first bit c0 of C1.

[0422] The position of y’(112) [e.g., the interleaved bit sequence 112] shall depend on the index m to allocate the radio burst index l and the position i as follows:

[0423]

[0424] i(m) = 8 + (m mod 24),

[0425] where m ∈ {0, 1, 2 … 551}, and where m = 0 refers to the first bit y’0 of y’.

[0426] In both cases, i = 0 refers to the first bit of the radio burst payload. If multiple codewords are transmitted, i = 0 for the next codeword refers to the first bit after the bits that have been placed.

[0427] Although some aspects have been described in the context of a device, it is evident that these aspects also represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Similarly, aspects described in the context of a method step also represent a description of the corresponding block or item or a feature of the corresponding device. Some or all of the method steps can be performed by (or using) a hardware device such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, one or more of the most important method steps can be performed by such a device.

[0428] Depending on certain implementation requirements, embodiments of the present invention can be implemented in hardware or software. The implementation can be performed using a digital storage medium such as a floppy disk, a DVD, a Blu-Ray, a CD, a ROM, a PROM, an EPROM, an EEPROM, or a flash memory, on which an electronically readable control signal is stored, the electronically readable control signal cooperating (or being capable of cooperating) with a programmable computer system such that the respective methods are performed. Thus, the digital storage medium can be computer-readable.

[0429] Some embodiments according to the present invention include a data carrier having an electronically readable control signal, which is capable of cooperating with a programmable computer system such that one of the methods described herein is performed.

[0430] Generally, embodiments of the present invention can be implemented as a computer program product having program code, which, when the computer program product is executed on a computer, is operable to perform one of the methods. The program code can be stored, for example, on a machine-readable carrier.

[0431] Other embodiments include a computer program stored on a machine-readable carrier for performing one of the methods described herein.

[0432] In other words, an embodiment of the method of the present invention is thus a computer program having program code for performing one of the methods described herein when the computer program is executed on a computer.

[0433] Thus, a further embodiment of the method of the present invention is a data carrier (or digital storage medium, or computer-readable medium) comprising a computer program recorded thereon for performing one of the methods described herein. The data carrier, digital storage medium or recorded medium is generally tangible and / or non-transitory.

[0434] Thus, a further embodiment of the method of the present invention is a data stream or signal sequence representing a computer program for performing one of the methods described herein. The data stream or signal sequence can be configured, for example, to be transmitted via a data communication connection (e.g., via the Internet).

[0435] Further embodiments include processing means, such as a computer or programmable logic device configured or adapted to perform one of the methods described herein.

[0436] Further embodiments include a computer on which a computer program for performing one of the methods described herein is installed.

[0437] A further embodiment according to the present invention includes a device or system configured to (e.g., electronically or optically) transmit a computer program for performing one of the methods described herein to a receiver. For example, the receiver can be a computer, a mobile device, a memory device, etc. The device or system can (e.g.) include a file server for transmitting the computer program to the receiver.

[0438] In some embodiments, a programmable logic device (e.g., a field programmable gate array) can be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field programmable gate array can cooperate with a microprocessor to perform one of the methods described herein. Generally, the method is preferably performed by any hardware device.

[0439] The devices described herein can be implemented using hardware devices or using a computer or using a combination of hardware devices and a computer.

[0440] The devices described herein or any element of the devices described herein can be implemented at least in part in hardware and / or in software.

[0441] The methods described herein can be performed using hardware devices or using a computer or using a combination of hardware devices and a computer.

[0442] The methods described herein or any elements of the apparatus described herein may be performed at least in part by hardware and / or software.

[0443] The above embodiments merely illustrate the principles of the present invention. It should be understood that modifications and variations to the configurations and details described herein will be apparent to those skilled in the art. Therefore, it is only intended to be limited by the scope of the following claims, rather than by the specific details presented by the description of the embodiments herein.

[0444] References

[0445] [1]IEEE P802.15.4w Low Power Wide Area

[0446] [2]DE 10 2018 206 132

[0447] [3]S.Kobayashi, N.Loghin, R.Ikegaya, “proposal-of-ldpc-low-density-parity-code-for-lpwa”, 15-18-0289-01-004w

Claims

1. An interleaver for interleaving an LDPC - encoded bit sequence, wherein the interleaver comprises: A segmentation stage configured to segment the LDPC - encoded bit sequence into a plurality of blocks, the plurality of blocks including a first block and one or more other blocks, A first interleaver stage configured to interleave the one or more other blocks or a concatenated version thereof, A second interleaver stage configured to interleavingly combine the first block in the plurality of blocks with the interleaved bit sequence provided by the first interleaver stage block - by - block to obtain an interleaved version of the LDPC - encoded bit sequence, Wherein the first block in the plurality of blocks consists of bits of a first type, and the bits of the first type are at least one of the following: - Error - correction bits of the LDPC - encoded bit sequence, - Repeat - accumulation bits of the LDPC - encoded bit sequence, wherein the LDPC - encoded bit sequence includes information bits and error - correction bits, and - Consecutive bits of the LDPC - encoded bit sequence, with variable nodes associated therewith represented in a Tanner graph of the LDPC - encoded bit sequence, and every two of the variable nodes are interconnected with corresponding check nodes via two edges, and the connection of the variable nodes to the corresponding check nodes follows a stepped structure represented in the Tanner graph of the LDPC - encoded bit sequence.

2. The interleaver according to claim 1, Wherein the first block bypasses the first interleaver stage.

3. The interleaver according to claim 1, Wherein one block in the one or more other blocks consists of bits of a second type, and the bits of the second type - Are information bits of the LDPC - encoded bit sequence, and / or - Are represented in a Tanner graph of the LDPC - encoded bit sequence through variable nodes including pseudo - random connections to error - correction check nodes.

4. The interleaver according to claim 3, Wherein the one or more other blocks are two or more other blocks, And another block in the two or more other blocks consists of bits of the first type.

5. The interleaver according to claim 1, Wherein the first interleaver stage is a pseudo - random interleaver.

6. The interleaver according to claim 5, Wherein the pseudo - random interleaver is based on a linear shift register.

7. The interleaver according to claim 5, Wherein the pseudo - random interleaver is a block - by - block interleaver.

8. The interleaver according to claim 1, Wherein the second interleaver stage is a block - by - block interleaver.

9. The interleaver according to claim 1, Wherein the second interleaver stage is configured to distribute the interleaved version of the LDPC - encoded bit sequence over a plurality of sub - data packets.

10. The interleaver according to claim 9, Wherein the second interleaver stage is configured to distribute the bits of the first block in the plurality of blocks block - by - block over the plurality of sub - data packets in at least two rounds.

11. The interleaver according to claim 9, Wherein the second interleaver stage is configured to distribute bits of the interleaved bit sequence provided by the first interleaver stage block-by-block uniformly over the plurality of sub-data packets.

12. The interleaver according to claim 1, wherein the number of the plurality of blocks into which the LDPC-encoded bit sequence is segmented is equal to one divided by the code rate of the LDPC-encoded bit sequence.

13. The interleaver according to claim 1, wherein the one or more other blocks are two or more other blocks, wherein the first interleaver stage is configured to interleave a concatenated version of the two or more other blocks.

14. The interleaver according to claim 13, wherein the interleaver includes a concatenation stage configured to concatenate the two or more other blocks to obtain a concatenated version of the two or more other blocks.

15. An interleaver for interleaving an LDPC-encoded codeword, the LDPC-encoded codeword including a bit sequence having 736 FEC-encoded bits, wherein the interleaver includes: a segmentation stage (104) configured to segment the bit sequence z having 736 FEC-encoded bits into four equally-sized blocks, the four blocks including a block numbered one, a block numbered two, a block numbered three, and a block numbered four, The first interleaver stage, configured to pseudo-randomly scramble a bit sequence y composed of the numbered one block, the numbered three block, and the numbered four block to obtain a scrambled version y' of the bit sequence, wherein the sequence y is pseudo-randomly scrambled using a scrambling vector u, and the scrambling vector u is derived from a pseudo-random sequence v generated by a 10-bit Galois LFSR with a generating polynomial g(x) = x 10 + x 7 + 1 A second interleaver stage, configured to distribute the numbered binary blocks over L radio bursts by assigning each bit c of the numbered binary blocks depending on an index n based on the following grammar n 、a radio burst index l, and a position i within the radio burst: where n ∈ {0, 1, 2... 183}, where n = 0 refers to the first bit c0 of the block numbered two, wherein the second interleaver stage is configured to distribute a scrambled version y' of the bit sequence over the L radio bursts by assigning a radio burst index l and a position i depending on an index m based on the following syntax: i(m) = 8 + (m mod 24), where m ∈ {0, 1, 2... 551}, where m = 0 refers to the first bit y'0 of the scrambled version y' of the bit sequence.

16. A transmitter, comprising: the interleaver according to claim 1 or 15, an LDPC encoder configured to provide the LDPC-encoded bit sequence, and a transmission unit configured to transmit an interleaved version of the LDPC-encoded bit sequence using a plurality of sub-data packets, wherein the plurality of sub-data packets are transmitted non-simultaneously.

17. A deinterleaver for deinterleaving an interleaved version of an LDPC-encoded bit sequence, wherein the deinterleaver includes: a first deinterleaver stage configured to deinterleave block-by-block the interleaved version of the LDPC-encoded bit sequence to obtain a first block and an interleaved bit sequence, a second deinterleaver stage configured to deinterleave the interleaved bit sequence to obtain one or more other blocks, a concatenation stage configured to concatenate the first block with the one or more other blocks to obtain the LDPC-encoded bit sequence, wherein the first block among the plurality of blocks is composed of bits of a first type, and wherein the bits of the first type are at least one of the following: - error correction bits of the LDPC-encoded bit sequence, - the repeated cumulative bits of the LDPC - encoded bit sequence, where the LDPC - encoded bit sequence includes information bits and error - correction bits, and - the consecutive bits of the LDPC - encoded bit sequence, with variable nodes represented by the Tanner graph of the LDPC - encoded bit sequence associated therewith, each two of the variable nodes being interconnected with corresponding check nodes via two edges, and the connection of the variable nodes with the corresponding check nodes following a ladder - type structure represented by the Tanner graph of the LDPC - encoded bit sequence.

18. The de - interleaver according to claim 17, wherein the first block bypasses the second de - interleaver stage.

19. The de - interleaver according to claim 17, wherein one of the one or more other blocks consists of bits of a second type, where the bits of the second type - are the information bits of the LDPC - encoded bit sequence, and / or - are represented by the Tanner graph of the LDPC - encoded bit sequence through variable nodes including pseudo - random connections with error - correction check nodes.

20. The de - interleaver according to claim 19, wherein the one or more other blocks are two or more other blocks, wherein another of the two or more other blocks consists of bits of the first type.

21. The de - interleaver according to claim 17, wherein the first de - interleaver stage is a block - by - block de - interleaver.

22. The de - interleaver according to claim 17, wherein the second de - interleaver stage is a pseudo - random de - interleaver.

23. The de - interleaver according to claim 22, wherein the pseudo - random de - interleaver is based on a linear shift register.

24. The de - interleaver according to claim 22, wherein the pseudo - random de - interleaver is a block - by - block de - interleaver.

25. The de - interleaver according to claim 17, wherein the interleaved bit sequence is an interleaved version of a concatenated version of two or more other blocks, wherein the second de - interleaver stage is configured to de - interleave the interleaved version of the concatenated version of the two or more other blocks.

26. A receiver, comprising: a receiving unit configured to receive a plurality of sub - data packets non - simultaneously transmitted from a transmitter to the receiver, the de - interleaver according to claim 17, wherein the de - interleaver is configured to iteratively de - interleave a faded version of the LDPC - encoded bit sequence transmitted together with the plurality of sub - data packets using channel state information describing the channel between the transmitter and the receiver, and an iterative decoder configured to iteratively decode the LDPC - encoded bit sequence iteratively provided by the de - interleaver, wherein the channel state information is iteratively updated based on the decoded bit sequence provided by the iterative decoder.

27. A method for interleaving an LDPC - encoded bit sequence, wherein the method includes: segmenting the LDPC - encoded bit sequence into a plurality of blocks, the plurality of blocks including a first block and one or more other blocks, Interleave the one or more other blocks or their concatenated versions to obtain an interleaved bit sequence. Interleave the first block among the multiple blocks with the interleaved bit sequence block by block to obtain an interleaved version of the LDPC-encoded bit sequence. Where the first block among the multiple blocks consists of bits of a first type, and the bits of the first type are at least one of the following: - Error correction bits of the LDPC-encoded bit sequence. - Repeated accumulation bits of the LDPC-encoded bit sequence, where the LDPC-encoded bit sequence includes information bits and error correction bits, and - Consecutive bits of the LDPC-encoded bit sequence, with variable nodes represented by the Tanner graph of the LDPC-encoded bit sequence associated therewith, and every two of the variable nodes are interconnected with corresponding check nodes via two edges, and the connection of the variable nodes with the corresponding check nodes follows a stepped structure represented by the Tanner graph of the LDPC-encoded bit sequence.

28. A method for interleaving an LDPC-encoded codeword, the LDPC-encoded codeword including a bit sequence having 736 FEC-encoded bits, where the method includes: Segment the bit sequence z having 736 FEC-encoded bits into four equally sized blocks, the four blocks including a block numbered one, a block numbered two, a block numbered three, and a block numbered four. Pseudo-randomly scramble the bit sequence y composed of the numbered one-block, the numbered three-block, and the numbered four-block to obtain a scrambled version y' of the bit sequence, where the sequence y is pseudo-randomly scrambled using a scrambling vector u, and the scrambling vector u is derived from a pseudo-random sequence v generated by a 10-bit Galois LFSR with a generating polynomial g(x) = x 10 + x 7 + 1 assigning each bit c of the numbered dichotomous block depending on an index n according to the following grammar n and a radio burst index l and a position i within the radio burst, distributing the numbered dichotomous block over L radio bursts: Where n ∈ {0, 1, 2... 183}, and n = 0 refers to the first bit c0 of the block numbered two. Distribute the scrambled version y' of the bit sequence over the L radio bursts by assigning a radio burst index l and a position i depending on the index m based on the following syntax: i(m) = 8 + (m mod 24). Where m ∈ {0, 1, 2... 551}, and m = 0 refers to the first bit y'0 of the scrambled version y' of the bit sequence.

29. A method for deinterleaving an interleaved version of an LDPC-encoded bit sequence, where the method includes: Deinterleave the interleaved version of the LDPC-encoded bit sequence block by block to obtain a first block and an interleaved version of one or more other blocks. Deinterleave the interleaved version of the one or more other blocks to obtain the one or more other blocks. Concatenate the first block with the one or more other blocks to obtain the LDPC-encoded bit sequence. Where the first block among the multiple blocks consists of bits of a first type, and the bits of the first type are at least one of the following: - Error correction bits of the LDPC-encoded bit sequence. - Repeated accumulation bits of the LDPC-encoded bit sequence, where the LDPC-encoded bit sequence includes information bits and error correction bits, and - Consecutive bits of the LDPC-coded bit sequence have variable nodes associated therewith represented by the Tanner graph of the LDPC-coded bit sequence, and every two of the variable nodes are interconnected with corresponding check nodes via two edges, and the connection of the variable nodes with the corresponding check nodes follows a stepped structure represented by the Tanner graph of the LDPC-coded bit sequence.

30. A computer program product comprising a computer program for performing the method according to claim 27 or 28 or 29 when the computer program runs on a computer or a microprocessor.

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