Asynchronous bridge circuit, bus apparatus and system on chip

Abstract

The present disclosure relates to an asynchronous bridge circuit, a bus apparatus, and a system on chip. The asynchronous bridge circuit comprises: a first asynchronous sub-module, wherein the first asynchronous sub-module is configured to be provided in a first hardening block, and the first asynchronous sub-module is configured to operate on the basis of a first clock frequency in the first hardening block; and a second asynchronous sub-module, wherein the second asynchronous sub-module is connected to the first asynchronous sub-module in an asynchronous communication mode, the second asynchronous sub-module is configured to be provided in a second hardening block, and the second asynchronous sub-module is configured to operate on the basis of a second clock frequency in the second hardening block different from the first clock frequency.

Description

Asynchronous bridge circuit, bus device and system on chip

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202310989663.X, filed on August 8, 2023, entitled “Asynchronous Bridge Circuit, Bus Device and System on Chip,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the technical field of electronic circuits, and in particular to an asynchronous bridge circuit, a bus device, and a system on chip. Background Art

[0004] To simplify chip design and reduce power consumption, a system-on-chip (SOC) can be divided into multiple hardening blocks. Each hardening block can be designed independently and can belong to different power or clock domains, enabling independent power-up and power-down control or clock control within the hardening block. However, when communicating between hardening blocks, the varying clock frequencies within the hardening blocks can lead to timing issues.

[0005] Summary of the Invention

[0006] One of the objectives of the present disclosure is to provide an asynchronous bridge circuit, a bus device, and a system on chip to solve the data communication problem between fixed domains with different clock frequencies.

[0007] According to a first aspect of the present disclosure, there is provided an asynchronous bridge circuit, comprising:

[0008] a first asynchronous submodule, the first asynchronous submodule being configured to be disposed in a first solidified domain and configured to operate based on a first clock frequency in the first solidified domain; and

[0009] A second asynchronous submodule, wherein the second asynchronous submodule is connected to the first asynchronous submodule in an asynchronous communication manner, the second asynchronous submodule is used to be set in a second solidified domain, and the second asynchronous submodule is configured to operate based on a second clock frequency in the second solidified domain that is different from the first clock frequency.

[0010] In some embodiments, one of the first asynchronous submodule and the second asynchronous submodule includes a cache component, wherein the cache component is configured to cache data to be transmitted based on a clock frequency in a solidified domain where the cache component is located; and

[0011] The other of the first asynchronous submodule and the second asynchronous submodule includes a reading component, wherein the reading component is configured to read the data to be transmitted based on a clock frequency in the solidified domain where the reading component is located;

[0012] The size of the cache space of the cache component is larger than the size of the space occupied by the data read each time.

[0013] In some embodiments, the asynchronous bridge circuit includes a first-in-first-out FIFO asynchronous bridge, wherein the FIFO asynchronous bridge includes a write submodule and a read submodule, one of the write submodule and the read submodule serves as the first asynchronous submodule, and the other of the write submodule and the read submodule serves as the second asynchronous submodule.

[0014] In some embodiments, the write submodule includes a write synchronizer, a write controller, and a FIFO memory, wherein:

[0015] The write synchronizer is communicatively connected to the read submodule, and the write synchronizer is configured to receive a read pointer from the read submodule and synchronize the read pointer with a clock frequency in the solidified domain where the write submodule is located;

[0016] The write controller is communicatively connected to the write synchronizer, and the write controller is configured to generate a corresponding write control signal according to the synchronized read pointer, write pointer and write request signal; and

[0017] The FIFO memory is communicatively connected to the write controller, and the FIFO memory is configured to receive and store data to be transmitted in response to the write control signal instructing to write data.

[0018] In some embodiments, the write controller is further configured to convert a write pointer in binary code form into a write pointer in Gray code form.

[0019] In some embodiments, the write controller is configured to generate a corresponding write control signal according to the synchronized read pointer, write pointer, and write request signal, including:

[0020] The write controller is configured to generate a first storage status indication signal according to the synchronized read pointer and write pointer; and

[0021] The write controller is configured to generate the write control signal according to the first storage state indication signal and the write request signal;

[0022] Wherein, when the first storage status indication signal indicates that the FIFO memory is in a non-full state and the write request signal indicates that there is a write request, the write control signal instructs to write data; otherwise, the write control signal instructs not to write data.

[0023] In some embodiments, the read submodule includes a read synchronizer, a read controller, and a selector, wherein:

[0024] The read synchronizer is communicatively connected to the write submodule, and the read synchronizer is configured to receive a write pointer from the write submodule and synchronize the write pointer with a clock frequency in the solidified domain where the read submodule is located;

[0025] The read controller is communicatively connected to the read synchronizer, and the read controller is configured to generate a corresponding read control signal according to the synchronized write pointer, read pointer and read request signal; and

[0026] The selector is communicatively connected to the read controller and the FIFO memory in the write submodule, and the selector is configured to select and receive the data to be transmitted in the FIFO memory in response to the read control signal instructing to read data.

[0027] In some embodiments, the read controller is further configured to convert a read pointer in a binary code form into a read pointer in a Gray code form.

[0028] In some embodiments, the read controller is configured to generate a corresponding read control signal according to the synchronized write pointer, read pointer, and read request signal, including:

[0029] The read controller is configured to generate a second storage status indication signal according to the synchronized write pointer and read pointer; and

[0030] The read controller is configured to generate the read control signal according to the second storage state indication signal and the read request signal;

[0031] Wherein, when the second storage state indication signal indicates that the FIFO memory is in a non-empty state and the read request signal indicates that there is a read request, the read control signal instructs to read data; otherwise, the read control signal instructs not to read data.

[0032] In some embodiments, the read synchronizer is communicatively connected to a write controller in the write submodule, and the read synchronizer is configured to receive a write pointer from the write controller; and

[0033] The read controller is communicatively connected to a write synchronizer in the write submodule, and the read controller is configured to transmit a read pointer to the write synchronizer.

[0034] In some embodiments, each of the write synchronizer and the read synchronizer includes two or more synchronization registers connected in series with each other.

[0035] In some embodiments, a transmission time of transmitting the to-be-transmitted data from the write submodule to the read submodule is less than or equal to a synchronization time of either the write synchronizer or the read synchronizer.

[0036] According to a second aspect of the present disclosure, there is provided a bus device, comprising:

[0037] One or more bridge channels, wherein at least one bridge channel of the one or more bridge channels comprises an asynchronous bridge circuit as described above.

[0038] In some embodiments, the bus device further comprises:

[0039] a first bus connected to a first end of the one or more bridge channels, and configured to be arranged in the first solidification domain; and

[0040] a second bus connected to a second end of the one or more bridge channels that is different from the first end, and configured to be arranged in the second solidification domain;

[0041] The first bus and the second bus are buses of the same type or buses of different types.

[0042] In some embodiments, either of the first bus and the second bus comprises an AXI bus or an AHB bus.

[0043] According to a third aspect of the present disclosure, there is provided a system on chip, comprising:

[0044] a plurality of fixed domains, wherein at least two of the plurality of fixed domains are respectively configured to operate based on different clock frequencies; and

[0045] An asynchronous bridge circuit or bus device as described above.

[0046] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0048] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0049] FIG1 shows a schematic structural diagram of an asynchronous bridge circuit in a system on chip;

[0050] FIG2 shows a schematic diagram of a clock path in the system on chip of FIG1 ;

[0051] FIG3 shows a schematic structural diagram of an asynchronous bridge circuit across solidified domains in a system on chip according to an exemplary embodiment of the present disclosure;

[0052] FIG4 shows a schematic structural diagram of an asynchronous bridge circuit according to a specific embodiment of the present disclosure;

[0053] FIG5 shows a schematic structural diagram of a bus device according to an exemplary embodiment of the present disclosure;

[0054] FIG6 shows a schematic structural diagram of an AXI2AXI bus device according to a specific embodiment of the present disclosure.

[0055] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0056] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0057] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0058] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or use. That is, the various techniques, methods, and devices described herein are presented in an exemplary manner to illustrate various embodiments of the present disclosure and are not intended to be limiting. Those skilled in the art will understand that these are merely exemplary of, and not exhaustive of, ways to practice the present disclosure.

[0059] Technologies, methods and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods and equipment should be considered part of the authorization specification.

[0060] Typically, a system-on-chip (SoC) can be divided into multiple fixed domains, each of which can be designed independently to simplify design and improve efficiency. Different fixed domains can reside in different power or clock domains, enabling independent power-up and power-down control or clock control, thereby reducing overall SoC power consumption. However, since buses in different fixed domains may use different clock frequencies, data transmission between these two fixed domains, especially at high speeds, can be problematic.

[0061] To solve the above problem, in a system on chip, the method shown in Figure 1 can be adopted. When data needs to be transmitted between the first solidified domain 110' and the second solidified domain 120', the first bus 111' of the first solidified domain 110' passes through the domain boundary between the first solidified domain 110' and the second solidified domain 120', enters the second solidified domain 120', and is transferred to the second bus 121' of the second solidified domain 120' through the asynchronous bridge circuit 300' provided in the second solidified domain 120'. In the specific example shown in Figure 1, the first bus 111' corresponds to the master port (MP) for sending data, and the second bus 121' corresponds to the slave port (SP) for receiving data. However, it can be understood that in other cases, the master port and the slave port can also be interchanged. The first fixed domain 110' is in the first clock domain 210', a portion of the second fixed domain 120' including the first bus 111' and part of the asynchronous bridge circuit 300' is also in the first clock domain 210', and the rest of the second fixed domain 120' is in the second clock domain 220'.

[0062] However, when using the method shown in Figure 1 to transmit data across solidified domains, the following problems may occur:

[0063] First, as shown in Figure 2, the first fixed domain 110' can be provided with a first on-chip clock (OCC) 112'. The first fixed domain 110', located in the first clock domain 210', can perform clock tree synthesis based on the first on-chip clock 112'. However, because a portion of the second fixed domain 120' also resides in the first clock domain 210', the backend needs to perform clock tree synthesis (CTS) on the first on-chip clock 112' in both the first and second fixed domains 110', 120'. That is, at least some of the clocks in the second fixed domain 120' are dependent on the first on-chip clock 112' in the first fixed domain 110'. Therefore, if clock tree synthesis is re-performed on either the first or second fixed domain 110', if the corresponding clock tree length or clock skew changes, the clock tree in the other fixed domain must also be adjusted accordingly. This increases chip design difficulty and reduces design efficiency.

[0064] Second, due to differences in temperature, power supply voltage, etc. between the first solidified domain 110' and the second solidified domain 120', the deterioration coefficients of the clocks in the two solidified domains may be different. In order to meet the holding time requirements in the static timing analysis (STA) (i.e., the delay cannot be less than the holding time), it may be necessary to add corresponding delay units in the solidified domain. However, with the increase in delay units, it may be impossible to meet the setup time requirements in the static timing analysis (i.e., the delay cannot be greater than the setup time). Specifically, as shown in Figure 2, when the clock tree length of the first on-chip clock 112' exceeds a certain threshold, the data delay, the first clock tree delay (Clk dealy 1), and the second clock tree delay (Clk delay 2) therein may not be able to meet the setup time and hold time requirements at the same time.

[0065] The timing conflicts described above will result in a reduction in the chip back-end verification (signoff) frequency, directly affecting the chip's performance parameters.

[0066] In order to solve the above problems, the present disclosure proposes an asynchronous bridge circuit, which avoids clock tree synthesis across solidified domains by splitting the asynchronous bridge circuit into two asynchronous sub-modules according to the clock domain and setting the two asynchronous sub-modules in two solidified domains respectively, thereby easily achieving timing convergence.

[0067] In an exemplary embodiment of the present disclosure, as shown in FIG3 , an asynchronous bridge circuit may include a first asynchronous sub-module 310 and a second asynchronous sub-module 320. The first asynchronous sub-module 310 is configured to be located in the first fixed domain 110 and to operate based on a first clock frequency (i.e., the first on-chip clock 112) in the first fixed domain 110. The second asynchronous sub-module 320 is configured to be located in the second fixed domain 120 and to operate based on a second clock frequency (i.e., the second on-chip clock 122) in the second fixed domain 120 that is different from the first clock frequency. In other words, the asynchronous bridge circuit is split into two asynchronous sub-modules based on clock domains: the first asynchronous sub-module 310 is located in the first clock domain 210, while the second asynchronous sub-module 320 is located in the second clock domain 220. By splitting the asynchronous bridge circuit into two different asynchronous sub-modules based on clock domains and respectively placing them in corresponding fixed domains or clock domains, the asynchronous sub-modules in each fixed domain can operate according to the clock frequency of that fixed domain. As can be seen from this, there is no longer a need to perform clock tree synthesis on one fixed domain based on the on-chip clock in the other fixed domain, as shown in Figure 1. On the one hand, the clock trees in the two fixed domains can be independent of each other and no longer have dependencies. Resynthesizing the clock tree in one fixed domain will not affect the clock tree in the other fixed domain, which helps reduce design difficulty and improve design efficiency. On the other hand, since the setup and hold time paths between the two fixed domains are no longer involved, as long as the data transmission delay between the two fixed domains is less than or equal to a certain maximum delay, timing convergence can be easily achieved, avoiding setup and hold time conflicts. This data transmission delay control can be easily achieved through synthesis constraints and floorplanning in the system-on-chip.

[0068] Furthermore, the second asynchronous submodule 320 and the first asynchronous submodule 310 can be connected in an asynchronous communication manner to achieve asynchronous transmission of the data to be transmitted. In some embodiments, one of the first asynchronous submodule 310 and the second asynchronous submodule 320 may include a cache component, and the other may include a read component. The cache component may be configured to receive and cache the data to be transmitted based on the clock frequency in the solidified domain where the cache component is located, and the read component may be configured to read the required data to be transmitted from the cache component based on the clock frequency in the solidified domain where the read component is located. It is understandable that the size of the cache space of the cache component may be larger than the size of the space occupied by the data read each time, so as to utilize the cache characteristics of the cache component to achieve asynchronous transmission of data. The cache component and the read component can be set in a variety of ways, which are not limited here. In addition, in some other embodiments, other possible ways can also be used to achieve asynchronous communication between the first asynchronous submodule 310 and the second asynchronous submodule 320, which are not limited here.

[0069] In a specific embodiment, asynchronous communication between the first asynchronous sub-module 310 and the second asynchronous sub-module 320 can be implemented based on a first-in-first-out (FIFO) approach. As shown in FIG4 , the asynchronous bridge circuit may include a FIFO asynchronous bridge. The FIFO asynchronous bridge may include a write sub-module 410 (or FIFO write domain, FIFO Push Domain) and a read sub-module 420 (or FIFO read domain, FIFO Pop Domain). Depending on the direction of data transmission, one of the write sub-module 410 and the read sub-module 420 may serve as the first asynchronous sub-module 310, and the other of the write sub-module 410 and the read sub-module 420 may serve as the second asynchronous sub-module 320.

[0070] 4 , in some embodiments, the write submodule 410 may include a write synchronizer 411 , a write controller 412 , and a FIFO memory 413 . The cache component described above may include at least the FIFO memory 413 in the write submodule 410 .

[0071] The write synchronizer 411 can be communicatively connected to the read submodule 420, for example, it can be communicatively connected to the read controller 422 in the read submodule 420, and the write synchronizer 411 can be configured to receive a read pointer from the read submodule 420 (or the read controller 422) and synchronize the read pointer with the clock frequency in the solidified domain where the write submodule 412 is located, so as to subsequently compare the read pointer and the write pointer.

[0072] In some embodiments, in order to simplify the synchronization process, the read pointer received by the write synchronizer 411 can be in the form of Gray code, and the read pointer (pop ptr_g) in the form of Gray code can be generated by converting the read pointer in binary code form by the read controller 422 in the read submodule 420. However, it is understandable that the read pointer in binary code form can also be converted into other coded forms, as long as it is easy to be synchronized by the write synchronizer 411, and there is no limitation on this. In some embodiments, the write synchronizer 411 may include two synchronization registers connected in series to synchronize the read pointer in Gray code form to the clock domain where the write submodule 410 is located, avoiding the metastable state that may be generated when only a single synchronization register is used for synchronization. However, in some other embodiments, as needed, the write synchronizer 411 may also include more synchronization registers to provide sufficient transmission delay, etc. (which will be explained in detail later), and there is no limitation on this.

[0073] The write controller 412 can be communicatively connected to the write synchronizer 411, and the write controller 412 can be configured to generate a corresponding write control signal based on the synchronized read pointer, write pointer, and write request signal. In some embodiments, the write controller 412 can also be configured to convert the write pointer in binary code form into a write pointer (push ptr_g) in Gray code form. On the one hand, the write pointer in Gray code form can be transmitted to the read submodule 420 for synchronization, and on the other hand, the write pointer and the read pointer can also be easily compared. Of course, in some embodiments, the write controller 412 can also compare the write pointer and the read pointer in binary code form, which is not limited here.

[0074] In some embodiments, various signals may have high and low levels to indicate different states. For example, the write controller 412 may be configured to generate a first storage status indication signal (ready_m) based on the synchronized read pointer and write pointer. In a specific example, when the write pointer is greater than the read pointer by FIFO_DEPTH (i.e., the depth of the FIFO memory 413), it can be determined that the storage status of the FIFO memory 413 currently being written to the submodule 410 is full, and the first storage status indication signal may be set to a low level. Otherwise, it can be determined that the storage status of the FIFO memory 413 currently being written to the submodule 410 is not full, and the first storage status indication signal may be set to a high level. Accordingly, when the first storage status indication signal is low, data cannot be written to the FIFO memory 413; and when the first storage status indication signal is high, data can be written to the FIFO memory 413. Furthermore, the write controller 412 can also be configured to generate a write control signal (we_addr) based on the first storage state indication signal (ready_m) and the write request signal (valid_m). In a specific example, when a write request is currently present, the write request signal can be set to a high level; otherwise, the write request signal can be set to a low level. Further, when the first storage state indication signal indicates that the FIFO memory 413 is not full (i.e., ready_m is at a high level) and the write request signal indicates that a write request is present (i.e., valid_m is at a high level), the write control signal (we_addr) can indicate writing data, at which point the FIFO memory 413 can receive and store the data to be transmitted (the source payload shown in FIG. 4 ); otherwise, the write control signal indicates not writing data, at which point the FIFO memory 413 does not receive and store the data to be transmitted. It is understandable that in other specific examples, other methods can be used to determine the storage state of the FIFO memory 413, or to set various signals and their levels to indicate the corresponding states, which are not limited here.

[0075] The FIFO memory 413 can be communicatively connected to the write controller 412, and the FIFO memory 413 can be configured to receive and store data to be transmitted in response to a write control signal indicating the writing of data. The size of the storage space of the FIFO memory 413 can be determined based on its bit width and depth. According to the first-in-first-out principle, each data written into the FIFO memory 413 is located in the topmost empty storage unit.

[0076] 4 , the reading submodule 420 may include a reading synchronizer 421 , a reading controller 422 , and a selector 423 . The reading component described above may include at least the selector 423 in the reading submodule 420 .

[0077] The read synchronizer 421 can be communicatively connected to the write submodule 410, for example, it can be communicatively connected to the write controller 412 in the write submodule 410, and the read synchronizer 421 can be configured to receive a write pointer from the write submodule 410 (or write controller 412) and synchronize the write pointer with the clock frequency in the solidified domain where the read submodule 420 is located, so as to subsequently compare the write pointer and the read pointer.

[0078] In some embodiments, in order to simplify the synchronization process, the write pointer received by the read synchronizer 421 can be in the form of Gray code, and the write pointer in the form of Gray code can be generated by converting the write pointer in the form of binary code by the write controller 412 in the write submodule 410. However, it is understandable that the write pointer in the form of binary code can also be converted into other coded forms, as long as it is easy to be synchronized by the read synchronizer 421, and there is no limitation on this. In some embodiments, the read synchronizer 421 may include two synchronization registers connected in series to synchronize the write pointer in the form of Gray code to the clock domain where the read submodule 420 is located, avoiding the metastable state that may be generated when only a single synchronization register is used for synchronization. However, in some other embodiments, as needed, the read synchronizer 421 may also include more synchronization registers to provide sufficient transmission delay, etc. (which will be explained in detail later), and there is no limitation on this.

[0079] The read controller 422 can be communicatively connected to the read synchronizer 421, and the read controller 422 can be configured to generate a corresponding read control signal based on the synchronized write pointer, read pointer and read request signal. In some embodiments, the read controller 422 can also be configured to convert the read pointer in binary code form into a read pointer in gray code form. On the one hand, the read pointer in gray code form can be transferred to the write submodule 410 for synchronization, and on the other hand, the read pointer and the write pointer can also be easily compared. Of course, in some embodiments, the read controller 422 can also compare the read pointer and the write pointer in binary code form, which is not limited here.

[0080] As described above, various signals can have high and low levels to indicate different states. For example, the read controller 422 can be configured to generate a second storage status indication signal (valid_s) based on the synchronized write pointer and read pointer. In a specific example, when the read pointer and the write pointer are identical, it can be determined that the storage state of the FIFO memory 413 currently being written to the submodule 410 is empty, in which case the second storage status indication signal can be set to a low level. Otherwise, it can be determined that the storage state of the FIFO memory 413 currently being written to the submodule 410 is not empty, in which case the second storage status indication signal can be set to a high level. Accordingly, when the second storage status indication signal is low, data cannot be read from the FIFO memory 413; however, when the second storage status indication signal is high, data can be read from the FIFO memory 413. Furthermore, the read controller 422 can also be configured to generate a read control signal (rd_addr) based on the second storage status indication signal (valid_s) and the read request signal (ready_s). In a specific example, when there is currently a read request, the read request signal can be placed at a high level; otherwise, the read request signal can be placed at a low level. Further, when the second storage state indication signal indicates that the FIFO memory 413 is in a non-empty state (i.e., valid_s is at a high level) and the read request signal indicates that there is a read request (i.e., ready_s is at a high level), the read control signal (rd_addr) can indicate reading data, at which time the corresponding data to be transmitted (the sink payload shown in FIG4 or the fifo_mem shown in FIG6 ) can be read from the FIFO memory 413 by the selector 423; otherwise, the read control signal indicates that no data is read. It is understandable that in some other specific examples, other methods can also be used to determine the storage state of the FIFO memory 413, or various signals and their levels can be set to indicate the corresponding state, which is not limited here.

[0081] The selector 423 can be communicatively connected to the read controller 422 and the FIFO memory 413 in the write submodule 410, and the selector 423 can be configured to select and receive the data to be transmitted in the FIFO memory 413 in response to the read control signal instruction to read data. In some embodiments, the selector 423 may include a multiplexer (MUX). Accordingly, the read control signal can be transmitted to the control end of the multiplexer to achieve the selection of the data stored in the FIFO memory 413. However, it is understandable that in some other embodiments, other selection circuits can also be used to select the corresponding data to be transmitted, which is not limited here. In addition, according to the first-in-first-out principle, the data read each time can be the data in the full storage unit of the bottom layer of the FIFO memory 413, and the data read each time only occupies a part of the storage space of the FIFO memory 413, thereby achieving asynchronous transmission of data.

[0082] Based on the asynchronous bridge circuit shown in FIG4 , to ensure correct timing within the SoC, it is sufficient to ensure that the transmission time of the data to be transmitted from the write submodule 410 to the read submodule 420 is less than or equal to the synchronization time of either the write synchronizer 412 or the read synchronizer 422. In other words, the time required for the selector 423 to read the corresponding data to be transmitted from the FIFO memory 413 is less than or equal to the synchronization time of either the write synchronizer 412 or the read synchronizer 422. This can be easily achieved through comprehensive constraints and floorplanning within the SoC.

[0083] According to another aspect of the present disclosure, a bus device is also provided. As shown in FIG5 , in an exemplary embodiment, the bus device may include one or more bridge channels 530, wherein at least one of the one or more bridge channels 530 may include the asynchronous bridge circuit described above. In other words, the bridge channel 530 can be split into two parts based on clock domains, with the first asynchronous sub-module and the second asynchronous sub-module respectively operating in corresponding fixed domains based on corresponding clock frequencies without affecting each other, thereby facilitating simple timing closure in each asynchronously operating fixed block.

[0084] In some embodiments, the bus can be included in a bus device. For example, as shown in Figure 5, the bus device can also include a first bus 510 and a second bus 520, the first bus 510 is connected to the first end of one or more bridge channels 530, and the first bus 510 is used to be set in a first solidified domain, and the second bus 520 is connected to the second end of one or more bridge channels 530 that is different from the first end, and the second bus 520 is used to be set in a second solidified domain. In some embodiments, the first bus 510 and the second bus 520 can be buses of the same type. In other embodiments, the first bus 510 and the second bus 520 can also be buses of different types, which is not limited here. Among them, the number of bridge channels 530 in the bus device can be determined according to the specific types of the first bus 510 and the second bus 520 bridged.

[0085] In a specific example, as shown in FIG6 , an asynchronous bridge circuit 300 can be used to bridge between an Advanced eXtensible Interface (AXI) bus and an AXI bus. The two AXI buses can be used in different fixed domains or power domains and have different clock frequencies. That is, the asynchronous bridge circuit 300 can serve as a Power Domain Bridge (PDB). In the specific example shown in FIG6 , the bus device can include a total of five bridge channels. Each bridge channel can be used to bridge a channel in one AXI bus with a corresponding channel in another AXI bus, including a read address channel (AR Channel), a read data channel (R Channel), a write address channel (AW Channel), a write data channel (W Channel), and a write response channel (B Channel). Each bridge channel can include the asynchronous bridge circuit described above. As shown in FIG6 , in the read address channel (AR Channel), the write submodule of the asynchronous bridge circuit can be set at the master end (AXI2AXI_PDB_MP), and the read submodule can be set at the slave end (AXI2AXI_PDB_SP); in the read data channel (R Channel), the write submodule of the asynchronous bridge circuit can be set at the slave end (AXI2AXI_PDB_SP), and the read submodule can be set at the master end (AXI2AXI_PDB_MP); in the write address channel (AW Channel), the write submodule of the asynchronous bridge circuit can be set at the master end (AXI2AXI_PDB_MP), and the read submodule can be set at the slave end (AXI2AXI_PDB_SP); in the write data channel (W Channel), the write submodule of the asynchronous bridge circuit can be set at the master end (AXI2AXI_PDB_MP), and the read submodule can be set at the slave end (AXI2AXI_PDB_SP); and in the write response channel (B Channel), the write submodule of the asynchronous bridge circuit can be set at the master end (AXI2AXI_PDB_MP), and the read submodule can be set at the slave end (AXI2AXI_PDB_SP). In the embodiment of the present invention, the write submodule of the asynchronous bridge circuit can be set at the slave end (AXI2AXI_PDB_SP), and the read submodule can be set at the master end (AXI2AXI_PDB_MP). Here, the master end can be in one fixed domain or clock domain, and the slave end can be in another fixed domain or clock domain. It is understood that in some other embodiments, the bus device can also be used to bridge other types of buses, including AHB buses, for example, it can be used to implement bridging between an AXI bus and an AHB bus, or to implement bridging between two AHB buses, etc., without limitation here.

[0086] According to another aspect of the present disclosure, a system-on-chip (SoC) is also provided. In an exemplary embodiment, as shown in FIG3 , the SoC may include multiple fixed domains (e.g., a first fixed domain 110 and a second fixed domain 120) and the asynchronous bridge circuit or bus device described above. At least two of the multiple fixed domains are configured to operate at different clock frequencies.

[0087] In some embodiments, as the depth of the FIFO memory in the asynchronous bridge circuit increases, in order to maintain the correctness of the voltage in the on-chip system, a level shift cell for deflecting the voltage and an isolation cell for isolating the voltage may be added accordingly, without limitation here.

[0088] The technical solution disclosed in the present invention provides a bus connection method between different solidified domains. By splitting the asynchronous bridge circuit into different sub-modules according to the clock domain and setting these sub-modules in the corresponding solidified domains, the timing problems caused by data transmission between solidified domains with different clocks can be avoided while ensuring the bus connection bandwidth. Since each sub-module only needs to operate according to the clock signal in the solidified domain where it is located, and different sub-modules are connected using asynchronous communication, the back-end only needs to perform clock tree synthesis based on its corresponding clock signal within each solidified domain. Different solidified domains are decoupled and there is no dependency on the clock tree, which can effectively reduce the design difficulty and improve the design efficiency. Moreover, since there are no setup time and hold time paths between any different solidified domains, timing convergence can be easily achieved. The timing path between cross-clock domains only needs to meet a certain maximum delay to ensure the correctness of the timing, and this maximum delay can be simply implemented based on the comprehensive constraints and layout planning of the system on chip.

[0089] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0090] The terms "front," "back," "top," "bottom," "above," "below," and the like, if any, in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0091] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be bound by any expressed or implied theory presented in the preceding technical field, background, summary, or detailed description.

[0092] As used herein, the word "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The word "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0093] The above description may indicate elements or nodes or features that are "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element / node / feature can be mechanically, electrically, logically, or otherwise connected to another element / node / feature in a direct or indirect manner to allow interaction, even if the two features may not be directly connected. In other words, "coupled" is intended to encompass both direct and indirect connections of elements or other features, including connections utilizing one or more intermediate elements.

[0094] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0095] Those skilled in the art will appreciate that the boundaries between the above-mentioned operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are also possible. Therefore, this specification and the accompanying drawings should be considered illustrative, not restrictive.

[0096] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An asynchronous bridge circuit, comprising: A first asynchronous submodule, the first asynchronous submodule is used to be set in a first solidified domain, and the first asynchronous submodule is configured to run based on a first clock frequency in the first solidified domain; as well as A second asynchronous submodule, wherein the second asynchronous submodule is connected to the first asynchronous submodule in an asynchronous communication manner, the second asynchronous submodule is used to be set in a second solidified domain, and the second asynchronous submodule is configured to operate based on a second clock frequency in the second solidified domain that is different from the first clock frequency.

2. The asynchronous bridge circuit according to claim 1, wherein: One of the first asynchronous submodule and the second asynchronous submodule includes a cache component, and the cache component is configured to cache the data to be transmitted based on the clock frequency in the solidified domain where the cache component is located; as well as The other of the first asynchronous submodule and the second asynchronous submodule comprises a reading component, wherein the reading component is configured to read the data to be transmitted based on a clock frequency in the solidified domain where the reading component is located; The size of the cache space of the cache component is larger than the size of the space occupied by the data read each time.

3. The asynchronous bridge circuit according to claim 1, wherein: The asynchronous bridge circuit includes a first-in-first-out FIFO asynchronous bridge, wherein the FIFO asynchronous bridge includes a write submodule and a read submodule, one of the write submodule and the read submodule serves as the first asynchronous submodule, and the other of the write submodule and the read submodule serves as the second asynchronous submodule.

4. The asynchronous bridge circuit according to claim 3, wherein: The writing submodule includes a writing synchronizer, a writing controller and a FIFO memory, wherein: The write synchronizer is communicatively connected to the read submodule, and the write synchronizer is configured to receive a read pointer from the read submodule and synchronize the read pointer with a clock frequency in the solidified domain where the write submodule is located; The write controller is communicatively connected to the write synchronizer, and the write controller is configured to generate a corresponding write control signal according to the synchronized read pointer, write pointer and write request signal; and The FIFO memory is communicatively connected to the write controller, and the FIFO memory is configured to receive and store data to be transmitted in response to the write control signal indicating writing data.

5. The asynchronous bridge circuit according to claim 4, wherein: The write controller is further configured to convert a write pointer in binary code form into a write pointer in Gray code form.

6. The asynchronous bridge circuit according to claim 4, wherein: The write controller is configured to generate a corresponding write control signal according to the synchronized read pointer, write pointer and write request signal, including: The write controller is configured to generate a first storage status indication signal according to the synchronized read pointer and write pointer; and The write controller is configured to generate the write control signal according to the first storage state indication signal and the write request signal; Wherein, when the first storage status indication signal indicates that the FIFO memory is in a non-full state and the write request signal indicates that there is a write request, the write control signal indicates to write data; otherwise, the write control signal indicates not to write data.

7. The asynchronous bridge circuit according to claim 3, wherein: The reading submodule includes a reading synchronizer, a reading controller and a selector, wherein: The read synchronizer is communicatively connected to the write submodule, and the read synchronizer is configured to receive a write pointer from the write submodule and synchronize the write pointer with a clock frequency in a solidified domain where the read submodule is located; The read controller is communicatively connected to the read synchronizer, and the read controller is configured to generate a corresponding read control signal according to the synchronized write pointer, read pointer and read request signal; and The selector is communicatively connected to the read controller and the FIFO memory in the write submodule, and the selector is configured to select and receive the data to be transmitted in the FIFO memory in response to the read control signal indicating the read data.

8. The asynchronous bridge circuit according to claim 7, wherein: The read controller is further configured to convert a read pointer in binary code form into a read pointer in Gray code form.

9. The asynchronous bridge circuit according to claim 7, wherein: The read controller is configured to generate a corresponding read control signal according to the synchronized write pointer, read pointer and read request signal, including: The read controller is configured to generate a second storage state pointer according to the synchronized write pointer and read pointer. signal; and The read controller is configured to generate the read control signal according to the second storage state indication signal and the read request signal; Wherein, when the second storage state indication signal indicates that the FIFO memory is in a non-empty state and the read request signal indicates that there is a read request, the read control signal indicates to read data; otherwise, the read control signal indicates not to read data.

10. The asynchronous bridge circuit according to claim 7, wherein: The read synchronizer is communicatively connected to a write controller in the write submodule, and the read synchronizer is configured to receive a write pointer from the write controller; and The read controller is communicatively connected to a write synchronizer in the write submodule, and the read controller is configured to transmit a read pointer to the write synchronizer.

11. The asynchronous bridge circuit according to claim 10, wherein: Each of the write synchronizer and the read synchronizer includes two or more synchronization registers connected in series to each other.

12. The asynchronous bridge circuit according to claim 10, wherein: The transmission time of the data to be transmitted from the writing submodule to the reading submodule is less than or equal to the synchronization time of any one of the writing synchronizer and the reading synchronizer.

13. A bus device, comprising: One or more bridge channels, wherein at least one bridge channel of the one or more bridge channels comprises an asynchronous bridge circuit according to any one of claims 1 to 12.

14. The bus device according to claim 13, further comprising: a first bus connected to a first end of the one or more bridge channels, and configured to be arranged in the first solidification domain; as well as a second bus connected to a second end of the one or more bridge channels different from the first end, and the second bus is used to be arranged in the second solidification domain; The first bus and the second bus are buses of the same type or buses of different types.

15. The bus device according to claim 14, wherein: Either of the first bus and the second bus includes an AXI bus or an AHB bus.

16. A system on chip, comprising: a plurality of fixed domains, wherein at least two of the plurality of fixed domains are respectively configured to operate based on different clock frequencies; and An asynchronous bridge circuit according to any one of claims 1 to 12 or a bus device according to any one of claims 13 to 15.

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