Phased array transceiver system having feedback path

Abstract

A phased array transceiver system having a feedback path, comprising at least one common TR channel, a plurality of branch TR channels, a power division and combination network, a feedback network, a feedback channel, and an error processing module, wherein the common TR channel sends a signal to the branch TR channels by means of the power division and combination network; each of the plurality of branch TR channels sends a signal from the outside to the common TR channel by means of the power division and combination network; one end of the feedback network is selectively connected to an antenna port of any branch TR channel by controlling a switch state, and the other end of the feedback network is connected to the feedback channel; the input end of the error processing module is connected to the output end of the common TR channel, and the output end of the error processing module is connected to the input end of the feedback channel. According to the phased array transceiver system having a feedback path of the present application, adding the error processing module solves the problem of feedback function deterioration or failure caused by insufficient chip isolation.

Description

A phased array transceiver system with feedback path Technical Field

[0001] The present application relates to the field of radio frequency technology, and in particular to a phased array transceiver system with a feedback path. Background Art

[0002] Phased array systems modify the radiation pattern by controlling the feed phase of each radiating element in the array, allowing signals to be received and transmitted in a specified direction, achieving spatial beam scanning of the signal. Commonly used phased array systems can be categorized as single-beam or multi-beam scanning systems, depending on the application scenario. Each beam can contain 1, 2, 4, 8, or 16 TR channels. Each TR (transmitter / receiver) channel can integrate common modules found in TR chips, such as switches, amplifiers, amplitude control units, and phase control units, as needed.

[0003] Referring to Figure 1 , in a phased array system, there is an application scenario in which a feedback system 20 is added to the antenna port of the phased array system 10. This system can sample the transmit signal power at the antenna port in real time to detect and calibrate the power amplitude and phase. Feedback system 20 can also provide an input signal to the antenna port to calibrate the receiving function of branch TR channel 13.

[0004] Because the transmitted signal is output from the antenna port through the feedback system 20 via coupling or detection, significant losses occur during this process. The output signal power of the feedback system 20 is low and easily interfered with by other noise signals. Furthermore, since the feedback system 20 and the phased array system 10 are integrated into the same chip, signals overlap and couple between different submodules in the system, significantly affecting the chip isolation. This results in poor feedback signal quality, making it impossible to accurately detect and calibrate the amplitude and phase of the transmitted signal.

[0005] Therefore, how to improve the quality of the feedback signal and solve the problem of feedback function deterioration or failure caused by insufficient isolation between the TR channels of the phased array system is the main problem to be solved by this patent.

[0006] Summary of the Invention

[0007] To address the shortcomings of the prior art, the present application aims to provide a phased array transceiver system with a feedback path. An error processing module is inserted between the output of a common TR channel and the input of a feedback channel to offset error signals mixed into the feedback signal. This improves the feedback function deterioration or failure problem in existing phased array systems caused by insufficient isolation between the feedback loop and other system pathways.

[0008] To achieve the above-mentioned object, the present application provides a phased array transceiver system with a feedback path, comprising: a phased array system and a feedback system, and an error processing module;

[0009] The feedback system includes a feedback network and a feedback channel; when the phase control system transmits a signal, the feedback system samples the transmitted signal and detects it;

[0010] The feedback network is used to select any one of the TR channels and the feedback channel. One end of the feedback network is selectively connected to the antenna port of any one of the TR channels of the phased array system by controlling the switch state, and the other end is connected to the feedback channel. In the transmitting state, the feedback network is used to output a first sampling signal to the feedback channel. The difference between the first sampling signal and the ideal sampling signal is the error signal.

[0011] The feedback channel performs at least one of amplification, amplitude modulation, and phase modulation on the sampling signal;

[0012] The error processing module, in the transmitting state, samples the signal input to the branch TR channel as a second sampling signal, performs error processing on the second sampling signal, and then feeds it back to the feedback channel. The error processing includes performing processing with a phase opposite to that of the error signal and the same amplitude.

[0013] Furthermore, the phased array system includes: in the transmitting state, at least one common TR channel, a power splitter / combiner network, a plurality of branch TR channels, and an antenna corresponding to each branch TR channel, which are sequentially connected along the signal propagation direction.

[0014] Furthermore, the input end of the error processing module is connected to the input end or output end of any element before the branch TR channel, and the output end is connected to the input end of the feedback channel.

[0015] Furthermore, the input end of the error processing module is connected to the output end of the common TR channel, and the output end is connected to the input end of the feedback channel.

[0016] Furthermore, the error processing module includes: a phase adjustment unit and an amplitude adjustment unit, the phase adjustment unit performs a phase shift processing on the second sampling signal with a phase opposite to that of the error signal, and the amplitude adjustment unit performs processing with the same amplitude as that of the error signal.

[0017] Furthermore, the amplitude attenuation performed by the amplitude adjustment unit on the second sampling signal is the same as the amplitude of the error signal.

[0018] Furthermore, the phase processing performed by the phase adjustment unit on the second sampling signal is opposite to the phase direction of the error signal.

[0019] Furthermore, the amplitude adjustment unit includes an attenuator, and the phase adjustment unit includes a phase shifter.

[0020] Furthermore, the feedback network includes: multiple groups of switches in cascade connection, realizing at least one input and multiple outputs, and selecting one channel by controlling the state of the switches.

[0021] Furthermore, the feedback channel includes at least one branch, each branch including one of an amplifier, an amplitude adjustment unit, and a phase adjustment unit, or a combination thereof;

[0022] When the feedback channel includes more than two branches, the feedback channel further includes a switch for selecting one of the branches.

[0023] Furthermore, the feedback system is connected to the phased array system via a coupler or a detector.

[0024] To achieve the above objectives, the present application further provides a method for confirming an error state of the above system, comprising:

[0025] Determine the TR branch channel to be tested;

[0026] Inputting a first control signal into the system to control the TR branch channel to be tested and the error processing module to be closed, and the remaining TR branch channels to be opened;

[0027] inputting a radio frequency test signal into the phased array system;

[0028] inputting a second control signal to the phased array system to control the error processing module to turn on;

[0029] Scanning the phase and amplitude of the output signal of the error processing module until they reach preset values;

[0030] The phase and amplitude of the signal output by the error processing module when the preset value is reached are recorded and stored as the phase and amplitude of the error signal of the TR branch channel to be measured.

[0031] Furthermore, it also includes: repeating the steps of determining the TR branch channel to be tested, inputting the first control signal, the RF test signal, the second control signal, scanning, recording and storing, until the error signal status of all TR branch channels is determined.

[0032] Furthermore, the method further includes: testing the amplitude value of the signal at the output end of the feedback channel, and when the amplitude value is the lowest, determining whether the phase and amplitude of the output signal of the error processing module at this time reach preset values.

[0033] To achieve the above-mentioned objectives, the present application further provides an error state confirmation device for the phased array transceiver system with a feedback path as described above, comprising:

[0034] A first amplitude and phase control module is configured to: receive an external instruction to determine whether a TR branch to be tested is open, input a first control signal to the phased array system, control the TR branch channel to be tested and the error processing module to be closed, and open the remaining TR branch channels;

[0035] The second amplitude and phase control module is used to control the radio frequency test signal to be input into the phased array system, and input a second control signal to the phased array system to control the error processing module to be turned on.

[0036] To achieve the above objectives, the present application also provides a computer-readable storage medium having computer program instructions stored thereon, and the computer program instructions can be executed by a processor to implement the above method.

[0037] The phased array transceiver system with feedback path of the present application has the following technical effects compared with the prior art:

[0038] A phased array transceiver system with a feedback path in a specific embodiment of the present application adds an error processing module. When the phased array system is operating normally, the module receives the amplitude control code and phase control code corresponding to each branch TR channel found during the error state confirmation process. The module then performs error processing (processing with a phase opposite to that of the error signal but the same amplitude as the error signal, which is the difference between the first sampled signal and the ideal signal in the transmitting state) on the second sampled signal sampled at the input of the phased array system. The error signal is then input into the feedback system to offset the error signal, which is then fed back to the phased array system. This offsets errors in the output sampled signal (i.e., the first sampled signal) caused by isolation issues, improves the isolation between the feedback loop of the phased array system and other system pathways, enables the phased array system to obtain a relatively accurate feedback signal, enhances the calibration of the phased array system, and alleviates feedback function degradation or failure caused by insufficient chip isolation.

[0039] Other features and advantages of the present application will be set forth in the following description, and in part will be apparent from the description, or may be learned by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings:

[0041] FIG1 is a schematic diagram of the structure of a phased array system in the prior art;

[0042] FIG2 is a schematic diagram of the structure of a phased array transceiver system with a feedback path according to an embodiment of the present application;

[0043] FIG3 is another structural diagram of a phased array transceiver system with a feedback path according to an embodiment of the present application;

[0044] FIG4 is a schematic diagram of the structure of an error processing module according to an embodiment of the present application;

[0045] FIG5 is a schematic diagram of an error cancellation principle according to an embodiment of the present application;

[0046] FIG6 is a schematic diagram of a gating network structure composed of a one-to-two switch according to an embodiment of the present application;

[0047] FIG7 is a schematic diagram of a gating network structure composed of a one-to-two switch and a one-to-four switch according to a first embodiment of the present application;

[0048] FIG8 is a schematic diagram of a gating network structure composed of a one-to-two switch according to an embodiment of the present application;

[0049] FIG9 is a schematic diagram of the structure of a phased array transceiver system with a feedback path according to a second embodiment of the present application;

[0050] FIG10 is a schematic diagram of the structure of a phased array transceiver system with a feedback path according to a third embodiment of the present application;

[0051] FIG11 is a schematic diagram of the structure of a phased array transceiver system with a feedback path according to a fourth embodiment of the present application;

[0052] FIG12 is a schematic structural diagram of an error state confirmation device according to a fifth embodiment of the present application;

[0053] FIG13 is a schematic diagram of the structure of a phased array system with a feedback path according to a sixth embodiment of the present application;

[0054] FIG14 is a flow chart of an error status confirmation method according to a sixth embodiment of the present application. DETAILED DESCRIPTION

[0055] The preferred embodiments of the present application are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application and are not used to limit the present application.

[0056] The following describes embodiments of the present application in more detail with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of protection of the present application.

[0057] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0058] In the accompanying drawings, some structural or method features are shown in a specific arrangement and / or order. However, it should be understood that such specific arrangement and / or order may not be required. In some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0059] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements or data, these elements or data should not be limited by these terms. These terms are used only to distinguish one feature from another. For example, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature without departing from the scope of the exemplary embodiments.

[0060] It should be noted that the modifications of "one" and "plurality" mentioned in this application are illustrative rather than restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more." "Plurality" should be understood as two or more.

[0061] The present application relates to a phased array system. In an existing phased array transceiver system with a feedback path, due to the influence of isolation (ISO), there is an amplitude and phase difference between the real signal (Pout_real) or sampling signal collected by the feedback channel and the target signal or ideal signal (Pout_ideal). If the phased array system adjusts its configuration based on the collected signal with errors, it will cause calibration errors of the phased array system, thereby affecting the signal quality of the phased array system. To solve this problem, the present application adds an error processing module to offset the influence of isolation, so that the phased array system can obtain a relatively real feedback signal and improve the calibration effect.

[0062] The following are the parameters involved or may be involved in this application:

[0063] Isolation ISO, in dB. Because phased array systems are non-ideal, in addition to being connected through the normal signal path, any two points in the system will also experience signal coupling. Isolation represents the strength of this non-ideal coupling.

[0064] Power P (unit: dBm), such as PIN, represents the input power of the signal stream;

[0065] Module gain G (unit: dB), such as G_COM represents the gain of the common TR channel;

[0066] Signal strength E (unit: dBm) is the signal strength of the coupling between two points caused by isolation.

[0067] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0068] Example 1

[0069] FIG2 is a schematic diagram of the structure of a phased array transceiver system with a feedback path according to an embodiment of the present application. As shown in FIG2 , the phased array transceiver system with a feedback path according to this embodiment includes:

[0070] Phased array system 10 and feedback system 20, and error processing module 30;

[0071] The feedback system 20 includes a feedback network 21 and a feedback channel 22. When the phased array system 10 transmits a signal, the feedback system 20 samples the transmitted signal and detects it.

[0072] The feedback network 21 is used to select any branch TR channel 13 and the feedback channel 22 of the phased array system 10. In the transmitting state, it is used to output a first sampling signal to the feedback channel 22. The difference between the first sampling signal and the ideal sampling signal is the error signal. Specifically, the feedback network 21 is a switching unit. One end of the feedback network 21 is selectively connected to the antenna port of any branch TR channel 13 of the phased array system 10 by controlling the switch state, and the other end is connected to the feedback channel 22. The ideal sampling signal is the transmitted signal sampled without error.

[0073] The feedback channel 22 performs at least one of amplification, amplitude modulation, and phase modulation on the first sampling signal. That is, each branch of the feedback channel 22 may include an amplifier to amplify the sampling signal, an amplitude adjustment unit such as an attenuator to adjust the amplitude of the sampling signal, or a phase adjustment unit to adjust the phase of the sampling signal. Alternatively, each branch may include an amplifier, an attenuator, and a phase shifter, or two of the three. Other components may be added to the feedback channel 22 as needed to perform other adjustments to the sampling signal.

[0074] In the transmitting state, the error processing module 30 samples the signal input to the branch TR channel 13 as a second sampling signal, performs error processing on the second sampling signal, and then feeds it back to the feedback channel 22. The error processing includes processing the second sampling signal to have a phase opposite to that of the error signal and the same amplitude as the error signal. That is, when the phased array system 10 is operating normally, the second sampling signal sampled at the input of the phased array system 10 is error processed (processed to have a phase opposite to that of the error signal and an amplitude opposite to the error signal). After processing, the second sampling signal is input to the feedback system 20 to offset the error signal, and then fed back to the phased array system 10. This offsets errors in the output sampling signal (e.g., the first sampling signal) caused by isolation issues, improves the isolation between the feedback loop of the phased array system 10 and other system pathways, enables the phased array system 10 to obtain a relatively accurate feedback signal, enhances the calibration performance of the phased array system 10, and alleviates the problem of feedback function degradation or failure caused by insufficient chip isolation. 2 , the phased array system 10 includes: in a transmitting state, at least one common TR channel 11 , a power splitter / combiner network 12 , and a plurality of branch TR channels 13 , which are sequentially connected along a signal propagation direction.

[0075] The common TR channel (COM) 11 is the common transceiver channel of the phased array system 10. It is connected to each branch TR channel (FEM) 13 through a power splitter / combiner network 12. In the transmitting system, it can pre-process the transmission signal and input multiple branch TR channels 13 through the power splitter / combiner network 12. Then, it is transmitted through the antenna 14. In the receiving system, the signals received by multiple branch TR channels 13 through the antenna 14 are synthesized by the power splitter / combiner network 12 and input into the common TR channel 11.

[0076] The power splitter / combiner network (PD) 12 acts as a power splitter in the transmitting system, evenly dividing the output signal of the common TR channel 11 to each branch TR channel 13; and acts as a combiner in the receiving system, combining the output signals of multiple branch TR channels 13 and inputting them into the common TR channel 11.

[0077] The feedback system 20 includes a feedback network 21 and a feedback channel 22 .

[0078] Feedback network (FBSW) 21 is a gating network composed of switches. One end of the feedback network 21 selectively connects to the connection port (also known as the antenna port) between any branch TR channel 13 and antenna 14 by controlling the switch state. The other end of the feedback network 21 maintains a connection to feedback channel (FB) 22. When used in a transmitting system, feedback network 21 can sample the output signal of the antenna port of any branch TR channel 13 and transfer it to feedback channel 22. When used in a receiving system, feedback network 21 can transmit the output signal of feedback channel 22 to the antenna port of any branch TR channel 13 as the receiving input signal for that branch TR channel.

[0079] In the transmitting system, the feedback channel 22 further amplifies, adjusts the amplitude, or modulates the phase of the signal transmitted by the branch TR channel 13 sampled by the feedback network 21. In the receiving system, the feedback channel 22 pre-processes the signal (i.e., further amplifies, adjusts the amplitude, or modulates the phase) and then inputs it to the branch TR channel 13 through the feedback network 21. Referring to FIG3 , the error processing module (ERROR CANCEL) 30 is configured to: in the transmitting system, after sampling the output port signal of the common TR channel 11, perform amplitude and phase processing based on the received amplitude control code and phase control code, including performing amplitude attenuation on the second sampled signal in accordance with the amplitude control code, and performing phase processing on the second sampled signal in the opposite direction of the error signal in accordance with the phase control code. After processing, the signal is then input to the feedback channel 22 to offset the error signal originally sampled from the output port signal of the phased array system 10 and input into the feedback channel 22. At this time, the amplitude control code is the amplitude control code corresponding to the branch TR channel 13 , and the phase control code is the phase control code corresponding to the branch TR channel 13 , which are used to offset the error signal of the branch TR channel 13 .

[0080] Table 1: Correspondence between branch TR channel, amplitude control code, and phase control code

[0081] In some embodiments, the phased array system 10 may include N branch TR channels 13, each branch TR channel 13 having a corresponding amplitude control code and a phase control code. For example, as shown in Table 1, the amplitude control code corresponding to the first branch TR channel 13 is f1, and the corresponding phase control code is d1; the amplitude control code corresponding to the second branch TR channel 13 is f2, and the corresponding phase control code is d2, ...; the amplitude control code corresponding to the nth branch TR channel 13 is fn, and the corresponding phase control code is dn. In the transmitting state, when the second sampling signal is input to the first branch TR channel 13 and the other branch TR channels 13 are closed, the error processing module 30 receives the corresponding amplitude control code f1 and phase control code d1 to offset the error signal of the first branch TR channel 13; when the second sampling signal is input to the second branch TR channel 13 and the other branch TR channels 13 are closed, the error processing module 30 receives the corresponding amplitude control code f2 and phase control code d2 to offset the error signal of the second branch TR channel 13;...when the second sampling signal is input to the nth branch TR channel 13 and the other branch TR channels 13 are closed, the error processing module 30 receives the corresponding amplitude control code fn and phase control code dn to offset the error signal of the nth branch TR channel 13.

[0082] Each amplitude control code can correspond to an adjusted amplitude value. For example, amplitude control code f1 corresponds to an amplitude adjustment of 3dB, amplitude control code f2 corresponds to an amplitude adjustment of 5dB, and so on. Phase control code d1 corresponds to a phase adjustment of 10°, phase control code d2 corresponds to a phase adjustment of 60°, and so on. The amplitude control code and phase control code can be digital signals, and the number of bits of the amplitude control code and phase control code can be set according to the adjustment accuracy. For example, when the amplitude and phase have 16 adjustment positions, the amplitude control code and phase control code are both 4-bit digital signals. The phase control codes and amplitude control codes can be the same or different between different channels.

[0083] In embodiments of the present application, the isolation of the phased array transceiver system can be pre-tested by testing the amplitude and phase of the signal coupled to the output port of the phased array system via other paths. The testing method can be found in Example 6, thereby determining the amplitude control code and phase control code corresponding to each branch TR channel 13. In some embodiments, when the branch TR channel 13 is closed and the error processing module 30 receives the corresponding amplitude control code and phase control code, the amplitude of the output signal of the feedback channel 22 is the lowest. In an embodiment of the present application, the error processing module 30 processes the error signal based on the input corresponding amplitude control code and corresponding phase control code. Therefore, it is not difficult to understand that different amplitude control codes and phase control codes have different processing effects on the error signal. When the isolation of the phased array transceiver system is tested in advance, all combinations of the amplitude control code and phase control code of the error processing module 30 can be traversed. When the amplitude of the power output signal of the feedback channel 22 is tested to be the lowest, it is determined that the amplitude control code and phase control code at this time are the target control code or target control word corresponding to the branch TR channel 13. When the error processing module 30 receives the target control code or target control word, it can offset the error signal of the corresponding branch TR channel 13.

[0084] Referring to FIG4 , the error processing module 30 of this embodiment includes an amplitude adjustment unit 31 and a phase adjustment unit 32. During normal operation of the phased array transceiver system, the phased array transceiver system is in a transmitting state. The error processing module 30 receives the corresponding amplitude control code to the amplitude adjustment unit 31 and the corresponding phase control code to the phase adjustment unit 32. The amplitude adjustment unit 31 processes the output port signal from the common TR channel 11, causing its amplitude attenuation to be equal to the amplitude of the error signal. The phase adjustment unit 32 then processes the signal, causing its phase to be opposite to that of the error signal. This allows the processed signal to enter the feedback channel 22 and offset the original error signal, thereby improving the feedback function degradation or failure caused by insufficient chip isolation. In the example shown in FIG4 , amplitude adjustment is performed first and then phase adjustment, but this is not limited to this approach. Phase adjustment can also be performed first and then amplitude adjustment. In other words, the positions of the phase shifter and attenuator in the circuit can be interchanged.

[0085] In the embodiment of the present application, the amplitude adjustment unit 31 adopts an active attenuator or a passive attenuator, and the phase adjustment unit 32 adopts an active phase shifter or a passive phase shifter. The accuracy of the attenuator and the phase shifter determines the final calibration effect.

[0086] You can choose to use a 6-bit attenuator with a step of 0.5dB, and the attenuation can reach 31.5dB.

[0087] Optionally, a 6-bit phase shifter with a step of 5.625° can be used, and the phase can cover 360°.

[0088] 5 , the following example illustrates the effect of introducing an error processing module into a phased array system with a feedback path.

[0089] Without the error processing module, assuming the feedback channel isolation is -20dB (at this isolation, the error signal amplitude is 1 / 10 of the main signal amplitude):

[0090] Pout_ideal=Acos(wt),

[0091] E=A / 10cos(wt+θ),

[0092] -E=A / 10cos(wt+θ+180°),

[0093] Where A is the amplitude of Pout_ideal (target signal), i.e., the amplitude of the main signal, w is the frequency of Pout_ideal, t is time, E is the error signal, and θ = 0° to 360° is the phase difference between the error signal and the target signal.

[0094] The target signal and the error signal are superimposed to obtain the real signal Pout_real:

[0095] That is, Pout_real=Pout_ideal+E=Bcos(wt+φ)=Acos(wt)+A / 10cos(wt+θ),

[0096] When θ=0°, Bcos(wt+φ)=Acos(wt)+A / 10cos(wt)=1.1Acos(wt)

[0097] When θ=180°, Bcos(wt+φ)=Acos(wt)-A / 10cos(wt)=0.9Acos(wt)

[0098] When θ=90°, Bcos(wt+φ)=Acos(wt)+A / 10cos(wt+90°)

[0099] =Acos(wt)+A / 10sin(wt)≈Acos(wt+5.7°)

[0100] When θ=270°, Bcos(wt+φ)=Acos(wt)+A / 10cos(wt+270°)

[0101] =Acos(wt)-A / 10sin(wt)≈Acos(wt-5.7°)

[0102] Therefore, 0.9A <B<1.1A,-5.7°<φ<+5.7°;

[0103] That is, when the error processing module is not introduced, compared with Pout_ideal, the amplitude error of Pout_real is ±0.9dB, and the phase error is ±5.7°.

[0104] After the error processing module is introduced, the remaining coupled signal after amplitude and phase cancellation is:

[0105] E'=(X)cos(wt+θ),

[0106] Among them, due to the step error of amplitude and phase control, the coupled signal cannot be completely offset. When the amplitude step is 0.5dB and the phase step is 5.625°, after offset, X<0.003A, -2.8°<θ<+2.8°;

[0107] The maximum amplitude error between Pout_real and Pout_ideal is ±0.03dB, and the phase error is ±0.3°. This improves the isolation of the entire feedback channel from -20dB to -50dB.

[0108] In the embodiments of the present application, common modules in a TR chip, such as switches, amplifiers, amplitude control units, and phase control units, can be integrated into the common TR channel 11, branch TR channels 13, feedback channel 22, and error processing module 30 as needed. Unless otherwise specified or limited, there is no restriction on the number or order of combinations of these common modules.

[0109] In an embodiment of the present application, the feedback network 21 includes multiple cascaded groups of switches, achieving at least one input and multiple outputs, with one output controlled by the switch state. This implementation is not limited to using multiple groups of one-to-two switches; combinations of one-to-four switches, two-to-four switches, and the like can also be implemented. FIG6 illustrates a combination of multiple one-to-two switches, where only multiple one-to-two switches are used to form the gating network from ANT1 to ANTN. FIG7 illustrates a combination of one-to-two switches and two-to-four switches to form the gating network from ANT1 to ANTN. FIG8 illustrates a combination of multiple one-to-two switches, where one-to-two switches S1 and multiple one-to-two switches S2 are combined to provide high isolation. The one-to-two switch S1 includes two grounding switches connected to the output via a quarter-coaxial transmission line. The one-to-two switch S2 includes two parallel cascaded switches S3, each of which includes two series switches and two grounding switches, where the series switch, the grounding switch, the series switch, and the grounding switch are connected in sequence.

[0110] In an embodiment of the present application, the feedback channel 22 includes at least one branch, each branch includes one of an amplifier, an amplitude adjustment unit, a phase adjustment unit, or a combination thereof; when the feedback channel 22 includes more than two branches, the feedback channel 22 also includes a switch for selecting one of the branches.

[0111] In addition, in this embodiment, the input end of the error processing module 30 is connected to the output end of the common TR channel 11, and the output end is connected to the input end of the feedback channel 22. In some other embodiments of the present application, the input end of the error processing module 30 can be connected to the input end or output end of any element before the branch TR channel 13, and the output end is connected to the input end of the feedback channel 22.

[0112] Example 2

[0113] In an embodiment of the present application, a phased array transceiver system with a feedback path is provided. As shown in FIG9 , based on Embodiment 1, the system further includes an amplitude and phase control module 40. The amplitude and phase control module 40 stores multiple amplitude control codes and multiple phase control codes, and is configured to transmit corresponding amplitude control codes and phase control codes to the error processing module based on an external first signal. "Based on the external first signal" includes "directly based on" or "indirectly based on" the external first signal. The first signal is used to select the amplitude control code and phase control code corresponding to each TR channel 13. The first signal corresponds to the amplitude control code and the phase control code. When the first signal changes, the amplitude control code and / or the phase control code change accordingly. For example, when the first signal indicates the first branch TR channel 13, the amplitude control code may be f1 in Table 1, and the phase control code may be d1 in Table 1; when the first signal indicates the second branch TR channel 13, the amplitude control code may be f2 in Table 1, and the phase control code may be d2 in Table 1; and so on. The amplitude control codes and / or phase control codes corresponding to different first signals may be the same or different. During the error state confirmation process, the isolation of the phased array transceiver system is tested. The amplitude and phase control module 40 is used to store the amplitude control code and the corresponding phase control code corresponding to each branch TR channel 13 found. When the phased array transceiver is operating normally, the amplitude and phase control module 40 is used to determine the amplitude control code and the corresponding phase control code corresponding to the selected branch TR channel 13 in the phased array system 10, and output the corresponding amplitude control code and the corresponding phase control code of the branch TR channel 13 to the error processing module 30, thereby processing the sampled signal at the output end of the phased array 10.

[0114] The isolation test of the phased array transceiver system is performed before the product leaves the factory. Before the product leaves the factory, the isolation is tested to find the amplitude control code and phase control code corresponding to each branch TR channel 13, and the amplitude control code and phase control code are fixed to the phased array transceiver system. After the product leaves the factory, when a TR channel 13 is used to send a signal during normal operation, the amplitude and phase control module 40 selects the amplitude control code and phase control code corresponding to the TR channel 13 based on the previously saved amplitude control code and phase control code to calibrate the TR channel 13. In some embodiments, the isolation can also be tested after the product leaves the factory, for example, after the product has been used for a period of time, and the tested amplitude control code and phase control code are updated to the phased array transceiver system.

[0115] In some embodiments, the first signal is not only used to indicate the amplitude control code and phase control code corresponding to the branch TR channel, but also used to instruct the feedback network which TR channel and feedback channel to select. The feedback network can also select any branch TR channel and feedback channel in the phased array system based on the first signal, thereby achieving signal multiplexing, eliminating the need to receive a separate signal for selecting TR channel 13, and conserving chip port resources. The term "based on the first signal" includes "directly based on" or "indirectly based on" the first signal to select any TR channel and feedback channel.

[0116] In this embodiment, the amplitude and phase control module 40 includes a control unit 41, a storage unit 42, and a selection unit 43, which can conveniently establish a corresponding relationship between the first signal and the corresponding amplitude control code and the corresponding phase control code.

[0117] Referring to Figure 9, the phased array transceiver system with a feedback path of this embodiment includes: a phased array system 10, a feedback system 20, an error processing module 30, a control unit 41, a storage unit 42, and a selection unit 43. The control unit 41 is configured to receive a first external signal and generate a call instruction and a second signal. The call instruction is configured to control the storage unit to output multiple amplitude control codes and multiple phase control codes. The call instruction can be a power-on signal that provides an operating voltage to the storage unit, enabling it to output the amplitude control code and the phase control code. The second signal is configured to control the selection unit to select the corresponding amplitude control code and the corresponding phase control code. In some embodiments, the second signal can also be transmitted to the feedback network to select one of the branch TR channels 13, thereby achieving signal multiplexing. This eliminates the need to receive a separate signal for selecting the TR channel 13, thus conserving chip port resources.

[0118] In some embodiments, the first signal can be sent from outside the chip to the phased array transceiver system. The first signal can include a control instruction and a second signal. The control instruction is used to instruct the chip's operation, such as processing the error signal; the second signal is a selection signal used to indicate which TR channel 13 to select. Control unit 41 decodes the first signal to obtain the control instruction and the second signal. Control unit 41 sends a call instruction to storage unit 42 based on the control instruction and sends the second signal to selection unit 43. Based on the second signal, selection unit 43 can select an amplitude control code and a phase control code from the multiple amplitude control codes and multiple phase control codes output by storage unit 42, and transmit the selected code to error processing module 30.

[0119] Storage unit 42 is used to store multiple amplitude control codes and multiple phase control codes and is configured to receive a call instruction and output the stored multiple amplitude control codes and multiple phase control codes. Storage unit 42 includes multiple storage subunits, each for storing corresponding amplitude control codes and phase control codes. In some embodiments, one amplitude control code and one phase control code form a control code set stored in storage unit 42, corresponding to one branch TR channel. Referring to Example 6, during the error state confirmation process, the amplitude control code and phase control code corresponding to each branch TR channel 13 found during calibration are written to storage unit 42 via a digital interface. The digital interface can be control unit 41. In the transmit state, storage unit 42 provides the amplitude control code and phase control code according to the call instruction from control unit 41. For example, if the phased array system 10 has ten branch TR channels, storage unit 42 can store ten sets of amplitude control codes and phase control codes corresponding to these ten channels. In actual use, one of these control code sets can be called based on the channel status. In some embodiments, the storage unit 42 outputs all amplitude control codes and phase control codes based on the call instruction, and the selection unit 43 selects a group of amplitude control codes and phase control codes based on the second signal and sends them to the error processing module 30 .

[0120] The selection unit 43 is configured to receive the second signal output by the control unit, select the amplitude control code and the phase control code corresponding to the branch TR channel from the multiple amplitude control codes and the multiple phase control codes output by the storage unit, and output the selected amplitude control code and the phase control code to the error processing module, thereby configuring the amplitude and phase of the output signal of the error processing module 30. The multiple amplitude control codes and the multiple phase control codes correspond to multiple branch TR channels, respectively.

[0121] In an embodiment of the present application, the selection unit 43 includes multiple inputs, each corresponding to one or more storage subunits. Based on the second signal, the selection unit 43 connects one or more storage subunits to the error processing module 3, thereby transmitting the corresponding amplitude control code and phase control code to the error processing module 30. In some embodiments, the selection unit 43 can be a device that can implement a multiple-select-one function, such as a multiplexer, a multiplexer, or a switch array. For example, a switch array can be used to control the connection state of the switches within the switch array based on the second signal provided by the control unit 41, and select and output the corresponding one path corresponding to the required amplitude control code and phase control code. The switch array has the advantages of strong programmability, high speed, and low power consumption.

[0122] In the embodiment of the present application, the storage unit 42 can be implemented using EFUSE (electrolyte-programmable memory) or SRAM (static random access memory). EFUSE and SRAM have the function of storing data without loss after the chip is powered off, thereby preventing the loss of the stored amplitude control code and phase control code. The control unit 41 can support communication protocols such as the SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit) buses. It inputs through digital interfaces such as CLK_IN (clock signal input interface) and DATA_IN (data input interface) and outputs the required control logic to implement functions such as configuring the storage unit 42, the selection unit 43, and the channel status of the phased array system 10. In some embodiments, the control unit 41 can include a decoding unit. When CLK_IN receives a clock signal and DATA_IN receives a first signal, the decoding unit decodes the first signal to obtain a control instruction and a second signal. Based on the control instruction, the decoding unit sends a call instruction to the storage unit 42 and sends the second signal to the selection unit 43.

[0123] In an embodiment of the present application, during the isolation test of the phased array transceiver system (see Example 6 for the test method), the target control code found is written into the storage unit 42 by the control unit 41. When the phased array transceiver system is in the transmitting state, the control unit 41 receives an external first signal. The first signal can be sent by the baseband or FPGA (Field-Programmable Gate Array) to the amplitude and phase control module 40. The baseband or FPGA can select which branch TR channel 13 to send the RF signal based on the current state of the phased array, and determine the first signal corresponding to the branch TR channel 13 to output the corresponding amplitude control code and phase control code. In one case, a storage subunit stores a set of amplitude control codes and phase control codes. For example, a storage subunit stores m bits of data, the first x bits are the amplitude control code for the amplitude adjustment device (such as a passive attenuator), and the last y bits are the phase control code for the phase adjustment device (such as a passive phase shifter). In another case, the amplitude control code and phase control code can be stored in two storage subunits respectively.

[0124] In some embodiments, the amplitude and phase control module and the error processing module may be located in the same chip to quickly calibrate the error processing module; in other embodiments, the amplitude and phase control module and the error processing module may also be located in different chips.

[0125] The amplitude and phase control module of the present application is not limited to the structure shown in FIG9 . For example, in some embodiments, the amplitude and phase control module may include a storage unit 42, and the amplitude and phase control module may not include the control unit 41 and the selection unit 43. The storage unit 42 stores all amplitude control codes and phase control codes, and the amplitude control codes and phase control codes are stored in different storage subunits. The error processing module 30 includes a reading module, which receives a first signal and reads the corresponding amplitude control code and phase control code from the corresponding storage subunit based on the first signal. The error processing module 30 can also obtain the corresponding amplitude control code and phase control code to calibrate the branch TR channel 13. At this time, the feedback network can also select any branch TR channel and feedback channel of the phased array system based on the first signal.

[0126] Alternatively, in other embodiments, the amplitude and phase control module can also be implemented in other ways. For example, the amplitude and phase control module can include a storage unit and a selection unit, the amplitude and phase control module may not include a control unit, and the first signal can be directly used to control the selection unit 43 to select the amplitude control code and the phase control code.

[0127] In the phased array transceiver system with a feedback path of this embodiment, when in operation, the control unit 41 outputs a control signal configuring the switching logic, causing the feedback network 21 to switch to any branch TR channel 13. At this time, the control signal synchronously controls the selection unit 43, which selects the corresponding amplitude control code and phase control code from the output of the storage unit 42 and inputs them to the error processing module 30 to configure the amplitude and phase states of its output signal.

[0128] Example 3

[0129] In an embodiment of the present application, a phased array transceiver system with a feedback path is further provided. As shown in FIG10 , in addition to the above-mentioned embodiment 1 or embodiment 2, the system further includes: a coupler 315 and / or a combiner 323. The error processing module 330 can be connected to the phased array system 310 via the coupler 315, and / or the error processing module 330 can be connected to the feedback system 320 via the combiner 323.

[0130] 10 , the phased array transceiver system with a feedback path of this embodiment includes a phased array system 310, a feedback system 320, and an error processing module 330. The phased array system 310 includes a common TR channel 311, a coupler 315, a power splitter / combiner network 312, multiple branch TR channels 313, and an antenna 314 corresponding to each branch TR channel 313, all connected in sequence.

[0131] Coupler 315 is connected between any two elements before the branch TR channel 311 of the phased array system. The coupling end of coupler 315 is connected to the input end of error processing module 330 to couple the RF signal out to error processing module 330. In the embodiment shown in Figure 10, the input end of coupler 315 is connected to the output end of common TR channel 311, the through end is connected to power splitter / combiner network 312, the coupling end is connected to the input end of error processing module 330, and the load end is grounded.

[0132] In the embodiment of the present application, after the RF signal passes through the common TR channel 311, the coupler 315 is used to output the main RF signal from the through-end of the coupler 315 to the power splitter / combiner network 312. A small amount of RF signal is sampled from the coupled end of the coupler 315 to the error processing module 330. This utilizes the low loss of the through-end of the coupler to prevent the sampling of the error processing module 330 from affecting the power of the signal on the normal transmission path. At the same time, although the output of the coupled end of the coupler 315 has a large loss, a sampled signal is still obtained and input to the error processing module 330. In some specific implementations, the coupling degree of the coupled end of the coupler 315 is between 15dB and 30dB, such as 20dB or 25dB. This ensures that the signal sampled from the coupled end to the error processing module 330 after processing is of the same power level as the error signal, further effectively offsetting the impact of the error signal.

[0133] The feedback system 320 includes: a feedback network 321, a feedback channel 322 and a combiner 323. The output end of the feedback network 321 is connected to the first input end of the combiner 323, the second input end of the combiner 323 is connected to the output end of the error processing module 330, and the output end of the combiner 323 is connected to the input end of the feedback channel 322.

[0134] In this embodiment of the present application, combiner 323 is used to combine two or more different RF signals into one, while preventing mutual interference between the individual signals. As shown in Figure 10, the RF signal at the output of feedback network 321 is combined by combiner 323 with the output signal of error processing module 330, canceling any errors, and then outputted via feedback channel 322, resulting in a high-quality feedback signal.

[0135] Example 4

[0136] In an embodiment of the present application, a phased array transceiver system with a feedback path is further provided, which differs from the above-mentioned embodiments 1 to 3 in that: there are multiple common TR channels.

[0137] It should be noted that in a phased array system, the number of common TR channels is usually the same as the number of beams.

[0138] 11 , the phased array transceiver system with a feedback path according to this embodiment includes a phased array system 710 , a feedback system 720 , and an error processing module 730 . The phased array system 710 includes a first common TR channel 711 , a second common TR channel 712 , a first power splitter / combiner network 713 connected to the first common TR channel 711 , and a second power splitter / combiner network 714 connected to the second common TR channel 712 .

[0139] The other ends of the first power splitting and combining network 713 and the second power splitting and combining network 714 are respectively connected to multiple first branch TR channels 715 and second branch TR channels 716, wherein the antenna port of each branch TR channel can be selectively connected to the feedback channel 722 through the feedback network 721; the first input end and the second input end of the error processing module 730 are respectively connected to the output end of the first common TR channel 711 and the output end of the second common TR channel 712, and the output end of the error processing module 730 is connected to the input end of the feedback channel 722.

[0140] According to this embodiment, a phased array architecture is extended to a combination of multiple common transceiver channels and multiple branch transceiver channels. The error signal mixed in the feedback signal is offset by the error processing module, thereby reducing the interference of the error signal caused by isolation.

[0141] Example 5

[0142] In an embodiment of the present application, a phased array transceiver system error state confirmation device with a feedback path is also provided, which is used in the isolation test phase of the phased array transceiver system to provide a control signal for testing. Referring to Figure 12, the error state confirmation device 800 of this embodiment includes: a first control module 801, which is used to receive external instructions to determine whether the TR branch to be tested by the phased array system 810 is open, and input a first control signal to the phased array system 810. The phased array system 810 controls the TR channel to be tested and the error processing module 830 to be closed according to the received first control signal, while the remaining TR branch channels are open;

[0143] The second control module 802 is configured to control the input of an RF test signal to the phased array system 810 and to input a second control signal to the phased array system 810, thereby enabling the error processing module 830. The second control module 802 then scans through combinations of amplitude control codes and phase control codes within the error processing module 830 while simultaneously testing the amplitude of the signal output from the feedback system 820. When the amplitude value is lowest among all combinations, it is determined that the phase and amplitude of the signal output from the error processing module 830 meet preset requirements. The amplitude control code and phase control code of the error processing module 830 at this point in time are recorded. Referring to Example 2, the recorded amplitude control code and phase control code can be stored in the storage unit 42.

[0144] In this embodiment, the error state confirmation device 800 determines the TR branch channel to be tested based on external instructions, and then inputs the first and second control signals respectively to control the state of the TR branch channel and the error processing module 830 of the phased array system 810. Each TR branch channel to be tested is tested separately until the error signal state of all TR branch channels is determined. Then, when the phased array system is operating normally, the signal sampled at the input of the phased array system 810 can be error processed (i.e., processed with a phase and amplitude opposite to that of the error signal) based on the determined error state. After processing, it is input into the feedback system 820 to offset the error signal introduced by the isolation problem in the sampled signal at the output of the phased array system 810, thereby ensuring that the phased array system 810 obtains a true and accurate feedback signal, thereby improving the calibration effect.

[0145] Example 6

[0146] In an embodiment of the present application, a method for confirming an error signal in a phased array transceiver system with a feedback path is provided. The method tests the isolation of the phased array transceiver system, namely, tests the amplitude and phase of a signal coupled to the output port of the phased array system via other paths. When the phased array transceiver system is operating normally, the phase and amplitude of the error processing module are configured to offset the coupled signal caused by the isolation by inputting a signal into the feedback channel, thereby improving feedback quality issues caused by the isolation. The method includes:

[0147] Determine the TR branch channel to be tested;

[0148] Inputting a first control signal into the system to control the TR branch channel to be tested and the error processing module to be closed, and the remaining TR branch channels to be opened;

[0149] inputting a radio frequency test signal into the phased array system;

[0150] inputting a second control signal into the phased array system to control the error processing module to turn on;

[0151] Scanning the phase and amplitude of the output signal of the error processing module until they reach preset values;

[0152] The phase and amplitude of the signal output by the error processing module when the preset value is reached are recorded and stored as the phase and amplitude of the error signal of the TR branch channel to be measured.

[0153] FIG13 is a schematic diagram of the structure of a phased array system with a feedback path according to a sixth embodiment of the present application. FIG14 is a flow chart of an error signal confirmation method according to a sixth embodiment of the present application. The method embodiments of the present application will be further described in detail with reference to FIG13 and FIG14 .

[0154] Execute step 1001 to disable a branch TR channel to be calibrated and the error processing module 930, while keeping all other modules enabled. Switch the feedback network 921 to the branch TR channel. For example, disable branch TR channel 9131 and the error processing module 930, while keeping all other modules enabled. Switch the feedback network 921 to the branch TR channel 9131.

[0155] Step 1002 is executed to input a power signal PIN into the common TR channel 911, and a power output signal POUT is measured at the output of the feedback channel 921. For example, a power signal PIN is input into the common TR channel 911, and POUT_1 is measured at the output port of the feedback channel 922. In this case, POUT_1 is the error signal E1 coupled to the output port of the feedback channel 922 through isolation from other paths.

[0156] Step 1003 is executed to enable the error processing module 930, scan its internal amplitude and phase until the amplitude of the power output signal POUT reaches a minimum value, and record the amplitude control code and phase control code of the error processing module 930. In this step, by traversing all combinations of the amplitude control code and phase control code of the error processing module 930 and testing the amplitude value of the power output signal POUT at the output end of the feedback channel 922, when the amplitude of the power output signal POUT reaches the minimum, it is determined that the phase and amplitude of the output signal of the error processing module 930 at this time have reached the preset values. In other words, the amplitude and phase control code corresponding to the combination when the amplitude of the power output signal POUT is the minimum is the target control code. For example, the error processing module 930 is enabled, and the amplitude and phase of the error processing module 930 are scanned until the amplitude of the power output signal POUT_1 reaches the minimum value. The amplitude control code ATT1 and the phase control code PHASE1 of the error processing module 930 at this time are recorded. In some embodiments, when the branch TR channel to be calibrated is closed, the control unit 41 in Figure 9 can control the input of the amplitude control code and the phase control code to the error processing module in sequence to traverse all combinations of the amplitude control code and the phase control code of the error processing module 930, and test the amplitude value of the power output signal POUT at the output end of the feedback channel 922 in sequence to find the target control word when the amplitude of the power output signal POUT is the lowest. At this time, the target control word is the amplitude control code ATT1 and the corresponding phase control word PHASE1 corresponding to the branch TR channel to be calibrated.

[0157] Execute step 1004 to disable one of the remaining TR channels and the error processing module, and repeat the above steps. For example, disable TR channels 9132 / … / 913n and error processing module 930, and correspondingly switch feedback network 921 to TR channels 9132 / … / 913n. Repeat steps 1002-1003 to confirm the error signal status of all TR channels and determine the target control word of error processing module 930 for each TR channel 913.

[0158] Executing step 1005, when the chip is operating normally, the error processing module is configured to use the previously recorded amplitude control code and phase control code according to the state of the feedback network. For example, when the chip is operating normally and feedback network 921 switches to branch TR channel 9131, the amplitude control code and phase control code of error processing module 930 are configured to be the recorded ATT1 and PHASE1.

[0159] The method of this embodiment closes the signal path to be calibrated, tests the amplitude and phase of the signal coupled to the output port via other paths, and then configures the phase and amplitude of the error processing module so that the signal processed by the error processing module is input into the feedback channel. This method can offset errors in the output sampling signal caused by isolation problems, thereby improving feedback quality problems caused by insufficient isolation in the phased array system.

[0160] It should be noted that the isolation test phase of the phased array transceiver system is completed through the above steps 1001-1004, and the target control code of the error processing module 930 corresponding to each branch TR channel (9131-913n) is found. At this time, referring to the above embodiment 2, all target control codes found in the test can be stored. For example, the amplitude control code ATT1 and the phase control code PHASE1 of the branch TR channel 9131 corresponding to the error processing module 930 can be saved in the storage unit 42. In this way, when the branch TR channel 9131 is operating normally, the stored amplitude control code ATT1 and the phase control code PHASE1 can be directly called to configure the error processing module 930.

[0161] Example 7

[0162] In an embodiment of the present application, a computer-readable storage medium is further provided, wherein the computer-readable storage medium stores computer program instructions, wherein the computer program instructions are configured to execute the steps in the above embodiment of the error signal confirmation method for a phased array transceiver system with a feedback path when executed.

[0163] In this embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer program instructions, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0164] Those skilled in the art will understand that the above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein with equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A phased array transceiver system with a feedback path, characterized in that: include: Phased array system and feedback system, as well as error processing module; The feedback system includes a feedback network and a feedback channel; When the phase control system transmits a signal, the feedback system samples the transmit signal and detects it; The feedback network is used to select any branch TR channel and feedback channel of the phased array system, and in the transmitting state, is used to output a first sampling signal to the feedback channel, and the difference between the first sampling signal and the ideal sampling signal is an error signal; The feedback channel performs at least one of amplification, amplitude modulation, and phase modulation on the first sampling signal; The error processing module, when in the transmitting state, samples the signal input to the branch TR channel as a second sampling signal, receives the corresponding amplitude control code and the corresponding phase control code, performs error processing on the second sampling signal and then feeds it back to the feedback channel, and the error processing includes performing processing with a phase opposite to that of the error signal and the same amplitude.

2. The phased array transceiver system with feedback path according to claim 1, characterized in that: When the branch TR channel is closed and the error processing module receives the corresponding amplitude control code and the corresponding phase control code, the amplitude of the output signal of the feedback channel is the lowest.

3. The phased array transceiver system with feedback path according to claim 1, characterized in that: Also includes: The amplitude and phase control module stores multiple amplitude control codes and multiple phase control codes, and is used to transmit the corresponding control amplitude control code and the corresponding phase control code to the error processing module based on an external first signal, and there is a corresponding relationship between the first signal and the corresponding amplitude control code and the corresponding phase control code.

4. The phased array transceiver system with feedback path according to claim 3, characterized in that: The amplitude and phase control module includes: a control unit, a storage unit, and a selection unit; The control unit is used to receive the first signal and generate a call instruction and a second signal, wherein the call instruction is used to control the storage unit to output multiple amplitude control codes and multiple phase control codes, and the second signal is used to control the selection unit to select the corresponding amplitude control code and the corresponding phase control code; The storage unit is used to store the multiple amplitude control codes and the multiple phase control codes, and is configured to receive the calling instruction and output the stored multiple amplitude control codes and the multiple phase control codes; The selection unit is used to receive the second signal output by the control unit, select the corresponding amplitude control code and the corresponding phase control code corresponding to the branch TR channel from the multiple amplitude control codes and the multiple phase control codes output by the storage unit, and output them to the error processing module; wherein the multiple amplitude control codes and the multiple phase control codes correspond to multiple branch TR channels respectively.

5. The phased array transceiver system with feedback path according to claim 4, characterized in that: The selection unit includes a multiplexer, a checksum or a switch array.

6. The phased array transceiver system with feedback path according to claim 4, characterized in that: The storage unit is used to store the corresponding amplitude control code and the corresponding phase control code of the branch TR channel during the error state confirmation process.

7. The phased array transceiver system with feedback path according to claim 3, characterized in that: The error processing module includes a reading module, which receives the first signal and reads the corresponding amplitude control code and the phase control code from the amplitude and phase control module according to the first signal.

8. The phased array transceiver system with feedback path according to claim 3, characterized in that: The feedback network selects the TR channel and the feedback channel of any branch of the phased array system based on the first signal.

9. The phased array transceiver system with feedback path according to claim 1, characterized in that: The phased array system includes: in the transmitting state, at least one common TR channel, a power splitter / combiner network, a plurality of branch TR channels, and an antenna correspondingly arranged in each branch TR channel, which are sequentially connected along the signal propagation direction.

10. The phased array transceiver system with feedback path according to claim 1, characterized in that: It also includes a coupler, which is connected between any two elements before the branch TR channel of the phased array system, and the coupling end of the coupler is connected to the input end of the error processing module.

11. The phased array transceiver system with feedback path according to claim 10, characterized in that: The coupling degree of the coupler is between 15dB and 30dB.

12. The phased array transceiver system with feedback path according to claim 1, characterized in that: It also includes a combiner, wherein a first input end of the combiner is connected to an output end of the feedback network, a second input end of the combiner is connected to an output end of the error processing module, and an output end of the combiner is connected to an input end of the feedback channel.

13. The phased array transceiver system with feedback path according to claim 1, characterized in that: The input end of the error processing module is connected to the input end or output end of any element before the branch TR channel of the phased array system, and the output end is connected to the input end of the feedback channel.

14. The phased array transceiver system with feedback path according to claim 13, characterized in that: The input end of the error processing module is connected to the output end of the common TR channel, and the output end is connected to the input end of the feedback channel.

15. The phased array transceiver system with feedback path according to claim 1, characterized in that: The error processing module includes: a phase adjustment unit and an amplitude adjustment unit. The phase adjustment unit performs a phase shift process on the second sampling signal that is opposite to the phase of the error signal, and the amplitude adjustment unit performs a process that is the same as the amplitude of the error signal.

16. The phased array transceiver system with feedback path according to claim 15, characterized in that: The amplitude attenuation performed by the amplitude adjustment unit on the second sampling signal is the same as the amplitude of the error signal.

17. The phased array transceiver system with feedback path according to claim 15, characterized in that: The phase processing performed by the phase adjustment unit on the second sampling signal is opposite to the phase direction of the error signal.

18. The phased array transceiver system with feedback path according to claim 15, characterized in that: The amplitude adjustment unit includes an attenuator, and the phase adjustment unit includes a phase shifter.

19. The phased array transceiver system with feedback path according to claim 1, characterized in that: The feedback network includes: multiple groups of cascaded switches to achieve at least one input and multiple outputs, and one channel is selected by controlling the state of the switch.

20. The phased array transceiver system with feedback path according to claim 1, characterized in that: The feedback channel includes at least one branch, each branch including one of an amplifier, an amplitude adjustment unit, a phase adjustment unit, or a combination thereof; When the feedback channel includes more than two branches, the feedback channel further includes a switch for selecting one of the branches.

21. The phased array transceiver system with feedback path according to claim 1, characterized in that: The feedback system is connected to the phased array system via a coupler or a detector.

22. A method for confirming an error state of a phased array transceiver system with a feedback path according to any one of claims 1 to 21, characterized in that: include: Determine the TR branch channel to be tested; Inputting a first control signal to the phased array system to control the TR branch channel and the error processing module to be tested to be closed, and the remaining TR branch channels to be opened; inputting a radio frequency test signal into the phased array system; Inputting a second control signal to the phased array system to control the error processing module to turn on; Scanning the phase and amplitude of the output signal of the error processing module until reaching a preset value; The phase and amplitude of the signal output by the error processing module when the preset value is reached are recorded and stored as the phase and amplitude of the error signal of the TR branch channel to be tested.

23. The error state confirmation method of the phased array transceiver system with feedback path according to claim 22, characterized in that: Also includes: The steps of determining the TR branch channel to be tested, inputting the first control signal, the radio frequency test signal, the second control signal, scanning, recording and storing are repeated until the error signal states of all TR branch channels are determined.

24. The error state confirmation method of the phased array transceiver system with feedback path according to claim 22, characterized in that: Also includes: The amplitude value of the signal at the output end of the feedback channel is tested, and when the amplitude value is the lowest, it is determined that the phase and amplitude of the output signal of the error processing module at this time reach the preset value.

25. An error state confirmation device of a phased array transceiver system with a feedback path according to any one of claims 1 to 21, characterized in that: include: A first control module is used to: receive an external instruction to determine whether the TR branch channel to be tested is open, input a first control signal to the phased array system, control the TR branch channel to be tested and the error processing module to be closed, and open the remaining TR branch channels; The second control module is used to control the radio frequency test signal to be input into the phased array system, and input a second control signal into the phased array system to control the error processing module to be turned on.

26. A computer-readable storage medium, characterized in that: Computer program instructions are stored thereon, and the computer program instructions can be executed by a processor to implement the method according to any one of claims 22 to 24.

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