Display substrate and display device

Abstract

The present invention relates to the technical field of display, and provides a display substrate and a display device. The display substrate comprises a base substrate, and gate lines and data lines located on the base substrate; the gate lines and the data lines intersect to define a plurality of pixel units; the gate lines extend in a first direction, the data lines extend in a second direction, and the first direction and the second direction intersect with each other; each pixel unit comprises a first transistor and a second transistor; an active layer of each first transistor comprises a first contact portion and a second contact portion; an active layer of each second transistor comprises a third contact portion and a fourth contact portion; the first contact portions are electrically connected to the data lines; the second contact portions are electrically connected to the third contact portions; the fourth contact portions are electrically connected to first electrodes of the pixel units; and in the second direction, the largest distance between each first contact portion and each gate line is not less than the largest distance between each fourth contact portion and the same gate line.

Description

Display substrate and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a display device. Background Art

[0002] Transistors, as switching control elements or integrated components in peripheral driver circuits, are core components in display technology. In the semiconductor field, mobility refers to the speed at which electrons move within a semiconductor material. For semiconductor display devices, mobility dictates the display quality and lifespan that can be achieved within a given device size.

[0003] However, with the optimization design of device semiconductor materials, while improving mobility, it also brings problems such as low threshold voltage and negative shift under light.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.

[0006] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a display substrate, which includes a base substrate, and gate lines and data lines located on the base substrate, the gate lines and the data lines intersecting to define a plurality of pixel units; the gate lines extend along a first direction, and the data lines extend along a second direction, and the first direction and the second direction intersect; the pixel unit includes a first transistor and a second transistor; the active layer of the first transistor includes a first contact portion and a second contact portion, and the active layer of the second transistor includes a third contact portion and a fourth contact portion, the first contact portion is electrically connected to the data line, the second contact portion is electrically connected to the third contact portion, and the fourth contact portion is electrically connected to the first electrode of the pixel unit; along the second direction, the maximum spacing between the first contact portion and the gate line is not less than the maximum spacing between the fourth contact portion and the same gate line.

[0007] In some embodiments, along the first direction, a width of the first contact portion is smaller than a width of the fourth contact portion.

[0008] In some embodiments, the orthographic projection of the first contact portion on the base substrate overlaps with the orthographic projection of the data line on the base substrate, the first contact portion includes a first portion and a second portion connected to each other, the first portion is electrically connected to the data line, and along the first direction, the width of the first portion is greater than the width of the second portion.

[0009] In some embodiments, the orthographic projection of the fourth contact portion on the substrate overlaps with the orthographic projection of the gate line on the substrate, the fourth contact portion includes a third portion and a fourth portion connected to each other, the fourth portion is electrically connected to the first electrode, and along the second direction, the minimum width of the fourth portion is greater than the minimum width of the third portion.

[0010] In some embodiments, the first contact portion is electrically connected to the data line through a first via hole, and the fourth contact portion is electrically connected to the first electrode through a second via hole; along the second direction, the minimum spacing between the first via hole and the gate line is greater than the minimum spacing between the second via hole and the same gate line.

[0011] In some embodiments, the first contact portion is electrically connected to the data line through a first via, and the fourth contact portion is electrically connected to the first electrode through a second via and a third via; along the second direction, the minimum spacing between the first via and the gate line is greater than the minimum spacing between the second via and the same gate line; the minimum spacing between the third via and the gate line is less than the minimum spacing between the second via and the same gate line.

[0012] In some embodiments, the pixel unit further includes an auxiliary component; the auxiliary component includes a fifth portion and a sixth portion connected to each other, the fifth portion is electrically connected to the fourth contact portion through the second via hole; the sixth portion is electrically connected to the first electrode through the third via hole.

[0013] In some embodiments, the auxiliary component is provided in the same layer as the data line, and in the first direction, the auxiliary component is provided between two adjacent data lines at positions where they are connected to the first contact portion.

[0014] In some embodiments, the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion are disposed in the same layer.

[0015] In some embodiments, the active layer of the first transistor and / or the active layer of the second transistor includes a metal oxide semiconductor material.

[0016] In some embodiments, the active layers of the first and second transistors include a plurality of stacked sub-layers, and the mobility of the sub-layers farther from the substrate is smaller than the mobility of the sub-layers closer to the substrate.

[0017] In some embodiments, the gate of the first transistor is located on a side of the active layer of the first transistor facing away from the substrate; the gate of the second transistor is located on a side of the active layer of the second transistor facing away from the substrate; the active layer of the first transistor and the active layer of the second transistor are arranged on the same layer;

[0018] The data line is multiplexed as the first electrode of the first transistor; the second contact portion is multiplexed as the second electrode of the first transistor, the third contact portion is multiplexed as the first electrode of the second transistor, and the second contact portion and the third contact portion are connected as an integrated structure.

[0019] In some embodiments, the first electrode is a pixel electrode; the orthographic projection of the second contact portion and the third contact portion connected as one body on the base substrate partially overlaps with the orthographic projection of at least one pixel electrode on the base substrate.

[0020] In some embodiments, for two adjacent pixel units, the orthographic projection of the second contact portion and the third contact portion connected as one in one pixel unit on the substrate partially overlaps with the orthographic projection of the other pixel unit on the substrate.

[0021] In some embodiments, the active layer of the first transistor further includes a first channel portion arranged between the first contact portion and the second contact portion, and the active layer of the second transistor further includes a second channel portion arranged between the third contact portion and the fourth contact portion; the first channel portion, the second contact portion and the third contact portion connected as a whole, and the pattern formed by the second channel portion have a U-shaped outline of the positive projection on the substrate.

[0022] In some embodiments, the gate of the first transistor and the gate of the second transistor are provided in the same layer; the active layer of the first transistor and the active layer of the second transistor are provided in the same layer; the first electrode and the second electrode of the first transistor are provided in the same layer as the first electrode and the second electrode of the second transistor;

[0023] The gate of the first transistor is located on a side of the active layer away from the substrate; the first electrode and the second electrode of the first transistor are located on a side of the gate away from the active layer;

[0024] The data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integrated structure, and the second electrode of the first transistor is electrically connected to the second contact portion through a fourth via, and the first electrode of the second transistor is electrically connected to the third contact portion through a fifth via.

[0025] In some embodiments, the display substrate further comprises a light shielding layer disposed near the base substrate at the pixel unit;

[0026] The active layer of the first transistor further includes a first channel portion disposed between the first contact portion and the second contact portion, and the active layer of the second transistor further includes a second channel portion disposed between the third contact portion and the fourth contact portion;

[0027] The orthographic projection of the light shielding layer on the base substrate at least covers the orthographic projections of the first channel portion and the second channel portion on the base substrate.

[0028] In some embodiments, in a first direction, a first distance exists between an edge of an orthographic projection of the light shielding layer on the base substrate and an edge of an orthographic projection of the first channel portion on the base substrate;

[0029] In the first direction, a second distance exists between an edge of an orthographic projection of the light shielding layer on the base substrate and an edge of an orthographic projection of the second channel portion on the base substrate;

[0030] The first spacing and / or the second spacing ranges from 4 μm to 6 μm.

[0031] In some embodiments, in the second direction, a third distance exists between an edge of an orthographic projection of the light shielding layer on the base substrate and an edge of an orthographic projection of the first channel portion on the base substrate;

[0032] In the second direction, a fourth distance exists between an edge of an orthographic projection of the light shielding layer on the base substrate and an edge of an orthographic projection of the second channel portion on the base substrate;

[0033] The third spacing and / or the fourth spacing ranges from 0 to 4 μm.

[0034] In some embodiments, the pixel units in the same row are electrically connected to the same gate line; the gate line serves as a gate of the first transistor and a gate of the second transistor.

[0035] In some embodiments, a gate insulating layer is provided on a side of the gate of the first transistor close to the active layer; and a thickness of the gate insulating layer is between 10 nm and 30 nm.

[0036] In some embodiments, the gate of the first transistor and the gate of the second transistor are provided in the same layer; the active layer of the first transistor and the active layer of the second transistor are provided in the same layer; the first electrode and the second electrode of the first transistor are provided in the same layer as the first electrode and the second electrode of the second transistor;

[0037] The gate of the first transistor is located on a side of the active layer close to the substrate; the first electrode and the second electrode of the first transistor are located on a side of the active layer away from the gate;

[0038] The data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integrated structure, and the second electrode of the first transistor is electrically connected to the second contact portion of the first transistor; the first electrode of the second transistor is electrically connected to the third contact portion of the second transistor.

[0039] In some embodiments, the pixel units in the same row are electrically connected to the same gate line; the gate line serves as the gate of the first transistor and the gate of the second transistor;

[0040] The gate line is a composite film layer, comprising a buffer layer and a main conductive layer sequentially arranged on the base substrate.

[0041] In some embodiments, a gate insulating layer is provided on a side of the gate of the first transistor close to the active layer; and a thickness of the gate insulating layer is between 30 nm and 50 nm.

[0042] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising a display substrate as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1a is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0044] FIG1b is a schematic diagram showing the positional relationship between the contact portion of the active layer and the gate line according to an embodiment of the present disclosure;

[0045] FIG2 is a schematic diagram showing the specific distribution of the first contact portion and the second contact portion provided by an embodiment of the present disclosure;

[0046] FIG3 a is a plan view showing electrical connections between a transistor and a data line according to an embodiment of the present disclosure;

[0047] FIG3 b is a plan view showing electrical connections between a transistor, a data line and a first electrode provided in an embodiment of the present disclosure;

[0048] FIG4 is a schematic diagram of an active layer using a composite film layer according to an embodiment of the present disclosure;

[0049] FIG5 a is a top plan view of a transistor with a top-gate structure provided by an embodiment of the present disclosure;

[0050] FIG5b is a cross-sectional view of the structure shown in FIG5a along the AA direction;

[0051] FIG6 a is a schematic diagram of the plane where the active layer shown in FIG5 b is located;

[0052] FIG6 b is a schematic diagram of the plane where the first conductive layer shown in FIG5 b is located;

[0053] FIG6c is a schematic diagram of the plane where the first via hole and the second via hole shown in FIG5b are located;

[0054] FIG6 d is a schematic diagram of the plane where the second conductive layer shown in FIG5 b is located;

[0055] FIG7 is a top plan view of a plurality of pixel units in a pixel unit provided by an embodiment of the present disclosure;

[0056] FIG8 a is a schematic diagram of the plane where the first sub-hole is located;

[0057] FIG8 b is a schematic diagram of the plane where the second electrode is located;

[0058] FIG8c is a schematic diagram of the plane where the second sub-hole is located;

[0059] FIG8 d is a schematic diagram of the plane where the first electrode is located;

[0060] FIG9 a is a schematic structural diagram of another top-gate transistor provided by an embodiment of the present disclosure;

[0061] FIG9b is a cross-sectional view of the structure shown in FIG9a along the BB direction;

[0062] FIG10 is a top view of the plane where the light shielding layer is located;

[0063] FIG11 is a top view of an exemplary light-shielding layer provided in an embodiment of the present disclosure;

[0064] FIG12a is a performance test result of the transistor device in the normal working state (-1.5V) of the dual NMOS shown in FIG9b;

[0065] FIG12 b is a performance test result of the transistor device in the negative bias state (-8V) of the dual NMOS shown in FIG9 b ;

[0066] FIG13a is a schematic structural diagram of a bottom-gate transistor provided by an embodiment of the present disclosure;

[0067] FIG13b is a cross-sectional view of the structure shown in FIG13a taken along the CC direction;

[0068] FIG14a is a schematic structural diagram of another bottom-gate transistor provided by an embodiment of the present disclosure;

[0069] FIG14b is a cross-sectional view of the structure shown in FIG14a along the DD direction;

[0070] 15a to 15j are schematic diagrams of a process for preparing the display substrate shown in FIG. 5b according to an embodiment of the present disclosure;

[0071] 16a to 16j are schematic diagrams of a process for preparing the display substrate shown in FIG. 9b according to an embodiment of the present disclosure;

[0072] 17a to 17i are schematic diagrams of a process for preparing the display substrate shown in FIG. 13b according to an embodiment of the present disclosure;

[0073] 18a to 18i are schematic diagrams of a preparation process of the display substrate shown in FIG. 10 provided in an embodiment of the present disclosure.

[0074] The reference numerals in the drawings are: 1, substrate; 2, pixel unit; 21, pixel circuit; 22, first electrode; 23, second electrode; T1, first transistor; T2, second transistor; T11, first electrode of the first transistor; T12, second electrode of the first transistor; T13, active layer of the first transistor; 13a, first contact portion; 13b, second contact portion; 13c, first channel portion; T14, gate of the first transistor; T21, first electrode of the second transistor; T22, second electrode of the second transistor; T23, active layer of the second transistor; 23a, third contact portion; 23b, fourth contact portion; 23c, second channel portion Channel portion; T24, gate of the second transistor; Gate, gate line; Data, data line; ACT, semiconductor layer; ACT_1, sublayer; 31, first insulating layer; 32, second insulating layer; 33, third insulating layer; 34, fourth insulating layer; 35, fifth insulating layer; 41, first conductive layer; 42, second conductive layer; 43, third conductive layer; 50, light-shielding layer; X, first direction; Y, second direction; 6, auxiliary component; 61, fifth portion; 62, sixth portion; Via1, first via hole; Via2, second via hole; Via3, third via hole; Via31, first sub-hole; Via32, second sub-hole. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0076] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0077] In the related technologies, the effective mobility of amorphous silicon (a-Si), metal oxide (IGZO), and low-temperature polysilicon (LTPS) currently used in the industry is actually about 1cm 2 / (V﹒s), 10cm 2 / (V﹒s),80cm 2 / (V﹒s), it can be seen that low-temperature polysilicon (LTPS) is far ahead in terms of material performance. Conventional technology has achieved a high mobility level by developing different series of metal oxide materials, such as adjusting the element ratio by increasing the indium (In) content, removing zinc (Zn) or adding tin (Sn), etc., thus achieving a mobility of approximately 20cm. 2 / (V﹒s)~50cm 2 / (V﹒s) has a higher mobility. However, while improving the mobility, it also brings about the following series of problems: On the one hand, the optical band gap (Eg) of high mobility materials is smaller, which makes it easier to generate carriers, so that the electrons in the high mobility materials can absorb part of the visible light band to produce electronic transitions, which in turn causes the device capability to be manifested as the thin film transistor (TFT) turning on early, and the increase of new defects under light, and the serious deterioration of the negative bias temperature illumination stability (NBTIS), resulting in a serious decline in service life. On the other hand, the development of high mobility materials is limited by the difficulty that mobility and Eg cannot achieve a win-win situation. At present, it has been difficult to break through the mass production of high mobility materials of Mob 30 and above. The relevant technology starts from the design direction of TFT devices and the design direction of dual-gate structures. Through dual-gate TFTs and ultra-thin gate insulating layers (GI), the thickness of approximately 20cm can be achieved. 2 / (V﹒s) and above ultra-high mobility index device performance. However, although this device design achieves high mobility, it also reduces the current value at low voltage, that is, the off-state current (Ioff), which will lead to a significant reduction in the device threshold voltage (Vth). At the same time, the reduction in GI thickness will also cause the device's breakdown voltage to decrease, thereby increasing the risk of device failure. Therefore, based on the above information, for the preparation of ultra-high mobility devices, there are problems such as low threshold voltage and negative offset under light. Based on these problems, traditional technical solutions often cannot break through 50cm 2 Ultra-high mobility of / (V﹒s) and above is not yet mass-produced on the market.

[0078] In view of this, an embodiment of the present disclosure provides a display substrate, which improves the leakage problem caused by the negative bias of the threshold voltage (Vth) of the existing device by connecting two transistors electrically connected to the first electrode of the pixel unit in series, thereby improving the switching capability of the display substrate and the service life of the product.

[0079] Figure 1a is a structural schematic diagram of a pixel circuit provided in an embodiment of the present disclosure, and Figure 1b is a schematic diagram of the positional relationship between the contact portion of the active layer and the gate line provided in an embodiment of the present disclosure. As shown in Figures 1a and 1b, the display substrate includes a base substrate 1 (not shown in Figures 1a and 1b, see Figure 4 for details), and gate lines Gate and data lines Data located on the base substrate 1, and the gate lines Gate and the data lines Data intersect to define a plurality of pixel units 2; the gate lines Gate extend along a first direction X, and the data lines Data extend along a second direction Y, and the first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are arranged perpendicularly. The pixel unit 2 includes a pixel circuit 21 and a first electrode 22; the pixel circuit 21 includes at least a first transistor T1 and a second transistor T2; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, the first contact portion 13a is electrically connected to the data line Data, the second contact portion 13b is electrically connected to the third contact portion 23a, and the fourth contact portion 23b is electrically connected to the first electrode 22 of the pixel unit 2; along the second direction Y, the maximum spacing d1 between the first contact portion 13a and the gate line Gate is not less than the maximum spacing d2 between the fourth contact portion 23b and the same gate line.

[0080] 1a, the second electrode T12 of the first transistor T1 is electrically connected to the first electrode T21 of the second transistor T2, and the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22. The active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both made of metal oxide semiconductor materials.

[0081] Exemplary metal oxide semiconductor materials can be made from one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), and rare earth-doped oxide (Ln-OS). The material can be amorphous, partially crystalline, single crystal, or polycrystalline, and the prepared active layer can have a single-layer or multi-layer structure. Based on the actual properties of metal oxide semiconductor materials, such materials can improve the mobility of transistors.

[0082] It should be noted that the transistor used in the embodiment of the present disclosure may be a field effect transistor (MOS transistor). Since the source and drain of the MOS transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present disclosure and the subsequent description, in order to distinguish the source and drain of the transistor, one of the electrodes is referred to as the first electrode and the other electrode is referred to as the second electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. In the embodiment of the present disclosure, the materials of the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both metal oxide semiconductor materials. It should be noted that transistors made of metal oxide semiconductor materials can only be used to prepare N-type transistors. Therefore, the transistor of the embodiment of the present disclosure is an N-type transistor. Among them, the first electrode of the transistor is the drain of the N-type transistor, and the second electrode of the transistor is the source of the N-type transistor. When a high-level signal is input to the gate, the source and drain are turned on.

[0083] In practical applications of the pixel unit 2, not all transistors in the pixel unit 2 employing the above structure will achieve similar effects. Therefore, it should be noted that for any pixel unit 2, the second transistor T2 electrically connected to the first electrode 22 is added, and the first transistor T1 is added in series with the second transistor T2. The current value of one transistor is suppressed by the other transistor. In extreme cases, when one transistor exhibits a negative bias in its conductive properties, the other transistor remains in normal operation, thereby significantly reducing the off-state current and the risk of a negative threshold voltage shift.

[0084] In the display substrate provided by the embodiment of the present disclosure, the active layers of the dual transistors electrically connected to the first electrode 22 are both made of metal oxide semiconductor materials, thereby improving the mobility of the transistors. At the same time, when the two transistors are connected in series, the current value of one transistor will be suppressed by the other transistor. In extreme cases, when one of the transistors has a negative bias in its conductive properties, the other transistor remains in normal operation, which can significantly increase the threshold voltage of the entire device, thereby effectively improving the leakage problem of the entire device and the sand bright spot (mura) problem of the display product caused by leakage.

[0085] In some embodiments, as shown in FIG. 1 b , along the first direction X, the minimum width of the first contact portion 13 a is smaller than the minimum width of the fourth contact portion 23 b .

[0086] Here, “width” may be understood as the maximum spacing or average spacing between boundaries of a specified film layer along a specified direction, and may be a transverse dimension or a longitudinal dimension.

[0087] In some embodiments, Figure 2 is a schematic diagram of the specific distribution of the first contact portion and the second contact portion provided in an embodiment of the present disclosure. As shown in Figure 2, the orthographic projection of the first contact portion 13a on the substrate 1 overlaps with the orthographic projection of the data line Data on the substrate 1. The first contact portion 13a includes a first portion 13a1 and a second portion 13a2 connected to each other. The first portion 13a1 is electrically connected to the data line Data. Along the first direction X, the width w1 of the first portion 13a1 is greater than the width w2 of the second portion 13a2.

[0088] In some embodiments, as shown in Figure 2, the orthographic projection of the fourth contact portion 23b on the base substrate 1 overlaps with the orthographic projection of the gate line Gate on the base substrate 1, and the fourth contact portion 23b includes a third portion 23b1 and a fourth portion 23b2 connected to each other, and the fourth portion 23b2 is electrically connected to the first electrode 22. Along the second direction Y, the minimum width w4 of the fourth portion 23b2 is greater than the minimum width w3 of the third portion 23b1.

[0089] In some embodiments, FIG3a is a plan view of the electrical connection between a transistor and a data line according to an embodiment of the present disclosure. As shown in FIG3a, the first contact portion 13a is electrically connected to the data line Data through a first via Via1, and the fourth contact portion 23b is electrically connected to the first electrode 22 through a second via Via2. Along the second direction Y, the minimum spacing d11 between the first via Via1 and the gate line Gate is greater than the minimum spacing d21 between the second via and the same gate line Gate.

[0090] In some embodiments, FIG3b is a plan view of the electrical connection between a transistor, a data line, and a first electrode provided for an embodiment of the present disclosure. As shown in FIG3b, the first contact portion 13a is electrically connected to the data line Data through a first via Via1, and the fourth contact portion 23b is electrically connected to the first electrode 22 through a second via Via2 and a third via Via3. Along the second direction Y, the minimum spacing d11 between the first via Via1 and the gate line Gate is greater than the minimum spacing d21 between the second via Via1 and the same gate line Gate. The minimum spacing d31 between the third via Via3 and Gate is less than the minimum spacing d21 between the second via Via2 and the same gate line Gate.

[0091] In some embodiments, as shown in Figure 3b, the pixel unit 2 also includes an auxiliary component 6; the auxiliary component 6 includes a fifth portion 61 and a sixth portion 62 connected to each other, the fifth portion 61 is electrically connected to the fourth contact portion 23b through the second via hole Via2; the sixth portion 62 is electrically connected to the first electrode 22 through the third via hole Via3.

[0092] In this embodiment, the position design of the third via hole Via3 and the auxiliary component 6 can reduce the via hole ratio, thereby improving the aperture ratio, and increase the overlap area and yield of the first electrode 22 (ie, the pixel electrode ITO) and other film layers.

[0093] In some embodiments, as shown in FIG6 d , the auxiliary component 6 is disposed in the same layer as the data line Data, and in the first direction X, an auxiliary component is disposed between the connection positions of two adjacent data lines Data with the first contact portion 13 a.

[0094] In some embodiments, as shown in FIG. 6 a , the first contact portion 13 a , the second contact portion 13 b , the third contact portion 23 a , and the fourth contact portion 23 b are disposed in the same layer.

[0095] In some embodiments, the active layer T13 of the first transistor T1 and / or the active layer T23 of the second transistor T2 includes multiple stacked sublayers, wherein the mobility of the sublayers farther from the substrate 1 is smaller than the mobility of the sublayers closer to the substrate 1 .

[0096] FIG4 is a schematic diagram of an active layer using a composite film layer according to an embodiment of the present disclosure. As shown in FIG4 , the active layer T13 of the first transistor T1 and / or the active layer T23 of the second transistor T2 includes a multilayer stack of sublayers ACT_1, ACT_2, and ACT_3. The mobility of the sublayer ACT_3, which is farther from the substrate 1, is lower than the mobility of the sublayer ACT_2, which is closer to the substrate 1; and the mobility of the sublayer ACT_2, which is farther from the substrate 1, is lower than the mobility of the sublayer ACT_1, which is closer to the substrate 1.

[0097] It should be noted that the higher the mobility, the lower the stability of the corresponding device. Therefore, this embodiment sequentially deposits sub-layers ACT_1 with lower mobility to ensure that the device has a higher mobility while improving the stability of the device.

[0098] In some embodiments, when the active layer T13 of the first transistor T1 includes a multi-layer stacked sub-layer, the material of the sub-layer includes one of IGO, ITZO, and IGZTO; when the active layer T23 of the second transistor T2 includes a multi-layer stacked sub-layer, the material of the sub-layer includes one of IGO, ITZO, and IGZTO.

[0099] The above metal oxide materials IGO, ITZO, and IGZTO all have a mobility greater than or equal to 20 cm 2 Of course, the material of the sub-layer ACT_1 provided in the embodiment of the present disclosure is not limited to the above-mentioned ones, and may also include other semiconductor materials with a mobility greater than or equal to 20cm 2 / (V﹒s) semiconductor materials, for which the embodiments of the present disclosure will not list them one by one.

[0100] The preparation process of the sub-layers of the multi-layer stacked arrangement includes but is not limited to the preparation methods of oxide semiconductor devices such as ESL, BCE, and Top Gate.

[0101] In some embodiments, the first transistor T1 and / or the second transistor T2 is an N-type metal oxide semiconductor transistor, hereinafter referred to as NMOS transistor.

[0102] The embodiment of the present disclosure takes the example that the first transistor T1 and the second transistor T2 are both NMOS transistors to illustrate the specific structures of the first transistor T1 and the second transistor T2.

[0103] In some embodiments, FIG5a is a top plan view of a top-gate transistor provided in an embodiment of the present disclosure, and FIG5b is a cross-sectional view taken along the AA direction of the structure shown in FIG5a. As shown in FIG5a and FIG5b, the first transistor T1 and the second transistor T2 can be top-gate transistors. The gate T14 of the first transistor T1 is located on the side of the active layer T13 of the first transistor T1 facing away from the substrate 1; the gate T24 of the second transistor T2 is located on the side of the active layer T23 of the second transistor T2 facing away from the substrate 1; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23c located between the third contact portion 23a and the fourth contact portion 23b.

[0104] The first contact portion 13a, the second contact portion 13b, the third contact portion 23a, and the fourth contact portion 23b are all conductive portions formed by conductively converting the active layer. The conductive properties of these conductive portions are higher than those of the first channel portion 13c (and higher than those of the second channel portion 23c), and lower than those of the metal electrodes. A specific conductive conversion process, for example, can be performed using a plasma treatment with a gas (including a mixed gas) such as He, Ar, H2, or NH3 to perform conductive doping to form the first contact portion 13a, the second contact portion 13b, the third contact portion 23a, and the fourth contact portion 23b.

[0105] For example, as shown in Figures 5a and 5b, the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged on the same layer. The second contact portion 13b is reused as the second electrode T12 of the first transistor T1, and the third contact portion 23a is reused as the first electrode T21 of the second transistor T2. The second contact portion 13b and the third contact portion 23a are connected to form an integrated structure. The first electrode T11 of the first transistor T1 is electrically connected to the first contact portion 13a and the data line Data through a first via Via1. The second electrode T22 of the second transistor is electrically connected to the fourth contact portion 23b and the fifth portion 61 of the auxiliary component 6 through a second via Via2.

[0106] Compared with bottom-gate transistors, top-gate transistors have a simpler manufacturing process, require fewer photomasks, and have lower costs.

[0107] Figure 6a is a schematic diagram of the plane where the active layer shown in Figure 5b is located, Figure 6b is a schematic diagram of the plane where the first conductive layer shown in Figure 5b is located, Figure 6c is a schematic diagram of the plane where the first via and the second via shown in Figure 5b are located, and Figure 6d is a schematic diagram of the plane where the second conductive layer shown in Figure 5b is located.

[0108] Exemplarily, as shown in FIG5b , the display substrate further includes a first insulating layer 31 disposed on the base substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 facing away from the base substrate 1 (as shown in FIG6a ); a second insulating layer 32 disposed on the side of the semiconductor layer ACT facing away from the first insulating layer 31; a first conductive layer 41 disposed on the side of the second insulating layer 32 facing away from the semiconductor layer ACT (as shown in FIG6b ); a third insulating layer 33 disposed on the side of the first conductive layer 41 facing away from the second insulating layer 32; and a second conductive layer 42 disposed on the side of the third insulating layer 33 facing away from the first conductive layer 41 (as shown in FIG6c and FIG6d ). The gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 (including the second contact portion 13b multiplexed as the second electrode T12 of the first transistor T1) and the active layer T23 of the second transistor T2 (including the third contact portion 23a multiplexed as the first electrode T21 of the second transistor T2) are both located in the semiconductor layer ACT; the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are both located in the second conductive layer 42.

[0109] In some embodiments, as shown in FIG5 a , the orthographic projection of a pattern formed by the first channel portion 13 c , the second contact portion 13 b and the third contact portion 23 a connected as one, and the second channel portion 23 c on the base substrate 1 is U-shaped.

[0110] In some embodiments, Figure 7 is a top plan view of multiple pixel units provided in an embodiment of the present disclosure. As shown in Figure 7, the first electrode 22 is a pixel electrode ITO; the orthographic projection of the second contact portion 13b and the third contact portion 23a connected as one on the base substrate 1 partially overlaps with the orthographic projection of at least one pixel electrode ITO on the base substrate 1.

[0111] For example, the active layer is a light-transmitting layer, and the area corresponding to the orthographic projection of the pixel electrode ITO is the display light-transmitting area. Therefore, the orthographic projections of the active layer contact portion and the pixel electrode ITO overlap, which does not affect the display luminescence. By having the orthographic projections of the integrally connected second contact portion 13b and third contact portion 23a on the base substrate 1 partially overlap with the orthographic projection of at least one pixel electrode ITO on the base substrate 1, the layout space of a single pixel unit 2 is reduced, thereby improving resolution.

[0112] In some embodiments, as shown in FIG. 7 , two pixel units 2 are adjacently arranged along a column direction, wherein the orthographic projection of the second contact portion 13 b and the third contact portion 23 a connected as one in one pixel unit 2 on the base substrate 1 partially overlaps with the orthographic projection of the other pixel electrode ITO on the base substrate 1 .

[0113] Of course, two pixel units 2 may be arranged adjacent to each other in the row direction, wherein the orthographic projection of the second contact portion 13b and the third contact portion 23a connected as one in one pixel unit 2 on the base substrate 1 partially overlaps with the orthographic projection of the other pixel electrode ITO on the base substrate 1.

[0114] In some embodiments, as shown in FIG7 , the display substrate further includes a data line Data. The data line Data is electrically connected to the first electrode T11 of the first transistor T1. The orthographic projection of the data line Data on the active layer T13 of the first transistor T1 extends in a direction from the first contact portion 13a to the second contact portion 13b (i.e., in a direction opposite to the Y direction), penetrating the active layer T13 of the first transistor T1. Furthermore, a contour edge of the orthographic projection of the data line Data on the active layer T13 of the first transistor T1 is spaced a certain distance from an edge of the active layer T13 of the first transistor T1 in the width direction X of the data line Data. The structural arrangement of this embodiment reduces the layout space of a single pixel unit 2, thereby improving resolution.

[0115] On this basis, combined with the layout structure of the pixel electrode ITO, the orthographic projection of the pixel electrode ITO on the second contact portion 13b and the third contact portion 23a connected as one does not fall within the orthographic projection of the data line Data on the active layer, so as to further improve the pixel resolution.

[0116] Figure 8a is a schematic diagram of the plane where the first sub-hole is located, Figure 8b is a schematic diagram of the plane where the second electrode is located, Figure 8c is a schematic diagram of the plane where the second sub-hole is located, and Figure 8d is a schematic diagram of the plane where the first electrode is located.

[0117] In some embodiments, as shown in Figures 15j and 8b, the pixel unit 2 further includes a second electrode 23, which is located on a side of the pixel electrode ITO close to the base substrate 1. The second electrode 23 is a common electrode.

[0118] In some embodiments, as shown in Figure 8d, the pixel electrode ITO is a slit electrode; the common electrode is a plate electrode. The pixel electrode ITO is electrically connected to the auxiliary component 6 via a third via hole via 3, and the auxiliary component 6 is electrically connected to the fourth contact portion 23b via a second via hole via 2. As shown in Figures 8a and 8c, the third via hole via 3 includes a first sub-hole via 31 that penetrates the planarization layer 342 and a second sub-hole via 32 that penetrates the metal protection layer 341. The pixel electrode ITO is electrically connected to the auxiliary component 6 through the first sub-hole via 31 and the second sub-hole via 32, respectively.

[0119] In some embodiments, FIG9a is a schematic structural diagram of another top-gate structure transistor provided by an embodiment of the present disclosure, and FIG9b is a cross-sectional view of the structure shown in FIG9a along the BB direction. As shown in FIG9a and FIG9b, the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged on the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged on the same layer; the first electrode T11 and the second electrode of the first transistor T1 are arranged on the same layer as the first electrode T21 and the second electrode of the second transistor T2; the first transistor T1 The gate T14 is located on the side of the active layer away from the substrate 1; the first electrode T11 and the second electrode of the first transistor T1 are located on the side of the gate away from the active layer; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23c located between the third contact portion 23a and the fourth contact portion 23b.

[0120] The first contact portion 13a, the second contact portion 13b, the third contact portion 23a, and the fourth contact portion 23b are all conductive portions formed by conductively converting the active layer. The conductive properties of these conductive portions are higher than those of the first channel portion 13c (and higher than those of the second channel portion 23c), and lower than those of the metal electrodes. A specific conductive conversion process, for example, can be performed using a plasma treatment with a gas (including a mixed gas) such as He, Ar, H2, or NH3 to perform conductive doping to form the first contact portion 13a, the second contact portion 13b, the third contact portion 23a, and the fourth contact portion 23b.

[0121] The second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are connected as an integrated structure. The second electrode T12 of the first transistor T1 is electrically connected to the second contact portion 13b via a fourth via Via4, and the first electrode T21 of the second transistor T2 is electrically connected to the third contact portion 23a via a fifth via Via5. The first electrode T11 of the first transistor T1 is electrically connected to the first contact portion 13a and the data line Data via a first via Via1. The second electrode T22 of the second transistor is electrically connected to the fourth contact portion 23b and the fifth portion 61 of the auxiliary component 6 via a second via Via2.

[0122] The transistor with the top-gate structure shown in FIG9b is connected in series in a different manner from the transistor with the top-gate structure shown in FIG5b. Compared with the transistor with the top-gate structure shown in FIG5b, the transistor with the top-gate structure shown in FIG9b adopts metal electrodes (the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 connected as an integral structure) to achieve series connection. Since the conductivity of the metal electrodes is higher than the conductivity of the second contact portion 13b and the third contact portion 23a after being conductorized, the top-gate structure shown in FIG9b has higher device stability.

[0123] Exemplarily, as shown in FIG9b , the display substrate further includes a first insulating layer 31 disposed on the base substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 facing away from the base substrate 1; a second insulating layer 32 disposed on the side of the semiconductor layer ACT facing away from the first insulating layer 31; a first conductive layer 41 disposed on the side of the second insulating layer 32 facing away from the semiconductor layer ACT; a third insulating layer 33 disposed on the side of the first conductive layer 41 facing away from the second insulating layer 32; and a second conductive layer 42 disposed on the side of the third insulating layer 33 facing away from the first conductive layer 41. The gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both located in the semiconductor layer ACT; the first electrode T11 and the second electrode T12 of the first transistor T1, as well as the first electrode T21 and the second electrode T22 of the second transistor T2, are both located in the second conductive layer 42.

[0124] For example, as shown in FIG9b , the first insulating layer 31 may be a buffer insulating layer, which may be provided with a single-layer structure and made of SiOx (x>0) material; or, the buffer insulating layer may be provided with a composite film layer structure and made of a composite film layer SiN / SiOx (x>0) material.

[0125] For example, as shown in FIG9b , the first insulating layer 31 can be a dielectric layer disposed between the light-shielding layer 50 and the semiconductor layer ACT. Besides its own light-shielding effect, it also produces other effects: Firstly, there is the electrical effect; the light-shielding layer 50 is conductive. For devices with a floating light-shielding layer 50, it will induce charge, causing the transistor to turn on prematurely, reducing the threshold voltage Vth. The thinner the first insulating layer 31, the greater the effect. For light-shielding layer devices connected to the gate, the first insulating layer 31 needs to be thinned to provide a higher Ion capability. Generally speaking, the electrical requirements are moderate for the thickness of the first insulating layer 31. Secondly, there is the effect of process coverage; the first insulating layer 31 needs to have a certain thickness to ensure isolation and prevent the active layer from breaking or short-circuiting at the edge of the light-shielding layer 50. The thickness of the first insulating layer 31 is set between 200nm and 500nm.

[0126] For example, as shown in FIG9 b , the second insulating layer 32 may be a gate insulating layer, and the material of the gate insulating layer may generally be SiO x (x>0) material.

[0127] For example, as shown in FIG9b, unlike the first insulating layer 31, the second insulating layer 32 exists between the first conductive layer 41 and the semiconductor layer ACT. For electrical properties, the thinner the second insulating layer 32, the higher the Ion. In addition, since the top-gate structure does not require a second insulating layer 32 for covering protection in the process, and considering the process capability, to prevent the film layer from being too thin and causing electrical breakdown, the thickness of the second insulating layer 32 is set between 100nm and 300nm. For example, as shown in FIG9b, the first conductive layer 41 can be set as a single-layer structure, using materials such as Al or Cu. Alternatively, the first conductive layer 41 can be set as a composite film layer structure, including a buffer layer and a main conductive layer, wherein the material of the buffer layer can be a Ti-based alloy material or a Mo-based alloy material, and the material of the main conductive layer can be a material such as Al or Cu. Alternatively, the first conductive layer 41 can be set as a single-layer structure, using Al or Cu with Ti-based alloy material or Mo-based alloy material added.

[0128] For example, as shown in FIG9b , the third insulating layer 33 is an intermediate dielectric layer, which can be provided with a single-layer structure and made of SiOx (x>0) material; alternatively, the intermediate dielectric layer can be provided with a composite film layer structure and made of a composite film layer SiN / SiOx (x>0) material.

[0129] For example, as shown in FIG9b , the third insulating layer 33 serves to separate the gate and source / drain in the longitudinal cross-section of the device. A certain thickness is required between the two to prevent short circuits and reduce the capacitance between metals to prevent pulling between electrical signals. An excessively thick intermediate dielectric layer is detrimental to the stability of engineering contact, so the thickness of the third insulating layer 33 is set between 300 nm and 600 nm.

[0130] Exemplarily, as shown in FIG9 b , the material of the second conductive layer 42 is metal.

[0131] For example, as shown in Figures 16j and 8a-8d, the top-gate structure shown in Figure 9b is connected to the pixel electrode ITO structure, as shown in Figures 16j and 8a-8d. The pixel electrode ITO is electrically connected to the auxiliary component 6 through the third via hole via3, and the auxiliary component 6 is electrically connected to the fourth contact portion 23b through the second via hole via2. As shown in Figures 8a and 8c, the third via hole via3 includes a first sub-hole via31 that penetrates the planarization layer 342 and a second sub-hole via32 that penetrates the metal protection layer 341. The pixel electrode ITO is electrically connected to the auxiliary component 6 through the first sub-hole via31 and the second sub-hole via32 in sequence.

[0132] Figure 10 is a top view of the plane where the light shielding layer is located. Both the top-gate structure shown in Figure 5b and the top-gate structure shown in Figure 9b include a light shielding layer 50. In some embodiments, as shown in Figures 5b, 9b, and 10, the display substrate further includes a light shielding layer 50 disposed near the base substrate 1 in the pixel unit 2.

[0133] For example, the light shielding layer 50 may be provided with a composite film structure, using a composite film layer of Mo-based alloy / Cu material, or a composite film layer of Mo-based alloy / Al material.

[0134] As shown in FIG5a or 9a, the orthographic projection of the light shielding layer 50 on the base substrate 1 at least covers the orthographic projections of the first channel portion 13c of the active layer T13 of the first transistor T1 and the second channel portion 23c of the active layer T23 of the second transistor T2 on the base substrate 1.

[0135] In this embodiment, a light-shielding layer 50 is provided to block the light emitted by the backlight source toward the first channel portion 13c and the second channel portion 23c. This can reduce the number of electron-hole pairs generated by the first contact portion 13a (or the third contact portion 23a) due to light excitation, thereby reducing the number of electrons moving toward the second contact portion 13b (or the fourth contact portion 23b) during the holding stage, thereby reducing the light leakage current and improving the flicker problem caused by the leakage current.

[0136] In some embodiments, Figure 11 is a plan view of an exemplary light-shielding layer provided in an embodiment of the present disclosure. As shown in Figure 11, there is a maximum first spacing between the contour edge of the orthographic projection of the light-shielding layer 50 on the substrate substrate 1 and the contour edge of the orthographic projection of the first channel portion 13c on the substrate substrate 1; there is a maximum second spacing between the contour edge of the orthographic projection of the light-shielding layer 50 on the substrate substrate 1 and the contour edge of the orthographic projection of the second channel portion 23c on the substrate substrate 1; the maximum first spacing and / or the maximum second spacing are in the range of 4μm to 6μm.

[0137] For example, as shown in FIG11 , in the first direction X, a first spacing L1 is defined between the edge of the orthographic projection of the light shielding layer 50 on the substrate 1 and the edge of the orthographic projection of the first channel portion 13c on the substrate 1. The first spacing L1 ranges from 4 μm to 6 μm. Because the direction from the first contact portion 13a to the second contact portion 13b is the direction of current flow (i.e., the direction opposite to the Y direction), the width of the light shielding layer 50 in the first direction X is slightly larger to prevent the formation of a current path along the opposing side portions of the first channel portion 13c along the first direction X. This ensures that the first channel portion 13c is not affected by light in the first direction X, thereby ensuring the stability of the first transistor T1. Similarly, in the first direction X, a second spacing L2 is defined between the edge of the orthographic projection of the light shielding layer 50 on the substrate 1 and the edge of the orthographic projection of the second channel portion 23c on the substrate 1. The second spacing L2 ranges from 4 μm to 6 μm. Since the direction in which the third contact portion 23a points to the fourth contact portion 23b is the current flow direction, that is, the second direction Y, in order to avoid the formation of a current path in the side portion of the second channel portion 23c opposite to the first direction X, the width of the light shielding layer 50 in the first direction X is set slightly larger to ensure that the second channel portion 23c is not affected by light in the first direction X, thereby ensuring the stability of the second transistor T2.

[0138] For example, as shown in Figure 11, in the second direction, a third spacing L3 is defined between the edge of the orthographic projection of the light shielding layer 50 onto the substrate 1 and the edge of the orthographic projection of the first channel portion 13c onto the substrate 1. The third spacing L3 ranges from 0 to 4 μm. In the second direction Y, a fourth spacing L4 is defined between the edge of the orthographic projection of the light shielding layer 50 onto the substrate 1 and the edge of the orthographic projection of the second channel portion 23c onto the substrate 1. The fourth spacing L4 ranges from 0 to 4 μm. Because the light shielding layer 50 is opaque, the smaller the coverage area of ​​the light shielding layer 50, the better. However, to ensure device stability, the larger the coverage area of ​​the light shielding layer 50, the better. Therefore, taking into account the impact of pixel specifications and device stability, the width of the light shielding layer 50 in the second direction Y is set slightly smaller to improve light transmittance.

[0139] In some embodiments, as shown in FIG. 5 a or FIG. 9 a , the pixel units 2 in the same row are electrically connected to the same gate line Gate; the gate line Gate serves as the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2.

[0140] In this embodiment, the gate line Gate is reused as the transistor gate. This configuration using in-plane routing is used to achieve a narrow frame.

[0141] FIG12a shows the performance test results of the transistor device in the normal working state (-1.5V) of the dual NMOS shown in FIG9b, and FIG12b shows the performance test results of the transistor device in the negative bias state (-8V) of the dual NMOS shown in FIG9b, wherein the abscissa Vg represents the gate T24 (i.e., gate line Gate) voltage of the first transistor T1 and the second transistor T2, the ordinate Ids represents the first electrode T11 (i.e., drain) current of the first transistor T1, Vth represents the threshold voltage, O1 represents the curve of the dual NMOS structure shown in FIG9b, and O2 represents the curve of the single NMOS structure. As can be seen from FIG9a and 9b, the off-state current of the dual NMOS is relatively smaller and the threshold voltage is relatively larger than that of the single NMOS, whether in the normal working state or the negative bias state. Therefore, compared with the prior art, the embodiments of the present disclosure can effectively improve the leakage problem of the entire device and the mura problem of display products caused by leakage.

[0142] In some embodiments, the first transistor T1 and the second transistor T2 may be bottom-gate transistors. FIG13a is a schematic diagram of a bottom-gate transistor structure provided by an embodiment of the present disclosure, and FIG13b is a cross-sectional view of the structure shown in FIG13a along the CC direction. As shown in FIG13a and FIG13b, the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged on the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged on the same layer; the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are arranged on the same layer; the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged on the same layer; 4 is located on a side of the active layer close to the substrate 1; the first electrode T11 of the first transistor T1 is located on a side of the active layer T13 away from the gate T14; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, wherein the second contact portion 13b is multiplexed as the first channel portion 13c of the first transistor T1; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, wherein the third contact portion 23a is multiplexed as the second channel portion 23c of the second transistor T2.

[0143] The first contact portion 13a and the fourth contact portion 23b are both conductive portions formed by conductively converting the active layer. The conductive properties of these conductive portions are higher than those of the first channel portion 13c (and higher than those of the second channel portion 23c), but lower than those of the metal electrodes. Specifically, the conductive conversion process can include plasma treatment with gases such as He, Ar, H2, and NH3 (including mixed gases) to perform conductive doping to form the first contact portion 13a and the fourth contact portion 23b.

[0144] As shown in FIG. 13 a , the second contact portion 13 b and the third contact portion 23 a are connected to form an integral structure.

[0145] As shown in FIG13 a , the data line Date is multiplexed into the first electrode T11 of the first transistor T1 , and the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22 through the third via hole Via3 .

[0146] In the embodiment of the present disclosure, whether it is a bottom-gate transistor or a top-gate transistor, the second contact portion 13b and the third contact portion 23a connected as one body can be used to realize the series connection of two transistors.

[0147] Compared to top-gate transistors, bottom-gate transistors can reuse the gate electrode on the side of the active layer closest to the substrate 1 as an optical protective film for the active layer. This prevents light from the backlight source from irradiating the active layer and generating carriers that could damage the electrical properties of the active layer. Therefore, bottom-gate transistors offer more stable device performance than top-gate transistors. Furthermore, in this embodiment, the second contact portion 13b and the third contact portion 23a are connected as an integrated structure, meaning that the first channel portion 13c and the second channel portion 23c are connected as an integrated structure. This increases the channel length of the transistor and reduces the risk of conductorization.

[0148] For example, as shown in FIG13b , the display substrate further includes a first conductive layer 41 disposed on the base substrate 1; a first insulating layer 31 disposed on a side of the first conductive layer 41 facing away from the base substrate 1; a semiconductor layer ACT disposed on a side of the first insulating layer 31 facing away from the first conductive layer 41; a second conductive layer 42 disposed on a side of the semiconductor layer ACT facing away from the first insulating layer 31; and a second insulating layer 32 disposed on a side of the second conductive layer 42 facing away from the semiconductor layer ACT. The gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 (including the second contact portion 13b multiplexed as the second electrode T12 of the first transistor T1) and the active layer T23 of the second transistor T2 (including the third contact portion 23a multiplexed as the first electrode T21 of the second transistor T2) are both located in the semiconductor layer ACT; and the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are both located in the second conductive layer 42.

[0149] In some embodiments, FIG14a is a schematic structural diagram of another bottom-gate transistor provided by an embodiment of the present disclosure, and FIG14b is a cross-sectional view of the structure shown in FIG14a along the DD direction. As shown in FIG14a and FIG14b, the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged on the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged on the same layer; the first electrode T11 and the second electrode T12 of the first transistor T1 are arranged on the same layer as the first electrode T21 and the second electrode T22 of the second transistor T2; The gate T14 of the body transistor T1 is located on a side of the active layer close to the substrate 1; the first electrode T11 and the second electrode T12 of the first transistor T1 are located on a side of the active layer away from the gate; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23c located between the third contact portion 23a and the fourth contact portion 23b.

[0150] The first contact portion 13a, the second contact portion 13b, the third contact portion 23a, and the fourth contact portion 23b are all conductive portions formed by conductively converting the active layer. The conductive properties of these conductive portions are higher than those of the first channel portion 13c (and higher than those of the second channel portion 23c), and lower than those of the metal electrodes. A specific conductive conversion process, for example, can be performed using a plasma treatment with a gas (including a mixed gas) such as He, Ar, H2, or NH3 to perform conductive doping to form the first contact portion 13a, the second contact portion 13b, the third contact portion 23a, and the fourth contact portion 23b.

[0151] As shown in Figure 14a, the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are connected as an integral structure, and the second electrode T12 of the first transistor T1 is electrically connected to the second contact portion 13b of the first transistor T1; the first electrode T21 of the second transistor T2 is electrically connected to the third contact portion 23a of the second transistor T2.

[0152] As shown in FIG14 a , the data line Date is multiplexed into the first electrode T11 of the first transistor T1 , and the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22 through the third via hole Via3 .

[0153] The bottom-gate transistor shown in FIG14b is connected in series in a different manner than the bottom-gate transistor shown in FIG13b. Compared to the bottom-gate transistor shown in FIG13b, the bottom-gate transistor shown in FIG14b uses metal electrodes (the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2, which are connected as an integral structure) to achieve series connection. Because the metal electrodes have a higher conductivity than the second contact portion 13b and the third contact portion 23a after being conductively connected, the bottom-gate structure shown in FIG14b provides greater device stability. Furthermore, in this embodiment, the two transistors are connected in series. If one transistor experiences a conductive shutdown anomaly, the other transistor can still operate normally.

[0154] Exemplarily, as shown in FIG14b , the display substrate further includes a first conductive layer 41 disposed on the substrate; a first insulating layer 31 disposed on a side of the first conductive layer 41 facing away from the substrate 1; a semiconductor layer ACT disposed on a side of the first insulating layer 31 facing away from the first conductive layer 41; a second conductive layer 42 disposed on a side of the semiconductor layer ACT facing away from the first insulating layer 31; and a second insulating layer 32 disposed on a side of the second conductive layer 42 facing away from the semiconductor layer ACT. The gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both located in the semiconductor layer ACT; the first electrode T11 and the second electrode of the first transistor T1, as well as the first electrode T21 and the second electrode of the second transistor T2, are both located in the second conductive layer 42.

[0155] For example, the first conductive layer 41 can be configured as a single-layer structure, using materials such as Al or Cu. Alternatively, the first conductive layer 41 can be configured as a composite film structure, including a buffer layer and a main conductive layer, wherein the buffer layer can be made of a Ti-based alloy material or a Mo-based alloy material, and the main conductive layer can be made of a material such as Al or Cu. Alternatively, the first conductive layer 41 can be configured as a single-layer structure, using Al or Cu with a Ti-based alloy material or a Mo-based alloy material added thereto.

[0156] For example, as shown in FIG. 13 b or FIG. 14 b , the first insulating layer 31 may be a gate insulating layer, and the material of the gate insulating layer may generally be SiO x (x>0) material.

[0157] For example, as shown in FIG13b or FIG14b, in terms of the coverage and capacitance reduction requirements of the gate, since the bottom gate structure process requires the first insulating layer 31 as the gate insulating layer for covering protection, and the thickness of the first insulating layer 31 as the gate insulating layer affects the capacitance, the thickness of the first insulating layer 31 as the gate insulating layer is larger than that of the top gate structure. In addition, in terms of the requirement for Ion, the thinner the first insulating layer 31 as the gate insulating layer, the higher the Ion. Combining the above two requirements, the thickness of the first insulating layer 31 can be between 300nm and 500nm. For example, as shown in FIG13b or FIG14b, the material of the second conductive layer 42 is metal.

[0158] For example, as shown in FIG. 13 b or FIG. 14 b , the second insulating layer 32 is a channel protection layer. The material of the channel protection layer can generally be SiOx (x>0). The thickness of the second insulating layer 32 is not less than 100 nm.

[0159] For example, as shown in FIG13b or FIG14b, the second insulating layer 32 is a channel protection layer. The material of the channel protection layer can generally be a composite film layer of SiN and SiOx (x>0). The overall thickness of the second insulating layer 32 is between 200nm and 400nm. In addition, the thickness of the second insulating layer 32 is not only determined by the thickness coverage requirement of the second conductive layer 42, but also by the protection requirements of the TFT characteristics. For example, the thickness requirement of the SiOx (x>0) film layer is required to ensure that the device does not become conductive, and the SiN film layer is used to block the influence of water vapor on the organic film layer (the water vapor barrier capability of the SiN film layer is better than that of the SiOx (x>0) film layer).

[0160] In some embodiments, as shown in FIG13b or FIG14b , pixel units 2 in the same row are electrically connected to the same gate line Gate; the gate line Gate serves as the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2; the gate line Gate is a composite film layer including a buffer layer and a main conductive layer sequentially disposed on the base substrate 1. The buffer layer can be made of a Ti-based alloy material or a Mo-based alloy material, and the main conductive layer can be made of materials such as Al or Cu.

[0161] In some embodiments, as shown in Figures 17i, 18i and 8b, the pixel unit 2 further includes a second electrode 23, which is located on a side of the pixel electrode ITO close to the base substrate 1. The second electrode 23 is a common electrode.

[0162] In some embodiments, as shown in Figure 8d, the pixel electrode ITO is a slit electrode; the common electrode is a plate electrode. The pixel electrode ITO is electrically connected to the second electrode T22 of the second transistor T2 via a third via hole via 3. As shown in Figures 8a and 8c, the third via hole via 3 includes a first sub-hole via 31 that penetrates the planarization layer 342 and a second sub-hole via 32 that penetrates the metal protection layer 341. The pixel electrode ITO is electrically connected to the second electrode T22 of the second transistor T2 via the first sub-hole via 31 and the second sub-hole via 32, respectively.

[0163] In addition, embodiments of the present disclosure further provide a display device comprising the display substrate of any of the aforementioned embodiments. The display device may be, for example, a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, vehicle-mounted device, or any other product with a display function. Other essential components of the display device are readily understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0164] In addition, an embodiment of the present disclosure further provides a method for preparing a display substrate, which is used to prepare the display substrate of any one of the above embodiments.

[0165] The method specifically includes: providing a base substrate 1; forming a plurality of pixel units 2 arranged in an array on the base substrate 1. The step of forming the pixel units 2 includes at least: sequentially forming a pixel circuit 21 and a first electrode 22 on the base substrate 1. The pixel circuit 21 includes at least a first transistor T1 and a second transistor T2; the second electrode T12 of the first transistor T1 is electrically connected to the first electrode T21 of the second transistor T2, and the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22. The active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both made of metal oxide semiconductor materials.

[0166] In some embodiments, FIG. 15 a to FIG. 15 j are schematic diagrams of a process for preparing the display substrate shown in FIG. 5 b according to an embodiment of the present disclosure, specifically including the following steps S11 to S111 , wherein:

[0167] S11, providing a base substrate 1.

[0168] In this step, the base substrate 1 is a glass substrate.

[0169] S12 , as shown in FIG15 a , forming a light shielding layer 50 on the base substrate 1 .

[0170] S13 , as shown in FIG15 b , forming a first insulating layer 31 on the side of the light shielding layer 50 facing away from the base substrate 1 .

[0171] S14 , as shown in FIG. 15 c , a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .

[0172] Specifically, the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.

[0173] S15 , as shown in FIG. 15 d , a second insulating layer 32 and a first conductive layer 41 are formed on a side of the semiconductor layer ACT away from the first insulating layer 31 .

[0174] The second insulating layer 32 is a gate insulating layer, and the first conductive layer 41 includes a gate, or is reused as a gate line Gate of the gate.

[0175] The material of the gate insulating layer and the material of the first conductive layer 41 are deposited in sequence; thereafter, gate photolithography and etching are performed, and the gate insulating layer is etched using the gate as a mask to expose the semiconductor layer ACT and then conduct it. The conduction process can be carried out using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases).

[0176] It should be noted that the conductive second contact portion 13 b is directly connected to the conductive third contact portion 23 a .

[0177] S16. As shown in FIG. 15e, a third insulating layer 33 is formed on the basis of step S15.

[0178] The material of the second insulating layer 32 is deposited, and then the interlayer dielectric layer is photolithographically and etched to form a first via hole Via1 leading to the first contact portion 13a of the active layer and a second via hole Via2 leading to the fourth contact portion 23b.

[0179] S17 . As shown in FIG. 15 f , a second conductive layer 42 is formed on a side of the third insulating layer 33 facing away from the base substrate 1 .

[0180] The second conductive layer 42 is made of a metal material and is electrically connected to the first contact portion 13a and the fourth contact portion 23b, respectively, through a first via hole Via1 and a second via hole Via2 that penetrate the third insulating layer 33. The second contact portion 13b serves as the second electrode T12 of the first transistor T1, and the third contact portion 23a serves as the first electrode T21 of the second transistor T2.

[0181] S18 . As shown in FIG. 15 g , a fourth insulating layer 34 is formed on a side of the second conductive layer 42 away from the third insulating layer 33 .

[0182] The fourth insulating layer 34 may be a metal protection layer 341 and a planarization layer 342 .

[0183] The materials of the metal protection layer 341 and the planarization layer 342 are deposited in sequence; then, the planarization layer 342 is subjected to organic material photolithography to form the first sub-hole Via31.

[0184] S19 . As shown in FIG. 15 h , a second electrode 23 is formed on a side of the fourth insulating layer 34 facing away from the third insulating layer 33 .

[0185] The second electrode 23 is a common electrode.

[0186] S110 , as shown in FIG15 i , forming a fifth insulating layer 35 on a side of the second electrode 23 away from the fourth insulating layer 34 .

[0187] The fifth insulating layer 35 is a passivation layer.

[0188] A passivation layer material is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.

[0189] S111 , as shown in FIG15 j , forming a pixel electrode ITO on a side of the fifth insulating layer 35 away from the second electrode 23 .

[0190] The pixel electrode ITO is a slit electrode and has a connecting portion connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through a third via hole Via3; the auxiliary component 6 is connected to the fourth contact portion 23b through a second via hole Via2.

[0191] In some embodiments, FIG. 16 a to FIG. 16 j are schematic diagrams of a process for preparing the display substrate shown in FIG. 9 b according to an embodiment of the present disclosure, specifically including the following steps S21 to S211 , wherein:

[0192] S21, providing a base substrate 1.

[0193] In this step, the base substrate 1 is a glass substrate.

[0194] S22 . As shown in FIG. 16 a , a light shielding layer 50 is formed on the base substrate 1 .

[0195] S23 , as shown in FIG16 b , forming a first insulating layer 31 on the side of the light shielding layer 50 facing away from the base substrate 1 .

[0196] S24 , as shown in FIG. 16 c , a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .

[0197] Specifically, the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.

[0198] S25 . As shown in FIG. 16 d , a second insulating layer 32 and a first conductive layer 41 are formed on the side of the semiconductor layer ACT away from the first insulating layer 31 .

[0199] The second insulating layer 32 is a gate insulating layer, and the first conductive layer 41 includes a gate, or is reused as a gate line Gate of the gate.

[0200] The material of the gate insulating layer and the material of the first conductive layer 41 are deposited in sequence; thereafter, gate photolithography and etching are performed, and the gate insulating layer is etched using the gate as a mask to expose the semiconductor layer ACT and then conduct it. The conduction process can be carried out using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases).

[0201] S26 , as shown in FIG16 e , continue to form a third insulating layer 33 based on step S25 .

[0202] The material of the second insulating layer 32 is deposited, and then the intermediate dielectric layer is photolithographically and etched to form a first via Via1 to the first contact portion 13a of the active layer, a fourth via Via4 to the second contact portion 13b, a fifth via Via5 to the third contact portion 23a, and a second via Via2 to the fourth contact portion 23b.

[0203] S27 . As shown in FIG. 16 f , a second conductive layer 42 is formed on the side of the third insulating layer 33 facing away from the base substrate 1 .

[0204] The material of the second conductive layer 42 is a source / drain metal, and the drain of the first transistor T1 in the source / drain metal is electrically connected to the first contact portion 13a through the first via Via1 that penetrates the third insulating layer 33. The source of the first transistor T1 is electrically connected to the drain of the second transistor T2, and is electrically connected to the second contact portion 13b and the third contact portion 23a through the fourth via Via4 and the fifth via Via5 respectively. The source of the second transistor T2 is electrically connected to the fourth contact portion 23b through a second via Via2. The auxiliary component 6 is reused as the source of the second transistor T2. The auxiliary component 6 is connected to the drain of the second transistor T2 through the third via Via4.

[0205] S28 . As shown in FIG. 16 g , a fourth insulating layer 34 is formed on a side of the second conductive layer 42 away from the third insulating layer 33 .

[0206] The fourth insulating layer 34 is a planarization layer.

[0207] The material of the planarization layer is deposited, and then the organic material is photolithography performed to form the first sub-hole Via31.

[0208] S29 . As shown in FIG. 16 h , a second electrode 23 is formed on a side of the fourth insulating layer 34 facing away from the third insulating layer 33 .

[0209] The second electrode 23 is a common electrode.

[0210] S210 , as shown in FIG16 i , forming a fifth insulating layer 35 on a side of the second electrode 23 away from the fourth insulating layer 34 .

[0211] The fifth insulating layer 35 is a passivation layer.

[0212] A passivation layer material is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.

[0213] S211 , as shown in FIG16 j , forming a pixel electrode ITO on a side of the fifth insulating layer 35 away from the second electrode 23 .

[0214] The pixel electrode ITO is a slit electrode and has a connecting portion connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through a third via hole Via3; the auxiliary component 6 is connected to the fourth contact portion 23b through a second via hole Via2.

[0215] In some embodiments, FIG. 17 a to FIG. 17 i are schematic diagrams of a process for preparing the display substrate shown in FIG. 13 b according to an embodiment of the present disclosure, specifically including the following steps S31 to S310 , wherein:

[0216] S31, providing a substrate 1.

[0217] In this step, the base substrate 1 is a glass substrate.

[0218] S32 , as shown in FIG17 a , forming a first conductive layer 41 on the base substrate 1 .

[0219] The first conductive layer 41 is a composite film layer, including a buffer layer and a main conductive layer sequentially provided on the base substrate 1. The buffer layer can be made of Ti alloy or Mo alloy, and the main conductive layer can be made of Al or Cu.

[0220] The first conductive layer 41 includes a gate line Gate which is multiplexed as the gate of the first transistor T1 and the gate of the second transistor T2 .

[0221] S33 , as shown in FIG17 b , forming a first insulating layer 31 on a side of the first conductive layer 41 facing away from the substrate 1 .

[0222] S34 , as shown in FIG. 17 c , a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .

[0223] Specifically, the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.

[0224] The semiconductor layer ACT is made conductive by using a mask. The conductive process can be performed by using plasma of gases such as He, Ar, H2, NH3 (including mixed gases) to form the first contact portion 13a and the fourth contact portion 23b of the active layer.

[0225] S35 , as shown in FIG. 17 d , forming a second conductive layer 42 on the side of the semiconductor layer ACT away from the first insulating layer 31 .

[0226] The second conductive layer 42 includes a first electrode T11 of the first transistor T1 and a second electrode T22 of the second transistor T2. The first electrode T11 of the first transistor T1 is directly connected to the first contact portion 13a. The second contact portion 13b serves as the first channel portion 13c of the first transistor T1. The third contact portion 23a serves as the second channel portion 23c of the second transistor T2. The second contact portion 13b and the third contact portion 23a are connected as an integral structure. The second electrode T22 of the second transistor T2 is directly connected to the fourth contact portion 23b.

[0227] In order to prevent the active layer (IGZO) from being excessively damaged by the etching solution, it is preferred to use a Cu stack and a hydrogen peroxide-based etching solution to complete the process of forming the second conductive layer 42 .

[0228] S36 , as shown in FIG17 e , forming a second insulating layer 32 on a side of the second conductive layer 42 away from the first insulating layer 31 .

[0229] The second insulating layer 32 is a channel protection layer.

[0230] S37 . As shown in FIG. 17 f , a third insulating layer 33 is formed on a side of the second insulating layer 32 away from the second conductive layer 42 .

[0231] The third insulating layer 33 is a planarization layer.

[0232] The material of the planarization layer is deposited, and then the organic material is photolithography performed to form the first sub-hole Via31.

[0233] S38 . As shown in FIG. 17 g , a second electrode 23 is formed on a side of the third insulating layer 33 facing away from the second insulating layer 32 .

[0234] The second electrode 23 is a common electrode.

[0235] S39. As shown in FIG. 17h, a fourth insulating layer 34 is formed on the side of the second electrode 23 away from the third insulating layer.

[0236] The fourth insulating layer 34 is a passivation layer.

[0237] A passivation layer material is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.

[0238] S310 , as shown in FIG17 i , forming a pixel electrode ITO on a side of the fourth insulating layer 34 away from the second electrode 23 .

[0239] The pixel electrode ITO is a slit electrode and has a connecting portion connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2 ) through the third via hole Via3 ; the auxiliary component 6 is directly connected to the fourth contact portion 23 b .

[0240] In some embodiments, FIG. 18 a to FIG. 18 i are schematic diagrams of a process for preparing the display substrate shown in FIG. 10 provided in an embodiment of the present disclosure, specifically including the following steps S41 to S410 , wherein:

[0241] S41, providing a base substrate 1.

[0242] In this step, the base substrate 1 is a glass substrate.

[0243] S42 , as shown in FIG18 a , forming a first conductive layer 41 on the base substrate 1 .

[0244] The first conductive layer 41 is a composite film layer, including a buffer layer and a main conductive layer sequentially provided on the base substrate 1. The buffer layer can be made of Ti alloy or Mo alloy, and the main conductive layer can be made of Al or Cu.

[0245] The first conductive layer 41 includes a gate line Gate which is multiplexed as the gate of the first transistor T1 and the gate of the second transistor T2 .

[0246] S43 , as shown in FIG18 b , forming a first insulating layer 31 on a side of the first conductive layer 41 away from the base substrate 1 .

[0247] S44 , as shown in FIG. 18 c , a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .

[0248] Specifically, the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.

[0249] The semiconductor layer ACT is conductively processed using a mask. The conductive process can be performed using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases) to form the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b of the active layer.

[0250] S45 , as shown in FIG. 18 d , forming a second conductive layer 42 on the side of the semiconductor layer ACT away from the first insulating layer 31 .

[0251] The second conductive layer 42 includes a first electrode T11 and a second electrode of the first transistor T1, and a first electrode T21 and a second electrode of the second transistor T2. The second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are integrally formed. The first electrode T11 of the first transistor T1 is directly connected to the first contact portion 13a, the second electrode T12 of the first transistor T1 is directly connected to the second contact portion 13b, the first electrode T21 of the second transistor T2 is directly connected to the third contact portion 23a, and the second electrode T22 of the second transistor T2 is directly connected to the fourth contact portion 23b.

[0252] In order to prevent the active layer (IGZO) from being excessively damaged by the etching solution, it is preferred to use a Cu stack and a hydrogen peroxide-based etching solution to complete the process of forming the second conductive layer 42 .

[0253] S46 , as shown in FIG18 e , forming a second insulating layer 32 on a side of the second conductive layer 42 away from the first insulating layer 31 .

[0254] The second insulating layer 32 is a channel protection layer.

[0255] S47 . As shown in FIG. 18 f , a third insulating layer 33 is formed on a side of the second insulating layer 32 away from the second conductive layer 42 .

[0256] The third insulating layer 33 is a planarization layer.

[0257] The material of the planarization layer is deposited, and then the organic material is photolithography performed to form the first sub-hole Via31.

[0258] S48 . As shown in FIG. 18 g , a second electrode 23 is formed on a side of the third insulating layer 33 facing away from the second insulating layer 32 .

[0259] The second electrode 23 is a common electrode.

[0260] S49. As shown in FIG. 18h, a fourth insulating layer 34 is formed on the side of the second electrode 23 away from the third insulating layer.

[0261] The fourth insulating layer 34 is a passivation layer.

[0262] A passivation layer material is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.

[0263] S410 , as shown in FIG. 18 i , a pixel electrode ITO is formed on a side of the fourth insulating layer 34 away from the second electrode 23 .

[0264] The pixel electrode ITO is a slit electrode and has a connecting portion connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2 ) through the third via hole Via3 ; the auxiliary component 6 is directly connected to the fourth contact portion 23 b .

[0265] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a base substrate, and gate lines and data lines located on the base substrate, wherein the gate lines and the data lines intersect to define a plurality of pixel units; the gate lines extend along a first direction, and the data lines extend along a second direction, and the first direction and the second direction intersect; the pixel unit comprises a first transistor and a second transistor; an active layer of the first transistor comprises a first contact portion and a second contact portion, and an active layer of the second transistor comprises a third contact portion and a fourth contact portion, the first contact portion is electrically connected to the data line, the second contact portion is electrically connected to the third contact portion, and the fourth contact portion is electrically connected to a first electrode of the pixel unit; along the second direction, a maximum spacing between the first contact portion and the gate line is not less than a maximum spacing between the fourth contact portion and the same gate line.

2. The display substrate according to claim 1, wherein: Along the first direction, a width of the first contact portion is smaller than a width of the fourth contact portion.

3. The display substrate according to claim 1, wherein: The orthographic projection of the first contact portion on the base substrate overlaps with the orthographic projection of the data line on the base substrate, the first contact portion includes a first part and a second part connected to each other, the first part is electrically connected to the data line, and along the first direction, the width of the first part is greater than the width of the second part.

4. The display substrate according to claim 3, wherein: The orthographic projection of the fourth contact portion on the substrate overlaps with the orthographic projection of the gate line on the substrate, the fourth contact portion includes a third portion and a fourth portion connected to each other, the fourth portion is electrically connected to the first electrode, and along the second direction, the minimum width of the fourth portion is greater than the minimum width of the third portion.

5. The display substrate according to claim 1, wherein: The first contact portion is electrically connected to the data line through a first via hole, and the fourth contact portion is electrically connected to the first electrode through a second via hole; along the second direction, the minimum spacing between the first via hole and the gate line is greater than the minimum spacing between the second via hole and the same gate line.

6. The display substrate according to claim 1, wherein: The first contact portion is electrically connected to the data line through a first via hole, and the fourth contact portion is electrically connected to the first electrode through a second via hole and a third via hole; along the second direction, the minimum spacing between the first via hole and the gate line is greater than the minimum spacing between the second via hole and the same gate line; The minimum distance between the third via hole and the gate line is smaller than the minimum distance between the second via hole and the same gate line.

7. The display substrate according to claim 6, wherein: The pixel unit further includes an auxiliary component; the auxiliary component includes a fifth portion and a sixth portion connected to each other, the fifth portion is electrically connected to the fourth contact portion through the second via hole; the sixth portion is electrically connected to the first electrode through the third via hole.

8. The display substrate according to claim 7, wherein: The auxiliary component is arranged in the same layer as the data line, and in the first direction, the auxiliary component is arranged between two adjacent data lines at positions where they are connected to the first contact portion.

9. The display substrate according to claim 1, wherein: The first contact portion, the second contact portion, the third contact portion and the fourth contact portion are arranged in the same layer.

10. The display substrate according to claim 1, wherein: The active layer of the first transistor and / or the active layer of the second transistor includes a metal oxide semiconductor material.

11. The display substrate according to claim 10, wherein: The active layers of the first transistor and the second transistor include a plurality of stacked sub-layers, and the mobility of the sub-layers away from the substrate is smaller than the mobility of the sub-layers close to the substrate.

12. The display substrate according to claim 1, wherein: The gate of the first transistor is located on a side of the active layer of the first transistor away from the substrate; the gate of the second transistor is located on a side of the active layer of the second transistor away from the substrate; the active layer of the first transistor and the active layer of the second transistor are arranged on the same layer; The data line is multiplexed as the first electrode of the first transistor; the second contact portion is multiplexed as the second electrode of the first transistor, the third contact portion is multiplexed as the first electrode of the second transistor, and the second contact portion and the third contact portion are connected as an integrated structure.

13. The display substrate according to claim 12, wherein: The first electrode is a pixel electrode; The orthographic projections of the second contact portion and the third contact portion connected as one body on the base substrate partially overlap with the orthographic projection of at least one pixel electrode on the base substrate.

14. The display substrate according to claim 13, wherein: For two adjacent pixel units, the orthographic projection of the second contact portion and the third contact portion connected as one body in one of the pixel units on the base substrate partially overlaps with the orthographic projection of the other pixel unit on the base substrate.

15. The display substrate according to claim 12, wherein: The active layer of the first transistor also includes a first channel portion arranged between the first contact portion and the second contact portion, and the active layer of the second transistor also includes a second channel portion arranged between the third contact portion and the fourth contact portion; the first channel portion, the second contact portion and the third contact portion connected as a whole, and the second channel portion The contour shape of the positive projection on the substrate is U-shaped.

16. The display substrate according to claim 1, wherein: The gate of the first transistor and the gate of the second transistor are arranged in the same layer; the active layer of the first transistor and the active layer of the second transistor are arranged in the same layer; the first electrode and the second electrode of the first transistor are arranged in the same layer as the first electrode and the second electrode of the second transistor; The gate of the first transistor is located on a side of the active layer away from the substrate; the first electrode and the second electrode of the first transistor are located on a side of the gate away from the active layer; The data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integrated structure, and the second electrode of the first transistor is electrically connected to the second contact portion through a fourth via, and the first electrode of the second transistor is electrically connected to the third contact portion through a fifth via.

17. The display substrate according to any one of claims 12 to 16, wherein: The display substrate further comprises a light shielding layer arranged on the pixel unit close to the base substrate; The active layer of the first transistor further includes a first channel portion disposed between the first contact portion and the second contact portion, and the active layer of the second transistor further includes a second channel portion disposed between the third contact portion and the fourth contact portion; The orthographic projection of the light shielding layer on the base substrate at least covers the orthographic projections of the first channel portion and the second channel portion on the base substrate.

18. The display substrate according to claim 17, wherein: In a first direction, a first distance exists between an edge of an outline of an orthographic projection of the light shielding layer on the base substrate and an edge of an outline of an orthographic projection of the first channel portion on the base substrate; In the first direction, there is a second distance between the contour edge of the orthographic projection of the light shielding layer on the base substrate and the contour edge of the orthographic projection of the second channel portion on the base substrate; The first spacing and / or the second spacing ranges from 4 μm to 6 μm.

19. The display substrate according to claim 17, wherein: In the second direction, a third distance exists between an edge of an outline of an orthographic projection of the light shielding layer on the base substrate and an edge of an outline of an orthographic projection of the first channel portion on the base substrate; In the second direction, there is a fourth distance between the contour edge of the orthographic projection of the light shielding layer on the base substrate and the contour edge of the orthographic projection of the second channel portion on the base substrate; The third spacing and / or the fourth spacing ranges from 0 to 4 μm.

20. The display substrate according to any one of claims 1 to 16, wherein: The pixel units in the same row are electrically connected to the same gate line; the gate line is used as the gate of the first transistor and the gate of the second transistor.

21. The display substrate according to any one of claims 1 to 16, wherein: A gate insulating layer is disposed on a side of the gate of the first transistor close to the active layer; the thickness of the gate insulating layer is between 10 nm and 30 nm.

22. The display substrate according to claim 1, wherein: The gate of the first transistor and the gate of the second transistor are arranged in the same layer; the active layer of the first transistor and the active layer of the second transistor are arranged in the same layer; the first electrode and the second electrode of the first transistor are arranged in the same layer as the first electrode and the second electrode of the second transistor; The gate of the first transistor is located on a side of the active layer close to the substrate; the first electrode and the second electrode of the first transistor are located on a side of the active layer away from the gate; The data line is multiplexed into the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integral structure, and the second electrode of the first transistor is electrically connected to the second contact portion of the first transistor; the first electrode of the second transistor is electrically connected to the second contact portion of the second transistor The third contacts of the transistors are electrically connected.

23. The display substrate according to claim 22, wherein: The pixel units in the same row are electrically connected to the same gate line; the gate line is used as the gate of the first transistor and the gate of the second transistor; The gate line is a composite film layer, comprising a buffer layer and a main conductive layer which are sequentially arranged on the base substrate.

24. The display substrate according to claim 22, wherein: A gate insulating layer is disposed on a side of the gate of the first transistor close to the active layer; the thickness of the gate insulating layer is between 30nm and 50nm.

25. A display device, wherein: The invention comprises the display substrate according to any one of claims 1 to 24.

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