Configurable network on chip

Abstract

Provided in the embodiments of the present disclosure are a configurable network on chip. The network on chip may comprise at least one sub-network including k-element n-dimensional nodes, the nodes of the network on chip are connected by means of network links, a selector is arranged between adjacent nodes, and the connection / disconnection of all network links in each sub-network and all network links between sub-networks is controlled by means of selectors to configure the topological structure of the network on chip. The topological structure of the network on chip can be flexibly configured on the basis of task requirements, so that the network on chip has good scalability, thereby solving the problems of a large transmission delay and limited transmission paths of the topological structure of an existing network on chip in a complex task scenario.

Description

Configurable Network-on-Chip

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on Chinese patent application CN202311026782.1 filed on August 15, 2023, with the invention name “Configurable on-chip network”, and claims the priority of the patent application, and all the contents disclosed therein are incorporated into this disclosure by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of communications, and in particular, to a configurable network on chip. Background Art

[0004] Neural network processing units (NPUs) are a representative many-core architecture with broad application prospects and great future potential. However, traditional communication methods limit NPU communication bandwidth, core count, and scalability. Introducing a network-on-chip (NoC) bus interconnect architecture into the NPU will significantly alleviate communication bandwidth limitations and facilitate the addition and expansion of NPU cores.

[0005] However, as the number of NPU cores increases, the existing on-chip network topology structure has problems such as a single transmission path and large transmission delay in complex task scenarios.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure provide a configurable on-chip network to at least solve the problems of the existing on-chip network topology structure in complex task scenarios in the related art, such as a single transmission path and large transmission delay.

[0008] According to one embodiment of the present disclosure, a configurable on-chip network is provided, wherein the on-chip network includes at least one k-ary n-dimensional sub-network of nodes; the nodes of the on-chip network are connected via network links; a selector is connected between two adjacent nodes;

[0009] The selector is used to configure the topology of the on-chip network by controlling the on-off of all network links of the on-chip network.

[0010] In an exemplary embodiment, the sub-network includes pier nodes, and the pier nodes of different sub-networks are connected via the network links.

[0011] In an exemplary embodiment, the on-chip network further includes a bridge node, and the bridge node is located between sub-networks; wherein each of the pier nodes is connected to one bridge node, and a plurality of adjacent pier nodes are connected to the same bridge node.

[0012] In an exemplary embodiment, a plurality of the bridge nodes are connected via the network link; and the selector is connected between adjacent bridge nodes.

[0013] In an exemplary embodiment, the network link includes at least one of the following types: a mesh link, a ring link, and a configurable link.

[0014] In an exemplary embodiment, two ends of the configurable link are respectively connected to different selectors; wherein the configurable link is a cross-node link, and the two ends of the configurable link are configured to cross one or more nodes.

[0015] In an exemplary embodiment, the selector is further configured to select one of the network links for connection when multiple network links are connected.

[0016] In an exemplary embodiment, the bridge nodes in the same row or column are connected via the ring links.

[0017] In an exemplary embodiment, the topology of the on-chip network includes an intra-subnetwork topology and an inter-subnetwork topology, and the intra-subnetwork topology and the inter-subnetwork topology are configured with different routing algorithms; wherein the inter-subnetwork topology is a topology formed by connecting multiple bridge nodes through the network links.

[0018] In an exemplary embodiment, the bridge node is configured with an inter-sub-network routing algorithm according to the inter-sub-network topology.

[0019] In an exemplary embodiment, the sub-network further includes non-pier nodes, and the non-pier nodes in the topological structure within the sub-network and the pier nodes in the topological structure within the sub-network are configured with different routing algorithms.

[0020] In an exemplary embodiment, the non-bridge node is configured with a label relabeling algorithm, and the bridge node is configured with a fusion routing algorithm of the inter-subnetwork routing algorithm and the relabeling algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a structural diagram of a configurable on-chip network according to an embodiment of the present disclosure;

[0022] FIG2 is a schematic diagram of a configurable heterogeneous sub-network structure according to an embodiment of the present disclosure;

[0023] FIG3 is a schematic diagram of a sub-network configuration as a ring-type topology according to an embodiment of the present disclosure;

[0024] FIG4 is a schematic diagram of a mesh topology structure in which a sub-network is configured according to an embodiment of the present disclosure;

[0025] FIG5 is a schematic diagram of a sub-network configuration as a cmesh topology structure according to an embodiment of the present disclosure;

[0026] FIG6 is a schematic diagram of a torus-type topology structure of a sub-network configuration according to an embodiment of the present disclosure;

[0027] FIG7 is a schematic diagram of a sub-network configured as a tree topology according to an embodiment of the present disclosure;

[0028] FIG8 is a schematic diagram of a sub-network configured as a hypercube topology according to an embodiment of the present disclosure;

[0029] FIG9 is a schematic diagram of a global integration of 2×2 heterogeneous sub-networks according to an embodiment of the present disclosure;

[0030] FIG10 is a schematic diagram of a global integration of 2×4 heterogeneous sub-networks according to an embodiment of the present disclosure;

[0031] FIG11 is a schematic diagram of a global integration of 4×4 heterogeneous sub-networks according to an embodiment of the present disclosure;

[0032] FIG12 is a schematic diagram of routing numbers within a network according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0035] Networks on Chips (NoCs) draw on the communication methods of distributed computing systems, employing routing and packet switching technologies to replace traditional buses. They offer a new approach to complex on-chip communication. NoC technology addresses three key architectural issues inherent in bus architectures: scalability due to limited address space, communication efficiency issues due to time-sharing, and power consumption and area issues due to global synchronization.

[0036] The key technologies of on-chip networks are:

[0037] Topology: The topology of a NoC is the arrangement of communicating node elements. The ability of a NoC to communicate effectively depends largely on the underlying topology.

[0038] Routing algorithm: The routing algorithm establishes the path that each message or packet will execute, and searches for a data transmission path that satisfies certain restrictions on the on-chip network structure.

[0039] Currently, on-chip networks (NOCs) primarily have three topologies: mesh, torus, and tree. The routing algorithm primarily uses the XY-order routing algorithm. Existing topologies are designed for specific applications and lack configurability based on application tasks. Furthermore, the corresponding routing algorithms are designed for specific topologies and lack the ability to route across multiple topologies.

[0040] Networks on a chip (NoCs) are primarily designed to address communication issues in multi-core / many-core architectures. Topology and routing algorithms are key elements of NoC technology. A suitable topology and routing algorithm can significantly enhance inter-core communication capabilities. Introducing NoCs as bus interconnects within NPUs significantly alleviates communication bandwidth limitations, facilitating the addition and expansion of NPU cores.

[0041] However, as the number of NPU cores increases, existing topologies suffer from high transmission latency and a single transmission path. Furthermore, given the diversity of NPU network connections and the sheer volume of data, single topologies like mesh and torus connections can easily cause communication issues.

[0042] The technical concept of the present disclosure is to select a k-element, n-dimensional network unit as a subnetwork of an on-chip network. The on-chip network can be composed of one or more subnetworks, and the nodes of the on-chip network are connected by network links. Selectors are set between nodes within each subnetwork, and selectors are set between nodes between subnetworks. The selectors are used to control the on-off of all network links within a subnetwork and all network links between subnetworks, thereby configuring the topology of the on-chip network. The topology of the on-chip network can be flexibly configured according to task requirements, making the on-chip network have good scalability, thereby solving the problems of large transmission delays and single transmission paths in existing on-chip network topologies in complex task scenarios.

[0043] The disclosed embodiments support communication tasks in multi-core / many-core systems and are applicable to artificial intelligence (AI) acceleration application environments such as service and communication, including but not limited to scenarios such as data centers, autonomous driving, virtual currency, and terminal AI.

[0044] Figure 1 is a structural diagram of a configurable on-chip network according to an embodiment of the present disclosure. The on-chip network includes at least one sub-network 10 with k elements and n dimensions. As shown in Figure 1, taking the on-chip network including a 4-element, 2-dimensional (i.e., 4×4) sub-network 10 as an example, the nodes 101 of the on-chip network are connected by network links 102; a selector 103 is connected between two adjacent nodes; the selector is used to configure the topology of the on-chip network by controlling the on and off of all network links of the on-chip network.

[0045] Network-on-chip (NoC) technology converts data transmission between IP cores into data forwarding between routers. Nodes on a NoC can include a processing unit node and a router node, with each router connected to a processing unit. In this disclosure, the routing node is used as a node on a subnetwork.

[0046] Here, K is the number of nodes on the edge of each sub-network. For example, a 4x4 mesh sub-network and a 4-element 2-dimensional torus sub-network both have a total of 16 nodes.

[0047] For example, a 4x4 sub-network 10 can be built first, and the nodes 101 in the sub-network 10 are connected through network links 102. On this basis, a selector 103 can be added and set between each adjacent node 101. The selector 103 is connected to the adjacent node 101 through the network link 102.

[0048] For example, the selector 103 may control the network link 102 , thereby controlling the input and output of the node.

[0049] The selector 103 of this embodiment can switch all links in the sub-network in real time according to application requirements, thereby realizing heterogeneity of the sub-network.

[0050] It should be noted that the above-mentioned selection of a 4x4 size sub-network is only an example. Sub-networks of other sizes, such as 3x3, 5x5, etc., can also be selected in the heterogeneous method, and the embodiments of the present disclosure are not limited thereto.

[0051] In an exemplary embodiment, the network link includes at least one of the following types: a mesh link, a ring link, and a configurable link.

[0052] For example, FIG2 is a schematic diagram of a configurable heterogeneous sub-network structure according to an embodiment of the present disclosure. Referring to FIG2 , the sub-network includes a network link 201, a router 202, a processing unit 203, a network interface (NI) (not shown in the figure), and a selector 204. The network link 201 may include at least the following three link structures: a mesh link 2011, a ring link 2012, and a configurable link 2013.

[0053] As an example, the mesh structure link 2011 is the link in the horizontal and vertical directions of the router, the ring link 2012 is the link between the sub-network edge nodes, and the configurable link 2013 is a link added to increase the variability of the topology and is a cross-node link.

[0054] In an exemplary embodiment, the two ends of the configurable link 2013 are respectively connected to different selectors; wherein, the configurable link 2013 is a cross-node link, and the two ends of the configurable link 2013 are configured to cross one or more nodes.

[0055] For example, the two ends of configurable link 2013 can be connected to different selectors, and configurable link 2013 can span one or more nodes depending on the size of the subnetwork. Configurable link 2013 can be connected to the same selector as mesh structure link 2011 and ring link 2012 in the same direction at some nodes.

[0056] In an exemplary embodiment, the selector 204 is further configured to select one of the network links 202 for connection when multiple network links 202 are connected.

[0057] For example, when a selector is connected to multiple network links, it can select an appropriate network link for connection based on the actual application scenario, thereby reducing the technical problem of large transmission delays. As shown in Figure 2, one end of selector 204 is connected to router 202 via a network link 201, and the other end is connected to different routers via two network links 201. Of the two network links 201 connected to selector 204, one can be a configurable link 2013. Configurable link 2013 can connect to another selector across a node. When the selector selects to connect to configurable link 2013, the subnetwork can achieve cross-node communication.

[0058] As an example, a subnetwork can use a selector to control the connectivity of network links between nodes within the subnetwork, thereby achieving heterogeneity in the subnetwork. For example, the topology within the subnetwork can be configured using a selector to be a ring, mesh, concentrated mesh (cmesh), torus, tree, hypercube, or other irregular topologies.

[0059] The following examples further illustrate the heterogeneity of sub-networks:

[0060] Example 1:

[0061] Figure 3 is a schematic diagram of a sub-network configured as a ring topology according to an embodiment of the present disclosure. As shown in Figure 3, gray links are disabled links, and black links are enabled links. A selector only needs to control the activation of some mesh links to configure a ring topology.

[0062] Example 2:

[0063] Figure 4 is a schematic diagram of a mesh topology structure configured as a sub-network according to an embodiment of the present disclosure. As shown in Figure 4, gray links are disabled links, black links are enabled links, and the selector only needs to control some mesh links to be enabled to configure a mesh topology structure.

[0064] Example 3:

[0065] Figure 5 is a schematic diagram of a sub-network configured as a CMEsh topology structure according to an embodiment of the present disclosure. As shown in Figure 5, gray links are disabled links, and black links are enabled links. To facilitate the expansion of the topology structure, the corner nodes of the sub-network can be selected as centralized nodes of the CMEsh topology. The selector only needs to control the opening of some mesh links and ring links to configure the CMEsh topology structure.

[0066] Example 4:

[0067] Figure 6 is a schematic diagram of a torus-type topology structure configured as a sub-network according to an embodiment of the present disclosure. As shown in Figure 6, gray links are disabled links, black links are enabled links, and the selector only needs to control the mesh link and ring link to be enabled to configure the torus topology structure.

[0068] Example 5:

[0069] Figure 7 is a schematic diagram of a tree-type topology structure configured as a sub-network according to an embodiment of the present disclosure. As shown in Figure 7, gray links are disabled links, and black links are enabled links. To facilitate the expansion of the topology, the corner nodes of the sub-network can be selected as the root nodes of the tree topology. The selector only needs to control the opening of some mesh links, ring links and configurable links to configure the tree topology structure. Among them, the root node of the tree topology can be selected according to the needs of horizontal expansion.

[0070] Example 6:

[0071] Figure 8 is a schematic diagram of a sub-network configured as a hypercube topology structure according to an embodiment of the present disclosure. As shown in Figure 8, gray links are disabled links, black links are enabled links, and the selector only needs to control the activation of some mesh links and configurable links to configure a hypercube topology structure.

[0072] The disclosed embodiments increase the variability of the topology of the on-chip network by adding selectors and partially configurable links. The topology can be configured into the required topology according to the application scenario, and the topology can also be customized according to user needs. This greatly improves the types and range of configurable topologies and has advantages over a single type of topology in terms of execution performance in different applications.

[0073] In addition, in terms of the global topology integration method of the hierarchical topology structure, multiple topologies can be selected as the hierarchical topology, and sub-networks can also be directly connected for communication.

[0074] In an exemplary embodiment, the sub-network includes pier nodes, and the pier nodes of different sub-networks are connected via the network links.

[0075] Exemplarily, nodes within a sub-network can be divided into pier nodes and non-pier nodes. Pier nodes in different sub-networks are connected via network links, and different sub-networks communicate with each other via the pier nodes.

[0076] As an example, the pier node can be selected based on the processing capability of the nodes in the sub-network or the amount of tasks to be processed. For example, if the corner node in the sub-network has high processing capability and a small amount of tasks to be processed, the corner node can be selected as the pier node for cross-sub-network communication.

[0077] It should be noted that the above selection of the corner node in the subnetwork as the pier node is only an example of the present disclosure. Those skilled in the art can select any node in the subnetwork as the pier node according to actual conditions, and the embodiments of the present disclosure are not limited here.

[0078] In an exemplary embodiment, the on-chip network further includes a bridge node, and the bridge node is located between the sub-networks; wherein each of the pier nodes is connected to one bridge node, and multiple adjacent pier nodes are connected to the same bridge node.

[0079] In the disclosed embodiments, different subnetworks can communicate directly through their respective pier nodes, or they can add bridge nodes between subnetworks to establish connections between adjacent pier nodes for communication. Those skilled in the art can choose to add bridge nodes based on actual mission scenarios.

[0080] For example, in order to ensure the minimum number of communication hops between sub-networks and reduce competition, a bridge node can be added outside the sub-network to be responsible for communication between sub-networks. The nodes connected to the bridge node are pier nodes. Each pier node can be connected to a bridge node, and multiple adjacent pier nodes can be connected to the same bridge node.

[0081] In an exemplary embodiment, a plurality of the bridge nodes are connected via the network link; and the selector is connected between adjacent bridge nodes.

[0082] For example, there can be multiple bridge nodes, each connected via network links. Selectors are connected between adjacent bridge nodes. The selectors configure the topology of the subnetworks by controlling the connectivity of network links between bridge nodes. For example, the degree of both bridge nodes and pier nodes can be set to 5, and the redundant links can be connected using selectors.

[0083] As an example, the topology between the bridge nodes between sub-networks can select mesh, torus or tree topologies according to the number of sub-networks, or the topology between the bridge nodes can be customized. The links in the configurable on-chip network topology can be appropriately increased or decreased according to application requirements, which is not limited in this embodiment.

[0084] As an example, heterogeneous sub-networks can be globally integrated to achieve network-on-chip expansion of different sizes. The following examples further illustrate the global integration of heterogeneous sub-networks:

[0085] Example 7:

[0086] Figure 9 is a schematic diagram of a global integration of 2x2 heterogeneous subnetworks according to an embodiment of the present disclosure. Referring to Figure 9 , the corner nodes of each subnetwork serve as bridge nodes. Adjacent bridge nodes between subnetworks are connected via a bridge node. Each subnetwork can have a different topology. As shown in Figure 9 , the subnetwork topologies from left to right and from top to bottom are mesh, torus, tree, and cmesh. The bridge nodes between subnetworks are connected via ring-shaped links.

[0087] FIG9 horizontally expands four 4x4 sub-networks into an 8x8 NoC, which includes four intra-sub-network topologies and one 3x3 inter-sub-network topology.

[0088] Example 8:

[0089] FIG10 is a schematic diagram of a global integration of 2x4 heterogeneous subnetworks according to an embodiment of the present disclosure. Referring to FIG10 , the corner nodes of each subnetwork serve as bridge nodes. Adjacent bridge nodes between subnetworks are connected by a bridge node. Each subnetwork can have a different topology. As shown in FIG10 , the subnetwork topologies from left to right and from top to bottom are mesh, torus, mesh, torus, tree, cmesh, tree, cmesh. The bridge nodes between subnetworks are connected by ring-shaped links.

[0090] Figure 10 horizontally expands eight 4x4 sub-networks into an 8x16 NoC, which includes eight intra-sub-network topologies and one 3x5 inter-sub-network topology.

[0091] Example 9:

[0092] FIG11 is a schematic diagram of a global integration of 4x4 heterogeneous subnetworks according to an embodiment of the present disclosure. Referring to FIG11 , the corner nodes of each subnetwork serve as bridge nodes. Adjacent bridge nodes between subnetworks are connected by a bridge node. Each subnetwork can have a different topology. As shown in FIG11 , the topologies of the subnetworks from left to right and from top to bottom are mesh, torus, mesh, torus, tree, cmesh, tree, cmesh, mesh, torus, mesh, torus, tree, cmesh, tree, cmesh. The bridge nodes between subnetworks are connected by ring-shaped links.

[0093] FIG11 expands 16 4x4 sub-networks horizontally and vertically into a 16x16 NoC, which includes 16 intra-sub-network topologies and one 5x5 inter-sub-network topology.

[0094] That is, global integration is based on the connection of sub-networks. You can first select pier nodes in the sub-network that can communicate across sub-networks, then add bridge nodes that can communicate between sub-networks, and connect the bridge nodes to the pier nodes in the corresponding sub-networks. Among them, the bridge nodes between sub-networks can be connected by selecting a topological structure. For example, you can select a topological structure such as a mesh structure, a torus structure, etc. to connect them, thereby obtaining an expanded on-chip network.

[0095] In an exemplary embodiment, the bridge nodes in the same row or column are connected via the ring links.

[0096] As an example, when horizontally expanding a topology of 4 or 8 4x4 configurable sub-networks, to ensure the minimum number of communication hops between sub-networks and equal support for multiple topologies, the corner nodes of the sub-network can be selected as pier nodes, and bridge nodes can be added outside the pier nodes. Bridge nodes in the same row or column can be connected in a ring-type topology.

[0097] In an exemplary embodiment, the topology of the on-chip network includes an intra-subnetwork topology and an inter-subnetwork topology, and the intra-subnetwork topology and the inter-subnetwork topology are configured with different routing algorithms; wherein, the inter-subnetwork topology is a topology formed by connecting multiple bridge nodes through the network links.

[0098] Exemplarily, the topology structure of the network on chip may include an intra-subnetwork topology structure and an inter-subnetwork topology structure, and the intra-subnetwork topology structure and the inter-subnetwork topology structure are configured with different routing algorithms.

[0099] Among them, the inter-subnetwork topology is a topology formed by connecting multiple bridge nodes through network links; the intra-subnetwork topology is a topology formed by connecting multiple intra-subnetwork nodes through network links.

[0100] In an exemplary embodiment, the bridge node is configured with an inter-sub-network routing algorithm according to the inter-sub-network topology.

[0101] For example, an inter-subnetwork routing algorithm can be configured for bridge nodes between subnetworks based on the inter-subnetwork topology. For example, if the inter-subnetwork routing algorithm is a deterministic routing algorithm (such as an xy-order routing algorithm) and the inter-subnetwork topology is a mesh structure, the source address and destination address can be determined according to the mesh structure, and corresponding coordinates can be configured for each bridge node in the mesh structure.

[0102] As an example, the inter-subnetwork routing algorithm may also perform inter-subnetwork isolation functions.

[0103] In an exemplary embodiment, the sub-network further includes non-pier nodes, and the non-pier nodes in the topological structure within the sub-network and the pier nodes in the topological structure within the sub-network are configured with different routing algorithms.

[0104] For example, non-pier nodes in the topology structure within a sub-network do not directly participate in cross-network node communication. Pier nodes can not only participate in internal communication within the sub-network, but also participate in communication between sub-networks and bridge nodes. Therefore, non-pier nodes and pier nodes can be configured with different routing algorithms.

[0105] In an exemplary embodiment, the non-bridge node is configured with a label relabeling algorithm, and the bridge node is configured with a fusion routing algorithm of the inter-subnetwork routing algorithm and the relabeling algorithm.

[0106] For example, a label rewriting relabeling algorithm may be configured for non-pier nodes, and a fusion routing algorithm of an inter-subnetwork routing algorithm and a relabeling algorithm may be configured for pier nodes, that is, a relabeling algorithm may be used within a subnetwork.

[0107] As an example, since the routing algorithm determines the routing direction based on the routing number, when the topology changes, the relabeling algorithm will rearrange the routing numbers according to the new topology and synchronously configure them to each routing node. The routing algorithm then routes according to the new numbers to achieve the conversion between physical ID and virtual ID, making it easy to implement routing for various topologies, and the implementation is simple and low-cost.

[0108] The following example further illustrates the routing algorithm within a subnet:

[0109] Example 10:

[0110] Figure 12 is a schematic diagram of intra-network route numbering according to an embodiment of the present disclosure. The starting route numbering in a subnetwork is shown in Figure 12. The numerical numbers represent the three dimensions z, y, and x, respectively. Y and x are intra-network route numbers, and z is an inter-subnetwork route number. Nodes 000, 003, 030, and 033 can be selected as pier nodes within a subnetwork, while the remaining nodes are non-pier nodes within the subnetwork. Source and target nodes can be selected based on the application scenario, and routing can be performed from the source node to the target node according to the node numbers. When the topology changes, the routing algorithm configured on the node can change the corresponding number to adapt to the new topology, thereby achieving the function of real-time topology configuration without changing the routing algorithm.

[0111] In the disclosed embodiment, a set of routing algorithms can be used within a sub-network to solve the communication problem of multiple routing heterogeneous sub-networks with low cost and strong feasibility.

[0112] In this embodiment, the disclosed configurable on-chip network may include one or more k-element, n-dimensional node subnetworks. The nodes of the on-chip network are connected via network links. Selectors are provided between adjacent nodes to control the on / off switching of all network links within a subnetwork and between subnetworks to configure the topology of the on-chip network. This allows the topology of the on-chip network to be flexibly configured according to task requirements, resulting in good scalability of the on-chip network, thereby resolving the problems of large transmission delays and single transmission paths in existing on-chip network topologies in complex task scenarios.

[0113] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A configurable on-chip network, the on-chip network comprising at least one sub-network of k-ary and n-dimensional nodes; the nodes of the on-chip network are connected via network links; and a selector is connected between two adjacent nodes; The selector is used to configure the topology of the on-chip network by controlling the on-off of all network links of the on-chip network.

2. The network on chip according to claim 1, wherein: The sub-network includes bridge nodes, and the bridge nodes of different sub-networks are connected via the network links.

3. The network on chip according to claim 2, wherein: The network on chip also includes a bridge node, and the bridge node is located between the sub-networks; wherein each of the pier nodes is connected to a bridge node, and a plurality of adjacent pier nodes are connected to the same bridge node.

4. The network on chip according to claim 3, wherein: A plurality of the bridge nodes are connected via the network link; and the selector is connected between adjacent bridge nodes.

5. The network on chip according to any one of claims 1 to 4, wherein: The network link includes at least one of the following types: a mesh link, a ring link, and a configurable link.

6. The network on chip according to claim 5, wherein: Two ends of the configurable link are respectively connected to different selectors; wherein the configurable link is a cross-node link, and the two ends of the configurable link are configured to cross one or more nodes.

7. The network on chip according to claim 6, wherein: The selector is also used to select one of the network links to be connected when multiple network links are connected.

8. The network on chip according to claim 5, wherein: The bridge nodes in the same row or column are connected via the ring link.

9. The network on chip according to claim 4, wherein: The topological structure of the on-chip network includes an intra-subnetwork topological structure and an inter-subnetwork topological structure, and the intra-subnetwork topological structure and the inter-subnetwork topological structure are configured with different routing algorithms; wherein the inter-subnetwork topological structure is a topological structure formed by connecting multiple bridge nodes through the network links.

10. The network on chip according to claim 9, wherein: The bridge node is configured with an inter-sub-network routing algorithm according to the inter-sub-network topology structure.

11. The network on chip according to claim 9, wherein: The sub-network also includes non-pier nodes, and the non-pier nodes in the topological structure within the sub-network and the pier nodes in the topological structure within the sub-network are configured with different routing algorithms.

12. The network on chip according to claim 11, wherein: The non-bridge nodes are configured with a label relabeling algorithm, and the bridge nodes are configured with a fusion routing algorithm of the inter-subnetwork routing algorithm and the relabeling algorithm.

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