Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises: a display area, having multiple sub-pixels; and a wiring area, located on one side of the multiple sub-pixels. The wiring area comprises an input area, an output area, and a dummy area; the dummy area is located between the input area and the output area; the input area is provided with multiple input protrusions; the output area is provided with multiple output protrusions; the dummy area is provided with multiple dummy protrusions; a first gap area is present between the multiple output protrusions and the multiple dummy protrusions; a second gap area is present between the multiple input protrusions and the multiple dummy protrusions; and the second gap area is provided with a stress equalization structure. Therefore, the generation of cracks in an inorganic insulating layer in an integrated circuit binding process can be mitigated or avoided, thereby avoiding defects caused by cracks in the inorganic insulating layer.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202311021581.2 filed on August 14, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0003] With the expansion of applications of flexible organic light-emitting diode (OLED) screens, foldable products have gradually occupied the market in recent years.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a display panel and a display device.

[0006] On the one hand, at least one embodiment of the present disclosure provides a display panel, comprising: a display area having a plurality of sub-pixels; and a wiring area located on one side of the plurality of sub-pixels; the wiring area having an input area, an output area, and a dummy area, the dummy area being located between the input area and the output area, the input area having a plurality of input protrusions, the output area having a plurality of output protrusions, the dummy area having a plurality of dummy protrusions, a first spacing area between the plurality of output protrusions and the plurality of dummy protrusions, a second spacing area between the plurality of input protrusions and the plurality of dummy protrusions, and a stress balancing structure being provided in the second spacing area.

[0007] For example, the stress equalization structure includes a plurality of auxiliary wirings, and the plurality of auxiliary wirings pass through the second spacing region.

[0008] For example, the first spacing area includes a plurality of signal connection lines, and a wiring density of the plurality of auxiliary wirings is greater than or equal to a wiring density of the plurality of signal connection lines.

[0009] For example, near the dummy area, the directions of the plurality of signal connection lines are axially symmetrical with the directions of the plurality of auxiliary wiring lines.

[0010] For example, the multiple dummy protrusions are arranged in a row along the first direction and are axially symmetrical along the second direction. Near the dummy area, the directions of the multiple signal connection lines are axially symmetrical with the directions of at least part of the auxiliary wiring along the second direction, and the first direction and the second direction intersect.

[0011] For example, the plurality of auxiliary wirings include bending lines.

[0012] For example, the bending line has a first part, a second part, and a third part, the second part is located between the first part and the third part, the angle between the second part and the first part is an obtuse angle, the angle between the second part and the third part is an obtuse angle, and the direction of the second part is from the virtual area to the input area.

[0013] For example, the plurality of auxiliary wirings include a disconnected line, and the disconnected line is disconnected at the second portion into two portions located on both sides of the second portion.

[0014] For example, the stress equalization structure includes a plurality of auxiliary blocks.

[0015] For example, the plurality of auxiliary blocks are arranged in an array.

[0016] For example, the area of ​​at least part of the auxiliary block is smaller than the area of ​​the input protrusion and smaller than the area of ​​the dummy protrusion.

[0017] For example, the stress-balancing structure includes auxiliary protrusions, and the auxiliary protrusions include a first auxiliary protrusion. The first auxiliary protrusion is located on a side of the plurality of input protrusions close to the dummy region.

[0018] For example, the minimum spacing between the first auxiliary protrusion and the multiple dummy protrusions is a first spacing, and the ratio of the absolute value of the difference between the first spacing and the minimum size of the first spacer to the minimum size of the first spacer is greater than or equal to 0 and less than or equal to 10%.

[0019] For example, the display panel further includes an alignment mark located between the first auxiliary protrusion and the plurality of input protrusions, and a distance between the first auxiliary protrusion and an adjacent input protrusion is greater than a distance between two adjacent input protrusions.

[0020] For example, the auxiliary protrusion further includes a second auxiliary protrusion, and the second auxiliary protrusion is located on a side of the plurality of dummy protrusions close to the input area.

[0021] For example, the minimum distance between the first auxiliary protrusion and the second auxiliary protrusion is a second distance, and the minimum size of the first spacing area is greater than the second distance.

[0022] For example, the minimum dimension of the first spacing region is greater than 1.5 times the second spacing.

[0023] For example, the minimum size of the first spacing area is greater than twice the second spacing.

[0024] For example, the display panel further includes a peripheral area surrounding the display area, and the peripheral area has a crack detection line, wherein the crack detection line passes through the second spacer area.

[0025] For example, the display panel further includes a source test line, the source test line is located in the peripheral area and on one side of the crack detection line, and the source test line passes through the second spacer area.

[0026] For example, the display panel further includes a data line configured to provide a data voltage to the sub-pixel, and the plurality of output bumps include an output bump connected to the data line.

[0027] For example, the display panel further includes an integrated circuit, and the multiple conductive structures on the integrated circuit are respectively connected to the multiple input protrusions, the multiple output protrusions, and the multiple dummy protrusions on the display panel through anisotropic adhesive.

[0028] For example, the display panel further includes an inorganic insulating layer, which includes at least a portion located in the second spacer area, and the stress equalization structure is configured to equalize the stress of the portion of the inorganic insulating layer located in the second spacer area during the integrated circuit binding process.

[0029] On the other hand, an embodiment of the present disclosure also provides a display panel, comprising: a display area having a plurality of sub-pixels; and a wiring area located on one side of the plurality of sub-pixels; the wiring area having an input area, an output area, and a dummy area, the dummy area being located between the input area and the output area, the input area having a plurality of input protrusions, the output area having a plurality of output protrusions, the dummy area having a plurality of dummy protrusions, a first spacing area between the plurality of output protrusions and the plurality of dummy protrusions, a second spacing area between the plurality of input protrusions and the plurality of dummy protrusions, and a plurality of auxiliary wirings, a plurality of auxiliary blocks, or at least one auxiliary protrusion in the second spacing area.

[0030] For example, in the display panel provided in an embodiment of the present disclosure, the multiple auxiliary wirings pass through the second spacing area, the first spacing area includes multiple signal connection lines, and the wiring density of the multiple auxiliary wirings is greater than or equal to the wiring density of the multiple signal connection lines.

[0031] For example, in the display panel provided by the embodiment of the present disclosure, an area of ​​each of the plurality of auxiliary blocks is smaller than an area of ​​each of the plurality of input protrusions, and smaller than an area of ​​each of the plurality of dummy protrusions.

[0032] For example, in the display panel provided in the embodiment of the present disclosure, the at least one auxiliary protrusion includes a first auxiliary protrusion located in the input area and / or a second auxiliary protrusion located in the dummy area, and the minimum spacing between the first auxiliary protrusion and the dummy protrusion most adjacent to it, the minimum spacing between the second auxiliary protrusion and the input protrusion most adjacent to it, or the absolute value of the difference between the minimum spacing between the first auxiliary protrusion and the second auxiliary protrusion and the minimum size of the first spacing area is greater than or equal to 0 and less than or equal to 10% to the minimum size of the first spacing area.

[0033] On the other hand, an embodiment of the present disclosure further provides a display device, comprising any of the above-mentioned display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0035] FIG1 is a partial schematic diagram of a display panel.

[0036] FIG. 2 is a schematic diagram of a crack in the display panel shown in FIG. 1 .

[0037] FIG. 3 is a schematic diagram of a wiring area of ​​a display panel.

[0038] FIG4 is a schematic diagram of a display panel (before IC binding) provided by an embodiment of the present disclosure.

[0039] FIG5 is a schematic diagram of a display panel (after IC binding) provided by an embodiment of the present disclosure.

[0040] FIG6 is a schematic diagram of a wiring area of ​​a display panel provided by an embodiment of the present disclosure.

[0041] FIG. 7A is a schematic diagram of a wiring area of ​​another display panel provided by an embodiment of the present disclosure.

[0042] FIG7B is a schematic diagram of a wiring area of ​​another display panel provided by an embodiment of the present disclosure.

[0043] FIG8A is a schematic diagram of a wiring area of ​​another display panel provided by an embodiment of the present disclosure.

[0044] FIG8B is a schematic diagram of a wiring area of ​​another display panel provided by an embodiment of the present disclosure.

[0045] FIG9 is a partial diagram of a display panel provided by an embodiment of the present disclosure.

[0046] FIG10 is a partial view of another display panel provided in an embodiment of the present disclosure.

[0047] FIG11 is a partial view of another display panel provided in an embodiment of the present disclosure.

[0048] FIG12 is a schematic diagram of a display panel (after IC binding) provided by an embodiment of the present disclosure.

[0049] FIG13 is a schematic diagram of a sub-pixel of a display panel provided according to an embodiment of the present disclosure.

[0050] FIG. 14A is a schematic diagram of a display panel in which an anisotropic adhesive layer is formed on a base substrate with protrusions formed thereon and a bonding process is not performed.

[0051] FIG. 14B is a schematic diagram of a display panel formed after the bonding process.

[0052] FIG15 is a structural diagram of an integrated circuit.

[0053] FIG. 16 is a partial schematic diagram of a display panel before the bonding process.

[0054] FIG17 is a partial schematic diagram of a display panel after the binding process. DETAILED DESCRIPTION

[0055] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0057] After flexible OLEDs are applied to foldable products, the screen quality in terms of picture quality and flicker needs to be further improved.

[0058] For OLED display products, they can be upgraded from low-temperature polysilicon (LTPS) type to low-temperature polycrystalline-oxide (LTPO) type to meet the higher image quality requirements of foldable products.

[0059] During the production process of LTPO-type foldable products, the production line consistently experienced 3%-7% panel crack detection (PCD) failures (Not Good, NG) . Analysis revealed that cracks were generated during the integrated circuit (IC) bonding process, causing the panel crack detection lines in the IC area to break, leading to panel crack detection failures. Therefore, the panel crack detection NG issue is essentially caused by cracks in the IC bonding process.

[0060] For foldable LTPO display panels, crack detection failures caused by the bonding process continue to occur, with visible cracks visible under a microscope. The NG rate fluctuates between batches by approximately 3%-7%. Failures in crack detection caused by the IC bonding process pose two risks for OLED screens: ① If the panel crack detection fails, cracks in other locations around the display panel will not be detected; ② Since the failure of the panel crack detection essentially indicates the presence of cracks in the display panel, there is a risk of further spread and deterioration over time or due to reliability issues, thereby affecting normal screen display. In other words, cracks in the display panel may cause related defects caused by crack induction, which are not limited to NG results in the panel crack detection.

[0061] Figure 1 is a partial schematic diagram of a display panel. Figure 2 is a schematic diagram of a crack in the display panel shown in Figure 1. Figure 3 is a schematic diagram of a wiring area of ​​a display panel.

[0062] As shown in Figures 1 and 3, the display panel includes multiple input bumps BP2 and multiple dummy bumps BP3. Figure 1 shows multiple traces L0. Figure 3 shows multiple output bumps BP1. The black rectangular box B1 in Figure 3 represents the outer boundary of the IC.

[0063] As shown in Figures 1 and 3, a spacer G0 is provided between the input bumps BP2 and the dummy bumps BP3. As shown in Figure 3, a spacer Gm is provided between the output bumps BP1 and the dummy bumps BP3. The minimum spacing M0 between the output bumps BP1 and the dummy bumps BP3 is small.

[0064] As shown in Figure 3, the gap region G0 is relatively large, while the gap region Gm is relatively small. For example, the minimum spacing D0 between the multiple input bumps BP2 and the multiple dummy bumps BP3 is relatively large. As a result, during the IC bonding process, cracks CK are generated in the inorganic insulating layer ISL0 at the gap region G0 (as shown in Figure 2).

[0065] For example, as shown in FIG. 3 , in some embodiments, the minimum pitch M0 is 82 μm, and the minimum pitch D0 is 104 μm, but the present invention is not limited thereto.

[0066] In the embodiment of the present disclosure, the output bump BP1 , the input bump BP2 , and the dummy bump BP3 may also be referred to as bumps.

[0067] As shown in FIG. 1 to FIG. 3 , the display panel may further include a crack detection line PCD. The crack CK generated in the inorganic insulating layer ISL0 may break the crack detection line PCD on the inorganic insulating layer ISL0 , thereby causing the panel to fail crack detection.

[0068] As shown in FIG. 1 , the display panel may further include a source test line ST. The source test line ST is located between the crack detection line PCD and the plurality of dummy bumps BP3 .

[0069] Of course, the defects caused by the cracks CK generated in the inorganic insulating layer ISL0 are not limited to failure of the panel crack detection, and may also cause other defects, such as disconnection of other wires and thus corresponding defects.

[0070] As shown in FIG2 , the display panel includes a trace L1. The trace L1 and the crack detection line PCD may be located on the same inorganic insulating layer. For example, the trace L1 and the crack detection line PCD may be located on the same layer, but this is not limited to this. For example, the trace L1 and the crack detection line PCD may be located on the first conductive layer LY1, but this is not limited to this. In other embodiments, the trace L1 and the crack detection line PCD may also be located on different layers.

[0071] To effectively improve defects caused by cracks in the inorganic insulating layer during the IC bonding process, the display panel provided by the embodiments of the present disclosure can be optimized in the following aspects: starting with the area where the cracks occur, auxiliary protrusions are added (which can be considered as increasing the number of dummy protrusions) to balance the stress during bonding pressure; at the same time, the notch area of ​​the spacer G0 is reduced, thereby reducing the deformation of the display panel and achieving the effect of alleviating or eliminating cracks caused by the bonding process.

[0072] FIG4 is a schematic diagram of a display panel (before IC binding) provided in an embodiment of the present disclosure. FIG5 is a schematic diagram of a display panel (after IC binding) provided in an embodiment of the present disclosure. FIG6 is a schematic diagram of a wiring area of ​​a display panel provided in an embodiment of the present disclosure. FIG7A is a schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure. FIG8A is a schematic diagram of a wiring area of ​​another display panel provided in an embodiment of the present disclosure.

[0073] As shown in Figures 4 and 5 , embodiments of the present disclosure provide a display panel comprising a display area 100 and a wiring area 200. The display area 100 includes a plurality of sub-pixels SP. The wiring area 200 is located to one side of the plurality of sub-pixels SP, that is, the wiring area 200 is located to one side of the display area 100. Figures 4 and 5 illustrate an example in which the wiring area 200 is located to the left of the display area 100.

[0074] As shown in Figures 4 and 5, the display panel further includes a peripheral region 300, which surrounds the display region 100. The embodiments of the present disclosure use an example in which the peripheral region 300 surrounds the display region 100, but the present invention is not limited thereto. The peripheral region 300 may be located on at least one side of the display region 100. For example, the peripheral region 300 may be located on at least one of the left side, right side, top side, and bottom side of the display region 100.

[0075] 4 and 5 , the peripheral region 300 includes the wiring region 200. As shown in FIG4 and 5 , the wiring region 200 is a portion of the peripheral region 300.

[0076] For example, as shown in FIG. 5 , the crack detection line PCD is located in the peripheral region 300 , and the crack detection line PCD passes through the second spacing region G2 .

[0077] As shown in Figures 4 and 5 , the wiring area 200 is located in the peripheral area 300. For clarity of illustration, Figures 4 and 5 do not show all structures and wirings of the display panel.

[0078] 4 and 5 also show data lines DL. The data lines DL are configured to provide data signals, such as data voltages, to the sub-pixels SP. The number of data lines DL is not limited to that shown in FIG. 4 and 5 and can be determined as needed.

[0079] It should be noted that the number of sub-pixels in the display panel is not limited to those shown in FIG. 4 and FIG. 5 , and the wiring and structure in the display panel are not limited to those shown in FIG. 4 and FIG. 5 , and can be determined according to needs.

[0080] Figure 5 shows integrated circuit 88 and flexible printed circuit board 99. For example, integrated circuit 88 and flexible printed circuit board 99 can be separately bonded to the display panel. For example, integrated circuit 88 can be bonded to conductive structures on the display panel, such as various protrusions. For example, flexible printed circuit board 99 can be bonded to conductive structures on the display panel, such as various protrusions. The protrusions on the display panel bonded to flexible printed circuit board 99 can be connected to the protrusions on the display panel bonded to integrated circuit 8.

[0081] As shown in Figures 4 and 5, the crack detection line PCD surrounds the display area 100. The two ends of the crack detection line PCD are connected to the input bumps, and then to the connection structure 701 and the connection structure 702, respectively. As shown in Figure 5, the connection structure 701 and the connection structure 702 can be connected to the conductive structure on the flexible circuit board 99.

[0082] The resistance can be used to determine whether the crack detection line PCD is broken. If the crack detection line PCD is not broken, its resistance is the normal value of the trace resistance. If the crack detection line PCD is broken, its resistance will be very large.

[0083] As shown in Figures 4 and 5 , one end of a source test line ST is connected to a data line DL via an output bump BP1, and the other end of the source test line ST is connected to a connection structure. Figures 4 and 5 show two source test lines ST, which are connected to connection structures 721 and 722, respectively. Connection structures 721 and 722 can each be connected to a conductive structure on the flexible printed circuit board 99.

[0084] The source test line ST is primarily used to test the function of the data line DL connected to it. For example, the waveform on the data line DL connected to it can be tested through the source test line ST. If the display panel displays abnormally, a source test can be performed to determine whether the abnormality is caused by a problem with the data line DL.

[0085] Figures 4 and 5 do not show the conductive structures on the flexible circuit board 99. The conductive structures on the flexible circuit board 99 can be considered to correspond to the connection structures on the display panel. For example, the conductive structures on the flexible circuit board 99 correspond in position and have similar dimensions to the connection structures on the display panel, but this is not the only limitation.

[0086] For example, as shown in Figures 6 to 8B , the display panel further includes a source test line ST. The source test line ST is located in the peripheral region 300 and on one side of the crack detection line PCD. The source test line ST passes through the second spacer region G2. The source test line ST is configured to test the data line DL. For example, the source test line ST is connected to one of the plurality of data lines DL. The crack detection line PCD is configured to detect cracks in the display panel.

[0087] The embodiment of the present disclosure takes the display panel including the source test line ST and the crack detection line PCD as an example, but is certainly not limited thereto. The embodiment of the present disclosure may also exclude at least one of the source test line ST and the crack detection line PCD.

[0088] As shown in FIG. 4 to FIG. 8B , the wiring region 200 includes an input region 202 , an output region 201 , and a dummy region 203 . The dummy region 203 is located between the input region 202 and the output region 201 .

[0089] As shown in Figures 4 to 8B, the input region 202 has a plurality of input bumps BP2, the output region 201 has a plurality of output bumps BP1, and the dummy region 203 has a plurality of dummy bumps BP3. In the embodiment of the present disclosure, the output region 201, the input region 202, and the dummy region 203 can be divided based on the line connecting the outermost edges of the bumps located therein.

[0090] As shown in Figures 6 to 8B , a first spacer G1 is provided between the plurality of output bumps BP1 and the plurality of dummy bumps BP3, and a second spacer G2 is provided between the plurality of input bumps BP2 and the plurality of dummy bumps BP3. A stress-balancing structure 66 is provided in the second spacer G2. The stress-balancing structure 66 is configured to balance stress during the integrated circuit bonding process. This can mitigate or prevent cracks in the inorganic insulating layer during the integrated circuit bonding process, thereby preventing defects caused by cracks in the inorganic insulating layer. For example, cracks in the inorganic insulating layer can prevent the panel crack detection line from breaking, thereby preventing panel crack detection failures.

[0091] For example, the inorganic insulating layer includes at least a portion located in the second spacer G2 , and the stress equalization structure 66 is configured to equalize the stress of the portion of the inorganic insulating layer located in the second spacer G2 during the integrated circuit bonding process.

[0092] For example, as shown in FIG6 , in the display panel provided in an embodiment of the present disclosure, the stress equalization structure 66 includes an auxiliary protrusion ABP, and the auxiliary protrusion ABP includes an auxiliary protrusion BP4. The auxiliary protrusion BP4 is located on the side of the multiple dummy protrusions BP3 close to the input area 202 to reduce the size of the second spacer area G2. FIG6 shows one auxiliary protrusion BP4, but the number of auxiliary protrusions BP4 is not limited to that shown in the figure and can be determined as needed. The provision of the auxiliary protrusion BP4 reduces the size of the gap at the second spacer area G2, making the force in this area more uniform. The smaller the deformation of the portion of the inorganic insulating layer located between the protrusions, the less likely cracks will occur. Theoretically, the smaller the size of the gap, the better. In the extreme case, the size of the gap is similar to the spacing between adjacent protrusions. The spacing between adjacent protrusions can be the spacing between adjacent dummy protrusions or the spacing between adjacent dummy protrusions and auxiliary protrusions.

[0093] For example, as shown in FIG6 , in the display panel provided by the embodiment of the present disclosure, the minimum spacing between the auxiliary protrusion BP4 and the plurality of input protrusions BP2 is a spacing N1. The closer the spacing N1 is to the minimum dimension D1, or, if the process allows, the smaller the spacing N1 is, the more conducive it is to reducing or removing cracks in the inorganic insulating layer in the second spacer region.

[0094] For example, the spacing N1 and the minimum dimension D1 may be equal or similar.

[0095] For example, a ratio R1 of the absolute value of the difference between the spacing N1 and the minimum dimension D1 of the first spacer G1 to the minimum dimension D1 is greater than or equal to 0 and less than or equal to 10%. For another example, the ratio R1 is greater than or equal to 0 and less than or equal to 5%. For another example, the ratio R1 is greater than or equal to 0 and less than or equal to 3%.

[0096] For example, the pitch N1 is equal to the minimum dimension D1 of the first spacer G1 . In this case, the ratio of the absolute value of the difference between the pitch N1 and the minimum dimension D1 of the first spacer G1 to the minimum dimension D1 is equal to 0.

[0097] For example, as shown in FIG6 , the pitch N1 is 82 μm and the minimum dimension D1 is 82 μm, but the present invention is not limited thereto. For example, in this case, referring to FIG3 and FIG6 , the minimum pitch between adjacent dummy bumps BP3 and input bumps BP2 is 104 μm. That is, at the lower left of the display panel, the pitch between bumps can be reduced from 104 μm to 82 μm.

[0098] For example, the pitch N1 is 80 μm and the minimum dimension D1 is 82 μm. In this case, the ratio R1 is 2.4%.

[0099] For example, the pitch N1 is 78 μm and the minimum dimension D1 is 82 μm. In this case, the ratio R1 is 4.8%.

[0100] For example, as shown in FIG6 , one or more auxiliary bumps ABP are arranged at equal sizes and spacings on one side of the dummy bump BP3 near the input region 202 to reduce the size of the gap at the second spacer region G2. This allows for more uniform force application in this region during the IC bonding process, reduces deformation of the inorganic insulating layer between the bumps, mitigates or prevents cracks in the inorganic insulating layer, and thereby avoids defects caused by cracks. Of course, the one or more auxiliary bumps ABP may not be arranged at equal sizes and spacings.

[0101] For example, the spacing N2 is smaller than the minimum dimension of the second spacer G2. For example, the ratio Ra of the spacing N1 to the minimum dimension of the second spacer G2 is greater than or equal to 60% and less than or equal to 85%. For another example, the ratio Ra is greater than or equal to 70% and less than or equal to 80%. For another example, the ratio Ra is approximately 77%.

[0102] In the embodiment of the present disclosure, the minimum dimension of the second spacing region G2 is the distance between adjacent input bumps BP2 and output bumps BP1 , which can be seen as the minimum distance D0 marked in FIG. 3 .

[0103] For example, as shown in FIG7A , in the display panel provided in an embodiment of the present disclosure, the stress-balancing structure 66 includes auxiliary protrusions ABP, which include auxiliary protrusions BP5. The auxiliary protrusions BP5 are located on a side of the plurality of input protrusions BP2 that is close to the dummy region 203. The provision of the auxiliary protrusions BP5 can reduce the size of the gap at the second spacer region G2 to balance stress, eliminate or reduce cracks in the inorganic insulating layer at this location, and alleviate or eliminate related defects. For details, please refer to the previous description and will not be repeated here.

[0104] For example, as shown in FIG7A , in the display panel provided by an embodiment of the present disclosure, the minimum spacing between the auxiliary protrusion BP5 and the plurality of dummy protrusions BP3 is a spacing N2. Alternatively, the minimum spacing between an auxiliary protrusion BP5 and its adjacent dummy protrusion BP3 is a spacing N2. The closer the spacing N2 is to the minimum dimension D1, or, if the process allows, the smaller the spacing N2 is, the more conducive it is to reducing or eliminating cracks in the inorganic insulating layer within the second spacer region.

[0105] For example, the spacing N2 and the minimum dimension D1 may be equal or similar.

[0106] For example, a ratio R2 of the absolute value of the difference between the spacing N2 and the minimum dimension D1 of the first spacer G1 to the minimum dimension D1 is greater than or equal to 0 and less than or equal to 10%. For another example, the ratio R2 is greater than or equal to 0 and less than or equal to 5%. For another example, the ratio R2 is greater than or equal to 0 and less than or equal to 3%.

[0107] For example, the interval N2 is equal to the minimum dimension D1 of the first spacer G1 . In this case, the ratio R2 is equal to 0.

[0108] For example, an absolute value of a difference between the interval N2 and the minimum dimension D1 of the first spacer G1 is greater than or equal to 0 and less than or equal to 2 μm.

[0109] For example, as shown in FIG7A , the pitch N2 is 84 μm and the minimum dimension D1 is 82 μm. In this case, the ratio R2 is 2.4%. In this case, referring to FIG3 and FIG7A , the minimum pitch between adjacent dummy bumps BP3 and input bumps BP2 is 104 μm. That is, at the lower left of the display panel, the pitch between bumps can be reduced from 104 μm to 84 μm.

[0110] For example, the pitch N2 is 80 μm and the minimum dimension D1 is 82 μm. In this case, the ratio R2 is equal to 2.4%.

[0111] For example, the spacing N2 is less than the minimum dimension of the second spacer G2. For example, a ratio Rb of the spacing N2 to the minimum dimension of the second spacer G2 is greater than 60% and less than or equal to 85%. For another example, the ratio Rb is greater than or equal to 70% and less than or equal to 85%. For another example, the ratio Rb is approximately 81%.

[0112] For example, as shown in FIG8A , in the display panel provided in an embodiment of the present disclosure, the stress-balancing structure 66 includes auxiliary protrusions ABP, which include auxiliary protrusions BP4 and BP5. Auxiliary protrusion BP4 is located on a side of the plurality of dummy protrusions BP3 that is close to the input region 202, and auxiliary protrusion BP5 is located on a side of the plurality of input protrusions BP2 that is close to the dummy region 203. The provision of auxiliary protrusions BP4 and BP5 can reduce the size of the gap at the second spacer region G2, thereby balancing stress and eliminating or reducing cracks in the inorganic insulating layer therein, thereby alleviating or eliminating related defects. For details, please refer to the previous description and will not be repeated here.

[0113] For example, as shown in FIG8A , in the display panel provided by the embodiment of the present disclosure, the minimum distance between the auxiliary protrusion BP4 and the auxiliary protrusion BP5 is a distance N3 , and the minimum size D1 of the first spacer G1 is greater than the distance N3 .

[0114] For example, in the display panel provided by the embodiment of the present disclosure, the minimum size D1 of the first spacer G1 is greater than 1.5 times the interval N3.

[0115] For example, in the display panel provided by the embodiment of the present disclosure, the minimum size D1 of the first spacing region G1 is greater than twice the interval N3.

[0116] For example, if the pitch N3 is 40 μm and the minimum dimension D1 is 82 μm, the minimum dimension D1 of the first spacer G1 is greater than twice the pitch N3. In this case, referring to Figures 3 and 8A , the minimum spacing between adjacent dummy bumps BP3 and input bumps BP2 is 104 μm. That is, at the lower left of the display panel, the spacing between bumps can be reduced from 104 μm to 40 μm.

[0117] For example, in the display panel provided by the embodiment of the present disclosure, the minimum size of the second spacing region G2 is greater than twice the interval N3.

[0118] For example, in the display panel provided by the embodiment of the present disclosure, the minimum size of the second spacing region G2 is greater than 2.5 times the interval N3.

[0119] For example, the spacing N2 is smaller than the minimum dimension of the second spacer G2. For example, the ratio Rc of the spacing N3 to the minimum dimension of the second spacer G2 is greater than 20% and less than or equal to 50%. For another example, the ratio Rc is greater than or equal to 30% and less than or equal to 40%. For another example, the ratio Rc is approximately 39%.

[0120] As shown in Figures 7B and 8B, the display panel also includes an alignment mark MK2, which is located between the auxiliary protrusion BP5 and multiple input protrusions BP2. The spacing M1 between the auxiliary protrusion BP5 and the adjacent input protrusion BP2 is greater than the spacing M2 between two adjacent input protrusions BP2. Because the input protrusion BP2 can be formed by stacking multiple film layers, the alignment mark MK2 is used to align the different stacked layers. The alignment mark MK2 can be formed using the film layer closest to the base substrate of the input protrusion BP2, such as the first conductive layer LY1, but is not limited thereto.

[0121] As shown in Figures 7B and 8B, the display panel also includes an alignment mark MK1 located on one side of the plurality of output bumps BP1. Because the output bumps BP1 can be formed by stacking multiple film layers, the alignment mark MK1 is used to facilitate alignment during the formation of the different stacked layers. The alignment mark MK1 can be formed in the film layer closest to the base substrate of the output bumps BP1, such as the first conductive layer LY1, but is not limited thereto.

[0122] In the case where the stacked structures of the output protrusion BP1 and the input protrusion BP2 are the same, the alignment mark MK1 and the alignment mark MK2 may be used for joint alignment.

[0123] 6 to 8B roughly illustrate the second spacing area G2 with a dotted line frame. Of course, the actual second spacing area G2 is not limited to a rectangle.

[0124] The display panels shown in FIG. 7B and FIG. 8B are provided with an alignment mark MK2 . The relevant dimensions of the second spacer G2 may refer to the display panels shown in FIG. 7B and FIG. 8B which are not provided with the alignment mark MK2 , and will not be described in detail here.

[0125] In other embodiments, an alignment mark MK1 and an alignment mark MK2 may also be provided to serve as alignment marks. For example, the alignment mark MK1 is provided on one side of the plurality of output protrusions BP1, and the alignment mark MK2 is provided on one side of the plurality of input protrusions BP2. Figures 7B and 8B are both described using the example that the alignment mark MK1 is provided on the left side of the plurality of output protrusions BP1, and the alignment mark MK2 is provided on the left side of the plurality of input protrusions BP2. In other embodiments, the alignment mark MK1 may also be provided on the right side of the plurality of output protrusions BP1, or the alignment mark MK1 may be provided on both the left and right sides of the plurality of output protrusions BP1. In other embodiments, the alignment mark MK2 is provided on the right side of the plurality of input protrusions BP2, or the alignment mark MK2 may be provided on both the left and right sides of the plurality of input protrusions BP2.

[0126] 6 to 8B show three dummy bumps BP3 , but the number of the dummy bumps BP3 is not limited to that shown in the figures and can be determined as needed.

[0127] Figures 6 to 8B illustrate a base substrate BS. Multiple output bumps BP1, multiple input bumps BP2, multiple dummy bumps BP3, and a stress equalization structure 66 are all disposed on base substrate BS. Integrated circuit 88 is bonded to base substrate BS through a bonding process. Integrated circuit 88 includes conductive structures bonded to the bumps within wiring region 200. The form of the conductive structures on integrated circuit 88 can be similar to the form of the bumps within wiring region 200. For example, the arrangement of the conductive structures on integrated circuit 88 may be similar to, but not limited to, the arrangement of the bumps within wiring region 200.

[0128] The drawings of some embodiments of the present disclosure illustrate at least one of direction X, direction Y, or direction Z. Both direction X and direction Y are parallel to the main surface of the substrate BS, and direction X and direction Y intersect. For example, the embodiments of the present disclosure use direction X as an example, where direction X is perpendicular to direction Z. For example, the main surface of the substrate BS is the surface used to manufacture various components.

[0129] The display panels shown in Figures 6 to 8B are provided with auxiliary protrusions, that is, the number and density of the dummy patterns are increased, the binding pressure is balanced, and the area of ​​the gap in the second spacer is reduced, thereby reducing the deformation of the display panel and achieving the effect of eliminating or reducing the binding cracks.

[0130] To effectively improve defects caused by cracks in the inorganic insulating layer during the IC bonding process, the display panel provided by the embodiments of the present disclosure can be optimized in the following aspects: starting with the pattern density in the cracked area, adding dummy patterns to balance the stress and deformation during bonding. The dummy patterns are auxiliary blocks.

[0131] Figure 9 is a partial view of a display panel provided in an embodiment of the present disclosure. Figure 10 is a partial view of another display panel provided in an embodiment of the present disclosure. Figure 11 is a partial view of another display panel provided in an embodiment of the present disclosure.

[0132] Figure 9 shows the first spacer G1 and the second spacer G2 in dotted lines. As shown in Figure 9, the minimum size of the first spacer G1 is smaller than the minimum size of the second spacer G2.

[0133] For example, as shown in FIG. 9 , in the display panel provided by the embodiment of the present disclosure, the stress equalization structure 66 includes a plurality of auxiliary wirings AL, and the plurality of auxiliary wirings AL pass through the second spacing region G2 .

[0134] The display panel provided by the embodiments of the present disclosure can prevent or mitigate cracks in the inorganic insulating layer within the second gap region G2 during the integrated circuit bonding process by disposing multiple auxiliary wirings AL within the second gap region G2, thereby avoiding various defects caused by cracks. The multiple auxiliary wirings AL serve to balance stress.

[0135] For example, as shown in FIG9 and FIG10, in the display panel provided by the embodiment of the present disclosure, the first spacing area G1 includes multiple signal connection lines WL, and the wiring density of the multiple auxiliary wirings AL is greater than or equal to the wiring density of the multiple signal connection lines WL.

[0136] For example, as shown in Figure 9, the signal connection line WL may be a gate driver on array (GOA) signal line. That is, the signal connection line WL is used to transmit signals and is not a floating line.

[0137] As shown in FIG9 , the plurality of signal connection lines WL includes two signal connection lines WL, and the plurality of auxiliary wiring lines AL includes four auxiliary wiring lines AL. Of course, the number of the plurality of signal connection lines WL is not limited to that shown in FIG9 , and the number of the plurality of auxiliary wiring lines AL is not limited to that shown in FIG9 . Of course, the number of the plurality of auxiliary wiring lines AL is also not limited to that shown in FIG10 .

[0138] For example, as shown in FIG. 9 , in the display panel provided by the embodiment of the present disclosure, near the dummy area 203 , the directions of the plurality of signal connection lines WL are symmetrical to the directions of the plurality of auxiliary wirings AL.

[0139] As shown in FIG9 , near the dummy area 203 , each of the plurality of signal connection traces WL runs along a direction X. As shown in FIG9 , each of the plurality of auxiliary wiring lines AL runs along a direction X. Near the dummy area 203 , the directions of the plurality of signal connection traces WL are symmetrical to the directions of the plurality of auxiliary wiring lines AL.

[0140] As shown in FIG9 , at a location relatively far from the dummy area 203, each of the plurality of signal connection traces WL runs toward the lower right, and as shown in FIG9 , each of the plurality of auxiliary traces AL runs toward the upper right. At a location relatively far from the dummy area 203, the directions of the plurality of signal connection traces WL and the plurality of auxiliary traces AL can be considered symmetrical. In the embodiments of the present disclosure, the plurality of signal connection traces WL and the plurality of auxiliary traces AL do not need to be arranged completely symmetrically.

[0141] For example, as shown in FIG9 , in the display panel provided in the embodiment of the present disclosure, a plurality of dummy protrusions BP3 are arranged in a row along direction Y and are axisymmetric along direction X. Near the dummy area 203 , the directions of a plurality of signal connection lines WL and the directions of at least part of the auxiliary wiring AL are axisymmetric along direction X.

[0142] For example, as shown in FIG9 , in a display panel provided by an embodiment of the present disclosure, a plurality of dummy bumps BP3 are arranged in a row. Near the dummy region 203 , the orientations of the plurality of signal connection traces WL and the orientations of the plurality of auxiliary wirings AL are symmetrical about an axis AX perpendicular to the orientation of the plurality of dummy bumps BP3. As shown in FIG9 , the axis AX extends along the direction X.

[0143] FIG9 also shows a source test line ST and a panel crack detection line PCD. The source test line ST and the panel crack detection line PCD do not belong to the auxiliary wiring AL. For example, in a display panel, a source test line ST and a panel crack detection line PCD are usually provided in the second spacing area G2. For example, more than or equal to one auxiliary wiring AL may be provided to facilitate the stress balance of the inorganic insulating layer during the integrated circuit binding process. FIG9 takes the provision of two auxiliary wirings AL as an example. The number of auxiliary wirings AL is not limited to that shown in the figure and may be provided as needed. For example, the auxiliary wiring AL may be a dummy line. The auxiliary wiring AL may be floating and not connected to any signal.

[0144] For example, as shown in FIG9 , the source test line ST and the panel crack detection line PCD overlap with the auxiliary wiring AL other than these two lines. For example, the source test line ST and the panel crack detection line PCD and the auxiliary wiring AL other than these two lines can be located on different layers. For example, the source test line ST and the panel crack detection line PCD are located on a first conductive layer, while the auxiliary wiring AL other than these two lines are located on a second conductive layer, but this is not limited to this.

[0145] For example, as shown in Figure 10, in the display panel provided by the embodiment of the present disclosure, the plurality of auxiliary wirings AL include bending lines BL. The provision of the bending lines BL can help prevent cracks from expanding and extending into the interior of the display panel.

[0146] For example, as shown in FIG10 , in the display panel provided in the embodiment of the present disclosure, the bending line BL has a first portion PT1, a second portion PT2, and a third portion PT3. The second portion PT2 is located between the first portion PT1 and the third portion PT3. The angle A1 between the second portion PT2 and the first portion PT1 is an obtuse angle, and the angle A2 between the second portion PT2 and the third portion PT3 is an obtuse angle. The second portion PT2 can serve as a crack barrier. As shown in FIG10 , the angle between the second portion PT2 and the direction X is an obtuse angle, and the angle between the second portion PT2 and the direction Y is an acute angle. Direction Y can be regarded as a direction from the output area to the input area. The output area is not shown in FIG10 , and reference may be made to other figures. As shown in FIG10 , the direction of the second portion PT2 is from the dummy area 203 to the input area 202.

[0147] As shown in FIG10 , the extension direction of the second portion PT2 may be perpendicular to the crack propagation direction DR to better prevent crack propagation. The crack propagation direction DR may refer to the direction in which the crack extends. The crack propagation direction DR may intersect with the direction from the dummy region 203 to the input region 202. For example, the angle between the crack propagation direction DR and the direction from the dummy region 203 to the input region 202 may be less than or equal to 30°, but is not limited thereto. The direction from the dummy region 203 to the input region 202 may refer to the direction from the center of the dummy region 203 to the center of the input region 202. For example, the angle between the extension direction of the second portion PT2 and the arrangement direction (direction X) of the plurality of input bumps BP2 may be an acute angle, while the angle between the extension direction of the second portion PT2 and the arrangement direction (direction Y) of the plurality of dummy bumps BP3 may be an obtuse angle. For example, the sum of the acute and obtuse angles may be 180°, but is not limited thereto.

[0148] For example, as shown in FIG10 , in a display panel provided by an embodiment of the present disclosure, the plurality of auxiliary wirings AL include a disconnection line KL, which is disconnected at a second portion PT2 into two portions located on either side of the second portion PT2. FIG10 shows that the disconnection line KL is disconnected at the second portion PT2 into a first portion KL1 and a second portion KL2 located on either side of the second portion PT2.

[0149] For example, as shown in FIG. 10 , the bending line BL is located between the crack detection line PCD and the plurality of input protrusions 202 .

[0150] For example, the source test line ST and the bending line BL are respectively arranged on both sides of the crack detection line PCD. As shown in FIG10 , the source test line ST and the bending line BL are respectively arranged on the upper side and the lower side of the crack detection line PCD.

[0151] For example, as shown in Fig. 10 , the plurality of bending lines BL are all provided on the same side of the crack detection line PCD. The plurality of bending lines BL are all provided on the side of the crack detection line PCD opposite to the side on which the source test line ST is provided.

[0152] The auxiliary wiring AL may be a stacked structure of at least one of the output bump BP2, the dummy bump BP3, and the input bump BP1. Of course, the auxiliary wiring AL may also be made of the first conductive layer LY1.

[0153] For example, as shown in FIG11 , in a display panel provided by an embodiment of the present disclosure, the stress equalization structure 66 includes a plurality of auxiliary blocks AK disposed in the second spacer region G2 to mitigate or avoid defects caused by cracks in the portion of the inorganic insulating layer located in the second spacer region G2.

[0154] For example, as shown in Figure 11, in the display panel provided by the embodiment of the present disclosure, a plurality of auxiliary blocks AK are arranged in an array. The plurality of auxiliary blocks AK arranged in an array is conducive to balancing stress during the bonding process of the integrated circuit.

[0155] For example, as shown in FIG11 , the area of ​​at least some auxiliary blocks AK is smaller than the area of ​​the input bump BP2 and smaller than the area of ​​the dummy bump BP3. For example, as shown in FIG11 , in the display panel provided in an embodiment of the present disclosure, the area of ​​each of the plurality of auxiliary blocks AK is smaller than the area of ​​each of the plurality of input bumps BP2 and smaller than the area of ​​each of the plurality of dummy bumps BP3. In FIG11 , due to the cutout position, the two rightmost auxiliary blocks AK are not shown in their entirety; in reality, the areas of the respective auxiliary blocks AK are the same or substantially the same. The rightmost input bump BP1 is not shown in its entirety; in reality, the areas of the respective input bumps BP1 are the same or substantially the same. The topmost dummy bump BP3 is not shown in its entirety; in reality, the areas of the respective dummy bumps BP3 are the same or substantially the same.

[0156] 11 illustrates an example in which the auxiliary block AK is rectangular, the dummy bump BP3 is stripe-shaped, and the input bump BP1 is stripe-shaped. However, the shapes of the auxiliary block AK, the dummy bump BP3, and the input bump BP1 are not limited to those shown in the figure.

[0157] In the embodiment of the present disclosure, the shapes of various components such as the output bump BP2 , the dummy bump BP3 , the input bump BP1 , and the auxiliary block AK can be determined as needed.

[0158] For example, the auxiliary block AK may be located in the first conductive layer. Alternatively, the auxiliary block AK may be formed by stacking multiple conductive layers to further optimize stress. For example, the auxiliary block AK may have a stacked structure of at least one of the output bump BP2, the dummy bump BP3, and the input bump BP1. Alternatively, the auxiliary block AK may be formed using the first conductive layer LY1.

[0159] For example, in an embodiment of the present disclosure, the auxiliary block AK may be a dummy block, that is, the auxiliary block AK is floating and is not connected to any signal.

[0160] Figures 9 to 11 also show trace L3, which can be a signal line. For example, trace L3 can be a gate driver on array (GOA) signal line. That is, trace L3 is used to transmit signals and is not a floating trace.

[0161] Figure 12 is a schematic diagram of a display panel (after IC bonding) provided in accordance with an embodiment of the present disclosure. Figure 13 is a schematic diagram of a sub-pixel of a display panel provided in accordance with an embodiment of the present disclosure.

[0162] As shown in FIG12 , the display panel includes a sub-pixel 60, which is located on a base substrate BS. As shown in FIG13 , the sub-pixel 60 includes a pixel circuit 601 and a light-emitting element 602, and the pixel circuit 601 is configured to drive the light-emitting element 602. For example, the pixel circuit 601 is configured to provide a driving current to drive the light-emitting element 602 to emit light. For example, the light-emitting element 602 is an organic light-emitting diode (OLED), but is not limited thereto. The light-emitting element 602 emits red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit 601. The color of the light emitted by the light-emitting element 602 can be determined as needed.

[0163] 12 and 13 , the display panel further includes a data line DL configured to provide a data voltage Vdt to the sub-pixel SP, and the plurality of output bumps BP1 include an output bump BP1 connected to the data line DL.

[0164] For example, as shown in Figures 12 and 13, the display panel further includes a data line DL, a first power supply voltage line PL1, and a second power supply voltage line PL2. The data line DL is configured to provide a data voltage Vdt to the sub-pixel SP, the first power supply voltage line PL1 is configured to provide a first power supply voltage VDD to the sub-pixel SP, and the second power supply voltage line PL2 is configured to provide a second power supply voltage VSS to the sub-pixel SP. The plurality of output bumps BP1 include output bumps BP1 connected to the data line DL, the first power supply voltage line PL1, and the second power supply voltage line PL2, respectively. For example, the first power supply voltage VDD is greater than the second power supply voltage VSS.

[0165] 13 also shows a gate line GL. The gate line GL is configured to provide a scan signal to the sub-pixel SP.

[0166] Figure 13 also shows that the light-emitting element 602 includes a first electrode E1 and a second electrode E2. As shown in Figure 13, the first electrode E1 is connected to the pixel circuit 601, and the second electrode E2 is connected to the second power supply voltage line PL2. For example, one of the first electrode E1 and the second electrode E2 is an anode, and the other of the first electrode E1 and the second electrode E2 is a cathode.

[0167] For example, the pixel circuit 601 includes a transistor and a capacitor. For example, the pixel circuit 601 includes a driving transistor and a data writing transistor.

[0168] For example, one of the source and drain of the data write transistor in the pixel circuit 601 is connected to the data line DL, and the other of the source and drain of the data write transistor in the pixel circuit 601 is connected to the drive transistor. The gate line GL is connected to the gate of the data write transistor.

[0169] In some embodiments, the pixel circuit 601 includes a driving transistor, a data writing transistor, a light emitting control transistor, a threshold compensation transistor, a reset control transistor, and a storage capacitor. The structure of the pixel circuit 601 is not limited to the above description and can be determined according to needs.

[0170] Figure 14A is a schematic diagram of a display panel formed with an anisotropic adhesive layer formed on a base substrate with protrusions formed thereon and before a bonding process is performed. Figure 14B is a schematic diagram of a display panel formed after a bonding process.

[0171] As shown in FIG14A , an anisotropic adhesive layer AHL is formed on the base substrate on which the protrusions and the plurality of sub-pixels are formed.

[0172] FIG14B shows a base substrate BS and a conductive structure 105 located on the base substrate BS. FIG14B also shows an inorganic insulating layer ISL located on the base substrate BS. For example, the inorganic insulating layer ISL includes at least one of a gate insulating layer GI1, a gate insulating layer GI2, and an interlayer insulating layer ILD. For example, the material of the inorganic insulating layer ISL includes an inorganic insulating material. For example, the inorganic insulating material includes at least one of SiOx, SiNy, and SiOxNy.

[0173] For example, as shown in FIG14B , the display panel further includes an integrated circuit 88, which includes a substrate SS and a plurality of conductive structures 106 located thereon. The plurality of conductive structures 106 may correspond one-to-one to the plurality of conductive structures 105 on the substrate BS, but is not limited thereto. The auxiliary protrusions ABP in the display panel provided in the embodiment of the present disclosure may also not correspond to the conductive structures 106 in the integrated circuit 88. That is, in the integrated circuit 88, no conductive structure 106 corresponding to the auxiliary protrusions ABP is provided. In other words, the orthographic projections of the plurality of conductive structures 105 of the display panel on the substrate BS do not overlap with the orthographic projections of the plurality of conductive structures 106 in the integrated circuit 88 on the substrate BS.

[0174] As shown in FIG14B , an integrated circuit is placed on a substrate BS and, through a bonding process, forces are applied to connect the multiple conductive structures 106 on the integrated circuit 88 to the multiple conductive structures 105 on the display panel via anisotropic adhesive AH. For example, the multiple conductive structures 105 include, but are not limited to, multiple input bumps BP2, multiple output bumps BP1, and multiple dummy bumps BP3. For example, the multiple conductive structures 105 may also include at least one auxiliary bump ABP.

[0175] Figures 6 to 8B illustrate integrated circuit 88 with substrate SS. Conductive structure 106 in integrated circuit 88 is not shown in Figures 6 to 8B. The various bumps shown in Figures 6 to 8B, such as output bump BP1, input bump BP2, dummy bump BP3, and auxiliary bump ABP, are all structures disposed on substrate BS.

[0176] For example, the base substrate BS of the display panel includes a flexible base substrate, but is not limited thereto. For example, the flexible base substrate includes polyimide, but is not limited thereto, and other suitable flexible base materials may also be used.

[0177] As shown in Figure 14B, the anisotropic adhesive AH includes a conductive portion AH1 and a non-conductive portion AH2. The conductive structure 106 is connected to the conductive structure 105 via the conductive portion AH1 of the anisotropic adhesive AH.

[0178] For example, as shown in FIG14B , conductive structure 105 includes conductive element 101, conductive element 102, and conductive element 103. For example, conductive element 101 is located in first conductive layer LY1, conductive element 102 is located in second conductive layer LY2, and conductive element 103 is located in third conductive layer LY3. For example, at least one of conductive element 101, conductive element 102, and conductive element 103 includes a stacked structure formed by multiple sublayers. For example, conductive element 101, conductive element 102, and conductive element 103 may be made of, but are not limited to, metal.

[0179] 14A and 14B , the first conductive layer LY1 is closer to the base substrate BS than the second conductive layer LY2 , and the second conductive layer LY2 is closer to the base substrate BS than the third conductive layer LY3 .

[0180] For example, the first conductive layer LY1 further includes a gate of a transistor, but is not limited thereto.

[0181] For example, the second conductive layer LY2 further includes a source and a drain of a transistor, but is not limited thereto.

[0182] For example, the third conductive layer LY3 further includes a first power voltage line PL1 , but is not limited thereto.

[0183] The crack detection line PCD and the source test line ST in the embodiment of the present disclosure may be made of a conductive material, for example, a metal material, but is not limited thereto.

[0184] Figure 15 is a structural diagram of an integrated circuit. For example, as shown in Figure 15 , the substrate SS of integrated circuit 88 includes a chip 502 having contact pads 500, redistribution layers (RDLs) 503 electrically connected to the contact pads 500 on chip 502, and an encapsulation layer 501 for protecting chip 502. Conductive structures 106 are electrically connected to the RDLs 503 to enable connection between chip 502 and other devices. Of course, the substrate SS of integrated circuit 88 is not limited to the structure described above and can be configured as needed.

[0185] FIG16 is a partial schematic diagram of the display panel before the bonding process. FIG17 is a partial schematic diagram of the display panel after the bonding process. FIG16 and FIG17 illustrate the location of the crack detection line PCD and the wiring area 200. Due to the dense wiring, the starting position of the arrows in FIG16 and FIG17 is the location of the crack detection line PCD, and the crack detection line PCD may not be clearly distinguished. FIG16 and FIG17 illustrate the expansion area FR. Multiple signal lines are expanded in the expansion area FR to enter the display area. FIG17 illustrates the integrated circuit 88. FIG16 and FIG17 illustrate the expansion area FR with a dotted box and the wiring area 200 with a dotted box.

[0186] For example, in an embodiment of the present disclosure, the protrusions located in the same row or in the same column may be arranged with equal sizes and equal spacing. For example, the input protrusions BP2 located in the same row may be arranged with equal sizes and equal spacing. For example, the output protrusions BP1 located in the same row may be arranged with equal sizes and equal spacing. For example, the dummy protrusions BP3 located in the same column may be arranged with equal sizes and equal spacing. When an auxiliary protrusion BP5 is provided, the auxiliary protrusion BP5 may be provided with equal sizes and equal spacing as the input protrusion BP2. When an auxiliary protrusion BP4 is provided, the auxiliary protrusion BP4 may be provided with equal sizes and equal spacing as the dummy protrusion BP3.

[0187] For example, in an embodiment of the present disclosure, the auxiliary bump BP5 may be referred to as a first auxiliary bump, and the auxiliary bump BP4 may be referred to as a second auxiliary bump.

[0188] For example, in an embodiment of the present disclosure, the interval N2 may be referred to as a first interval, and the interval N3 may be referred to as a second interval.

[0189] The various components or structures in the embodiments of the present disclosure may be arranged in order of appearance, without being restricted to the names with ordinal numbers given in the specification.

[0190] Embodiments of the present disclosure further provide a display device comprising any of the above-described display panels. For example, the display panel may be a foldable display panel, and the display device may be a foldable display device. Of course, the display panel may also be a non-foldable display panel, and the display device may also be a non-foldable display device.

[0191] For example, the display device includes an OLED or a product including an OLED. For example, the display device includes any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigation system, etc., which includes the above-mentioned display panel.

[0192] It should be noted that, for the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or intervening elements may be present.

[0193] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A display area having a plurality of sub-pixels; as well as A wiring area is located on one side of the plurality of sub-pixels, The wiring area includes an input area, an output area, and a dummy area, and the dummy area is located between the input area and the output area. The input area has a plurality of input protrusions, the output area has a plurality of output protrusions, and the dummy area has a plurality of dummy protrusions. A first spacing area is provided between the plurality of output protrusions and the plurality of dummy protrusions, and a second spacing area is provided between the plurality of input protrusions and the plurality of dummy protrusions. A stress equalization structure is arranged in the second spacing area.

2. The display panel according to claim 1, wherein: The stress equalization structure includes a plurality of auxiliary wirings, and the plurality of auxiliary wirings pass through the second spacing area.

3. The display panel according to claim 2, wherein: The first spacing area includes a plurality of signal connection wirings, and a wiring density of the plurality of auxiliary wirings is greater than or equal to a wiring density of the plurality of signal connection wirings.

4. The display panel according to claim 3, wherein: Near the dummy area, the directions of the plurality of signal connection wirings are axially symmetrical with the directions of the plurality of auxiliary wirings.

5. The display panel according to claim 4, wherein: The multiple dummy protrusions are arranged in a row along the first direction and are axisymmetric along the second direction. Near the dummy area, the directions of the multiple signal connection lines are axisymmetric with the directions of at least part of the auxiliary wiring along the second direction, and the first direction intersects with the second direction.

6. The display panel according to any one of claims 2 to 5, wherein: The plurality of auxiliary wirings include bending lines.

7. The display panel according to claim 6, wherein: The bending line has a first part, a second part, and a third part, the second part is located between the first part and the third part, the angle between the second part and the first part is an obtuse angle, the angle between the second part and the third part is an obtuse angle, and the direction of the second part is from the dummy area to the input area.

8. The display panel according to claim 7, wherein: The plurality of auxiliary wirings include a disconnected line that is disconnected at the second portion into two portions that are respectively located at both sides of the second portion.

9. The display panel according to claim 1, wherein: The stress equalization structure includes a plurality of auxiliary blocks.

10. The display panel according to claim 9, wherein: The plurality of auxiliary blocks are arranged in an array.

11. The display panel according to claim 9 or 10, wherein: An area of ​​at least part of the auxiliary block is smaller than an area of ​​the input protrusion and smaller than an area of ​​the dummy protrusion.

12. The display panel according to claim 1, wherein: The stress equalization structure includes auxiliary protrusions, and the auxiliary protrusions include a first auxiliary protrusion. The first auxiliary protrusion is located on a side of the plurality of input protrusions close to the dummy area.

13. The display panel according to claim 12, wherein: The minimum spacing between the first auxiliary protrusion and the plurality of dummy protrusions is a first spacing, and a ratio of an absolute value of a difference between the first spacing and a minimum dimension of the first spacing area to the minimum dimension of the first spacing area is greater than or equal to 0 and less than or equal to 10%.

14. The display panel according to claim 12, further comprising an alignment mark, wherein: The alignment mark is located between the first auxiliary protrusion and the plurality of input protrusions, and a distance between the first auxiliary protrusion and an input protrusion adjacent thereto is greater than a distance between two adjacent input protrusions.

15. The display panel according to claim 12, wherein: The auxiliary protrusion further includes a second auxiliary protrusion, and the second auxiliary protrusion is located on a side of the plurality of dummy protrusions close to the input area.

16. The display panel according to claim 15, wherein: The minimum distance between the first auxiliary protrusion and the second auxiliary protrusion is a second distance, and the minimum size of the first spacing area is greater than the second distance.

17. The display panel according to claim 16, wherein: The minimum size of the first spacing area is greater than 1.5 times the second spacing.

18. The display panel according to claim 16, wherein: The minimum size of the first spacing area is greater than twice the second spacing.

19. The display panel according to any one of claims 1 to 18, further comprising a peripheral area, wherein: The peripheral area surrounds the display area, and the peripheral area has a crack detection line, wherein the crack detection line passes through the second spacing area.

20. The display panel according to claim 19, further comprising a source test line, wherein: The source test line is located in the peripheral area and at one side of the crack detection line, and the source test line passes through the second spacing area. 21 . The display panel of claim 19 , further comprising a data line, wherein the data line is configured to provide a data voltage to the sub-pixel, and the plurality of output bumps include an output bump connected to the data line.

22. The display panel according to any one of claims 1 to 21, further comprising an integrated circuit, wherein: The plurality of conductive structures on the integrated circuit are respectively connected to the plurality of input protrusions, the plurality of output protrusions, and the plurality of dummy protrusions on the display panel through anisotropic adhesive.

23. The display panel according to any one of claims 1 to 21, further comprising an inorganic insulating layer, wherein: The inorganic insulating layer at least includes a portion located in the second spacer region, and the stress equalization structure is configured to equalize stress of the portion of the inorganic insulating layer located in the second spacer region during an integrated circuit bonding process.

24. A display panel comprising: A display area having a plurality of sub-pixels; as well as A wiring area is located on one side of the plurality of sub-pixels, The wiring area includes an input area, an output area, and a dummy area, and the dummy area is located between the input area and the output area. The input area has a plurality of input protrusions, the output area has a plurality of output protrusions, and the dummy area has a plurality of dummy protrusions. A first spacing area is provided between the plurality of output protrusions and the plurality of dummy protrusions, and a second spacing area is provided between the plurality of input protrusions and the plurality of dummy protrusions. The second spacing region has a plurality of auxiliary wirings, a plurality of auxiliary blocks, or at least one auxiliary protrusion.

25. The display panel according to claim 24, wherein: The plurality of auxiliary wirings pass through the second spacing area, the first spacing area includes a plurality of signal connection wirings, and a wiring density of the plurality of auxiliary wirings is greater than or equal to a wiring density of the plurality of signal connection wirings.

26. The display panel according to claim 24 or 25, wherein: An area of ​​each of the plurality of auxiliary blocks is smaller than an area of ​​each of the plurality of input bumps, and smaller than an area of ​​each of the plurality of dummy bumps.

27. The display panel according to any one of claims 24 to 26, wherein: The at least one auxiliary protrusion includes a first auxiliary protrusion located in the input area and / or a second auxiliary protrusion located in the dummy area, and the minimum spacing between the first auxiliary protrusion and the dummy protrusion most adjacent to it, the minimum spacing between the second auxiliary protrusion and the input protrusion most adjacent to it, or the absolute value of the difference between the minimum spacing between the first auxiliary protrusion and the second auxiliary protrusion and the minimum size of the first spacing area and the minimum size of the first spacing area are greater than or equal to 0 and less than or equal to 10%.

28. A display device comprising the display panel according to any one of claims 1-27.

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