Clock gate tree

Abstract

This document describes systems and techniques for implementing a clock gate tree to save clock power. A root level clock gate receives a clock signal associated with a line of data to be accessed in a data structure. A line level clock gate is associated with the line of data to be accessed in the data structure. A clock gate tree includes multiple clock gates. The clock gate tree receives the clock signal from the root level clock gate and activates a portion of the plurality of clock gates in the clock gate tree to communicate the clock signal to the line level clock gate. The portion of the plurality of clock gates in the clock gate tree are activated based on the line level clock gate that activates the line of data to be accessed.

Description

CLOCKGATETREEBACKGROUND

[0001] Multi-dimensional arrays of storage devices typically use clock gates to manage clock signals provided to the multiple storage devices. In many multi-dimensional arrays, the configuration includes root level clock gates and line level clock gates. The root level clock gates control access to the entire multi-dimensional array or a large section of the multi-dimensional array. The line level clock gates control access to lines of data within the multi-dimensional array. This configuration consumes large amounts of power because many clock gates are using power during active workloads. Active workloads refers to active use of a data structure to store and access data. For example, in some multi-dimensional array configurations, the root level clock gates consume power along with all of the line level clock gates when dealing with active workloads. This increased use of power can be expensive, may produce significant heat within the system, and may cause other problems. SUMMARY

[0002] This document describes systems and techniques for implementing a clock gate tree to save clock power by using selective clock gating. In some aspects, these systems and techniques deactivate clock signals when one or more circuits or storage lines are not in use.

[0003] To reduce clock power used by a storage device (e.g., a device with multi- dimensional arrays), a clock gate tree is included along with root level clock gates and line level clock gates. As discussed herein, the clock gate tree may selectively activate and deactivate particular line level clock gates associated with storage lines in a storage device. Deactivating unused line level clock gates reduces power consumption by the storage device.

[0004] For example, an apparatus includes a root level clock gate that is configured to receive a clock signal associated with a data structure to be accessed. A line level clock gate may be associated with a line of data to be accessed (e.g., read or written) in the data structure. A clock gate tree includes multiple clock gates. The clock gate tree is configured to receive the clock signal from the root level clock gate. The clock gate tree is also configured to activate a portion of the plurality of the clock gates in the clock gate tree to communicate the clock signal to the line level clock gate.

[0005] In another example, a method comprises receiving a clock signal at a root level clock gate, where the clock signal is associated with a line of data to be accessed. The method comprises communicating the clock signal to a clock gate tree. The method further comprises activating appropriate clock gates in the clock gate tree to communicate the clock signal to a linelevel clock gate associated with the line of data to be accessed. The method further comprises deactivating other clock gates in the clock gate tree that are not needed to access the line of data. The clock signal is then communicated to the line level clock gate associated with the line of data to be accessed.

[0006] This document also describes other methods, configurations, and systems for implementing clock gate trees. Optional features of one aspect, such as the apparatus or method described above, may be combined with other aspects.

[0007] This summary is provided to introduce simplified concepts for implementing clock gate trees, which is further described below in the detailed description and drawings. This summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The details of one or more aspects of clock gate tree control in integrated circuits are described in this document with reference to the following drawings. The same numbers are used throughout multiple drawings to reference like features and components.

[0009] FIG.1 illustrates an example device diagram of a computer system in which binary clock gate trees can be implemented.

[0010] FIG. 2 illustrates an example diagram of a configuration of a device that includes a binary clock gate tree to manage clock power usage by activating and deactivating clock signals.

[0011] FIG. 3 illustrates an example of a binary clock gate tree to manage clock power usage.

[0012] FIG. 4 illustrates additional details regarding the binary clock gate tree illustrated in FIG.3.

[0013] FIG. 5 illustrates another example of a binary clock gate tree to manage clock power usage.

[0014] FIG.6 illustrates an example of a 4-way clock gate tree capable of managing clock power usage.

[0015] FIG. 7 illustrates an example method for processing clock signals using a binary clock gate tree, wherein at least some of the clock gates in the binary clock gate tree are deactivated to save power.

[0016] FIG.8 illustrates an example method for determining a circuit to implement power savings while considering the physical space needed to support additional clock gates that provide the power savings.

[0017] FIG.9 illustrates an example method for controlling the activation and deactivation of clock gates to access appropriate lines of data in a storage device while reducing power consumption of the storage device. DETAILED DESCRIPTION OVERVIEW

[0018] This document describes clock gate trees that may be used in integrated circuits to save clock power by deactivating particular clock signals when a circuit is not in use. Specific examples described herein are illustrated using binary clock gate trees. However, the systems and methods described herein are applicable to any type of n-way clock gate tree, as shown in one example.

[0019] Although particular examples discussed herein refer to multi-dimensional arrays of storage devices, the described systems and techniques are useful with a variety of devices and a variety of configurations.

[0020] Various example configurations and methods are described throughout this document. This document now describes example methods and components of the described clock gate trees. EXAMPLEDEVICES

[0021] FIG. 1 illustrates an example device diagram 100 of a computer system 102 in which binary clock gate trees can be implemented, such as in one or more integrated circuits 106. The computer system 102 may include additional components and interfaces omitted from FIG.1 for the sake of clarity.

[0022] The computer system 102 can be a variety of consumer electronic devices. As non- limiting examples, the computer system 102 can be a mobile phone 102-1, a tablet device 102-2, a laptop computer 102-3, a desktop computer 102-4, a computerized watch 102-5, a wearable computer 102-6, a video game controller 102-7, a voice-assistant system 102-8, and the like.

[0023] The computer system 102 includes one or more radio frequency (RF) transceiver(s) 104 for communicating over wireless networks. The computer system 102 can tune the RF transceiver(s) 104 and supporting circuitry (e.g., antennas, front-end modules, amplifiers) to one or more frequency bands defined by various communication standards.

[0024] The computer system 102 includes the one or more integrated circuits 106. The integrated circuits 106 can include, as non-limiting examples, a central processing unit, a graphics processing unit, or a tensor processing unit. A central processing unit generally executes commands and processes needed for the computer system 102 and an operating system 118. Agraphics processing unit performs operations to display graphics of the computer system 102 and can perform other specific computational tasks. A tensor processing unit generally performs symbolic match operations in neural-network machine-learning applications. The integrated circuits 106 can be single-core or multiple-core processors.

[0025] The computer system 102 also includes computer-readable storage media (CRM) 116. The CRM 116 is a suitable storage device (e.g., random-access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NVRAM), read-only memory (ROM), Flash memory) to store device data of the computer system 102. The device data can include the operating system 118, one or more applications 120 of the computer system 102, user data, and multimedia data. The operating system 118 generally manages hardware and software resources (such as the applications 120) of the computer system 102 and provides common services for the applications 120. The operating system 118 and the applications 120 are generally executable by the integrated circuits 106 (e.g., a central processing unit) to enable communications and user interaction with the computer system 102.

[0026] The integrated circuits 106 may include one or more sensors 108, a clock generator 110, a clock gate tree module 112, and a frequency control module 114. The integrated circuits 106 can include other components (not illustrated), including N-way clock gate trees, communication units (e.g., modems), input / output controllers, and system interfaces.

[0027] The one or more sensors 108 include sensors or other circuitry operably coupled to at least one integrated circuit 106. The sensors 108 monitor the process, voltage, and temperature of the integrated circuit 106 to assist in evaluating operating conditions of the integrated circuit 106. The sensors 108 can also monitor other aspects and states of the integrated circuit 106. The integrated circuit 106 can utilize outputs of the sensors 108 to monitor its chip state and provide an input to the frequency control module 114 to dynamically control the frequency of a clock signal. Other modules can also use the sensor outputs to adjust the system voltage of the integrated circuit 106.

[0028] The clock generator 110 provides an input clock signal, which can oscillate between a high state and a low state, to synchronize operations of the integrated circuit 106. In other words, the input clock signal can pace sequential processes of the integrated circuit 106. The clock generator 110 can include a variety of devices, including a crystal oscillator or a voltage- controlled oscillator, to produce the input clock signal with a consistent number of pulses (e.g., clock cycles) with a particular duty cycle (e.g., the width of individual high states) at the desired frequency. As an example, the input clock signal can be a periodic square wave.

[0029] The clock gate tree module 112 can manage any number of clock gates in a clock gate tree, such as a binary clock gate tree, to reduce power consumption. For example, the clockgate tree module 112 may deactivate particular clock gates when associated circuits or storage lines are not in use. Deactivating a portion of the clock gates reduces power consumption by the related storage device. The clock gate tree module 112 also manages the propagation of clock signals through multiple clock gates to activate the appropriate circuits or storage lines to allow access to desired data in the storage device.

[0030] In some aspects, the clock gate tree module 112 may instantiate all clocks in a data storage structure. These clocks can include root level clocks, binary level clocks, and line level clocks. As discussed herein, the root level clocks may include a free running clock that is gated using a root level clock enable signal. The root level clock enable signal can determine whether an entire data structure is activated or deactivated. The binary level clocks are based on a number of levels of clock gates that are implemented in the binary tree. The line level clocks are implemented such that each line level gate will drive one or more flops in the circuit, as discussed in greater detail herein.

[0031] Additionally, the clock gate tree module 112 may manage various parameters, including user-defined parameters discussed herein. Example parameters may be related to the number of lines in a particular storage device, the number of binary tree levels in a particular configuration, and the like.

[0032] The frequency control module 114 can alter the input clock signal generated by the clock generator 110. The frequency control module 114 can be implemented using hardware, software, firmware, or any combination thereof. The frequency control module 114 can adaptively manage, based on operating conditions of the integrated circuit 106 detected by one or more of the sensors 108, the frequency of the clock signal to improve performance and reduce the power consumption of the integrated circuit 106. This document describes components and operation of binary clock gate trees in greater detail with respect to FIG.2.

[0033] FIG. 2 illustrates an example diagram 200 of a configuration of a device that includes a binary clock gate tree to manage clock power usage by activating and deactivating clock gates and associated clock signals. In the example of FIG. 2, the various clock gates are identified by a broken line 202. The clock gates in 202 include a root level clock gate 204 that receives a free running clock signal that is gated using a root level clock enable signal. The root level clock enable signal may be used to determine whether an entire data structure shown in FIG. 2 is activated. For example, if the root level clock enable signal is active, the root level clock gate 204 activates a first column of binary clock gates identified as binary clock gates 206-1. In contrast, if the root level clock enable signal is not active, the root level clock gate 204 does not activate any gates in the first level of binary clock gates 206-1.

[0034] The clock gates in 202 include a binary clock gate tree arranged in three columns 206-1, 206-2, and 206-3. In some aspects, each column 206-1, 206-2, and 206-3 may be referred to as a “level” of the binary clock gate tree. For example, column 206-1 may be referred to as a first level of the binary clock gate tree, column 206-2 may be referred to as a second level of the binary clock gate tree, and column 206-3 may be referred to as a third level of the binary clock gate tree.

[0035] As discussed herein, each of the clock gates in columns 206-1, 206-2, and 206-3 can be activated individually depending on a data line being activated. It is noted, however, that individual enable signals are not illustrated for each of the clock gates in the columns 206-1, 206- 2, and 206-3. The various clock gates shown in FIG.2 also include line level clock gates 208, 210, 212, and 214 that activate or deactivate specific data lines (or groups of data lines) in a data structure. In the example of FIG. 2, a first line level clock gate 208 activates or deactivates data lines 0 and 1, a second line level clock gate 210 activates or deactivates data lines 2 and 3, a third line level clock gate 212 activates or deactivates data lines N-3 and N-4, and a fourth line level clock gate 214 activates or deactivates data lines N-1 and N-2. Although the four line level clock gates 208, 210, 212, and 214 are illustrated in FIG. 2, the entire circuit may include a different number of line level clock gates. For example, the entire circuit may include 64 line level clock gates, where each line level clock gate activates or deactivates two data lines, which provides control of all 128 data lines in the data storage structure.

[0036] As shown in FIG. 2, the binary clock gate tree is arranged in the three columns 206-1, 206-2, and 206-3. In other aspects, any number of columns of clock gates may be included in the binary clock gate tree and different numbers of clock gates may be included in each column. The configuration of the binary clock gate tree may change based on the desired power savings as well as the amount of physical space available (or allocated) in the device for additional clock gates and communication links between the additional clock gates and other components. The configuration of the binary clock gate tree may be determined by a designer, an administrator, design software, and the like.

[0037] In the example of FIG. 2, N lines are activated or deactivated by line level clock gates, such as 208, 210, 212, and 214. Line Id (e.g., Line Identifier) information provided to the line level clock gate 208, 210, 212 or 214 indicates which data line in the data storage structure needs to be accessed. For example, if the line level clock gate 208 receives Line Id information identifying Line1, then Line1 of the data structure is accessed. A data line may be accessed to perform, for example, a read operation or a write operation.

[0038] Each of the N lines shown in FIG. 2 has the same line width (e.g., the number of flops (or bits) in each line). In an example, a particular device may include 128 lines that are eight flops wide.

[0039] In a particular implementation, the device shown in FIG.2 wants to access data in Line1. This is accomplished by activating the root level clock gate 204 and binary clock gates 216-1, 216-2, and 216-3. The remaining binary clock gates in columns 206-1, 206-2, and 206-3 are deactivated because they are not required for accessing data in Line1. Regarding the line level clock gates, the gate 208 is activated to access data in Line1. The remaining line level clock gates are deactivated.

[0040] Therefore, a significant number of clock gates shown in the example of FIG.2 are deactivated, thereby saving power because the deactivated clock gates do not require any power. Although there is a power saving, that saving is offset by the additional clock gates in the device (e.g., the binary clock gates) and the additional connections between the clock gates. Thus, designers of a storage structure may adjust the design of the device shown in FIG. 2 to optimize the power savings when compared to the increased number of clock gates and additional connections between the clock gates.

[0041] Thus, specific clock gates in the example of FIG.2 can be activated and deactivated to reduce power when the deactivated portions of the data structure are not being used.

[0042] Although FIG.2 illustrates the binary clock gate tree 206, alternate configurations may include an N-way clock gate tree, where N is an integer. An example N-way clock gate tree is illustrated in FIG.6 and discussed herein.

[0043] FIG.3 illustrates an aspect 300 of a binary clock gate tree to manage clock power usage. In the example of FIG. 3, clock gates include a root level clock gate 304 that receives a free running clock signal that is gated using a root level clock enable signal. The root level clock enable signal may be used to determine whether an entire data structure shown in FIG. 3 is activated or deactivated.

[0044] The example of FIG.3 also includes a binary clock gate tree 302 arranged in three columns (similar to the binary clock gate tree 206 in FIG. 2), each column corresponding to a clock gate tree level. The left column may be referred to as a highest level column in the clock gate tree. Each clock gate in the highest level column is connected to the root level clock gate. The right column corresponds to the lowest level column in the clock gate tree, which is the third level in the illustrated example. As discussed herein, each of the clock gates in the binary clock gate tree 302 can be activated individually depending on the data line being activated. It is noted, however, that individual enable signals are not illustrated for each of the clock gates in the binary clock gate tree 302. The activated data line may be accessed to perform a data read or data writeoperation. The various clock gates in FIG. 3 also include line level clock gates 306 that activate or deactivate specific lines in a data structure depending on the data line being accessed.

[0045] As shown in FIG. 3, a particular clock gate 308 in a right column (lowest level column) in the binary clock gate tree 302 is connected to 16 data lines (Line0 – Line15). Each of the seven other clock gates in the right column of the binary clock gate tree 302 is also connected to 16 data lines. Thus, the eight clock gates in the right column of the binary clock gate tree 302 are each connected to 16 data lines, which provides support for all 128 data lines.

[0046] In the example of FIG.3, there are 128 lines and each line has a width of 8 bits (or 8 flops). The minimum number of flops per line level clock gate is 8. As shown in FIG.3, each line level clock gate 306 represents one line of data. As mentioned above, there are eight clock gates in the right column of the binary clock gate tree 302, which means each of the eight clock gates is connected to 16 line level clock gates 306 (e.g., 8 x 16 = 128).

[0047] For the example configuration shown in FIG. 3, during active workloads the number of clock gates that will use power is 23 clock gates. This includes 16 line level clock gates 306, two clock gates in each column (i.e., 6 clock gates in this example) and the root level clock gate 304. Alternatively, without the binary clock gate tree 302, during active workloads the number of clock gates that would use power is 129 gates. So, the addition of the binary clock gate tree 302 significantly reduces the amount of power used during active workloads.

[0048] Thus, specific clock gates in the example of FIG.3 can be activated and deactivated to reduce power when the deactivated portions of the data structure are not being used.

[0049] Although FIG.3 illustrates the binary clock gate tree 302, alternate configurations may include an N-way clock gate tree, where N is an integer. An example N-way clock gate tree is illustrated in FIG.6 and discussed herein.

[0050] FIG. 4 illustrates additional details 400 regarding the binary clock gate tree illustrated in FIG.3. In particular, FIG.4 illustrates various line id signals that are inputs to clock gates in an illustrated circuit to activate and deactivate clock gates to reduce power consumption.

[0051] For example, the binary clock gate tree illustrated in FIG. 3 is shown in FIG. 4 as a binary clock gate tree 402. A root level clock gate 404 receives a free running clock signal that is gated using a root level clock enable signal. The root level clock enable signal may be used to determine whether an entire data structure shown in FIG. 4 is activated or deactivated. Additionally, multiple line level clock gates 406 are connected to a right column 420 of clock gates in the binary clock gate tree 402. In the example of FIG.4, there are 128 data lines connected to the line level clock gates 406.

[0052] As illustrated in FIG.4, the root level clock gate 404 is connected to binary clock gates 408 and 410 of the binary clock gate tree 402. The binary clock gates 408 and 410 receiveline_id signals as inputs. Since the number of lines in the example of FIG. 4 is 128, the system uses line_id[6:0] as input. Thus, an enable condition for the binary clock gate 408 is line_id[6]=0. When this condition is satisfied, an enable signal is provided to clock gate 408, to access an upper half of the data structure. The enable condition for the binary clock gate 410 is line_id[6]=1, which allows an enable signal to be provided to clock gate 410 to access a lower half of the data structure.

[0053] An output of the binary clock gate 408 is connected to an input of binary clock gates 412 and 416. An output of the binary clock gate 410 is connected to an input of binary clock gates 414 and 418. Additionally, an input signal line_id[5]=0 is provided to the binary clock gates 412 and 414, while an input signal line_id[5]=1 is provided to the binary clock gates 416 and 418.

[0054] Outputs of the binary clock gates 412, 414, 416, and 418 are connected to inputs of various pairs of binary clock gates in the right column 420 of the binary clock gate tree 402. The inputs to the binary clock gates in the right column 420 are line_id[4]=0 and line_id[4]=1, as shown by two different broken lines illustrated in FIG.4.

[0055] Thus, specific clock gates in the example of FIG.4 can be activated and deactivated to reduce power when the deactivated portions of the data structure are not being used. In a binary clock gate tree, as shown in FIG. 4, each column of the clock gate tree can be activated and deactivated based on a particular bit of the line_id. That is, each of the plurality of clock gates within the clock gate tree is configured to receive an enable signal based on a line identifier that indicates the line of data to be accessed in the data structure. Enable signals for each column of clock tree gates may be generated based on a different bit of the line_id.

[0056] Although FIG.4 illustrates the binary clock gate tree 402, alternate configurations may include an N-way clock gate tree, where N is an integer. An example N-way clock gate tree is illustrated in FIG.6 and discussed herein.

[0057] FIG. 5 illustrates another aspect 500 of a binary clock gate tree to manage clock power usage. In the example of FIG.5, clock gates include a root level clock gate 504 that receives a free running clock signal that is gated using a root level clock enable signal. The root level clock enable signal may be used to determine whether an entire data structure shown in FIG. 5 is activated or deactivated.

[0058] The example of FIG. 5 also includes a binary clock gate tree 502 arranged in two columns. As discussed herein, each of the clock gates in the binary clock gate tree 502 can be activated individually depending on a data line being activated in the data structure. The various clock gates in FIG. 5 also include line level clock gates 506 that activate or deactivate specific lines in the data structure.

[0059] In the example of FIG.5, there are 128 lines and each line has a width of 5 bits (or 5 flops). The minimum number of flops per line level clock gate is 8, which can be a design decision based on the understanding of the benefit (e.g., return on investment) of inserting a clock gate for a particular number of flops. As shown in FIG.5, each line level clock gate 506 represents two lines of data. There are 4 clock gates in the right column of the binary clock gate tree 502.

[0060] For the example configuration shown in FIG. 5, during active workloads the number of clock gates that will use power is 21 clock gates. The number of clock gates that use power in this configuration can be defined by: Number of clock gates using power = (Number of levels in Clock Gate Tree x 2) + MaxFOPerICG + 1, where FO is Fan Out and ICG is Integrated Clock Gate.

[0061] In the example of FIG. 5, there are two levels in the clock gate tree and MaxFOPerICG = 16. So, the Number of clock gates using power = (2 x 2) +16 + 1 = 21.

[0062] Alternatively, without the binary clock gate tree 502, during active workloads the number of clock gates that would use power is 129 clock gates. So, the addition of the binary clock gate tree 502 significantly reduces the amount of power used during active workloads (e.g., by reducing power consumption from 129 clock gates to 21 clock gates).

[0063] Thus, specific clock gates in the example of FIG.5 can be activated and deactivated to reduce power when the deactivated portions of the data structure are not being used.

[0064] Although FIG.5 illustrates the binary clock gate tree 502, alternate configurations may include an N-way clock gate tree, where N is an integer. An example N-way clock gate tree is illustrated in FIG.6 and discussed herein.

[0065] FIG. 6 illustrates an aspect of an N-way clock gate tree 600 where N=4 (i.e., a 4- way clock gate tree) capable of managing clock power usage. In the example of FIG. 6, clock gates include a root level clock gate 602 that receives a free running clock signal that is gated using a root level clock enable signal. The root level clock enable signal may be used to determine whether an entire data structure shown in FIG.6 is activated or deactivated.

[0066] The example of FIG.6 also includes multiple clock gates 604 coupled to an output of the root level clock gate 602. The multiple clock gates 604 use bit 5 and bit 6 for enable conditions. In one aspect, enable conditions are 00, 01, 10, and 11 for each of the multiple clock gates 604.

[0067] In some implementations, multiple clock gates 606, 608, 610, and 612 are coupled to outputs of each of the clock gates 604. The multiple clock gates 606, 608, 610, and 612 use bit 4 and bit 3 for enable conditions. That is, enable signals for each column of clock tree gates may be generated based on different bits of the line_id. In this example, where N=4, bits 5 and 6 areused to generate the enable signals for the first column, and bits 3 and 4 are used to generate the enable signals the second column.

[0068] Thus, specific clock gates in the example of FIG.6 can be activated and deactivated to reduce power when the deactivated portions of the data structure are not being used.

[0069] Although the example discussed regarding FIG. 6 is a 4-way clock gate tree, a similar approach may be used for any N-way clock gate tree where N is an integer. In some implementations, N is an integer that is a multiple of 2, which may simplify determination of an enable condition for the clock gates in the clock gate tree. EXAMPLEMETHODS

[0070] FIG. 7 illustrates an example method 700 for processing clock signals using a binary clock gate tree, wherein at least some of the clock gates in the binary clock gate tree are deactivated to save power.

[0071] At 702, a clock signal is received at a root level clock gate. The clock signal is associated with a line of data to be accessed in a data structure. For example, the root level clock gate may be the root level clock gate 204 illustrated in FIG. 2 and discussed herein. The data structure may include the N lines of data shown in FIG.2.

[0072] At 704, the clock signal is communicated to a binary clock gate tree that activates appropriate clock gates in the binary clock gate tree to communicate the clock signal to a line level clock gate associated with the line of data to be accessed. For example, the binary clock gate tree may include the binary clock gate tree illustrated in FIG.2 in the combination of the columns 206- 1, 206-2, and 206-3. Additionally, the line level clock gate may be any of the line level clock gates 208, 210, 212, or 214 shown in FIG.2.

[0073] At 706, the method deactivates other binary clock gate tree gates and line level clock gates not needed for accessing the line of data (e.g., some or all other clock gates). For example, binary clock gate tree gates and line level clock gates that are associated with lines of data not being accessed can be deactivated to reduce power consumption. The binary clock gate tree gates and line level clock gates associated with a line of data being accessed in the data structure remain active (and use power) at least until the data access activity is finished. 704 and 706 may occur concurrently.

[0074] At 708, the clock signal is communicated to the line level clock gate associated with the line of data to be accessed. In the example of FIG.2, if Line0 or Line1 is being accessed, the line level clock gate 208 is activated to allow access to that data.

[0075] At 710, data is accessed from the line of data. For example, data may be read from or written to Line0 or Line1 of FIG.2. In some aspects, the data may be communicated to other devices or systems depending on the planned use of the data.

[0076] The method of FIG.7 may continue operating by accessing data from another line of data by activating and deactivating the appropriate clock gates for the desired line of data. Thus, different combinations of clock gates may be activated and deactivated to support different data access activities.

[0077] FIG. 8 illustrates an example method 800 for determining a circuit to implement power savings while considering the physical space needed to support additional clock gates that provide the power savings. In some aspects, the circuit that implements the power savings includes a clock gate tree as discussed herein.

[0078] At 802, the method 800 determines an amount of power savings desired. This determination may be based on the computer system or other device in which the clock gate tree is operating. The power savings determination may be calculated by a designer, an administrator, design software, and the like.

[0079] At 804, the method 800 determines a number of additional clock gates and a configuration of the clock gates to achieve the desired power savings. In some aspects, the additional clock gates are part of a clock gate tree that interacts with existing root level clock gates and line level clock gates. The clock gate tree may have different configurations of clock gates (e.g., different numbers of columns of clock gates) as shown herein. The configuration of the clock gates may vary based on the number of data lines being supported, the number of data lines associated with each line level clock gate, and the like.

[0080] As discussed herein, the additional clock gates in the clock gate tree may allow deactivation of other clock gates that reduce the amount of power used by the overall circuit to access a data line. For example, the additional clock gates in the clock gate tree may include the binary clock gate tree illustrated in FIG. 2 in the combination of the columns 206-1, 206-2, and 206-3.

[0081] At 806, the method 800 determines an amount of physical space needed to support the additional clock gates and routing of communication links between the additional clock gates and other components. Each additional clock gate requires physical space in the device. Additionally, the number of communication links between the clock gates and other components increases with each added clock gate. Additional communication links also require physical space in the device. Thus, a designer, an administrator, design software, and the like may calculate the extra physical space used by the clock gates and the communication links while comparing that extra physical space requirement to the power savings benefits.

[0082] At 808, a circuit is designed to implement the desired power savings. The example implementation may include a binary clock gate tree (as shown in FIG. 2) as well as the communication links between the gates in the binary clock gate tree and other components. As mentioned above, design of the circuit to implement the desired power savings is based on the amount of power savings desired (benefit) and a cost of the extra physical space used by the clock gates and the communication links.

[0083] The method of FIG.8 may be performed multiple times to optimize the design of a particular circuit that provides power savings without using too much extra physical space. Additionally, the method of FIG.8 may be performed multiple times to implement power savings in any number of different computer systems or other devices.

[0084] FIG. 9 illustrates an example method 900 for controlling the activation and deactivation of clock gates to access a line of data in a storage device while reducing power consumption of the storage device.

[0085] At 902, the method 900 receives a request to access data in a storage device. In some aspects, the request to access data may include a line of data in the storage device.

[0086] At 904, the method 900 identifies a line of data to access in the storage device. In some aspects, the access of the line of data may include reading data and / or storing data in the identified line of data.

[0087] At 906, the method 900 determines multiple clock gates to activate in the storage device that will provide access to the line of data identified at 904. The activated clock gates will depend on a configuration of root level clock gates, the clock gates in a clock gate tree, and line level clock gates. In some aspects, the multiple clock gates to activate are associated with a path (or paths) from a root level clock gate to the line of data identified in 904.

[0088] At 908, the method 900 activates the multiple clock gates determined at 906 to access the line of data in the storage device. Additionally, the method 900 deactivates other clock gates that are not needed to access the line of data. By deactivating clock gates that are not needed to access the line of data, power consumption by the storage device is decreased. Examples of activating and deactivating various clock gates to access a particular line of data are discussed herein.

[0089] At 910, the method 900 accesses data from the line of data using the activated clock gates. The activated clock gates remain active until the read or write operation is completed regarding the line of data.

[0090] The method of FIG. 9 may continue operating by receiving another request to access data in the storage device at 902. The method 900 may then identify a line of data relatedto the new data access request and activate / deactivate various clock gates to provide access to the new line of data. EXAMPLES

[0091] In the following section, examples are provided.

[0092] Example 1: An apparatus comprising: a root level clock gate configured to receive a clock signal associated with a line of data to be accessed in a data structure; a line level clock gate associated with the line of data to be accessed in the data structure; and a clock gate tree including a plurality of clock gates, the clock gate tree configured to receive the clock signal from the root level clock gate and configured to activate a portion of the plurality of clock gates in the clock gate tree to communicate the clock signal to the line level clock gate, wherein the portion of the plurality of clock gates in the clock gate tree are activated based on the line level clock gate that activates the line of data to be accessed.

[0093] Example 2: The apparatus of example 1 or any other example, wherein the clock gate tree is further configured to deactivate line level clock gates not needed to access the line of data.

[0094] Example 3: The apparatus of example 2 or any other example, wherein deactivation of the line level clock gates not needed to access the line of data reduces power usage by the data structure.

[0095] Example 4: The apparatus of example 1 or any other example, wherein the line level clock gate is configured to receive a line identifier that indicates the line of data to be accessed in the data structure.

[0096] Example 5: The apparatus of example 1 or any other example, wherein each of the plurality of clock gates within the clock gate tree is configured to receive an enable signal based on a line identifier that indicates the line of data to be accessed in the data structure.

[0097] Example 6: The apparatus of example 1 or any other example, wherein a number of clock gates in the clock gate tree is selected to improve power savings while reducing an impact of added clock gates in the clock gate tree.

[0098] Example 7: The apparatus of example 1 or any other example, wherein the clock gate tree is further configured to reduce a number of clock gates that receive the clock signal.

[0099] Example 8: The apparatus of example 1 or any other example, wherein the clock gate tree is a binary clock gate tree.

[0100] Example 9: The apparatus of example 1 or any other example, wherein the clock gate tree is configured as a plurality of columns of clock gates, wherein a rightmost column of clock gates is connected to a plurality of line level clock gates.

[0101] Example 10: The apparatus of example 1 or any other example, wherein the clock gate tree is configured as a plurality of columns of clock gates, each column corresponding to a clock gate tree level, wherein a lowest level column of clock gates is connected to a plurality of line level clock gates.

[0102] Example 11: The apparatus of example 11, wherein a highest level column of clock gates is connected to the root level clock gate.

[0103] Example 12: A method comprising: receiving a clock signal at a root level clock gate, wherein the clock signal is associated with a line of data to be accessed in a data structure; communicating the clock signal to a clock gate tree; activating clock gates in the clock gate tree to communicate the clock signal to a line level clock gate associated with the line of data to be accessed; deactivating other clock gates in the clock gate tree that are not needed to access the line of data; and communicating the clock signal to the line level clock gate associated with the line of data to be accessed.

[0104] Example 13: The method of example 12 or any other example, the method further comprising: accessing data from the line of data.

[0105] Example 14: The method of example 12 or any other example, the method further comprising: determining a number of clock gates in the clock gate tree that improve power savings while also reducing an impact of added clock gates in the clock gate tree.

[0106] Example 15: The method of example 14 or any other example, wherein the power savings are based on deactivating line level clock gates not needed to access the line of data.

[0107] Example 16: The method of example 12 or any other example, the method further comprising: receiving a line identifier that indicates the line of data to be accessed.

[0108] Example 17: The method of example 12 or any other example, the method further comprising: reducing a number of clock gates in the clock gate tree and the line level clock gates that receive the clock signal.

[0109] Example 18: The method of example 12 or any other example, wherein the clock gate tree is a binary clock gate tree. CONCLUSION

[0110] While various configurations and methods for implementing clock gate trees have been described in language specific to features and / or methods, it is to be understood that the subject of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as non-limiting examples of implementing clock gate trees in integrated circuits or other systems.

Claims

CLAIMS What is claimed is:

1. An apparatus comprising: a root level clock gate configured to receive a clock signal associated with a line of data to be accessed in a data structure; a line level clock gate associated with the line of data to be accessed in the data structure; and a clock gate tree including a plurality of clock gates, the clock gate tree configured to receive the clock signal from the root level clock gate and configured to activate a portion of the plurality of clock gates in the clock gate tree to communicate the clock signal to the line level clock gate, wherein the portion of the plurality of clock gates in the clock gate tree are activated based on the line level clock gate that activates the line of data to be accessed.

2. The apparatus of claim 1, wherein the clock gate tree is further configured to deactivate line level clock gates not needed to access the line of data.

3. The apparatus of claim 2, wherein deactivation of the line level clock gates not needed to access the line of data reduces power usage by the data structure.

4. The apparatus of any preceding claim, wherein the line level clock gate is configured to receive a line identifier that indicates the line of data to be accessed in the data structure.

5. The apparatus of any preceding claim, wherein each of the plurality of clock gates within the clock gate tree is configured to receive an enable signal based on a line identifier that indicates the line of data to be accessed in the data structure.

6. The apparatus of any preceding claim, wherein a number of clock gates in the clock gate tree is selected to improve power savings while reducing an impact of added clock gates in the clock gate tree.

7. The apparatus of any preceding claim, wherein the clock gate tree is further configured to reduce a number of clock gates that receive the clock signal.

8. The apparatus of any preceding claim, wherein the clock gate tree is a binary clock gate tree.

9. The apparatus of any preceding claim, wherein the clock gate tree is configured as a plurality of columns of clock gates, each column corresponding to a clock gate tree level, wherein a lowest level column of clock gates is connected to a plurality of line level clock gates.

10. A method comprising: receiving a clock signal at a root level clock gate, wherein the clock signal is associated with a line of data to be accessed in a data structure; communicating the clock signal to a clock gate tree; activating clock gates in the clock gate tree to communicate the clock signal to a line level clock gate associated with the line of data to be accessed; deactivating other clock gates in the clock gate tree that are not needed to access the line of data; and communicating the clock signal to the line level clock gate associated with the line of data to be accessed.

11. The method of claim 10, the method further comprising: accessing data from the line of data.

12. The method of claim 10 or 11, the method further comprising: determining a number of clock gates in the clock gate tree that improve power savings while also reducing an impact of added clock gates in the clock gate tree.

13. The method of claim 12, wherein the power savings are based on deactivating line level clock gates not needed to access the line of data.

14. The method of any one of claims 10 to 13, the method further comprising: receiving a line identifier that indicates the line of data to be accessed.

15. The method of any one of claims 10 to 14, the method further comprising: reducing a number of clock gates in the clock gate tree and the line level clock gates that receive the clock signal.

16. The method of any one of claims 10 to 15, wherein the clock gate tree is a binary clock gate tree.

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