Micro-emitter display having a segmented backplane

Abstract

A display including rows that are divided into segments may result in shorter row conductors which can reduce the electrical loading associated with writing to a pixel, which can increase the speed that a pixel can display information. Further, the segmentation of the row lines of the display allows a controller to not address and write to pixels that do not contribute to an image for display.

Description

MICRO-EMITTER DISPLAY HAVING ASEGMENTED BACKPLANECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 519,043, filed on August 11, 2023, the disclosure of which is incorporated by reference herein in its entirety.FIELD OF THE DISCLOSURE

[0002] The present disclosure relates to a display and more specifically to a backplane for a display.BACKGROUND

[0003] A micro-emitter display includes pixels that have a switch for toggling the illumination ON / OFF at a high rate to encode a grayscale level onto the light emitted by the pixel. The pixel may further include a static random-access memory cell (i.e., SRAM) for each pixel that can hold the state of the switch to maintain the illumination of the pixel between the toggling. The memory cell for a pixel may be addressed by a backplane. The backplane can include a word-line corresponding to a row of the pixel and a bit-line corresponding to a column of the pixel.SUMMARY

[0004] In some aspects, the techniques described herein relate to a display including: a pixel array including: pixels arranged in rows and columns, each row divided into a plurality of segments; a plurality of bit-lines, wherein each bit-line is coupled to the pixels in a corresponding column; and a plurality of word-lines for each row, wherein each of the plurality of word-lines for each row is coupled to one of the plurality of segments of each row; and a display controller configured to write to a pixel of the pixel array based on a row, a segment, and a column of the pixel.

[0005] In some aspects, the techniques described herein relate to a method including: receiving an image at a display including pixels arranged in rows subdivided into a plurality of segments; designating at least one of the plurality of segments of a row as an active segment; transmitting a word-line signal to a respective word-line for each active segment ofthe row, coupling the pixels of each active segment to respective bit-lines based on the wordline signal; and controlling the pixels of each active segment based on image data received at the respective bit-lines corresponding to the image.

[0006] In some aspects, the techniques described herein relate to a display including: a pixel array including: pixels arranged in rows and columns, each row including a plurality of segments; and a display controller configured to: receive an image for display on the pixel array; generate a segment map of the pixel array based on the image, the segment map designating some segments of each row as active segments and other segments of each row as inactive segments; control the pixels in the active segments to display the image, while pixels in the inactive segments are not addressed to reduce a power consumed by the display.

[0007] The foregoing illustrative summary, as well as other exemplary objectives and / or advantages of the disclosure, and the manner in which the same are accomplished, are further explained within the following detailed description and its accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 illustrates a display according to a possible implementation of the present disclosure.

[0009] FIG. 2 illustrates a bit plane sequence according to a possible implementation of the present disclosure.

[0010] FIG. 3 illustrates a pixel for a display according to a possible implementation of the present disclosure.

[0011] FIG. 4 illustrates a display according to a possible implementation of the present disclosure.

[0012] FIG. 5 illustrates a display according to a possible implementation of the present disclosure.

[0013] FIG. 6 illustrates a display according to a possible implementation of the present disclosure.

[0014] FIG. 7 is a flowchart for a method for controlling pixels in a display according to a possible implementation of the present disclosure.

[0015] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.DETAILED DESCRIPTION

[0016] A micro-emitter display, such as a micro-light-emitting-diode display (i.e., microLED display), may include millions of pixels, each having dimensions that are a few micrometers (e.g., < 10 microns). The display may include pixels that are all configured to radiate light of the same color (e.g., red, green, blue, etc.). A pixel illumination may be controlled by the state of a 1 -bit memory cell associated with the pixel. Accordingly, the micro-emitter display may be referred to as a memory -in-pixel (MIP) display. When the memory cell stores a logical-high (i.e., 1), the pixel may be active (i.e., illuminated, lit) and when the memory element stores a logical-low (i.e. 0), the pixel may be inactive (i.e., not illuminated, dark).

[0017] The memory cell may be a static random-access memory cell (i.e., SRAM cell), and rendering an image on the display can include writing to an array of SRAM cells (i.e., SRAM). Accordingly, the micro-LED display may be referred to as an SRAM display. The SRAM display is well suited for a planar rendering (i.e., bit plane rendering), which decomposes a grayscale image into multiple binary images (i.e. bit planes), each written to the SRAM in rapid succession (e.g., faster than a flicker threshold of human perception).

[0018] An SRAM display may include more than a million pixels, which can require multiple millions of ON / OFF write operations per second for bit plane rendering of an image stream. A technical problem with an SRAM display of this size is that the relatively long connections (e.g., traces) used to address the SRAM cells, as well as the number of SRAM cells coupled to the traces, may electrically load a driver so that the ON / OFF control of the pixels is slower than desirable. The present disclosure describes an SRAM display that can reduce the electrical loading of each word-line (i.e., row) to increase the rate at which the SRAM cells of the display can be toggled during the rendering (e.g., bit plane rendering) of an image.

[0019] The overall power consumed by an SRAM display corresponds to the millions of ON / OFF write operations required to render an image. Another technical problem with the SRAM display (i.e., micro-LED display) is that the overall power consumed is too high for battery operation. For example, a head-mounted display (e.g., augmented reality (AR) glasses or AR goggles) can require battery operation of a display for, at least, several hours. The disclosed display addresses this technical problem by disabling pixels (i.e., SRAM cells) that are not required to display content to reduce the power consumed. One technical effect of this power reduction is extending the operating lifetime of a battery-operated device (e.g., AR glasses, AR goggles) using the display.

[0020] FIG. 1 is a schematic block diagram of a display according to a possible implementation of the present disclosure. The display 100 includes a plurality of pixels arranged in a 2D grid (i.e., pixel array 120). Each pixel 121 may be configured to generate light while conducting a drive current from a drive current module 140. Each pixel includes a memory cell (e.g., SRAM cell) for setting and maintaining the illumination state of a microLED as ON or OFF. The state of an SRAM cell of a pixel can be controlled (i.e., set / reset) by a signal (e.g., bit-line signal) transmitted over a column conductor (i.e., bit-line) coupled to the SRAM cell. The SRAM cell of the pixel is coupled to the bit-line based on a signal (e.g., word-line signal) transmitted over a row conductor (i.e., word-line) to the pixel. Accordingly, the display 100 further includes a word-line driver 112 configured to transmit a word-line signal to a word-line (i.e., row) of the pixel array 120. The word-line signal can activate a row so that each pixel in an active row is coupled to its respective bit-line.

[0021] As shown in FIG. 1, the display 100 further includes a bit-line driver 113 configured to transmit bit-line signals to the bit-lines of the pixels in an active row. The bit- line signals may change or maintain the state of the SRAM cells in the active row according to an image for display. In a possible implementation, a bit-line signal is a differential signal. In this case, each bit-line may include a positive bit-line (BL+) configured to carry a positive bit-line signal and a negative bit-line configured to carry a negative bit-line signal (BL-). In this differential configuration, the positive bit-line and the negative bit-line may be referred to collectively as the bit-line.

[0022] The display 100 further includes a controller 111 configured to control the operation of the word-line driver 112 and the bit-line driver 113. The controller 111 may be configured to address and write to the SRAMs of the pixel array so that the micro-LEDs illuminate to generate an image as a sequence of bit planes. Each bit plane may be rendered on the pixel array 120 on a row-by-row basis until every row necessary for rendering the image has been activated. For example, a word-line signal activates a row. After being activated, a bit-line signal for each pixel in the row controls the pixel ON / OFF according to the image data for the active row. The SRAM cell for each pixel in an inactive row can hold the pixels ON (illuminated) or OFF (not illuminated) while the other rows of the frame are activated. After writing a value to an SRAM cell (i.e., after a write operation), the SRAM cell can hold this value. As a result, updating the values in an SRAM display may only require a portion of the SRAM cells to change their state (i.e., flip) from a previous frame (i.e., bit plane).

[0023] Power is consumed by an SRAM display in a variety of ways. First, lit pixels may consume more power than dark pixels. Dark pixels may consume almost no power (e.g., zero power). Second, flipping of the state of the SRAM cell may consume more power than maintaining the state of the SRAM cell. Maintaining the state of the SRAM cell may consume almost no power (e.g., zero power). Third, addressing all the SRAM cells in the pixel array for rendering a frame may consume more power than addressing a portion of the SRAM cells in the pixel array. For example, the SRAM can be programmed by engaging all bit-lines (e.g., > 1000 bit-lines) at each frame. In this case, the power consumed by the logic and registers for programming corresponds to the entire pixel array even if only a small portion of the pixel array includes content. The SRAM display of the present disclosure can reduce this power by only addressing portions of the display that include content. The SRAM display of the present disclosure reduces the power consumed by the display by deactivating portions of the display that are not required. These portions can be reactivated whenever necessary so the power consumed by the display over time can be reduced without sacrificing the performance (e.g., viewing area) of the display.

[0024] FIG. 2 illustrates a bit plane sequence according to a possible implementation of the present disclosure. In this example, a grayscale image 200 has four pixels. Each pixel defines a location and a gray scale level. The gray scale level for each pixel in the grayscale image 200 may be represented as a binary image 201 that includes pixels with binary values corresponding to the grayscale levels. A number of bits of the binary values corresponds to a bit-depth of the binary image 201. A bit plane sequence 220 can be generated based on the binary image. Each bit plane in the bit plane sequence 220 includes pixels corresponding to the pixels of the binary image 201. In other words, each pixel of a bit plane corresponds to one bit of the binary value of a corresponding pixel in the binary image 201.

[0025] A first bit plane (MSB) of the bit plane sequence 220 of bit planes includes the most significant bit of the binary number. A last bit plane (LSB) of the bit plane sequence 220 of bit planes includes the least significant bit of the binary number. Rendering the grayscale image 200 may include writing each bit plane to the pixel array (i.e., SRAM) in succession.

[0026] The bit planes may be weighted and displayed in rapid succession so that a viewer sees the grayscale level for each pixel instead of the binary values. The weighting of the bit planes may be carried out by adjusting the ON light levels of each bit plane, which can be managed using pulse width modulation (PWM). For example, a 1 -bit in the MSB bitplane may be weighted higher (e.g., generate brighter light) than a 1 -bit of the LSB bitplane.Alternatively, the weighting of the bit planes may be carried out by adjusting how long each bit plane in the bit plane sequence 220 is displayed. For example, a 1 -bit in the MSB bitplane may be displayed longer in the bit plane sequence 220 than a 1 -bit of the LSB bitplane.

[0027] FIG. 3 illustrates a pixel for a display according to a possible implementation of the present disclosure. As shown in FIG. 3, the pixel 300 includes a switch 320 coupled between a micro-LED 310 and the drive current module 140. The switch 320 can be in a short circuit state (i.e., ON-condition) so that the micro-LED 310 is illuminated (i.e., generates light) by the current of the drive current module 140. Alternatively, the switch 320 can be in an open circuit state (i.e., OFF-condition) so that the micro-LED 310 is dark because it receives no current.

[0028] As shown in FIG. 3, the switch 320 can be controlled ON or OFF according to the state (i.e., the stored value) of an SRAM cell 350. The SRAM cell 350 receives power for operation from a power supply 311 which is coupled to each pixel of the pixel array 120. The SRAM cell 350 may be configured to output a HIGH voltage (e.g., VDD) while in a HIGH state (i.e., ON-state) or output a LOW voltage (e.g., ground 312) while in a LOW state (i.e., OFF-state). An advantage of using an SRAM cell 350 to control the switch 320 is that while the SRAM cell 350 is in the HIGH-state (i.e., ON-state) or the LOW-state (i.e., OFF- state) it consumes very little current (e.g., approximately zero current) from the power supply 311. The SRAM cell 350 draws current (e.g., a shoot-through current) as it is transitioned (i.e., is flipped) between states during a write operation.

[0029] As shown in FIG. 3, the SRAM cell 350 includes two inverters (i.e., a pair of inverters) coupled in parallel with their polarities reversed (i.e., coupled output to input). The pair of inverters function as a digital latch circuit (i.e., latch 313). A write operation (i.e., write process) configures the latch 313 into one of two states: an ON-state to output a signal corresponding to a logical HIGH (i.e., 1) and an OFF-state to output a signal corresponding to a logical LOW (i.e., 0).

[0030] As shown in FIG. 3, the pixel 300 further includes a bit-line 315, and the state of the SRAM cell 350 may be set / reset by bit-line signals (BL+, BL-) applied to the bit-line 315. During the write operation, the signals (BL+, BL-) are set to assert the desired state onto the latch 313. Once the desired state is set and the output of the latch 313 is stable, the signals (BL+, BL-) may be removed.

[0031] As shown in FIG. 3, the pixel 300 further includes a word-line 314. During the write operation, the latch circuit is coupled to the positive / negative signals of the bit-line 315 by switches controlled by a word-line signal (WL) transmitted on a word-line 314. Forexample, a first level (e.g., HIGH) on the word-line 314 turns the switches ON to couple the input / output of latch 313 to respective positive / negative lines of the bit-line 315. The wordline 314 may be coupled to other pixels in a row of pixels in the pixel array 120. A second level (e.g., LOW) on the word-line 314 turns the switches OFF to decouple the input / output of the latch 313 from the bit-line drivers so that the state is stored. The state of the SRAM cell 350 can appear as a voltage at the output of one of the inverters of the latch 313. The voltage at the output can be toggled between a high level (i.e., HIGH) and a low level (i.e., LOW) according to a pulse width modulation signal (i.e. PWM signal 301). A perceived intensity of light from the micro-LED 310 may correspond to a duty cycle of the PWM signal 301.

[0032] Changing the state of the latch (i.e., flipping the latch) can include changing the ON / OFF condition of the transistors in each inverter. While the transistors are changing, a low-resistance path to ground 312 may be created, and a shoot-through current may flow from the power supply 311 to the SRAM cell 350 until the transition is completed. This shoot-through current may be relatively large and contributes to the power consumed by the write operation.

[0033] FIG. 4 is a display according to a possible implementation of the present disclosure. The display 400 includes a pixel array 420. The pixel array 420 includes pixels (e.g., see FIG. 3) arranged in rows and columns. The pixel array 420 further includes a plurality of bit-lines. Each bit-line is coupled to the pixels of a column. The pixel array 420 further includes a plurality of word-lines. Each word-line is coupled to the pixels in a row.

[0034] The display 400 further includes a bit plane sequencer 410. The bit plane sequencer 410 is configured to receive an image for display on the pixel array 420. The image (e.g., grayscale image) may include, but is not limited to, pictures, text, icons, and the like. The image may include portions (e.g., dark portions, dark areas) that do not contain any relevant visual information (e.g., no information).

[0035] The bit plane sequencer 410 is configured to output an image (i.e., bit plane 412) based on the grayscale image 411 received at the input. The bit plane sequencer may be configured to output a sequence of bit planes (i.e., bit plane sequence 220) as shown and discussed in conjunction with FIG. 2. Like the grayscale image 411, the bit plane 412 may include portions (e.g., dark portions, dark areas) that do not contain any relevant visual information (e.g., no information). What is more, these portions may be present in all bit planes of a sequence of bit planes.

[0036] As shown in FIG. 4, the grayscale image 411 includes a dark border (i.e., border) surrounding a picture. Because there is no visual information in the border, pixels in these areas can be ignored during the rendering process (assuming that the pixels in these areas are OFF by default). In other words, the size of the display can be functionally reduced to roughly match the size of the picture. The reduction can decrease the amount of power required to display the image by reducing the amount of buffering and switching required to carry out the write operations to render the picture on the display. The amount of reduction may change based on each image rendered. Some images may require the entire area of the pixel array 420. For these images no power savings based on the reduction may be achieved. On average, however, power savings will be achieved because many images displayed will only require a portion of the entire area.

[0037] The display 400 further includes a display controller 440 (i.e., controller) configured to generate write operations to render the grayscale image 411 on the display. A write operation can include addressing the pixels of the pixel array 420 by rows and columns. The disclosed display can further address the pixels by segment. Each row of the pixel array 420 can be subdivided into a plurality of segments 421. As a result, the display controller 440 may be configured to write to a pixel of the pixel array based on its column, its row, and its segment within the row.

[0038] In a possible implementation, each segment in a row includes the same number of pixels (i.e., the segments are the same size). In another possible implementation, the segments in a row are different sizes. In another possible implementation, one or more segments in a row are the same size and one or more of the segments in the row are different sizes.

[0039] In a possible implementation each row of the pixel array 420 includes the same number of segments. In another possible implementation the number of segments in the rows are different. In another possible implementation, one or more rows of the pixel array 420 have the same number of segments and one or more rows of the pixel array 420 have a different number of segments.

[0040] In a possible implementation, a first portion of the rows of the pixel array 420 include segments and a second portion of the rows of the pixel array 420 do not include segments. In another possible implementation, the first portion and the second portion define areas on the pixel array. In a possible implementation, the first portion and the second portion are interleaving rows.

[0041] The choices of which rows to segment and how many segments should each row have may be based on the application of the display. For example, it may be desirable to segment a first region (e.g., bottom portion) of the pixel array 420 that is commonly used for text and icons and not segment a second region (e.g., middle portion) of the pixel array 420 that is commonly used for video and pictures. The number of segments in the display may be based on a balance between power savings and circuit complexity. Inactive segments consume less power than active segments so that a power consumed by the display is reduced based on the inactive segments

[0042] The display controller 440 may be configured to designate the plurality of segments for each row as active segments or inactive segments based on the image received for display. Pixels (i.e., SRAM cells) in active segments are written to, while pixels (i.e., SRAM cells) in inactive segments are not written to.

[0043] The display controller 440 can be configured to generate a segment map 450 that designates active and inactive segments for each row of the pixel array 420. The segment map 450 further maps each pixel to one of the active segments or inactive segments. For example, the segment map may be an array of binary values for each pixel based on the row, segment, and column of the pixel. The value (e.g., 0, 1) of the binary number for each pixel corresponds to the active / inactive status of the pixel, which can be determined based on the visual information in the image. In other words, the segment map may designate active segments and inactive segments row by row.

[0044] The display controller 440 is further configured to write to a pixel (i.e., SRAM cell) of the pixel array 420 to render a corresponding pixel in the grayscale image 411. To write to the pixel array 420, the display controller 440 may be configured to transmit a wordline signal to a row decoder 430 of the display 400 in order to activate a row of the pixel array 420. In a possible implementation, the row decoder 430 is configured to route the word-line signal to the proper row based on an address 431 that can include a first identifier corresponding to an active row. When the row is divided into a plurality of segments, the address 431 can further includes a second identifier corresponding to an active segment (or active segments) of the active row.

[0045] The display 400 further includes a row decoder 430 configured to route a wordline signal to a particular pixel based on an address 431 (i.e., index) received from the display controller with the word-line signal. The address 431 may include the active row and the active segment of the particular pixel. The word-line signal is configured to couple the particular pixel of the active segment to a corresponding bit-line. Word-line signals are nottransmitted to inactive segments of the active row. Not transmitting the word-line signal can reduce the power consumed by the display. This process may be repeated row-by-row until all rows have been addressed (i.e., have been activated).

[0046] The display 400 further includes a column decoder 436 configured to route image data (e.g., bitplane data) to the appropriate columns of an active row. The column decoder 436 may be configured to only route the image data to active segments of the active row. In other words, the column decoder 436 may ignore columns of pixels in inactive segments. Eliminating the logic and registers required to route image data, which carries no visual information, to inactive segments can reduce the power consumed by the display. The display 400 may include a buffer (not shown) between the display controller 440 and the column decoder 436 to provide the proper timing between a row activation and routing of image data.

[0047] The column decoder 436 can be coupled to a bit-line driver 435 of the row decoder 430. The bit-line driver 435 may include an amplifier for each column of the display. The amplifiers may buffer the digital logic and circuitry of the column decoder from the SRAM cells of the pixel array 420, which can draw a relatively high amount of power during a write operation. The amplifiers of the bit-line driver 435 are configured to supply the current necessary to flip the state of the latch in the SRAM cell, which was described in conjunction with FIG. 3. The amplifiers for columns of inactive segments may be deactivated to further save power. Accordingly, in a possible implementation the bit-line driver 435 may be subdivided into a plurality of bit-line drivers, each corresponding to a segment of the pixel array 420, so that bit-line drivers corresponding to inactive segments may be deactivated to save power.

[0048] FIG. 5 illustrates a display according to a possible implementation of the present disclosure. A backplane of the display includes conductors arranged in rows and columns that are coupled to pixels of the display (e.g., via transistors). The pixels of the display 500 can be micro-emitters (e.g., micro-LEDs) which can be controlled according to a segmented backplane (i.e., segmented rows). The pixels are arranged into segments based on their location in the pixel array 520. As shown, the pixel array 520 includes a first segment 521, a second segment 522, and a third segment 523. Pixels of a row can be addressed by their row and their segment. Each segment of a row is coupled to a corresponding word line (i.e., segment word-line). As shown, an Nth row 510 of the pixel array 520 includes a first word line 531 coupled to pixels in the first segment 521, a second word line 532 coupled to pixels in the second segment 522, and a third word-line 533 coupled to pixels in the third segment523. When activating the Nth row of a frame, the display controller 440 may transmit a word-line signal to the first word line 531 (e.g., based on an address) to activate the pixels in the first segment 521. The display controller 440 may transmit the word-line signal to the second word line 532 (e.g., based on an address) to activate the pixels in the second segment 522 of the nth row 510. The display controller 440 may transmit the word-line signal to the third segment 523 (e.g., based on an address) to activate the pixels in the third segment 523 of the nth row 510. The word-line signal transmitted to each segment may be the same and the transmission of the word-line signals to the segments may occur at approximately the same time (e.g., simultaneously). When a segment is determined to be inactive (e.g., based on the segment map 450), the display controller 440 may be configured to not transmit a word-line signal to its corresponding word line of the inactive segment.

[0049] The active segments for rows may be the same or different. For example, a first row may have an active first segment 521, an inactive second segment 522, and an inactive third segment 523, while a second row may have an inactive first segment 521, an active second segment 522, and an active third segment 523. The segment map 450 may define active segments for each row of the pixel array 520 (e.g., in a lookup table). Likewise, the segment map 450 may define inactive segments for each row of the pixel array 520.

[0050] The display 500 may include a plurality of bit-line drivers. As shown, the display 500 may include a first bit-line driver 541 corresponding to the first segment 521, a second bit-line dnver 542 corresponding to the second segment 522, and a third bit-line driver 543 coupled to the third segment 523. In a possible implementation, the bit-line drivers may be enabled or disabled based on the active segments for the particular row being addressed. To continue the example presented above, the first row may enable the first bit-line driver 541, disable the second bit-line driver 542, and disable the third bit-line driver 543, while the second row may disable the first bit-line driver 541, enable the second bit-line driver 542, and enable the third bit-line driver 543.

[0051] The backplane of the display, including row conductors, column conductors, pixels, and associated coupling electronics, may be segmented physically, with each segment of a row having its own word line. The backplane of the display may also be segmented logically. For example, logic circuits (e.g., shift registers, buffers, etc.) can be configured to activate pixels of a row in groups (i.e., segments).

[0052] Dedicated word lines for each segment may reduce the circuit loading (e.g., parasitic capacitance) associated with each word line. The reduced loading may result from a reduced length of segment word-line and / or the reduced number of pixels coupled to thesegment word-line. The reduced circuit loading may result in a faster activation of pixels because a distortion (e.g., low pass filtering) caused by the circuit loading (e.g., parasitic capacitance) is reduced.

[0053] A pixel array may include any number of segments (e.g., 6, 12, etc.). Increasing the number of segments may provide more resolution at which the pixel array may be adjusted to conserve power. When the number of segments is high (e.g., > 6), the advantage of circuit loading may be diminished because the length of a line (i.e., trace) between the row decoder and segment becomes large and / or because the separation between lines becomes small.

[0054] FIG. 6 illustrates a display according to a possible implementation of the present disclosure. The display 600 includes a first segment 621, a second segment 622, a third segment 623, a fourth segment 624, a fifth segment 625, and a six segment 626. The segments may be further designated as being in a left segment group 641 or a right segment group 642. As shown, the first segment 621, the second segment 622, and the third segment 623 are in the left segment group 641 and the fourth segment 624, the fifth segment 625, and the six segment 626 are in the right segment group 642.

[0055] The display 600 includes a left row decoder 611 configured to address pixels in the left segment group 641. Rows in the left segment group 641 have segmented word-lines coupled to the left row decoder 611. The display 600 includes a right row decoder 612 configured to address pixels in the right segment group 642. Rows in the left segment group 641 have word-lines for segments coupled to the left row decoder 611. For example, a first word-line 651 is coupled between the first segment 621 and the left row decoder 611; a second word-line 652 is coupled between the second segment 622 and the left row decoder 611; and a third word-line 653 is coupled between the third segment 623 and the left row decoder 611. Rows in the right segment group 642 have word-lines for segments coupled to the right row decoder 612. For example, a fourth word-line 654 is coupled between the fourth segment 624 and the right row decoder 612; a fifth word-line 655 is coupled between the fifth segment 625 and the right row decoder 612; and a sixth word-line 656 is coupled between the six segment 626 and the right row decoder 612.

[0056] In a possible implementation, the display controller 440 may be configured to address write-signals to the left row decoder 611 or the right row decoder 612 based on an address 631 that includes the row, the segment, and the segment group (i.e. L / R). A segment map 550 may map active pixels and / or inactive pixels based on their row, segment, andsegment group. In a possible implementation, the display 600 can further include a bit-line driver 540, which includes an amplifier 661 for each column (i.e. bit line).

[0057] FIG. 7 is a method for controlling pixels in a display according to a possible implementation of the present disclosure. Some operations of the method may be executed according to computer readable instructions stored in a non-transitory computer readable memory. For example, the instructions may be stored and executed by the display controller 440. The method 700 includes receiving 710 an image (e.g., bitplane) at the display. The display includes pixels arranged in rows that are subdivided into a plurality of segments, each having their own word-line. The method 700 further includes transmitting 720 image data for a row (i.e., the active row) to the appropriate columns of the display (e.g., via the column decoder). The method 700 further includes designating 730 at least one of the segments of a row as an active segment. The method 700 further includes transmitting 740 a word-line signal to a respective word-line for each active segment of the row (e.g., via the row decoder). The method 700 further includes coupling 750 (in response to the word-line signal) the pixels of each active segment to respective bit-lines based on the word-line signal. The method 700 further includes controlling 760 the pixels of each active segment based on image data received at the respective bit-lines. The method 700 may then shift rows and transmit 720 image data for the new row to the appropriate columns of the display.

[0058] In the specification and / or figures, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term “and / or” includes any and all combinations of one or more of the associated listed items. The figures are schematic representations and so are not necessarily drawn to scale. Unless otherwise noted, specific terms have been used in a generic and descriptive sense and not for purposes of limitation.

[0059] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification, and in the appended claims, the singular forms “a,” “an,” “the” include plural referents unless the context clearly dictates otherwise. The term “comprising” and variations thereof as used herein is used synonymously with the term “including” and variations thereof and are open, non-limiting terms. The terms “optional” or “optionally” used herein mean that the subsequently- described feature, event or circumstance may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where itdoes not. Ranges may be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, an aspect includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

[0060] Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and / or so forth.

[0061] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or sub-combinations of the functions, components and / or features of the different implementations described.

[0062] It will be understood that, in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element, there are no intervening elements present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application, if any, may be amended to recite exemplary relationships described in the specification or shown in the figures.

[0063] As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g.,over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

Claims

WHAT IS CLAIMED IS:

1. A display comprising: a pixel array including: pixels arranged in rows and columns, each row divided into a plurality of segments; a plurality of bit-lines, wherein each bit-line is coupled to the pixels in a corresponding column; and a plurality of word-lines for each row, wherein each of the plurality of word-lines for each row is coupled to one of the plurality of segments of each row; and a display controller configured to write to a pixel of the pixel array based on a row, a segment, and a column of the pixel.

2. The display according to claim 1, wherein the display controller is further configured to: designate the plurality of segments for each row as active segments or inactive segments based on an image.

3. The display according to claim 2, wherein the display controller is configured to: write to the pixels in the active segments; and not write to the pixels in the inactive segments.

4. The display according to claim 2 or 3, wherein the display controller is further configured to: receive the image; generate a segment map indicating: segments that require a write operation to display the image; and segments that do not required the write operation to display the image; and designating the active segments and the inactive segments, row by row, based on the segment map.

5. The display according to any one of claims 2 to 4, further comprising: a bit plane sequencer configured to output a bit plane based of the image received at the display.

6. The display according to claim 5, wherein the display controller is further configured to: receive the bit plane; generate a segment map indicating: segments that require a write operation to display the bit plane; and segments that do not required the write operation to display the bit plane; and designating the active segments and the inactive segments, row by row, based on the segment map.

7. The display according to claim 5 or 6, wherein the active segments and the inactive segments of each row change for each image displayed.

8. The display according to any one of claims 2 to 7, wherein the inactive segments consume less power than the active segments so that a power consumed by the display is reduced based on the inactive segments.

9. The display according to any one of claims 2 to 8, wherein the pixels each include: a micro-LED; and a static random access memory (SRAM) cell, wherein an ON / OFF state of the micro- LED is based on a state of the SRAM cell.

10. The display according to any one of claims 2 to 9, further comprising: a row decoder configured to route a word-line signal to a particular pixel based on an address received from the display controller, the address including an active row and an active segment of the particular pixel, the word-line signal coupling the particular pixel to a corresponding bit-line; and a column decoder configured to route image data for the particular pixel to the corresponding bit-line.

11. The display according to claim 10, wherein the row decoder is a first row decoder on a first side of the display and wherein the display further includes: a second row decoder on a second side of the display, the second side opposite the first side;the first row decoder is coupled to a first group of segments closest to the first row decoder; and the second row decoder is coupled to a second group of segments closest to the second row decoder.

12. A method comprising: receiving an image at a display including pixels arranged in rows subdivided into a plurality of segments; designating at least one of the plurality of segments of a row as an active segment; transmitting a word-line signal to a respective word-line for each active segment of the row, coupling the pixels of each active segment to respective bit-lines based on the word-line signal; and controlling the pixels of each active segment based on image data received at the respective bit-lines corresponding to the image.

13. The method according to claim 12, wherein designating at least one of the plurality of segments of the row as an active segment includes: determining which pixels require a write operation to display the image; and determining which segments correspond to the pixels determined to require the write operation.

14. The method according to claim 12 or 13, further comprising: designating at least one of the plurality of segments of the row as an inactive segment; not transmitting the word-line signal to the respective word-line for each inactive segment of the row; and not controlling the pixels of each inactive segment to reduce a power consumed by the display.

15. The method according to claim 14, wherein designating at least one of the plurality of segments of the row as inactive includes: determining which pixels do not require a write operation to display the image; and determining which segments correspond to the pixels determined to not require the write operation.

16. The method according to any one of claims 12 to 15, further comprising: receiving the image data for each row of the display; and repeating, for each row, the designating, transmitting, coupling, and controlling for each row to display the image.

17. The method according to any one of claims 12 to 16, wherein: the image data corresponds binary values of a bit plane; and each pixel of each active segment is controlled ON / OFF according to the binary values for the row of the bit plane.

18. The method according to claim 17, wherein the display is a micro-LED display configured to display the image as a sequence of bit planes.

19. A display comprising: a pixel array including: pixels arranged in rows and columns, each row including a plurality of segments; and a display controller configured to: receive an image for display on the pixel array; generate a segment map of the pixel array based on the image, the segment map designating some segments of each row as active segments and other segments of each row as inactive segments; and control the pixels in the active segments to display the image, while pixels in the inactive segments are not addressed to reduce a power consumed by the display.

20. The display according to claim 19, wherein the display is a static random access memory (SRAM) display configured to display the image as a sequence of bit planes.

Images