Heterogeneous hardware emulation method and system

Abstract

The present invention relates to the technical field of chip verification, and in particular to a heterogeneous hardware emulation method and system. Microprocessors and FPGA chips are interconnected. The microprocessors have higher compiling speed than the FPGAs and lower emulation performance than the FPGA chips. Integrated circuit design is divided to the multiple microprocessors and FPGA chips by means of a system compiler. Autonomous design modules D to be debugged and corrected in the integrated circuit design are divided to the microprocessors, physical interconnection links are allocated to the microprocessors and the FPGAs after dividing, the microprocessors and the FPGAs are respectively compiled and executable files are generated, and then collaborative emulation is performed. The compiling speed of the microprocessors where said autonomous design modules are located is higher than the compiling speed of the FPGA chips. Moreover, it is guaranteed that mature design modules in the FPGA chips have high emulation performance, and the advantages of the iteration speed of the microprocessors and the emulation performance of the FPGAs are fused.

Description

A heterogeneous hardware simulation method and system Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a heterogeneous hardware simulation method and system. Background Art

[0002] Chip design, also known as integrated circuit design (IC design), refers to the design process targeting integrated circuits and very large-scale integrated circuits. Chip design generally uses hardware description languages ​​such as Verilog, System Verilog, and VHDL, which describe the structure and behavior of digital system hardware in text form. After the chip design is completed, it enters the tape-out phase. If a critical problem occurs in the chip design, the tape-out will fail, and the cost of tape-out failure is very high. To reduce the risk of tape-out failure, the chip design must be fully verified before tape-out to promptly identify problems in the chip design and adjust the chip design to ensure a smooth tape-out.

[0003] Verification of digital chip logic functions involves both software simulation and hardware emulation. Hardware emulator architectures include field programmable gate arrays (FPGAs) and microprocessors. During hardware emulation, the FPGA compilation process is time-consuming and has a low compilation iteration speed, but offers good simulation performance. Microprocessors, on the other hand, offer high compilation iteration speeds but relatively poor simulation performance. Currently, no hardware emulator offers a balance of simulation performance and iteration speed. Therefore, effectively partitioning the IC design between the FPGA and microprocessor to leverage the strengths of each hardware emulator has become a pressing technical challenge.

[0004] Summary of the Invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is:

[0006] In a first aspect, an embodiment of the present invention provides a heterogeneous hardware emulation method, the method comprising:

[0007] S200, obtain an interconnected hardware emulator Emu and K memories, wherein Emu includes N microprocessors and M FPGA chips, the compilation speed of the microprocessor is greater than that of the FPGA chip and the simulation performance is lower than that of the FPGA chip, and L physical interconnection links are included between the N microprocessors, M FPGA chips and K memories, where K≥0, N≥1, M≥1, and L≥1.

[0008] S400: Obtain a chip design DUT, where the DUT includes an independently designed module D to be debugged and modified.

[0009] S600: The system compiler processes the DUT to obtain n first-class executable files corresponding to n microprocessors in Emu and m second-class executable files corresponding to m FPGA chips, where 0 < n ≤ N and 0 < m ≤ M; including:

[0010] S620, divide the DUT into n microprocessors and m FPGA chips respectively, where D is divided into the microprocessor, to obtain the first type design modules of n microprocessors and the second type design modules of m FPGA chips; where 0<n≤N and 0<m≤M.

[0011] S640 , allocating physical interconnection links for transmission signals between the n first-category design modules and the m second-category design modules, to obtain signal transmission configuration modules for the n first-category design modules and signal transmission configuration modules for the m second-category design modules.

[0012] S660, compile and generate the first type executable file of the microprocessor according to each first type design module and its signal transmission configuration module, and obtain n first type executable files; compile and generate the second type executable file of the FPGA chip according to each second type design module and its signal transmission configuration module, and obtain m second type executable files.

[0013] S800: Store n first-category executable files in n microprocessors respectively, store m second-category executable files in m FPGA chips respectively, and control the n microprocessors and m FPGA chips through the first-category executable files and the second-category executable files to perform collaborative simulation and debugging.

[0014] In a second aspect, an embodiment of the present invention provides a heterogeneous hardware simulation system, the system including an interconnected hardware simulator Emu, K memories, and a system compiler, the Emu including N microprocessors and M FPGA chips, the compilation speed of the microprocessor being greater than that of the FPGA chip and the simulation performance being lower than that of the FPGA chip, the N microprocessors, the M FPGA chips, and the K memories including L physical interconnection links, where K ≥ 0, N ≥ 1, M ≥ 1, and L ≥ 1; the system compiler including a divider, a router, n microprocessor compilers, and m FPGA chip compilers, 0 < n ≤ N and 0 < m ≤ M; wherein:

[0015] A divider is used to divide the chip design DUT into n microprocessors and m FPGA chips, wherein the DUT includes an independent design module D to be debugged and corrected, and D is divided into the microprocessor to obtain the first type of design modules of n microprocessors and the second type of design modules of m FPGA chips.

[0016] The router is used to allocate physical interconnection links for transmission signals between n first-type design modules and m second-type design modules, thereby obtaining signal transmission configuration modules for n first-type design modules and signal transmission configuration modules for m second-type design modules.

[0017] The microprocessor compiler is used for compiling and generating a first type of executable file of the microprocessor according to the first type of design module and its signal transmission configuration module.

[0018] The FPGA chip compiler is used to compile and generate the second type of executable file of the FPGA chip according to the second type of design module and its signal transmission configuration module.

[0019] The server is used to store n first-category executable files in n microprocessors respectively, store m second-category executable files in m FPGA chips respectively, and control the n microprocessors and m FPGA chips for collaborative simulation and debugging through the first-category executable files and the second-category executable files.

[0020] Compared with the prior art, the present invention has significant advantages. By means of the above technical solution, the heterogeneous hardware simulation method and system provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following advantages:

[0021] The present invention provides a heterogeneous hardware simulation method and system. This method interconnects a microprocessor and an FPGA chip to form a heterogeneous system. Using a system compiler, the chip design is partitioned into multiple microprocessors and FPGA chips. Specifically, the independently designed module D in the chip design, which is to be debugged and corrected, is partitioned into the microprocessor. These modules are then compiled into executable files and then co-simulated. Compared to using only an FPGA or a microprocessor as a hardware emulator, the present invention achieves a simulation iteration speed equivalent to that of the microprocessor, achieving simulation performance close to that of an FPGA. Thus, the present invention combines the advantages of both the microprocessor iteration speed and the FPGA simulation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] FIG1 is a flow chart of a heterogeneous hardware simulation method provided by an embodiment of the present invention;

[0024] FIG2 is a block diagram of a system compiler in a heterogeneous hardware simulation system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0026] Hardware emulators consist of FPGAs (Field Programmable Gate Arrays) and microprocessors. FPGAs don't require software to simulate circuit behavior, but instead directly perform simulation tasks, resulting in superior simulation performance. Placement and routing is a crucial step in the compilation process, determining the physical layout and electrical connections of the logic circuit on the FPGA. However, due to the extensive optimization and constraint setting required during placement and routing, the process is time-consuming, leading to long FPGA compilation times and slow iteration speeds. If a bug in the chip design is encountered during simulation, the FPGA must recompile the modified chip design each time a bug is corrected. This results in lengthy compilation times, slow iteration speeds, and limited debugging usability. The microprocessor does not require layout and routing, and the iteration speed of direct compilation is fast. However, its simulation performance is lower than that of FPGA. In the process of simulation and debugging of IC design, in order to combine the advantages of simulation performance and iteration speed, the present invention combines FPGA and microprocessor, divides the independent design modules that need to be debugged and corrected in the chip design into the microprocessor, and mainly divides the mature design modules in the chip design into FPGA. Then, each FPGA and microprocessor are compiled separately and the corresponding executable files are generated. The executable files are used to control the FPGA and microprocessor for joint simulation. When the independent design module needs to be debugged, the chip design corresponding to the modified part is recompiled, and the compilation speed is greatly improved compared with FPGA. At the same time, in subsequent simulations, the mature design module can give full play to the simulation performance advantages of FPGA, thus combining the advantages of simulation performance and iteration speed.

[0027] Please refer to FIG1 , which shows a flow chart of a heterogeneous hardware simulation method provided by an embodiment of the present invention. The method includes the following steps:

[0028] S200, obtain an interconnected hardware emulator Emu and K memories, wherein Emu includes N microprocessors and M FPGA chips, the compilation speed of the microprocessor is greater than that of the FPGA chip and the simulation performance is lower than that of the FPGA chip, and L physical interconnection links are included between the N microprocessors, M FPGA chips and K memories, where K≥0, N≥1, M≥1, and L≥1.

[0029] Optionally, the microprocessor is a Boolean microprocessor or a multi-core processor. Any microprocessor in the prior art that can be used for hardware simulation and has a compilation speed greater than that of an FPGA falls within the scope of protection of the present invention. Preferably, the microprocessor is a Boolean processor. It should be noted that a Boolean processor is a microprocessor specifically used to process Boolean operations, wherein Boolean operations include AND, OR, and NOT operations. In the process of compiling and generating an executable file, a Boolean processor does not require a layout and routing process. Its compilation speed is faster than that of an FPGA, and its debugging ease is high.

[0030] The memory is used to support memory (memories) in debugging or emulating chip design. Optionally, the memory is a random access memory (RAM). Further, the memory is a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0031] The N microprocessors, M FPGA chips, and K memories include multiple physical interconnect links, each of which is an interconnect channel. In the interconnect structure, the uth memory is simultaneously connected to f1 microprocessors and f2 FPGA chips, where f1 and f2 are both greater than or equal to 0.

[0032] S400: Obtain a chip design DUT (Design under Test), which includes an independently designed module D to be debugged and revised. The chip design DUT is the RTL code for the chip design and includes both the independently designed module D and a mature design module P. The independently designed module D to be debugged and revised is a user-designed module that requires focused debugging and is specified by the user. The mature design P is a circuit module that has been repeatedly verified and does not require extensive modification or adjustment, such as an IP core or a previously verified, mature circuit module.

[0033] S600: The system compiler processes the DUT to obtain n first-class executable files corresponding to n microprocessors and m second-class executable files corresponding to m FPGA chips in Emu, where 0 < n ≤ N and 0 < m ≤ M. The executable files are binary codes.

[0034] Furthermore, the steps of processing the DUT by the system compiler include:

[0035] S620 , divide the DUT into n microprocessors and m FPGA chips respectively, wherein D is divided into the microprocessor, thereby obtaining the first type of design modules of the n microprocessors and the second type of design modules of the m FPGA chips.

[0036] For the convenience of description, FPGA chips and microprocessors are collectively referred to as hardware emulators and will not be further stated below.

[0037] It should be noted that the scale of chip design DUT is generally large, and the hardware resources of a single hardware simulator are limited. One hardware simulator cannot accommodate the entire chip design. Therefore, the chip design DUT needs to be divided into n+m design modules, and each design module is used to be implemented on the corresponding hardware simulator.

[0038] Among them, the independently designed module D requires significant debugging and revision, requiring multiple recompilations. Therefore, it is assigned to the microprocessor, which accelerates compilation during simulation and improves simulation efficiency. Furthermore, when D needs to be recompiled, this also speeds up recompilation, improving overall simulation efficiency. Mature design modules other than the independently designed module require less significant debugging and revision, prioritizing simulation and avoiding multiple recompilations. Therefore, assigning these mature design modules primarily to the FPGA results in better simulation performance.

[0039] Optionally, the division step includes: marking the independent design module D as a first type of label and marking the mature design module P as a second type of label, assigning the chip design with the first type of label to the microprocessor, and assigning the chip design with the second type of label to the FPGA.

[0040] S640 allocates physical interconnection links for transmission signals between n first-category design modules and m second-category design modules, obtaining signal transmission configuration modules for n first-category design modules and m second-category design modules. Routing algorithms can be used to allocate physical interconnection links for data transmission and communication between hardware emulators. Routing algorithms known in the prior art fall within the scope of protection of the present invention. It should be noted that the signal transmission configuration module stores the mapping between transmission signals and physical interconnection links in the corresponding first-category design modules.

[0041] S660: Compile each first-category design module and its signal transmission configuration module to generate a first-category executable file for the microprocessor, thereby obtaining n first-category executable files. Compile each second-category design module and its signal transmission configuration module to generate a second-category executable file for the FPGA chip, thereby obtaining m second-category executable files. It should be noted that the executable files are binary files.

[0042] S800: Store n first-category executable files in n microprocessors respectively, store m second-category executable files in m FPGA chips respectively, and control the n microprocessors and m FPGA chips through the first-category executable files and the second-category executable files to perform collaborative simulation and debugging.

[0043] Regarding the iteration speed of hardware simulation, the present invention divides the independent design module into the microprocessor. When debugging and modifying the independent design module, only the microprocessor needs to be recompiled, and the iteration speed of the entire system is equal to the iteration speed of the microprocessor. If the DUT is divided into the FPGA, the iteration speed of the entire system is equal to the iteration speed of the FPGA. Since the iteration speed of the microprocessor is greater than the iteration speed of the FPGA, the present invention improves the iteration speed of the entire system. For example, for a design module, the compilation time of an FPGA is 26 hours, and the compilation time of a microprocessor is 6 hours. If the DUT is divided into the FPGA, the compilation time of the system is 26 hours; if the present invention is adopted, the compilation time is 6 hours, so the iteration speed is improved compared to dividing the DUT into the FPGA.

[0044] For hardware simulation performance, the parts that need to be frequently modified account for a small proportion, and the mature designs with a higher proportion are simulated in FPGA. The simulation performance of FPGA is higher than that of microprocessors, so the simulation performance of the entire system is close to that of FPGA.

[0045] Therefore, the present invention divides the independent design module into the microprocessor and divides the mature design into the FPGA. Compared with using only FPGA or microprocessor as hardware emulator, it can make the simulation iteration speed equivalent to the iteration speed of the microprocessor and integrate the simulation performance into the simulation performance close to that of FPGA. Therefore, the present invention takes into account the advantages of both the iteration speed of the microprocessor and the simulation performance of FPGA.

[0046] As a preferred embodiment, S600 further includes: S630, optimizing the number of physical interconnection links between the microprocessors.

[0047] Furthermore, S630 includes the following steps:

[0048] S632, respectively obtain the first type of design modules B allocated to the j-th microprocessor j and the second type of design module F allocated to the i-th FPGA chip i , B j Include submodule D of D j; Wherein, the value range of j is 1 to n, and the value range of i is 1 to m. When the divider divides the modules, it will give priority to dividing D into the same microprocessor; when the microprocessor cannot accommodate the entire D, the divider will divide D into multiple submodules and divide them into multiple microprocessors respectively, where the submodule D j The first type of design module B is assigned to the jth microprocessor j .

[0049] S634, get F i Middle and D j Q connected elements cell={cell1,cell2,…,cell q ,…,cell Q}, cell q F i Middle and D j The qth element across the chip, where q ranges from 1 to Q. It should be noted that the element can be a sequential unit, such as a register, a flip-flop, or a latch, or a combinational logic unit, such as a gated clock.

[0050] S636, respectively obtain each element in the cell and D j Number of connected lines Sum1 i and each element in F i The number of connections within Sum2 i , among which, cell q With D j Number of connected lines Sum1 i,q , cell q In F i The number of connections in Sum2 i,q .

[0051] S638, when Sum1 i,q Greater than Sum2 i,q When the cell q Reassign to B j Inside. q Reassign to B with more connections j It can reduce the number of cross-chip connection lines between FPGA and microprocessor, convert inter-chip connections into intra-chip connections, shorten the signal transmission path, reduce the delay on the transmission path, and by reducing inter-chip connections, it can further reduce the failure rate and improve the reliability of the system.

[0052] As a preferred embodiment, when the number of physical interconnection links in a microprocessor or FPGA chip is less than the number of transmission signal lines, the corresponding physical interconnection links are multiplexed through a multiplexer. The method also includes: S300, configuring multiplexers for the ports of the microprocessor and FPGA chip respectively.

[0053] Optionally, the multiplexer configured for each port is a time division multiplexer or a frequency division multiplexer. Other multiplexers in the prior art fall within the scope of protection of the present invention. It should be noted that the ports at both ends of the same interconnection channel are configured with the same type of time division multiplexer, while the ports of different interconnections can be configured with different types of multiplexers as needed. Preferably, the multiplexer is a time division multiplexer (TDM), which is used to transmit multiple signals via a single interconnection channel.

[0054] As a preferred embodiment, S640 further includes: allocating time slot resources for transmission signals between n first-class design modules and m second-class design modules, inserting a multiplexer into each physical interconnection link according to the time slot resources, and obtaining signal transmission configuration modules for n first-class design modules and signal transmission configuration modules for m second-class design modules. Assigning a physical interconnection link to each transmission signal through a routing algorithm can clarify the physical interconnection link corresponding to each transmission signal, and the allocation of time slot resources can clarify the time slot allocation rules between multiple transmission signals that need to be transmitted by the same physical interconnection link. Optionally, the allocated time slot resources are a time division multiplexing ratio. Preferably, the time division multiplexing ratio k of the time division multiplexer is to combine k input signals into one output signal for transmission.

[0055] As a preferred embodiment, the method further includes:

[0056] S700: Obtain k memories connected to n microprocessors and m FPGA chips, respectively, and package the n microprocessors, m FPGA chips, and k memories through chiplet integration, where 0 ≤ k ≤ K. This chiplet integration can reduce interconnection latency between the microprocessors, FPGAs, and memories, thereby improving the performance of the heterogeneous simulation system provided by the present invention.

[0057] As a preferred embodiment, the S700 is packaged in any one of the following ways: interconnecting n microprocessors, m FPGA chips and k memories through a PCB; interconnecting n microprocessors, m FPGA chips and k memories through a silicon interposer; or interconnecting n microprocessors, m FPGA chips and k memories through through-holes in a silicon substrate.

[0058] As a preferred embodiment, the heterogeneous simulation system provided by the present invention may not be packaged as a whole. In this case, the n microprocessors, m FPGA chips, and k memories are interconnected through PCB boards or physical connections, where 0≤k≤K.

[0059] Based on the same inventive concept as the above method embodiment, an embodiment of the present invention further provides a heterogeneous hardware simulation system, the system including an interconnected hardware simulator Emu, K memories, a system compiler, and a server, the Emu including N microprocessors and M FPGA chips, the compilation speed of the microprocessor being faster than that of the FPGA chip and the simulation performance being lower than that of the FPGA chip, the N microprocessors, the M FPGA chips, and the K memories including L physical interconnection links, where K ≥ 0, N ≥ 1, M ≥ 1, and L ≥ 1; the system compiler including a divider, a router, n microprocessor compilers, and m FPGA chip compilers, as shown in FIG2 , 0 < n ≤ N and 0 < m ≤ M; wherein:

[0060] A divider is used to divide the chip design DUT into n microprocessors and m FPGA chips, wherein the DUT includes an independent design module D to be debugged and corrected, and D is divided into the microprocessor to obtain the first type of design modules of n microprocessors and the second type of design modules of m FPGA chips.

[0061] The router is used to allocate physical interconnection links for transmission signals between n first-type design modules and m second-type design modules, thereby obtaining signal transmission configuration modules for n first-type design modules and signal transmission configuration modules for m second-type design modules.

[0062] The microprocessor compiler is used for compiling the first type of design modules and their signal transmission configuration modules to generate the first type of executable files of the microprocessor.

[0063] The FPGA chip compiler is used to compile the second type of design modules and their signal transmission configuration modules to generate the second type of executable files of the FPGA chip.

[0064] The server is configured to store n first-category executable files in n microprocessors, respectively, and m second-category executable files in m FPGA chips, respectively. The first-category executable files and the second-category executable files are then used to control the n microprocessors and m FPGA chips for collaborative simulation and debugging. It should be noted that the server includes hardware emulation system runtime software (emulator runtime software) that supports the correct operation of the entire hardware emulation system.

[0065] As a preferred embodiment, wherein: the router is used to allocate physical interconnection links and time slot resources for transmission signals between n first-type design modules and m second-type design modules, and the system compiler also includes: a multiplexer inserter, used to insert the time slot resources allocated according to each physical interconnection link into the multiplexer.

[0066] It should be noted that the invention concept of this system embodiment is the same as that of the above-mentioned method embodiment, and the technical features with the same name are the same and will not be repeated.

[0067] Through this heterogeneous hardware simulation system, the independently designed modules are divided into microprocessors, and the mature designs are divided into FPGAs for simulation, taking into account the iteration speed of microprocessors and the performance advantages of FPGA simulation.

[0068] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A heterogeneous hardware simulation method, characterized in that: The method comprises: S200, obtaining an interconnected hardware emulator Emu and K memories, wherein Emu includes N microprocessors and M FPGA chips, the compilation speed of the microprocessor is greater than that of the FPGA chip and the simulation performance is lower than that of the FPGA chip, and L physical interconnection links are included between the N microprocessors, the M FPGA chips and the K memories, wherein K≥0, N≥1, M≥1, and L≥1; S400, obtaining a chip design DUT, wherein the DUT includes an independent design module D to be debugged and modified; S600, the system compiler processes the DUT to obtain n first-category executable files corresponding to n microprocessors in Emu and m second-category executable files corresponding to m FPGA chips, where 0<n≤N and 0<m≤M; including: S620, dividing the DUT into n microprocessors and m FPGA chips respectively, wherein D is divided into the microprocessor, thereby obtaining the first type of design modules of the n microprocessors and the second type of design modules of the m FPGA chips; S640, allocating physical interconnection links for transmission signals between n first-category design modules and m second-category design modules, and obtaining signal transmission configuration modules for n first-category design modules and signal transmission configuration modules for m second-category design modules; S660, compile and generate a first-class executable file of the microprocessor according to each first-class design module and its signal transmission configuration module, and obtain n first-class executable files; compile and generate a second-class executable file of the FPGA chip according to each second-class design module and its signal transmission configuration module, and obtain m second-class executable files; S800, storing n first-category executable files in n microprocessors respectively, storing m second-category executable files in m FPGA chips respectively, and controlling the n microprocessors and the m FPGA chips to perform collaborative simulation and debugging through the first-category executable files and the second-category executable files; Among them, S600 also includes: S630 optimizes the number of physical interconnect links between chips, including: S632, respectively obtain the first type of design modules B allocated to the j-th microprocessor j and the second type of design module F allocated to the i-th FPGA chip i , B j Include submodule D of D j ; Wherein, the value range of j is 1 to n, and the value range of i is 1 to m; S634, Get F i Middle and D j Q connected elements cell={cell1,cell2,…,cell q ,…,cell Q }, cell q F i Middle and D j The qth element connected, where q ranges from 1 to Q; S636, respectively obtain each element in the cell and D j The number of physical interconnection links Sum1 i and each element in F i The number of physical links in Sum2 i , where cell q With D j The number of physical interconnection links Sum1 i,q , cell q In F i The number of physical links in Sum2 i,q ; S638, when Sum1 i,q Greater than Sum2 i,q When q Reassign to B j Inside.

2. The method according to claim 1, characterized in that The method further comprises: S300 configures multiplexers for the ports of the microprocessor and the FPGA chip respectively.

3. The method according to claim 1, characterized in that in: S640 also includes: allocating time slot resources for transmission signals between n first-category design modules and m second-category design modules, inserting a multiplexer into each physical interconnection link according to the time slot resources, and obtaining signal transmission configuration modules for n first-category design modules and signal transmission configuration modules for m second-category design modules.

4. The method according to claim 3, characterized in that The multiplexer is a time division multiplexer, and the time slot resource is a time division multiplexing ratio.

5. The method according to claim 1, characterized in that The microprocessor is a Boolean processor.

6. The method according to claim 1, characterized in that The method further comprises: S700, obtaining k memories respectively connected to n microprocessors and m FPGA chips, and packaging the n microprocessors, the m FPGA chips, and the k memories through core particle integration, wherein 0≤k≤K.

7. The method according to claim 6, characterized in that The S700 is packaged in any of the following ways: Interconnect n microprocessors, m FPGA chips and k memories through PCB; Interconnect n microprocessors, m FPGA chips, and k memories through a silicon interposer; The n microprocessors, m FPGA chips and k memories are interconnected through through-holes in the silicon substrate.

8. The method according to claim 1, characterized in that: The n microprocessors, m FPGA chips and k memories are interconnected via PCB boards or physical wires, wherein 0≤k≤K.

9. A heterogeneous hardware simulation system, the system comprising an interconnected hardware simulator Emu, K memories and a system compiler, the Emu comprising N microprocessors and M FPGA chips, the compilation speed of the microprocessor being greater than that of the FPGA chip and the simulation performance being lower than that of the FPGA chip, the N microprocessors, the M FPGA chips and the K memories comprising L physical interconnection links, wherein K≥0, N≥1, M≥1, and L≥1; the system compiler comprising a divider, a router, n microprocessor compilers and m FPGA chip compilers, 0<n≤N and 0<m≤M; wherein: A divider is used to divide the chip design DUT into n microprocessors and m FPGA chips, wherein the DUT includes an independent design module D to be debugged and modified, and D is divided into the microprocessor to obtain the first type of design modules of the n microprocessors and the second type of design modules of the m FPGA chips; A router, used to allocate physical interconnection links for transmission signals between the n first-category design modules and the m second-category design modules, and obtain signal transmission configuration modules of the n first-category design modules and signal transmission configuration modules of the m second-category design modules; A microprocessor compiler, used for compiling and generating a first type of executable file of the microprocessor according to the first type of design module and its signal transmission configuration module; An FPGA chip compiler, used for compiling and generating a second type of executable file of the FPGA chip according to the second type of design module and its signal transmission configuration module; The server is used to store n first-class executable files in n microprocessors respectively, and m second-class executable files in n microprocessors respectively. The files are stored in m FPGA chips respectively, and the n microprocessors and m FPGA chips are controlled by the first type of executable files and the second type of executable files to perform collaborative simulation and debugging.

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