Electronic-paper driving circuit and preparation method therefor, and electronic-paper display panel

Abstract

Provided in the present application is an electronic-paper driving circuit, comprising a plurality of driving units. Each driving unit comprises a data writing module, a voltage-stabilizing module, a retaining module and a driving module, wherein a first end of the data writing module is electrically connected to a data signal line, a second end thereof is electrically connected to a first end of the voltage-stabilizing module and a first end of the retaining module, and a control end of the data writing module is electrically connected to a scanning signal line; a second end of the voltage-stabilizing module is electrically connected to a fixed potential end; a second end of the retaining module is electrically connected to a first end of the driving module, and a control end of the retaining module is electrically connected to the scanning signal line; and a second end of the driving module is electrically connected to the fixed potential end.

Description

Electronic paper driving circuit, preparation method and electronic paper display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311076285.2, filed on August 24, 2023, entitled “Electronic paper driving circuit, preparation method and electronic paper display panel,” and the entire contents of that application are incorporated herein by reference. Technical Field

[0003] The present application belongs to the field of display technology, and in particular relates to an electronic paper driving circuit, a preparation method, and an electronic paper display panel. Background Art

[0004] With the development of display technology, the performance requirements for display devices are becoming increasingly higher. Electronic paper technology uses a 1T1C driver circuit consisting of only one transistor and one capacitor to achieve electronic paper display through the electric field effect. However, this configuration has certain drawbacks that affect the display quality of electronic paper display panels.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide an electronic paper driving circuit, a manufacturing method, and an electronic paper display panel, which can improve the display quality of the electronic paper display panel.

[0007] An embodiment of the first aspect of the embodiments of the present application provides an electronic paper driving circuit, including multiple driving units, each of the driving units including a data writing module, a voltage stabilizing module, a holding module and a driving module, the first end of the data writing module is electrically connected to the data signal line, the second end of the data writing module is electrically connected to the first end of the voltage stabilizing module and the first end of the holding module, the control end of the data writing module is electrically connected to the scanning signal line, the second end of the voltage stabilizing module is electrically connected to the fixed potential end, the second end of the holding module is electrically connected to the first end of the driving module, the control end of the holding module is electrically connected to the scanning signal line, and the second end of the driving module is electrically connected to the fixed potential end.

[0008] The embodiment of the second aspect of the present application further provides a method for preparing an electronic paper driving circuit, comprising:

[0009] providing a substrate;

[0010] A driving circuit layer is formed in sequence on one side of the substrate, wherein the driving circuit layer includes a driving unit, and the driving unit includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The driving circuit layer includes a first metal layer, a semiconductor layer, and a second metal layer stacked in a direction away from the substrate, wherein the semiconductor layer is used to form the source region, the drain region, and the channel region of the first transistor and the second transistor, respectively; the first metal layer is used to form the gate of the first transistor and the second transistor, and the first plate of the first capacitor and the second capacitor, respectively; and the second metal layer is used to form the source and drain of the first transistor and the second transistor, and the second plate of the first capacitor and the second capacitor, respectively.

[0011] An embodiment of the third aspect of the present application further provides an electronic paper display panel, comprising any electronic paper driving circuit provided in the first aspect of the present application.

[0012] The electronic paper driving circuit provided in the present application includes multiple driving units, each of which includes a data writing module, a voltage stabilizing module, a holding module, and a driving module. As shown in the figure, the data writing module is used to write data signals into the driving unit. During the data writing phase, the scanning signal in the scanning signal line drives the data writing module and the holding module to work, and the data signal in the data signal line can be written into the voltage stabilizing module and the driving module; during the frame holding phase, the voltage stabilizing module and the holding module can effectively suppress the influence of the data writing module on the potential of the driving module, thereby making the driving voltage of the pixels in the electronic paper close to the ideal value, improving the performance of the electronic paper driving circuit, and further can be used to improve the display effect of the electronic paper display panel using the electronic paper driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a top view of an electronic paper driving circuit provided in an embodiment of the present application;

[0014] FIG2 is a circuit diagram of a driving unit in an electronic paper driving circuit provided in an embodiment of the present application;

[0015] FIG3 is a timing diagram of an electronic paper driving circuit provided in an embodiment of the present application;

[0016] FIG4 is a circuit diagram of a driving unit in an electronic paper driving circuit provided by an embodiment of the present application;

[0017] FIG5 is a schematic diagram of a film structure of a driving unit in an electronic paper driving circuit provided in an embodiment of the present application;

[0018] FIG6 is a circuit diagram of a driving unit in another electronic paper driving circuit provided by an embodiment of the present application;

[0019] FIG7 is a schematic diagram of a film structure of a driving unit in another electronic paper driving circuit provided in an embodiment of the present application;

[0020] FIG8 is a schematic diagram of a film structure of a driving unit in another electronic paper driving circuit provided in an embodiment of the present application;

[0021] FIG9 is a schematic diagram of a film structure of a driving unit in another electronic paper driving circuit provided in an embodiment of the present application;

[0022] FIG10 is a reference diagram of an electronic paper driving circuit in use according to an embodiment of the present application;

[0023] FIG11 is a flow chart of a method for preparing an electronic paper driving circuit provided in an embodiment of the present application;

[0024] 12 and 13 are schematic structural diagrams of a method for preparing an electronic paper driving circuit according to an embodiment of the present application during the preparation process;

[0025] 14 to 16 are schematic structural diagrams of another method for preparing an electronic paper driving circuit according to an embodiment of the present application during the preparation process;

[0026] FIG17 is a schematic structural diagram of an electronic paper display panel provided in an embodiment of the present application;

[0027] FIG18 is a cross-sectional view taken along line MM' in FIG17;

[0028] FIG19 is a circuit diagram of an electronic paper display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating the examples of the present application.

[0030] After long-term research, the inventors discovered that the driving potential of pixels in electronic paper deviates significantly from the ideal value, affecting display quality. The specific reason is that electronic paper technology uses a 1T1C driving circuit consisting of only one transistor and one capacitor to achieve electronic paper display through the electric field effect. One end of the transistor is connected to the data signal line and the other end is connected to the capacitor. When the data signal in the data signal line is written to the capacitor and the data signal jumps, the voltage difference between the two ends of the transistor is large, which makes leakage prone. This causes the potential written into the capacitor to change, thereby affecting the actual driving voltage of the pixel and, in turn, the display quality of the electronic paper. Based on the research on the above issues, the inventors provide an electronic paper driving circuit, a preparation method, and an electronic paper display panel to improve the display quality of electronic paper display panels.

[0031] In order to better understand the present application, the electronic paper driving circuit, preparation method and electronic paper display panel according to the embodiments of the present application are described in detail below with reference to Figures 1 to 19.

[0032] Please refer to Figures 1 to 2. An embodiment of the present application provides an electronic paper driving circuit 1, including multiple driving units 11, each driving unit 11 including a data writing module 16, a voltage stabilizing module 17, a holding module 18 and a driving module 19. The first end of the data writing module 16 is electrically connected to the data signal line 12, the second end of the data writing module 16 is electrically connected to the first end of the voltage stabilizing module 17 and the first end of the holding module 18, the control end of the data writing module 16 is electrically connected to the scanning signal line 15, the second end of the voltage stabilizing module 17 is electrically connected to the fixed potential end 13, the second end of the holding module 18 is electrically connected to the first end of the driving module 19, the control end of the holding module 18 is electrically connected to the scanning signal line 15, and the second end of the driving module 19 is electrically connected to the fixed potential end 13.

[0033] The electronic paper driving circuit 1 provided in the present application includes a plurality of driving units 11, each of which includes a data writing module 16, a voltage stabilizing module 17, a holding module 18, and a driving module 19. As shown in FIG3 , the data writing module 16 is used to write a data signal Data into the driving unit 11. During a data writing phase t1, the scan signal Scan in the scan signal line 15 drives the data writing module 16 and the holding module 18 to operate, thereby writing the data signal Data in the data signal line 12 into the voltage stabilizing module 17 and the driving module 19. During a frame holding phase t2, the voltage stabilizing module 17 and the holding module 18 can effectively suppress the influence of the data writing module 16 on the potential of the driving module 19, thereby making the driving voltage of the pixels in the electronic paper close to the ideal value, thereby improving the performance of the electronic paper driving circuit 1, and further improving the display effect of the electronic paper display panel 3 using the electronic paper driving circuit 1.

[0034] In a feasible embodiment, as shown in Figures 4 and 5, the data writing module 16 includes a first transistor 111, the voltage stabilizing module 17 includes a first capacitor 113, the holding module 18 includes a second transistor 112, the driving module 19 includes a second capacitor 114, the first capacitor 113 includes a first connection terminal 1131 and a second connection terminal 1132, and the second capacitor 114 includes a third connection terminal 1141 and a fourth connection terminal 1142, wherein the first electrode 1113 of the first transistor 111 is electrically connected to the data signal line 12, the second electrode 1114 of the first transistor 111 is electrically connected to the first connection terminal 1131 and the first electrode 1121 of the second transistor 112, the second electrode 1122 of the second transistor 112 is electrically connected to the third connection terminal 1141 of the second capacitor 114, the second connection terminal 1132 and the fourth connection terminal 1142 are electrically connected to the fixed potential terminal 13, and the gate of the first transistor 111 and the gate of the second transistor 112 are respectively electrically connected to the scanning signal line 15.

[0035] In the above embodiment, the first end of the data writing module 16 is the first electrode 1113 of the first transistor 111, and the second end of the data writing module 16 is the second electrode 1114 of the first transistor 111. The first end of the voltage stabilizing module 17 is the first connection terminal 1131 of the first capacitor 113, and the second end of the voltage stabilizing module 17 is the second connection terminal 1132 of the first capacitor 113. The first end of the holding module 18 is the first electrode 1121 of the second transistor 112, and the second end of the holding module 18 is the second electrode 1122 of the second transistor 112. The first end of the driving module 19 is the third connection terminal 1141 of the second capacitor 114, and the second end of the driving module 19 is the fourth connection terminal 1142 of the second capacitor 114.

[0036] The electronic paper driving circuit 1 provided in the present application includes a plurality of driving units 11, each driving unit 11 including two transistors and two capacitors. Specifically, the two transistors include a first transistor 111 and a second transistor 112, and the two capacitors include a first capacitor 113 and a second capacitor 114. The gate of the first transistor 111 and the gate of the second transistor 112 are electrically connected to the scanning signal line 15, respectively, so that the two transistors can be turned on and off synchronously. The first electrode 1113 of the first transistor 111 is electrically connected to the data signal line 12, the second electrode 1114 of the first transistor 111 is electrically connected to the first connection terminal 1131 of the first capacitor 113 and the first electrode 1121 of the second transistor 112, the second electrode 1122 of the second transistor 112 is electrically connected to the third connection terminal 1141 of the second capacitor 114, and the second connection terminal 1132 and the fourth connection terminal 1142 are electrically connected to the fixed potential terminal 13. In the data writing phase t1, that is, the phase in which the scanning signal Scan in the scanning signal line 15 drives the first transistor 111 and the second transistor 112 to turn on, the data signal Data in the data signal line 12 can be written into the first capacitor 113 and the second capacitor 114; in the frame holding phase t2, the first capacitor 113 can effectively suppress the influence of the first transistor 111 on the potential of the second capacitor 114, thereby playing a voltage stabilizing role. Specifically, as shown in Figure 3, in the data writing phase t1, the data signal Data is at a low level and is written into the first capacitor 113 and the second capacitor 114, so that the first capacitor 113 and the second capacitor 114 are in an equipotential state; in the frame holding phase t2, the data signal Data jumps to a high level. At this time, the first electrode 1113 and the second electrode 1114 of the first transistor 111 are at the same potential state. The voltage difference is large, which makes the first transistor 111 prone to leakage, thereby changing the potential of the first capacitor 113. At this time, the voltage difference between the first electrode 1121 and the second electrode 1122 of the second transistor 112 (that is, the potential difference between the first capacitor 113 and the second capacitor 114) is small, so the second transistor 112 is not prone to leakage at this time, that is, the first capacitor 113 and the second transistor 112 can achieve voltage stabilization of the second capacitor 114, weakening the potential change at both ends of the second transistor 112 caused by the leakage of the first transistor 111, reducing the difference between the potential of the second capacitor 114 and the data signal Data, so that the driving voltage of the pixel in the electronic paper can be close to the ideal value, thereby improving the performance of the electronic paper driving circuit 1, and further can be used to improve the display effect of the electronic paper display panel 3 using the electronic paper driving circuit 1.

[0037] The electronic paper display panel 3 includes pixel electrodes and a common electrode located at two ends of a pixel, and the fixed potential end 13 may have the same potential as the common electrode.

[0038] In a feasible embodiment, as shown in Figures 6 and 7, the first transistor 111 includes a first sub-transistor 1111 and a second sub-transistor 1112, the second pole of the first sub-transistor 1111 is electrically connected to the first pole of the second sub-transistor 1112, the gate of the first sub-transistor 1111 and the gate of the second sub-transistor 1112 are both electrically connected to the scanning signal line 15, the first pole of the first sub-transistor 1111 is electrically connected to the data signal line 12, and the second pole of the second sub-transistor 1112 is electrically connected to the first connection terminal 1131 and the first pole 1121 of the second transistor 112.

[0039] In the above embodiment, the first transistor 111 is a dual-gate transistor, that is, the first transistor 111 includes two sub-transistors. Each transistor in the present application can be replaced by two sub-transistors (dual-gate transistors), that is, the source of one sub-transistor is connected to the drain of the other sub-transistor, and the gates of these two sub-transistors are connected to the same scan signal line 15. When two interconnected sub-transistors are used instead of one transistor, the effect of leakage current on the potential of the second capacitor 114 can be further reduced, thereby further improving the performance of the electronic paper driving circuit 1.

[0040] In a feasible embodiment, as shown in FIG5 or FIG7 , the driving circuit includes a substrate 115 and a driving circuit layer 116. The driving circuit layer 116 is located on one side of the substrate 115 and includes a driving unit 11. The driving circuit layer 116 includes a semiconductor layer 1161, a first metal layer 1162, and a second metal layer 1163 stacked in a direction away from the substrate 115. In which, the semiconductor layer 1161 is used to form the source region, drain region and channel region of the first transistor 111 and the second transistor 112 respectively, the first metal layer 1162 is used to form the gate of the first transistor 111 and the second transistor 112, as well as the first plate 1133 of the first capacitor 113 and the first plate 1143 of the second capacitor 114 respectively, and the second metal layer 1163 is used to form the source and drain of the first transistor 111 and the second transistor 112, as well as the second plate 1134 of the first capacitor 113 and the second plate 1144 of the second capacitor 114 respectively, wherein the first connection terminal 1131 is located at the first plate 1133 of the first capacitor 113, the second connection terminal 1132 is located at the second plate 1134 of the first capacitor 113, the third connection terminal 1141 is located at the first plate 1143 of the second capacitor 114, and the fourth connection terminal 1142 is located at the second plate 1144 of the second capacitor 114.

[0041] In the above embodiment, the first transistor 111 and the second transistor 112 are both top-gate structures.

[0042] In the above embodiment, the semiconductor layer 1161 may include a first semiconductor partition B1 for forming the first transistor 111 and a second semiconductor partition B2 for forming the second transistor 112. When the first transistor 111 includes two sub-transistors, the first semiconductor partition B1 may include two channel regions, and a source region and a drain region located on both sides of each channel region, wherein the source region and the drain region located between the two channel regions are connected.

[0043] Specifically, the device may further include a first insulating layer 119, which is located between the semiconductor layer 1161 and the first metal layer 1162. The material of the first insulating layer 119 may include silicon oxide, silicon nitride, etc. The device may further include a second insulating layer 120, which is located between the first metal layer 1162 and the second metal layer 1163. The material of the second insulating layer 120 may include an inorganic material, such as silicon nitride.

[0044] In another feasible embodiment, as shown in FIG8 , the driving circuit includes a substrate 115 and a driving circuit layer 116. The driving circuit layer 116 is located on one side of the substrate 115. The driving circuit layer 116 includes a driving unit 11. The driving circuit layer 116 includes a first metal layer 1162, a semiconductor layer 1161, and a second metal layer 1163 stacked in a direction away from the substrate 115. The semiconductor layer 1161 is used to form the source region, drain region, and channel region of the first transistor 111 and the second transistor 112, respectively. The first metal layer 1162 is used to form the gate of the first transistor 111 and the second transistor 112, and the first plate 1133 of the first capacitor 113 and the second capacitor 114, respectively. The first electrode 1143 and the second metal layer 1163 are used to respectively form the source and drain of the first transistor 111 and the second transistor 112, as well as the second electrode 1134 of the first capacitor 113 and the second electrode 1144 of the second capacitor 114, wherein the first connection terminal 1131 is located at the second electrode 1134 of the first capacitor 113, the second connection terminal 1132 is located at the first electrode 1133 of the first capacitor 113, the third connection terminal 1141 is located at the second electrode 1144 of the second capacitor 114, and the fourth connection terminal 1142 is located at the first electrode 1143 of the second capacitor 114.

[0045] In the above embodiment, the first transistor 111 and the second transistor 112 are both bottom-gate structures.

[0046] In the above embodiment, the second plate 1134 of the first capacitor 113 is continuously arranged with the second electrode 1114 of the first transistor 111 and the first electrode 1121 of the second transistor 112 , and the second plate 1144 of the second capacitor 114 is continuously arranged with the second electrode 1122 of the second transistor 112 .

[0047] In the above embodiment, the second electrode 1114 and the first connection terminal 1131 of the first transistor 111 and the second electrode 1122 and the third connection terminal 1141 of the second transistor 112 are located in the same layer, making the electrical connection more concise and simplifying the manufacturing process.

[0048] In a feasible embodiment, as shown in Figure 7, when the first transistor 111 includes a first sub-transistor 1111 and a second sub-transistor 1112, the first sub-transistor 1111 includes a first sub-gate, the second sub-transistor 1112 includes a second sub-gate, the gate of the first transistor 111 includes a first sub-gate and a second sub-gate, the second metal layer 1163 also includes a voltage-stabilizing structure 14, the orthographic projection of the voltage-stabilizing structure 14 on the substrate 115 is a first projection, the orthographic projection of the area between the first sub-gate and the second sub-gate on the substrate 115 is a second projection, and the first projection and the second projection at least partially overlap.

[0049] In the above embodiment, a voltage-stabilizing structure 14 is formed in the second metal layer 1163, so that after the data writing stage t1 ends, that is, after the stage in which the scanning signal Scan in the scanning signal line 15 drives the first transistor 111 and the second transistor 112 to turn on ends, the voltage of the middle node of the first transistor 111 (that is, the area between the channel regions of the two sub-transistors in the semiconductor layer 1161) can be well stabilized, reducing the probability of leakage of the first transistor 111 or reducing the leakage size, thereby further improving the performance of the electronic paper driving circuit 1.

[0050] At the same time, the voltage-stabilizing structure 14 is formed on the second metal layer 1163 , without adding a new film layer, and the preparation process is simple and low-cost.

[0051] In a feasible embodiment, as shown in Figures 6 and 7, the second capacitor 114 includes a first sub-capacitor 1145 and a second sub-capacitor 1146, the second capacitor 114 includes a first plate 1143, a second plate 1144 and a third plate 1147, the first sub-capacitor 1145 is formed between the first plate 1143 of the second capacitor 114 and the second plate 1144 of the second capacitor 114, and the second sub-capacitor 1146 is formed between the second plate 1144 of the second capacitor 114 and the third plate 1147 of the second capacitor 114.

[0052] In the above embodiment, the second capacitor 114 includes a third plate 1147 in addition to the first plate 1143 and the second plate 1144, forming a first sub-capacitor 1145 and a second sub-capacitor 1146 connected in parallel. The use of the first sub-capacitor 1145 and the second sub-capacitor 1146 in the second capacitor 114 significantly increases the capacitance of the second capacitor 114, thereby better maintaining the capacitance stability of the second capacitor 114 during the frame hold period t2.

[0053] Specifically, the third electrode plate 1147 may be located on the side of the second electrode plate 1144 facing away from the substrate 115. A new conductive layer may be added or an existing film layer in the driving circuit layer 116 may be used for preparation, which is not particularly limited in this application.

[0054] In one feasible embodiment, as shown in FIG7 , the driving circuit layer 116 further includes an interlayer dielectric layer 117 and a pixel electrode layer 118. The interlayer dielectric layer 117 is located on the side of the second metal layer 1163 facing away from the substrate 115, and the pixel electrode layer 118 is located on the side of the interlayer dielectric layer 117 facing away from the substrate 115 and contacts the interlayer dielectric layer 117. The interlayer dielectric layer 117 includes a first groove 1171 located on the surface of the interlayer dielectric layer 117 facing away from the substrate 115. The orthographic projection of the first groove 1171 on the substrate 115 at least partially overlaps with the orthographic projection of the second plate 1144 of the second capacitor 114 on the substrate 115. The pixel electrode layer 118 is partially located within the first groove 1171 to form the third plate 1147 of the second capacitor 114.

[0055] In the above embodiment, the third electrode 1147 is manufactured through the pixel electrode layer 118 in the driving circuit layer 116 without adding a new film layer, thereby simplifying the manufacturing process of the driving circuit layer 116 .

[0056] In the above embodiment, a first groove 1171 is formed in the interlayer dielectric layer 117, and the opening of the first groove 1171 is located on the side of the interlayer dielectric layer 117 facing away from the substrate 115, so that the distance between the portion of the pixel electrode layer 118 located in the first groove 1171 and the second electrode plate 1144 in the direction perpendicular to the substrate 115 is smaller, that is, the distance between the third electrode plate 1147 and the second electrode plate 1144 in the direction perpendicular to the substrate 115 is reduced, thereby increasing the capacitance of the second sub-capacitor 1146, and further increasing the capacitance of the second capacitor 114.

[0057] In a feasible embodiment, as shown in FIG7 , the pixel electrode layer 118 includes a plurality of pixel electrodes. The pixel electrode can have an integrated structure with the third electrode plate 1147, that is, the pixel electrode and the third electrode plate 1147 are reused, and the power supply to the third electrode plate 1147 can be realized while powering the pixel electrode, thereby simplifying the power supply to the third electrode plate 1147, reducing the wiring difficulty, and thus simplifying the preparation process. Alternatively, the pixel electrode and the third electrode plate 1147 can be independent of each other and connected by a connecting line to realize the power supply to the third electrode plate 1147, which is not particularly limited in this application.

[0058] In one feasible embodiment, as shown in FIG7 , the pixel electrode is electrically connected to the second electrode 1122 of the second transistor 112. Because the second electrode 1122 of the second transistor 112 is electrically connected to the third connection terminal 1141, the second capacitor 114 serves as the primary capacitor of the pixel electrode. The stability of the potential of the second capacitor 114 is directly related to the voltage stability of the pixel electrode, thereby affecting the display quality of the electronic paper display panel 3 using this electronic paper driver circuit 1. Because the second capacitor 114 includes a first sub-capacitor 1145 and a second sub-capacitor 1146, the capacitance of the second capacitor 114 can be significantly increased, and the capacitance stability of the second capacitor 114 can be better maintained during the frame hold period t2, thereby improving the display quality of the electronic paper display panel 3 using this electronic paper driver circuit 1. At the same time, since the electronic paper driving circuit 1 provided in the present application includes two transistors and two capacitors, that is, a 2T2C structure, the voltage of the second capacitor 114 can be stabilized through the first capacitor 113 and the second transistor 112, thereby reducing the difference between the potential of the second capacitor 114 and the data signal Data, so that the driving voltage of the pixel in the electronic paper driving circuit 1, that is, the voltage of the pixel electrode, can be close to the ideal value, thereby improving the performance of the electronic paper driving circuit 1, and can be used to improve the display effect of the electronic paper display panel 3 using the electronic paper driving circuit 1.

[0059] In a feasible embodiment, as shown in Figure 9, the second plate 1144 of the second capacitor 114 is continuously arranged with the second plate 1134 of the first capacitor 113, and the interlayer dielectric layer 117 also includes a second groove 1172 located on the surface of the interlayer dielectric layer 117 facing away from the substrate 115. The orthographic projection of the second groove 1172 on the substrate 115 at least partially overlaps with the orthographic projection of the second plate 1134 of the first capacitor 113 on the substrate 115, and the pixel electrode layer 118 is partially located in the second groove 1172, and the portion of the pixel electrode layer 118 located in the second groove 1172 is continuously arranged with the portion located in the first groove 1171.

[0060] In the above embodiment, the second plate 1144 of the second capacitor 114 is disposed continuously with the second plate 1134 of the first capacitor 113, thereby increasing the area of ​​the second plate 1144 of the second sub-capacitor 1146 and thereby increasing the capacitance of the second sub-capacitor 1146. Furthermore, by forming a second recess 1172 in the interlayer dielectric layer 117, the orthographic projection of the second recess 1172 on the substrate 115 at least partially overlaps with the orthographic projection of the second plate 1134 of the first capacitor 113 on the substrate 115, thereby forming a portion of the third plate 1147 that opposes the second plate 1134 of the first capacitor 113 within the second recess 1172. Part of the pixel electrode layer 118 is located in the second groove 1172, and the part of the pixel electrode layer 118 located in the second groove 1172 is continuously arranged with the part located in the first groove 1171, thereby increasing the area of ​​the third plate 1147, that is, the area of ​​the third plate 1147, the second plate 1144 and the facing area of ​​the second sub-capacitor 1146 are increased, thereby increasing the capacitance of the second sub-capacitor 1146.

[0061] In a feasible embodiment, as shown in Figure 9, the interlayer dielectric layer 117 includes a non-thinning region Q1 and a first thinning region Q2 and a second thinning region Q3. The first thinning region Q2 is located between the first groove 1171 and the second plate 1144 of the second capacitor 114, and the size of the first thinning region Q2 along the direction perpendicular to the substrate 115 is less than or equal to 0.5 μm; and / or, the second thinning region Q3 is located between the second groove 1172 and the second plate 1134 of the first capacitor 113, and the size of the second thinning region Q3 along the direction perpendicular to the substrate 115 is less than or equal to 0.5 μm; and / or, the size of the non-thinning region Q1 along the direction perpendicular to the substrate 115 is 1.2 μm-1.65 μm.

[0062] In the above embodiment, the interlayer dielectric layer 117 includes a first thinned region Q2 and a second thinned region Q3 opposite the first groove 1171 and the second groove 1172, thereby reducing the distance between the second plate 1144 and the third plate 1147 of the second sub-capacitor 1146, thereby increasing the capacitance of the second sub-capacitor 1146. Specifically, the dimensions of the first thinned region Q2 and the second thinned region Q3 along a direction perpendicular to the substrate 115 are less than or equal to 0.5 μm, and may include 0.1 μm, 0.2 μm, 0.3 μm, 0.5 μm, etc., and are not particularly limited in this application.

[0063] In the above embodiment, the interlayer dielectric layer 117 includes a non-thinned region Q1 except the first thinned region Q2 and the second thinned region Q3 . The size of the non-thinned region Q1 in the direction perpendicular to the substrate 115 is 1.2 μm-1.65 μm.

[0064] Specifically, the size of the non-thinning region Q1 in a direction perpendicular to the substrate 115 may include 1.2 μm, 1.3 μm, 1.35 μm, 1.48 μm, 1.65 μm, etc., which is not particularly limited in this application.

[0065] By making the non-thinning region Q1 thicker, when the electronic paper driving circuit 1 is applied to the electronic paper display panel 3, the adverse effect of the interference electric field formed between the data signal Data in the second metal layer 1163 and the common electrode in the electronic paper display panel 3 on the display quality of the electronic paper display panel 3 can be reduced. Furthermore, the loss of the data signal Data in the second metal layer 1163 during transmission is greatly reduced.

[0066] In a feasible embodiment, the material of the interlayer dielectric layer 117 includes organic glue; on the one hand, the organic glue can have a good insulation effect, and on the other hand, the organic glue is easy to pattern to form the first groove 1171 and the second groove 1172, which helps to reduce the difficulty of preparation, thereby improving the preparation yield and saving preparation costs.

[0067] In a feasible embodiment, when the first transistor 111 and the second transistor 112 are top-gate structures, the second plate 1134 of the first capacitor 113 , the second plate 1144 of the second capacitor 114 , and the voltage stabilizing structure 14 are all connected to the fixed potential terminal 13 .

[0068] As shown in FIG10 , the electronic paper drive circuit 1 is located within the electronic paper display panel 3 during use. The electronic paper display panel 3 also includes an electrophoretic layer 31, which is located on one side of the electronic paper drive circuit 1 and includes microcapsules 311 and a solvent 312. The second plate 1134 of the first capacitor 113, the second plate 1144 of the second capacitor 114, and the voltage stabilizing structure 14 are all connected to the fixed potential terminal 13, thereby providing a shielding effect and preventing potential changes on the first plate 1133 of the first capacitor 113 and the first plate 1143 of the second capacitor 114 from adversely affecting the microcapsules 311 in the electronic paper display panel 3.

[0069] In a feasible embodiment, as shown in Figures 5, 7 and 8, the semiconductor layer 1161 includes a first semiconductor partition B1 and a second semiconductor partition B2, the first semiconductor partition B1 is used to form the source region, drain region and channel region of the first transistor 111, and the second semiconductor partition B2 is used to form the source region, drain region and channel region of the second transistor 112, and the materials of the first semiconductor partition B1 and the second semiconductor partition B2 both include low-temperature polycrystalline silicon.

[0070] In the above embodiment, the materials of the first semiconductor partition B1 and the second semiconductor partition B2 include low-temperature polycrystalline silicon. The field-effect mobility of low-temperature polycrystalline silicon is greatly improved compared to the a-Si semiconductor commonly used in conventional technology, thereby improving the charging speed of the first capacitor 113 and the second capacitor 114. In conventional technology, the field-effect mobility of transistors using a-Si semiconductor in the semiconductor layer 1161 is extremely low. To ensure the charging rate of the capacitor, the channel width of the transistor is as large as possible. In this case, the size of the transistor is large, which will significantly increase the area ratio of the transistor in the drive unit 11, thereby reducing the area ratio of the capacitor in the drive unit 11, that is, reducing the size of the capacitor. At the same time, the large area ratio of the transistor in the drive unit 11 increases the parasitic capacitance between the gate and source, and between the gate and drain in the transistor, thereby significantly increasing the load of the scan signal line 15, thereby exacerbating the delay problem, and at the same time affecting the potential change of the second capacitor 114. When the materials of the first semiconductor partition B1 and the second semiconductor partition B2 both include low-temperature polysilicon, the sizes of the first transistor 111 and the second transistor 112 can be reduced while meeting the charging speed requirements, thereby reducing the parasitic capacitance of the first transistor 111 and the second transistor 112 to improve the performance of the driving circuit and improve the display effect of the electronic paper display panel 3 using the electronic paper driving circuit 1.

[0071] Or in another embodiment, the material of the first semiconductor partition B1 includes low-temperature polysilicon, and the material of the second semiconductor partition B2 includes oxide semiconductor.

[0072] In the above embodiment, the material of the first semiconductor subregion B1 includes low-temperature polysilicon, which improves the field-effect mobility of the first transistor 111, accelerates the charging speed of the first capacitor 113 and the second capacitor 114, and reduces the size of the first transistor 111, thereby reducing the adverse effects of parasitic capacitance. The material of the second semiconductor subregion B2 includes an oxide semiconductor, which significantly improves the field-effect mobility compared to a-Si semiconductors. The use of an oxide semiconductor also reduces leakage problems in the second transistor 112.

[0073] In the above embodiment, the material of the pixel electrode layer 118 may include a transparent oxide material, such as indium tin oxide, which is not particularly limited in this application.

[0074] In a feasible embodiment, a buffer layer (not shown in the figure) is also included between the substrate 115 and the driving circuit layer 116, which may specifically include a silicon nitride layer and a silicon oxide layer stacked in a direction away from the substrate 115. The buffer layer can play a buffering role and at the same time can isolate water vapor entering from the side of the substrate 115 to improve the service life.

[0075] The present application also provides a method for preparing an electronic paper driving circuit 1, as shown in FIG11 , comprising:

[0076] S100 , providing a substrate 115 .

[0077] S200, a driving circuit layer 116 is sequentially formed on one side of the substrate 115, the driving circuit layer 116 including a driving unit 11, the driving unit 11 including a first transistor 111, a second transistor 112, a first capacitor 113 and a second capacitor 114, the driving circuit layer 116 including a first metal layer 1162, a semiconductor layer 1161 and a second metal layer 1163 stacked in a direction away from the substrate 115, wherein the semiconductor layer 1161 is used to form a source region, a drain region and a channel region of the first transistor 111 and the second transistor 112, respectively, the first metal layer 1162 is used to form a gate of the first transistor 111 and the second transistor 112, as well as a first plate 1133 of the first capacitor 113 and a first plate 1143 of the second capacitor 114, and the second metal layer 1163 is used to form a source and a drain of the first transistor 111 and the second transistor 112, as well as a second plate 1134 of the first capacitor 113 and a second plate 1144 of the second capacitor 114, respectively.

[0078] The electronic paper drive circuit 1 fabricated using the above-described fabrication process includes multiple drive units 11, each of which includes two transistors and two capacitors. Specifically, the two transistors include a first transistor 111 and a second transistor 112, and the two capacitors include a first capacitor 113 and a second capacitor 114. The first capacitor 113 and the second transistor 112 can be used to stabilize the voltage of the second capacitor 114, reducing the difference between the potential of the second capacitor 114 and the data signal Data. This allows the drive voltage of the pixels in the electronic paper to approach the ideal value, improving the performance of the electronic paper drive circuit 1, and can further enhance the display effect of the electronic paper display panel 3 using the electronic paper drive circuit 1.

[0079] In a feasible implementation, it further includes:

[0080] S300, an interlayer dielectric layer 117 is formed on the side of the second metal layer 1163 facing away from the substrate 115, and a first groove 1171 is patterned to form the first groove 1171, and the orthographic projection of the first groove 1171 on the substrate 115 at least partially overlaps with the orthographic projection of the second plate 1144 of the second capacitor 114 on the substrate 115.

[0081] S400 , forming a pixel electrode layer 118 on a side of the interlayer dielectric layer 117 facing away from the substrate 115 . A portion of the pixel electrode layer 118 is located in the first groove 1171 to form the third plate 1147 of the second capacitor 114 .

[0082] In the above embodiment, the second capacitor 114 includes a first sub-capacitor 1145 formed between the first plate 1143 and the second plate 1144 and a second sub-capacitor 1146 formed between the second plate 1144 and the pixel electrode layer 118 in the second groove 1172. The capacitance is greatly increased, which can improve the display effect.

[0083] In a feasible embodiment, the steps of forming an interlayer dielectric layer 117 on a side of the second metal layer 1163 facing away from the substrate 115 and patterning the first groove 1171 include:

[0084] S301, as shown in Figure 12, a mask plate 2 is set on the side of the interlayer dielectric layer 117 facing away from the substrate 115, and the mask plate 2 includes a non-transparent area A1 and a semi-transparent area A2. The semi-transparent area A2 is located on the side of the interlayer dielectric layer 117 where the area for forming the first groove 1171 is facing away from the substrate 115.

[0085] S302 , as shown in FIG. 12 and FIG. 13 , a portion of the interlayer dielectric layer 117 in the region for forming the first groove 1171 is removed by light irradiation, thereby forming the first groove 1171 .

[0086] In the above embodiment, the interlayer dielectric layer 117 is made of an organic resin and can be removed by exposure. The mask plate 2 is positioned on the side of the interlayer dielectric layer 117 facing away from the substrate 115, thereby allowing exposure to only a portion of the interlayer dielectric layer 117. Specifically, the semi-transparent area A2 of the mask plate 2 is aligned with the area for forming the first groove 1171 and exposed, thereby removing a portion of the interlayer dielectric layer 117 to form the first thinned region Q2.

[0087] In the above embodiment, the transmittance of the semi-transparent region A2 is 20%-30%, so that the thickness of the first thinned region Q2 is less than or equal to 0.5 micrometers, thereby increasing the capacitance of the second sub-capacitor 1146 .

[0088] In the above embodiment, the semi-transparent region A2 is made of chromium oxide, and the non-transparent region A1 is made of chromium. The mask plate 2 may further include a fully transparent region A3 for forming a via hole in the interlayer dielectric layer 117 to electrically connect the pixel electrode layer 118 to the second transistor 112 and the second capacitor 114.

[0089] Alternatively, as shown in Figures 14, 15, and 16, the semi-transparent area A2 includes strip-shaped vias 21 extending through the thickness of the mask plate 2, with the spacing between adjacent strip-shaped vias 21 being 1μm-2μm. Specifically, the strip-shaped vias 21 can be rectangular strip-shaped vias 21. Due to the slit diffraction effect, the exposure light intensity in the slit is weakened (equivalent to 30% transmittance of the semi-transparent area A2). At this time, only a portion of the area in the interlayer dielectric layer 117 corresponding to the semi-transparent area A2 is partially exposed and developed, forming a plurality of exposure vias 1173. Then, after a curing process, based on the fluidity of the material used to form the interlayer dielectric layer 117, the sidewall areas of the different exposure vias 1173 are reduced in height after flowing and connected together to form a first groove 1171 with a non-flat bottom wall. This embodiment has a low cost for the mask plate 2, which can reduce the manufacturing cost of the electronic paper driving circuit 1.

[0090] The present application also provides an electronic paper display panel 3, as shown in Figures 17, 18 and 19, comprising any electronic paper driving circuit 1 provided in the above embodiments of the present application.

[0091] Since the electronic paper display panel 3 provided in the present application includes any one of the electronic paper driving circuits 1 provided in the above embodiments, the electronic paper display panel 3 provided in the present application has the beneficial effects of any one of the electronic paper driving circuits 1 provided in the above embodiments, which will not be repeated here.

[0092] In a feasible embodiment, as shown in Figures 18 and 19, the electronic paper display panel 3 also includes an electrophoretic layer 31 and a common electrode layer 32. The electrophoretic layer 31 is located on one side of the electronic paper driving circuit 1, and includes microcapsules 311 and a solvent 312. The microcapsules 311 are distributed in the solvent 312; the common electrode layer 32 is located on the side of the electrophoretic layer 31 away from the electronic paper driving circuit 1.

[0093] The material of the common electrode layer 32 may include a transparent conductive material, specifically may include indium tin oxide, which is not particularly limited in this application.

[0094] In a feasible embodiment, an encapsulation layer is further included, which is located on the side of the common electrode layer facing away from the substrate and is used to block water vapor to increase the service life of the electronic paper display panel.

[0095] While the embodiments described above are not exhaustive, they do not limit the present application to specific embodiments. Clearly, numerous modifications and variations are possible based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. An electronic paper driving circuit, comprising a plurality of driving units, each of the driving units comprising a data writing module, a voltage stabilizing module, a holding module and a driving module, a first end of the data writing module being electrically connected to a data signal line, a second end of the data writing module being electrically connected to a first end of the voltage stabilizing module and a first end of the holding module, a control end of the data writing module being electrically connected to the scanning signal line, a second end of the voltage stabilizing module being electrically connected to a fixed potential end, a second end of the holding module being electrically connected to a first end of the driving module, a control end of the holding module being electrically connected to the scanning signal line, and a second end of the driving module being electrically connected to the fixed potential end.

2. The electronic paper driving circuit according to claim 1, wherein: The data writing module includes a first transistor, the voltage stabilizing module includes a first capacitor, the holding module includes a second transistor, the driving module includes a second capacitor, the first capacitor includes a first connection end and a second connection end, the second capacitor includes a third connection end and a fourth connection end, wherein the first electrode of the first transistor is electrically connected to the data signal line, the second electrode of the first transistor is electrically connected to the first connection end and the first electrode of the second transistor, the second electrode of the second transistor is electrically connected to the third connection end, the second connection end and the fourth connection end are electrically connected to the fixed potential end, and the gate of the first transistor and the gate of the second transistor are electrically connected to the scanning signal line respectively.

3. The electronic paper driving circuit according to claim 2, wherein: The first transistor includes a first sub-transistor and a second sub-transistor, the second electrode of the first sub-transistor is electrically connected to the first electrode of the second sub-transistor, the gate of the first sub-transistor and the gate of the second sub-transistor are both electrically connected to the scanning signal line, the first electrode of the first sub-transistor is electrically connected to the data signal line, and the second electrode of the second sub-transistor is electrically connected to the first connection end and the first electrode of the second transistor.

4. The electronic paper driving circuit according to claim 3, wherein: The driving circuit comprises: substrate; A driving circuit layer is located on one side of the substrate, the driving circuit layer includes the driving unit, and the driving circuit layer includes a semiconductor layer, a first metal layer and a second metal layer stacked in a direction away from the substrate, wherein the semiconductor layer is used to form the first transistor and the source region, drain region and channel region of the second transistor, the first metal layer is used to respectively form the gates of the first transistor and the second transistor and the first plates of the first capacitor and the second capacitor, the second metal layer is used to respectively form the source and drain of the first transistor and the second transistor and the second plates of the first capacitor and the second capacitor, wherein the first connection end is located at the first plate of the first capacitor, the second connection end is located at the second plate of the first capacitor, the third connection end is located at the first plate of the second capacitor, and the fourth connection end is located at the second plate of the second capacitor.

5. The electronic paper driving circuit according to claim 3, wherein: The driving circuit comprises: substrate; A driving circuit layer is located on one side of the substrate, the driving circuit layer includes the driving unit, and the driving circuit layer includes a first metal layer, a semiconductor layer and a second metal layer stacked in a direction away from the substrate, wherein the semiconductor layer is used to form the source region, the drain region and the channel region of the first transistor and the second transistor, respectively, the first metal layer is used to form the gate of the first transistor and the second transistor and the first plate of the first capacitor and the second capacitor, respectively, and the second metal layer is used to form the source and drain of the first transistor and the second transistor and the second plate of the first capacitor and the second capacitor, respectively, wherein the first connection end is located at the second plate of the first capacitor, the second connection end is located at the first plate of the first capacitor, the third connection end is located at the second plate of the second capacitor, and the fourth connection end is located at the first plate of the second capacitor.

6. The electronic paper driving circuit according to claim 5, wherein: The second electrode plate of the first capacitor is continuously arranged with the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate of the second capacitor is continuously arranged with the second electrode of the second transistor.

7. The electronic paper driving circuit according to any one of claims 4 to 6, wherein: The first sub-transistor includes a first sub-gate, the second sub-transistor includes a second sub-gate, the gate of the first transistor includes the first sub-gate and the second sub-gate, the second metal layer also includes a voltage-stabilizing structure, the orthographic projection of the voltage-stabilizing structure on the substrate is a first projection, the orthographic projection of the area between the first sub-gate and the second sub-gate on the substrate is a second projection, and the first projection and the second projection at least partially overlap.

8. The electronic paper driving circuit according to claim 7, wherein: The second capacitor includes a first sub-capacitor and a second sub-capacitor, the second capacitor includes a first plate, a second plate and a third plate, the first sub-capacitor is formed between the first plate of the second capacitor and the second plate of the second capacitor, and the second sub-capacitor is formed between the second plate of the second capacitor and the third plate of the second capacitor.

9. The electronic paper driving circuit according to claim 8, wherein: The driving circuit layer also includes an interlayer dielectric layer and a pixel electrode layer, wherein the interlayer dielectric layer is located on a side of the second metal layer away from the substrate, the pixel electrode layer is located on a side of the interlayer dielectric layer away from the substrate and is in contact with the interlayer dielectric layer, the interlayer dielectric layer includes a first groove located on a surface of the interlayer dielectric layer away from the substrate, the orthographic projection of the first groove on the substrate at least partially overlaps with the orthographic projection of the second plate of the second capacitor on the substrate, and the pixel electrode layer is partially located in the first groove to form a third plate of the second capacitor.

10. The electronic paper driving circuit according to claim 9, wherein: The pixel electrode layer includes a plurality of pixel electrodes; The pixel electrode is electrically connected to the second electrode of the second transistor.

11. The electronic paper driving circuit according to claim 9, wherein: The second electrode plate of the second capacitor is continuously arranged with the second electrode plate of the first capacitor, the interlayer dielectric layer also includes a second groove located on the surface of the interlayer dielectric layer facing away from the substrate, the orthographic projection of the second groove on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate, the pixel electrode layer is partially located in the second groove, and the portion of the pixel electrode layer located in the second groove is continuously arranged with the portion located in the first groove.

12. The electronic paper driving circuit according to claim 9, wherein: The interlayer dielectric layer includes a non-thinning area and a first thinning area and a second thinning area. The first thinning area is located between the first groove and the second plate of the second capacitor, and the size of the first thinning area along the direction perpendicular to the substrate is less than or equal to 0.5μm; and / or, the second thinning area is located between the second groove and the second plate of the first capacitor, and the size of the second thinning area along the direction perpendicular to the substrate is less than or equal to 0.5μm; and / or, the size of the non-thinning area along the direction perpendicular to the substrate is 1.2μm-1.65μm.

13. The electronic paper driving circuit according to claim 9, wherein: The second plate of the first capacitor, the second plate of the second capacitor and the voltage stabilizing structure are all connected to the fixed potential end.

14. The electronic paper driving circuit according to any one of claims 4 to 6, wherein: The semiconductor layer includes a first semiconductor partition and a second semiconductor partition, the first semiconductor partition is used to form a source region, a drain region and a channel region of the first transistor, and the second semiconductor partition is used to form a source region, a drain region and a channel region of the second transistor, the material of the first semiconductor partition includes low-temperature polycrystalline silicon, and the material of the second semiconductor partition includes an oxide semiconductor; or the materials of the first semiconductor partition and the second semiconductor partition both include low-temperature polycrystalline silicon.

15. A method for preparing an electronic paper driving circuit, comprising: providing a substrate; A driving circuit layer is sequentially formed on one side of the substrate, the driving circuit layer comprising a driving unit, the driving unit comprising a first transistor, a second transistor, a first capacitor and a second capacitor, the driving circuit layer comprising a first metal layer, a semiconductor layer and a second metal layer stacked in a direction away from the substrate, wherein the semiconductor layer is used to respectively form a source region, a drain region and a channel region of the first transistor and the second transistor, the first metal layer is used to respectively form a gate of the first transistor and the second transistor and a first electrode plate of the first capacitor and the second capacitor, and the second metal layer is used to respectively form a source electrode, a drain electrode of the first transistor and the second transistor and a second electrode plate of the first capacitor and the second capacitor.

16. The preparation method according to claim 15, wherein: Also includes: forming an interlayer dielectric layer on a side of the second metal layer facing away from the substrate, and patterning to form a first groove, wherein an orthographic projection of the first groove on the substrate at least partially overlaps an orthographic projection of the second electrode plate of the second capacitor on the substrate; A pixel electrode layer is formed on a side of the interlayer dielectric layer facing away from the substrate, and a portion of the pixel electrode layer is located in the first groove to form a third plate of the second capacitor.

17. The electronic paper driving circuit according to claim 16, wherein: The step of forming an interlayer dielectric layer on a side of the second metal layer away from the substrate and patterning to form a first groove comprises: A mask is arranged on a side of the interlayer dielectric layer away from the substrate, the mask comprising a non-light-transmitting area and a semi-light-transmitting area, the semi-light-transmitting area is located on a side of the interlayer dielectric layer where a region for forming the first groove is away from the substrate; A portion of the interlayer dielectric layer in a region of the interlayer dielectric layer for forming the first groove is removed by light irradiation, thereby forming the first groove.

18. The electronic paper driving circuit according to claim 17, wherein: The transmittance of the semi-transparent area is 20%-30%; the material of the semi-transparent area includes chromium oxide, and the material of the non-transparent area includes chromium; or, the semi-transparent area includes strip-shaped via holes running through the thickness direction of the mask plate, and the spacing between adjacent strip-shaped via holes is 1μm-2μm.

19. An electronic paper display panel, comprising an electronic paper driving circuit, an electrophoretic layer and a common electrode layer, the electronic paper driving circuit comprising a plurality of driving units, each of the driving units comprising a data writing module, a voltage stabilizing module, a holding module and a driving module, the first end of the data writing module being electrically connected to a data signal line, the second end of the data writing module being electrically connected to the first end of the voltage stabilizing module and the first end of the holding module, the control end of the data writing module being electrically connected to the scanning signal line, the second end of the voltage stabilizing module being electrically connected to a fixed potential end, the second end of the holding module being electrically connected to the first end of the driving module, the control end of the holding module being electrically connected to the scanning signal line, and the second end of the driving module being electrically connected to the fixed potential end.

20. The electronic paper display panel according to claim 19, wherein: The electrophoretic layer is located on one side of the electronic paper driving circuit and includes microcapsules and a solvent, wherein the microcapsules are distributed in the solvent; the common electrode layer is located on a side of the electrophoretic layer away from the electronic paper driving circuit.

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