Optoelectronic device and method for manufacturing an optoelectronic device

Abstract

The invention concerns an optoelectronic device comprising a semiconductor layer stack of at least a first layer of a first conductivity type, a second layer of a second conductivity type and an active region between the first and second layer. The first layer comprises a buried contact layer arranged between the active region and a light emitting surface of the semiconductor layer stack. The semiconductor layer stack comprises: a bottom surface opposite the light emitting surface; first side wall portions extending from the bottom surface into the direction of the light emitting surface until a level between the active region and the buried contact layer; second side wall portions extending from a level between the active region and the buried contact layer until the buried contact layer; and third side wall portions different from the first and second side wall portions extending from the buried contact layer into the direction of the light emitting surface. The optoelectronic device further comprises a material layer covering at least portions of the first side wall portions, a first contact element covering at least portions of the material layer and the second side wall portions electrically contacting the buried contact layer, and a second contact element electrically contacting the bottom surface.

Description

[0001] OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC

[0002] DEVICE

[0003] The present application claims priority from German patent application DE 10 2023 122 224.4 filed on August 18, 2023, the disclosure of which is incorporated by way for reference in its entirety.

[0004] The present invention concerns an optoelectronic device, in particular pLED, in a flip chip configuration. The present invention further concerns a method for manufacturing such an optoelectronic device as well as an array of optoelectronic devices manufactured by such a method .

[0005] BACKGROUND pLEDs are optoelectronic devices that comprise a lateral dimension in the range from a few pm to about 40 pm. Such devices provide a variety of different applications, including but not limited to displays.

[0006] They are usually processed in arrays of several thousands of devices, and subsequently transferred from their growth substrate or an intermediate carrier to a target substrate (e.g. display backplane) . To date optoelectronic devices and in particular p-LEDs are manufactured in such a way that the finished devices can be transferred to a driver substrate (e.g. display backplane) by a respective transfer process (e.g. stamping, LIFT, ... ) . If a subsequent processing of the devices on backplane level, for example electrically contacting a top contact, is to be avoided, optoelectronic devices in a flip chip configuration (horizontal pLEDs) are necessary, which have both electric contacts (p and n) on the same side of the device.

[0007] In particular for red-emitting p-pLEDs, based on for example an Indium Gallium Aluminium Phosphite (InGaAlP) material system, such a configuration is however difficult, as a highly doped contact layer buried in the epitaxial structure is required for electrical contacting the optoelectronic device. Such a highly doped contact layer with a sufficient thickness to be reliably hit by conventional etching processes can however cause high absorption losses . Very thin contact layers , on the other hand cannot be reliably hit by conventional etching processes .

[0008] Furthermore , optoelectronic devices in a flip chip configuration in general , but especially those based on an InGaAlP material system, run the risk of tensile stress in the semiconductor layers in the region between contacting pads of the device when subj ected to thermal stress due to CTE differences . Since this intermediate region of the semiconductor layers between the contacting pads floats freely like a bridge after assembly, the tensile stress can lead to cracking of the semiconductor layers and thus to failure of the device .

[0009] Therefore red-emitting p-pLEDs based on an InGaAlP material system, are to date manufactured with a contact or contact layer on both sides of the optoelectronic devices , namely on the bottom as well as emission side of the device . This is as very thin epitaxial contact layers can be realized as a first and / or last layer of an epitaxially grown layer stack and can thus be easily contacted from both sides .

[0010] It is an obj ect of the present application to provide an enhanced optoelectronic device , in particular pLED, in a flip chip configuration, as well as an enhanced method for manufacturing such an optoelectronic device .

[0011] SUMMARY OF THE INVENTION

[0012] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0013] The core of the invention is to use a multi-stage etching process to reliably expose a very thin contact layer buried in one of the semiconductor layers of a semiconductor layer stack forming the later optoelectronic device . This etching step is done from the same side as the semiconductor layer on the other side of an active region of the semiconductor layer stack . For example , by means of the multi-stage etching process a very thin contact layer buried in the n-side of the optoelectronic device can be reliably exposed when etching from the p- side of the optoelectronic device . Both electric contacts (p and n ) can thus be arranged on the same side of the optoelectronic device and a contact layer on the light emitting surface of the optoelectronic device can be dispensed with while still providing two electric contacts with good contact to the respective semiconductor layer on both sides of an active region . Thus , an optoelectronic device , for example red emitting pLED, can be provided in a flip chip configuration with a low contact resistance and thus high power efficiency . With a respective arrangement of a contact element contacting the buried contact layer, for example in form of a circular ring around the remaining semiconductor layer structure , tensile stresses in the intermediate area are largely avoided and the optoelectronic device thus becomes more reliable in operation .

[0014] A key aspects lies in the interaction of several process and design features such as for example :

[0015] A combination of dry and wet etch allowing to reliably etch until a thin buried contact layer within a layer of a semiconductor layer stack;

[0016] A circular contact pad design, which encloses the remaining semiconductor layer stack structure to prevent cracks in the semiconductor layer stack;

[0017] A mirror around the remaining semiconductor layer stack structure ( optical cavity) ;

[0018] A holding structure during manufacturing contacting a side laterally outside the active region; and

[0019] A specifically tuned material combination for holding structure material , sacrificial layer material and contact layer material .

[0020] According to a first aspect an optoelectronic device , in particular pLED, is provided . The optoelectronic device comprises a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and the second layer . The first layer thereby comprises a buried contact layer arranged between the active region and a light emitting surface of the semiconductor layer stack formed by an outer surface of the first layer . The semiconductor layer stack further comprises a bottom surface opposite the light emitting surface , first side wall portions extending from the bottom surface into the direction of the light emitting surface until a level between the active region and the buried contact layer , second side wall portions extending from a level between the active region and the buried contact layer until the buried contact layer, and third side wall portions different from the first and second side wall portions extending from the buried contact layer into the direction of the light emitting surface . The semiconductor layer stack can in particular be configured to emit light of a desired wavelength or wavelength range when electrically powered .

[0021] The optoelectronic device further comprises a material layer covering at least portions of the first side wall portions as well as in particular portions of the bottom surface . In addition, the optoelectronic device comprises a first contact element covering at least portions of the material layer and at least portions of the second side wall portions electrically contacting the buried contact layer, and a second contact element electrically contacting the bottom surface .

[0022] The first , second and third side wall portions can result from each an etching step in particular mesa etching step . The first , second and third side wall portions can in particular result from each a mesa etching step of the semiconductor layer stack from the same side of the semiconductor layer stack, namely the bottom surface of the semiconductor layer stack . The etching steps can thereby be a combination of dry and wet etching steps , wherein in particular a first etching step for generating the first side wall portions and the third etching step for generating the third side wall portion can be a dry etching step whereas the second side wall portions can in particular result from a second etching step in form of a wet etching step . By means of these etching steps in combination with a respective arrangement of contact layers / elements , a particularly advantageous structure can be achieved . The term side wall portions shall in this regard be understood as at least portions of the side walls of the respective structure being etched . The respective structure being etched resulting in the first , second and third side wall portions can in particular be the semiconductor layer stack .

[0023] In some aspects , the first contact element electrically contacts the buried contact layer from a side facing away from the light emitting surface . This can in particular result from the fact that the buried contact layer is exposed from a side facing away from the light emitting surface and a contact layer electrically contacting the buried contact layer contacts the exposed side of the buried contact layer .

[0024] In some aspects , the light emitting surface is free of a metal and / or conductive oxide material . In particular the optoelectronic device is of a flip chip configuration and both electric contacts for powering the optoelectronic device are arranged on the same side of the optoelectronic device , namely the same side as the bottom surface of the semiconductor layer stack . By contacting the first layer via the buried contact layer from the same side as the bottom surface of the semiconductor layer stack, a conductive material , in particular transparent conductive material on the light emitting surface as known from the art can be dispensed with .

[0025] In some aspects , the first side wall portions extend until the same level as the level from which the second side wall portions extend until the buried contact layer . In particular, the first side wall portions can be adj acent to the second sidewall portions and can be contiguous except , for example , for a lateral offset from each other . However it can also be conceivable that due to a further intermediate etching step further side wall portions are formed between the first and second side wall portions . It can also be conceivable that due to thechosen parameters of the first and second etching step, the first and second side wall portions are substantially contiguous , thus no or substantially no lateral offset between the first and second sidewall portions is present . In some aspects , the third side wall portions extend from the buried contact layer until the light emitting surface . Hence the third side wall portions can be contiguous from the buried contact layer until the light emitting surface . In other words , the second side wall portions can be adj acent to the third sidewall portions and can be contiguous except , for example , for a lateral offset from each other . However it can also be conceivable that due to a further intermediate etching step further side wall portions are formed between the second and third side wall portions .

[0026] In some aspects , wherein the first side wall portions comprise portions of the first layer, the second layer and the active region, but in particular not the buried contact layer . In particular , the first side wall portions comprise the whole side surfaces of the second layer and the active region as well as a side surface portion of the first layer between the active region and a level between the active region and the buried carrier layer . The second side wall portions can on the other hand comprise portions of the first layer, but in particular not the buried contact layer . In particular , the second side wall portions comprise a side surface portion of the first layer between a level between the active region and the buried carrier layer and the buried carrier layer . The third side wall portions lastly can comprise portions of the buried contact layer as well as portions of first layer . In particular , the third side wall portions comprise a side surface portion of the buried carrier layer as well as a side surface portion of the first layer between the buried carrier layer and the light emitting surface or a side surface portion of the first layer from the buried carrier layer to the light emitting surface .

[0027] In some aspects , adj acent first side wall portions and second side wall portions are laterally distant from each other and / or adj acent second wall portions and third side wall portions are laterally distant from each other . Due to an etching from the same side of the semiconductor layer stack resulting in the side wall portions , a pyramidal shape can for example be generated with several trapezoids stacked above each other in cross section, the side surfaces of which are forming the side wall portions with the largest trapezoid forming the third side wall portions , the second largest trapezoid forming the second side wall portions and the smallest trapezoid forming the first side wall portions . In particular, adj acent first side wall portions and second side wall portions and / or adj acent second and third side wall portions are shifted towards each other laterally and are not contiguous . The lateral shift can result from different etching steps with different sized etched surfaces and cross sections resulting from the etching .

[0028] According to some aspects , the first side wall portions and / or the second side wall portions and / or the third side wall portions are inclined . Due to a mesa etching, the resulting side wall portions can be inclined with respect to a perpendicular of the light emitting surface or bottom surface . In particular , the resulting side wall portions can be inclined such that the surface towards the bottom surface is smaller in area than the surface towards the light-emitting surface . The mesa etching can in particular leave a truncated pyramid or truncated cone in each case , the outer surfaces of which form the first , second and third side wall portions at least in places . In particular , the mesa etching can leave a truncated pyramid or truncated cone of different sizes stacked on top of each other , the outer surfaces of which form the inclined and laterally distant from each other first , second and third side wall portions at least in places .

[0029] According to some aspects , the semiconductor layer stack comprises a semiconductor material such as for example Indium Gallium Aluminium Phosphide ( InGaAlP ) . The semiconductor layer stack comprises at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and second layer . The first layer can for example be a semiconductor layer that is n-doped, whereas the second layer can for example be a semiconductor layer that is p-doped . The two layers can thus form a pn-j unction with the active region arranged in-between . The active region can for example comprise a quantum well or multi quantum well structure , or can for example comprise quantum dots .

[0030] The buried contact layer can for example be of InGaAlP with an Aluminium and / or Gallium content of 50 to 80% . The buried contact layer can also be of InAlP with an Aluminium content of 50 to 80% . The buried contact layer can for example be a few to a few hundred nanometres thick . For example , the buried contact layer can comprise a thickness of less than 500nm, less than 250nm, less than lO Onm or less than l Onm.

[0031] The optoelectronic device can in particular be a small light emitting component / element such as a small LED or pLED . A pLED can in particular be a very small LED with edge lengths down to 30 pm, down to 10 pm, down to 5 pm or even less . Such small LEDs can be free of a growth substrate and require a special handling and processing to improve their IQE and light outcoupling efficiency . One approach to improve the IQE of the pLED is to cover the first side wall portions with a regrowth layer . A possible approach to improve the outcoupling efficiency and light directionality of the light emitted by the pLED is to provide outcoupling structures and / or reflective structures on / in the pLED .

[0032] According to some aspects , the material layer comprises a regrowth layer covering the first side wall portions . In addition or as an alternative , the material layer comprises a first dielectric layer arranged between the first and second contact element and / or between the bottom surface and the first contact element and / or between the first side wall portions and the first contact element . Apart from quantum well intermixing , the material layer can be regrown with a semiconductor material and / or contain SiO2 , A12O3 and any other suitable material . In some instances , the material layer forms a portion of the outer surface of the optoelectronic device and / or is formed between the first and second contact element and / or between the bottom surface and the first contact element and / or between the first side wall portions and the first contact element . The material layer can in particular be configured as or comprise a dielectric material layer electrically isolating layers / components within the optoelectronic device preventing a short .

[0033] The material layer can for example comprise or consist of SiO2 , silicon nitride , Nb2O5 , HfO2 , A12O3 , or a stack of a combination of aforementioned materials . The material layer or portions thereof can in particular be deposited using physical vapor deposition ( PVD) , plasma-enhanced chemical vapor deposition ( PECVD ) or atomic layer deposition (ALD) .

[0034] In some aspects , the first contact element comprises a first contact layer arranged on the material layer and the second side wall portions , the first contact layer electrically contacting the buried contact layer . In addition or as an alternative , the first contact element comprises a first reflective layer arranged on the first contact layer and / or the material layer; and / or the first contact element comprises a first contact pad / metal layer arranged on the first contact layer , the first reflective layer and / or the material layer, the first contact pad electrically contacting the first contact layer and / or the buried contact layer . The first contact element can in particular comprise a first contact layer in particular also being reflective arranged on the material layer and the second side wall portions forming a mirror around the remaining semiconductor layer stack structure ( optical cavity) . The first contact layer can however also be of a transparent conductive material and a first reflective layer can be arranged on the first contact layer or below the first contact layer can form a mirror around the remaining semiconductor layer stack structure ( optical cavity) . The first contact pad can for example be a contact pad arranged on the first contact layer only in an area opposite the bottom surface or can be in form of a layer enclosing the first contact layer also electrically contacting the buried contact layer directly .

[0035] The first contact element can for example comprise or consist of a transparent conductive oxide ( TCO ) such as indium tin oxide ( ITO ) as a first contact layer . The first contact element can for example also comprise or consist of a transparent conductive oxide (TCO ) such as indium tin oxide ( ITO ) as a first contact layer combined with a gold (Au) germanium (Ge ) alloy layer . In addition, the first contact element can comprise a gold (Au) , platin ( Pt ) and / or titanium (Ti ) layer as well as a titanium (Ti ) , platin ( Pt ) , gold-indium-tin (AulnSn) , NilnSn, AuSn, InSn and / or a gold (Au ) based solder material as a first contact pad . According to some aspects , the first contact element covers at least portions of the third side wall portions . The first contact element can thus also contact the buried contact layer from a side surface of the buried contact layer further enhancing the contact resistance between the first contact element and the buried contact layer . Therefore the first contact layer or at least a portion of the first contact layer can be provided after the step of etching the third side wall portions . A further or alternative advantage can be that the semiconductor layer stack is encapsulated completely but not the light emitting surface , in particular by a reflective material forming a mirror cavity for the optoelectronic device and protecting the material of the semiconductor layer stack .

[0036] In some aspects , the second contact element comprises a second contact layer arranged on the bottom surface and / or a second reflective layer arranged on the second contact layer and / or the bottom surface . In addition or as an alternative , the second contact element comprises a second contact pad arranged on the second contact layer, the second reflective layer or the bottom surface . The second contact element can in particular comprise a second contact layer in particular also being reflective arranged on the bottom surface forming a mirror at a back side of the semiconductor layer stack . The second contact layer can however also be of a transparent conductive material and a second reflective layer can be arranged on the second contact layer or below the second contact layer can form a mirror at a back side of the semiconductor layer stack . The second contact pad can for example be a contact pad arranged on the second contact layer only in an area opposite the bottom surface or can be in form of a layer covering the whole first contact layer .

[0037] The second contact element can for example comprise or consist of a transparent conductive oxide ( TCO ) such as indium tin oxide ( ITO ) as a second contact layer . The second contact element can for example also comprise or consist of a transparent conductive oxide (TCO ) such as indium tin oxide ( ITO ) as a second contact layer combined with a silver (Ag ) , aluminum (Al ) , gold (Au ) , platinum ( Pt ) and / or titanium ( Ti ) layer or a layer stack thereof as a second reflective layer . The second contact element can for example also comprise or consist of a transparent conductive oxide ( TCO ) such as indium tin oxide ( ITO ) as a second contact layer combined with a silver (Ag ) , platinum ( Pt ) , nickel (Ni ) and / or titanium-tungsten-nitride ( TiW : N) layer . In addition, the second contact element can comprise a gold (Au ) , platinum ( Pt ) and / or titanium ( Ti ) layer as well as a titanium ( Ti ) , platinum ( Pt ) , gold- indium-tin (AulnSn ) , NilnSn, AuSn, InSn and / or a gold (Au) based solder material as a second contact pad .

[0038] The first as well as the second contact element can comprise a solder material or solder material layer at their outer surface facing away from the bottom surface , which can make a later transfer of the optoelectronic device easier .

[0039] The first contact element can, when viewed in a direction perpendicular to the bottom surface , be in form of a ring like structure , wherein the second contact element is arranged in the centre of the ring like structure being electrically isolated from the first contact element . The first contact element can in particular extend along the whole outer circumference of the optoelectronic device , while when viewed in a direction perpendicular to the bottom surface , the second contact element is arranged in the centre of the first contact element distant from the first contact element and thus being electrically isolated from the first contact element .

[0040] According to a second aspect , a method for manufacturing an optoelectronic device is provided . The method can in particular be a method for manufacturing an optoelectronic device according to at least some of aforementioned aspects . Hence all aspects already described for the optoelectronic device can in the same way be applied to the method for manufacturing the same .

[0041] According to some aspects , the method for manufacturing an optoelectronic device comprises the following steps :

[0042] Providing a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and second layer , on a growth substrate , the first layer comprising a buried contact layer arranged between the active region and the growth substrate ;

[0043] Structuring the semiconductor layer stack such that the structured semiconductor layer stack comprises a bottom surface and first side wall portions extending from the bottom surface into a direction away from the bottom surface until a level between the active region and the buried contact layer ;

[0044] Providing a material layer or first portion of a material layer covering at least portions of the first side wall portions and in particular covering portions of the bottom surface ;

[0045] Structuring the semiconductor layer stack such that the structured semiconductor layer stack comprises second side wall portions extending from a level between the active region and the buried contact layer until the buried contact layer ;

[0046] Providing a first contact element or at least a first portion of a first contact element covering at least portions of the material layer and at least portions of the second side wall portions , electrically contacting the buried contact layer ;

[0047] Structuring the semiconductor layer stack such that the structured semiconductor layer stack comprises third side wall portions different from the first and second side wall portions extending from the buried contact layer into the direction of the light emitting surface ; and

[0048] Providing a second contact element electrically contacting the bottom surface .

[0049] The first , second and third side wall portions can result from each an etching step in particular mesa etching step . The first , second and third side wall portions can in particular result from each a mesa etching step of the semiconductor layer stack from the same side of the semiconductor layer stack, namely the bottom surface of the semiconductor layer stack . The etching steps can thereby be a combination of dry and wet etching steps , wherein in particular a first etching step for generating the first side wall portions and the third etching step for generating the third side wall portion can be a dry etching step whereas the second side wall portions can in particular result from a second etching step in form of a wet etching step . In particular the second etching steps for generating the second side wall portions can be a wet etching step using aqueous solutions of K3Fe ( CN ) 6 , K2CO3 and / or K2HCO3 . By means of this , a reliable exposure of the buried contact layer can be achieved even if the buried contact layer is only a few to a few hundred nanometres thick .

[0050] In some aspects , the first structuring of the semiconductor layer stack can comprises the step of depositing a structured mask, for example hard mask, on the semiconductor layer stack . The material of the mas k can be suitable as the second contact element or a first portion of the second contact element and may comprise transparent conductive oxides or another conductive material . By doing so , the structured mas k material may remain on the bottom surface of the semiconductor layer stack after the mesa etching step .

[0051] In some aspects , the second structuring of the semiconductor layer stack as well as the later third structuring of the semiconductor layer stack is conducted into remaining portions of the semiconductor layer stack layer stack to a depth greater than the depth of the preceding structuring step . At least the first and second step of structuring will stop prior to reaching the growth substrate but the third step of structuring may reach until the growth substrate . Generally, after each structuring step , some cleaning or protecting the exposed surface may be conducted .

[0052] In some aspects , the second structuring of the semiconductor layer stack is conducted before the step of providing a material layer . In this case , the material layer covers at least parts of the first and second sidewall portions .

[0053] According to some aspects , the method further comprises at least one of the following steps : depositing a sacrificial layer at least partially covering the first and / or second contact element and / or the material layer; structuring the sacrificial layer to form at least one recess thereby exposing a portion of first and / or second contact element and / or the material layer and / or the semiconductor layer stack; depositing a bond layer into the recess ; attaching a temporary carrier to the bond layer; removing the growth substrate , thereby exposing portions of the sacrificial layer and / or the first contact element and / or the semiconductor layer stack; removing the sacrificial layer , in particular by one of dryetching, wet-etching, plasma-etching or dissolving in a solvent , for example water; and lifting off the optoelectronic device attached to the bond layer .

[0054] In addition to the steps described for reliably exposing the buried contact layer , the inventor proposes steps for processing the optoelectronic device , that result in the device being held from below, so there is no interference with the contact to a die or a carrier suitable for laser-induced forward transfer ( LI FT ) . Holding structures made of a bond material are also not broken but lose their mechanical contact to the semiconductor element during the transfer, specifically at an interface between the material of the holding structure and the material of the semiconductor element facing the holding structure .

[0055] According to some aspects , the bond material of the holding structure is carefully selected and free of semiconductor component . It comprises an organic compound or a thin layer of solder material . Both approaches avoid the formation of particles or rupture and residues on the interface .

[0056] The transfer process leaves a defined surface on the underside of the optoelectronic device , the contact area or the surface of the device used for bonding to the target substrate .

[0057] According to some aspects a planarization step of a sacrificial layer material prior to bonding the device with a growth substrate to a temporary carrier takes place . This avoids the filling of areas on the sides of the semiconductor elements by bond material . The bond material is different from the material of the sacrificial layer, such that removal of the sacrificial layer is easily achievable using substances that do not affect the bond material or the device ' s surface . The planar sacrificial layer with dedicated opening for the bond material of the holding structure attached to the optoelectronic device enables a maximum access area for the etchant used to remove the sacrificial layer in subsequent process steps . The planarization allows the openings in the sacrificial layer , which define the holding structures after filling with bond material , to be designed with lithographic precision .

[0058] This - in combination with the material selection for the bond material and surface of the optoelectronic device - is crucial to be able to control the adhesion force of the optoelectronic devices on the carrier for the transfer process . In addition, planarization of the sacrificial layer enables a particularly thin layer to be bonded to the substrate , which means that metallic ( thin-film) solders can be used as the material for the bond layer in addition to organic polymers . These are particularly resistant to the etching medium used for undercutting .

[0059] In accordance with some aspects , a sacrificial layer is deposited . The sacrificial layer covers at least partially the first and / or second contact element and / or the material layer . In other words , the sacrificial layer covers all surfaces of the optoelectronic device being exposed, including any contact material on top . The sacrificial layer material is then planarized to form an even surface . Said sacrificial layer comprises one of a metal-oxide and an organic material .

[0060] In accordance with some aspects , the sacrificial layer can be structured and at least one recess is formed therein, thereby exposing a portion of the material layer and / or the first contact element and / or the semiconductor layer stack . The area of the optoelectronic devices surface being exposed is dependent on the location of the recess . In some aspects , the exposed surface only contains one material . In particular , the exposed surface only contains the material of the buried contact layer or of the first contact element . In some other aspects , the exposed surface can include two materials , i . e . a dielectric and a contact layer adj acent to it . According to some aspects , a bond layer is deposited into the recess , the bond material also extending above the recess and forming an even surface in some instances . The bond layer may comprise an organic material or a metallic alloy, in particular containing gold . The composition of the bond layer is different from the sacrificial layer but selected such that any etchant used for removing the sacrificial layer does not affect the bond layer material or the surface of the optoelectronic device .

[0061] According to some aspects , a temporary carrier is attached to the bond layer . After the attachment of the temporary carrier , the growth substrate as well as a potential buffer layer can be removed to expose the light emitting surface of the semiconductor layer stack . If needed, material of the semiconductor layer stack is also removed until portions of the sacrificial layer are exposed . This will provide access to the sacrificial layer .

[0062] The proposed steps provide several benefits . The method can be used for a plurality of semiconductor devices to be processed on their growth substrate by patterned etching from continuous semiconductor layer stack . The sacrificial layer fills the gap between the plurality of mesa structured layer stacks . The surface of the sacrificial layer facing away from the mesa structured semiconductor layer stacks (within experimental accuracy) is essentially co-planar with the growth substrate and comprises openings in the ( lateral ) regions of the semiconductor elements . The bond material fills the openings and mechanically bonds the semiconductor layer stack to the temporary carrier .

[0063] The bond layer does not obstruct a later transfer process in any way, because no bond material is located at undesired places , for example between the optoelectronic devices . This enables the processing of elements with a very high density on the growth substrate , reducing the overall costs . The holding structure , it ' s number per optoelectronic device , its shape , form and the chosen material provides a flexible yet precise control of the adhesive force between the devices and the holding structure . As the sacrificial layer can be exposed at a relatively large size , the etching process for removing the sacrificial layer can be shortened, which does not only increase process speed but also reduces possible effects of the etchant on the remaining portions , i . e . the semiconductor layer stack .

[0064] Some aspects concern the selection of material for the sacrificial layer . Such selection should be based on a combination of the desired bond material as well as the material of the outer surface of the optoelectronic device . The material for the sacrificial layer can be selected based on all layers that are in direct contact with the etchant used for removing the sacrificial layer .

[0065] In some aspects , the material of the sacrificial layer is selected to be ZnO if the material layer comprises Si02 or Si3N4 , and / or a first and / or second contact element at the outer surface of the optoelectronic device comprises Au or Ag and in particular a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn . Dissolving ZnO would be an inorganic implementation . However, ZnO is easily removed with diluted HC1 that leaves Si02 , Si3N4 or noble metals like Au, Pd, Pt and Ag unaffected .

[0066] As an alternative , one can use organic materials and compounds for the sacrificial layer . Polystyrene , particularly solute in Ethylacetate or Toluol and is suitable if the material layer comprises Si02 or Si3N4 and / or a first and / or second contact element at the outer surface of the optoelectronic device comprises Au or Ag and in particular a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn . Polystyrene has the benefit that it is dissolvable in organic solvents , facilitating the later sacrificial layer removal .

[0067] Other forms of Polystyrene are possible , for example when melted and planarized by pressing if a first and / or second contact element at the outer surface of the optoelectronic device comprises one of Au and Ag , an Au containing alloy, or a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn . Polyvinylalcohol , PVA is also a suitable material if the material layer comprises Si02 . It also has the benefit that it is dissolvable in H20. A similar material is Polyvinylacetate , PVAc , if the material layer comprises Si02 or Si3N4 . It can be dissolved in Ethyl acetate . Finally, soft-baked photoresist can be used, if a first and / or second contact element at the outer surface of the optoelectronic device comprises one of Au and Ag , an Au containing alloy, or a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn . All organic materials as sacrificial layer material can also be removed by an oxygen-based plasma-etching process if a first and / or second contact element at the outer surface of the optoelectronic device comprises one of Au, an Au containing alloy, or a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn .

[0068] Some or all of the material of the sacrificial layer can be deposited by various means , further increasing the flexibility and optimizing the process . For example , deposition techniques include spinning , sputtering , or spraying the sacrificial layer material on a first and / or second contact element at the outer surface of the optoelectronic device and / or the surface of the material layer . In some aspects , viscosity is adj usted by adding a suitable solvent . Consequently, some techniques are also used to planarize the sacrificial layer .

[0069] For example , sacrificial layer material together with a solvent is deposited using one of the above-mentioned techniques . The solvent is vaporized, leaving a substantially planar and even surface of sacrificial layer material . Other deposition techniques include melting sacrificial layer material or pressing molten and low viscous sacrificial layer material are also possible .

[0070] To planarize an uneven surface of the sacrificial layer , one can use CMP and other mechanical techniques . In some further aspects , structuring the sacrificial layer comprises depositing a structured photo resist layer as to expose surface portions of the sacrificial layer . Then, the exposed portions of the sacrificial layer are wet etched or dry etched until a portion of the optoelectronic device' s surface is exposed . The recess can be formed above the bottom surface of the semiconductor layer stack and, for example , above the first or second contact element . The recess may also be formed in a sidewall portion of the optoelectronic device or partially adj acent to a sidewall portion of the optoelectronic device . The latter allows utilizing the bond material to connect to two adj acent optoelectronic devices .

[0071] Depositing the bond material on the sacrificial layer and the at least one recess may include a vapor deposition of the bond layer material . In some aspects a thin film solder material based on a gold allow like AuSn, AulnSn, but also InSn or NilnSn solder material is suitable . Alternatively, the bond layer material may be spinned, sputtered or evaporated onto the sacrificial layer . In some aspects , the bond material comprises an organic compound . Consequently, the bond material may comprise a solvent to adj ust its viscosity . This will provide an even surface after the solvent has evaporated .

[0072] Further deposition techniques may be used depending on the material . For example , one may use melting bond layer material on the surface or pressing molten or low viscous bond layer material on the surface of the sacrificial layer .

[0073] Different bond layer materials are suitable , particular bond layer materials that are different in its etching characteristics from the material of the sacrificial layer . In some aspects , the bond layer material comprises one of Benzocyclobuthene or epoxy resin, that is at least partially cured at room temperature or slightly elevated temperature , particularly if the sacrificial layer comprises an organic compound and / or if the first and / or second contact elements contain a solderable material stack . The bond layer material comprises in other aspects polystyrene if the sacrificial layer comprises PVA, or the bond layer material comprises epoxy resin or Benzocyclobuthene if the sacrificial layer comprises polystyrene . The various combinations are also stated further below .

[0074] In some aspects , the bond layer is cured after the temporary carrier is attached to the bond layer . For curing purposes , thermal or optical measures can be used . Of course , the curing process can be divided to fit the attachment and planarization process .

[0075] After attaching the temporary carrier, the semiconductor layer stack can be freed of the growth substrate . The temporary carrier acts as a new substrate for such process steps . Various methods of removing the growth substrate are known in the art . This will expose the semiconductor layer stack from the front side . A possible continuous portion of the semiconductor layer stack can also be removed to separate the individual optoelectronic devices embedded within the sacrificial layer . Removing the continuous portion of the semiconductor layer stack includes but is not limited to mechanical grinding , polishing, chemical mechanical polishing , CMP , wet or dry etching or combinations thereof .

[0076] The front side of the optoelectronic devices namely a light emitting surface of the semiconductor layer stack opposite the bottom surface is then exposed and can be further structured .

[0077] Finally, the proposed method may include removal of the sacrificial layer, in particular by one of dry-etching, wet-etching, plasmaetching, or dissolving in a solvent , in particular in water . Again, the selected removal process depends on the combination of the material of the semiconductor' s surface , the material of the sacrificial layer and the bond material . The optoelectronic device is then held by the bond material , defining a specific adhesion force at the interface . This will allow an easy transfer process onto a target substrate or a carrier for a subsequent LIFT process using a stamp, for example .

[0078] In some aspects , before or after the removal of the sacrificial layer the semiconductor layer stack opposite the bottom surface is covered by a passivation layer . This passivation layer can contain or consist of SiO2 , A12O3 , Si3N4 , HfO2 or other suitable dielectric materials .

[0079] In accordance with some aspects , the step of providing the first contact element comprises : providing a first contact layer on the material layer and the second side wall portions , the first contact layer electrically contacting the buried contact layer; and / or providing a first reflective layer on the first contact layer and / or the material layer; and / or providing a first contact pad on the first contact layer , the reflective layer and / or the material layer , the first contact pad electrically contacting the first contact layer and / or the buried contact layer .

[0080] In accordance with some aspects , the step of providing the second contact element comprises : providing a second contact layer on the bottom surface ; and / or providing a second reflective layer on the second contact layer or the bottom surface ; and / or providing a second contact pad on the second contact layer , on the second reflective layer or on the bottom surface .

[0081] In accordance with some aspects , the step of providing the material layer comprises : providing a regrowth layer on the first side wall portions ; and / or providing a first dielectric layer between the first and second contact element and / or between the bottom surface and the first contact element and / or between the first side wall portions and the first contact element .

[0082] In accordance with some aspects , the step of providing the first contact element comprises covering at least portions of the third side wall portions .

[0083] Another aspect concerns an array of optoelectronic devices processed by the proposed method and being arranged adj acent to one another . In the array, the sacrificial layer is in particular removed exposing bond layer material forming posts , wherein in particular a respective post is attached to a respective optoelectronic device . SHORT DESCRIPTION OF THE DRAWINGS

[0084] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0085] Fig . 1 to 11 show steps for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ; and

[0086] Fig . 12A and 12B show a cross sectional view of embodiments of an optoelectronic device connected to a holding structure in accordance with some aspects of the proposed principle ; and

[0087] Fig . 13A to 14B show a top view of embodiments of an optoelectronic device in accordance with some aspects of the proposed principle .

[0088] DETAILED DESCRIPTION

[0089] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

[0090] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0091] Figures 1 to 12 show steps for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle .

[0092] In a first step, as shown in figure 1 , a growth substrate 2 is provided with a semiconductor layer stack 3 epitaxially grown on top . The semiconductor layer stack comprises a first layer 4 of a first conductivity type , a second layer 5 of a second conductivity type as well as an active region 6 between the first and second layer 4 , 5 . In addition, the semiconductor layer stack 3 and in particular the first layer 4 comprises a buried contact layer 19 arranged between the active region 6 and the growth substrate 2 , wherein the buried contact layer 19 is for example a layer of a similar material as the first layer 4 but with a higher doping concentration . The buried contact layer 19 can for example of a thickness between 500 nm and 50nm .

[0093] In a second step, as shown in figure 2 , a structured contact layer , in particular a first portion of a second contact element 7 is deposited on a surface of the semiconductor layer stack 3 . The first portion of the second contact element 7 can for example form a structured mas k which is suitable as a mask for a subsequent etching step but can also be deposited / grown on the semiconductor layer stack 3 after a mesa etching of the semiconductor layer stack 3 has been performed . In the embodiment shown, the first portion of a second contact element 7 comprises a second contact layer 7a and a second reflective layer 7b . The second contact layer 7a can for example be of a transparent conductive material such as a TCO and the second reflective layer 7b can for example be of a metal and can comprise for example a solder material or solder material layer on a surface facing away from the second layer 5 . A solder material can for example comprise a metal layer stack consisting of AuSn, AulnSn, InSn, NiSn, NilnSn, SnAgCu . In a further step , as shown in figure 3 , a first mesa etching step is performed, in particular a dry etching step . The mesa etching step structures the semiconductor layer stack 3 , resulting in exposed portions of the semiconductor layer stack 3 that include a top surface 8 and inclined first side wall portions 9a . The etching is performed such that the etching does not go through the whole first layer 4 but stops well before reaching the growth substrate 2 . In particular the etching is performed such that the etching does not go through the whole first layer 4 but stops well before reaching the buried carrier layer 19 . The resulting first side wall portions 9a are thus extending from the bottom surface 8 into a direction away from the bottom surface 8 until a level between the active region 6 and the buried contact layer 19 . The exposed portions are thereby as shown in cross section in form of a trapezoid arranged on a residue of the first layer 4 .

[0094] In a following step, as shown in figure 4 , a first portion of a material layer 10 is provided on the mesa etched structure following the shape of the mesa etched structure . The first portion of the material layer 10 can be provided such that it covers at least the first side wall portions 9a . In the embodiment shown, the first portion of the material layer 10 covers the first side wall portions 9a, portions of the bottom surface adj acent to the first portion of the second contact element 7 , as well as a portion of the top surface of the first portion of the second contact element 7 . The first portion of the material layer 10 or at least a portion of the first portion of the material layer 10 can for example result from a Quantum well intermixing , and / or the exposed first side wall portions 9a and other exposed surfaces can be regrown with a semiconductor material , SiO2 , A12O3 and any other suitable material . In the embodiment shown, the first portion of the material layer 10 is a structured regrowth layer of SiO2 provided by means of ALD that covers the first side wall portions 9a, portions of the bottom surface adj acent to the first portion of the second contact element 7 , as well as a portion of the top surface of the first portion of the second contact element 7 . The first portion of the material layer 10 thereby in particular is of or at least comprises a dielectric material that covers the first side wall portions 9a, portions of the bottom surface adj acent to the first portion of the second contact element 7 , as well as a portion of the top surface of the first portion of the second contact element 7 .

[0095] In a further step, as shown in figure 5 , a second mesa etching step is performed . The mesa etching step structures the remaining semiconductor layer stack 3 , resulting in exposed portions of the semiconductor layer stack 3 that include inclined second side wall portions 9b . The etching is performed such that the etching does not go through the whole first layer 4 but stops when reaching the buried carrier layer 19 . In particular the second etching steps for generating the second side wall portions 9b is a wet etching step using for example K3 Fe (CN) 6 , K2CO3 and / or K2HCO3 . By means of this , a reliable exposure of the buried contact layer 19 can be achieved even if the buried contact layer 19 is only a few to a few hundred nanometres thick .

[0096] The resulting second side wall portions 9b are extending from the level , at which the first etching step stopped into a direction away from the bottom surface 8 until the buried contact layer 19 . The exposed portions are thereby as shown in cross section in form of a trapezoid arranged on a residue of the first layer 4 with a further trapezoid arranged on top .

[0097] In a following step , as shown in figure 6 , a first portion of a first contact element 16 , in particular a first contact layer 16a is provided on the mesa etched structure following the shape of the mesa etched structure . The first contact layer 16a can be provided such that it covers at least the second side wall portions 9b and electrically contacts the buried contact layer 19 . In the embodiment shown in Figure , the first contact layer 16a covers the second wall portions 9b , portions of the buried contact layer 19 , as well as a portion of the material layer 10 . In the embodiment shown, the first contact layer 16a is a structured metal layer that covers the second wall portions 9b , portions of the buried contact layer 19 , as well as a portion of the material layer 10 . The first contact layer 16a thereby in particular is a metal layer deposited on the respective surface that can subsequently be annealed . The first portion of the first contact element 16 can however also be a combination of a first contact layer 16a TCO in combination with a first reflective layer covering the first contact layer 16a .

[0098] Figures 7A and 7B show two possible following steps in which a second portion of the material layer 10 is provided on the first portion of the first contact element 16 . The second portion of the material layer 10 can be provided such that it covers at least a portion of the first portion of the first contact element 16 being in contact with the first portion of the material layer 10 . In the embodiment shown in figure 7A, the second portion of the material layer 10 covers a portion of the first contact layer 16a adj acent to the first portion of the material layer 10 , in particular in a transition area between the first contact layer 16a and the first portion of the material layer 10 . In the embodiment shown in figure 7B, the second portion of the material layer 10 covers a larger portion of the first contact layer 16a except an area of the first contact layer 16a directly opposite the buried carrier layer 19 and exposing a portion of the first contact layer 16a directly opposite the buried carrier layer 19 .

[0099] In the two embodiment shown, the second portion of the material layer 10 is a structured regrowth layer of SiO2 provided by means of for example ALD that covers a portion of the first contact layer 16a being in contact with the first portion of the material layer 10 . The second portion of the material layer 10 thereby in particular is of or at least comprises a dielectric material similar to that of the first portion of the material layer 10 .

[0100] Figures 8A, 8B and 8C show possible following steps , wherein the steps shown in Figure 8A and 8C can be subsequently to the step shown in figure 7A and wherein the step shown in Figure 8B can be subsequently to the step shown in figure 7B .

[0101] As shown in figures 8A and 8B a second portion of the first contact element 16 , in particular a first contact pad 16c is provided on the first contact layer 16a and the material layer 10 in form of a layer , and a second portion of the second contact element 7 , in particular a second contact pad 7c is provided on the second reflective layer 7b and the material layer 10 in form of a layer . In the embodiment shown in figure 8A, the first contact pad 16c covers a portion of the first contact layer 16a from a top surface down to the buried contact layer 19 also electrically contacting the buried contact layer 19 . In the embodiment shown in figure 8B, the first contact pad 16c covers a portion of the material layer 10 from a top surface down to the buried contact layer 19 electrically contacting the buried contact layer 19 at the exposed portion of the first contact layer 16a directly opposite the buried carrier layer 19 . In both embodiments , the second contact pad 7 c is provided on the second reflective layer 7b electrically contacting the bottom surface 8 . The first contact pad 16c is provided in an outer area of the later optoelectronic device , in particular along side surfaces and an edge region of a bottom surface of the later optoelectronic device , whereas the second contact pad 7 c is provided in the centre of the bottom surface of the later optoelectronic device . The first and second contact pad 16c , 7c are thereby laterally distant from each other . The first and second contact pad 16c, 7 c can for example be of a metal and can comprise for example a solder material or solder material layer on a surface facing away from the semiconductor layer stack 3 . A solder material can for example comprise a metal layer stack consisting of AuSn, AulnSn, InSn, NiSn, NilnSn, SnAgCu .

[0102] As shown in figures 8A and 8B exemplarily, the second contact pad 7 c can either follow the underlaying shape and be of a layer with substantially an equal thickness over its whole area , as shown in figure 8A, or comprise an substantially even surface opposite the semiconductor layer stack, as shown in figure 8B .

[0103] As shown in figure 8C in contrast , a third etching step is performed before providing the second portion of the first contact element 16 and the second portion of the second contact element 7 . The third etching step structures the remaining semiconductor layer stack 3 , resulting in exposed portions of the semiconductor layer stack 3 that include inclined third side wall portions 9c . In the embodiment shown, the etching is performed such that the etching goes from the buried carrier layer 19 through the whole first layer 4 and stops when reaching the growth substrate 2 . In particular the third etching step for generating the third side wall portions 9c is a dry etching step structuring the semiconductor layer stack into separate portions each later forming an optoelectronic device .

[0104] The resulting third side wall portions 9c are extending from the buried contact layer 19 into a direction away from the bottom surface 8 until the growth substrate 2 . The exposed portions are thereby as shown in cross section in form of a trapezoid arranged on the growth substrate with two further trapezoids arranged on top .

[0105] Figures 9A and 9B show possible following steps , wherein the step shown in Figure 9A can be subsequently to the step shown in figure 8A and wherein the step shown in Figure 9B can be subsequently to the step shown in figure 8B .

[0106] As shown in figure 9A, the third etching step is performed after providing the second portion of the first contact element 16 and the second portion of the second contact element 7 . The third etching step structures the remaining semiconductor layer stack 3 , resulting in exposed portions of the semiconductor layer stack 3 that include inclined third side wall portions 9c . In the embodiment shown, the etching is performed such that the etching goes from the buried carrier layer 19 through the whole first layer 4 and stops when reaching the growth substrate 2 . In particular the third etching step for generating the third side wall portions 9c is a dry etching step structuring the semiconductor layer stack into separate portions each later forming an optoelectronic device .

[0107] As shown in figure 9B the second portion of the first contact element 16 , in particular the first contact pad 16c is provided on the first contact layer 16a and the material layer 10 in form of a layer , and the second portion of the second contact element 7 , in particular the second contact pad 7c is provided on the second reflective layer 7b and the material layer 10 in form of a layer after the third etching step . Thus , tthe first contact pad 16c covers a portion of the first contact layer 16a from a top surface down to the buried contact layer 19 also electrically contacting the buried contact layer 19 further extending along the third side wall portions 9c . The second contact pad 7 c is provided on the second reflective layer 7b electrically contacting the bottom surface 8 . The first contact pad 16c is provided in an outer area of the later optoelectronic device , in particular along side surfaces and an edge region of a bottom surface of the later optoelectronic device , whereas the second contact pad 7 c is provided in the centre of the bottom surface of the later optoelectronic device . The first and second contact pad 16c , 7c are thereby laterally distant from each other . The first and second contact pad 16c, 7 c can for example be of a metal and can comprise for example a solder material or solder material layer on a surface facing away from the semiconductor layer stack 3 . A solder material can for example comprise a metal layer stack consisting of AuSn, AulnSn, InSn, NiSn, NilnSn, SnAgCu .

[0108] As shown in figures IDA and 10B, a sacrificial layer 11 is then deposited on the material layer 10 as well as on the first and second contact element 16 , 7 . The sacrificial layer 11 covers the sidewalls of the first contact element 16 and extends onto the material layer 10 and the second contact pad 7 . The sacrificial layer 11 in particular covers all exposed surfaces of the optoelectronic device and in particular fills up completely all gaps resulting from the mesa etching . The sacrificial layer 11 thereby comprises one of a metal- oxide or an organic material .

[0109] The sacrificial layer 11 is then, planarized to form an even surface 12 . The even surface 12 of the sacrificial layer 11 facing away from the semiconductor layer stack 3 (within experimental accuracy) is substantially co-planar with the growth substrate 2 .

[0110] The deposition of the sacrificial layer 11 can for example comprise a spinning , sputtering , or spraying of the sacrificial layer material on the exposed surface ( s ) of the optoelectronic device . The planarization of the sacrificial layer 11 can comprise a mechanical planarization such as for example grinding and / or polishing, a chemical planarization using for example an etchant , a chemical mechanical polishing ( CMP ) , or by melting and / or pressing molten or low viscous sacrificial layer material on the surface the exposed surface ( s ) . In case of molten / liquid sacrificial layer material being deposited the exposed surface ( s ) , the step of planarization can be dispensed with in such that the planarization can take place over time by itself as the molten sacrificial layer material levels itself over time .

[0111] The sacrificial layer 11 is then in a subsequent step structured to provide recess ( es ) 13 in the sacrificial layer 11 . Due to structuring the sacrificial layer 11 , thereby generating the recess ( es ) 13 , a portion of the buried carrier layer 19 ( see Fig . I DA) and / or a portion of the first contact element 16 ( see Fig . 10B ) is exposed . The area being exposed is dependent on the position where a holing structure is desired to be later provided . In the embodiment shown, only a portion of the buried carrier layer 19 or a portion of the first contact element 16 is exposed, however it can also be conceivable to expose other areas as well as other material or material combinations .

[0112] As shown in figure 11A, a bond layer 14 is then provided on the sacrificial layer 11 and into the recess ( es ) 13 . In the embodiment shown, the bond layer 14 forms an even surface opposite the semiconductor layer stack 3 . The bond layer 14 can for example comprise an organic material , a gold alloy or can be a ( thin film) solder material or combinations thereof . The composition of the bond layer 10 is however different form the sacrificial layer 11 and selected such that an etchant used for removing the sacrificial layer 11 does not or not substantially affect the bond layer 11 , the first and second contact element 16 , 7 , the material layer 10 and any other exposed surface ( s ) of the semiconductor layer stack 3 . The bond layer 14 can for example be provided by means of a spin-on process or sputtering the material of the bond layer 14 onto the sacrificial layer 11 and into the recess ( es ) 13 . The bond layer material within the recesses 13 contacting the exposed portion ( s ) of the buried carrier layer 19 or the portion of the first contact element 16 together with the rest of the bond layer 14 forms a later holding structure 18 for the optoelectronic device ( s ) .

[0113] A temporary carrier 15 is then attached to the bond layer 14 , for example by means of bonding . After the attachment of the temporary carrier 15 , the growth substrate 2 as well as a potential buffer layer is removed, as shown in figure 11B , to expose the light emitting surface 17 of the semiconductor layer stack 2 , in particular the first layer 4 . The semiconductor layer stack 3 , in particular the first layer 4 can, if necessary be thinned to remove a connected residue of the first layer 4 . By means of this , the semiconductor layer stack portions later forming an optoelectronic device can be singulated and access to the sacrificial layer 11 is provided . The growth substrate removal and / or thinning can for example comprise LLO, grinding, dry etching, wet etching, CMP , or combinations thereof . After the step of thinning , portions of the semiconductor layer stack 3 are separated each exposing a light emitting surface 17 of the semiconductor layer stack portions .

[0114] The sacrificial layer 11 is then removed to expose the optoelectronic devices 1 attached to the holding structure 18 as shown in two embodiments in figures 12A and 12B . Due to the good accessibility of the sacrificial layer 11 , also in the region between the bond layer 14 and the semiconductor layer stack 3 , the sacrificial layer 11 can easily be removed . The removal of the sacrificial layer 11 can for example be done by one of dry-etching, wet-etching or plasma-etching . The selected removal process thereby depends on the combination of the material of the material layer 10 , the first and second contact element 16 , 7 as well as the material of the bond layer 14 . The optoelectronic device 1 is then held by the holding structure 18 , defining a specific adhesion force at the interface between the holding structure 18 and the first contact element 7 . This will allow an easy subsequent transfer process onto a target substrate .

[0115] The holding structure 18 can also be configured to be arranged contacting the material layer 10 and / or the first and / or the second contact element 16 , 7 at one , two or even more positions of the optoelectronic device 1 . The holding structure 18 can for example be configured to be arranged contacting the first contact element 16 at a side surface or at side surfaces of the optoelectronic device 1 . The holding structure 18 can also be configured to be arranged contacting two or more optoelectronic devices 1 at a time for example contacting the first contact element 16 at a side surface of the optoelectronic devices 1 . These embodiments are however only to be understood as exemplary and shall not be limiting in any way . The described structures can for example be combined or changed in any possible way .

[0116] Figures 13A and 14A show each a top view of an embodiment of an optoelectronic device 1 in accordance with some aspects of the proposed principle , when vied in a direction perpendicular onto the bottom surface . Figures 13B, 13C and 14B on the other hand show a possible contact scheme of the respective optoelectronic device 1 on contact pads 20 & 21 on for example a target substrate .

[0117] As shown in figures 13A and 13B , the first contact element and in particular the first contact pad 16c of the first contact element is of a ring-like structure covering the outer area / edge area of the backside of the optoelectronic device 1 . The second contact element and in particular the second contact pad 7 c is arranged centred of the ring like structure distant from the first contact pad 16c and electrically isolated from the same by means of the material layer 10 . The embodiments shown relate for example to an optoelectronic device shown in cross section in figure 12A, with a portion of the buried carrier layer 19 being exposed at the outer edge of the semiconductor layer stack . The first contact element in this embodiment thus does not extend along the third side wall portions .

[0118] The optoelectronic device 1 shown in figure 13A comprises a square footprint , whereas the optoelectronic device 1 shown in figure 14A comprises a rectangular footprint . This can lead for example to the structure shown with a circular / round second contact pad 7 c ( Fig . 13A) or an ellipsoid second contact pad 7 c ( Fig . 14A) .

[0119] Figures 13B , 13C and 14B on the other hand show a possible contact scheme of the respective optoelectronic device 1 on contact pads 20 & 21 on for example a target substrate . As shown in figures 13B and 14B the contact pads 20 & 21 can be arranged adj acent to each other , two first contact pads each contacting the first contact pad 16c of the optoelectronic device 1 and one middle contact pad 21 contacting the second contact pad 7 c of the optoelectronic device . Figure 13C shows an embodiment of a ring like first contact element 20 contacting the first contact pad 16c of the optoelectronic device 1 and a circular middle contact pad 21 contacting the second contact pad 7 c of the optoelectronic device with the first and second contact pad 20 & 21 being electrically isolated by means of an isolation 22 .

[0120] LIST OF REFERENCES optoelectronic device growth substrate semiconductor layer stack first layer second layer active region contact element a contact layer b reflective layer c contact pad bottom surface a , 9b , 9c side wall portion 0 material layer 1 sacrificial layer 2 even surface 3 recess 4 bond layer 5 temporary carrier 6 contact element 6a contact layer 6b reflective layer 6c contact pad 7 light emitting surface8 holding structure 9 buried contact layer 0 contact pad 1 contact pad 2 isolation

Claims

CLAIMS1. Optoelectronic device (1) , in particular pLED, comprising: a semiconductor layer stack (3) of at least a first layer (4) of a first conductivity type, a second layer (5) of a second conductivity type as well as an active region (6) between the first and second layer (4, 5) , the first layer (4) comprising a buried contact layer (19) arranged between the active region (5) and a light emitting surface (17) of the semiconductor layer stack (2) in particular formed by the first layer (4) , wherein the semiconductor layer stack (3) comprises: a bottom surface (8) opposite the light emitting surface (17) ; first side wall portions (9a) extending from the bottom surface (8) into the direction of the light emitting surface (17) until a level between the active region (6) and the buried contact layer (19) ; second side wall portions (9b) extending from a level between the active region (6) and the buried contact layer (19) until the buried contact layer (19) ; and third side wall portions (9c) different from the first and second side wall portions (9a, 9b) extending from the buried contact layer (19) into the direction of the light emitting surface (17) ; a material layer (10) covering at least portions of the first side wall portions (9a) and in particular portions of the bottom surface ( 8 ) ; a first contact element (16) covering at least portions of the material layer (10) and at least portions of the second side wall portions (9b) and electrically contacting the buried contact layer (19) ; and a second contact element (7) electrically contacting the bottom surface (8) .

2. Optoelectronic device according to claim 1,wherein the first contact element (16) electrically contacts the buried contact layer (19) from a side facing away from the light emitting surface (17) .

3. Optoelectronic device according to claim 1 or 2, wherein the light emitting surface (17) is free of a metal and / or conductive oxide material.

4. Optoelectronic device according to any one of the preceding claims, wherein the first side wall portions (9a) extend until the same level as the level from which the second side wall portions (9b) extend until the buried contact layer (19) .

5. Optoelectronic device according to any one of the preceding claims, wherein the third side wall portions (9c) extend from the buried contact layer (19) until the light emitting surface (17) .

6. Optoelectronic device according to any one of the preceding claims, wherein the first side wall portions (9a) comprise portions of the first layer (4) , the second layer (5) and the active region (6) , but in particular not the buried contact layer (19) .

7. Optoelectronic device according to any one of the preceding claims, wherein the second side wall portions (9b) comprise portions of the first layer (4) , but in particular not the buried contact layer (19) .

8. Optoelectronic device according to any one of the preceding claims, wherein the third side wall portions (9c) comprise portions of the buried contact layer (19) .

9. Optoelectronic device according to any one of the preceding claims, wherein adjacent first side wall portions (9a) and second side wall portions (9b) are laterally distant from each other and / or wherein adjacent second side wall portions (9b) and third side wall portions (9c) are laterally distant from each other.

10. Optoelectronic device according to any one of the preceding claims, wherein the first side wall portions (9a) and / or the second side wall portions (9b) and / or the third side wall portions (9c) are inclined .

11. Optoelectronic device according to any one of the preceding claims, wherein the material layer (10) comprises: a regrowth layer covering the first side wall portions (9a) ; and / or a dielectric layer arranged between the first and second contact element (16, 7) and / or between the bottom surface (8) and the first contact element (16) and / or between the first side wall portions (9a) and the first contact element (16) .

12. Optoelectronic device according to any one of the preceding claims, wherein the first contact element (16) comprises: a first contact layer (16a) arranged on the material layer (10) and the second side wall portions (9b) , the first contact layer (16a) electrically contacting the buried contact layer (19) ; and / or a first reflective layer (16b) arranged on the first contact layer (16a) and / or the material layer (10) ; and / or a first contact pad (16c) arranged on the first contact layer (16a) , the reflective layer (16b) and / or the material layer (10) , the first contact pad (16c) electrically contacting the first contact layer (16a) and / or the buried contact layer (19) .

13. Optoelectronic device according to any one of the preceding claims, wherein the second contact element (7) comprises: a second contact layer (7a) arranged on the bottom surface ( 8 ) ; and / or a second reflective layer (7b) arranged on the second contact layer (7a) or the bottom surface (8) ; and / or a second contact pad (7c) arranged on the second contact layer (7a) , the second reflective layer (7b) or the bottom surface (8) .

14. Optoelectronic device according to any one of the preceding claims,wherein the first contact element (16) covers at least portions of the third side wall portions (9c) .

15. Optoelectronic device according to any one of the preceding claims, wherein the first contact pad (16c) laterally encloses the second contact pad (7c) in a circumferential direction, wherein the material layer (10) isolates the first and second contact pad (16c, 7c) from each other.

16. Method for manufacturing an optoelectronic device (1) comprising the steps :Providing a semiconductor layer stack (3) of at least a first layer (4) of a first conductivity type, a second layer (5) of a second conductivity type as well as an active region (6) between the first and second layer (4, 5) , on a growth substrate (2) , the first layer (4) comprising a buried contact layer (19) arranged between the active region (6) and the growth substrate (2) ;Structuring the semiconductor layer stack (3) such that the structured semiconductor layer stack (3) comprises a bottom surface (8) and first side wall portions (9a) extending from the bottom surface (8) into a direction away from the bottom surface (8) until a level between the active region (6) and the buried contact layer (19) ;Providing a second contact element (7) electrically contacting the bottom surface (8) ;Providing a material layer (10) covering at least portions of the first side wall portions (9a) and / or covering at least portions of the second contact element (7) and in particular covering portions of the bottom surface (8) ;Structuring the semiconductor layer stack (3) such that the structured semiconductor layer stack (3) comprises second side wall portions (9b) extending from a level between the active region (6) and the buried contact layer (19) until the buried contact layer (19) ;Providing a first contact element (16) covering at least portions of the material layer (10) and / or at least portions ofthe second side wall portions (9b) and electrically contacting the buried contact layer (19) ; andStructuring the semiconductor layer stack (3) such that the structured semiconductor layer stack (3) comprises third side wall portions (9c) different from the first and second side wall portions (9a, 9b) extending from the buried contact layer (19) into the direction of the light emitting surface (17) .

17. The method according to claim 15 further comprising at least one of the steps : depositing a sacrificial layer (11) at least partially covering the first and / or second contact element (16, 7) and / or the material layer (10) ; structuring the sacrificial layer (11) to form a recess (13) thereby exposing a portion of first and / or second contact element (16, 7) and / or the material layer (10) and / or the semiconductor layer stack (3) ; depositing a bond layer (14) into the recess (13) ; attaching a temporary carrier (15) to the bond layer (14) ; removing the growth substrate (2) , thereby exposing portions of the sacrificial layer (11) and / or the semiconductor layer stack (3) ; removing the sacrificial layer (11) , in particular by one of dry-etching, wet-etching, plasma-etching or dissolving in a solvent; and lifting off the optoelectronic device (1) attached to the bond layer ( 14 ) .

18. The method according to claim 15 or 16 wherein the step of providing the first contact element (16) comprises: providing a first contact layer (16a) on the material layer (10) and / or the second side wall portions (9b) , the first contact layer (16a) electrically contacting the buried contact layer (19) ; and / or providing a first reflective layer (16b) on the first contact layer (16a) and / or the material layer (10) ; and / orproviding a first contact pad (16c) on the first contact layer (16a) , the first reflective layer (16b) and / or the material layer (10) , the first contact pad (16c) electrically contacting the first contact layer (16a) and / or the buried contact layer (19) .

19. The method according to any one of claims 15 to 17 wherein the step of providing the second contact element (7) comprises: providing a second contact layer (7a) on the bottom surface ( 8 ) ; and / or providing a second reflective layer (7b) on the second contact layer (7a) or the bottom surface (8) ; and / or providing a second contact pad (7c) on the second contact layer (7a) , on the second reflective layer (7b) or on the bottom surface ( 8 ) .

20. The method according to any one of claims 15 to 18 wherein the step of providing the material layer (10) comprises: providing a regrowth layer on the first side wall portions (9a) ; and / or providing a dielectric layer between the first and second contact element (16, 7) and / or between the bottom surface (8) and the first contact element (16) and / or between the first side wall portions (9a) and the first contact element (16) .

21. The method according to any one of claims 15 to 19 wherein the step of providing the first contact element (16) comprises covering at least portions of the third side wall portions (9c) .

22. Array of optoelectronic devices (1) processed by a method according to any of claims 15 to 20, wherein in particular the sacrificial layer (11) is removed exposing bond layer material (14) forming a holding structure (18) ; and wherein in particular the holding structure (18) is attached to a respective optoelectronic device (18) .

23. Array of optoelectronic devices (1) according to claim 22,wherein the holding structure (18) is attached to the buried contact layer (19) and / or the first contact pad (16c) laterally offset the bottom surface (8) .

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