Demultiplexing circuit and control method therefor, and display device

Abstract

The present application provides a demultiplexing circuit and a control method therefor, and a display device. The demultiplexing circuit comprises at least one demultiplexing module and a switch control module, wherein a compensation unit of each demultiplexing unit in the demultiplexing module is coupled to the potential of an output end of a data writing transistor on the basis of a clock signal received by a control end of the data writing transistor, and an output end of each switch control unit of the switch control module is electrically connected to the control end of the data writing transistor comprised in one demultiplexing unit.

Description

Demultiplexing circuit, control method thereof, and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a demultiplexing circuit and a control method thereof, and a display device. Background Art

[0002] Demultiplexers are widely used in display devices because they can decompose a single signal channel into multiple output channels. Using a demultiplexer can reduce the number of display signal channels required by a display device, thereby reducing the number of data driver chips and lowering the cost of display device manufacturing. However, because the demultiplexer needs to write more signals in the same amount of time, the transistors responsible for writing the signals experience greater voltage and current stress, accelerating the aging of the demultiplexer, causing the transistor threshold voltage to shift positively, and ultimately leading to failure. Technical issues

[0003] The embodiments of the present application provide a demultiplexing circuit and a control method thereof, and a display device, which can improve the problem of positive drift of the threshold voltage of the data writing transistor responsible for signal writing. Technical Solutions

[0004] An embodiment of the present application provides a demultiplexing circuit, comprising at least one demultiplexing module and a switch control module. Each demultiplexing module is electrically connected to an input signal line and multiple output signal lines. Each demultiplexing module includes multiple demultiplexing units. Each demultiplexing unit includes a data write transistor and a compensation unit electrically connected to the data write transistor. The output end of the data write transistor is electrically connected to the corresponding output signal line. The switch control module includes multiple switch control units electrically connected to the switch control line. Each switch control unit is electrically connected to a clock signal line. The output end of each switch control unit is electrically connected to the control end of the data write transistor of the demultiplexing unit. Each switch control unit is configured to output a clock signal transmitted by the clock signal line to the control end of the corresponding data write transistor according to a switch control signal transmitted by the switch control line. The compensation unit of each demultiplexing unit is configured to detect the threshold voltage of the data write transistor and receive a corresponding compensation control signal to compensate for the threshold voltage of the data write transistor.

[0005] An embodiment of the present application also provides a control method for a demultiplexing circuit, which is configured to control any of the above-mentioned demultiplexing circuits, including the switch control module outputting the clock signal transmitted by the clock signal line to the control end of the data write transistor included in the corresponding demultiplexing unit according to the switch control signal transmitted by the switch control line, so as to reset the control end potential of the data write transistor included in the corresponding demultiplexing unit; the switch control module outputting the clock signal to the control end of the data write transistor included in the corresponding demultiplexing unit according to the switch control signal, so as to detect the threshold voltage of the data write transistor through the compensation unit included in the demultiplexing unit; the compensation unit of the demultiplexing unit compensates the threshold voltage of the data write transistor according to the corresponding compensation control signal.

[0006] The present application also provides a display device, comprising any of the above-mentioned demultiplexing circuits. Beneficial effects

[0007] Compared to the prior art, embodiments of the present application provide a demultiplexing circuit, a control method thereof, and a display device. The demultiplexing circuit includes at least one demultiplexing module and a switch control module. Each demultiplexing unit included in the demultiplexing module includes a data write transistor. The switch control module includes an output terminal of each switch control unit electrically connected to the control terminal of the data write transistor included in a demultiplexing unit, so as to transmit a clock signal to the control terminal of the data write transistor included in the corresponding demultiplexing unit via the switch control unit to reset the control terminal potential of the data write transistor included in the corresponding demultiplexing unit. Each demultiplexing unit includes a compensation unit that couples the output terminal potential of the data write transistor based on the clock signal received at the control terminal of the data write transistor to detect the threshold voltage of the data write transistor, and then compensates the threshold voltage of the data write transistor based on a corresponding compensation control signal. This internal compensation for threshold voltage drift of the data write transistor is achieved, thereby alleviating the problem of positive threshold voltage drift of the data write transistor responsible for signal writing and extending the operating life of the demultiplexing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] 1A to 1C are schematic structural diagrams of a demultiplexing circuit provided in an embodiment of the present application;

[0009] FIG2 is a flow chart of a method for controlling a demultiplexing circuit according to an embodiment of the present application;

[0010] FIG3 is a timing diagram of a demultiplexing circuit provided in an embodiment of the present application;

[0011] FIG4 is a schematic structural diagram of a display device provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0012] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0013] Specifically, FIG. 1A to FIG. 1C are schematic structural diagrams of a demultiplexing circuit provided in an embodiment of the present application. The embodiment of the present application provides a demultiplexing circuit, including at least one demultiplexing module 10 and a switch control module 20 .

[0014] Each of the demultiplexing modules 10 is electrically connected to an input signal line IL and multiple output signal lines OL. Each of the demultiplexing modules 10 is configured to convert an input signal IS transmitted by the input signal line IL into multiple output signals, and the multiple output signals are output through the multiple output signal lines OL.

[0015] Each demultiplexing module 10 includes a plurality of demultiplexing units 101. Each demultiplexing unit 101 includes a data writing transistor Tda and a compensation unit 101a electrically connected to the data writing transistor Tda. Optionally, the output end of the data writing transistor Tda is electrically connected to the corresponding output signal line OL.

[0016] The switch control module 20 includes a plurality of switch control units 201 electrically connected to a switch control line SiL. Each of the switch control units 201 is electrically connected to a clock signal line CKL. The output end of each switch control unit 201 is electrically connected to a demultiplexing unit 101. Each switch control unit 201 of the switch control module 20 is configured to output a clock signal CK transmitted by the clock signal line CKL to the corresponding demultiplexing unit 101 according to a switch control signal Si transmitted by the switch control line SiL.

[0017] Optionally, the output terminal of each switch control unit 201 is electrically connected to the control terminal of the data write transistor Tda of a demultiplexing unit 101, so that each switch control unit 201 is configured to transmit a clock signal CK to the control terminal of the corresponding data write transistor Tda according to the switch control signal Si, thereby resetting the control terminal potential of the data write transistor Tda via the clock signal CK. The compensation unit 101a of each demultiplexing unit 101 is configured to couple the output terminal potential of the data write transistor Tda according to the clock signal CK received at the control terminal of the data write transistor Tda, thereby detecting the threshold voltage of the data write transistor Tda and receiving a corresponding compensation control signal E. The compensation unit 101a then compensates the threshold voltage of the data write transistor Tda according to the corresponding compensation control signal E, thereby achieving internal compensation for threshold voltage drift of the data write transistor Tda, improving the problem of positive threshold voltage drift of the data write transistor Tda responsible for signal writing, and extending the service life of the demultiplexing circuit.

[0018] Optionally, please continue to refer to FIG. 1A to FIG. 1C , the compensation unit 101 a includes a compensation transistor Tc and a first capacitor Cst.

[0019] The input end of the compensation transistor Tc is electrically connected to the corresponding input signal line IL, the output end of the compensation transistor Tc is electrically connected to the input end of the data writing transistor Tda, and the control end of the compensation transistor Tc receives the corresponding compensation control signal E.

[0020] A first end of the first capacitor Cst is electrically connected to the control end of the data writing transistor Tda, and a second end of the first capacitor Cst is electrically connected to the output end of the data writing transistor Tda.

[0021] In which, the clock signal CK received by the control end of the data write transistor Tda can be coupled to the output end of the data write transistor Tda through the first capacitor Cst, so as to extract the threshold voltage of the data write transistor Tda through the clock signal CK and the compensation unit 101a, and store the threshold voltage of the data write transistor Tda through the first capacitor Cst.

[0022] Optionally, please continue to refer to Figures 1A to 1C. The switch control module 20 includes a switch transistor Ts, the control end of the switch transistor Ts is electrically connected to the switch control line SiL, the input end of the switch transistor Ts is electrically connected to the corresponding clock signal line CKL, and the output end of the switch transistor Ts is electrically connected to the control end of the data write transistor Tda of the corresponding demultiplexing unit 101.

[0023] Optionally, in order to accurately detect the threshold voltage of the data writing transistor Tda, the demultiplexing circuit also includes a potential reset module 30, and the potential reset module 30 includes a plurality of potential reset units 301 electrically connected to the reset control line RcL, each of the potential reset units 301 is electrically connected to a reset signal line ReL, and the output end of each of the potential reset units 301 is electrically connected to a demultiplexing unit 101, and each of the potential reset units 301 of the potential reset module 30 is configured to output the reset signal Re transmitted by the reset signal line ReL to the corresponding demultiplexing unit 101 according to the reset control signal Rc transmitted by the reset control line RcL.

[0024] Optionally, the output end of each of the potential reset units 301 is electrically connected to the output end of the data write transistor Tda of the demultiplexing unit 101, so that each of the potential reset units 301 is configured to transmit the reset signal Re to the output end of the corresponding data write transistor Tda, so as to reset the output end potential of the data write transistor Tda through the reset signal Re, and then when the compensation unit 101a detects the threshold voltage of the data write transistor Tda, it can have a more stable potential basis.

[0025] Optionally, please continue to refer to Figures 1A to 1C. Each of the reset units 301 includes a reset transistor Ti, the control end of the reset transistor Ti is electrically connected to the reset control line RcL, the input end of the reset transistor Ti is electrically connected to the corresponding reset signal line ReL, and the output end of the reset transistor Ti is electrically connected to the output end of the data write transistor Tda of the corresponding demultiplexing unit 101.

[0026] Optionally, in order to improve the impact of the potential change of the control end of the data writing transistor Tda on the potential stability state of the output end of the data writing transistor Tda, the demultiplexing circuit also includes a potential stabilization unit, which is electrically connected to the output end of the data writing transistor Tda to stabilize the potential of the output end of the data writing transistor Tda.

[0027] Optionally, please continue to refer to Figures 1A to 1C. The potential stabilization unit includes a second capacitor Ca, a first end of the second capacitor Ca is electrically connected to the output end of the data writing transistor Tda, and a second end of the second capacitor Ca is electrically connected to the corresponding input signal line IL.

[0028] Optionally, please continue to refer to FIG. 1A to FIG. 1C , and take a demultiplexing module 10 including two demultiplexing units 101 as an example to illustrate the connection between the demultiplexing unit 101 and the switch control unit 201 and the potential resetting unit 301 .

[0029] The plurality of reset units 301 include a first reset unit 3011 and a second reset unit 3012 electrically connected to the reset control line RcL. The first reset unit 3011 is electrically connected to a first reset signal line ReL1, and the second reset unit 3012 is electrically connected to a second reset signal line ReL2. The first reset signal line ReL1 transmits a first reset signal Re1, and the second reset signal line ReL2 transmits a second reset signal Re2.

[0030] The plurality of switch control units 201 include a first switch control unit 2011 and a second switch control unit 2012 electrically connected to the switch control line SiL. The first switch control unit 2011 is electrically connected to a first clock signal line CKL1, and the second switch control unit 2012 is electrically connected to a second clock signal line CKL2. The first clock signal line CKL1 transmits a first clock signal CK1, and the second clock signal line CKL2 transmits a second clock signal CK2.

[0031] The demultiplexing module 10 includes a first demultiplexing module 10a. The first demultiplexing module 10a includes a plurality of demultiplexing units 101, including at least a first demultiplexing unit 1011 and a second demultiplexing unit 1012. The first demultiplexing unit 1011 is electrically connected to a first input signal line IL1 and a first output signal line OL1, and the second demultiplexing unit 1012 is electrically connected to the first input signal line IL1 and the second output signal line OL2. The first input signal line IL1 transmits a first input signal IS1, the first output signal line OL1 transmits a first output signal, and the second output signal line OL2 transmits a second output signal.

[0032] Optionally, the first demultiplexing unit 1011 is electrically connected between the output end of the first switch control unit 2011 and the output end of the first reset unit 3011, and the compensation unit 101a of the first demultiplexing unit 1011 is configured to receive a first compensation control signal E1; the second demultiplexing unit 1012 is electrically connected between the output end of the second switch control unit 2012 and the output end of the second reset unit 3012, and the compensation unit 101a of the second demultiplexing unit 1012 is configured to receive a second compensation control signal E2.

[0033] Optionally, the input terminal of the switching transistor Ts1 included in the first switching control unit 2011 is electrically connected to the first clock signal line CKL1, and the output terminal of the switching transistor Ts1 included in the first switching control unit 2011 is electrically connected to the output terminal of the first switching control unit 2011. The input terminal of the reset transistor Ti1 included in the first reset unit 3011 is electrically connected to the first reset signal line ReL1, and the output terminal of the reset transistor Ti1 included in the first reset unit 3011 is electrically connected to the output terminal of the first reset unit 3011. The control terminal of the data writing transistor Tda1 included in the first demultiplexing unit 1011 is electrically connected to the output terminal of the first switching control unit 2011, and the output terminal of the data writing transistor Tda1 included in the first demultiplexing unit 1011 is electrically connected to the output terminal of the first reset unit 3011.

[0034] The input terminal of the switch transistor Ts2 included in the second switch control unit 2012 is electrically connected to the second clock signal line CKL2, and the output terminal of the switch transistor Ts2 included in the second switch control unit 2012 is electrically connected to the output terminal of the second switch control unit 2012. The input terminal of the reset transistor Ti2 included in the second reset unit 3012 is electrically connected to the second reset signal line ReL2, and the output terminal of the reset transistor Ti2 included in the second reset unit 3012 is electrically connected to the output terminal of the second reset unit 3012. The control terminal of the data write transistor Tda2 included in the second demultiplexing unit 1012 is electrically connected to the output terminal of the second switch control unit 2012, and the output terminal of the data write transistor Tda2 included in the second demultiplexing unit 1012 is electrically connected to the output terminal of the second reset unit 3012.

[0035] Optionally, in various devices employing a demultiplexing circuit, there may be application scenarios in which the input signals IS are different, but multiple output signals need to be output simultaneously (for example, when the demultiplexing circuit is applied to a display device, multiple sub-pixels in the same row may require different data signals, but the multiple sub-pixels in the same row need to be controlled to achieve display during the same time period. Therefore, the demultiplexing circuit should be able to meet the design requirement of simultaneously outputting multiple output signals to the multiple sub-pixels in the same row based on different input signals IS during the same time period). Therefore, in order to enable the demultiplexing circuit to output multiple output signals based on different input signals IS during the same time period, the demultiplexing circuit may include multiple demultiplexing modules 10, and the multiple demultiplexing modules 10 are electrically connected between the switch control module 20 and the potential reset module 30.

[0036] Taking the demultiplexing circuit including two demultiplexing modules 10 as an example, the specific connection structure of multiple demultiplexing modules 10 is described.

[0037] Specifically, please continue to refer to FIG. 1A to FIG. 1C , the demultiplexing module 10 includes the first demultiplexing module 10 a and the second demultiplexing module 10 b .

[0038] The plurality of demultiplexing units 101 included in the second demultiplexing module 10b include at least a third demultiplexing unit 1013 and a fourth demultiplexing unit 1014. The third demultiplexing unit 1013 is electrically connected to the second input signal line IL2 and the third output signal line OL3, and the fourth demultiplexing unit 1014 is electrically connected to the second input signal line IL2 and the fourth output signal line OL4. The second input signal line IL2 transmits a second input signal IS2, the third output signal line OL3 transmits a third output signal, and the fourth output signal line OL4 transmits a fourth output signal.

[0039] Optionally, the third demultiplexing unit 1013 is electrically connected between the output end of the first switch control unit 2011 and the output end of the first reset unit 3011, and the compensation unit 101a of the third demultiplexing unit 1013 is configured to receive the first compensation control signal E1; the fourth demultiplexing unit 1014 is electrically connected between the output end of the second switch control unit 2012 and the output end of the second reset unit 3012, and the compensation unit 101a of the fourth demultiplexing unit 1014 is configured to receive the second compensation control signal E2.

[0040] Specifically, the control end of the data writing transistor Tda3 included in the third demultiplexing unit 1013 is electrically connected to the output end of the first switch control unit 2011, so that the control end of the data writing transistor Tda1 included in the first demultiplexing unit 1011 and the control end of the data writing transistor Tda3 included in the third demultiplexing unit 1013 are electrically connected, so that the first clock signal CK1 is simultaneously transmitted to the control end of the data writing transistor Tda1 included in the first demultiplexing unit 1011 and the control end of the data writing transistor Tda3 included in the third demultiplexing unit 1013 through the first switch control unit 2011, so that the data writing transistor Tda1 included in the first demultiplexing unit 1011 and the data writing transistor Tda3 included in the third demultiplexing unit 1013 are synchronously turned on or off.

[0041] The output end of the data write transistor Tda3 included in the third demultiplexing unit 1013 is electrically connected to the output end of the first reset unit 3011, so that the output end of the data write transistor Tda1 included in the first demultiplexing unit 1011 and the output end of the data write transistor Tda3 included in the third demultiplexing unit 1013 are electrically connected, so that the first reset signal Re1 is simultaneously transmitted to the output end of the data write transistor Tda1 included in the first demultiplexing unit 1011 and the output end of the data write transistor Tda3 included in the third demultiplexing unit 1013 through the first potential reset unit 301, so as to simultaneously reset the output end potential of the data write transistor Tda1 included in the first demultiplexing unit 1011 and the output potential of the data write transistor Tda3 included in the third demultiplexing unit 1013.

[0042] The control end of the data writing transistor Tda4 included in the fourth demultiplexing unit 1014 is electrically connected to the output end of the second switch control unit 2012, so that the control end of the data writing transistor Tda2 included in the second demultiplexing unit 1012 and the control end of the data writing transistor Tda4 included in the fourth demultiplexing unit 1014 are electrically connected, so that the second clock signal CK2 is simultaneously transmitted to the control end of the data writing transistor Tda2 included in the second demultiplexing unit 1012 and the control end of the data writing transistor Tda4 included in the fourth demultiplexing unit 1014 through the second switch control unit 2012, so that the data writing transistor Tda2 included in the second demultiplexing unit 1012 and the data writing transistor Tda4 included in the fourth demultiplexing unit 1014 are synchronously turned on or off.

[0043] The output end of the data write transistor Tda4 included in the fourth demultiplexing unit 1014 is electrically connected to the output end of the second reset unit 3012, so that the output end of the data write transistor Tda4 included in the fourth demultiplexing unit 1014 and the output end of the data write transistor Tda2 included in the second demultiplexing unit 1012 are electrically connected, so that the second reset signal Re2 is simultaneously transmitted to the output end of the data write transistor Tda2 included in the second demultiplexing unit 1012 and the output end of the data write transistor Tda4 included in the fourth demultiplexing unit 1014 through the second potential reset unit 301, so as to simultaneously reset the output end potential of the data write transistor Tda2 included in the second demultiplexing unit 1012 and the output potential of the data write transistor Tda4 included in the fourth demultiplexing unit 1014.

[0044] By making the first demultiplexing unit 1011 and the third demultiplexing unit 1013 simultaneously receive the first clock signal CK1 and the first reset signal Re1, the first demultiplexing unit 1011 and the third demultiplexing unit 1013 can synchronously reset the potentials of the control terminal and the output terminal of the data write transistor Tda and detect the threshold voltage. By making the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 simultaneously receive the second clock signal CK2 and the second reset signal Re2, the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 can synchronously reset the potentials of the control terminal and the output terminal of the data write transistor Tda and detect the threshold voltage. By having the first demultiplexing unit 1011 and the second demultiplexing unit 1012 share the first input signal IS1, and the third demultiplexing unit 1013 and the fourth demultiplexing unit 1014 share the second input signal IS2, the first input signal IS1 can be decomposed into the first output signal and the second output signal by the first demultiplexing unit 1011 and the second demultiplexing unit 1012, and the second input signal IS2 can be decomposed into the third output signal and the fourth output signal by the third demultiplexing unit 1013 and the fourth demultiplexing unit 1014. By having the first demultiplexing unit 1011 and the third demultiplexing unit 1013 share the first compensation control signal E1, and the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 share the first compensation control signal E1, the first output signal and the third output signal can be output at the same time period, and the second output signal and the fourth output signal can be output at the same time period.

[0045] It is understandable that, in this application, the demultiplexing circuit includes two demultiplexing modules 10, and the demultiplexing module 10 includes two demultiplexing units 101. The description of the connection form between the demultiplexing modules 10 and the connection form between the demultiplexing units 101 is not intended to limit the number of the demultiplexing modules 10 included in the demultiplexing circuit, nor is it intended to limit the number of demultiplexing units 101 included in the demultiplexing module 10. That is, the demultiplexing circuit may include m demultiplexing modules 10, and each demultiplexing module 10 may include n demultiplexing units 101. Wherein, m ≥ 2, n ≥ 2.

[0046] If the demultiplexing circuit further includes a third demultiplexing module 10, the multiple demultiplexing units 101 included in the first demultiplexing module 10a further include a fifth demultiplexing unit 1015, and the multiple demultiplexing units 101 included in the second demultiplexing module 10b further include a sixth demultiplexing unit 1016. Accordingly, the multiple reset units 301 further include a third reset unit 3013 electrically connected to the reset control line RcL, and the third reset unit 3013 is electrically connected to the third reset signal line ReL3. The multiple switch control units 201 further include a third switch control unit 2013 electrically connected to the switch control line SiL, and the third switch control unit 2013 is electrically connected to the third clock signal line CKL3.

[0047] The compensation unit 101a of the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 is configured to receive a third compensation control signal E3; an input terminal of the switch transistor Ts3 included in the third switch control unit 2013 is electrically connected to the third clock signal line CKL3, and an output terminal of the switch transistor Ts3 included in the third switch control unit 2013 is electrically connected to an output terminal of the third switch control unit 2013. An input terminal of the reset transistor Ti3 included in the third reset unit 3013 is electrically connected to the third reset signal line ReL3, and an output terminal of the reset transistor Ti3 included in the third reset unit 3013 is electrically connected to an output terminal of the third reset unit 3013. The control end of the data writing transistor Tda5 included in the fifth demultiplexing unit 1015 and the control end of the data writing transistor Tda6 included in the sixth demultiplexing unit 1016 are electrically connected to the output end of the third switch control unit 2013, and the output end of the data writing transistor Tda5 included in the fifth demultiplexing unit 1015 and the output end of the data writing transistor Tda6 included in the sixth demultiplexing unit 1016 are electrically connected to the output end of the third reset unit 3013.

[0048] Optionally, the number of the demultiplexing modules 10 and the demultiplexing units 101 included in the demultiplexing circuit may be determined in combination with various devices applying the demultiplexing circuit.

[0049] If the demultiplexing circuit is applied to a display device, the number of the demultiplexing modules 10 and the demultiplexing units 101 included in the demultiplexing circuit may be determined in combination with the arrangement of pixels in the display panel.

[0050] Optionally, in a display device to which the demultiplexing circuit is applied, each row includes X pixels, and each of the pixels includes Y sub-pixels. Then, the demultiplexing circuit may include X1 demultiplexing modules 10, and each of the demultiplexing modules 10 may include Y1 demultiplexing units 101. Here, X>1, Y>1, X1≤X, and Y1≤Y. And X1<X may correspond to a case where multiple pixels share multiple output signals output by one demultiplexing module 10; Y1<Y may correspond to a case where multiple sub-pixels share an output signal output by one demultiplexing unit 101.

[0051] Optionally, each pixel includes 3 sub-pixels, and each of the demultiplexing modules 10 may include demultiplexing units 101 corresponding to the number of the sub-pixels (that is, each of the demultiplexing modules 10 may include 3 demultiplexing units 101). For example, the first demultiplexing module 10a includes the first demultiplexing unit 1011, the second demultiplexing unit 1012, and the fifth demultiplexing unit 1015, and the second demultiplexing module 10b includes the third demultiplexing unit 1013, the fourth demultiplexing unit 1014, and the sixth demultiplexing unit 1016, so as to respectively provide output signals to 3 sub-pixels through the first demultiplexing unit 1011, the second demultiplexing unit 1012, and the fifth demultiplexing unit 1015, and respectively provide output signals to 3 sub-pixels through the third demultiplexing unit 1013, the fourth demultiplexing unit 1014, and the sixth demultiplexing unit 1016.

[0052] Optionally, the first demultiplexing module 10a and the second demultiplexing module 10b may be configured to provide output signals to the sub-pixels included in different pixels.

[0053] FIG. 2 is a flowchart of a control method for a demultiplexing circuit provided by an embodiment of the present application. An embodiment of the present application further provides a control method for a demultiplexing circuit, which is configured to control any one of the above demultiplexing circuits. The control method for the demultiplexing circuit includes:

[0054] The switch control module 20 outputs the clock signal CK transmitted by the clock signal line CKL to a control end of the data writing transistor Tda included in the corresponding demultiplexing unit 101 according to the switch control signal Si transmitted by the switch control line SiL, so as to reset a potential of the control end of the data writing transistor Tda included in the corresponding demultiplexing unit 101.

[0055] The switch control module 20 outputs the clock signal CK to the control terminal of the data writing transistor Tda included in the corresponding demultiplexing unit 101 according to the switch control signal Si, so as to detect the threshold voltage of the data writing transistor Tda through the compensation unit 101a included in the demultiplexing unit 101.

[0056] The compensation unit 101 a of the demultiplexing unit 101 compensates the threshold voltage of the data writing transistor Tda according to the corresponding compensation control signal E.

[0057] As shown in Figure 3, which is a timing diagram of the demultiplexing circuit provided in an embodiment of the present application, the control method of the demultiplexing circuit is described by taking the example that the demultiplexing circuit includes the first demultiplexing module 10a and the second demultiplexing module 10b, the first demultiplexing module 10a includes the first demultiplexing unit 1011, the second demultiplexing unit 1012 and the fifth demultiplexing unit 1015, the second demultiplexing module 10b includes the third demultiplexing unit 1013, the fourth demultiplexing unit 1014 and the sixth demultiplexing unit 1016, and the switching transistor Ts, the reset transistor Ti, the data writing transistor Tda and the compensation transistor Tc are all N-type transistors.

[0058] First stage t1: the switch control signal Si, the reset control signal Rc, the first compensation control signal E1, the second compensation control signal E2, and the third compensation control signal E3 are at a high level; the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the first input signal IS1, the second input signal IS2, the first reset signal Re1, the second reset signal Re2, and the third reset signal Re3 are at a low level.

[0059] The switching transistors Ts1 to Ts3 included in the first to third switching control units 2011 to 2013 are turned on according to the switching control signal Si, the first clock signal CK1 is transmitted to the control ends of the data writing transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 via the switching transistor Ts1 included in the first switching control unit 2011, the second clock signal CK2 is transmitted to the control ends of the data writing transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 via the switching transistor Ts2 included in the second switching control unit 2012, the third clock signal CK3 is transmitted to the control ends of the data writing transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 via the switching transistor Ts2 included in the second switching control unit 2013, The switching transistor Ts3 included is transmitted to the control end of the data writing transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016, so as to reset the control end potential of the data writing transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 through the first clock signal CK1, reset the control end potential of the data writing transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 through the second clock signal CK2, and reset the control end potential of the data writing transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 through the third clock signal CK3.

[0060] The reset transistors Ti1 to Ti3 included in the first reset unit 3011 to the third reset unit 3013 are turned on according to the reset control signal Rc, and the first reset signal Re1 is transmitted to the output ends of the data writing transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 via the reset transistor Ti1 included in the first reset unit 3011. The second reset signal Re2 is transmitted to the output ends of the data writing transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 via the switching transistor Ts2 included in the second reset unit 3012. The third reset signal Re3 is transmitted to the output ends of the data writing transistors Tda4 and Tda2 included in the third reset unit 3013 via the switching transistor Ts2 included in the third reset unit 3013. The reset transistor Ti3 is transmitted to the output ends of the data write transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016, so as to reset the output end potential of the data write transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 through the first reset signal Re1, reset the output end potential of the data write transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 through the second reset signal Re2, and reset the output end potential of the data write transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 through the third reset signal Re3.

[0061] The compensation transistors Tc1 and Tc3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 are turned on according to the first compensation control signal E1, the compensation transistors Tc2 and Tc4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 are turned on according to the second compensation control signal E2, and the compensation transistors Tc5 and Tc6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 are turned on according to the third compensation control signal E3. The first input signal IS1 is converted into a positive signal by the first demultiplexing unit 1011. The compensation transistors Tc1, Tc2 and Tc5 included in the demultiplexing unit 1011, the second demultiplexing unit 1012 and the fifth demultiplexing unit 1015 are transmitted to the input ends of the corresponding write data write transistors Tda1, Tda2 and Tda5, and the second input signal IS2 is transmitted to the input ends of the corresponding write data write transistors Tda3, Tda4 and Tda6 via the third demultiplexing unit 1013, the fourth demultiplexing unit 1014 and the sixth demultiplexing unit 1016.

[0062] Second stage t2: the switch control signal Si, the first compensation control signal E1, the second compensation control signal E2, the third compensation control signal E3, the first input signal IS1, and the second input signal IS2 are at a high level; the reset control signal Rc, the second clock signal CK2, the third clock signal CK3, the first reset signal Re1, the second reset signal Re2, and the third reset signal Re3 are at a low level; the first clock signal CK1 has a first voltage value V11.

[0063] The switching transistors Ts1 to Ts3 included in the first switch control unit 2011 to the third switch control unit 2013 remain turned on, the first clock signal CK1 is transmitted to the control ends of the data writing transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013, the compensation transistors Tc1 to Tc6 included in the first demultiplexing unit 1011 to the sixth demultiplexing unit 1016 remain turned on, the first input signal IS1 is output to the input ends of the write data transistors Tda1, Tda2 and Tda5 included in the first demultiplexing unit 1011, the second demultiplexing unit 1012 and the fifth demultiplexing unit 1015, the second input signal IS2 is output to the input ends of the write data transistors Tda3, Tda4 and Tda6 included in the third demultiplexing unit 1013, the fourth demultiplexing unit 1014 and the sixth demultiplexing unit 1016, so that The potential of the control end of the data writing transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 is a first voltage value V11 (i.e., Vg_Tda1=Vs_Tda3=V11), and the potential of the output end of the data writing transistor Tda1 included in the first demultiplexing unit 1011 is the difference between the first voltage value V11 and the threshold voltage Vth_Tda1 of the data writing transistor Tda1 (i.e., Vs_Tda1=V11). -Vth_Tda1), the potential of the output terminal of the data write transistor Tda3 included in the third demultiplexing unit 1013 is the difference between the first voltage value V11 and the threshold voltage Vth_Tda3 of the data write transistor Tda3 (i.e., Vs_Tda3=V11-Vth_Tda3), and the threshold voltage of the corresponding data write transistor Tda is stored through the first capacitor Cst included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013. Wherein, Vg_Tda1 represents the potential of the control terminal of the data write transistor Tda1, Vg_Tda3 represents the potential of the control terminal of the data write transistor Tda3; Vs_Tda1 represents the potential of the output terminal of the data write transistor Tda1, and Vs_Tda3 represents the potential of the output terminal of the data write transistor Tda3.

[0064] The data write transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 are turned off according to the second clock signal CK2, and the data write transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 are turned off according to the third clock signal CK3. The reset transistors Ti1 to Ti3 included in the first reset unit 3011 to the third reset unit 3013 are turned off according to the reset control signal Rc.

[0065] The third stage t3: the switch control signal Si, the second compensation control signal E2, and the third compensation control signal E3 are at a high level; the reset control signal Rc, the first input signal IS1, the second input signal IS2, the first compensation control signal E1, the second clock signal CK2, the third clock signal CK3, the first reset signal Re1, the second reset signal Re2, and the third reset signal Re3 are at a low level; the first clock signal CK1 has a second voltage value V12, and the second voltage value V12 is greater than the first voltage value V11.

[0066] The switching transistors Ts1 to Ts3 included in the first switch control unit 2011 to the third switch control unit 2013 remain turned on, the first clock signal CK1 is transmitted to the control ends of the data writing transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013, and the compensation transistors Tc1 and Tc3 of the first demultiplexing unit 1011 and the third demultiplexing unit 1013 are turned off according to the first compensation control signal E1. The compensation transistors Tc2, Tc4, Tc5 and Tc6 included in the second demultiplexing unit 1012, the fourth demultiplexing unit 1014, the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 remain turned on, the first input signal IS1 is output to the input ends of the write data transistors Tda2 and Tda5 included in the second demultiplexing unit 1012 and the fifth demultiplexing unit 1015, and the second input signal IS2 is output to the input ends of the write data transistors Tda4 and Tda6 included in the fourth demultiplexing unit 1014 and the sixth demultiplexing unit 1016, so that the potentials of the control ends of the data write transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 are the second voltage value V12, and the data write transistors included in the first demultiplexing unit 1011 are The potential of the output end of Tda1 is Vs_Tda1=V11–Vth_Tda1+(V12-V11)·Cst1 / (Cst1+Ca1), and the potential of the output end of the data writing transistor Tda3 included in the third demultiplexing unit 1013 is Vs_Tda3=V11–Vth_Tda3+(V12-V11)·Cst3 / (Cst3+Ca3), so that the first demultiplexing unit 101 1. The potential difference between the control end and the output end of the data write transistor Tda1 included in the third demultiplexing unit 1013 is Vgs_Tda1=(V12-V11)·Ca1 / (Cst1+Ca1)+Vth_Tda1, and the potential difference between the control end and the output end of the data write transistor Tda3 included in the third demultiplexing unit 1013 is Vgs_Tda3=(V12-V11)·Ca3 / (Cst3+Ca3)+Vth_Tda3.

[0067] The data write transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 are turned off according to the second clock signal CK2, and the data write transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 are turned off according to the third clock signal CK3. The reset transistors Ti1 to Ti3 included in the first reset unit 3011 to the third reset unit 3013 are turned off according to the reset control signal Rc.

[0068] Fourth stage t4: the first input signal IS1, the second input signal IS2, the first compensation control signal E1, the second compensation control signal E2, and the third compensation control signal E3 are at a high level; the switch control signal Si, the reset control signal Rc, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the first reset signal Re1, the second reset signal Re2, and the third reset signal Re3 are at a low level.

[0069] The switching transistors Ts1 to Ts3 included in the first switch control unit 2011 to the third switch control unit 2013 are turned off, and the first compensation control signal E1 turns on the compensation transistors Tc1 and Tc3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013. The first input signal IS1 with a voltage value of IS1_H is output to the first output signal line OL1 through the compensation transistor Tc1 and the data writing transistor Tda1 included in the first demultiplexing unit 1011; the second input signal IS2 with a voltage value of IS2_H is output to the third output signal line OL3 through the compensation transistor Tc3 and the data writing transistor Tda3 included in the third demultiplexing unit 1013.

[0070] In the third stage t3, the potential difference between the control terminal and the output terminal of the data writing transistor Tda1 included in the first demultiplexing unit 1011 is Vgs_Tda1=(V12-V11)·Ca1 / (Cst1+Ca1)+Vth_Tda1. Therefore, the current flowing through the data writing transistor Tda1 included in the first demultiplexing unit 1011 in the fourth stage t4 is: I_Tda1=C ox μ n W(Vgs-Vth_Tda1) 2 / 2L=C ox μ n W((V12-V11)·Ca1 / (Cst1+Ca1)) 2 / 2L. Similarly, in the fourth stage t4, the current flowing through the data writing transistor Tda3 included in the third demultiplexing unit 1013 is: I_Tda3=C ox μ n W((V12-V11)·Ca3 / (Cst3+Ca3)) 2 Therefore, the current flowing through the data writing transistor Tda included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 is no longer affected by the threshold voltage of the data writing transistor Tda. ox 、μ n , W and L represent the channel capacitance per unit area, channel mobility, channel width and channel length, respectively.

[0071] By resetting the control end and output end potentials of the data write transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 in the first stage t1, detecting the threshold voltages of the data write transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 in the second stage t2, and compensating the threshold voltages of the data write transistors Tda1 and Tda3 included in the first demultiplexing unit 1011 and the third demultiplexing unit 1013 in the third stage t3, and by outputting the signal transmitted by the first input signal line IL1 to the first output signal line OL1 via the first demultiplexing unit 1011, and outputting the signal transmitted by the second input signal line IL2 to the third output signal line OL3 via the third demultiplexing unit 1013 in the fourth stage t4.

[0072] Similarly, in the fifth stage t5, the control end and output end potentials of the data write transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 can be reset, and in the sixth stage t6, the threshold voltage detection of the data write transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 can be implemented. In the seventh stage t7, the threshold voltage compensation of the data write transistors Tda2 and Tda4 included in the second demultiplexing unit 1012 and the fourth demultiplexing unit 1014 can be implemented. In the eighth stage t8, the signal transmitted by the first input signal line IL1 is output to the second output signal line OL2 via the second demultiplexing unit 1012, and the signal transmitted by the second input signal line IL2 is output to the fourth output signal line OL4 via the fourth demultiplexing unit 1014.

[0073] Similarly, in the ninth stage t9, the control end and output end potentials of the data write transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 can be reset, and in the tenth stage t10, the threshold voltage detection of the data write transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 can be implemented. In the eleventh stage t11, the threshold voltage compensation of the data write transistors Tda5 and Tda6 included in the fifth demultiplexing unit 1015 and the sixth demultiplexing unit 1016 can be implemented. In the twelfth stage t12, the signal transmitted by the first input signal line IL1 is output to the fifth output signal line OL5 via the fifth demultiplexing unit 1015, and the signal transmitted by the second input signal line IL2 is output to the sixth output signal line OL6 via the sixth demultiplexing unit 1016.

[0074] FIG4 is a schematic structural diagram of a display device provided in an embodiment of the present application. The present application further provides a display device comprising any of the above-mentioned demultiplexing circuits (as shown in 401 in FIG4 ).

[0075] Optionally, the display device further includes a display panel 402 and a driving module 403 electrically connected to the demultiplexing circuit.

[0076] Optionally, the display panel 402 includes a passive light-emitting display panel (such as a liquid crystal display panel, etc.) or a self-luminous display panel (such as a display panel including light-emitting devices such as organic light-emitting diodes, sub-millimeter light-emitting diodes, and micro light-emitting diodes).

[0077] The display panel 402 includes a plurality of sub-pixels Pi and a plurality of output signal lines OL electrically connected to the plurality of sub-pixels Pi.

[0078] Optionally, the display panel 402 includes a plurality of pixels, each of which includes a plurality of sub-pixels Pi. Optionally, the number of demultiplexing modules 10 included in the demultiplexing circuit 401 is less than the number of pixels included in a row of the display panel, so that the output signals received by the plurality of pixels can be generated by a corresponding demultiplexing module 10 based on the input signal IS. Optionally, the number of demultiplexing modules 10 included in the demultiplexing circuit 401 is equal to the number of pixels included in a row of the display panel, so that the output signal received by each pixel can be generated by a corresponding demultiplexing module 10 based on the input signal IS.

[0079] Optionally, the demultiplexing unit 101 included in the demultiplexing module 10 is smaller than the number of sub-pixels Pi included in the pixel, so that at least some of the multiple sub-pixels Pi included in the pixel can receive the same output signal. Optionally, the demultiplexing unit 101 included in the demultiplexing module 10 is equal to the number of sub-pixels Pi included in the pixel, so that the multiple sub-pixels Pi included in the pixel can receive different output signals.

[0080] Optionally, the plurality of sub-pixels Pi include a first sub-pixel Pi1, a second sub-pixel Pi2, and a third sub-pixel Pi3 that emit different luminous colors and are adjacent to each other. Each pixel includes the first sub-pixel Pi1, the second sub-pixel Pi2, and the third sub-pixel Pi3; the first demultiplexing module 10a is electrically connected to one pixel, and the second demultiplexing module 10b is electrically connected to another pixel. Optionally, the first output signal line OL1 is electrically connected to the first sub-pixel Pi1 of the first pixel, the second output signal line OL2 is electrically connected to the second sub-pixel Pi2 of the first pixel, and the fifth output signal line OL5 is electrically connected to the third sub-pixel Pi3 of the first pixel. The third output signal line OL3 is electrically connected to the first sub-pixel Pi1 of the second pixel, the fourth output signal line OL4 is electrically connected to the second sub-pixel Pi2 of the second pixel, and the sixth output signal line OL6 is electrically connected to the third sub-pixel Pi3 of the second pixel.

[0081] Optionally, the output signal line OL includes a data line for transmitting a data signal.

[0082] In addition, the output signal line OL may also be configured as a signal line for transmitting a scan signal, a light emitting control signal, a reset signal, etc. as required.

[0083] The driving module 403 is electrically connected to the demultiplexing circuit 401 through the input signal line IL. The driving module 403 is configured to provide an input signal IS to the demultiplexing circuit through the input signal line IL.

[0084] Optionally, the driving module 403 includes a source driver chip. In addition, the driving module may also include a gate driver chip, a timing controller, and the like.

[0085] By causing each demultiplexing unit 101 to undergo resetting the control terminal and output potential of the data write transistor Tda, threshold voltage detection, threshold voltage compensation, and transmission of the input signal IS to the output signal line OL via the compensation transistor Tc and the data write transistor Tda, the demultiplexing circuit 401 can automatically compensate for threshold voltage drift of the data write transistor Tda caused by pressures such as voltage and current, thereby extending the service life of the data write transistor Tda and, in turn, extending the operating life of the demultiplexing circuit 401. Furthermore, because the demultiplexing circuit 401 can automatically compensate for threshold voltage drift of the data write transistor Tda caused by pressures such as voltage and current, the output signals received by the multiple sub-pixels Pi in the display panel are not affected by the threshold voltage of the data write transistor Tda. This can alleviate problems such as signal write delay and decreased charging rate caused by threshold voltage drift of the data write transistor Tda in the display panel, thereby reducing costs and extending the service life of the display device.

[0086] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A demultiplexing circuit, wherein: include: At least one demultiplexing module, each of which is electrically connected to an input signal line and a plurality of output signal lines, each of which includes a plurality of demultiplexing units, each of which includes a data writing transistor and a compensation unit electrically connected to the data writing transistor, and an output end of the data writing transistor is electrically connected to the corresponding output signal line; A switch control module, comprising a plurality of switch control units electrically connected to the switch control line, each of the switch control units electrically connected to a clock signal line, and an output end of each of the switch control units electrically connected to a control end of the data writing transistor of the demultiplexing unit; Among them, each of the switch control units is configured to output the clock signal transmitted by the clock signal line to the control end of the corresponding data write transistor according to the switch control signal transmitted by the switch control line, and the compensation unit of each of the demultiplexing units is configured to detect the threshold voltage of the data write transistor and receive the corresponding compensation control signal to compensate the threshold voltage of the data write transistor.

2. The demultiplexing circuit according to claim 1, wherein: The compensation unit comprises: a compensation transistor, wherein an input terminal of the compensation transistor is electrically connected to the corresponding input signal line, an output terminal of the compensation transistor is electrically connected to the input terminal of the data writing transistor, and a control terminal of the compensation transistor receives the corresponding compensation control signal; and A first capacitor, wherein a first end of the first capacitor is electrically connected to the control end of the data writing transistor, and a second end of the first capacitor is electrically connected to the output end of the data writing transistor.

3. The demultiplexing circuit according to claim 1, wherein: Each of the switch control units comprises: A switch transistor, wherein the control end of the switch transistor is electrically connected to the switch control line, the input end of the switch transistor is electrically connected to the corresponding clock signal line, and the output end of the switch transistor is electrically connected to the control end of the data write transistor of the corresponding demultiplexing unit.

4. The demultiplexing circuit according to claim 1, wherein: Also includes: A potential reset module, comprising a plurality of potential reset units electrically connected to a reset control line, each of the potential reset units electrically connected to a reset signal line, and an output end of each of the potential reset units electrically connected to an output end of the data writing transistor of a demultiplexing unit; Wherein, each of the potential resetting units is configured to output the reset signal transmitted by the reset signal line to the output end of the corresponding data writing transistor according to the reset control signal transmitted by the reset control line.

5. The demultiplexing circuit according to claim 4, wherein: Each of the potential resetting units comprises: A reset transistor, wherein the control end of the reset transistor is electrically connected to the reset control line, the input end of the reset transistor is electrically connected to the corresponding reset signal line, and the output end of the reset transistor is electrically connected to the output end of the data write transistor of the corresponding demultiplexing unit.

6. The demultiplexing circuit according to claim 4, wherein: The plurality of potential reset units include a first reset unit and a second reset unit electrically connected to the reset control line, the first reset unit is electrically connected to a first reset signal line, and the second reset unit is electrically connected to a second reset signal line; The plurality of switch control units include a first switch control unit and a second switch control unit electrically connected to the switch control line, the first switch control unit is electrically connected to the first clock signal line, and the second switch control unit is electrically connected to the second clock signal line; The demultiplexing module includes a first demultiplexing module, and the plurality of demultiplexing units included in the first demultiplexing module include at least a first demultiplexing unit and a second demultiplexing unit; the first demultiplexing unit is electrically connected to a first input signal line and a first output signal line, and the second demultiplexing unit is electrically connected to the first input signal line and the second output signal line; Among them, the control end of the data writing transistor included in the first demultiplexing unit is electrically connected to the output end of the first switch control unit, the output end of the data writing transistor included in the first demultiplexing unit is electrically connected to the output end of the first reset unit, and the compensation unit of the first demultiplexing unit is configured to receive a first compensation control signal; the control end of the data writing transistor included in the second demultiplexing unit is electrically connected to the output end of the second switch control unit, the output end of the data writing transistor included in the second demultiplexing unit is electrically connected to the output end of the second reset unit, and the compensation unit of the second demultiplexing unit is configured to receive a second compensation control signal.

7. The demultiplexing circuit according to claim 6, wherein: The demultiplexing module includes a second demultiplexing module, and the plurality of demultiplexing units included in the second demultiplexing module include at least a third demultiplexing unit and a fourth demultiplexing unit; the third demultiplexing unit is electrically connected to the second input signal line and the third output signal line, and the fourth demultiplexing unit is electrically connected to the second input signal line and the fourth output signal line; Among them, the control end of the data writing transistor included in the third demultiplexing unit is electrically connected to the output end of the first switch control unit, the output end of the data writing transistor included in the third demultiplexing unit is electrically connected to the output end of the first reset unit, and the compensation unit of the third demultiplexing unit is configured to receive the first compensation control signal; the control end of the data writing transistor included in the fourth demultiplexing unit is electrically connected to the output end of the second switch control unit, the output end of the data writing transistor included in the fourth demultiplexing unit is electrically connected to the output end of the second reset unit, and the compensation unit of the fourth demultiplexing unit is configured to receive the second compensation control signal.

8. The demultiplexing circuit according to claim 7, wherein: The plurality of reset units include a third reset unit electrically connected to the reset control line, and the third reset unit is electrically connected to a third reset signal line; The plurality of switch control units include a third switch control unit electrically connected to the switch control line, and the third switch control unit is electrically connected to a third clock signal line; The plurality of demultiplexing units included in the first demultiplexing module include a fifth demultiplexing unit, and the plurality of demultiplexing units included in the second demultiplexing module include a sixth demultiplexing unit; In which, the compensation units of the fifth demultiplexing unit and the sixth demultiplexing unit are configured to receive a third compensation control signal, the control end of the data writing transistor included in the fifth demultiplexing unit and the control end of the data writing transistor included in the sixth demultiplexing unit are electrically connected to the output end of the third switch control unit, and the output end of the data writing transistor included in the fifth demultiplexing unit and the output end of the data writing transistor included in the sixth demultiplexing unit are electrically connected to the output end of the third reset unit.

9. The demultiplexing circuit according to claim 1, wherein: Each of the demultiplexing units also includes: A second capacitor, wherein a first end of the second capacitor is electrically connected to the output end of the data writing transistor, and a second end of the second capacitor is electrically connected to the corresponding input signal line.

10. A method for controlling a demultiplexing circuit, wherein: is configured to control the demultiplexing circuit as claimed in claim 1, comprising: The switch control module outputs the clock signal transmitted by the clock signal line to the control end of the data writing transistor included in the corresponding demultiplexing unit according to the switch control signal transmitted by the switch control line, so as to reset the control end potential of the data writing transistor included in the corresponding demultiplexing unit; The switch control module transmits the clock signal to the control end of the data writing transistor included in the corresponding demultiplexing unit according to the switch control signal, so as to detect the threshold voltage of the data writing transistor through the compensation unit included in the demultiplexing unit; The compensation unit of the demultiplexing unit compensates for a threshold voltage of the data writing transistor according to the corresponding compensation control signal.

11. A display device, wherein: A demultiplexing circuit is included, wherein the demultiplexing circuit includes: At least one demultiplexing module, each of which is electrically connected to an input signal line and a plurality of output signal lines, each of which includes a plurality of demultiplexing units, each of which includes a data writing transistor and a compensation unit electrically connected to the data writing transistor, and an output end of the data writing transistor is electrically connected to the corresponding output signal line; A switch control module, comprising a plurality of switch control units electrically connected to the switch control line, each of the switch control units electrically connected to a clock signal line, and an output end of each of the switch control units electrically connected to a control end of the data writing transistor of the demultiplexing unit; Among them, each of the switch control units is configured to output the clock signal transmitted by the clock signal line to the control end of the corresponding data write transistor according to the switch control signal transmitted by the switch control line, and the compensation unit of each of the demultiplexing units is configured to detect the threshold voltage of the data write transistor and receive the corresponding compensation control signal to compensate the threshold voltage of the data write transistor.

12. The display device according to claim 11, wherein: The compensation unit comprises: a compensation transistor, wherein an input terminal of the compensation transistor is electrically connected to the corresponding input signal line, an output terminal of the compensation transistor is electrically connected to the input terminal of the data writing transistor, and a control terminal of the compensation transistor receives the corresponding compensation control signal; and A first capacitor, wherein a first end of the first capacitor is electrically connected to the control end of the data writing transistor, and a second end of the first capacitor is electrically connected to the output end of the data writing transistor.

13. The display device according to claim 11, wherein: Each of the switch control units comprises: A switch transistor, wherein the control end of the switch transistor is electrically connected to the switch control line, the input end of the switch transistor is electrically connected to the corresponding clock signal line, and the output end of the switch transistor is electrically connected to the control end of the data write transistor of the corresponding demultiplexing unit.

14. The display device according to claim 11, wherein: Also includes: A potential reset module, comprising a plurality of potential reset units electrically connected to a reset control line, each of the potential reset units electrically connected to a reset signal line, and an output end of each of the potential reset units electrically connected to an output end of the data writing transistor of a demultiplexing unit; Wherein, each of the potential resetting units is configured to output the reset signal transmitted by the reset signal line to the output end of the corresponding data writing transistor according to the reset control signal transmitted by the reset control line.

15. The display device according to claim 14, wherein: Each of the potential resetting units comprises: A reset transistor, wherein the control end of the reset transistor is electrically connected to the reset control line, the input end of the reset transistor is electrically connected to the corresponding reset signal line, and the output end of the reset transistor is electrically connected to the output end of the data write transistor of the corresponding demultiplexing unit.

16. The display device according to claim 14, wherein: The plurality of potential reset units include a first reset unit and a second reset unit electrically connected to the reset control line, the first reset unit is electrically connected to a first reset signal line, and the second reset unit is electrically connected to a second reset signal line; The plurality of switch control units include a first switch control unit and a second switch control unit electrically connected to the switch control line, the first switch control unit is electrically connected to the first clock signal line, and the second switch control unit is electrically connected to the second clock signal line; The demultiplexing module includes a first demultiplexing module, and the plurality of demultiplexing units included in the first demultiplexing module include at least a first demultiplexing unit and a second demultiplexing unit; the first demultiplexing unit is electrically connected to a first input signal line and a first output signal line, and the second demultiplexing unit is electrically connected to the first input signal line and the second output signal line; Wherein, the control terminal of the data writing transistor included in the first demultiplexing unit is connected to the control terminal of the data writing transistor The output end of a switch control unit is electrically connected, the output end of the data writing transistor included in the first demultiplexing unit is electrically connected to the output end of the first reset unit, and the compensation unit of the first demultiplexing unit is configured to receive a first compensation control signal; the control end of the data writing transistor included in the second demultiplexing unit is electrically connected to the output end of the second switch control unit, the output end of the data writing transistor included in the second demultiplexing unit is electrically connected to the output end of the second reset unit, and the compensation unit of the second demultiplexing unit is configured to receive a second compensation control signal.

17. The display device according to claim 16, wherein: The demultiplexing module includes a second demultiplexing module, and the plurality of demultiplexing units included in the second demultiplexing module include at least a third demultiplexing unit and a fourth demultiplexing unit; the third demultiplexing unit is electrically connected to the second input signal line and the third output signal line, and the fourth demultiplexing unit is electrically connected to the second input signal line and the fourth output signal line; Among them, the control end of the data writing transistor included in the third demultiplexing unit is electrically connected to the output end of the first switch control unit, the output end of the data writing transistor included in the third demultiplexing unit is electrically connected to the output end of the first reset unit, and the compensation unit of the third demultiplexing unit is configured to receive the first compensation control signal; the control end of the data writing transistor included in the fourth demultiplexing unit is electrically connected to the output end of the second switch control unit, the output end of the data writing transistor included in the fourth demultiplexing unit is electrically connected to the output end of the second reset unit, and the compensation unit of the fourth demultiplexing unit is configured to receive the second compensation control signal.

18. The display device according to claim 17, wherein: The plurality of reset units include a third reset unit electrically connected to the reset control line, and the third reset unit is electrically connected to a third reset signal line; The plurality of switch control units include a third switch control unit electrically connected to the switch control line, and the third switch control unit is electrically connected to a third clock signal line; The plurality of demultiplexing units included in the first demultiplexing module include a fifth demultiplexing unit, and the plurality of demultiplexing units included in the second demultiplexing module include a sixth demultiplexing unit; The compensation units of the fifth demultiplexing unit and the sixth demultiplexing unit are configured to receive a third compensation control signal, and the data writing transistors included in the fifth demultiplexing unit are The control end and the control end of the data writing transistor included in the sixth demultiplexing unit are electrically connected to the output end of the third switch control unit, and the output end of the data writing transistor included in the fifth demultiplexing unit and the output end of the data writing transistor included in the sixth demultiplexing unit are electrically connected to the output end of the third reset unit.

19. The display device according to claim 11, wherein: Each of the demultiplexing units further comprises: A second capacitor, wherein a first end of the second capacitor is electrically connected to the output end of the data writing transistor, and a second end of the second capacitor is electrically connected to the corresponding input signal line.

20. The display device according to claim 11, wherein: The display device further includes a display panel and a driving module electrically connected to the demultiplexing circuit; The display panel includes a plurality of sub-pixels and a plurality of output signal lines electrically connected to the plurality of sub-pixels, and the driving module is electrically connected to the demultiplexing circuit via the input signal lines.

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