Transmission device and output impedance adjustment method

Abstract

A transmission device according to an embodiment of the present disclosure comprises: a dummy driver including a first circuit provided in a path connecting a first node and a first power supply node, a second circuit provided in a path connecting the first node and a second power supply node, a third circuit provided in a path connecting a second node and the first power supply node, and a fourth circuit provided in a path connecting the second node and the second power supply node; a switch provided in a path connecting the first node and the second node; a driver including a fifth circuit provided in a path connecting a first output terminal and the first power supply node, a sixth circuit provided in a path connecting the first output terminal and the second power supply node, a seventh circuit provided in a path connecting a second output terminal and the first power supply node, and an eighth circuit provided in a path connecting the second output terminal and the second power supply node; and a control circuit.

Description

Transmitter and output impedance adjustment method

[0001] The present disclosure relates to a transmitter with adjustable output impedance and a method for adjusting the output impedance.

[0002] In communication systems, adjustment of output impedance in a transmitter is often performed. For example, Patent Document 1 discloses a technique for adjusting output impedance by supplying a current from outside the chip to a replica circuit of an output driver.

[0003] International Publication No. 2019 / 198434

[0004] Thus, in a communication system, it is desirable to be able to adjust the output impedance, and it is expected that the output impedance can be adjusted effectively.

[0005] It is desirable to provide a transmitter and an output impedance adjustment method that can effectively adjust the output impedance.

[0006] A first transmission device according to an embodiment of the present disclosure includes a dummy driver, a first switch, a driver, and a control circuit. The dummy driver has: a first circuit provided on a path connecting a first node and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal; a second circuit provided on a path connecting the first node and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal; a third circuit provided on a path connecting the second node and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal; and a fourth circuit provided on a path connecting the second node and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, and is capable of changing impedances of the first circuit, the second circuit, the third circuit, and the fourth circuit. The first switch is provided on a path connecting the first node and the second node. The driver has: a fifth circuit provided on a path connecting the first output terminal and the first power supply node, the fifth circuit including a fifth transistor and a fifth resistor element that can be turned on and off based on a fifth signal; a sixth circuit provided on a path connecting the first output terminal and the second power supply node, the sixth circuit including a sixth transistor and a sixth resistor element that can be turned on and off based on a sixth signal; a seventh circuit provided on a path connecting the second output terminal and the first power supply node, the seventh circuit including a seventh transistor and a seventh resistor element that can be turned on and off based on a seventh signal; and an eighth circuit provided on a path connecting the second output terminal and the second power supply node, the eighth circuit including an eighth transistor and an eighth resistor element that can be turned on and off based on an eighth signal, and is capable of changing impedances of the fifth circuit, the sixth circuit, the seventh circuit, and the eighth circuit. The control circuit is capable of setting the impedance of the first circuit, the impedance of the second circuit, the impedance of the third circuit, the impedance of the fourth circuit, the impedance of the fifth circuit, the impedance of the sixth circuit, the impedance of the seventh circuit, and the impedance of the eighth circuit, and is capable of controlling the operation of the first switch.The control circuit is capable of performing a first operation, which includes turning on the first switch, turning on the second transistor and the third transistor, turning off the first transistor and the fourth transistor, sequentially changing the impedance of the second circuit, and setting the impedance of the sixth circuit and the impedance of the eighth circuit in the driver based on first setting data that is set based on the voltage of the second node when the impedance of the second circuit is sequentially changed.

[0007] A second transmission device according to an embodiment of the present disclosure includes a driver, a first switch, and a control circuit. The driver includes: a first circuit provided in a path connecting a first output terminal and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal; a second circuit provided in a path connecting the first output terminal and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal; a third circuit provided in a path connecting the second output terminal and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal; and a fourth circuit provided in a path connecting the second output terminal and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal. The driver is capable of changing impedances of the first circuit, the second circuit, the third circuit, and the fourth circuit. The first switch is provided in the path connecting the first output terminal and the second output terminal. The control circuit is capable of setting the impedance of the first circuit, the impedance of the second circuit, the impedance of the third circuit, and the impedance of the fourth circuit, and is capable of controlling the operation of the first switch. The control circuit is capable of performing a first operation. The first operation includes turning on the first switch, turning on the second transistor and the third transistor, turning off the first transistor and the fourth transistor, sequentially changing the impedance of the second circuit, and setting the impedance of the second circuit and the impedance of the fourth circuit based on first setting data that is set based on the voltage of the second output terminal when the impedance of the second circuit is sequentially changed.

[0008] An output impedance adjusting method according to an embodiment of the present disclosure includes a dummy driver including: a first circuit provided in a path connecting a first node and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal; a second circuit provided in a path connecting the first node and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal; a third circuit provided in a path connecting the second node and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal; and a fourth circuit provided in a path connecting the second node and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, the output impedance adjusting method including the steps of: turning on a first switch provided in a path connecting the first node and the second node; turning on the second transistor and the third transistor; The method includes sequentially changing the impedance, and setting the impedance of the sixth circuit and the impedance of the eighth circuit in a driver having: a fifth circuit provided in a path connecting the first output terminal and the first power supply node and including a fifth transistor and a fifth resistor element that can be turned on and off based on a fifth signal; a sixth circuit provided in a path connecting the first output terminal and the second power supply node and including a sixth transistor and a sixth resistor element that can be turned on and off based on a sixth signal; a seventh circuit provided in a path connecting the second output terminal and the first power supply node and including a seventh transistor and a seventh resistor element that can be turned on and off based on a seventh signal; and an eighth circuit provided in a path connecting the second output terminal and the second power supply node and including an eighth transistor and an eighth resistor element that can be turned on and off based on an eighth signal, based on first setting data that is set based on the voltage of the second node when the impedance of the second circuit is sequentially changed.

[0009] In a first transmission device and an output impedance adjustment method according to an embodiment of the present disclosure, in a first operation, a first switch is turned on, thereby connecting a first node and a second node to each other. In the dummy driver, the second and third transistors are turned on, and the first and fourth transistors are turned off. The impedance of the second circuit of the dummy driver is controlled to change sequentially. The impedances of the sixth and eighth circuits in the driver are set based on first setting data set based on the voltage of the second node when the impedance of the second circuit is changing sequentially.

[0010] In a second transmission device according to an embodiment of the present disclosure, in a first operation, the first switch is turned on, thereby connecting the first output terminal and the second output terminal to each other. In the driver, the second transistor and the third transistor are turned on, and the first transistor and the fourth transistor are turned off. The impedance of the second circuit is controlled to change sequentially. The impedance of the second circuit and the impedance of the fourth circuit in the driver are set based on first setting data that is set based on the voltage of the second output terminal when the impedance of the second circuit is changing sequentially.

[0011] FIG. 1 is a block diagram illustrating an example configuration of a communication system according to a first embodiment of the present disclosure. FIG. 2 is a circuit diagram illustrating an example configuration of a driver shown in FIG. 1. FIG. 3A is an explanatory diagram illustrating an operating state of the driver shown in FIG. 2. FIG. 3B is an explanatory diagram illustrating another operating state of the driver shown in FIG. 2. FIG. 4 is a circuit diagram illustrating a more detailed example configuration of the driver shown in FIG. 2. FIG. 5 is a block diagram illustrating an example configuration of the impedance adjustment circuit shown in FIG. 1. FIG. 6 is a circuit diagram illustrating an example configuration of a dummy driver shown in FIG. 5. FIG. 7 is a circuit diagram illustrating a more detailed example configuration of the driver shown in FIG. 6. FIG. 8 is a flowchart illustrating an example of impedance adjustment operation in the impedance adjustment circuit shown in FIG. 5. FIG. 9 is a timing waveform diagram illustrating an example of impedance adjustment operation in the impedance adjustment circuit shown in FIG. 5. FIG. 10A is an explanatory diagram illustrating one operating state of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 5. FIG. 10B is an explanatory diagram illustrating another operating state of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 5. FIG. 11 is a circuit diagram illustrating an example configuration of a driver according to a modified example of the first embodiment. FIG. 12 is a circuit diagram showing an example of a configuration of a driver according to another modification of the first embodiment. FIG. 13 is a timing diagram showing an example of an operation of a communication system according to another modification of the first embodiment. FIG. 14 is a timing diagram showing an example of an operation of a communication system according to another modification of the first embodiment. FIG. 15 is a block diagram showing an example of a configuration of a communication system according to another modification of the first embodiment. FIG. 16 is a block diagram showing an example of a configuration of the impedance adjustment circuit shown in FIG. 15. FIG. 17 is a block diagram showing an example of a configuration of a communication system according to another modification of the first embodiment. FIG. 18 is a block diagram showing an example of a configuration of a communication system according to the second embodiment. FIG. 19 is a block diagram showing an example of a configuration of the impedance adjustment circuit shown in FIG. 18. FIG. 20A is a flowchart showing an example of an impedance adjustment operation in the impedance adjustment circuit shown in FIG. 19. FIG. 20B is another flowchart showing an example of an impedance adjustment operation in the impedance adjustment circuit shown in FIG. 19.FIG. 21A is an explanatory diagram showing one operating state of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 19 . FIG. 21B is an explanatory diagram showing another operating state of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 19 . FIG. 22A is an explanatory diagram showing one operating state of the BIST operation in the impedance adjustment circuit shown in FIG. 19 . FIG. 22B is an explanatory diagram showing another operating state of the BIST operation in the impedance adjustment circuit shown in FIG. 19 . FIG. 23 is an explanatory diagram showing one operating state of the impedance adjustment circuit when the communication system shown in FIG. 18 performs communication operation. FIG. 24 is a block diagram showing an example configuration of a communication system according to a modified example of the second embodiment. FIG. 25 is a block diagram showing an example configuration of the impedance adjustment circuit shown in FIG. 24 . FIG. 26A is an explanatory diagram showing one operating state of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 25 . FIG. 26B is another explanatory diagram showing an example of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 25 . FIG. 27 is a block diagram showing an example configuration of a communication system according to another modified example of the second embodiment. FIG. 28 is a block diagram showing an example of the configuration of a communication system according to the third embodiment. FIG. 29 is a block diagram showing an example of the configuration of the impedance adjustment circuit shown in FIG. 28. FIG. 30 is a flowchart showing an example of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 29. FIG. 31A is an explanatory diagram showing one operating state of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 29. FIG. 31B is an explanatory diagram showing another operating state of the impedance adjustment operation in the impedance adjustment circuit shown in FIG. 29. FIG. 32A is an explanatory diagram showing one operating state of the BIST operation in the impedance adjustment circuit shown in FIG. 29. FIG. 32B is an explanatory diagram showing another operating state of the BIST operation in the impedance adjustment circuit shown in FIG. 29. FIG. 33 is an explanatory diagram showing one operating state of the impedance adjustment circuit when the communication system shown in FIG. 28 performs a communication operation. FIG. 34 is a block diagram showing an example of the configuration of a communication system according to a modification of the third embodiment.Fig. 35 is a block diagram showing an example configuration of the impedance adjustment circuit shown in Fig. 34. Fig. 36A is an explanatory diagram showing one operating state of the impedance adjustment operation in the impedance adjustment circuit shown in Fig. 35. Fig. 36B is another explanatory diagram showing one example of the impedance adjustment operation in the impedance adjustment circuit shown in Fig. 35. Fig. 37 is a block diagram showing an example configuration of a communication system according to another modified example of the third embodiment. Fig. 38 is a circuit diagram showing an example configuration of a driver according to the modified example. Fig. 39 is a circuit diagram showing a more detailed example configuration of the driver shown in Fig. 38.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. First embodiment 2. Second embodiment 3. Reference example

[0013] 1 shows an example of the configuration of a communication system 1 including a transmitting device according to a first embodiment. The communication system 1 includes a transmitting device 10 and a receiving device 100. The transmitting device 10 is configured to transmit signals SIGP and SIGN to the receiving device 100. The signals SIGP and SIGN constitute differential signals. The receiving device 100 is configured to receive the signals SIGP and SIGN transmitted from the transmitting device 10.

[0014] The transmitting device 10 has output terminals OUTP and OUTN, and the receiving device 100 has input terminals INP and INN. The output terminal OUTP of the transmitting device 10 and the input terminal INP of the receiving device 100 are connected to each other via a transmission line 90P, and the output terminal OUTN of the transmitting device 10 and the input terminal INN of the receiving device 100 are connected to each other via a transmission line 90N. The characteristic impedance of each of the transmission lines 90P and 90N is 50 [Ω] in this example. The output impedance of the transmitting device 10 seen from the output terminal OUTP and the output impedance of the transmitting device 10 seen from the output terminal OUTN are each adjusted to 50 [Ω] in this example. A resistive element 91 is provided between the input terminals INP and INN of the receiving device 100. In this example, the resistance value of the resistive element 91 is 100 [Ω]. The receiving device 100 has a receiver 101. The receiver 101 is connected to the input terminals INP and INN and is configured to receive the signals SIGP and SIGN.

[0015] The transmitter 10 is a semiconductor circuit, and includes a driver 11 , a pre-driver 12 , a BIST (Built in Self Test) circuit 13 , and an impedance adjustment circuit 20 .

[0016] The driver 11 is configured to drive the transmission lines 90P and 90N to transmit the signals SIGP and SIGN that constitute a differential signal.

[0017] 2 shows an example of the configuration of the driver 11. The driver 11 has four circuits UP, DP, UN, and DN.

[0018] The circuit UP is provided in a path connecting the output terminal OUTP and the power supply node of the power supply voltage VRH. The circuit UP includes a transistor MP1 and a resistor element R1. The transistor MP1 is a P-type MOS (Metal Oxide Semiconductor) transistor. A signal SUP is supplied to the gate of the transistor MP1, the source is connected to the power supply node of the power supply voltage VRH, and the drain is connected to one end of the resistor element R1. One end of the resistor element R1 is connected to the drain of the transistor MP1, and the other end is connected to the output terminal OUTP.

[0019] The circuit DP is provided in a path connecting the output terminal OUTP and the power supply node of the power supply voltage VRL. The circuit DP includes a transistor MN2 and a resistor element R2. The transistor MN2 is an N-type MOS transistor. A signal SDP is supplied to the gate of the transistor MN2, the source is connected to the power supply node of the power supply voltage VRL, and the drain is connected to one end of the resistor element R2. One end of the resistor element R2 is connected to the drain of the transistor MN2, and the other end is connected to the output terminal OUTP.

[0020] The circuit UN is provided in a path connecting the output terminal OUTN and the power supply node of the power supply voltage VRH. The circuit UN includes a transistor MP3 and a resistor element R3. The transistor MP3 is a P-type MOS transistor. A signal SUN is supplied to the gate of the transistor MP3, the source is connected to the power supply node of the power supply voltage VRH, and the drain is connected to one end of the resistor element R3. One end of the resistor element R3 is connected to the drain of the transistor MP3, and the other end is connected to the output terminal OUTN.

[0021] The circuit DN is provided in a path connecting the output terminal OUTN and the power supply node of the power supply voltage VRL. The circuit DN includes a transistor MN4 and a resistor element R4. The transistor MN4 is an N-type MOS transistor, and a signal SDN is supplied to the gate of the transistor MN4. The source of the transistor MN4 is connected to the power supply node of the power supply voltage VRL, and the drain is connected to one end of the resistor element R4. One end of the resistor element R4 is connected to the drain of the transistor MN4, and the other end is connected to the output terminal OUTN.

[0022] 3A and 3B show an example of the operation of the driver 11, with FIG. 3A showing one operating state of the driver 11 and FIG. 3B showing another operating state of the driver 11.

[0023] In the operating state shown in Figure 3A, transistors MP1 and MN4 are on, and transistors MN2 and MP3 are off. In this case, current I flows from the power supply node of the power supply voltage VRH through transistor MP1, resistor R1, output terminal OUTP, transmission line 90P, resistor 91, transmission line 90N, output terminal OUTN, resistor R4, transistor MN4, and the power supply node of the power supply voltage VRL in this order. The impedance between the output terminal OUTP and the power supply node of the power supply voltage VRH is adjusted to 50 [Ω], the resistance value of resistor 91 is 100 [Ω], and the impedance between the output terminal OUTN and the power supply node of the power supply voltage VRL is adjusted to 50 [Ω]. Therefore, the voltage of signal SIGP is "3 / 4 × (VRH - VRL) + VRL," and the voltage of signal SIGN is "1 / 4 × (VRH - VRL) + VRL."

[0024] In the operating state shown in Figure 3B, transistors MN2 and MP3 are on, and transistors MP1 and MN4 are off. In this case, current I flows from the power supply node of the power supply voltage VRH through transistor MP3, resistor R3, output terminal OUTN, transmission line 90N, resistor 91, transmission line 90P, output terminal OUTP, resistor R2, transistor MN2, and the power supply node of the power supply voltage VRL in this order. The impedance between the output terminal OUTN and the power supply node of the power supply voltage VRH is adjusted to 50 [Ω], the resistance value of resistor 91 is 100 [Ω], and the impedance between the output terminal OUTP and the power supply node of the power supply voltage VRL is adjusted to 50 [Ω]. Therefore, the voltage of signal SIGP is "1 / 4 x (VRH - VRL) + VRL," and the voltage of signal SIGN is "3 / 4 x (VRH - VRL) + VRL."

[0025] The driver 11 can be in two operating states shown in Figures 3A and 3B. Therefore, each of the signals SIGP and SIGN transitions between a high level ("3 / 4 x (VRH - VRL) + VRL") and a low level ("1 / 4 x (VRH - VRL) + VRL"). The driver is configured to transmit such signals SIGP and SIGN.

[0026] Fig. 4 shows an example of a specific circuit configuration of the driver 11. In Fig. 4, "x4", "x8", "x16", and "x32" indicate the number of parallel connections.

[0027] In this example, the circuit UP has four circuits UP3, UP2, UP1, and UP0. Signals SUP3, SUP2, SUP1, and SUP0 are supplied to these four circuits UP3, UP2, UP1, and UP0, respectively. These signals SUP3 to SUP0 correspond to the signal SUP shown in FIG. 2.

[0028] The circuit UP3 includes four paths connecting the output terminal OUTP and the power supply node of the power supply voltage VRH, each of which has a series-connected transistor MP and a resistor element RES. The transistor MP is a P-type MOS transistor. A signal SUP3 is supplied to the gates of these four transistors MP. The circuit UP2 includes eight paths connecting the output terminal OUTP and the power supply node of the power supply voltage VRH, each of which has a series-connected transistor MP and a resistor element RES. A signal SUP2 is supplied to the gates of these eight transistors MP. The circuit UP1 includes 16 paths connecting the output terminal OUTP and the power supply node of the power supply voltage VRH, each of which has a series-connected transistor MP and a resistor element RES. A signal SUP1 is supplied to the gates of these 16 transistors MP. The circuit UP0 includes 32 paths connecting the output terminal OUTP and the power supply node of the power supply voltage VRH, and each of the 32 paths includes a transistor MP and a resistor element RES connected in series. A signal SUP0 is supplied to the gates of the 32 transistors MP.

[0029] With this configuration, the four circuits UP3 to UP0 are individually set to be enabled or disabled using the signals SUP3 to SUP0.

[0030] Specifically, for example, when signal SUP3 transitions between high and low levels and signals SUP2 to SUP0 are maintained at a high level, the four transistors MP in circuit UP3 are turned on and off based on signal SUP3, and the 56 (=8+16+32) transistors MP in circuits UP2, UP1, and UP0 remain off. In other words, circuit UP3 is enabled, and circuits UP2 to UP0 are disabled. In this case, since only the four transistors MP in circuit UP3 can be turned on, the impedance of circuit UP is large.

[0031] On the other hand, for example, when signals SUP3 to SUP0 transition between high and low levels, 60 (=4+8+16+32) transistors MP in circuits UP3 to UP0 are turned on and off based on signals SUP3 to SUP0. In other words, all of circuits UP3 to UP0 are enabled. In this case, since all 60 transistors MP in circuits UP3 to UP0 can be turned on, the impedance of circuit UP is small.

[0032] In this way, the transmitter 10 can adjust the impedance of the circuit UP by setting which of the four circuits UP3 to UP0 to enable. In this example, the impedance of the circuit UP is adjusted to approximately 50 Ω.

[0033] In this example, the circuit DP has four circuits DP3, DP2, DP1, and DP0. Signals SDP3, SDP2, SDP1, and SDP0 are supplied to these four circuits DP3, DP2, DP1, and DP0, respectively. These signals SDP3 to SDP0 correspond to the signal SDP shown in FIG. 2.

[0034] The circuit DP3 includes four paths connecting the output terminal OUTP and the power supply node of the power supply voltage VRL, each of which has a series-connected transistor MN and a resistor element RES. The transistor MN is an N-type MOS transistor. A signal SDP3 is supplied to the gates of these four transistors MN. The circuit DP2 includes eight paths connecting the output terminal OUTP and the power supply node of the power supply voltage VRL, each of which has a series-connected transistor MN and a resistor element RES. A signal SDP2 is supplied to the gates of these eight transistors MN. The circuit DP1 includes 16 paths connecting the output terminal OUTP and the power supply node of the power supply voltage VRL, each of which has a series-connected transistor MN and a resistor element RES. A signal SDP1 is supplied to the gates of these 16 transistors MN. The circuit DP0 includes 32 paths connecting the output terminal OUTP and the power supply node of the power supply voltage VRL, and each of the 32 paths includes a transistor MN and a resistor element RES connected in series. A signal SDP0 is supplied to the gates of the 32 transistors MN.

[0035] With this configuration, the four circuits DP3 to DP0 are individually enabled or disabled using signals SDP3 to SDP0. In the transmitter 10, the impedance of the circuit DP can be adjusted to approximately 50 Ω by setting which of the four circuits DP3 to DP0 to be enabled.

[0036] In this example, the circuit UN has four circuits UN3, UN2, UN1, and UN0. Signals SUN3, SUN2, SUN1, and SUN0 are supplied to these four circuits UN3, UN2, UN1, and UN0, respectively. These signals SUN3 to SUN0 correspond to the signal SUN shown in FIG. 2.

[0037] The circuit configuration of circuits UN3 to UN0 is the same as that of circuits UP3 to UP0. A signal SUN3 is supplied to the gates of four transistors MP in circuit UN3. A signal SUN2 is supplied to the gates of eight transistors MP in circuit UN2. A signal SUN1 is supplied to the gates of 16 transistors MP in circuit UN1. A signal SUN0 is supplied to the gates of 32 transistors MP in circuit UN0.

[0038] With this configuration, the four circuits UN3 to UN0 are individually enabled or disabled using signals SUN3 to SUN0. In the transmitter 10, by setting which of the four circuits UN3 to UN0 to be enabled, the impedance of the circuit UN can be adjusted to approximately 50 Ω.

[0039] In this example, the circuit DN has four circuits DN3, DN2, DN1, and DN0. Signals SDN3, SDN2, SDN1, and SDN0 are supplied to these four circuits DN3, DN2, DN1, and DN0, respectively. These signals SDN3 to SDN0 correspond to the signal SDN shown in FIG. 2.

[0040] The circuit configuration of circuits DN3 to DN0 is similar to that of circuits DP3 to DP0. A signal SDN3 is supplied to the gates of four transistors MN in circuit DN3. A signal SDN2 is supplied to the gates of eight transistors MN in circuit DN2. A signal SDN1 is supplied to the gates of 16 transistors MN in circuit DN1. A signal SDN0 is supplied to the gates of 32 transistors MN in circuit DN0.

[0041] With this configuration, the four circuits DN3 to DN0 are individually enabled or disabled using signals SDN3 to SDN0. In the transmitter 10, the impedance of the circuit DN can be adjusted to approximately 50 Ω by setting which of the four circuits DN3 to DN0 to be enabled.

[0042] In this way, the impedance of the circuit UP, the impedance of the circuit DP, the impedance of the circuit UN, and the impedance of the circuit DN are adjusted in the driver 11. As a result, the driver 11 is able to adjust the output impedance seen from the output terminal OUTP and the output impedance seen from the output terminal OUTN.

[0043] The pre-driver 12 (FIGS. 1 and 2) is configured to generate signals SUP, SDP, SUN, and SDN based on the input signal, and to use these signals SUP, SDP, SUN, and SDN to turn on or off the transistors MP1, MN2, MP3, and MN4 (FIG. 2) in the driver 11, respectively.

[0044] In addition, the pre-driver 12 is capable of setting which circuits in the driver 11 to enable and which circuits to disable among the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 based on instructions from a control circuit 26 (described later) of the impedance adjustment circuit 20.

[0045] Specifically, the pre-driver 12 enables or disables each of the circuits UP3 to UP0, for example, using four signals SUP3 to SUP0 included in the signal SUP. The pre-driver 12 enables or disables each of the circuits UP3 to UP0, for example, by supplying a signal corresponding to an input signal to a circuit among the four circuits UP3 to UP0 that is to be enabled and a high-level signal to a circuit that is to be disabled. The pre-driver 12 also enables or disables each of the circuits DP3 to DP0, for example, using four signals SDP3 to SDP0 included in the signal SDP. The pre-driver 12 enables or disables each of the circuits DP3 to DP0, for example, by supplying a signal corresponding to an input signal to a circuit among the four circuits DP3 to DP0 that is to be enabled and a low-level signal to a circuit that is to be disabled.

[0046] Similarly, the pre-driver 12 enables or disables each of the circuits UN3 to UN0, for example, using four signals SUN3 to SUN0 included in the signal SUN. The pre-driver 12 enables or disables each of the circuits UN3 to UN0, for example, by supplying a signal corresponding to an input signal to a circuit among the four circuits UN3 to UN0 that is to be enabled and a high-level signal to a circuit that is to be disabled. The pre-driver 12 also enables or disables each of the circuits DN3 to DN0, for example, using four signals SDN3 to SDN0 included in the signal SDN. The pre-driver 12 enables or disables each of the circuits DN3 to DN0, for example, by supplying a signal corresponding to an input signal to a circuit among the four circuits DN3 to DN0 that is to be enabled and a low-level signal to a circuit that is to be disabled.

[0047] The BIST circuit 13 (FIG. 1) is configured to check whether the output impedance of the driver 11 is set appropriately based on the voltages of the output terminals OUTP and OUTN. In this example, the BIST circuit 13 is configured to simply check whether the output impedance is set appropriately, rather than checking the impedance value (absolute value) of the output impedance itself.

[0048] The impedance adjustment circuit 20 is configured to adjust the output impedance of the driver 11. In this example, this output impedance adjustment operation is performed before shipping the transmission device 10. That is, since semiconductor circuits can have variations in electrical characteristics due to the manufacturing process, in this example, the output impedance of the driver 11 is adjusted before shipping.

[0049] FIG. 5 shows an example of the configuration of the impedance adjustment circuit 20. In addition to the impedance adjustment circuit 20, FIG. 5 also shows a driver 11, a pre-driver 12, and a BIST circuit 13. Also, in FIG. 5, the transmission device 10 is connected to an LSI (Large Scale Integrated Circuit) tester 102. The LSI tester 102 has a resistive element 103. One end of the resistive element 103 is connected to an output terminal OUTP of the transmission device 10, and the other end is connected to an output terminal OUTN of the transmission device 10. The resistive element 103 has a resistance value of 100 Ω. The LSI tester 102 is also connected to a control circuit 26 (described below) and a non-volatile memory 27 (described below) of the impedance adjustment circuit 20 of the transmission device 10.

[0050] The impedance adjustment circuit 20 includes a dummy driver 21 , a setting circuit 22 , switches SW1 and SW2 , a current source 23 , a voltage generation circuit 24 , a comparator 25 , a control circuit 26 , and a nonvolatile memory 27 .

[0051] The dummy driver 21 is configured so that the output impedance can be adjusted, similar to the driver 11 .

[0052] 6 shows an example of the configuration of the dummy driver 21. The dummy driver 21 has four circuits DUP, DDP, DUN, and DDN. The circuit configuration of the dummy driver 21 is similar to the circuit configuration of the driver 11 (FIG. 2).

[0053] The circuit DUP is provided in a path connecting the node N1 and the power supply node of the power supply voltage VRH. The circuit DUP includes a transistor DMP1 and a resistor element DR1. The transistor DMP1 is a P-type MOS transistor. A signal SDUP is supplied to the gate of the transistor DMP1, the source is connected to the power supply node of the power supply voltage VRH, and the drain is connected to one end of the resistor element DR1. One end of the resistor element DR1 is connected to the drain of the transistor DMP1, and the other end is connected to the node N1.

[0054] The circuit DDP is provided in a path connecting the node N1 and the power supply node of the power supply voltage VRL. The circuit DDP includes a transistor DMN2 and a resistor element DR2. The transistor DMN2 is an N-type MOS transistor. A signal SDDP is supplied to the gate of the transistor DMN2, the source is connected to the power supply node of the power supply voltage VRL, and the drain is connected to one end of the resistor element DR2. One end of the resistor element DR2 is connected to the drain of the transistor DMN2, and the other end is connected to the node N1.

[0055] The circuit DUN is provided in a path connecting the node N2 and the power supply node of the power supply voltage VRH. The circuit DUN includes a transistor DMP3 and a resistor element DR3. The transistor DMP3 is a P-type MOS transistor, and a signal SDUN is supplied to the gate of the transistor DMP3. The source of the transistor DMP3 is connected to the power supply node of the power supply voltage VRH, and the drain is connected to one end of the resistor element DR3. One end of the resistor element DR3 is connected to the drain of the transistor DMP3, and the other end is connected to the node N2.

[0056] The circuit DDN is provided in a path connecting the node N2 and the power supply node of the power supply voltage VRL. The circuit DDN has a transistor DMN4 and a resistor element DR4. The transistor DMN4 is an N-type MOS transistor, and a signal SDDN is supplied to the gate of the transistor DMN4. The source of the transistor DMN4 is connected to the power supply node of the power supply voltage VRL, and the drain is connected to one end of the resistor element DR4. One end of the resistor element DR4 is connected to the drain of the transistor DMN4, and the other end is connected to the node N2.

[0057] Fig. 7 shows an example of a specific circuit configuration of the dummy driver 21. The circuit configuration of the dummy driver 21 is similar to the circuit configuration of the driver 11 (Fig. 4). In Fig. 7, "x1", "x2", "x4", and "x8" indicate the number of parallel connections.

[0058] In this example, the circuit DUP has four circuits DUP3, DUP2, DUP1, and DUP0. Signals SDUP3, SDUP2, SDUP1, and SDUP0 are supplied to these four circuits DUP3, DUP2, DUP1, and DUP0, respectively. These signals SDUP3 to SDUP0 correspond to the signal SDUP shown in FIG. 6.

[0059] Circuit DUP3 includes one path connecting node N1 and the power supply node of power supply voltage VRH, and includes a series-connected transistor MP and a resistor element RES along this path. A signal SDUP3 is supplied to the gate of this transistor MP. Circuit DUP2 includes two paths connecting node N1 and the power supply node of power supply voltage VRH, and includes a series-connected transistor MP and a resistor element RES along each of these two paths. A signal SDUP2 is supplied to the gates of these two transistors MP. Circuit DUP1 includes four paths connecting node N1 and the power supply node of power supply voltage VRH, and includes a series-connected transistor MP and a resistor element RES along each of these four paths. A signal SDUP1 is supplied to the gates of these four transistors MP. Circuit DUP0 includes eight paths connecting node N1 and the power supply node of power supply voltage VRH, and includes a series-connected transistor MP and a resistor element RES along each of these eight paths. The gates of these eight transistors MP are supplied with a signal SDUP0.

[0060] With this configuration, the four circuits DUP3 to DUP0 are individually enabled or disabled using signals SDUP3 to SDUP0. In the dummy driver 21, by setting which of the four circuits DUP3 to DUP0 to be enabled in this manner, the impedance of the circuit DUP can be adjusted to approximately 200 [Ω]. That is, since the number of transistors MP and resistor elements RES of the four circuits DUP3 to DUP0 in the dummy driver 21 is one-fourth the number of transistors MP and resistor elements RES of the four circuits UP3 to UP0 in the driver 11, the impedance of the circuit DUP in the dummy driver 21 is four times the impedance of the circuit UP in the driver 11. Therefore, in the dummy driver 21, the impedance of the circuit DUP can be adjusted to approximately 200 [Ω].

[0061] In this example, the circuit DDP has four circuits DDP3, DDP2, DDP1, and DDP0. Signals SDDP3, SDDP2, SDDP1, and SDDP0 are supplied to these four circuits DDP3, DDP2, DDP1, and DDP0, respectively. These signals SDDP3 to SDDP0 correspond to the signal SDDP shown in FIG. 6.

[0062] The circuit DDP3 includes one path connecting the node N1 and the power supply node of the power supply voltage VRL, and includes a series-connected transistor MN and a resistor element RES in this path. A signal SDDP3 is supplied to the gate of the transistor MN. The circuit DDP2 includes two paths connecting the node N1 and the power supply node of the power supply voltage VRL, and includes a series-connected transistor MN and a resistor element RES in each of these two paths. A signal SDDP2 is supplied to the gates of these two transistors MN. The circuit DDP1 includes four paths connecting the node N1 and the power supply node of the power supply voltage VRL, and includes a series-connected transistor MN and a resistor element RES in each of these three paths. A signal SDDP1 is supplied to the gates of these four transistors MN. The circuit DDP0 includes eight paths connecting the node N1 and the power supply node of the power supply voltage VRL, and includes a series-connected transistor MN and a resistor element RES in each of these eight paths. The gates of these eight transistors MN are supplied with a signal SDDP0.

[0063] With this configuration, the four circuits DDP3 to DDP0 are individually set to be enabled or disabled using the signals SDDP3 to SDDP0. In the dummy driver 21, by setting which of the four circuits DDP3 to DDP0 to be enabled in this way, the impedance of the circuit DDP can be adjusted to approximately 200 [Ω].

[0064] In this example, the circuit DUN has four circuits DUN3, DUN2, DUN1, and DUN0. Signals SDUN3, SDUN2, SDUN1, and SDUN0 are supplied to these four circuits DUN3, DUN2, DUN1, and DUN0, respectively. These signals SDUN3 to SDUN0 correspond to the signal SDUN shown in FIG. 6.

[0065] The circuit configurations of the circuits DUN3 to DUN0 are the same as those of the circuits DUP3 to DUP0. A signal SDUN3 is supplied to the gate of one transistor MP in the circuit DUN3. A signal SDUN2 is supplied to the gates of two transistors MP in the circuit DUN2. A signal SDUN1 is supplied to the gates of four transistors MP in the circuit DUN1. A signal SDUN0 is supplied to the gates of eight transistors MP in the circuit DUN0.

[0066] With this configuration, the four circuits DUN3 to DUN0 are individually set to be enabled or disabled using the signals SDUN3 to SDUN0. In the dummy driver 21, by setting which of the four circuits DUN3 to DUN0 to be enabled in this way, the impedance of the circuit DUN can be adjusted to approximately 200 [Ω].

[0067] In this example, the circuit DDN has four circuits DDN3, DDN2, DDN1, and DDN0. Signals SDDN3, SDDN2, SDDN1, and SDDN0 are supplied to these four circuits DDN3, DDN2, DDN1, and DDN0, respectively. These signals SDDN3 to SDDN0 correspond to the signal SDDN shown in FIG. 6.

[0068] The circuit configuration of the circuits DDN3 to DDN0 is the same as that of the circuits DDP3 to DDP0. A signal SDDN3 is supplied to the gate of one transistor MN in the circuit DDN3. A signal SDDN2 is supplied to the gates of two transistors MN in the circuit DDN2. A signal SDDN1 is supplied to the gates of four transistors MN in the circuit DDN1. A signal SDDN0 is supplied to the gates of eight transistors MN in the circuit DDN0.

[0069] With this configuration, the four circuits DDN3 to DDN0 are individually set to be enabled or disabled using the signals SDDN3 to SDDN0. In this way, the dummy driver 21 can adjust the impedance of the circuit DDN to approximately 200 [Ω] by setting which of the four circuits DDN3 to DDN0 to be enabled.

[0070] The number of transistors MP and resistor elements RES in the dummy driver 21 is 1 / 4 of the number of transistors MP and resistor elements RES in the driver 11. Therefore, in the transmitting device 10, the size of the dummy driver 21 can be 1 / 4 of the size of the driver 11. Since the output impedance of the dummy driver 21 is four times the output impedance of the driver 11, the current flowing through the dummy driver 21 can be 1 / 4 of the current flowing through the driver 11.

[0071] In this example, the number of transistors MP and resistor elements RES in the dummy driver 21 is set to 1 / 4 of the number of transistors MP and resistor elements RES in the driver 11, but this is not limited to this. By setting the number of transistors MP and resistor elements RES in the dummy driver 21 to 1 / N of the number of transistors MP and resistor elements RES in the driver 11, the size of the dummy driver 21 can be set to 1 / N of the size of the driver 11, and the current flowing through the dummy driver 21 can be set to 1 / N of the current flowing through the driver 11. Here, N is an integer greater than or equal to 2. Specifically, for example, the number of transistors MP and resistor elements RES in the dummy driver 21 may be set to 1 / 2 of the number of transistors MP and resistor elements RES in the driver 11. In this case, the size of the dummy driver 21 can be set to 1 / 2 of the size of the driver 11, and the current flowing through the dummy driver 21 can be set to 1 / 2 of the current flowing through the driver 11. Furthermore, for example, the number of transistors MP and resistor elements RES in the dummy driver 21 may be 1 / 8 of the number of transistors MP and resistor elements RES in the driver 11. In this case, the size of the dummy driver 21 can be 1 / 8 of the size of the driver 11, and the current flowing through the dummy driver 21 can be 1 / 8 of the current flowing through the driver 11.

[0072] The setting circuit 22 (Figures 5 and 6) is configured to generate signals SDUP, SDDP, SDUN, and SDDN, and to use these signals SDUP, SDDP, SDUN, and SDDN to turn on or off each of the transistors DMP1, DMN2, DMP3, and DMN4 (Figure 6) in the dummy driver 21.

[0073] In addition, similar to the pre-driver 12, the setting circuit 22 is capable of setting which circuits to enable and which circuits to disable among the circuits DUP3 to DUP0, DDP3 to DDP0, DUN3 to DUN0, and DDN3 to DDN0 in the dummy driver 21 based on instructions from the control circuit 26.

[0074] The switch SW1 (FIG. 5) is configured to be able to connect the node N1 and the node N2 based on an instruction from the control circuit 26. The switch SW1 is configured using, for example, an N-type MOS transistor or a transfer gate.

[0075] The switch SW2 (FIG. 5) is configured to be able to connect the node N2 to one end of the current source 23 based on an instruction from the control circuit 26. The switch SW2 is configured using, for example, an N-type MOS transistor or a transfer gate.

[0076] The current source 23 is a constant current source, and one end is connected to the switch SW2, and the other end is connected to the ground node. The current source 23 is configured to be able to sink a current from the dummy driver 21 toward the ground node. In this example, the current source 23 is set to pass a current that is 1 / 4 of the current I that flows through the driver 11 shown in FIGS. 3A and 3B. That is, in this example, the output impedance of the dummy driver 21 is four times the output impedance of the driver 11, so the current that flows through the dummy driver 21 can be set to 1 / 4 of the current that flows through the driver 11.

[0077] The voltage generation circuit 24 is configured to generate a reference voltage VREF based on instructions from the control circuit 26. The voltage generation circuit 24 has variable resistance elements RH and RL. One end of the variable resistance element RH is connected to a power supply node of a power supply voltage VRH, and the other end is connected to one end of the variable resistance element RL. One end of the variable resistance element RL is connected to the other end of the variable resistance element RH, and the other end is connected to the power supply node of the power supply voltage VRL. The voltage generation circuit 24 generates the reference voltage VREF by dividing a voltage using the variable resistance elements RH and RL. The voltage generation circuit 24 can change the ratio between the resistance values ​​of the variable resistance element RH and the variable resistance element RL based on instructions from the control circuit 26. For example, the voltage generation circuit 24 can set the reference voltage VREF to "3 / 4 × (VRH - VRL) + VRL" by setting the ratio between the resistance values ​​of the variable resistance element RH and the variable resistance element RL to 1:3. In addition, the voltage generating circuit 24 is capable of setting the reference voltage VREF to "1 / 2 x (VRH-VRL) + VRL" by setting the ratio of the resistance value of the variable resistance element RH to the resistance value of the variable resistance element RL to 1:1.

[0078] The comparator 25 is configured to compare the reference voltage VREF with the voltage at the node N2 (voltage VREP) and supply the comparison result (signal COUT) to the control circuit 26. The positive input terminal of the comparator 25 is connected to the voltage generating circuit 24, and the negative input terminal is connected to the node N2.

[0079] The control circuit 26 is configured to control the impedance adjustment operation of the impedance adjustment circuit 20 by controlling the operation of the setting circuit 22, the switches SW1 and SW2, and the voltage generation circuit 24. The control circuit 26 transmits the results of this impedance adjustment operation to the LSI tester 102. Based on the results of the impedance adjustment operation, the LSI tester 102 generates setting data DT indicating whether each of the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 is enabled or disabled, and writes this setting data DT to the nonvolatile memory 27 of the transmission device 10. This setting data DT is setting data for the output impedance of the driver 11. The control circuit 26 reads the setting data DT stored in the nonvolatile memory 27, for example, when the power supply of the transmission device 10 is started, and supplies this setting data DT to the pre-driver 12.

[0080] The nonvolatile memory 27 is configured to store the setting data DT of the driver 11 supplied from the LSI tester 102. Furthermore, the nonvolatile memory 27 is configured to supply the stored setting data DT to the control circuit 26 based on an instruction from the control circuit 26, for example, when the power supply of the transmission device 10 is turned on.

[0081] Here, the dummy driver 21 corresponds to a specific example of a "dummy driver" in an embodiment of the present disclosure. The node N1 corresponds to a specific example of a "first node" in an embodiment of the present disclosure. The node N2 corresponds to a specific example of a "second node" in an embodiment of the present disclosure. The power supply node of the power supply voltage VRH corresponds to a specific example of a "first power supply node" in an embodiment of the present disclosure. The power supply node of the power supply voltage VRL corresponds to a specific example of a "second power supply node" in an embodiment of the present disclosure. The circuit DUP corresponds to a specific example of a "first circuit" in an embodiment of the present disclosure. The circuit DDP corresponds to a specific example of a "second circuit" in an embodiment of the present disclosure. The circuit DUN corresponds to a specific example of a "third circuit" in an embodiment of the present disclosure. The circuit DDN corresponds to a specific example of a "fourth circuit" in an embodiment of the present disclosure. The transistor DMP1 corresponds to a specific example of a "first transistor" in an embodiment of the present disclosure. The transistor DMN2 corresponds to a specific example of a "second transistor" in an embodiment of the present disclosure. The transistor DMP3 corresponds to a specific example of a "third transistor" in an embodiment of the present disclosure. The transistor DMN4 corresponds to a specific example of a "fourth transistor" in an embodiment of the present disclosure. The resistor element DR1 corresponds to a specific example of a "first resistor element" in an embodiment of the present disclosure. The resistor element DR2 corresponds to a specific example of a "second resistor element" in an embodiment of the present disclosure. The resistor element DR3 corresponds to a specific example of a "third resistor element" in an embodiment of the present disclosure. The resistor element DR4 corresponds to a specific example of a "fourth resistor element" in an embodiment of the present disclosure. The signal SDUP corresponds to a specific example of a "first signal" in an embodiment of the present disclosure. The signal SDDP corresponds to a specific example of a "second signal" in an embodiment of the present disclosure. The signal SDUN corresponds to a specific example of a "third signal" in an embodiment of the present disclosure. The signal SDDN corresponds to a specific example of a "fourth signal" in an embodiment of the present disclosure. The switch SW1 corresponds to a specific example of a "first switch" in an embodiment of the present disclosure. The control circuit 26 corresponds to a specific example of a "control circuit" in an embodiment of the present disclosure.The current source 23 corresponds to a specific example of a "current source" in an embodiment of the present disclosure. The switch SW2 corresponds to a specific example of a "second switch" in an embodiment of the present disclosure. The voltage generation circuit 24 corresponds to a specific example of a "voltage generation circuit" in an embodiment of the present disclosure. The comparator 25 corresponds to a specific example of a "comparator" in an embodiment of the present disclosure.

[0082] The driver 11 corresponds to a specific example of a "driver" in an embodiment of the present disclosure. The output terminal OUTP corresponds to a specific example of a "first output terminal" in an embodiment of the present disclosure. The output terminal OUTN corresponds to a specific example of a "second output terminal" in an embodiment of the present disclosure. The circuit UP corresponds to a specific example of a "fifth circuit" in an embodiment of the present disclosure. The circuit DP corresponds to a specific example of a "sixth circuit" in an embodiment of the present disclosure. The circuit UN corresponds to a specific example of a "seventh circuit" in an embodiment of the present disclosure. The circuit DN corresponds to a specific example of an "eighth circuit" in an embodiment of the present disclosure. The transistor MP1 corresponds to a specific example of a "fifth transistor" in an embodiment of the present disclosure. The transistor MN2 corresponds to a specific example of a "sixth transistor" in an embodiment of the present disclosure. The transistor MP3 corresponds to a specific example of a "seventh transistor" in an embodiment of the present disclosure. The transistor MN4 corresponds to a specific example of an "eighth transistor" in an embodiment of the present disclosure. Resistor element R1 corresponds to a specific example of a "fifth resistor element" in an embodiment of the present disclosure. Resistor element R2 corresponds to a specific example of a "sixth resistor element" in an embodiment of the present disclosure. Resistor element R3 corresponds to a specific example of a "seventh resistor element" in an embodiment of the present disclosure. Resistor element R4 corresponds to a specific example of an "eighth resistor element" in an embodiment of the present disclosure. Signal SUP corresponds to a specific example of a "fifth signal" in an embodiment of the present disclosure. Signal SDP corresponds to a specific example of a "sixth signal" in an embodiment of the present disclosure. Signal SUN corresponds to a specific example of a "seventh signal" in an embodiment of the present disclosure. Signal SDN corresponds to a specific example of an "eighth signal" in an embodiment of the present disclosure.

[0083] [Operation and Function] Next, the operation and function of the transmitting device 10 of this embodiment will be described.

[0084] 1, 2, 4, and 5, an overview of the overall operation of the transmitter 10 will be described. The pre-driver 12 generates signals SUP, SDP, SUN, and SDN based on an input signal, and supplies these signals SUP, SDP, SUN, and SDN to the driver 11. The driver 11 drives transmission paths 90P and 90N based on the signals SUP, SDP, SUN, and SDN supplied from the pre-driver 12, thereby transmitting signals SIGP and SIGN.

[0085] In the impedance adjustment operation, the impedance adjustment circuit 20 uses the dummy driver 21 to generate setting data for the output impedance of the dummy driver 21. The LSI tester 102 generates setting data DT for the output impedance of the driver 11 based on the setting data for the output impedance of the dummy driver 21. The nonvolatile memory 27 of the impedance adjustment circuit 20 stores this setting data DT. The predriver 12 sets which circuits to enable and which circuits to disable among the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 based on the setting data DT read from the nonvolatile memory 27.

[0086] (Impedance Adjustment Operation) Figure 8 shows an example of the impedance adjustment operation. Figure 9 shows an example of the impedance adjustment operation, where (A) shows the operation of switch SW1, (B) shows the operation of switch SW2, (C) shows the waveform of the reference voltage VREF, (D) shows the waveform of the voltage (voltage VREP) at node N1, (E) shows the waveform of the output signal (signal COUT) of comparator 25, (F) shows a code (code CUN[3:0]) indicating whether circuits DUN3 to DUN0 are enabled or disabled, and (G) shows a code (code CDP[3:0]) indicating whether circuits DDP3 to DDP0 are enabled or disabled. Figures 10A and 10B show an example of the operating state in the impedance adjustment operation.

[0087] Here, the code CUN[3:0] is a code having four bits CUN[3], CUN[2], CUN[1], and CUN[0]. The bit CUN[0] indicates whether the circuit DUN0 is enabled or disabled. If the circuit DUN0 is enabled, the bit CUN[0] is "1", and if the circuit DUN0 is disabled, the bit CUN[0] is "0". Similarly, the bit CUN[1] indicates whether the circuit DUN1 is enabled or disabled, the bit CUN[2] indicates whether the circuit DUN2 is enabled or disabled, and the bit CUN[3] indicates whether the circuit DUN3 is enabled or disabled. The bit CUN[3] is the MSB (Most Significant Bit), and the bit CUN[0] is the LSB (Least Significant Bit).

[0088] Similarly, the code CDP[3:0] is a code having four bits CDP[3], CDP[2], CDP[1], and CDP[0]. The bit CDP[0] indicates whether the circuit DDP0 is enabled or disabled. If the circuit DDP0 is enabled, the bit CDP[0] is "1", and if the circuit DDP0 is disabled, the bit CDP[0] is "0". Similarly, the bit CDP[1] indicates whether the circuit DDP1 is enabled or disabled, the bit CDP[2] indicates whether the circuit DDP2 is enabled or disabled, and the bit CDP[3] indicates whether the circuit DDP3 is enabled or disabled. The bit CDP[3] is the MSB, and the bit CDP[0] is the LSB.

[0089] First, as shown in FIG. 10A, the control circuit 26 turns on the transistor DMP3 in the dummy driver 21 and turns off the transistors DMP1, DMN2, and DMN4 (step S101).

[0090] Next, as shown in FIG. 10A, the control circuit 26 turns switch SW1 off and switch SW2 on (step S102). In the example of FIG. 9, the control circuit 26 turns switch SW1 off at timing t11 and turns switch SW2 on at timing t12 (FIGS. 9A and 9B). As a result, as shown in FIG. 10A, current I flows from the power supply node of the power supply voltage VRH through transistor DMP3, resistor DR3, switch SW2, current source 23, and the ground node in this order. As a result, in the example of FIG. 9, at timing t12 when switch SW2 turns on, voltage VREP begins to change (FIG. 9D). In this example, the initial value of code CUN[3:0] associated with circuit DUN is "0001." Therefore, circuits DUN3 to DUN1 are disabled, and circuit DUN0 is enabled, resulting in a large impedance for circuit DUN. The voltage VREP is lower than the power supply voltage VRH by the voltage drop in this circuit DUN.

[0091] In this example, in step S101, the transistor DMN2 is turned off, but this is not limiting and the transistor DMN2 may be turned on. Even in this case, as shown in FIG. 10A, the transistor DMP1 is in the off state and the switch SW1 is also in the off state, so no current flows through the transistor DMN2.

[0092] Next, the control circuit 26 sequentially switches the setting of the circuit DUN, and determines the setting of the circuit DUN based on the output signal (signal COUT) of the comparator 25 (step S103).

[0093] In step S103, the voltage generating circuit 24 first sets the ratio of the resistance value of the variable resistance element RH to the resistance value of the variable resistance element RL to 1:3 based on an instruction from the control circuit 26, thereby setting the reference voltage VREF to "3 / 4×(VRH−VRL)+VRL." In the example of FIG. 9, at timing t13, the reference voltage VREF begins to rise and reaches "3 / 4×(VRH−VRL)+VRL" (FIG. 9(C)). At that time, at timing t14, the reference voltage VREF exceeds the voltage VREP, and the signal COUT changes from low to high (FIG. 9(E)).

[0094] Then, the control circuit 26 sequentially changes the code CUN[3:0] associated with the circuit DUN from "0001" to "1111" (see FIG. 9(F)). The setting circuit 22 sequentially sets the circuit DUN based on instructions from the control circuit 26. As a result, the impedance of the circuit DUN gradually decreases in accordance with the change in the code CUN[3:0]. In the example of FIG. 9, during a period P1 from timing t15 to t17, the control circuit 26 sequentially changes the code CUN[3:0] associated with the circuit DUN from "0001" to "1111". As a result, the voltage VREP gradually increases during this period P1 (see FIG. 9(D)). In this example, at timing t16, the voltage VREP exceeds the reference voltage VREF, and the signal COUT changes from high to low (see FIG. 9(E)). The control circuit 26 stores the code CUN[3:0] at timing t16 when the signal COUT changes from high to low in a register included in the control circuit 26. In this way, the control circuit 26 determines the setting of the circuit DUN.

[0095] Next, as shown in FIG. 10B, the control circuit 26 turns on the transistors DMN2 and DMP3 in the dummy driver 21 and turns off the transistors DMP1 and DMN4 (step S104).

[0096] Next, as shown in FIG. 10B, the control circuit 26 turns switch SW1 on and switch SW2 off (step S105). In the example of FIG. 9, the control circuit 26 turns switch SW2 off at timing t18 and turns switch SW1 on at timing t19. As a result, as shown in FIG. 10B, current I flows from the power supply node of the power supply voltage VRH through transistor DMP3, resistor DR3, switch SW1, resistor DR2, transistor DMN2, and the power supply node of the power supply voltage VRL in this order. As a result, in the example of FIG. 9, the voltage VREP begins to change at timing t19. In this example, the initial value of the code CDP[3:0] associated with the circuit DDP is "0001." Therefore, circuits DDP3 to DDP1 are disabled and circuit DDP0 is enabled, resulting in a large impedance for the circuit DDP. The voltage VREP is divided by the impedance of the circuit DUN and the impedance of the circuit DDP.

[0097] Next, the control circuit 26 sequentially switches the setting of the circuit DDP and determines the setting of the circuit DDP based on the output signal (signal COUT) of the comparator 25 (step S106).

[0098] In step S106, first, the voltage generating circuit 24 sets the reference voltage VREF to "½×(VRH−VRL)+VRL" by setting the ratio of the resistance value of the variable resistance element RH to the resistance value of the variable resistance element RL to 1:1 based on an instruction from the control circuit 26. In the example of FIG. 9, at timing t20, the reference voltage VREF decreases to "½×(VRH−VRL)+VRL" (FIG. 9C).

[0099] Then, the control circuit 26 sets the code CUN[3:0] relating to the circuit DUN to the value stored in the register in step S103 (FIG. 9(F)). The setting circuit 22 sets the circuit DUN based on the instruction from the control circuit 26.

[0100] Then, the control circuit 26 sequentially changes the code CDP[3:0] associated with the circuit DDP from "0001" to "1111" (see FIG. 9(G)). The setting circuit 22 sequentially sets the circuit DDP based on instructions from the control circuit 26. As a result, the impedance of the circuit DDP gradually decreases in accordance with the change in the code CDP[3:0]. In the example of FIG. 9, during a period P2 from timing t21 to t23, the control circuit 26 sequentially changes the code CDP[3:0] associated with the circuit DDP from "0001" to "1111". As a result, the voltage VREP gradually decreases during this period P2 (see FIG. 9(D)). In this example, at timing t22, the voltage VREP falls below the reference voltage VREF, and the signal COUT changes from low to high (see FIG. 9(E)). The control circuit 26 stores the code CDP[3:0] at timing t22 when the signal COUT changes from low to high in a register included in the control circuit 26. In this way, the control circuit 26 determines the setting of the circuit DDP.

[0101] Next, the control circuit 26 supplies the circuit DUN and DDP settings determined and stored in the register in steps S103 and S106 to the LSI tester 102 (step S107).

[0102] Based on the settings of the circuits DUN and DDP, the LSI tester 102 generates setting data DT for the driver 11 to be written to the nonvolatile memory 27. For example, the LSI tester 102 can set the settings of the circuits UP and UN in the driver 11 to the same setting as the setting of the circuit DUN in the dummy driver 21, and set the settings of the circuits DP and DN in the driver 11 to the same setting as the setting of the circuit DDP in the dummy driver 21.

[0103] For example, the setting of circuit UN in driver 11 is the same as the setting of circuit DUN in dummy driver 21. Specifically, the enable / disable setting of circuits UN3, UN2, UN1, and UN0 in driver 11 is the same as the enable / disable setting of circuits DUN3, DUN2, DUN1, and DUN0 in dummy driver 21. For example, when circuit DUN0 is enabled, circuit UN0 is also enabled, and when circuit DUN0 is disabled, circuit UN0 is disabled. Since the impedance of dummy driver 21 is four times the impedance of driver 11, circuit UN0 has 32 paths as shown in FIG. 4, and circuit DUN0 has eight paths as shown in FIG. 7. In other words, the enable / disable setting of circuit UN0, which has 32 paths, is the same as the enable / disable setting of circuit DUN0, which has eight paths. Similarly, the enable or disable setting in circuit UN1 having 16 paths is set to the same setting as the enable or disable setting in circuit DUN1 having four paths, the enable or disable setting in circuit UN2 having eight paths is set to the same setting as the enable or disable setting in circuit DUN2 having two paths, and the enable or disable setting in circuit UN3 having four paths is set to the same setting as the enable or disable setting in circuit DUN3 having one path.

[0104] Similarly, the setting of the circuit UP in the driver 11 is the same as the setting of the circuit DUN in the dummy driver 21. The setting of the circuit DP in the driver 11 is the same as the setting of the circuit DDP in the dummy driver 21. The setting of the circuit DN in the driver 11 is the same as the setting of the circuit DDP in the dummy driver 21.

[0105] In this way, the LSI tester 102 generates the setting data DT. Then, the LSI tester 102 performs a write operation to write this setting data DT into the nonvolatile memory 27 of the transmitting device 10.

[0106] The nonvolatile memory 27 stores the setting data DT supplied from the LSI tester 102 based on the write operation of the LSI tester 102 (step S108).

[0107] This completes the process.

[0108] Thereafter, each time the power of the transmitter 10 is turned on, the control circuit 26 of the transmitter 10 reads the setting data DT stored in the nonvolatile memory 27 and supplies this setting data DT to the pre-driver 12. The pre-driver 12 sets the circuits UP, DP, UN, and DN in the driver 11 based on this setting data DT. As a result, each of the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 is set to be enabled or disabled based on the setting data DT. In this way, the output impedance of the driver 11 is adjusted in the transmitter 10.

[0109] For example, in a state where the transmitting device 10 is connected to the receiving device 100, the BIST circuit 13 can check whether the output impedance of the driver 11 is set appropriately.

[0110] For example, during the test period, as shown in FIG. 3A, the BIST circuit 13 turns on transistors MP1 and MN4 and turns off transistors MN2 and MP3. Based on the voltages at the output terminals OUTP and OUTN during this period, the BIST circuit 13 checks whether the impedances of the circuit UP and the circuit DN are set appropriately. That is, in this state, the voltage at the output terminal OUTP is desired to be 3 / 4 × (VRH − VRL) + VRL, and the voltage at the output terminal OUTN is desired to be 1 / 4 × (VRH − VRL) + VRL. For example, if the impedance of the circuit UP deviates from 50 Ω or if the impedance of the circuit DN deviates from 50 Ω, the voltages at the output terminals OUTP and OUTN will deviate from these desired voltages. Therefore, the BIST circuit 13 checks whether the impedance of the circuit UP and the impedance of the circuit DN are set appropriately based on the voltages of the output terminals OUTP and OUTN.

[0111] Similarly, for example, during a test period, as shown in FIG. 3B , the BIST circuit 13 turns on transistors MN2 and MP3 and turns off transistors MP1 and MN4. Then, based on the voltages of the output terminals OUTP and OUTN during this period, the BIST circuit 13 checks whether the impedances of the circuits UN and DP are set appropriately. That is, in this state, the voltage of the output terminal OUTP is desired to be ¼×(VRH−VRL)+VRL, and the voltage of the output terminal OUTN is desired to be ¾×(VRH−VRL)+VRL. For example, if the impedance of the circuit UN deviates from 50 Ω or if the impedance of the circuit DP deviates from 50 Ω, the voltages of the output terminals OUTP and OUTN will deviate from these desired voltages. Therefore, the BIST circuit 13 checks whether the impedance of the circuit UN and the impedance of the circuit DP are set appropriately based on the voltages of the output terminals OUTP and OUTN.

[0112] In this example, the BIST circuit 13 checks whether the output impedance of the driver 11 is set appropriately when the transmitting device 10 is connected to the receiving device 100, but the present invention is not limited to this. For example, when the transmitting device 10 is connected to the LSI tester 102, the impedance adjustment circuit 20 may adjust the output impedance, and then the BIST circuit 13 may check whether the output impedance of the driver 11 is set appropriately.

[0113] As described above, the transmitter 10 is provided with the dummy driver 21, the first switch (switch SW1), the driver 11, and the control circuit 26. The dummy driver 21 is provided on a path connecting the first node (node ​​N1) and the first power supply node (power supply node of the power supply voltage VRH) and includes a first circuit (circuit DUP) that is provided on a path connecting the first node (node ​​N1) and the second power supply node (power supply node of the power supply voltage VRL) and includes a first transistor (transistor DMP1) and a first resistor element (resistance element DR1) that can be turned on and off based on a first signal (signal SDUP), a second circuit (circuit DDP) that is provided on a path connecting the first node (node ​​N1) and the second power supply node (power supply node of the power supply voltage VRL) and includes a second transistor (transistor DMN2) and a second resistor element (resistance element DR2) that can be turned on and off based on a second signal (signal SDDP), and a second circuit (circuit DDP) that is provided on a path connecting the second node (node ​​N2) and the first power supply node (power supply node of the power supply voltage VRH). The power supply voltage VRL is connected to a first node (node ​​N1) and a second node (node ​​N2) via a third circuit (circuit DUN) including a third transistor (transistor DMP3) and a third resistor element (resistor element DR3) that can be turned on and off based on a third signal (signal SDUN), and a fourth circuit (circuit DDN) that is connected to a second node (node ​​N2) and a second power supply node (power supply node for a power supply voltage VRL) via a fourth transistor (transistor DMN4) and a fourth resistor element (resistor element DR4) that can be turned on and off based on a fourth signal (signal SDDN), and the impedance of the first circuit, the second circuit, the third circuit, and the fourth circuit is changeable. A first switch (switch SW1) is provided on the path connecting the first node (node ​​N1) and the second node (node ​​N2).The driver 11 includes a fifth circuit (circuit UP) that is provided on a path connecting the first output terminal (output terminal OUTP) and the first power supply node (power supply node of the power supply voltage VRH) and includes a fifth transistor (transistor MP1) and a fifth resistor element (resistor element R1) that can be turned on and off based on a fifth signal (signal SUP), a sixth circuit (circuit DP) that is provided on a path connecting the first output terminal (output terminal OUTP) and the second power supply node (power supply node of the power supply voltage VRL) and includes a sixth transistor (transistor MN2) and a sixth resistor element (resistor element R2) that can be turned on and off based on a sixth signal (signal SDP), and a sixth circuit (circuit DP) that is provided on a path connecting the second output terminal (output terminal OUTN) and the first power supply node (power supply node of the power supply voltage VRL). The fifth circuit (circuit UN) is provided in a path connecting the first output terminal (output terminal OUTN) and the second power supply node (power supply node for the power supply voltage VRL) and includes a seventh transistor (transistor MP3) and a seventh resistor element (resistance element R3) that can be turned on and off based on a seventh signal (signal SUN), and an eighth circuit (circuit DN) is provided in a path connecting the second output terminal (output terminal OUTN) and the second power supply node (power supply node for the power supply voltage VRL) and includes an eighth transistor (transistor MN4) and an eighth resistor element (resistance element R4) that can be turned on and off based on an eighth signal (signal SDN), and the impedance of the fifth circuit, the sixth circuit, the seventh circuit, and the eighth circuit are changeable. The control circuit 26 can set the impedance of the first circuit, the impedance of the second circuit, the impedance of the third circuit, the impedance of the fourth circuit, the impedance of the fifth circuit, the impedance of the sixth circuit, the impedance of the seventh circuit, and the impedance of the eighth circuit, and can control the operation of the first switch (switch SW1). The control circuit 26 is capable of performing a first operation.The first operation includes turning on the first switch (switch SW1), turning on the second transistor (transistor DMN2) and the third transistor (transistor DMP3) and turning off the first transistor (transistor DMP1) and the fourth transistor (transistor DMN4), sequentially changing the impedance of the second circuit (circuit DDP), and setting the impedance of the sixth circuit (circuit DP) and the impedance of the eighth circuit (circuit DN) in the first driver (driver 11) based on first setting data that is set based on the voltage of the second node (node ​​N2) when the impedance of the second circuit (circuit DDP) is sequentially changed. As a result, in the first operation, as shown in FIG. 10B , a current I flows from the power supply node of the power supply voltage VRH through the transistor DMP3, the resistor element DR3, the switch SW1, the resistor element DR2, the transistor DMN2, and the power supply node of the power supply voltage VRL in this order. As a result, by setting the circuit DDP so that the voltage of the node N2 becomes the midpoint voltage between the power supply voltage VRH and the power supply voltage VRL, the output impedance of the dummy driver 21 can be adjusted, and the output impedance of the driver 11 can be adjusted based on the setting of this dummy driver 21. As a result, the output impedance of the transmitter 10 can be adjusted effectively.

[0114] 10A, if the circuit DUN is set using the current source 23 that sinks current, and then the circuit DDP is set using a current source that similarly sinks current, a current source like this will be required. Such a current source that sinks current is configured using a P-type MOS transistor, which increases the circuit size.

[0115] On the other hand, in the transmitter 10, the circuit DDP is set so that the voltage of the node N2 becomes the midpoint voltage between the power supply voltage VRH and the power supply voltage VRL. This allows the circuit DDP to be set without using a current source that injects current. As a result, the transmitter 10 does not need to use a current source that injects current, which allows the circuit size to be reduced and the output impedance to be adjusted effectively.

[0116] The transmitter 10 further includes a current source (current source 23) capable of causing a current to flow from the third node toward the ground node, and a second switch (switch SW2) provided in a path connecting the second node and the third node. The control circuit 26 is configured to be able to perform a second operation before the first operation. The second operation includes turning the first switch (switch SW1) off and the second switch (switch SW2) on, turning the third transistor (transistor DMP3) on and the fourth transistor (transistor DMN4) off, sequentially changing the impedance of the third circuit (circuit DUN), and setting the impedance of the fifth circuit (circuit UP) and the impedance of the seventh circuit (circuit UN) in the driver (driver 11) based on second setting data set based on the voltage of the second node (node ​​N2) when the impedance of the third circuit (circuit DUN) is sequentially changed. 10A, in the second operation, current I flows from the power supply node of power supply voltage VRH through transistor DMP3, resistor element DR3, switch SW2, and current source 23 in this order. In transmitter 10, by setting circuit DUN so that the voltage of node N2 becomes "3 / 4×(VRH−VRL)+VRL," the output impedance of dummy driver 21 can be adjusted, and the output impedance of driver 11 can be adjusted based on the setting of dummy driver 21. As a result, in transmitter 10, the output impedance can be adjusted effectively.

[0117] That is, for example, when using a current source of an LSI tester as in the technology described in Patent Document 1, a relay is used to turn this current source on and off, so it may take time for the current and voltage to stabilize when the relay is turned on and off. In particular, when using the current source of an LSI tester to perform a current sink operation and a current inflow operation, two relays are turned on and off, so it may take even longer.

[0118] On the other hand, the transmitter 10 is provided with, for example, the current source 23, and can control the current source without using a relay, thereby shortening the time until the current and voltage stabilize. Also, the transmitter 10 uses the current source 23 to perform only the operation of sinking the current, thereby shortening the total time required for turning the relay on and off. As a result, the transmitter 10 can effectively adjust the output impedance.

[0119] In addition, in the transmitting device 10, the second circuit (circuit DDP) in the dummy driver 21 has a plurality of partial paths arranged in parallel with each other, the second transistor (transistor DMN2) has a transistor (transistor MN) arranged in each of the plurality of partial paths in the second circuit, the second resistive element (resistive element DR2) has a resistive element (resistive element RES) arranged in each of the plurality of partial paths in the second circuit, the second circuit has a plurality of partial circuits (circuits DDP3 to DDP0) including a first partial circuit (e.g., circuit DDP1) having a first number (e.g., four) of partial paths and a second partial circuit (e.g., circuit DDP0) having a second number (e.g., eight) of partial paths that is twice the first number, and the impedance of the second circuit is adjustable by setting the plurality of partial circuits in the second circuit to be enabled or disabled on a partial circuit basis. Further, the sixth circuit (circuit DP) in the driver 11 has a plurality of partial paths arranged in parallel with each other, the sixth transistor (transistor MN2) has a transistor (transistor MN) arranged in each of the plurality of partial paths in the sixth circuit, the sixth resistor (resistor element R2) has a resistor (resistor element RES) arranged in each of the plurality of partial paths in the sixth circuit, the sixth circuit has a plurality of partial circuits (circuits DP3 to DP0) including a third partial circuit (e.g., circuit DP1) having a third number (e.g., 16) of partial paths and a fourth partial circuit (e.g., circuit DP0) having a fourth number (e.g., 32) of partial paths that is twice the third number, and the impedance of the sixth circuit is adjustable by setting the plurality of partial circuits in the sixth circuit to be enabled or disabled on a partial circuit basis. The third number (e.g., 16) in the third partial circuit (e.g., circuit DP1) of the driver 11 is greater than the first number (e.g., 4) in the first partial circuit (e.g., circuit DDP1) of the dummy driver 21, and the fourth number (e.g., 32) in the fourth partial circuit (e.g., circuit DP0) of the driver 11 is greater than the second number (e.g., 8) in the second partial circuit (e.g., circuit DDP0) of the dummy driver 21.The control circuit 26 is capable of determining whether to enable or disable a first partial circuit (e.g., circuit DDP1) in the second circuit and whether to enable or disable a second partial circuit (e.g., circuit DDP2) in the second circuit based on the voltage at the second node (node ​​N2) when the impedance of the second circuit is sequentially changed. The enable or disable setting of the third partial circuit (e.g., circuit DP1) in the sixth circuit of the driver 11 is set to be the same as the enable or disable setting of the first partial circuit (e.g., circuit DDP1) in the second circuit of the dummy driver 21. The enable or disable setting of the fourth partial circuit (e.g., circuit DP0) in the sixth circuit of the driver 11 is set to be the same as the enable or disable setting of the second partial circuit (e.g., circuit DDP0) in the second circuit of the dummy driver 21. As a result, in the transmitting device 10, for example, the settings of the circuits DDP3, DDP2, DDP1, and DDP0 in the dummy driver 21 can be used as they are as the settings of the circuits DP3, DP2, DP1, and DP0 in the driver 11. As a result, in the transmitting device 10, the impedance setting in the driver 11 can be easily determined based on the impedance setting in the dummy driver 21, and the output impedance can be adjusted effectively.

[0120] [Effect] As described above, in this embodiment, a dummy driver, a first switch, a driver, and a control circuit are provided. The dummy driver has a first circuit provided on a path connecting a first node and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal, a second circuit provided on a path connecting the first node and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal, a third circuit provided on a path connecting the second node and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal, and a fourth circuit provided on a path connecting the second node and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, and the impedance of the first circuit, the second circuit, the third circuit, and the fourth circuit are changeable. The first switch is provided on a path connecting the first node and the second node. The driver has a fifth circuit provided on a path connecting the first output terminal and the first power supply node, the fifth circuit including a fifth transistor and a fifth resistor element that can be turned on and off based on a fifth signal, a sixth circuit provided on a path connecting the first output terminal and the second power supply node, the sixth circuit including a sixth transistor and a sixth resistor element that can be turned on and off based on a sixth signal, a seventh circuit provided on a path connecting the second output terminal and the first power supply node, the seventh circuit including a seventh transistor and a seventh resistor element that can be turned on and off based on a seventh signal, and an eighth circuit provided on a path connecting the second output terminal and the second power supply node, the eighth circuit including an eighth transistor and an eighth resistor element that can be turned on and off based on an eighth signal, and the driver is capable of changing impedances of the fifth circuit, the sixth circuit, the seventh circuit, and the eighth circuit. The control circuit is capable of setting the first circuit impedance, the second circuit impedance, the third circuit impedance, the fourth circuit impedance, the fifth circuit impedance, the sixth circuit impedance, the seventh circuit impedance, and the eighth circuit impedance, and is capable of controlling the operation of the first switch.The control circuit is capable of performing a first operation. The first operation includes turning on the first switch, turning on the second transistor and the third transistor, turning off the first transistor and the fourth transistor, sequentially changing the impedance of the second circuit, and setting the impedance of the sixth circuit and the impedance of the eighth circuit in the first driver based on first setting data that is set based on the voltage of the second node when the impedance of the second circuit is sequentially changed. As a result, the output impedance can be effectively adjusted.

[0121] In this embodiment, the circuit further includes a current source capable of causing a current to flow from the third node toward the ground node, and a second switch provided in a path connecting the second node and the third node. The control circuit is capable of performing a second operation before the first operation. The second operation includes turning the first switch off and the second switch on, turning the third transistor on and the fourth transistor off, sequentially changing the impedance of the third circuit, and setting the impedance of the fifth circuit and the impedance of the seventh circuit in the driver based on second setting data set based on the voltage of the second node when the impedance of the third circuit is sequentially changed. As a result, the output impedance can be effectively adjusted.

[0122] In this embodiment, the second circuit in the dummy driver has a plurality of partial paths arranged in parallel with each other, the second transistor has a transistor provided in each of the plurality of partial paths in the second circuit, the second resistive element has a resistive element provided in each of the plurality of partial paths in the second circuit, the second circuit has a plurality of partial circuits including a first partial circuit having a first number of partial paths and a second partial circuit having a second number of partial paths that is twice the first number, and the impedance of the second circuit is adjustable by setting the plurality of partial circuits in the second circuit to be enabled or disabled on a partial circuit basis. The sixth circuit in the driver has a plurality of partial paths arranged in parallel with each other, the sixth transistor has a transistor provided in each of the plurality of partial paths in the sixth circuit, the sixth resistor element has a resistor element provided in each of the plurality of partial paths in the sixth circuit, the sixth circuit has a plurality of partial circuits including a third partial circuit having a third number of partial paths and a fourth partial circuit having a fourth number of partial paths that is twice the third number, and the impedance of the sixth circuit is adjustable by enabling or disabling the plurality of partial circuits in the sixth circuit on a partial circuit basis. The third number in the third partial circuit of the driver is greater than the first number in the first partial circuit of the dummy driver, and the fourth number in the fourth partial circuit of the driver is greater than the second number in the second partial circuit of the dummy driver. The control circuit 26 is capable of determining whether to enable or disable the first partial circuit in the second circuit and whether to enable or disable the second partial circuit in the second circuit based on the voltage at the second node when the impedance of the second circuit is sequentially changed. The enable or disable setting of the third partial circuit in the sixth circuit of the driver is set to be the same as the enable or disable setting of the first partial circuit in the second circuit of the dummy driver. The enable or disable setting of the fourth partial circuit in the sixth circuit of the driver is set to be the same as the enable or disable setting of the second partial circuit in the second circuit of the dummy driver. As a result, the output impedance can be effectively adjusted.

[0123] [Variation 1-1] In the above embodiment, the driver 11 has a circuit configuration as shown in FIG. 2, and the dummy driver 21 has a circuit configuration as shown in FIG. 6, but this is not limited to this.

[0124] For example, the driver 11C1 shown in FIG. 11 may have four N-type MOS transistors. In this example, the circuit UP includes a transistor MN1 and a resistor R1. The transistor MN1 is an N-type MOS transistor. A signal SUP is supplied to the gate of the transistor MN1, the drain is connected to the power supply node of the power supply voltage VRH, and the source is connected to one end of the resistor R1. The circuit UN includes a transistor MN3 and a resistor R3. The transistor MN3 is an N-type MOS transistor. A signal SUN is supplied to the gate of the transistor MN3, the drain is connected to the power supply node of the power supply voltage VRH, and the source is connected to one end of the resistor R3. The polarities of the signals SUP and SUN in this modification are opposite to those of the signals SUP and SUN in the above embodiment. When the driver 11C1 has four N-type MOS transistors as shown in FIG. 11, the dummy driver 21 is also configured to have four N-type MOS transistors.

[0125] 12, for example, in the driver 11 shown in Fig. 11, the connections of the transistor MN1 and the resistor element R1 may be interchanged, the transistor MN2 and the resistor element R2 may be interchanged, the transistor MN3 and the resistor element R3 may be interchanged, and the transistor MN4 and the resistor element R4 may be interchanged. In this case, the transistors and resistor elements are also interchanged in the dummy driver 21.

[0126] [Variation 1-2] In the above embodiment, the LSI tester 102 generates the setting data DT for the driver 11 based on the settings of the circuits DUN and DDP, but this is not limiting. Furthermore, for example, in addition to the LSI tester 102, the control circuit 26 may also generate the setting data DT for the driver 11 based on the settings of the circuits DUN and DDP. In this case, for example, when the transmission device 10 is operating, the impedance adjustment circuit 20 generates setting data DT for the output impedance of the driver 11 using the dummy driver 21. Based on this setting data DT, the pre-driver 12 can set which circuits to enable and which circuits to disable among the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11.

[0127] Figure 13 shows an example of operation of the communication system 1 according to this modified example, where (A) shows the operation of the communication system 1, (B) shows the operation of the impedance adjustment circuit 20, and (C) shows the waveforms of the signals SIGP and SIGN.

[0128] In this example, the communication system 1 performs communication operations before timing t32 (FIG. 13(A)). Therefore, the transmitting device 10 transmits signals SIGP and SIGN indicating transmission data during this period (FIG. 13(C)). During the period from timing t31 to t32, the impedance adjustment circuit 20 of the transmitting device 10 uses the dummy driver 21 to perform steps S101 to S106 in FIG. 8 to generate setting data DT for the output impedance of the driver 11 (FIG. 13(B)). In this example, the impedance adjustment circuit 20 does not store this setting data DT in the nonvolatile memory 27. In other words, the setting data DT stored in the nonvolatile memory 27 remains the data stored before shipping.

[0129] Then, during the period from timing t32 to t33, the communication system 1 stops communication (FIG. 13(A)). The impedance adjustment circuit 20 applies this setting data DT and supplies this setting data DT to the pre-driver 12 (FIG. 13(B)). The pre-driver 12 sets the output impedance of the driver 11 based on this setting data DT. As a result, in this example, the amplitudes of the signals SIGP and SIGN increase (FIG. 13(C)).

[0130] Then, at timing t33, the communication system 1 resumes communication operation (FIG. 13(A)). Therefore, the transmitting device 10 transmits signals SIGP and SIGN indicating transmission data in the period after timing t33 ​​(FIG. 13(C)).

[0131] For example, when the communication system 1 transmits image data, the period for applying the setting data DT is set during a blanking period. This allows the communication system 1 to adjust the output impedance of the driver 11 according to the operating environment of the transmitting device 10, such as the ambient temperature and power supply voltage.

[0132] Figure 14 shows an example of operation of another communication system 1 related to this modified example, where (A) shows the operation of the communication system 1, (B) shows the operation of the impedance adjustment circuit 20, and (C) shows the waveforms of the signals SIGP and SIGN.

[0133] In this example, the communication system 1 performs a training operation upon power-on before timing t36 (FIG. 14A). During the training operation, the communication system 1 does not perform communication (FIG. 14C). During the period from timing t34 to t35, the impedance adjustment circuit 20 of the transmitting device 10 uses the dummy driver 21 to perform steps S101 to S106 in FIG. 8 to generate setting data DT for the output impedance of the driver 11 (FIG. 14B). In this example, the impedance adjustment circuit 20 does not store this setting data DT in the nonvolatile memory 27. That is, the setting data DT stored in the nonvolatile memory 27 remains the data stored before shipment. Then, during the period from timing t35 to t36, the impedance adjustment circuit 20 applies this setting data DT and supplies this setting data DT to the pre-driver 12 (FIG. 14B). The pre-driver 12 sets the output impedance of the driver 11 based on this setting data DT (FIG. 14B). In this example, this increases the amplitude of the signals SIGP and SIGN.

[0134] Then, at timing t36, the communication system 1 starts communication operation (FIG. 14(A)). Therefore, the transmitting device 10 transmits signals SIGP and SIGN indicating transmission data in the period after timing t36 (FIG. 14(C)).

[0135] As a result, in the communication system 1, the output impedance of the driver 11 can be adjusted according to the operating environment of the transmitter 10, such as the ambient temperature and power supply voltage.

[0136] In this example, the communication system 1 does not perform communication during the period in which the training operation is performed, but this is not limiting. Instead, for example, the communication system 1 may perform communication during the period in which the training operation is performed.

[0137] 1, the impedance adjustment circuit 20 and the BIST circuit 13 are provided separately, but this is not limiting, and instead, for example, the impedance adjustment circuit 20 may have the function of the BIST circuit 13. This modification will be described in detail below.

[0138] 15 shows an example of the configuration of a communication system 1A according to this modification. The communication system 1A includes a transmitter 10A. The transmitter 10A includes an impedance adjustment circuit 20A.

[0139] 16 shows an example of the configuration of the impedance adjustment circuit 20 A. The impedance adjustment circuit 20 A has switches SW3 and SW4 and a control circuit 26 A.

[0140] The switch SW3 is configured to connect the node N4 to the output terminal OUTP or to connect the node N4 to the output terminal OUTN based on an instruction from the control circuit 26 A. Furthermore, the switch SW3 is configured to connect the node N4 to neither the output terminal OUTP nor OUTN based on an instruction from the control circuit 26 A.

[0141] The switch SW4 is configured to connect the negative input terminal of the comparator 25 to the node N2 or to connect the negative input terminal of the comparator 25 to the node N4 based on an instruction from the control circuit 26A.

[0142] Similar to the control circuit 26 according to the above embodiment, the control circuit 26A is configured to control the impedance adjustment operation in the impedance adjustment circuit 20A by controlling the operation of the setting circuit 22, the switches SW1 to SW4, and the voltage generation circuit 24. Furthermore, after the output impedance of the driver 11 has been adjusted, the control circuit 26A is able to check whether the output impedance of the driver 11 has been appropriately set based on the voltages of the output terminals OUTP and OUTN.

[0143] 16, when performing impedance adjustment operation, the control circuit 26A controls the operation of the switch SW4 so as to connect the negative input terminal of the comparator 25 to the node N2. The control circuit 26A also controls the operation of the switch SW3 so as not to connect the node N4 to either the output terminal OUTP or OUTP. This allows the impedance adjustment circuit 20A to operate in the same manner as in the above embodiment.

[0144] For example, when the transmitting device 10A is connected to the receiving device 100, the impedance adjustment circuit 20A can check whether the output impedance of the driver 11 is set appropriately. First, the control circuit 26A controls the operation of the switch SW4 so as to connect the negative input terminal of the comparator 25 to the node N4.

[0145] 3A, the control circuit 26A turns on the transistors MP1 and MN4 of the driver 11 and turns off the transistors MN2 and MP3. If the output impedance of the driver 11 is set appropriately, the voltage of the output terminal OUTP is desirably 3 / 4×(VRH−VRL)+VRL, and the voltage of the output terminal OUTN is desirably 1 / 4×(VRH−VRL)+VRL.

[0146] Next, the control circuit 26A controls the operation of the switch SW3 to connect the node N4 to the output terminal OUTP. As a result, the voltage at the output terminal OUTP is supplied to the negative input terminal of the comparator 25. The control circuit 26A then sets the ratio of the resistance values ​​of the variable resistor element RH and the variable resistor element RL in the voltage generating circuit 24 to 1:3. As a result, the reference voltage VREF becomes "3 / 4 × (VRH - VRL) + VRL." The control circuit 26A then slightly changes the impedance of the circuit UP associated with the transistor MP1, for example, and checks whether the output signal of the comparator 25 changes.

[0147] Next, the control circuit 26A controls the operation of the switch SW3 to connect the node N4 to the output terminal OUTN. As a result, the voltage at the output terminal OUTN is supplied to the negative input terminal of the comparator 25. The control circuit 26A then sets the ratio of the resistance value of the variable resistor RH to the resistance value of the variable resistor RL in the voltage generating circuit 24 to 3:1. As a result, the reference voltage VREF becomes "1 / 4 × (VRH - VRL) + VRL." The control circuit 26A then slightly changes the impedance of the circuit DN associated with the transistor MN4, for example, and checks whether the output signal of the comparator 25 changes.

[0148] If the output signal of the comparator 25 changes when the impedance of the circuit UP is slightly changed, and if the output signal of the comparator 25 changes when the impedance of the circuit DN is slightly changed, the control circuit 26A determines that the impedances of the circuits UP and DN are set appropriately.

[0149] 3B, the control circuit 26A turns on the transistors MN2 and MP3 of the driver 11 and turns off the transistors MP1 and MN4. If the output impedance of the driver 11 is set appropriately, the voltage of the output terminal OUTP is desirably 1 / 4×(VRH−VRL)+VRL, and the voltage of the output terminal OUTN is desirably 3 / 4×(VRH−VRL)+VRL.

[0150] Next, the control circuit 26A controls the operation of the switch SW3 to connect the node N4 to the output terminal OUTP. As a result, the voltage at the output terminal OUTP is supplied to the negative input terminal of the comparator 25. The control circuit 26A then sets the ratio of the resistance values ​​of the variable resistor element RH and the variable resistor element RL in the voltage generating circuit 24 to 3:1. As a result, the reference voltage VREF becomes "1 / 4 × (VRH - VRL) + VRL." The control circuit 26A then slightly changes the impedance of the circuit UN associated with the transistor MP3, for example, and checks whether the output signal of the comparator 25 changes.

[0151] Next, the control circuit 26A controls the operation of the switch SW3 to connect the node N4 to the output terminal OUTN. As a result, the voltage at the output terminal OUTN is supplied to the negative input terminal of the comparator 25. The control circuit 26A then sets the ratio of the resistance values ​​of the variable resistor element RH and the variable resistor element RL in the voltage generating circuit 24 to 1:3. As a result, the reference voltage VREF becomes "3 / 4 × (VRH - VRL) + VRL." The control circuit 26A then slightly changes the impedance of the circuit DP associated with the transistor MN2, for example, and checks whether the output signal of the comparator 25 changes.

[0152] If the output signal of the comparator 25 changes when the impedance of the circuit UN is slightly changed, and if the output signal of the comparator 25 changes when the impedance of the circuit DP is slightly changed, the control circuit 26A determines that the impedances of the circuits UN and DP are set appropriately.

[0153] In this way, the impedance adjustment circuit 20 checks whether the impedances of the circuits UP, DP, UN, and DN are set appropriately, thereby checking whether the output impedance of the driver 11 is set appropriately.

[0154] Thereafter, the control circuit 26A controls the operation of the switch SW3 so that the node N4 is not connected to either of the output terminals OUTP and OUTP, and the communication system 1A then performs communication operations.

[0155] [Variation 1-4] In the above embodiment, as shown in FIG. 1, one communication lane is provided. However, this is not limited to this. Instead, multiple communication lanes (two communication lanes L1 and L2 in this example) may be provided, as in the communication system 1B shown in FIG. 17. The communication system 1B includes a transmitting device 10B and a receiving device 100B. The impedance adjustment circuit 20 of the transmitting device 10B performs impedance adjustment operations, as in the above embodiment. The impedance adjustment circuit 20 then supplies setting data DT to the pre-driver 12 in the communication lane L1 and to the pre-driver 12 in the communication lane L2. The pre-driver 12 in the communication lane L1 configures the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 of the communication lane L1 based on the setting data DT. The pre-driver 12 of the communication lane L2 sets the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 of the communication lane L2 based on this setting data DT.

[0156] [Other Modifications] Two or more of these modifications may be combined.

[0157] 2. Second Embodiment Next, a communication system 2 according to a second embodiment will be described. In this embodiment, the driver 11 is used to adjust the output impedance of the driver 11. That is, in the first embodiment, the output impedance of the driver 11 is adjusted using a dummy driver 21, but instead, in this embodiment, the driver 11 itself is used to adjust the output impedance of the driver 11. Note that components that are substantially the same as those in the communication system 1 according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0158] 18 shows an example of the configuration of a communication system 2 according to this embodiment. The communication system 2 includes a transmission device 30. The transmission device 30 includes a switch circuit 31, a BIST circuit 13, and an impedance adjustment circuit 40.

[0159] FIG. 19 shows an example of the configuration of the switch circuit 31 and the impedance adjustment circuit 40. In addition to the switch circuit 31 and the impedance adjustment circuit 40, FIG. 19 also shows the driver 11, the pre-driver 12, and the BIST circuit 13. Also, in FIG. 19, the transmission device 30 is connected to an LSI tester 112. The LSI tester 112 has a switch SW22, a current source 113, a switch SW21, and a resistance element 114. In this example, the switch SW22 is a relay, and one end is connected to the output terminal OUTN of the transmission device 30 and the other end is connected to one end of the current source 113. One end of the current source 113 is connected to the other end of the switch SW22, and the other end is connected to the ground node. The current source 113 is configured to be able to sink a current from the driver 11 toward the ground node. In this example, the switch SW21 is a relay, and one end of the switch SW21 is connected to the output terminal OUTP of the transmitting device 30, and the other end is connected to one end of the resistive element 114. One end of the resistive element 114 is connected to the other end of the switch SW21, and the other end is connected to the output terminal OUTN of the transmitting device 30. The resistance value of the resistive element 114 is 100 [Ω].

[0160] The switch circuit 31 has switches SW11 to SW16. The switches SW11 to SW16 are configured to operate based on instructions from a control circuit 46 (described later) of the impedance adjustment circuit 40. One end of the switch SW11 is connected to the output terminal OUTP of the transmission device 30, and the other end is connected to a node N11. One end of the switch SW12 is connected to the output terminal OUTN of the transmission device 30, and the other end is connected to a node N12. One end of the switch SW13 is connected to the node N11, and the other end is connected to the node N12. The switch SW14 is configured to connect the node N11 to the node N13 or the BIST circuit 13. The switch SW15 is configured to connect the node N12 to the node N14 or the BIST circuit 13. The switch SW16 is configured to connect the node N13 or the node N14 to the negative input terminal of the comparator 25 in the impedance adjustment circuit 40.

[0161] The impedance adjustment circuit 40 includes a voltage generation circuit 24 , a comparator 25 , a control circuit 46 , and a nonvolatile memory 27 .

[0162] The control circuit 46 is configured to control the impedance adjustment operation in the impedance adjustment circuit 40 by controlling the operations of the voltage generation circuit 24, the pre-driver 12, and the switch circuit 31. The control circuit 46 transmits the results of this impedance adjustment operation to the LSI tester 112. Based on the results of the impedance adjustment operation, the LSI tester 112 generates setting data DT indicating whether each of the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 is enabled or disabled, and writes this setting data DT to the non-volatile memory 27 of the transmitting device 30. The control circuit 46 reads the setting data DT stored in the non-volatile memory 27, for example, when the transmitting device 30 is powered on, and supplies this setting data DT to the pre-driver 12.

[0163] Here, the driver 11 corresponds to a specific example of a "driver" in an embodiment of the present disclosure. The output terminal OUTP corresponds to a specific example of a "first output terminal" in an embodiment of the present disclosure. The output terminal OUTN corresponds to a specific example of a "second output terminal" in an embodiment of the present disclosure. The circuit UP corresponds to a specific example of a "first circuit" in an embodiment of the present disclosure. The circuit DP corresponds to a specific example of a "second circuit" in an embodiment of the present disclosure. The circuit UN corresponds to a specific example of a "third circuit" in an embodiment of the present disclosure. The circuit DN corresponds to a specific example of a "fourth circuit" in an embodiment of the present disclosure. The transistor MP1 corresponds to a specific example of a "first transistor" in an embodiment of the present disclosure. The transistor MN2 corresponds to a specific example of a "second transistor" in an embodiment of the present disclosure. The transistor MP3 corresponds to a specific example of a "third transistor" in an embodiment of the present disclosure. The transistor MN4 corresponds to a specific example of a "fourth transistor" in an embodiment of the present disclosure. The resistor element R1 corresponds to a specific example of a "first resistor element" in an embodiment of the present disclosure. The resistor element R2 corresponds to a specific example of a "second resistor element" in an embodiment of the present disclosure. The resistor element R3 corresponds to a specific example of a "third resistor element" in an embodiment of the present disclosure. The resistor element R4 corresponds to a specific example of a "fourth resistor element" in an embodiment of the present disclosure. The signal SUP corresponds to a specific example of a "first signal" in an embodiment of the present disclosure. The signal SDP corresponds to a specific example of a "second signal" in an embodiment of the present disclosure. The signal SUN corresponds to a specific example of a "third signal" in an embodiment of the present disclosure. The signal SDN corresponds to a specific example of a "fourth signal" in an embodiment of the present disclosure. The switch SW13 corresponds to a specific example of a "first switch" in an embodiment of the present disclosure. The control circuit 46 corresponds to a specific example of a "control circuit" in an embodiment of the present disclosure.

[0164] 20A and 20B show an example of the impedance adjusting operation, and Fig. 21A and 21B show an example of the operating state in the impedance adjusting operation.

[0165] First, as shown in FIG. 21A, the control circuit 46 turns on the transistor MP3 in the driver 11 and turns off the transistors MP1, MN2, and MN4 (step S201).

[0166] 21A, the LSI tester 112 turns off the switch SW21 and turns on the switch SW22 (step S202). As a result, a current I flows from the power supply node of the power supply voltage VRH through the transistor MP3, the resistor R3, the output terminal OUTN, the switch SW22, the current source 113, and the ground node in this order. The voltage of the output terminal OUTN becomes lower than the power supply voltage VRH by the amount of the voltage drop in the circuit UN.

[0167] Next, the control circuit 46 turns off the switch SW13 of the switch circuit 31 and enables the path from the output terminal OUTN to the comparator 25 (step S203). Specifically, as shown in FIG. 21A, the control circuit 46 turns on the switch SW12 and turns off the switches SW11 and SW13. The control circuit 46 also controls the operation of the switch SW14 to connect the node N11 to the node N13, the operation of the switch SW15 to connect the node N12 to the node N14, and the operation of the switch SW16 to connect the node N14 to the negative input terminal of the comparator 25. This enables the path PATH1 from the output terminal OUTN to the negative input terminal of the comparator 25.

[0168] Next, the control circuit 46 sequentially switches the setting of the circuit UN and determines the setting of the circuit UN based on the output signal of the comparator 25 (step S204). This operation is the same as step S103 (FIG. 8) in the first embodiment.

[0169] Next, as shown in FIG. 21B, the control circuit 46 turns on the transistors MN2 and MP3 in the driver 11 and turns off the transistors MP1 and MN4 (step S205).

[0170] Next, the LSI tester 112 turns off the switches SW21 and SW22 as shown in FIG. 21B (step S206).

[0171] Then, the control circuit 46 turns on the switches SW11 to SW13 of the switch circuit 31 and enables the paths from the output terminals OUTP and OUTN to the comparator 25 (step S207).

[0172] Specifically, the control circuit 46 turns on the switches SW11 to SW13, as shown in FIG. 21B. This connects the output terminals OUTP and OUTN to each other via the switches SW11 to SW13, causing a current I to flow from the power supply node of the power supply voltage VRH through the transistor MP3, the resistor R3, the switch SW12, the switch SW13, the switch SW11, the resistor R2, the transistor MN2, and the power supply node of the power supply voltage VRL in this order. The voltages at the output terminals OUTP and OUTN are voltages divided by the impedances of the circuits UN and DP.

[0173] Furthermore, the control circuit 46 controls the operation of the switch SW14 to connect the node N11 to the node N13, controls the operation of the switch SW15 to connect the node N12 to the node N14, and controls the operation of the switch SW16 to connect the node N13 to the negative input terminal of the comparator 25. As a result, the path PATH2 from the output terminals OUTP and OUTN to the negative input terminal of the comparator 25 becomes valid.

[0174] Next, the control circuit 46 sequentially switches the setting of the circuit DP and determines the setting of the circuit DP based on the output signal of the comparator 25 (step S208). This operation is the same as step S106 (FIG. 8) in the first embodiment.

[0175] Next, the control circuit 46 supplies the settings of the circuits UN and DP determined in steps S204 and S208 to the LSI tester 112 (step S209).

[0176] Based on the settings of the circuits UN and DP, the LSI tester 112 generates setting data DT for the driver 11 to be written to the nonvolatile memory 27. For example, the LSI tester 112 can set the setting of the circuit UP in the driver 11 to the same setting as the setting of the circuit UN, and the setting of the circuit DN in the driver 11 to the same setting as the setting of the circuit DP. In this way, the LSI tester 112 generates the setting data DT. Then, the LSI tester 112 performs a write operation to write this setting data DT to the nonvolatile memory 27 of the transmitting device 30.

[0177] The nonvolatile memory 27 stores the setting data DT supplied from the LSI tester 112 based on the write operation of the LSI tester 112 (step S210).

[0178] This completes the process.

[0179] Thereafter, each time the power of the transmitter 30 is turned on, the control circuit 46 of the transmitter 30 reads the setting data DT stored in the nonvolatile memory 27 and supplies this setting data DT to the pre-driver 12. The pre-driver 12 sets the circuits UP, DP, UN, and DN in the driver 11 based on this setting data DT. As a result, each of the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 is set to be enabled or disabled based on the setting data DT. In this way, the output impedance of the driver 11 is adjusted in the transmitter 30.

[0180] For example, in a state where the transmitting device 30 is connected to the receiving device 100, the BIST circuit 13 can check whether the output impedance of the driver 11 is set appropriately.

[0181] 22A and 22B show an example of an operation for checking whether the output impedance of the driver 11 is set appropriately. Note that the receiving device 100 is not shown in FIGS. 22A and 22B. The control circuit 46 turns on the switches SW11 and SW12 of the switch circuit 31 and turns off the switch SW13. The control circuit 46 also controls the operation of the switch SW14 to connect the node N11 to the BIST circuit 13, and controls the operation of the switch SW15 to connect the node N12 to the BIST circuit 13. This enables the path PATH3 from the output terminal OUTP to the BIST circuit 13 and the path PATH4 from the output terminal OUTN to the BIST circuit 13.

[0182] 22A, the control circuit 46 turns on the transistors MP1 and MN4 of the driver 11 and turns off the transistors MN2 and MP3. If the output impedance of the driver 11 is set appropriately, the voltage of the output terminal OUTP is desirably "3 / 4×(VRH−VRL)+VRL" and the voltage of the output terminal OUTN is desirably "1 / 4×(VRH−VRL)+VRL". The BIST circuit 13 can confirm that the circuits UP and DN are set appropriately based on the voltages of the output terminals OUTP and OUTN.

[0183] 22B, the control circuit 46 turns on the transistors MN2 and MP3 of the driver 11 and turns off the transistors MP1 and MN4. If the output impedance of the driver 11 is set appropriately, the voltage of the output terminal OUTP is desirably "1 / 4×(VRH−VRL)+VRL", and the voltage of the output terminal OUTN is desirably "3 / 4×(VRH−VRL)+VRL". The BIST circuit 13 can confirm that the circuits UN and DP are set appropriately based on the voltages of the output terminals OUTP and OUTN.

[0184] In this example, the BIST circuit 13 checks whether the output impedance of the driver 11 is set appropriately when the transmitting device 30 is connected to the receiving device 100, but the present invention is not limited to this. For example, when the transmitting device 30 is connected to the LSI tester 112, the impedance adjustment circuit 40 may adjust the output impedance, and then the BIST circuit 13 may check whether the output impedance of the driver 11 is set appropriately. In this case, for example, the LSI tester 112 turns on the switch SW21.

[0185] 23 shows an example of the operation of the transmitter 30 when the communication system 2 is performing a communication operation. When the communication system 2 is performing a communication operation, the control circuit 46 turns off the switches SW11 and SW12 in the switch circuit 31. This disconnects the output terminals OUTP and OUTN from the BIST circuit 13 and the comparator 25. In FIG. 23, in the driver 11, the transistors MP1 and MN4 are on, and the transistors MN2 and MP3 are off. Therefore, as in the case of FIG. 3A, a current I flows from the power supply node of the power supply voltage VRH through the transistor MP1, the resistor R1, the output terminal OUTP, the transmission line 90P, the resistor 91, the transmission line 90N, the output terminal OUTN, the resistor R4, the transistor MN4, and the power supply node of the power supply voltage VRL in this order. Also, for example, when the transistors MN2 and MP3 of the driver 11 are in an ON state and the transistors MP1 and MN4 are in an OFF state, as in the case of Figure 3B, a current I flows from the power supply node of the power supply voltage VRH through the transistor MP3, the resistor element R3, the output terminal OUTN, the transmission line 90N, the resistor element 91, the transmission line 90P, the output terminal OUTP, the resistor element R2, the transistor MN2, and the power supply node of the power supply voltage VRL in this order.

[0186] As described above, the transmitting device 30 is provided with the driver 11, the first switch (switch SW13), and the control circuit 46. The driver 11 is provided on a path connecting the first output terminal (output terminal OUTP) and the first power supply node (power supply node of the power supply voltage VRH) and includes a first circuit (circuit UP) that is provided on a path connecting the first output terminal (output terminal OUTP) and the second power supply node (power supply node of the power supply voltage VRL) and includes a first transistor (transistor MP1) and a first resistor element (resistor element R1) that can be turned on and off based on a first signal (signal SUP), a second circuit (circuit DP) that is provided on a path connecting the first output terminal (output terminal OUTP) and the second power supply node (power supply node of the power supply voltage VRL) and includes a second transistor (transistor MN2) and a second resistor element (resistor element R2) that can be turned on and off based on a second signal (signal SDP), and a second circuit (circuit DP) that is provided on a path connecting the second output terminal (output terminal OUTN) and the first power supply node (power supply voltage VRL). The power supply node for the power supply voltage VRL includes a third circuit (circuit UN) that is provided in a path connecting the first output terminal (output terminal OUTN) and the second power supply node (power supply node for the power supply voltage VRL) and includes a third transistor (transistor MP3) and a third resistor element (resistor element R3) that can be turned on and off based on a third signal (signal SUN), and a fourth circuit (circuit DN) that is provided in a path connecting the second output terminal (output terminal OUTN) and the second power supply node (power supply node for the power supply voltage VRL) and includes a fourth transistor (transistor MN4) and a fourth resistor element (resistor element R4) that can be turned on and off based on a fourth signal (signal SDN), and the impedance of the first circuit, the second circuit, the third circuit, and the fourth circuit can be changed. A first switch (switch SW13) is provided in the path connecting the first output terminal (output terminal OUTP) and the second output terminal (output terminal OUTN). The control circuit 46 can set the impedance of the first circuit, the impedance of the second circuit, the impedance of the third circuit, and the impedance of the fourth circuit, and can control the operation of the first switch (switch SW13). The control circuit 46 can perform a first operation.The first operation includes turning on the first switch (switch SW13), turning on the second transistor (transistor MN2) and the third transistor (transistor MP3) while turning off the first transistor (transistor MP1) and the fourth transistor (transistor MN4), sequentially changing the impedance of the second circuit, and setting the impedance of the second circuit and the impedance of the fourth circuit based on first setting data that is set based on the voltage of the second output terminal (output terminal OUTN) when the impedance of the second circuit is sequentially changed. As a result, in the first operation, as shown in FIG. 21B , a current I flows from the power supply node of the power supply voltage VRH through the transistor MP3, the resistor R3, the switch SW12, the switch SW13, the switch SW11, the resistor R2, the transistor MN2, and the power supply node of the power supply voltage VRL in this order. This allows the output impedance of the driver 11 to be adjusted by setting the circuit DP so that the voltage at the output terminal OUTN becomes the midpoint voltage between the power supply voltages VRH and VRL, thereby enabling the output impedance of the transmitter 30 to be adjusted effectively.

[0187] 21A, if the circuit UN is set using the current source 113 that sinks current in the LSI tester 112, and then the circuit DP is set using the current source that pours current in the LSI tester 112, then such a current source that sinks current and a current source that pours current will be required. In particular, in the LSI tester, it may take time for the current and voltage to stabilize when turning on and off a relay, so if a current source that sinks current and a current source that pours current are used, it may take even longer because two relays are turned on and off.

[0188] On the other hand, in the transmitter 30, the circuit DP is set so that the voltage at the output terminal OUTN is the midpoint voltage between the power supply voltage VRH and the power supply voltage VRL. This allows the circuit DP to be set without using a current source that sinks current in an LSI tester. As a result, the transmitter 30 uses only a current source that sinks current, which shortens the total time required for turning the relay on and off compared to when two relays are used. As a result, the transmitter 30 can effectively adjust the output impedance.

[0189] Furthermore, unlike the first embodiment, the transmitter 30 can adjust the output impedance of the driver 11 without using the dummy driver 21. That is, since the dummy driver 21 is not required, the circuit size can be reduced. Therefore, the transmitter 30 can effectively adjust the output impedance using a circuit with a small circuit size.

[0190] Furthermore, in the transmitter 30, the control circuit 46 is capable of performing a second operation before the first operation. This second operation includes turning off the first switch (switch SW13), turning on the third transistor (transistor MP3) and turning off the fourth transistor (transistor MN4), sequentially changing the impedance of the third circuit while sinking current from the second output terminal (output terminal OUTN), and setting the impedance of the first circuit and the impedance of the third circuit based on second setting data that is set based on the voltage of the second output terminal (output terminal OUTN) when the impedance of the third circuit is sequentially changed. As a result, in the second operation, as shown in FIG. 21A , a current I flows from the power supply node of the power supply voltage VRH through the transistor MP3, the resistor element R3, the switch SW22, and the current source 113 in this order. In the transmitter 30, the output impedance of the driver 11 can be adjusted by setting the circuit UN so that the voltage of the output terminal OUTN becomes "3 / 4 × (VRH - VRL) + VRL." As a result, the transmitter 30 can effectively adjust the output impedance.

[0191] [Effect] As described above, this embodiment provides a driver, a first switch, and a control circuit. The driver includes a first circuit provided in a path connecting the first output terminal and the first power supply node and including a first transistor and a first resistor element that can be turned on and off based on a first signal, a second circuit provided in a path connecting the first output terminal and the second power supply node and including a second transistor and a second resistor element that can be turned on and off based on a second signal, a third circuit provided in a path connecting the second output terminal and the first power supply node and including a third transistor and a third resistor element that can be turned on and off based on a third signal, and a fourth circuit provided in a path connecting the second output terminal and the second power supply node and including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, and the driver is capable of changing the impedance of the first circuit, the impedance of the second circuit, the impedance of the third circuit, and the impedance of the fourth circuit. The first switch is provided in the path connecting the first output terminal and the second output terminal. The control circuit is capable of setting the impedance of the first circuit, the impedance of the second circuit, the impedance of the third circuit, and the impedance of the fourth circuit, and is capable of controlling the operation of the first switch. The control circuit is capable of performing a first operation. The first operation includes turning on the first switch, turning on the second transistor and the third transistor, turning off the first transistor and the fourth transistor, sequentially changing the impedance of the second circuit, and setting the impedance of the second circuit and the impedance of the fourth circuit based on first setting data that is set based on the voltage of the second output terminal when the impedance of the second circuit is sequentially changed. As a result, the output impedance can be effectively adjusted.

[0192] In this embodiment, the control circuit is capable of performing a second operation before the first operation. The second operation includes turning off the first switch, turning on the third transistor and turning off the fourth transistor, sequentially changing the impedance of the third circuit while sinking current from the second output terminal, and setting the impedance of the first circuit and the impedance of the third circuit based on second setting data that is set based on the voltage of the second output terminal when the impedance of the third circuit is sequentially changed. As a result, the output impedance can be effectively adjusted.

[0193] [Variant 2-1] In the above embodiment, a driver 11 having the circuit configuration shown in FIG. 2 is used, but this is not limited to this. Instead, for example, a driver 11C1 shown in FIG. 11 or a driver 11C2 shown in FIG. 12 may be used, as in variant 1-1 of the first embodiment.

[0194] [Modification 2-2] In the above embodiment, the LSI tester 112 generates the setting data DT for the driver 11 based on the settings of the circuits UN and DP, but this is not limiting. As in Modification 1-2 of the first embodiment, for example, in addition to the LSI tester 112, the control circuit 46 may also generate the setting data DT for the driver 11 based on the settings of the circuits UN and DP.

[0195] 18, the impedance adjustment circuit 40 and the BIST circuit 13 are provided separately, but this is not limiting, and instead, for example, the impedance adjustment circuit 40 may have the function of the BIST circuit 13. This modification will be described in detail below.

[0196] 24 shows an example of the configuration of a communication system 2A according to this modification. The communication system 2A includes a transmitting device 30A. The transmitting device 30A includes an impedance adjustment circuit 40A.

[0197] 25 shows an example of the configuration of the impedance adjustment circuit 40 A. The impedance adjustment circuit 40 A includes a switch circuit 49 A and a control circuit 46 A.

[0198] The switch circuit 49A has switches SW11 to SW13, and SW16. The switches SW11 to SW13, and SW16 are configured to operate based on instructions from a control circuit 46A (described later). One end of the switch SW11 is connected to the output terminal OUTP of the transmitting device 30A, and the other end is connected to a node N11. One end of the switch SW12 is connected to the output terminal OUTN of the transmitting device 30A, and the other end is connected to a node N12. One end of the switch SW13 is connected to the node N11, and the other end is connected to the node N12. The switch SW16 is configured to connect the node N11 or the node N12 to the negative input terminal of the comparator 25 in the impedance adjustment circuit 40A.

[0199] Similar to the control circuit 46 according to the above embodiment, the control circuit 46A is configured to control the impedance adjustment operation in the impedance adjustment circuit 40A by controlling the operations of the voltage generation circuit 24, the switch circuit 49A, and the pre-driver 12. Furthermore, after the output impedance of the driver 11 has been adjusted, the control circuit 46A is able to check whether the output impedance of the driver 11 has been appropriately set based on the voltages of the output terminals OUTP and OUTN.

[0200] When performing impedance adjustment operation, the control circuit 46A first turns off the switches SW11 and SW13 of the switch circuit 49A and turns on the switch SW12, as shown in FIG. 26A. The remaining steps are the same as those in the above embodiment (FIG. 21A). The control circuit 46A then sequentially switches the setting of the circuit UN and determines the setting of the circuit UN based on the output signal of the comparator 25.

[0201] Next, as shown in FIG. 26B, the control circuit 46A turns on the switches SW11 to SW13 of the switch circuit 49A. The rest of the process is the same as in the above embodiment (FIG. 21B). The control circuit 46A then sequentially switches the setting of the circuit DP and determines the setting of the circuit DP based on the output signal of the comparator 25.

[0202] Then, the LSI tester 112 generates setting data DT for the driver 11 to be written to the nonvolatile memory 27 based on the settings of the circuits UN and DP, and writes this setting data DT to the nonvolatile memory 27 of the transmitting device 30A.

[0203] For example, when the transmitting device 30A is connected to the receiving device 100, the impedance adjustment circuit 40A can check whether the output impedance of the driver 11 is set appropriately. First, the control circuit 46A turns on the switches SW11 and SW12 of the switch circuit 49A and turns off the switch SW13.

[0204] 3A, the control circuit 46A turns on the transistors MP1 and MN4 of the driver 11 and turns off the transistors MN2 and MP3. If the output impedance of the driver 11 is set appropriately, the voltage of the output terminal OUTP is desirably 3 / 4×(VRH−VRL)+VRL, and the voltage of the output terminal OUTN is desirably 1 / 4×(VRH−VRL)+VRL.

[0205] Next, the control circuit 46A controls the operation of the switch SW16 to connect the node N11 to the comparator 25. As a result, the voltage at the output terminal OUTP is supplied to the negative input terminal of the comparator 25. The control circuit 46A then sets the ratio of the resistance values ​​of the variable resistor element RH and the variable resistor element RL in the voltage generating circuit 24 to 1:3. As a result, the reference voltage VREF becomes "3 / 4 × (VRH - VRL) + VRL." The control circuit 46A then slightly changes the impedance of the circuit UP associated with the transistor MP1, for example, and checks whether the output signal of the comparator 25 changes.

[0206] Next, the control circuit 46A controls the operation of the switch SW16 to connect the node N12 to the comparator 25. As a result, the voltage at the output terminal OUTN is supplied to the negative input terminal of the comparator 25. The control circuit 46A then sets the ratio of the resistance value of the variable resistance element RH to the resistance value of the variable resistance element RL in the voltage generating circuit 24 to 3:1. As a result, the reference voltage VREF becomes "1 / 4 × (VRH - VRL) + VRL". The control circuit 46A then slightly changes the impedance of the circuit DN associated with the transistor MN4, for example, and checks whether the output signal of the comparator 25 changes.

[0207] If the output signal of the comparator 25 changes when the impedance of the circuit UP is slightly changed, and if the output signal of the comparator 25 changes when the impedance of the circuit DN is slightly changed, the control circuit 46A determines that the impedances of the circuits UP and DN are set appropriately.

[0208] 3B, the control circuit 46A turns on the transistors MN2 and MP3 of the driver 11 and turns off the transistors MP1 and MN4. If the output impedance of the driver 11 is set appropriately, the voltage at the output terminal OUTP is desirably 1 / 4×(VRH−VRL)+VRL, and the voltage at the output terminal OUTN is desirably 3 / 4×(VRH−VRL)+VRL.

[0209] Next, the control circuit 46A controls the operation of the switch SW16 to connect the node N11 to the comparator 25. As a result, the voltage at the output terminal OUTP is supplied to the negative input terminal of the comparator 25. The control circuit 46A then sets the ratio of the resistance values ​​of the variable resistor element RH and the variable resistor element RL in the voltage generating circuit 24 to 3:1. As a result, the reference voltage VREF becomes "1 / 4 × (VRH - VRL) + VRL." The control circuit 46A then slightly changes the impedance of the circuit UN associated with the transistor MP3, for example, and checks whether the output signal of the comparator 25 changes.

[0210] Next, the control circuit 26A controls the operation of the switch SW16 to connect the node N12 to the comparator 25. As a result, the voltage at the output terminal OUTN is supplied to the negative input terminal of the comparator 25. The control circuit 46A then sets the ratio of the resistance values ​​of the variable resistance element RH and the variable resistance element RL in the voltage generation circuit 24 to 1:3. As a result, the reference voltage VREF becomes "3 / 4 × (VRH - VRL) + VRL". The control circuit 46A then slightly changes the impedance of the circuit DP associated with the transistor MN2, for example, and checks whether the output signal of the comparator 25 changes.

[0211] If the output signal of the comparator 25 changes when the impedance of the circuit UN is slightly changed, and if the output signal of the comparator 25 changes when the impedance of the circuit DP is slightly changed, the control circuit 46A determines that the impedances of the circuits UN and DP are set appropriately.

[0212] In this way, the impedance adjustment circuit 40A checks whether the impedances of the circuits UP, DP, UN, and DN are set appropriately, thereby checking whether the output impedance of the driver 11 is set appropriately.

[0213] Thereafter, the control circuit 46A turns off the switches SW11 and SW12, and the communication system 2A performs communication operations.

[0214] [Variation 2-4] In the above embodiment, one communication lane is provided as shown in FIG. 18 . However, this is not limiting. Instead, multiple communication lanes (two communication lanes L1 and L2 in this example) may be provided, as in the communication system 2B shown in FIG. 27 . The communication system 2B includes a transmitting device 30B and a receiving device 100B. In this example, an impedance adjustment circuit 40 is provided in the communication lane L1. This impedance adjustment circuit 40 performs impedance adjustment operations, similar to the above embodiment. The impedance adjustment circuit 40 then supplies setting data DT to the pre-driver 12 in the communication lane L1 and to the pre-driver 12 in the communication lane L2. The pre-driver 12 in the communication lane L1 configures the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 of the communication lane L1 based on this setting data DT. The pre-driver 12 of the communication lane L2 sets the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 of the communication lane L2 based on this setting data DT.

[0215] [Other Modifications] Two or more of these modifications may be combined.

[0216] 3. Reference Example Next, a communication system 3 according to a reference example will be described. In this embodiment, a current source that sources a current and a current source that sinks a current are used to adjust the output impedance of the driver 11. Note that components that are substantially the same as those in the communication system 1 according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0217] 28 shows an example of the configuration of a communication system 3 according to a reference example. The communication system 3 includes a transmission device 50. The transmission device 50 includes a switch circuit 51, a BIST circuit 13, and an impedance adjustment circuit 60.

[0218] FIG. 29 shows an example of the configuration of the switch circuit 51 and the impedance adjustment circuit 60. In addition to the switch circuit 51 and the impedance adjustment circuit 60, FIG. 29 also shows the driver 11, the pre-driver 12, and the BIST circuit 13. Also, in FIG. 29, the transmission device 50 is connected to an LSI tester 122. The LSI tester 122 has a switch SW22, a current source 113, a current source 115, a switch SW23, a switch SW21, and a resistor 114. In this example, the switch SW22 is a relay, and one end is connected to the output terminal OUTN of the transmission device 50 and the other end is connected to one end of the current source 113. One end of the current source 113 is connected to the other end of the switch SW22, and the other end is connected to the ground node. The current source 113 is configured to be able to sink a current from the driver 11 toward the ground node. One end of the current source 115 is connected to the power supply node of the power supply voltage VRH2, and the other end is connected to one end of the switch SW23. The current source 113 is configured to be able to flow current from the power supply node of the power supply voltage VRH2 toward the driver 11. The switch SW23 is a relay in this example, and one end is connected to the other end of the current source 115, and the other end is connected to the output terminal OUTP of the transmitter 50. The switch SW21 is a relay in this example, and one end is connected to the output terminal OUTP of the transmitter 50, and the other end is connected to one end of the resistor element 114. One end of the resistor element 114 is connected to the other end of the switch SW21, and the other end is connected to the output terminal OUTN of the transmitter 50. The resistance value of the resistor element 114 is 100 [Ω].

[0219] The switch circuit 51 has switches SW11, SW12, and SW14 to SW16. The switches SW11, SW12, and SW14 to SW16 are configured to operate based on instructions from a control circuit 66 (described later) of the impedance adjustment circuit 60. One end of the switch SW11 is connected to an output terminal OUTP of the transmission device 50, and the other end is connected to a node N11. One end of the switch SW12 is connected to an output terminal OUTN of the transmission device 50, and the other end is connected to a node N12. The switch SW14 is configured to connect the node N11 to a node N13 or the BIST circuit 13. The switch SW15 is configured to connect the node N12 to a node N14 or the BIST circuit 13. The switch SW16 is configured to connect the node N13 or the node N14 to the negative input terminal of the comparator 25 in the impedance adjustment circuit 60.

[0220] The impedance adjustment circuit 60 includes a voltage generation circuit 24 , a comparator 25 , a control circuit 66 , and a nonvolatile memory 27 .

[0221] The control circuit 66 is configured to control the impedance adjustment operation in the impedance adjustment circuit 60 by controlling the operations of the voltage generation circuit 24, the pre-driver 12, and the switch circuit 51. The control circuit 66 transmits the results of this impedance adjustment operation to the LSI tester 122. The LSI tester 122 generates setting data DT indicating whether each of the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 is enabled or disabled based on the results of the impedance adjustment operation, and writes this setting data DT to the non-volatile memory 27 of the transmitting device 50. The control circuit 66 reads the setting data DT stored in the non-volatile memory 27, for example, when the transmitting device 50 is powered on, and supplies this setting data DT to the pre-driver 12.

[0222] Fig. 30 shows an example of the impedance adjusting operation, and Figs. 31A and 31B show an example of the operating state in the impedance adjusting operation.

[0223] First, as shown in FIG. 31A, the control circuit 66 turns on the transistors MN2 and MP3 in the driver 11 and turns off the transistors MP1 and MN4 (step S301).

[0224] 31A , the LSI tester 122 turns off the switch SW21 and turns on the switches SW22 and SW23 (step S302). As a result, a current I1 flows from the power supply node of the power supply voltage VRH through the transistor MP3, the resistor R3, the output terminal OUTN, the switch SW22, the current source 113, and the ground node, in that order, and a current I2 flows from the power supply node of the power supply voltage VRH2 through the current source 115, the switch SW23, the output terminal OUTP, the resistor R2, the transistor MN2, and the power supply node of the power supply voltage VRL, in that order. As a result, the voltage of the output terminal OUTN becomes lower than the power supply voltage VRH by the amount of the voltage drop in the circuit UN, and the voltage of the output terminal OUTP becomes higher than the power supply voltage VRL by the amount of the voltage drop in the circuit DP.

[0225] Next, the control circuit 66 enables the path from the output terminal OUTN to the comparator 25 (step S303). Specifically, as shown in FIG. 31A , the control circuit 66 turns on the switches SW11 and SW12, controls the operation of the switch SW14 to connect the node N11 to the node N13, controls the operation of the switch SW15 to connect the node N12 to the node N14, and controls the operation of the switch SW16 to connect the node N14 to the negative input terminal of the comparator 25. This enables the path PATH1 from the output terminal OUTN to the negative input terminal of the comparator 25.

[0226] Next, the control circuit 66 sequentially switches the setting of the circuit UN and determines the setting of the circuit UN based on the output signal of the comparator 25 (step S304). In step S304, the voltage generating circuit 24 first sets the ratio of the resistance value of the variable resistance element RH to the resistance value of the variable resistance element RL to 1:3 based on an instruction from the control circuit 66, thereby setting the reference voltage VREF to "3 / 4×(VRH−VRL)+VRL." Then, the control circuit 66 sequentially switches the setting of the circuit UN to determine the setting of the circuit UN, similar to step S103 in the first embodiment.

[0227] Next, the control circuit 66 enables the path from the output terminal OUTP to the comparator 25 (step S305). Specifically, as shown in FIG. 31B, the control circuit 66 controls the operation of the switch SW16 to connect the node N13 to the negative input terminal of the comparator 25. This enables the path PATH3 from the output terminal OUTP to the negative input terminal of the comparator 25.

[0228] Next, the control circuit 66 sequentially switches the setting of the circuit DP and determines the setting of the circuit DP based on the output signal of the comparator 25 (step S306). In step S306, the voltage generating circuit 24 first sets the ratio of the resistance value of the variable resistance element RH to the resistance value of the variable resistance element RL to 3:1 based on an instruction from the control circuit 66, thereby setting the reference voltage VREF to "1 / 4×(VRH−VRL)+VRL." Then, the control circuit 66 sequentially switches the setting of the circuit DP to determine the setting of the circuit DP, similar to step S106 in the first embodiment.

[0229] Next, the control circuit 66 supplies the settings of the circuits UN and DP determined in steps S304 and S306 to the LSI tester 122 (step S307).

[0230] Based on the settings of the circuits UN and DP, the LSI tester 122 generates setting data DT for the driver 11 to be written to the nonvolatile memory 27. For example, the LSI tester 122 can set the setting of the circuit UP in the driver 11 to the same setting as the circuit UN, and the setting of the circuit DN in the driver 11 to the same setting as the circuit DP. In this way, the LSI tester 122 generates the setting data DT. Then, the LSI tester 122 performs a write operation to write this setting data DT to the nonvolatile memory 27 of the transmitting device 50.

[0231] The nonvolatile memory 27 stores the setting data DT supplied from the LSI tester 122 based on the write operation of the LSI tester 122 (step S308).

[0232] This completes the process.

[0233] Thereafter, each time the power of the transmitter 50 is turned on, the control circuit 66 of the transmitter 50 reads the setting data DT stored in the nonvolatile memory 27 and supplies this setting data DT to the pre-driver 12. The pre-driver 12 sets the circuits UP, DP, UN, and DN in the driver 11 based on this setting data DT. As a result, each of the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 is set to be enabled or disabled based on the setting data DT. In this way, the output impedance of the driver 11 is adjusted in the transmitter 50.

[0234] For example, in a state where the transmitting device 50 is connected to the receiving device 100, the BIST circuit 13 can check whether the output impedance of the driver 11 is set appropriately.

[0235] 32A and 32B show an example of an operation for checking whether the output impedance of the driver 11 is set appropriately. Note that the receiving device 100 is not shown in FIGS. 31A and 31B. The control circuit 66 turns on the switches SW11 and SW12 of the switch circuit 51. The control circuit 66 also controls the operation of the switch SW14 to connect the node N11 to the BIST circuit 13, and controls the operation of the switch SW15 to connect the node N12 to the BIST circuit 13. This enables the path PATH3 from the output terminal OUTP to the BIST circuit 13 and the path PATH4 from the output terminal OUTN to the BIST circuit 13.

[0236] 32A, the control circuit 66 turns on the transistors MP1 and MN4 of the driver 11 and turns off the transistors MN2 and MP3. If the output impedance of the driver 11 is set appropriately, the voltage of the output terminal OUTP is desirably "3 / 4×(VRH−VRL)+VRL", and the voltage of the output terminal OUTN is desirably "1 / 4×(VRH−VRL)+VRL". The BIST circuit 13 can confirm that the circuits UP and DN are set appropriately based on the voltages of the output terminals OUTP and OUTN.

[0237] 32B, the control circuit 66 turns on the transistors MN2 and MP3 of the driver 11 and turns off the transistors MP1 and MN4. If the output impedance of the driver 11 is set appropriately, the voltage of the output terminal OUTP is desirably "1 / 4×(VRH−VRL)+VRL", and the voltage of the output terminal OUTN is desirably "3 / 4×(VRH−VRL)+VRL". The BIST circuit 13 can confirm that the circuits UN and DP are set appropriately based on the voltages of the output terminals OUTP and OUTN.

[0238] In this example, the BIST circuit 13 checks whether the output impedance of the driver 11 is set appropriately when the transmitting device 50 is connected to the receiving device 100, but the present invention is not limited to this. For example, when the transmitting device 50 is connected to the LSI tester 122, the impedance adjustment circuit 60 may adjust the output impedance, and then the BIST circuit 13 may check whether the output impedance of the driver 11 is set appropriately. In this case, for example, the LSI tester 122 turns on the switch SW21.

[0239] 33 shows an example of the operation of the transmitter 50 when the communication system 3 is performing a communication operation. When the communication system 3 is performing a communication operation, the control circuit 66 turns off the switches SW11 and SW12 in the switch circuit 51. This disconnects the output terminals OUTP and OUTN from the BIST circuit 13 and the comparator 25. In FIG. 33, in the driver 11, the transistors MP1 and MN4 are on, and the transistors MN2 and MP3 are off. Therefore, as in the case of FIG. 3A, a current I flows from the power supply node of the power supply voltage VRH through the transistor MP1, the resistor R1, the output terminal OUTP, the transmission line 90P, the resistor 91, the transmission line 90N, the output terminal OUTN, the resistor R4, the transistor MN4, and the power supply node of the power supply voltage VRL in this order. Also, for example, when the transistors MN2 and MP3 of the driver 11 are in an ON state and the transistors MP1 and MN4 are in an OFF state, as in the case of Figure 3B, a current I flows from the power supply node of the power supply voltage VRH through the transistor MP3, the resistor element R3, the output terminal OUTN, the transmission line 90N, the resistor element 91, the transmission line 90P, the output terminal OUTP, the resistor element R2, the transistor MN2, and the power supply node of the power supply voltage VRL in this order.

[0240] In this reference example, a first circuit (circuit UP) is provided in a path connecting a first output terminal (output terminal OUTP) and a first power supply node (power supply node of a power supply voltage VRH) and includes a first transistor (transistor MP1) and a first resistor element (resistance element R1) that can be turned on and off based on a first signal (signal SUP); and a second circuit (circuit UP) is provided in a path connecting the first output terminal (output terminal OUTP) and a second power supply node (power supply node of a power supply voltage VRL) and includes a second transistor (transistor MN2) and a second resistor element (resistance element R1) that can be turned on and off based on a second signal (signal SDP). a third circuit (circuit UN) including a third transistor (transistor MP3) and a third resistor element (resistor element R3) that are provided in a path connecting the second output terminal (output terminal OUTN) and the first power supply node (power supply node for the power supply voltage VRH) and that can be turned on and off based on a third signal (signal SUN); and a fourth transistor (transistor MP3) and a third resistor element (resistor element R3) that are provided in a path connecting the second output terminal (output terminal OUTN) and the second power supply node (power supply node for the power supply voltage VRL) and that can be turned on and off based on a fourth signal (signal SDN). In a driver (driver 11) having a fourth circuit (circuit DN) including a second transistor (transistor MN2) and a third transistor (transistor MP3) in an ON state and a first transistor (transistor MP1) and a fourth transistor (transistor MN4) in an OFF state, a current is supplied to a first output terminal (output terminal OUTP) of the driver (driver 11) via a first relay (switch SW23), and a current is supplied to a second output terminal (output terminal OUTP) of the driver (driver 11) via a first relay (switch SW23). sinking a current from a second output terminal (output terminal OUTN) of the second relay (switch SW11) via a second relay (switch SW22); sequentially changing the impedance of the second circuit (circuit DP); setting the impedance of the second circuit (circuit DP) and the impedance of the fourth circuit (circuit DN) based on first setting data that is set based on the voltage of the first output terminal (output terminal OUTP) when the impedance of the second circuit (circuit DP) is sequentially changed; and sequentially changing the impedance of the third circuit (circuit UN).and setting the impedance of the first circuit (circuit UP) and the impedance of the third circuit (circuit UN) based on second setting data that is set based on the voltage of the second output terminal (output terminal OUTN) when the impedance of the third circuit (circuit UN) is sequentially changed. This allows, for example, the switches SW22 and SW23 to be turned on and off together, thereby shortening the total time required for turning on and off the relays and effectively adjusting the output impedance.

[0241] That is, for example, by turning on transistor MP3 of driver 11 and turning on a relay provided in LSI tester 122 to sink current from output terminal OUTN, the impedance of circuit UN is adjusted and the relay is turned off. Then, by turning on transistor MN4 of driver 11 and turning on another relay provided at output terminal OUTN, current is flowed into output terminal OUTN to adjust the impedance of circuit DN and turn the relay off. In this case, two relays must be turned on and off separately. Generally, relays take time to turn on and off, so turning the relays on and off individually lengthens the total time required for the relays to be turned on and off. In contrast, in this embodiment, the two switches SW22 and SW23 can be turned on and off together, thereby shortening the total time required for the relays to be turned on and off. As a result, the transmitter according to this embodiment can effectively adjust the output impedance.

[0242] [Variant 3-1] In the above reference example, a driver 11 having the circuit configuration shown in Figure 2 was used, but this is not limited to this. Instead, for example, driver 11C1 shown in Figure 11 or driver 11C2 shown in Figure 12 may be used, as in variant 1-1 of the first embodiment above.

[0243] [Modification 3-2] In the above reference example, the LSI tester 122 generates the setting data DT for the driver 11 based on the settings of the circuits UN and DP, but this is not limiting. As in Modification 1-2 of the first embodiment, for example, in addition to the LSI tester 122, the control circuit 66 may also be configured to generate the setting data DT for the driver 11 based on the settings of the circuits UN and DP.

[0244] 28, the impedance adjustment circuit 60 and the BIST circuit 13 are provided separately, but this is not limiting, and instead, for example, the impedance adjustment circuit 60 may have the function of the BIST circuit 13. This modification will be described in detail below.

[0245] 34 shows an example of the configuration of a communication system 3A according to this modification. The communication system 3A includes a transmitting device 50A. The transmitting device 50A includes an impedance adjustment circuit 60A.

[0246] 35 shows an example of the configuration of the impedance adjustment circuit 60 A. The impedance adjustment circuit 60 A includes a switch circuit 69 A and a control circuit 66 A.

[0247] The switch circuit 69A has switches SW11, SW12, and SW16. The switches SW11, SW12, and SW16 are configured to operate based on instructions from a control circuit 66A (described below). One end of the switch SW11 is connected to the output terminal OUTP of the transmitter 30A, and the other end is connected to a node N11. One end of the switch SW12 is connected to the output terminal OUTN of the transmitter 30A, and the other end is connected to a node N12. The switch SW16 is configured to connect the node N11 or the node N12 to the negative input terminal of the comparator 25 in the impedance adjustment circuit 60A.

[0248] Similar to the control circuit 66 according to the above embodiment, the control circuit 66A is configured to control the impedance adjustment operation in the impedance adjustment circuit 60A by controlling the operations of the voltage generation circuit 24, the switch circuit 69A, and the pre-driver 12. Furthermore, after the output impedance of the driver 11 has been adjusted, the control circuit 66A is able to check whether the output impedance of the driver 11 has been appropriately set based on the voltages of the output terminals OUTP and OUTN.

[0249] When performing impedance adjustment operation, first, as shown in FIG. 36A, the control circuit 66A turns on switches SW11 and SW12 of the switch circuit 69A and controls the operation of switch SW16 so as to connect node N12 to the negative input terminal of the comparator 25. The rest is the same as in the above embodiment ( FIG. 31A ). Then, the control circuit 66A sequentially switches the setting of the circuit UN and determines the setting of the circuit UN based on the output signal of the comparator 25.

[0250] Next, as shown in FIG. 36B, the control circuit 46A turns on switches SW11 and SW12 of the switch circuit 69A and controls the operation of switch SW16 to connect node N11 to the negative input terminal of the comparator 25. The rest is the same as in the above embodiment ( FIG. 31B ). Then, the control circuit 66A sequentially switches the setting of the circuit DP and determines the setting of the circuit DP based on the output signal of the comparator 25.

[0251] Then, the LSI tester 122 generates setting data DT for the driver 11 to be written to the nonvolatile memory 27 based on the settings of the circuits UN and DP, and writes this setting data DT to the nonvolatile memory 27 of the transmitting device 50A.

[0252] For example, when the transmitting device 50A is connected to the receiving device 100, the impedance adjustment circuit 60A can check whether the output impedance of the driver 11 is set appropriately. First, the control circuit 66A turns on the switches SW11 and SW12 of the switch circuit 69A.

[0253] 3A, the control circuit 66A turns on the transistors MP1 and MN4 of the driver 11 and turns off the transistors MN2 and MP3. If the output impedance of the driver 11 is set appropriately, the voltage of the output terminal OUTP is desirably 3 / 4×(VRH−VRL)+VRL, and the voltage of the output terminal OUTN is desirably 1 / 4×(VRH−VRL)+VRL.

[0254] Next, the control circuit 66A controls the operation of the switch SW16 to connect the node N11 to the comparator 25. As a result, the voltage at the output terminal OUTP is supplied to the negative input terminal of the comparator 25. The control circuit 66A then sets the ratio of the resistance values ​​of the variable resistor element RH and the variable resistor element RL in the voltage generating circuit 24 to 1:3. As a result, the reference voltage VREF becomes "3 / 4 × (VRH - VRL) + VRL". The control circuit 66A then slightly changes the impedance of the circuit UP associated with the transistor MP1, for example, and checks whether the output signal of the comparator 25 changes.

[0255] Next, the control circuit 66A controls the operation of the switch SW16 to connect the node N12 to the comparator 25. As a result, the voltage at the output terminal OUTN is supplied to the negative input terminal of the comparator 25. The control circuit 66A then sets the ratio of the resistance value of the variable resistance element RH to the resistance value of the variable resistance element RL in the voltage generation circuit 24 to 3:1. As a result, the reference voltage VREF becomes "1 / 4 × (VRH - VRL) + VRL". The control circuit 66A then slightly changes the impedance of the circuit DN associated with the transistor MN4, for example, and checks whether the output signal of the comparator 25 changes.

[0256] If the output signal of the comparator 25 changes when the impedance of the circuit UP is slightly changed, and if the output signal of the comparator 25 changes when the impedance of the circuit DN is slightly changed, the control circuit 66A determines that the impedances of the circuits UP and DN are set appropriately.

[0257] 3B, the control circuit 66A turns on the transistors MN2 and MP3 of the driver 11 and turns off the transistors MP1 and MN4. If the output impedance of the driver 11 is set appropriately, the voltage at the output terminal OUTP is desirably 1 / 4×(VRH−VRL)+VRL, and the voltage at the output terminal OUTN is desirably 3 / 4×(VRH−VRL)+VRL.

[0258] Next, the control circuit 66A controls the operation of the switch SW16 to connect the node N11 to the comparator 25. As a result, the voltage at the output terminal OUTP is supplied to the negative input terminal of the comparator 25. The control circuit 66A then sets the ratio of the resistance value of the variable resistor element RH to the resistance value of the variable resistor element RL in the voltage generating circuit 24 to 3:1. As a result, the reference voltage VREF becomes "1 / 4 × (VRH - VRL) + VRL". The control circuit 66A then slightly changes the impedance of the circuit UN associated with the transistor MP3, for example, and checks whether the output signal of the comparator 25 changes.

[0259] Next, the control circuit 66A controls the operation of the switch SW16 to connect the node N12 to the comparator 25. As a result, the voltage at the output terminal OUTN is supplied to the negative input terminal of the comparator 25. The control circuit 66A then sets the ratio of the resistance value of the variable resistance element RH to the resistance value of the variable resistance element RL in the voltage generation circuit 24 to 1:3. As a result, the reference voltage VREF becomes "3 / 4 × (VRH - VRL) + VRL". The control circuit 66A then slightly changes the impedance of the circuit DP associated with the transistor MN2, for example, and checks whether the output signal of the comparator 25 changes.

[0260] If the output signal of the comparator 25 changes when the impedance of the circuit UN is slightly changed, and if the output signal of the comparator 25 changes when the impedance of the circuit DP is slightly changed, the control circuit 66A determines that the impedances of the circuits UN and DP are set appropriately.

[0261] In this way, the impedance adjustment circuit 60A checks whether the impedances of the circuits UP, DP, UN, and DN are set appropriately, thereby checking whether the output impedance of the driver 11 is set appropriately.

[0262] Thereafter, the control circuit 66A turns off the switches SW11 and SW12, and the communication system 3A performs communication operations.

[0263] [Variation 3-4] In the above embodiment, one communication lane is provided as shown in FIG. 28 . However, this is not limiting. Instead, multiple communication lanes (two communication lanes L1 and L2 in this example) may be provided, as in the communication system 3B shown in FIG. 37 . The communication system 3B includes a transmitting device 50B and a receiving device 100B. In this example, an impedance adjustment circuit 60 is provided in the communication lane L1. This impedance adjustment circuit 60 performs impedance adjustment operations, similar to the above embodiment. The impedance adjustment circuit 60 then supplies setting data DT to the pre-driver 12 in the communication lane L1 and to the pre-driver 12 in the communication lane L2. The pre-driver 12 in the communication lane L1 configures the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 of the communication lane L1 based on this setting data DT. The pre-driver 12 of the communication lane L2 sets the circuits UP3 to UP0, DP3 to DP0, UN3 to UN0, and DN3 to DN0 in the driver 11 of the communication lane L2 based on this setting data DT.

[0264] [Other Modifications] Two or more of these modifications may be combined.

[0265] Although the present technology has been described above by giving several embodiments and modifications, the present technology is not limited to these embodiments and the like, and various modifications are possible.

[0266] For example, in each of the above embodiments, the voltage generating circuit 24 generates the reference voltage VREF by dividing the voltage using the variable resistance elements RH and RL, but this is not limited to this. Instead, the reference voltage VREF may be generated using, for example, a bandgap reference circuit.

[0267] For example, in each of the above-described embodiments, the driver 11 has the circuit configuration shown in FIG. 2 , but this is not limiting. Alternatively, for example, a driver 11C3 having the circuit configuration shown in FIGS. 38 and 39 may be used. As shown in FIG. 38 , this driver 11C3 includes transistors MP1, MN2, MP3, and MN4 and resistor elements R5 and R6. A signal SUP is supplied to the gate of transistor MP1, its source is connected to the power supply node of power supply voltage VRH, and its drain is connected to the drain of transistor MN2 and one end of resistor element R5. A signal SDP is supplied to the gate of transistor MN2, its source is connected to the power supply node of power supply voltage VRL, and its drain is connected to the drain of transistor MP1 and one end of resistor element R5. One end of resistor element R5 is connected to the drains of transistors MP1 and MN2, and the other end is connected to output terminal OUTP. A signal SUN is supplied to the gate of transistor MP3, its source is connected to the power supply node of the power supply voltage VRH, and its drain is connected to the drain of transistor MN4 and one end of resistor R6. A signal SDN is supplied to the gate of transistor MN4, its source is connected to the power supply node of the power supply voltage VRL, and its drain is connected to the drain of transistor MP3 and one end of resistor R6. One end of resistor R6 is connected to the drains of transistors MP3 and MN4, and the other end is connected to the output terminal OUTN. Transistor MP1 and resistor R5 correspond to circuit UP, transistor MN2 and resistor R5 correspond to circuit DP, transistor MP3 and resistor R6 correspond to circuit UN, and transistor MN4 and resistor R6 correspond to circuit DN.

[0268] Specifically, this driver 11C3 is configured as shown in FIG. 39 . In FIG. 39 , “×4,” “×8,” “×16,” and “×32” indicate the number of parallel connections. In this example, this driver 11C3 is configured using 60 (=4+8+16+32) circuits U. Of the 60 circuits U, four circuits U are connected in parallel, eight circuits U are connected in parallel, 16 circuits U are connected in parallel, and 32 circuits U are connected in parallel. Each of these 60 circuits U has two transistors MP corresponding to transistors MP1 and MP3, two transistors MN corresponding to transistors MN2 and MN4, and two resistor elements RES corresponding to resistor elements R5 and F6, respectively. The four parallel-connected circuits U operate based on signals SUP3, SDP3, SUN3, and SDN3. The eight parallel-connected circuits U operate based on signals SUP2, SDP2, SUN2, and SDN2. The sixteen parallel-connected circuits U operate based on signals SUP1, SDP1, SUN3, and SDN3. The thirty-two parallel-connected circuits U operate based on signals SUP0, SDP0, SUN0, and SDN0.

[0269] With this configuration, the impedance between the output terminal OUTP and the power supply node of the power supply voltage VRH is adjusted by signals SUP3 to SUP0, the impedance between the output terminal OUTP and the power supply node of the power supply voltage VRL is adjusted by signals SDP3 to SDP0, the impedance between the output terminal OUTN and the power supply node of the power supply voltage VRH is adjusted by signals SUN3 to SUN0, and the impedance between the output terminal OUTN and the power supply node of the power supply voltage VRL is adjusted by signals SDN3 to SDN0. As a result, the driver 11C3 can adjust the output impedance seen from the output terminal OUTP and the output impedance seen from the output terminal OUTN.

[0270] In this example, this modified example is applied to the driver 11 having the circuit configuration shown in FIG. 3, but this is not limited to this, and instead, for example, this modified example may be applied to the driver 11C1 shown in FIG. 11.

[0271] For example, in the first embodiment, if the driver 11C3 shown in Figures 38 and 39 is used, the dummy driver 21 also has a circuit configuration similar to that of the driver 11C3. If the driver 11C3 has 60 circuits U, the dummy driver 21 has, for example, 15 circuits U (=1 + 2 + 4 + 8). Of the 15 circuits U, two circuits U are connected in parallel, four circuits U are connected in parallel, and eight circuits U are connected in parallel. One circuit U operates based on signals SDUP3, SDDP3, SDUN3, and SDDN3. The two parallel-connected circuits U operate based on signals SDUP2, SDDP2, SDUN2, and SDDN2. The four parallel-connected circuits U operate based on signals SDUP1, SDDP1, SDUN3, and SDDN3. The eight circuits U connected in parallel operate based on signals SDUP0, SDDP0, SDUN0, and SDDN0.

[0272] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0273] The present technology can be configured as follows: According to the present technology configured as follows, it is possible to effectively adjust the output impedance.

[0274] (1) A dummy driver including: a first circuit provided in a path connecting a first node and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal; a second circuit provided in a path connecting the first node and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal; a third circuit provided in a path connecting the second node and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal; and a fourth circuit provided in a path connecting the second node and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, the dummy driver being capable of changing an impedance of the first circuit, an impedance of the second circuit, an impedance of the third circuit, and an impedance of the fourth circuit; a first switch provided in the path connecting the first node and the second node; a fifth circuit provided in a path connecting a first output terminal and the first power supply node, the fifth circuit including a fifth transistor and a fifth resistor element that can be turned on and off based on a fifth signal; a sixth circuit provided in a path connecting the first output terminal and the second power supply node, the sixth circuit including a sixth transistor and a sixth resistor element that can be turned on and off based on a sixth signal; a seventh circuit provided in a path connecting the second output terminal and the first power supply node, the seventh circuit including a seventh transistor and a seventh resistor element that can be turned on and off based on a seventh signal; and an eighth circuit provided in a path connecting the second output terminal and the second power supply node, the eighth circuit including an eighth transistor and an eighth resistor element that can be turned on and off based on an eighth signal; and a driver that can change an impedance of the fifth circuit, an impedance of the sixth circuit, an impedance of the seventh circuit, and an impedance of the eighth circuit; a control circuit capable of setting an impedance of the first circuit, an impedance of the second circuit, an impedance of the third circuit, an impedance of the fourth circuit, an impedance of the fifth circuit, an impedance of the sixth circuit, an impedance of the seventh circuit, and an impedance of the eighth circuit and capable of controlling an operation of the first switch;the control circuit is capable of performing a first operation, the first operation including: turning on the first switch; turning on the second transistor and the third transistor and turning off the first transistor and the fourth transistor; sequentially changing the impedance of the second circuit; and setting the impedance of the sixth circuit and the impedance of the eighth circuit in the driver based on first setting data that is set based on the voltage of the second node when the impedance of the second circuit is sequentially changed. (2) The transmitting device according to (1), further comprising: a current source capable of causing a current to flow from a third node toward a ground node; and a second switch provided in a path connecting the second node and the third node, wherein the control circuit is capable of performing a second operation before the first operation, and the second operation includes: turning the first switch to an off state and turning the second switch to an on state; turning the third transistor to an on state and turning the fourth transistor to an off state; sequentially changing the impedance of the third circuit; and setting the impedance of the fifth circuit and the impedance of the seventh circuit in the driver based on second setting data set based on the voltage of the second node when the impedance of the third circuit is sequentially changed. (3) The driver further includes a voltage generating circuit capable of generating a reference voltage and changing the reference voltage; and a comparator capable of comparing a voltage at the second node with the reference voltage, wherein the first operation includes: setting the reference voltage to a first voltage; and setting the impedance of the sixth circuit and the impedance of the eighth circuit in the driver based on the first setting data that is set based on a comparison result of the comparator when the impedance of the second circuit is sequentially changed; and the second operation includes: setting the reference voltage to a second voltage;(4) The transmitter according to (3), wherein the comparator is further capable of comparing the voltage of the first output terminal with the reference voltage, and the comparator is further capable of comparing the voltage of the second output terminal with the reference voltage. (5) The transmitter according to any of (2) to (4), wherein the first operation further includes generating the first setting data based on the voltage of the second node when the impedance of the second circuit is sequentially changed, and the second operation further includes generating the second setting data based on the voltage of the second node when the impedance of the third circuit is sequentially changed. (6) The transmitting device according to any one of (2) to (4), comprising a plurality of the drivers, wherein the first operation includes setting an impedance of the sixth circuit and an impedance of the eighth circuit in each of the plurality of drivers based on the first setting data, and the second operation includes setting an impedance of the fifth circuit and an impedance of the seventh circuit in each of the plurality of drivers based on the second setting data. (7) The second circuit in the dummy driver has a plurality of partial paths provided in parallel to each other, wherein the second transistor has a transistor provided in each of the plurality of partial paths in the second circuit, wherein the second resistive element has a resistive element provided in each of the plurality of partial paths in the second circuit, wherein the second circuit has a plurality of partial circuits including a first partial circuit having a first number of partial paths and a second partial circuit having a second number of partial paths that is twice the first number, and wherein the impedance of the second circuit is adjustable by setting the plurality of partial circuits in the second circuit to be enabled or disabled on a partial circuit basis,The sixth circuit in the driver has a plurality of partial paths arranged in parallel with each other, the sixth transistor has a transistor provided in each of the plurality of partial paths in the sixth circuit, the sixth resistive element has a resistive element provided in each of the plurality of partial paths in the sixth circuit, the sixth circuit has a plurality of partial circuits including a third partial circuit having a third number of partial paths and a fourth partial circuit having a fourth number of partial paths that is twice the third number, and the impedance of the sixth circuit is adjustable by setting the plurality of partial circuits in the sixth circuit to be enabled or disabled on a partial circuit basis. A transmitting device described in any of (1) to (6). (8) The transmitting device according to (7), wherein the third number in the third partial circuit of the driver is greater than the first number in the first partial circuit of the dummy driver, the fourth number in the fourth partial circuit of the driver is greater than the second number in the second partial circuit of the dummy driver, the control circuit is capable of determining whether to enable or disable the first partial circuit in the second circuit and whether to enable or disable the second partial circuit in the second circuit based on a voltage of the second node when the impedance of the second circuit is sequentially changed, the enable or disable setting of the third partial circuit in the sixth circuit of the driver is set to be the same as the enable or disable setting of the first partial circuit in the second circuit of the dummy driver, and the enable or disable setting of the fourth partial circuit in the sixth circuit of the driver is set to be the same as the enable or disable setting of the second partial circuit in the second circuit of the dummy driver.a driver having: a first circuit provided in a path connecting a first output terminal and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal; a second circuit provided in a path connecting the first output terminal and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal; a third circuit provided in a path connecting the second output terminal and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal; and a fourth circuit provided in a path connecting the second output terminal and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, the driver being able to change an impedance of the first circuit, an impedance of the second circuit, an impedance of the third circuit, and an impedance of the fourth circuit; a first switch provided in the path connecting the first output terminal and the second output terminal; a control circuit capable of setting an impedance of the first circuit, an impedance of the second circuit, an impedance of the third circuit, and an impedance of the fourth circuit and capable of controlling an operation of the first switch, wherein the control circuit is capable of performing a first operation, the first operation including: turning on the first switch; turning on the second transistor and the third transistor and turning off the first transistor and the fourth transistor; sequentially changing the impedance of the second circuit; and setting the impedance of the second circuit and the impedance of the fourth circuit based on first setting data that is set based on a voltage of the second output terminal when the impedance of the second circuit is sequentially changed. (10) The control circuit is capable of performing a second operation before the first operation, and the second operation includes turning off the first switch, turning on the third transistor and turning off the fourth transistor, and sequentially changing the impedance of the third circuit while sinking current from the second output terminal.and setting the impedance of the first circuit and the impedance of the third circuit based on second setting data that is set based on the voltage of the second output terminal when the impedance of the third circuit is sequentially changed. (11) The transmission device according to (10), further comprising: a voltage generation circuit capable of generating a reference voltage and changing the reference voltage; and a comparator capable of comparing the voltage of the second output terminal with the reference voltage, wherein the first operation includes setting the reference voltage to a first voltage, and setting the impedance of the second circuit and the impedance of the fourth circuit based on the first setting data that is set based on the comparison result of the comparator when the impedance of the second circuit is sequentially changed, and the second operation includes setting the reference voltage to a second voltage, and setting the impedance of the first circuit and the impedance of the third circuit based on the second setting data that is set based on the comparison result of the comparator when the impedance of the third circuit is sequentially changed. (12) The transmitting device according to (10) or (11), further comprising a plurality of the drivers, wherein the first operation and the second operation are performed using a first driver among the plurality of drivers, the first operation includes setting an impedance of the second circuit and an impedance of the fourth circuit in a second driver among the plurality of drivers based on the first setting data, and the second operation includes setting an impedance of the first circuit and an impedance of the third circuit in the second driver based on the second setting data.a first circuit provided in a path connecting a first node and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal; a second circuit provided in a path connecting the first node and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal; a third circuit provided in a path connecting the second node and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal; and a fourth circuit provided in a path connecting the second node and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, (14) An output impedance adjusting method for a driver including: a fifth circuit provided in a path connecting a first output terminal and the first power supply node and including a fifth transistor and a fifth resistor element that can be turned on and off based on a fifth signal, a sixth circuit provided in a path connecting the first output terminal and the second power supply node and including a sixth transistor and a sixth resistor element that can be turned on and off based on a sixth signal, a seventh circuit provided in a path connecting the second output terminal and the first power supply node and including a seventh transistor and a seventh resistor element that can be turned on and off based on a seventh signal, and an eighth circuit provided in a path connecting the second output terminal and the second power supply node and including an eighth transistor and an eighth resistor element that can be turned on and off based on an eighth signal, the method including: setting an impedance of the sixth circuit and an impedance of the eighth circuit based on first setting data that is set based on a voltage of the second node when the impedance of the second circuit is sequentially changed.a first circuit provided in a path connecting a first output terminal and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal; a second circuit provided in a path connecting the first output terminal and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal; a third circuit provided in a path connecting the second output terminal and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal; and a fourth circuit provided in a path connecting the second output terminal and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, an output impedance adjusting method comprising: sequentially changing the impedance of the second circuit; setting the impedance of the second circuit and the impedance of the fourth circuit based on first setting data that is set based on the voltage of the first output terminal when the impedance of the second circuit is sequentially changed; sequentially changing the impedance of the third circuit; and setting the impedance of the first circuit and the impedance of the third circuit based on second setting data that is set based on the voltage of the second output terminal when the impedance of the third circuit is sequentially changed.

[0275] This application claims priority based on Japanese Patent Application No. 2023-145194, filed on September 7, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0276] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A dummy driver having a first circuit provided on a path connecting a first node and a first power supply node, the first circuit including a first transistor and a first resistance element that can be turned on and off based on a first signal, a second circuit provided on a path connecting the first node and a second power supply node, the second circuit including a second transistor and a second resistance element that can be turned on and off based on a second signal, a third circuit provided on a path connecting the second node and the first power supply node, the third circuit including a third transistor and a third resistance element that can be turned on and off based on a third signal, and a fourth circuit provided on a path connecting the second node and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistance element that can be turned on and off based on a fourth signal, the dummy driver being capable of changing an impedance of the first circuit, an impedance of the second circuit, an impedance of the third circuit, and an impedance of the fourth circuit; a first switch provided on the path connecting the first node and the second node; a fifth circuit provided on a path connecting a first output terminal and the first power supply node, the fifth circuit including a fifth transistor and a fifth resistor element that can be turned on and off based on a fifth signal; a sixth circuit provided on a path connecting the first output terminal and the second power supply node, the sixth circuit including a sixth transistor and a sixth resistor element that can be turned on and off based on a sixth signal; a seventh circuit provided on a path connecting the second output terminal and the first power supply node, the seventh circuit including a seventh transistor and a seventh resistor element that can be turned on and off based on a seventh signal; and an eighth circuit provided on a path connecting the second output terminal and the second power supply node, the eighth circuit including an eighth transistor and an eighth resistor element that can be turned on and off based on an eighth signal, and a driver capable of changing an impedance of the fifth circuit, an impedance of the sixth circuit, an impedance of the seventh circuit, and an impedance of the eighth circuit; a control circuit capable of setting an impedance of the first circuit, an impedance of the second circuit, an impedance of the third circuit, an impedance of the fourth circuit, an impedance of the fifth circuit, an impedance of the sixth circuit, an impedance of the seventh circuit, and an impedance of the eighth circuit and capable of controlling an operation of the first switch,a first operation including: turning on the first switch; turning on the second transistor and the third transistor and turning off the first transistor and the fourth transistor; sequentially changing an impedance of the second circuit; and setting an impedance of the sixth circuit and an impedance of the eighth circuit in the driver based on first setting data that is set based on a voltage of the second node when the impedance of the second circuit is sequentially changed.

2. The transmitting device according to claim 1, further comprising: a current source capable of causing a current to flow from a third node to a ground node; and a second switch provided in a path connecting the second node and the third node, wherein the control circuit is capable of performing a second operation before the first operation, and the second operation includes turning the first switch to an off state and turning the second switch to an on state, turning the third transistor to an on state and turning the fourth transistor to an off state, sequentially changing the impedance of the third circuit, and setting the impedance of the fifth circuit and the impedance of the seventh circuit in the driver based on second setting data that is set based on the voltage of the second node when the impedance of the third circuit is sequentially changed.

3. The transmitting device according to claim 2, further comprising: a voltage generating circuit capable of generating a reference voltage and changing the reference voltage; and a comparator capable of comparing a voltage at the second node with the reference voltage, wherein the first operation includes: setting the reference voltage to a first voltage; and setting the impedance of the sixth circuit and the impedance of the eighth circuit in the driver based on the first setting data that is set based on a comparison result of the comparator when the impedance of the second circuit is sequentially changed; and the second operation includes: setting the reference voltage to a second voltage; and setting the impedance of the fifth circuit and the impedance of the seventh circuit in the driver based on the second setting data that is set based on a comparison result of the comparator when the impedance of the third circuit is sequentially changed.

4. The transmitting device according to claim 3, wherein the comparator is further capable of comparing the voltage at the first output terminal with the reference voltage, and is capable of comparing the voltage at the second output terminal with the reference voltage.

5. The transmitting device of claim 2, wherein the first operation further includes generating the first setting data based on the voltage of the second node when the impedance of the second circuit is sequentially changed, and the second operation further includes generating the second setting data based on the voltage of the second node when the impedance of the third circuit is sequentially changed.

6. A transmitting device as described in claim 2, comprising a plurality of drivers, wherein the first operation includes setting an impedance of the sixth circuit and an impedance of the eighth circuit in each of the plurality of drivers based on the first setting data, and the second operation includes setting an impedance of the fifth circuit and an impedance of the seventh circuit in each of the plurality of drivers based on the second setting data.

7. The second circuit in the dummy driver has a plurality of partial paths provided in parallel with each other, the second transistor has a transistor provided in each of the plurality of partial paths in the second circuit, the second resistance element has a resistance element provided in each of the plurality of partial paths in the second circuit, the second circuit has a plurality of partial circuits including a first partial circuit having a first number of partial paths and a second partial circuit having a second number of partial paths that is twice the first number, the impedance of the second circuit is adjustable by setting the plurality of partial circuits in the second circuit to be enabled or disabled on a partial circuit basis, the sixth circuit in the driver has a plurality of partial paths provided in parallel with each other, the sixth transistor has a transistor provided in each of the plurality of partial paths in the sixth circuit, and the sixth resistance element has a resistance element provided in each of the plurality of partial paths in the sixth circuit, The transmitting device according to claim 1, wherein the sixth circuit has a plurality of partial circuits including a third partial circuit having a third number of partial paths and a fourth partial circuit having a fourth number of partial paths that is twice the third number, and the impedance of the sixth circuit is adjustable by setting the plurality of partial circuits in the sixth circuit to be enabled or disabled on a partial circuit basis.

8. The transmitting device of claim 7, wherein the third number in the third partial circuit of the driver is greater than the first number in the first partial circuit of the dummy driver; the fourth number in the fourth partial circuit of the driver is greater than the second number in the second partial circuit of the dummy driver; the control circuit is capable of determining an enable or disable setting of the first partial circuit in the second circuit and an enable or disable setting of the second partial circuit in the second circuit based on a voltage of the second node when an impedance of the second circuit is sequentially changed; the enable or disable setting of the third partial circuit in the sixth circuit of the driver is set to be the same as the enable or disable setting of the first partial circuit in the second circuit of the dummy driver; and the enable or disable setting of the fourth partial circuit in the sixth circuit of the driver is set to be the same as the enable or disable setting of the second partial circuit in the second circuit of the dummy driver.

9. A driver having a first circuit provided on a path connecting a first output terminal and a first power supply node, the first circuit including a first transistor and a first resistor element that can be turned on and off based on a first signal, a second circuit provided on a path connecting the first output terminal and a second power supply node, the second circuit including a second transistor and a second resistor element that can be turned on and off based on a second signal, a third circuit provided on a path connecting the second output terminal and the first power supply node, the third circuit including a third transistor and a third resistor element that can be turned on and off based on a third signal, and a fourth circuit provided on a path connecting the second output terminal and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistor element that can be turned on and off based on a fourth signal, the driver being capable of changing an impedance of the first circuit, an impedance of the second circuit, an impedance of the third circuit, and an impedance of the fourth circuit; a first switch provided on the path connecting the first output terminal and the second output terminal; a control circuit capable of setting an impedance of the first circuit, an impedance of the second circuit, an impedance of the third circuit, and an impedance of the fourth circuit and capable of controlling an operation of the first switch, wherein the control circuit is capable of performing a first operation, the first operation including: turning on the first switch; turning on the second transistor and the third transistor and turning off the first transistor and the fourth transistor; sequentially changing the impedance of the second circuit; and setting the impedance of the second circuit and the impedance of the fourth circuit based on first setting data that is set based on a voltage of the second output terminal when the impedance of the second circuit is sequentially changed.

10. The transmitting device according to claim 9, wherein the control circuit is capable of performing a second operation before the first operation, and the second operation includes: turning off the first switch; turning on the third transistor and turning off the fourth transistor; sequentially changing the impedance of the third circuit while sinking current from the second output terminal; and setting the impedance of the first circuit and the impedance of the third circuit based on second setting data that is set based on the voltage of the second output terminal when the impedance of the third circuit is sequentially changed.

11. The transmitting device according to claim 10, further comprising: a voltage generating circuit capable of generating a reference voltage and changing the reference voltage; and a comparator capable of comparing a voltage at the second output terminal with the reference voltage, wherein the first operation includes: setting the reference voltage to a first voltage; and setting the impedance of the second circuit and the impedance of the fourth circuit based on the first setting data that is set based on a comparison result of the comparator when the impedance of the second circuit is sequentially changed; and the second operation includes: setting the reference voltage to a second voltage; and setting the impedance of the first circuit and the impedance of the third circuit based on the second setting data that is set based on a comparison result of the comparator when the impedance of the third circuit is sequentially changed.

12. A transmitting device as described in claim 10, comprising a plurality of the drivers, the first operation and the second operation being performed using a first driver of the plurality of drivers, the first operation including setting an impedance of the second circuit and an impedance of the fourth circuit in a second driver of the plurality of drivers based on the first setting data, and the second operation including setting an impedance of the first circuit and an impedance of the third circuit in the second driver based on the second setting data.

13. A dummy driver having a first circuit provided on a path connecting a first node and a first power supply node, the first circuit including a first transistor and a first resistance element that can be turned on and off based on a first signal, a second circuit provided on a path connecting the first node and a second power supply node, the second circuit including a second transistor and a second resistance element that can be turned on and off based on a second signal, a third circuit provided on a path connecting the second node and the first power supply node, the third circuit including a third transistor and a third resistance element that can be turned on and off based on a third signal, and a fourth circuit provided on a path connecting the second node and the second power supply node, the fourth circuit including a fourth transistor and a fourth resistance element that can be turned on and off based on a fourth signal, the driver comprising: turning on a first switch provided on a path connecting the first node and the second node; turning on the second transistor and the third transistor and turning off the first transistor and the fourth transistor; sequentially changing an impedance of the second circuit; an output impedance adjusting method for a driver including: a fifth circuit provided in a path connecting a first output terminal and the first power supply node, the fifth circuit including a fifth transistor and a fifth resistor element that can be turned on and off based on a fifth signal; a sixth circuit provided in a path connecting the first output terminal and the second power supply node, the sixth circuit including a sixth transistor and a sixth resistor element that can be turned on and off based on a sixth signal; a seventh circuit provided in a path connecting the second output terminal and the first power supply node, the seventh circuit including a seventh transistor and a seventh resistor element that can be turned on and off based on a seventh signal; and an eighth circuit provided in a path connecting the second output terminal and the second power supply node, the eighth circuit including an eighth transistor and an eighth resistor element that can be turned on and off based on an eighth signal, the method comprising: setting an impedance of the sixth circuit and an impedance of the eighth circuit based on first setting data that is set based on a voltage of the second node when the impedance of the second circuit is sequentially changed.

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