Testing communication receivers with periodic signals

Abstract

A system (100) includes a testing transmitter (102) including a Pseudo-Random Bit Sequence (PRBS) generator and a signal generation circuit. The PRBS generator is configured to generate a PRBS. The signal generation circuit is configured to generate a test signal that includes repetitions of a truncated portion of the PRBS, such that a period of the repetitions is shorter than the period of the PRBS.

Description

[0001] TESTING COMMUNICATION RECEIVERS WITH PERIODIC SIGNALS

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of U.S. Provisional Patent Application 63 / 581,005, filed September 7, 2023, whose disclosure is incorporated herein by reference.

[0004] FIELD OF THE INVENTION

[0005] The present invention relates generally to communication systems, and particularly to the testing of communication receivers.

[0006] BACKGROUND OF THE INVENTION

[0007] Digital communication systems and, in particular, digital communication receivers present a significant testing challenge. Some background on the testing of digital communication systems can be found in “A survey of communication protocol testing”, Lai, R., Journal of Systems and Software, 62(1), 21-46 (2002), including a literature survey of communication protocol testing, focusing on the following five areas: test sequence generation methods, test coverage, fault model and prediction, test tools, and experience reports.

[0008] Other communication system testing background can be found in “BER Testing of Communication Interfaces”, Yongquan Fan, & Zilic, Z. IEEE Transactions on Instrumentation and Measurement, 57(5) (2008). The authors present a versatile bit-error-rate (BER) testing scheme to characterize the quality of communication interfaces. The paper presents, for both the design and evaluation phases, a scheme for BER testing in field-programmable gate arrays (FPGAs) that consists of a BER tester (BERT) core and a novel additive white Gaussian noise (AWGN) generator core; the authors further present a pipelined structure that exploits the central limit theorem for speedups of four or more.

[0009] SUMMARY OF THE INVENTION

[0010] An embodiment of the present invention that is described herein provides a system including a testing transmitter including a Pseudo-Random Bit Sequence (PRBS) generator and a signal generation circuit. The PRBS generator is configured to generate a PRBS. The signal generation circuit is configured to generate a test signal that includes repetitions of a truncated portion of the PRBS, such that a period of the repetitions is shorter than the period of the PRBS.

[0011] In some embodiments, in generating the test signal, the signal generation circuit is configured to generate a sequence of packets including (i) the repetitions of the truncated portion of the PRBS serving as payloads, and (ii) additional symbols. In some embodiments, the system further includes receiver circuitry' and a test circuit. The receiver circuitry is configured to receive and decode the test signal. The test circuit is configured to generate a reference signal that is identical to the repetitions of the truncated portion of the PRBS, and to evaluate a performance of the receiver circuitry- by comparing the reference signal to the test signal decoded by the receiver circuitry-’.

[0012] In an example embodiment, the test circuit in the receiver is configured to generate the reference signal that, includes repetitions of the truncated portion of the PRBS. In another embodiment, the test signal generated by the transmitter includes additional symbols interleaved between the repetitions of the truncated portion of the PRBS, and the test circuit in the receiver is configured to omit the additional symbols from comparison to the reference signal.

[0013] There is additionally provided, in accordance with an embodiment of the present invention, a test transmitter including an encoder and a test sequence generation circuit. The encoder is configured to encode an input data sequence with an unterminated Forward Error Correction (FEC) code. The test sequence generation circuit is configured to generate a periodic FEC-cyclic test sequence of a preset period length that, when encoded repeatedly by the encoder, forms a valid unterrminated encoded data stream in accordance with the FEC code.

[0014] In some embodiments, each period of the FEC-cyclic test sequence begins at a same state of the encoder. In some embodiments, the test sequence generation circuit is configured to insert Cyclic Redundancy Check (CRC) codes within the FEC-cyclic test sequence.

[0015] There is also provided, in accordance with an embodiment of the present invention, a method for test signal generation, including generating a Pseudo-Random Bit Sequence (PRBS). A test signal, which includes repetitions of a truncated portion of the PRBS, is generated such that, a period of the repetitions is shorter than the period of the PRBS.

[0016] There is further provided, in accordance with an embodiment of the present invention, a method for test signal generation including operating an encoder that encodes an input, data sequence with an unterminated Forward Error Correction (FEC) code. A periodic FEC-cyclic test sequence of a preset period length is generated that, when encoded repeatedly by the encoder, forms a valid unterminated encoded data stream in accordance with the FEC code.

[0017] The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

[0018] BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Fig. 1 is a block diagram that schematically illustrates a Test System, in accordance with an embodiment of the present invention; Fig. 2 is a block diagram that schematically illustrates a Mode-A Configured OIF 800ZR Testing Transmitter, in accordance with an embodiment of the present invention;

[0020] Fig. 3 is a block diagram that schematically illustrates a Mode-B Configured OIF 400ZR Testing Transmitter, in accordance with an embodiment of the present invention;

[0021] Fig. 4 is a. flowchart that schematically illustrates a method for creating a valid periodic test sequence, in accordance with an embodiment of the present invention;

[0022] Fig. 5 A is a flowchart, that schematically illustrates a method for the testing of a communication Receiver Under Test (RUT) in a first testing mode, in accordance with an embodiment of the present invention; and

[0023] Fig. 5B is a flowchart that schematically illustrates a method for the testing of a communication RUT in a second testing mode, in accordance with an embodiment of the present invention.

[0024] DETAILED DESCRIPTION OF EMBODIMENTS

[0025] OVERVIEW

[0026] Modern high-speed digital communication systems are often complex and present a testing challenge. We will refer below mainly to optical (over fiber) communication systems; the present invention, however, is by no way limited to optical communication systems and can be applied to other suitable communication systems, e.g., using electrical, optical and electromagnetic signaling.

[0027] Many proprietary systems and standards for fiber-optics communication have emerged in last years. For example, Optical Internetworking Forum (OIF) standards 400ZR / 800ZR, openZR+, OpenROADM and others.

[0028] The 400ZR standard, for example, specifies a link reach of 80 kilometers without amplification and 120 kilometers with amplification, using QAM16 at rates of 60 to 68Gbaud. For forward error correction (FEC), the 400ZR standard supports a concatenated FEC (CFEC) method, which combines inner and outer FEC codes to enhance the performance compared to a standard FEC code.

[0029] The 800ZR is similar but faster, using QAM16 modulation.

[0030] To test and calibrate the communication equipment, the different parts of the modem need to be tested with various signals. On the receiver (Rx) side, the test may be performed with a test signal from a compatible transmitter, or from specialized test equipment.

[0031] Test and calibration using test equipment is preferrable in the sense that the transmitted signal quality is high, and that imperfections and errors can be inserted, for testing purposes. A drawback of using test equipment is that the transmission length is typically limited, and, hence, periodic signals, which may be poorly covered by some communication standards, should be used.

[0032] Embodiments of the present invention that are disclosed herein provide apparatuses and methods for the testing of a communication receiver (referred to as Receiver Under lest, or RUT) using multiple instances of a relatively short periodic test signal. In an embodiment, the Testing Transmitter is configured to operate in one of two modes - a first Mode (Mode- A) and a second mode (Mode-B).

[0033] In an embodiment that, is disclosed below, Mode-A is used to test the demodulator part of the RUT, using a truncated Pseudo-Random-Bit-Sequence (PRBS) that is input to the modulator part of the Testing Transmitter. The RUT is modified to compare the output of the RUT demodulator with the truncated PRBS sequences, and to output mismatches (if any).

[0034] In another embodiment that is disclosed below, Mode-B is used to test the complete RUT, using an FEC -cyclic test sequence that also generates a cyclic sequence at. the output of the Transmitter. The test sequence is input to the Testing Transmitter, which outputs a cyclic signal, with a period length that, is an integer number of super-frames. The test results can be examined by counting RUT CRC errors. In some Mode-B embodiments, the RUT comprises a multi block alignment signal (MBAS) circuit that is modified according to the length of the test sequence period.

[0035] Lastly, in an embodiment that is disclosed hereinbelow, a method for generating the FEC-cyclic input sequence is disclosed.

[0036] SYSTEM: DESCRIPTION

[0037] Forward Error Correction (FEC) that use Bose, Chaudhuri, and Hocquenghem (BCH) codewords generates output symbols according to input signals and to an internal state of the FEC circuit. Some communication standards (e.g., 400ZR, 800ZR) use infinite series of interleaved BCH codewords, resulting in an unterminated code, meaning that there is no point in time where the encoding terminates (in contrast, for example, with BCH, Hamming and other block codes). In the description hereinbelow, we wall use the term FEC for unterminated FEC (such as OFEC or CFEC).

[0038] In the embodiments to be disclosed below, we test a communication receiver (will be referred to as Receiver Under Test, or RUT) using a test equipment that comprises a modified communication transmitter. We focus on two testing scenarios - a de-modulator testing scenario (will be referred to hereinbelow as Mode A), and a complete receiver testing scenario (Mode B hereinbelow).

[0039] Fig. I is a block diagram that schematically illustrates a Test System 100, in accordance with an embodiment of the present invention. Test System 100 comprises a Testing Transmitter 102, a Medium 104 (e.g., a fiber-optics cable) and a Receiver Under Test (RUT) 106.

[0040] We will arbitrarily divide the transmission chain of Testing Transmitter 102 into two major circuits - an Encoder 108 and a Modulator 110. Encoder 108 includes some or all of the following circuits (not shown in Fig. 1) - a Cyclic Redundancy Code (CRC) circuit, a Padding circuit, a Scrambler, a Forward Error Correction (FEC)-encoder and an interleaver. Modulator 110 includes a Mapper and circuitry to add sync and pilot bits to the transmitted signal.

[0041] Similarly, we divide the receive chain to a Demodulator 112 and a Decoder 114. Demodulator 112 includes circuitry to sync the input data according to the sync and pilot bits, and a de-Mapper. Decoder 114 includes some or all of the following circuits: an FEC-decoder, a Descrambler, a de-interleaver, a Pad-Remover and a CRC Checker. It should be noted that, in some embodiments, not all the functions described above are included; moreover, in embodiments, other functions may be added to the chain, e.g., an Error Correction Code (ECC) insertion in the Testing Transmitter, and an Error Correction circuit in the RUT.

[0042] According to the example embodiment illustrated in Fig. 1, Testing Transmitter 120 comprises a configuration switch 116, which sets the testing mode to either Mode A, which mainly tests the demodulation functions of the RUT, or a Mode B, which tests the full functionality of the RUT. When in Mode A, Tx Encoder 108 is not used and, instead, a Tx Pseudo-Random-Binary-Sequence (PRBS) generator 118 sends a periodic truncated PRBS sequence to the Tx Modulator 110. The Truncated PRBS generator 118 starts the PRBS from a given seed; in some embodiments the seed may change between tests, e.g., the seed may be preloaded by a processor of the Testing Transmitter (that is not shown). The PRBS length is relatively large (for example, the length of 31-bit PRBS31 is 2,147,483,647 bits) and may be impractical to use as a testing signal, therefore, Truncated PRBS generator 118 sends repetitions of a truncated PRBS. In some embodiments, the truncated PRBS length is an integer number of super-frames (as defined in the 400ZR / 800ZR and other standards).

[0043] According to the example embodiment illustrated in Fig. 1, for Mode A testing, RUT 106 comprises a Comparator 120 that compares the sequence received by Demodulator 112 with a periodic truncated PRBS sequence that an Rx Truncated-PRBS generator 122 generates. In some embodiments, Rx Truncated-PRBS generator 122 is the same as Tx Truncated-PRBS generator 118, starting from the same seed, and generating the same sequence (Tx-Rx Truncated-PRBS synchronization techniques that may be used in embodiments will be described below). Thus, when in Mode A, the tests results can be observed at the output of Comparator 120 (in some embodiments, RUT 106 may further comprise an error counter, to count errors that the comparator detects).

[0044] In embodiments, various Truncated-PRBS synchronization techniques may be used:

[0045] 1. In some embodiments, when the length of the Truncated-PRBS is a single superframe, the Rx Truncated-PRBS generator may restart (to the preset seed value), responsively to the sync signal that Demodulator 112 detects.

[0046] 2. In other embodiments, when the length of the Truncated-PRBS is a one or more super-frame, the Rx PRBS generator can detect the last state of the truncated PRBS period, and, responsively, restart to the preset seed value.

[0047] 3. In yet other embodiments, when the Truncated-PRBS length is one or more superframes, the RUT comprises a super-frame counter that resets at the beginning of the test (e.g., responsively to a global RUT reset signal), increments responsively to the sync signal that Demodulator 112 detects and resets when a preset number of superframes has been received.

[0048] 4. Lastly, in some other embodiments, the Testing Transmitter sends an out-of-band Truncated-PRBS Restart signal, and the Rx Truncated-PRBS generator resets responsively to receiving the Restart indication.

[0049] A detailed description of an OIF 800ZR Testing Transmitter set to Mode A will be described below7, with reference to Fig. 2.

[0050] When Test System 100 is set to Mode-B testing, Switch 116 routes the output of Tx Encoder 108 to Tx Modulator 110, and, thus, PRBS Generator 118 is not used. A Forward- Error-Correction (FEC)-Cyclic Sequence Generator 124 sends a periodic test sequence to Tx Encoder 108, which Encodes the sequence (including functions such as adding CRC, scrambling, FEC -encoding, interleaving, etc.), and sends the encoded signal to Tx Modulator 110.

[0051] The periodic test sequence that FEC -Cyclic Sequence Generator 124 generates is repetitive, with a period cycle that is an integer number of super-frames. In addition, the periodic test sequences are built such that the consequent Tx -Encoder output wall also be periodic. This requirement may be challenging because the output of the FEC-encoder of the Tx Testing Transmitter is generated according to the input and to an internal FEC-encoder state, that changes responsively to the input. In embodiments, the FEC -Cyclic sequence is configured so that, when input to the FEC circuit, the internal FEC-encoder state will also be cyclic, having the same period cycle.

[0052] A detailed description of an OIF 400ZR Testing Transmitter set to Mode A will be described below, with reference to Fig. 3. An example technique to generate such FEC-cyclic sequences will be described below, with reference to Fig. 4.

[0053] When in Mode B, the test results can be obtained by observing a CRC error count that Rx Decoder 114 outputs.

[0054] In some embodiments, Testing Transmitter 102 further comprises an Error Insertion circuit 126 to test the fault resilience and fault recovery of RUT 104. The Error Insertion circuit may be configured to insert errors in various Testing-Transmitter circuits, under software control. In some embodiments, the Error Insertion circuit is also configured to insert errors in the medium, e.g., by controlling a variable optical attenuator that is coupled to a fiber-optics.

[0055] Thus, according to the example embodiment illustrated in Fig. 1 and described herein above, a testing transmitter can test an RUT in two modes - a modulator-demodulator test (Mode A), wherein the modulation and demodulation are tested using a Periodic Truncated-PRBS signal, and a full test (Mode B), wherein the complete communication path is tested using a periodic input that is designed to generate a periodic output.

[0056] The configuration of Test System 100 is cited by way of example. Other configurations may be used in alternative embodiments. For example, in some embodiments, the Testing Transmitter is configured to test the RUT in Mode A only, and, thus, some of the Testing Transmitter circuits may not be used. In other embodiments, Mode-B testing only is used. In an embodiment, the Test System is configured to test a plurality of Receivers using a single Testing Transmitter (in some cases, a fiber-optic splitter may be needed).

[0057] In embodiments, the communication system is not necessarily optical - various suitable communication systems, wired and wireless, electrical, electro-magnetic or optical, can be used.

[0058] Fig. 2 is a block diagram that schematically illustrates a Mode-A Configured OIF 800ZR Testing Transmitter 200, in accordance with an embodiment of the present invention. According to the OIF specifications, the Transmitter comprises:

[0059] 1. A CRC circuit 202, which receives the input sequence and adds a 32-bit CRC code to groups of input bits;

[0060] 2. a Padding / Scrambling circuit 204, which receives the CRC circuit output, adds fixed- value padding bits and then scrambles that data;

[0061] 3. an FEC-Encoder 206, which adds forward error-correction code to the input that Padding / Scrambling circuit 204 outputs, and generates an unterminated FEC code, 4. an Interleaver 208, which interleaves the untemiinated FEC code that FEC-encoder 206 outputs;

[0062] 5. a Mapping circuit 210, which maps the output of interleaver 208 to symbols; and

[0063] 6. a Sync / Pilot circuit 212, which adds sync, pilot and other auxiliary signals to the output of Mapping Circuit 210.

[0064] For Mode-A testing, the connection between Interleaver 208 and Mapping Circuit 210 is disconnected (for example, by setting configuration switch 1 16, Fig. 1 to Mode-A), and a Truncated-PRBS generator circuit sends a periodic truncated PRBS to the input of the Mapping Circuit, As explained above, the period length of the Truncated-PRBS i s an integer number of super-frames. A suitable circuit is added to the RUT, to check for errors in the periodic Truncated-PRB S sequence.

[0065] Fig. 3 is a block diagram that schematically illustrates a Mode-B Configured OIF 400ZR Testing Transmitter 300, in accordance with an embodiment of the present invention. According to the OIF specifications, the Transmitter comprises:

[0066] 1. a CRC circuit 302, which receives the input sequence and adds a 32-bit CRC code to groups of input bits;

[0067] 2. an Error Decorrelator Interleaver (EDI) Circuit 304, which modifies the output of CRC circuit 302 to reduce possible correlation of the errors.

[0068] 3. A multi block alignment signal (MBAS) circuit 306, which counts super-frames (the contents of MB AS 306 is input to EDI circuit. 304);

[0069] 4. an FEC-Encoder 308, which receives the output of EDI circuit 304 and adds forward error-correction bits and generates an unterminated FEC output code;

[0070] 5. a State register 310, which temporarily stores the state of FEC Encoder 308,

[0071] 6. an Error-Decorrelator-Deinterleaver (EDD) / Hamming circuit 312, which receives the unterminated FEC code of FEC-Encoder 308 and preforms inverse decorrelation on the parity bits.

[0072] 7. a Mapper / In terleaver circuit 314, which receives the output of EDD / Hamming circuit 314, maps the data into symbols and interleaves the symbols; and

[0073] 8. a Sync / Pilot circuit 316, which adds sync signals according to sub-frames, adds pilot signals and adds other auxiliary signals to the output of Mapper / Interl eaver circuit 314,

[0074] For Mode-B testing, an FEC-Cyclic Sequence Generator 318, which is connected to the input of CRC circuit 302, generates the input sequence of the testing transmitter. In addition, MBAS circuit is modified so as to wrap the super-frame count to zero upon reaching the number of super-frames in a testing period.

[0075] As explained above, the periodic input sequence is FEC -cyclic, so that, at the beginning of all periods, the state of State 310 is the same.

[0076] GENERATING AN FEC-CYCLIC PATTERN

[0077] A periodic testing signal that is also a valid FEC codeword cannot be generated by the retransmission of any periodic sequences, comprising an integer number of super-frames, because in the seam between two repeated sequences the individual BCH codeword will not be valid codewords. In embodiments, sequence is built so that, when repeated, all BCH codewords will be valid. A technique to build such “FEC -cyclic” sequence is outlined below.

[0078] First, we note that the state of the BCH encoder can be described by a finite number of bits, representing the syndromes or partial parities of the BCH codewords that are not fully coded. Let us denote the size of the state as n.

[0079] The code is a linear code, so the encoder is a binary linear system. For a fixed number of input bits, k, (e.g., the length of the sequence) we can find matrices A,B,C,D such that:

[0080] Where: state is the state of the encoder at the beginning of the encoding segment. state'is the state of the encoder at the end of the encoding segment. inp is the input data to the encoder. out is the output of the encoder.

[0081] The condition of periodicity is achieved by adding the extra condition:

[0082] These equations can be solved to find multiple solutions for state and inp. We will prefer higher entropy solutions (the trivial solution of 0 may be less useful). Note that, in embodiments, more than one solution can be used, for a wider diversity of tests.

[0083] In typical communication standards, the input data is modified prior to the FEC coding - for example, a CRC code is added to the data, and, sometimes, the data is scrambled. The effect of those modifications is usually (e.g., in ZR 800) a linear operation on the output plus a fixed value:

[0084] In this new set of equations, the size of the input has been changed from k to k' and the factors E and F have been added. By solving these overdetennined equations we can find the state and input that will result in a periodic valid signal out.

[0085] A solution to the equation exists, depending on the properties of the matrices A, B, and E. The equations can be modified by changing the period to one or more super-frames. Ordinary' mathematical techniques can be used to find a solution to the equations (if a solution exits):

[0086] This can be written in matrix form:

[0087] A solution exists if Enis in the subspace spanned by the columns of X.

[0088] Fig. 4 is a flowchart 400 that schematically illustrates a method for creating a valid FEC- cyclic test sequence in accordance with an embodiment of the present invention. The flowchart is typically executed off-line by a suitable computer software program (“SW” hereinbelow) using a simulation model of the Transmitter, and the created testing sequence is loaded to the FEC-Cyclic Sequence Generator 124 of Testing Transmitter 102 (Fig. 1).

[0089] For brevity, we will refer below to the sequence of input data bits as D, to the FEC state as S, to state and input data as S / D, and to single — set-bit words (for both FEC states and the input data) as SSB.

[0090] The flowchart starts at a Reset-S / D operation 402, wherein the SW sets the state and the input data to zero. Next, at an Apply-Encoder operation 404, the SW runs the transmitter simulation, starting with the all -zero state and with an all-zero input data, to generate the vector E (defined above). The SW saves the E vector, which will be used in further operations.

[0091] The SW now enters a Reset-S / D-and-Bit-Pointer operation 406, wherein the SW sets the state and the input data to zero, and sets a bit-pointer variable, which points to bits of the encoder state, to zero. Next, at a Generate-SSB-State operation 408, the SW generates an encoder state in which the bit pointed to by the bit-pointer is at binary- 1, and all other bits are binary-0.

[0092] The SW now, at an Apply-Encoder operation 410, runs the Transmitter simulation to encode the all-zero input data sequence with the initial input states that w'ere set in operation 408. The SW saves the post-simulation states for each initial state in memory, and proceeds to a XOR-Matrix-Column operation 412, in which each encoding result A_i is XORed with matrix E (derived in operation 404), to obtain the A i + E.

[0093] Now, in a Check-Last-Bit-Pointer operation 414, the SW checks whether the bit-pointer is pointing at the last state bit (for example, for an 8-bit state, the SW checks whether the bitpointer equals binary -10000000). If the bit pointer has not reached the last state bit, the SW enters an Increment-Bit-Pointer operation 416, increments the bit-pointer to point to the next state bit, and then reenters operation 408, to generate the next SSB state.

[0094] If, in operation 414, the bit-pointer is pointing at the last state bit, the SW will enter a Reset-S / D-and-Bit-Pointer operation 418, wherein the SW sets the state and the input bits to zero, and sets a bit-pointer variable, which points to bits of the input data, to zero. Next, at a Generate-SSB-Input operation 420, the SW generates an input data sequence in which the input data bit pointed to by the bit-pointer is at binary-1, and all other bits are binary-0.

[0095] The SW now, at an Apply-Encoder operation 422, runs the Transmitter simulation to encode the SSB input sequence, starting from an all-zero state, and with the input data as set in operation 420. The SW saves the post-simulation states for each SSB input data in memory and proceeds to a XOR-Matrix-Column operation 424, in which the encoding result B i is XORed with matrix E (derived in operation 404), to obtain Bi+E.

[0096] Now, in Check-Last-Bit-Pointer operation 426, the SW checks whether the bit-pointer is pointing at the last sequence bit. If the bit pointer has not reached the last sequence bit, the SW enters an Increment-Bit-Pointer operation 428, increments the bit-pointer to point to the next data bit and then reenters operation 420, to generate the next data SSB.

[0097] If, in operation 426, the bit-pointer is pointing at the last input data sequence bit, the SW will enter a Find-Matrix-A operation 430, wherein the SW performs a XOR operation of the post-simulation states saved in operation 410 with the matrix E, to find the matrix A. Similarly, at a following Find-Matrix-B operation 432, the SW performs a XOR operation of the postsimulation states saved in operation 422 with the matrix E, to find the matrix B.

[0098] Now, at a Find-Solution operation 434, the SW finds a solution of the non-homogeneous overdetermined linear equation system s=As+Binp+E, which has many solutions. The solutions can be found using, for example, Gaussian Elimination or other methods known in the art.

[0099] The SW may optionally enter a Find Output operation 436, wherein the testing transmitter is simulated with the calculated input, and the generated output is stored. In embodiments, the stored output may be used in a simplified testing transmitter that includes the PHY only. The method described above creates a periodic test signal for communication standards such as OIF ZR800, OpenZR + and OpenroadM. The created test signal will have valid CRC and FEC codewords, allowing direct BER measurement by monitoring CRC errors. The relatively long period length will not affect BER measurements due to spikes at multiples of the sequence period.

[0100] For the OIF ZR400 standard, there is an additional synchronization signal (MBAS) that is incremented by one for every super-frame, wrapping-around to zero at 128. Consequently, sequences shorter than 128 super-frames will not be valid. In embodiments, the RUT is modified to support MBAS wrapping-around values that are less than 128; in an embodiment, the wraparound value is one super-frame; in other embodiments the value may be other integer numbers of super-frames, and, in yet other embodiments, the wrap-around value of the MBAS signal is programmable.

[0101] The method for finding an FEC-Cyclic input sequence illustrated in Fig. 4 and described herein above is cited by way of example. Other methods can be used in alternative embodiments. For example, in some embodiments, the Tester executes operations 418 through 428 prior to operations 406 through 416. In some embodiments, some operations may be run concurrently, e.g., on a multi-core processor.

[0102] Fig. 5 A is a flowchart 500 that schematically illustrates a method for the testing of a communication RUT in a first testing mode, in accordance with an embodiment of the present invention. The flowchart is executed by testing hardware and software (referred to as the Tester). The tested RUT will be referred to as Receiver Under Test (RUT).

[0103] The flowchart starts at a Generate-Periodic-PRBS operation 502, wherein the Tester generates a periodic test sequence by truncating a PRBS sequence to an integer number of superframes. Next, at a Send-Sequence-to-Modulator operation 504, the Tester sends the periodic test sequence to the modulator part, of a. communication transmitter that, is compatible with the communication receiver under test, bypassing the Encoder part of the Transmitter. In some embodiments, the Encoder part of the transmitter comprises CRC generation, Padding, Scrambling, FEC-encoding and Interleaving, and the Encoder part of the Transmitter may comprise Mapping and the addition of Sync and Pilot symbols.

[0104] Next, at a Send-Transmitter-Output operation 506, the Tester sends the output of the transmitter, over a suitable medium (e.g., fiber-optics) to the RUT. In embodiments, the Tester may inject errors in various transmitter stages and / or in the medium, for testing purposes. Lastly, in a Compare-Outputs operation 508, the Tester compares the output of the demodulator part of the RUT to the periodic Truncated-PRBS sequence of operation 502. In embodiment, such comparison is done by circuitry' that is added to the RUT.

[0105] Fig. 5B is a flowchart 550 that schematically illustrates a method for the testing of a communication receiver in a second testing mode, in accordance with an embodiment of the present invention. The flowchart is executed by testing hardware and software (referred to as the Tester). The tested receiver will be referred to as Receiver Under Test (RUT).

[0106] The flowchart starts at an optional Modify MBAS operation 552, wherein the Tester modifies the Multi Block Alignment Signal (MBAS) circuit of the RUT to reset according to the size of the testing sequence (as was described above, with reference to Fig. 4). This operation is optional, and is needed in communication systems that comprise an MBAS, e.g., 400ZR.

[0107] Next, at a Generate-FEC-Cyclic-Sequence operation 554, the Tester generates a test sequence that is cyclic, having a period length that is an integer number of super-frames, and resulting in a cyclic operation of the Transmitter FEC encoder and, hence, a cyclic output from the Transmitter (a method to find an FEC-cyclic test sequence has been described above, with reference to Fig. 4).

[0108] Now', at a Send-Sequence-to-Tester operation 556, the Tester sends the periodic test sequence to a communication transmitter, which will, responsively, generate a cyclic transmission signal. Nov,', at a Send-Transmitter-Output operation 558, the Tester sends the output of the transmitter, over a suitable medium (e.g., fiber-optics) to the RUT. In embodiments, the tester may inject errors in various transmitter stages and / or in the medium, for testing purposes.

[0109] Lastly, at a Count CRC Errors operation 560, the Tester observes CRC errors that the RUT outputs, to assess the operation of the RUT.

[0110] EXTENTION TO NON-PEROIDIC TEST SEQUENCES

[0111] In some embodiments, the techniques described above may be used for non-periodic tests. For example, in the 800ZR specifications, the equations disclosed above can be used to send data, ensuring that the state of the encoder at the end of the super-frame is known. This can eliminate the initial sync phase of the decoder during which the initial state is not known, and the input stream cannot be decoded until enough bits have been received. In an embodiment, initial transmission can use some of the data bits to make sure the final or initial states are zero.

[0112] The apparatuses and methods described hereinabove, with reference to Figs. 1 through 5B, including all units and subunits thereof, are example configurations and methods that, are shown purely for the sake of conceptual clarity. Any other suitable methods and configurations can be used in alternative embodiments. For example, in embodiments, a combination of Mode- A and Mode-B testing can be used.

[0113] In various embodiments, Testing Transmitter 102 and Receiver 106, including subunits thereof, may be implemented using suitable hardware, such as one or more Application-Specific Integrated Circuits (ASIC) or Field-Programmable Gate Arrays (FPGA), or a combination of ASIC and FPGA.

[0114] It will thus be appreciated that the embodiments described above are cited by way of example, and that, the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which w'ould occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integer part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Claims

CLAIMS1. A system, comprising: a testing transmiter, comprising: a Pseudo-Random Bit Sequence (PRBS) generator, configured to generate a PRBS; and a signal generation circuit, configured to generate a test signal that comprises repetitions of a truncated portion of the PRBS, such that a period of the repetitions is shorter than the period of the PRBS.

2. The system according to claim 1, wherein, in generating the test signal, the signal generation circuit is configured to generate a sequence of packets comprising (i) the repetitions of the truncated portion of the PRBS seiwing as payloads, and (ii) additional symbols.

3. The system according to claim 1 or 2, further comprising: receiver circuitry configured to receive and decode the test signal; and a test circuit, configured to generate a reference signal that is identical to the repetitions of the truncated portion of the PRBS, and to evaluate a performance of the receiver circuitry by comparing the reference signal to the test signal decoded by the receiver circuitry.

4. The svstem according to claim 3. wherein the test circuit in the receiver is configured to generate the reference signal that comprises repetitions of the truncated portion of the PRBS.

5. The system according to claim 3, wherein: the test signal generated by the transmitter comprises additional symbols interleaved between the repetitions of the truncated portion of the PRBS; and the test circuit in the receiver is configured to omit the additional symbols from comparison to the reference signal.

6. A test tran sm i tter, com pri si ng : an encoder, configured to encode an input data sequence with an unterminated Forward Error Correction (FEC) code; and a test sequence generation circuit, configured to generate a periodic FEC-cyclic test sequence of a preset period length that, when encoded repeatedly by the encoder, forms a valid unterminated encoded data stream in accordance with the FEC code.

7. The test transmitter according to claim 6, wherein each period of the FEC-cyclic test sequence begins at a same state of the encoder.

8. The test transmitter according to claim 6 or 7, wherein the test sequence generation circuit is configured to insert Cyclic Redundancy Check (CRC) codes within the FEC -cyclic test sequence.

9. A method for test signal generation, comprising: generating a Pseudo-Random Bit Sequence (PRBS); and generating a test signal that comprises repetitions of a truncated portion of the PRBS, such that a period of the repetitions is shorter than the period of the PRBS.

10. The method according to claim 9, wherein generating the test signal comprises generating a sequence of packets comprising (i) the repetitions of the truncated portion of the PRBS serving as payloads, and (ii) additional symbols.1 1. The method according to claim 9 or 10, further comprising, in a receiver being tested: receiving and decode the test signal; generating a reference signal that i s identical to the repetitions of the truncated portion of the PRBS; and evaluating a performance of receiver circuitry by comparing the reference signal to the test signal decoded by the receiver.

12. The method according to claim 11, wherein generating the reference signal comprises generating repetitions of the truncated portion of the PRBS.

13. The method according to claim 1 1, wherein: the test signal comprises additional symbols interleaved between the repetitions of the truncated portion of the PRBS, and comparing the reference signal comprises omitting the additional symbols from comparison to the reference signal.

14. A method for test signal generation, comprising: operating an encoder that encodes an input data sequence with an unterminated Forward Error Correction (FEC) code; and generating a periodic FEC-cyclic test sequence of a preset period length that, when encoded repeatedly by the encoder, forms a valid unterminated encoded data stream in accordance with the FEC code.

15. The method according to claim 14, wherein each period of the FEC-cyclic test sequence begins at a same state of the encoder.

16. The method according to claim 14 or 15, wherein generating the FEC-cyclic test sequence comprises inserting Cyclic Redundancy Check (CRC) codes within the FEC-cyclic test sequence.

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