Turn-on control circuit, display panel, and display device

Abstract

Embodiments of the present disclosure provide a turn-on control circuit, a display panel, and a display device. The turn-on control circuit comprises: a gating control circuit coupled to a first node and configured to provide a signal of a first clock signal end to the first node in response to signals of a plurality of different gating control signal ends; a control circuit coupled to the first node and a second node and configured to provide the signal of the first clock signal end or a signal of a first power supply end to the second node in response to a signal of the first node; and a turn-on signal output circuit coupled to the second node and a third node and configured to provide a signal of a second clock signal end to a driving output end in response to a signal of the second node, and provide a signal of a first reference signal end to the driving output end in response to a signal of the third node.

Description

Conduction control circuit, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a conduction control circuit, a display panel, and a display device. Background Art

[0002] With the advent of the 5G era, display devices will inevitably become the terminal outlets for the Internet of Everything. However, outdated, single display modes no longer meet people's needs. As people's living standards improve, the requirements for gaming display devices are becoming increasingly stringent. Currently, regional high-refresh technology is the only option that is compatible with high dynamic range image quality and low data transmission rates. To achieve regional high-refresh technology, it is necessary to add partitions to the pixel design in both the column and horizontal directions of the display panel, which requires the addition of a large number of common signal lines, which greatly occupies space, increases costs, and lacks intelligent adjustment capabilities.

[0003] Summary of the Invention

[0004] The conduction control circuit provided by the embodiment of the present disclosure includes:

[0005] a gating control circuit coupled to the first node and configured to provide a signal from a first clock signal terminal to the first node in response to signals from a plurality of different gating control signal terminals;

[0006] a control circuit coupled to the first node and the second node, and configured to provide a signal from the first clock signal terminal or a signal from the first power supply terminal to the second node in response to a signal from the first node;

[0007] The conduction signal output circuit is coupled to the second node and the third node, and is configured to provide the signal of the second clock signal terminal to the driving output terminal in response to the signal of the second node, and to provide the signal of the first reference signal terminal to the driving output terminal in response to the signal of the third node.

[0008] In some possible implementations, the gating control circuit includes: N gating control transistors;

[0009] The N gate control transistors correspond one-to-one to the multiple different gate control signal terminals;

[0010] The gate of the nth gate control transistor among the N gate control transistors is coupled to the corresponding gate control signal terminal;

[0011] A first electrode of the first gate control transistor among the N gate control transistors is coupled to the first clock signal terminal;

[0012] A second electrode of the Nth gate control transistor among the N gate control transistors is coupled to the first node;

[0013] The second electrode of the nth transistor among the N gate control transistors is coupled to the first electrode of the (n+1)th transistor among the N gate control transistors.

[0014] In some possible implementations, the control circuit includes:

[0015] a first control circuit configured to provide the signal of the first clock signal terminal to the first node in response to the signal of the reset signal terminal;

[0016] The second control circuit is configured to provide the signal of the first clock signal terminal or the signal of the first power supply terminal to the second node in response to the signal of the first clock signal terminal and the signal of the first node.

[0017] In some possible implementations, the first control circuit includes: a first transistor;

[0018] A gate of the first transistor is coupled to the reset signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the first clock signal terminal.

[0019] In some possible implementations, the second control circuit includes: a second transistor and a third transistor;

[0020] The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first clock signal terminal or the first power supply terminal, and the second electrode of the second transistor is coupled to the first electrode of the third transistor;

[0021] A gate of the third transistor is coupled to the first clock signal terminal, and a second electrode of the third transistor is coupled to the second node.

[0022] In some possible implementations, the second control circuit further includes: a first capacitor;

[0023] A first electrode of the first capacitor is coupled to the first power supply terminal, and a second electrode of the first capacitor is coupled to the first node.

[0024] In some possible implementations, the conduction signal output circuit includes: a first conduction transistor, a second conduction transistor, and a second capacitor;

[0025] The gate of the first pass transistor is coupled to the second node, the first electrode of the first pass transistor is coupled to the second clock signal terminal, and the second electrode of the first pass transistor is coupled to the driving output terminal;

[0026] The gate of the second pass transistor is coupled to the third node, the first electrode of the second pass transistor is coupled to the driving output terminal, and the second electrode of the second pass transistor is coupled to the first reference signal terminal;

[0027] A first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the driving output terminal.

[0028] In some possible implementations, the further embodiment includes: a reset circuit configured to provide the signal of the reset signal terminal or the signal of the first power supply terminal to the third node in response to the signal of the reset signal terminal.

[0029] In some possible implementations, the reset circuit includes: a fourth transistor and a third capacitor;

[0030] The gate of the fourth transistor is coupled to the reset signal terminal, the first electrode of the fourth transistor is coupled to the reset signal terminal or the first power supply terminal, and the second electrode of the fourth transistor is coupled to the third node;

[0031] A first electrode of the third capacitor is coupled to the second electrodes of the four transistors, and a second electrode of the third capacitor is coupled to the first reference signal terminal or the second reference signal terminal.

[0032] In some possible implementations, the system further includes: a third control circuit configured to control a signal of the third node in response to signals of the first node and the third node.

[0033] In some possible implementations, the third control circuit includes: a fifth transistor, a sixth transistor, and a seventh transistor;

[0034] The gate of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the reset signal terminal;

[0035] The gate of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the reset signal terminal;

[0036] A gate of the seventh transistor is coupled to the third node, a first electrode of the seventh transistor is coupled to the second node, and a second electrode of the seventh transistor is coupled to the first reference signal terminal.

[0037] In some possible implementations, the system further includes: a fourth control circuit configured to control the signal of the third node in response to signals of the first node, the second node, and the third node.

[0038] In some possible implementations, the fourth control circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

[0039] The gate of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the third node, and the second electrode of the eighth transistor is coupled to the second electrode of the ninth transistor;

[0040] The gate of the ninth transistor is coupled to the third node, and the first electrode of the ninth transistor is coupled to the first power supply terminal;

[0041] The gate of the tenth transistor is coupled to the second node, the first electrode of the tenth transistor is coupled to the reset signal terminal, and the second electrode of the tenth transistor is coupled to the second electrode of the ninth transistor;

[0042] A gate of the eleventh transistor is coupled to the second node, a first electrode of the eleventh transistor is coupled to the second electrode of the tenth transistor, and a second electrode of the eleventh transistor is coupled to the third node.

[0043] In some possible implementations, the system further includes: a fifth control circuit configured to control the signal of the second node in response to the signal of the third node.

[0044] In some possible implementations, the fifth control circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor;

[0045] The gate of the twelfth transistor is coupled to the third node, the first electrode of the twelfth transistor is coupled to the first electrode of the third transistor, and the second electrode of the twelfth transistor is coupled to the second electrode of the thirteenth transistor;

[0046] The gate of the thirteenth transistor is coupled to the second node, and the first electrode of the thirteenth transistor is coupled to the first power supply terminal;

[0047] The gate of the fourteenth transistor is coupled to the third node, the first electrode of the fourteenth transistor is coupled to the second reference signal terminal, and the second electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor;

[0048] A gate of the fifteenth transistor is coupled to the third node, a first electrode of the fifteenth transistor is coupled to a second electrode of the fourteenth transistor, and a second electrode of the fifteenth transistor is coupled to the second node.

[0049] In some possible implementations, the system further includes: a sixth control circuit configured to control the signal of the third node in response to signals of the first node, the third node, and the second power supply terminal.

[0050] In some possible implementations, the sixth control circuit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor;

[0051] The gate of the sixteenth transistor is coupled to the second node, the first electrode of the sixteenth transistor is coupled to the third reference signal terminal, and the second electrode of the sixteenth transistor is coupled to the first electrode of the seventeenth transistor;

[0052] The gate of the seventeenth transistor is coupled to the second power supply terminal, and the second electrode of the seventeenth transistor is coupled to the second power supply terminal;

[0053] The gate of the eighteenth transistor is coupled to the first electrode of the seventeenth transistor, the first electrode of the eighteenth transistor is coupled to the third node, and the second electrode of the eighteenth transistor is coupled to the second power supply terminal;

[0054] The gate of the nineteenth transistor is coupled to the first node, the first electrode of the nineteenth transistor is coupled to the first electrode of the eighteenth transistor, and the second electrode of the nineteenth transistor is coupled to the second reference signal terminal;

[0055] A gate of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the third node, and a second electrode of the twentieth transistor is coupled to the second reference signal terminal.

[0056] In some possible implementations, the system further includes: a seventh control circuit configured to control the signal of the second node in response to signals of the second node, the third node, and the reset signal terminal.

[0057] In some possible implementations, the seventh control circuit includes: a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-fifth transistor;

[0058] The gate of the twenty-first transistor is coupled to the third node, the first electrode of the twenty-first transistor is coupled to the second reference signal terminal, and the second electrode of the twenty-first transistor is coupled to the first electrode of the twenty-second transistor;

[0059] A gate of the twenty-second transistor is coupled to the third node, and a second electrode of the twenty-second transistor is coupled to the second node;

[0060] a gate of the twenty-third transistor coupled to the second node, a first electrode of the twenty-third transistor coupled to the first power supply terminal, and a second electrode of the twenty-third transistor coupled to the first electrode of the twenty-second transistor;

[0061] A gate of the twenty-fourth transistor is coupled to the reset signal terminal, a first electrode of the twenty-fourth transistor is coupled to the second reference signal terminal, and a second electrode of the twenty-fourth transistor is coupled to the first electrode of the twenty-second transistor;

[0062] A gate of the 25th transistor is coupled to the reset signal terminal, a first electrode of the 25th transistor is coupled to a second electrode of the 24th transistor, and a second electrode of the 25th transistor is coupled to the second node.

[0063] The display panel provided by the embodiment of the present disclosure includes: a display area and a non-display area;

[0064] The display area includes: a plurality of sub-pixels, each of the plurality of sub-pixels including a pixel circuit;

[0065] The non-display area includes:

[0066] A timing controller configured to provide a plurality of strobe control signals;

[0067] Multiple of the above-mentioned conduction control circuits are coupled to the timing controller and the pixel circuit, and the multiple selection control signal terminals are used to receive the multiple selection control signals. The conduction control circuit is configured to provide the signal of the driving output terminal to the pixel circuit in response to the multiple selection control signals provided by the timing controller.

[0068] In some possible implementations, the display area further includes: a plurality of conduction signal lines, wherein the pixel circuits in a column of sub-pixels are coupled to one of the conduction signal lines;

[0069] One of the conduction signal lines is coupled to a driving output terminal of the conduction control circuit.

[0070] In some possible implementations, the non-display area further includes:

[0071] The data driving circuit is coupled to the pixel circuit and the timing controller, and is configured to provide a data signal to the pixel circuit in response to a data signal output by the timing controller.

[0072] In some possible implementations, the plurality of conduction control circuits are located between the data driving circuit and the display area.

[0073] In some possible implementations, the plurality of conduction control circuits are located on a side of the display area away from the data driving circuit.

[0074] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] FIG1 is a schematic diagram of some structures of a display panel provided by an embodiment of the present disclosure;

[0076] FIG2 is a schematic diagram of another structure of a display panel provided by an embodiment of the present disclosure;

[0077] FIG3 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0078] FIG4 is a schematic diagram of some structures of pixel circuits provided by an embodiment of the present disclosure;

[0079] FIG5 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0080] FIG6 is a schematic diagram of some structures of a conduction control circuit provided by an embodiment of the present disclosure;

[0081] FIG7 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0082] FIG8 is another signal timing diagram provided by an embodiment of the present disclosure;

[0083] FIG9 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0084] FIG10 is another schematic diagram of the structure of the conduction control circuit provided by an embodiment of the present disclosure;

[0085] FIG11 is a schematic diagram of some further structures of the conduction control circuit provided in an embodiment of the present disclosure;

[0086] FIG12 is a schematic diagram of some further structures of the conduction control circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0087] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0088] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0089] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0090] In some embodiments of the present disclosure, as shown in FIG1 , the display panel may include a display area AA and a non-display area BB. The display area AA may include a plurality of pixels. Each pixel may include a plurality of sub-pixels SPX. For example, the pixel may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display. Alternatively, the pixel may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel can be designed and determined according to the actual application environment, and is not limited here.

[0091] In some embodiments of the present disclosure, as shown in FIG1 , the display area AA may include multiple gate lines GA and multiple data lines DA. Each sub-pixel may include a transistor and a pixel electrode. In the display panel, the normal display of the display area AA is controlled by both the gate line GA and the data line DA. The gate line GA is used to transmit a scanning signal that controls the switching of the transistors in the pixel. The data line DA transmits the data signal required for pixel display. A row of sub-pixels SPX1 corresponds to a gate line GA, and a column of sub-pixels SPX1 corresponds to a data line DA. The gate of the transistor is coupled to the corresponding gate line, the first electrode of the transistor is coupled to the corresponding data line, and the second electrode of the transistor is coupled to the pixel electrode. It should be noted that the pixel structure of the present disclosure may also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of sub-pixels SPX. This arrangement can reduce the number of data lines by half, that is, some data lines are included between two adjacent columns of sub-pixels SPX, and some data lines are not included between two adjacent columns of sub-pixels SPX. The specific sub-pixel arrangement structure and the arrangement of data lines and gate lines are not limited.

[0092] In some embodiments of the present disclosure, as shown in FIG1 , the array substrate gate drive technology (Gate Driver on Array, GOA) is to integrate the gate drive circuit 500 on the array substrate of the display panel to realize a line-by-line scanning drive mode, thereby eliminating the gate drive circuit part, which has the advantages of reducing production costs and realizing a narrow frame design of the panel, and is used by a variety of displays. The non-display area BB may include a gate drive circuit 500 and a data drive circuit (arranged on the circuit board in FIG1 ). The gate drive circuit 500 is coupled to the gate line GA, and the data drive circuit is coupled to the data line DA, respectively. In addition, the timing controller can be coupled to the gate drive circuit 500 and the data drive circuit (arranged on the circuit board in FIG1 ), respectively. Generally, the gate drive circuit 500 is arranged in the non-display area BB on the left and right sides of the display panel. For example, the timing controller 200 can obtain display data of a picture to be displayed in the current display frame, and the timing controller 200 can input a control signal to the gate driving circuit 500 so that the gate driving circuit 500 can output a gate scanning signal to each gate line according to the input control signal, thereby driving each gate line to control the conduction of the transistors in the coupled sub-pixels. In addition, the timing controller 200 inputs the obtained display data to the data driving circuit so that the data driving circuit can input a data signal to the coupled data line DA according to the input display data, thereby inputting the voltage on the data line DA into the sub-pixel through the turned-on transistor to charge the sub-pixel SPX, thereby charging each sub-pixel SPX with the corresponding data signal, thereby realizing the picture display function.

[0093] For example, as shown in FIG1 , in order to realize the regional high refresh technology, it is necessary to add a partition design to the sub-pixel SPX in both the column and lateral directions. For example, the gate drive circuit 500 is divided into 6 areas (such as GOA1, GOA2, GOA3, GOA4, GOA5, and GOA6 in FIG1 ), and the sub-pixel SPX is divided into i column areas. Each column of sub-pixels SPX1 needs to receive the control of the signal of the timing controller through a common signal line (such as Com_1, Com_2, Com_3, Com_4, Com_i-3, Com_i-2, Com_i-1, and Com_i in FIG1 ). For example, if the sub-pixel SPX is divided into 4096 column areas, 4096 common signal lines are required. It can be seen that a large number of common signal lines need to be added, which greatly takes up space, increases costs, and does not have the ability to intelligently adjust pixels.

[0094] In view of the above problems, the display panel provided by the embodiment of the present disclosure, as shown in FIG2 , includes:

[0095] The display area AA includes: a plurality of sub-pixels SPX, each of the plurality of sub-pixels SPX includes a pixel circuit 100;

[0096] The non-display area BB includes:

[0097] The timing controller 200 is configured to provide a plurality of gating control signals;

[0098] Multiple conduction control circuits 300 are coupled to the timing controller 200 and the pixel circuit 100, and multiple strobe control signal terminals are used to receive multiple strobe control signals. The conduction control circuit 300 is configured to provide the signal of the driving output terminal OT to the pixel circuit 100 in response to the multiple strobe control signals provided by the timing controller 100.

[0099] The present disclosure provides multiple strobe control signal terminals to receive multiple strobe control signals, enabling the conduction control circuit to respond to the multiple strobe control signals provided by the timing controller and provide the signal from the drive output terminal to the pixel circuit. This configuration allows the pixel circuit to be controlled by controlling the strobe control signals of the conduction control circuit, thereby flexibly controlling the number of sub-pixel partitions. This significantly reduces the number of signals required for the pixel circuit to operate, saves space occupied by signal lines, reduces costs, and also provides intelligent adjustment capabilities.

[0100] In some embodiments of the present disclosure, as shown in Figures 2 and 3, the display area AA also includes: multiple conduction signal lines (for example, SA in Figure 2), the pixel circuit 100 in a column of sub-pixels SPX is coupled to a conduction signal line (for example, SA in Figure 2); and a conduction signal line (for example, SA-1, SA-2, SA-3 in Figure 3) is coupled to the driving output terminal OT of a conduction control circuit (for example, 300-1, 300-2, 300-3 in Figure 3).

[0101] In some embodiments of the present disclosure, as shown in FIG. 2 , the non-display area BB further includes: a data driving circuit 400 coupled to the pixel circuit 100 and the timing controller 200 , and configured to provide a data signal to the pixel circuit 100 in response to a data signal output by the timing controller 200 .

[0102] In some embodiments of the present disclosure, as shown in FIG. 2 , a plurality of conduction control circuits 300 are located between the data driving circuit 400 and the display area AA.

[0103] For example, as shown in FIG4 , the pixel circuit structure diagram includes: a driving transistor T0, a light-emitting device L, a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, a fourth switching transistor T4, and a voltage-stabilizing capacitor C0; wherein, the gate of the driving transistor T0 is coupled to the second electrode of the first switching transistor T1, the first electrode of the driving transistor T0 is coupled to the first power supply voltage terminal VDD, and the second electrode of the driving transistor T0 is coupled to the light-emitting device L; the gate of the first switching transistor T1 is coupled to the conduction control signal terminal Gc-n, the first electrode of the first switching transistor T1 is coupled to the second electrode of the second switching transistor T2; The gate of the second switching transistor T2 is coupled to the gate scan signal terminal Gate_n, and the first electrode of the second switching transistor T2 is coupled to the data signal terminal Data; the gate of the third switching transistor T3 is coupled to the gate scan signal terminal Gate_n, the first electrode of the third switching transistor T3 is coupled to the second electrode of the voltage-stabilizing capacitor C0, and the second electrode of the third switching transistor T3 is coupled to the second electrode of the fourth switching transistor T4; the gate of the fourth switching transistor T4 is coupled to the gate conduction control signal terminal Gc-n, and the first electrode of the fourth switching transistor T4 is coupled to the scan signal terminal Scan; the first electrode of the voltage-stabilizing capacitor C0 is coupled to the gate of the driving transistor T0. In the embodiment of the present disclosure, the first electrode of the light-emitting device L can be its anode, and the second electrode can be its cathode. Exemplarily, the light-emitting device L can be an organic light-emitting diode. For example, the light-emitting device L can include: at least one of a micro light-emitting diode (Micro LED), an organic light-emitting diode (OLED), and a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED). For example, the light-emitting device L may include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer may include layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In practical applications, the specific structure of the light-emitting device L can be designed and determined based on the actual application environment and is not limited here.

[0104] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0105] Generally, transistors using low-temperature polysilicon (LTPS) as active layers have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, thereby achieving high mobility in the pixel circuit, and allowing it to be made thinner and smaller, with lower power consumption.

[0106] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, to reduce leakage current, in some embodiments of the present disclosure, the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0107] For example, all transistors may be configured as LTPS transistors, or all transistors may be configured as oxide transistors, or some transistors may be configured as oxide transistors and the remaining transistors may be configured as LTPS transistors.

[0108] The present disclosure provides further structural diagrams of display panels, as shown in Figure 5 , which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0109] In some embodiments of the present disclosure, as shown in FIG. 5 , the plurality of conduction control circuits 300 are located on a side of the display area AA away from the data driving circuit 400 .

[0110] The present disclosure arranges the conduction control circuit on one side of the circuit board, thereby ensuring that the frame close to the side of the circuit board is not affected.

[0111] The conduction control circuit provided by the embodiment of the present disclosure, as shown in FIG6 , includes:

[0112] The gating control circuit 10 is coupled to the first node N1 and is configured to provide a signal of the first clock signal terminal CLK1 to the first node N1 in response to signals of a plurality of different gating control signal terminals;

[0113] The control circuit 20 is coupled to the first node N1 and the second node N2 and is configured to provide the signal of the first clock signal terminal CLK1 or the signal of the first power supply terminal VDD1 to the second node N2 in response to the signal of the first node N1;

[0114] The conduction signal output circuit 30 is coupled to the second node N2 and the third node N3, and is configured to provide the signal of the second clock signal terminal CLK2 to the driving output terminal OT in response to the signal of the second node N2, and to provide the signal of the first reference signal terminal VREF1 to the driving output terminal OT in response to the signal of the third node N3.

[0115] The disclosed embodiments control the signal at the driver output terminal through the interaction of a gating control circuit, a control circuit, and a conduction signal output circuit. Furthermore, the signals at multiple different gating control signal terminals are controlled to provide the signal at the first clock signal terminal to the first node. In other words, by controlling the signals at multiple different gating control signal terminals, the operation of the gating control circuit is controlled. This configuration saves space occupied by signal lines and reduces costs.

[0116] In some embodiments of the present disclosure, the gating control circuit includes: N gating control transistors; wherein the N gating control transistors correspond one-to-one to a plurality of different gating control signal terminals; the gate of the nth gating control transistor among the N gating control transistors is coupled to the corresponding gating control signal terminal; the first electrode of the 1st gating control transistor among the N gating control transistors is coupled to the first clock signal terminal; the second electrode of the Nth gating control transistor among the N gating control transistors is coupled to the first node; the second electrode of the nth transistor among the N gating control transistors is coupled to the first electrode of the n+1th transistor among the N gating control transistors.

[0117] Exemplarily, the gate control transistor can be turned on under the control of the active level of the gate control signal transmitted by the gate control signal terminal, and can be turned off under the control of the inactive level of the gate control signal. Exemplarily, if the gate control transistor is configured as a P-type transistor, the active level of the gate control signal is a low level, and the inactive level of the gate control signal is a high level. Alternatively, if the gate control transistor is configured as an N-type transistor, the active level of the gate control signal is a high level, and the inactive level of the gate control signal is a low level.

[0118] As shown in FIG6 , N=12 is used as an example for explanation. The gate control circuit 10 includes 12 gate control transistors, wherein the gate of the first gate control transistor M0_1 is coupled to the corresponding gate control signal terminal DC_1, the first electrode of the first gate control transistor M0_1 is coupled to the first clock signal terminal CLK1, and the second electrode of the first gate control transistor M0_1 is coupled to the first electrode of the second gate control transistor M0_2. The gate of the second gate control transistor M0_2 ​​is coupled to the corresponding gate control signal terminal DC_2, the second electrode of the second gate control transistor M0_2 ​​is coupled to the first electrode of the third gate control transistor M0_3. The gate of the third gate control transistor M0_3 is coupled to the corresponding gate control signal terminal DC_3, and the second electrode of the third gate control transistor M0_3 is coupled to the first electrode of the fourth gate control transistor M0_4. The gate of the fourth gate control transistor M0_4 is coupled to the corresponding gate control signal terminal DC_4, and the second electrode of the fourth gate control transistor M0_4 is coupled to the first electrode of the fifth gate control transistor M0_5. The gate of the fifth gate control transistor M0_5 is coupled to the corresponding gate control signal terminal DC_5, and the second electrode of the fifth gate control transistor M0_5 is coupled to the first electrode of the sixth gate control transistor M0_6. The gate of the sixth gate control transistor M0_6 is coupled to the corresponding gate control signal terminal DC_6, and the second electrode of the sixth gate control transistor M0_6 is coupled to the first electrode of the seventh gate control transistor M0_7. The gate of the seventh gate control transistor M0_7 is coupled to the corresponding gate control signal terminal DC_7, and the second electrode of the seventh gate control transistor M0_7 is coupled to the second electrode of the seventh gate control transistor M0_7. The gate of the eighth gate control transistor M0_8 is coupled to the corresponding gate control signal terminal DC_8, and the second electrode of the eighth gate control transistor M0_8 is coupled to the first electrode of the ninth gate control transistor M0_9. The gate of the ninth gate control transistor M0_9 is coupled to the corresponding gate control signal terminal DC_9, and the second electrode of the ninth gate control transistor M0_9 is coupled to the first electrode of the tenth gate control transistor M0_10. The gate of the tenth gate control transistor M0_10 is coupled to the corresponding gate control signal terminal DC_10, and the second electrode of the tenth gate control transistor M0_10 is coupled to the first electrode of the eleventh gate control transistor M0_11. The gate of the eleventh gate control transistor M0_11 is coupled to the corresponding gate control signal terminal DC_12, and the second electrode of the eleventh gate control transistor M0_11 is coupled to the first electrode of the twelfth gate control transistor M0_12. A gate electrode of the 12th gate control transistor M0_12 is coupled to the corresponding gate control signal terminal DC_12 , and a second electrode of the 12th gate control transistor M0_12 is coupled to the first node N1 .

[0119] For example, as shown in FIG3 , the display panel further includes: a reset signal line Re, a first clock signal line Clk1, a second clock signal line Clk2, a plurality of first selection signal lines Do1-Do12, and a plurality of second selection signal lines De1-De12; wherein the reset signal terminal RE is coupled to the timing controller via the reset signal line Re; the first clock signal terminal CLK1 is coupled to the timing controller via the first clock signal line Clk1; the second clock signal terminal CLK2 is coupled to the timing controller via the second clock signal line Clk2; the selection control signal terminal DC_1 is coupled to the timing controller via the first selection signal line The signal line Do1 or the second strobe signal line De1 is coupled to the timing controller; the strobe control signal terminal DC_1 is coupled to the timing controller through the first strobe signal line Do1 or the second strobe signal line De1; the strobe control signal terminal DC_2 is coupled to the timing controller through the first strobe signal line Do2 or the second strobe signal line De2; the strobe control signal terminal DC_3 is coupled to the timing controller through the first strobe signal line Do3 or the second strobe signal line De3; the strobe control signal terminal DC_4 is coupled to the timing controller through the first strobe signal line Do4 or the second strobe signal line De4; The strobe control signal terminal DC_5 is coupled to the timing controller through the first strobe signal line Do5 or the second strobe signal line De5; the strobe control signal terminal DC_6 is coupled to the timing controller through the first strobe signal line Do6 or the second strobe signal line De6; the strobe control signal terminal DC_7 is coupled to the timing controller through the first strobe signal line Do7 or the second strobe signal line De7; the strobe control signal terminal DC_8 is coupled to the timing controller through the first strobe signal line Do8 or the second strobe signal line De8; the strobe control signal terminal DC_9 is coupled to the timing controller through the first strobe signal line Do9 or the second strobe signal line The selection signal line De9 is coupled to the timing controller; the selection control signal terminal DC_10 is coupled to the timing controller through the first selection signal line Do10 or the second selection signal line De10; the selection control signal terminal DC_11 is coupled to the timing controller through the first selection signal line Do11 or the second selection signal line De11; the selection control signal terminal DC_1 is coupled to the timing controller through the first selection signal line Do1 or the second selection signal line De1; the selection control signal terminal DC_12 is coupled to the timing controller through the first selection signal line Do12 or the second selection signal line De12.

[0120] Since each strobe control signal terminal in the conduction control circuit may be coupled to the first strobe signal line or the second strobe signal line, that is, each strobe control signal terminal has two coupling modes, when there are 12 strobe control signal terminals in the conduction control circuit, there are 2 conduction control circuits in total. 12(i.e., 4096) coupling modes. And since one conduction control circuit corresponds to one column of sub-pixels, when there are 12 strobe control signal terminals in the conduction control circuit, it corresponds to 4096 columns of sub-pixels. It can be seen that the timing controller only needs to provide strobe control signals for 12 first strobe signal lines and 12 second strobe signal lines to control the emission of each column of sub-pixels through the conduction control circuit, that is, reducing signal lines, thereby saving space and further reducing costs. Moreover, since the coupling modes of each conduction control circuit are not exactly the same, it can have intelligent adjustment capabilities.

[0121] In some embodiments of the present disclosure, as shown in FIG6 , the control circuit 20 includes:

[0122] The first control circuit 210 is configured to provide the signal of the first clock signal terminal CLK1 to the first node N1 in response to the signal of the reset signal terminal RE;

[0123] The second control circuit 220 is configured to provide the signal of the first clock signal terminal CLK1 or the signal of the first power supply terminal VDD1 to the second node N2 in response to the signal of the first clock signal terminal CLK1 and the signal of the first node N1.

[0124] In some embodiments of the present disclosure, as shown in Figure 6, the first control circuit 210 includes: a first transistor M1; wherein the gate of the first transistor M1 is coupled to the reset signal terminal RE, the first electrode of the first transistor M1 is coupled to the first node N1, and the second electrode of the first transistor M1 is coupled to the first clock signal terminal CLK1.

[0125] Exemplarily, the first transistor can be turned on under the control of the active level of the reset signal transmitted by the reset signal terminal, and can be turned off under the control of the inactive level of the reset signal. Exemplarily, if the first transistor is configured as a P-type transistor, the active level of the reset signal is a low level, and the inactive level of the reset signal is a high level. Alternatively, if the first transistor is configured as an N-type transistor, the active level of the reset signal is a high level, and the inactive level of the reset signal is a low level.

[0126] In some embodiments of the present disclosure, as shown in Figure 6, the second control circuit 220 includes: a second transistor M2 and a third transistor M3; wherein, the gate of the second transistor M2 is coupled to the first node N1, the first electrode of the second transistor M2 is coupled to the first clock signal terminal CLK1 or the first power supply terminal VDD1, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3; the gate of the third transistor M3 is coupled to the first clock signal terminal CLK1, and the second electrode of the third transistor M3 is coupled to the second node N2.

[0127] Exemplarily, the second transistor can be turned on under the control of the active level of the signal transmitted on the first node, and can be turned off under the control of the inactive level of the signal transmitted on the first node. Exemplarily, if the second transistor is configured as a P-type transistor, the active level of the signal transmitted on the first node is a low level, and the inactive level of the signal transmitted on the first node is a high level. Alternatively, if the second transistor is configured as an N-type transistor, the active level of the signal transmitted on the first node is a high level, and the inactive level of the signal transmitted on the first node is a low level.

[0128] Exemplarily, the third transistor can be turned on under the control of the active level of the first clock signal transmitted by the first clock signal terminal, and can be turned off under the control of the inactive level of the first clock signal. Exemplarily, if the third transistor is configured as a P-type transistor, the active level of the first clock signal is a low level, and the inactive level of the first clock signal is a high level. Alternatively, if the third transistor is configured as an N-type transistor, the active level of the first clock signal is a high level, and the inactive level of the first clock signal is a low level.

[0129] In some embodiments of the present disclosure, as shown in Figure 6, the conduction signal output circuit 30 includes: a first conduction transistor Mt1, a second conduction transistor Mt2 and a second capacitor C2; wherein, the gate of the first conduction transistor Mt1 is coupled to the second node N2, the first electrode of the first conduction transistor Mt1 is coupled to the second clock signal terminal CLK2, and the second electrode of the first conduction transistor Mt1 is coupled to the drive output terminal OT; the gate of the second conduction transistor Mt2 is coupled to the third node N3, the first electrode of the second conduction transistor Mt2 is coupled to the drive output terminal OT, and the second electrode of the second conduction transistor Mt2 is coupled to the first reference signal terminal VREF1; the first electrode of the second capacitor C2 is coupled to the second node N2, and the second electrode of the second capacitor C2 is coupled to the drive output terminal OT.

[0130] Exemplarily, the first pass transistor can be turned on under the control of the active level of the signal transmitted on the second node, and can be turned off under the control of the inactive level of the signal transmitted on the second node. Exemplarily, if the first pass transistor is configured as a P-type transistor, the active level of the signal transmitted on the second node is a low level, and the inactive level of the signal transmitted on the second node is a high level. Alternatively, if the first pass transistor is configured as an N-type transistor, the active level of the signal transmitted on the second node is a high level, and the inactive level of the signal transmitted on the second node is a low level.

[0131] Exemplarily, the second pass transistor can be turned on under the control of the active level of the signal transmitted on the third node, and can be turned off under the control of the inactive level of the signal transmitted on the third node. Exemplarily, if the second pass transistor is configured as a P-type transistor, the active level of the signal transmitted on the third node is a low level, and the inactive level of the signal transmitted on the third node is a high level. Alternatively, if the second pass transistor is configured as an N-type transistor, the active level of the signal transmitted on the third node is a high level, and the inactive level of the signal transmitted on the third node is a low level.

[0132] In some embodiments of the present disclosure, as shown in FIG. 6 , the further embodiment includes: a reset circuit 40 configured to provide the signal of the reset signal terminal RE to the third node N3 in response to the signal of the reset signal terminal RE.

[0133] In some embodiments of the present disclosure, as shown in Figure 6, the reset circuit 40 includes: a fourth transistor M4 and a third capacitor C3; wherein, the gate of the fourth transistor M4 is coupled to the reset signal terminal RE, the first electrode of the fourth transistor M4 is coupled to the reset signal terminal RE, and the second electrode of the fourth transistor M4 is coupled to the third node N3; the first electrode of the third capacitor C3 is coupled to the second electrode of the fourth transistor M4, and the second electrode of the third capacitor C3 is coupled to the first reference signal terminal VREF1.

[0134] Exemplarily, the fourth transistor can be turned on under the control of the active level of the reset signal transmitted by the reset signal terminal, and can be turned off under the control of the inactive level of the reset signal. Exemplarily, the fourth transistor is configured as a P-type transistor, then the active level of the reset signal is a low level, and the inactive level of the reset signal is a high level. Alternatively, the fourth transistor is configured as an N-type transistor, then the active level of the reset signal is a high level, and the inactive level of the reset signal is a low level.

[0135] In some embodiments of the present disclosure, as shown in FIG. 6 , the present invention further includes: a third control circuit 50 configured to control a signal of the third node N3 in response to signals of the first node N1 and the third node N3 .

[0136] In some embodiments of the present disclosure, as shown in Figure 6, the third control circuit 50 includes: a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7; wherein, the gate of the fifth transistor M5 is coupled to the first node N1, the first electrode of the fifth transistor M5 is coupled to the third node N3, and the second electrode of the fifth transistor M5 is coupled to the reset signal terminal RE; the gate of the sixth transistor M6 is coupled to the second node N2, the first electrode of the sixth transistor M6 is coupled to the third node N3, and the second electrode of the sixth transistor M6 is coupled to the reset signal terminal RE; the gate of the seventh transistor M7 is coupled to the third node N3, the first electrode of the seventh transistor M7 is coupled to the second node N2, and the second electrode of the seventh transistor M7 is coupled to the first reference signal terminal VREF1.

[0137] Exemplarily, the fifth transistor can be turned on under the control of the active level of the signal transmitted on the first node, and can be turned off under the control of the inactive level of the signal transmitted on the first node. Exemplarily, if the fifth transistor is configured as a P-type transistor, the active level of the signal transmitted on the first node is a low level, and the inactive level of the signal transmitted on the first node is a high level. Alternatively, if the fifth transistor is configured as an N-type transistor, the active level of the signal transmitted on the first node is a high level, and the inactive level of the signal transmitted on the first node is a low level.

[0138] Exemplarily, the sixth transistor can be turned on under the control of the active level of the signal transmitted on the second node, and can be turned off under the control of the inactive level of the signal transmitted on the second node. Exemplarily, if the sixth transistor is configured as a P-type transistor, the active level of the signal transmitted on the second node is a low level, and the inactive level of the signal transmitted on the second node is a high level. Alternatively, if the sixth transistor is configured as an N-type transistor, the active level of the signal transmitted on the second node is a high level, and the inactive level of the signal transmitted on the second node is a low level.

[0139] Exemplarily, the seventh transistor can be turned on under the control of the active level of the signal transmitted on the third node, and can be turned off under the control of the inactive level of the signal transmitted on the third node. Exemplarily, if the seventh transistor is configured as a P-type transistor, the active level of the signal transmitted on the third node is a low level, and the inactive level of the signal transmitted on the third node is a high level. Alternatively, if the seventh transistor is configured as an N-type transistor, the active level of the signal transmitted on the third node is a high level, and the inactive level of the signal transmitted on the third node is a low level.

[0140] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0141] It should be noted that the transistors mentioned in the embodiments of the present disclosure may be thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSs), which are not limited here.

[0142] The following describes the working process of the conduction control circuit provided by the embodiment of the present disclosure by taking the conduction control circuit shown in FIG6 as an example, in combination with the display panel structure diagrams shown in FIG2 and FIG3 and the signal timing diagram shown in FIG7.

[0143] In the embodiment of the present disclosure, as shown in FIG7 , re represents the reset signal of the reset signal terminal RE, clk1 represents the first clock signal of the first clock signal terminal CLK1, clk2 represents the second clock signal of the second clock signal terminal CLK2, do1 represents the signal transmitted on the first selection signal line Do1, de1 represents the signal transmitted on the second selection signal line De1, do2 represents the signal transmitted on the first selection signal line Do2, de2 represents the signal transmitted on the second selection signal line De2, do3 represents the signal transmitted on the first selection signal line Do3, de3 represents the signal transmitted on the second selection signal line De3, do4 represents the signal transmitted on the first selection signal line Do4, de4 represents the signal transmitted on the second selection signal line De4, do5 represents the signal transmitted on the first selection signal line Do5, de5 represents the signal transmitted on the second selection signal line De5, do6 represents the first selection signal line The signal transmitted on the signal line Do6, de6 represents the signal transmitted on the second selection signal line De6, do7 represents the signal transmitted on the first selection signal line Do7, de7 represents the signal transmitted on the second selection signal line De7, do8 represents the signal transmitted on the first selection signal line Do8, de8 represents the signal transmitted on the second selection signal line De8, do9 represents the signal transmitted on the first selection signal line Do9, de9 represents the signal transmitted on the second selection signal line De9, do10 represents the signal transmitted on the first selection signal line Do10, de10 represents the signal transmitted on the second selection signal line De10, do11 represents the signal transmitted on the first selection signal line Do11, de11 represents the signal transmitted on the second selection signal line De11, do12 represents the signal transmitted on the first selection signal line Do12, de12 represents the signal transmitted on the second selection signal line De12.

[0144] Furthermore, a blanking phase H1 and a scanning phase H2 in a display frame 1H are selected.

[0145] In the blank phase H1, first, the reset signal re provides a high level, the first clock signal clk1 provides a low level, the second clock signal clk2 provides a low level, the signal transmitted on the first selection signal line Do1 provides a low level, the signal transmitted on the first selection signal line Do2 provides a low level, the signal transmitted on the first selection signal line Do3 provides a low level, the signal transmitted on the first selection signal line Do4 provides a low level, the signal transmitted on the first selection signal line Do5 provides a low level, the signal transmitted on the first selection signal line Do6 provides a low level, the signal transmitted on the first selection signal line Do7 provides a low level, the signal transmitted on the first selection signal line Do8 provides a low level, the signal transmitted on the first selection signal line Do9 provides a low level, the signal transmitted on the first selection signal line Do10 provides a low level, and the signal transmitted on the first selection signal line Do11 provides a low level. Provide a low level, the signal transmitted on the first selection signal line Do12 provides a low level, the signal transmitted on the second selection signal line De1 provides a low level, the signal transmitted on the second selection signal line De2 provides a low level, the signal transmitted on the second selection signal line De3 provides a low level, the signal transmitted on the second selection signal line De4 provides a low level, the signal transmitted on the second selection signal line De5 provides a low level, the signal transmitted on the second selection signal line De6 provides a low level, the signal transmitted on the second selection signal line De7 provides a low level, the signal transmitted on the second selection signal line De8 provides a low level, the signal transmitted on the second selection signal line De9 provides a low level, the signal transmitted on the second selection signal line De10 provides a low level, the signal transmitted on the second selection signal line De11 provides a low level, and the signal transmitted on the second selection signal line De12 provides a low level.The gate control transistors M0_1-M0_12 are all turned off under the control of the low-level signal; the first transistor M1 is turned on under the control of the high-level reset signal, and provides the first clock signal to the first node N1. Since the first clock signal is low, the signal on the first node N1 is low; the second transistor M2 is turned off under the control of the low-level signal transmitted on the first node N1; the third transistor M3 is turned off under the control of the low-level first clock signal; the fourth transistor M4 is turned on under the control of the high-level reset signal, and provides the reset signal to the third node N3, so the signal on the third node N3 is high; the fifth transistor The transistor M5 is turned off under the control of the low level transmitted on the first node N1; the seventh transistor M7 is turned on under the control of the high level of the reset signal, and provides the signal on the first reference signal terminal VREF1 to the second node N2; the sixth transistor M6 is turned off under the control of the low level of the signal on the second node N2; the first conduction transistor Mt1 is turned off under the control of the low level of the signal on the second node N2; the second conduction transistor Mt2 is turned on under the control of the high level of the signal on the third node N3, and provides the signal on the first reference signal terminal VREF1 to the driving output terminal OT, and the signal output by the driving output terminal OT is a low level.

[0146] Then, the reset signal re provides a low level, the first clock signal clk1 provides a high level, the second clock signal clk2 provides a low level, the signal transmitted on the first selection signal line Do1 provides a high level, the signal transmitted on the first selection signal line Do2 provides a high level, the signal transmitted on the first selection signal line Do3 provides a high level, the signal transmitted on the first selection signal line Do4 provides a high level, the signal transmitted on the first selection signal line Do5 provides a high level, the signal transmitted on the first selection signal line Do6 provides a high level, the signal transmitted on the first selection signal line Do7 provides a high level, the signal transmitted on the first selection signal line Do8 provides a high level, the signal transmitted on the first selection signal line Do9 provides a high level, the signal transmitted on the first selection signal line Do10 provides a high level, and the signal transmitted on the first selection signal line Do11 provides a high level. , the signal transmitted on the first selection signal line Do12 provides a high level, the signal transmitted on the second selection signal line De1 provides a high level, the signal transmitted on the second selection signal line De2 provides a high level, the signal transmitted on the second selection signal line De3 provides a high level, the signal transmitted on the second selection signal line De4 provides a high level, the signal transmitted on the second selection signal line De5 provides a high level, the signal transmitted on the second selection signal line De6 provides a high level, the signal transmitted on the second selection signal line De7 provides a high level, the signal transmitted on the second selection signal line De8 provides a high level, the signal transmitted on the second selection signal line De9 provides a high level, the signal transmitted on the second selection signal line De10 provides a high level, the signal transmitted on the second selection signal line De11 provides a high level, and the signal transmitted on the second selection signal line De12 provides a high level.The gate control transistors M0_1-M0_12 are all turned on under the control of the high-level signal, and the high-level first clock signal is provided to the first node N1, so that the signal on the first node N1 is at a high level; the first transistor M1 is turned off under the control of the low-level reset signal; the second transistor M2 is turned on under the control of the high-level signal transmitted on the first node N1, and the first clock signal is provided to the first electrode of the third transistor M3; the third transistor M3 is turned on under the control of the high-level first clock signal, and the first clock signal on the first electrode of the third transistor M3 is provided to the second node N2, so that the signal on the second node N2 is at a high level; the fourth transistor M4 is turned off under the control of the low-level reset signal. The fifth transistor M5 is turned on under the control of the high level transmitted on the first node N1, and provides the low level of the reset signal to the third node N3, so the signal on the third node N3 is low level; the seventh transistor M7 is turned off under the control of the low level of the signal on the third node N3; the sixth transistor M6 is turned on under the control of the high level of the signal on the second node N2, and provides the reset signal to the third node N3; the second conduction transistor Mt2 is turned off under the control of the low level of the signal on the third node N3; the first conduction transistor Mt1 is turned on under the control of the high level of the signal on the second node N2, and provides the second clock signal to the driving output terminal OT, so the signal output by the driving output terminal OT is low level.

[0147] In the scanning phase H2, the reset signal re provides a low level, the first clock signal clk1 provides a low level, the second clock signal clk2 provides a high level, the signal transmitted on the first selection signal line Do1 provides a high level, the signal transmitted on the first selection signal line Do2 provides a high level, the signal transmitted on the first selection signal line Do3 provides a high level, the signal transmitted on the first selection signal line Do4 provides a high level, the signal transmitted on the first selection signal line Do5 provides a high level, the signal transmitted on the first selection signal line Do6 provides a high level, the signal transmitted on the first selection signal line Do7 provides a high level, the signal transmitted on the first selection signal line Do8 provides a high level, the signal transmitted on the first selection signal line Do9 provides a high level, the signal transmitted on the first selection signal line Do10 provides a high level, and the signal transmitted on the first selection signal line Do11 provides a high level. level, the signal transmitted on the first selection signal line Do12 provides a high level, the signal transmitted on the second selection signal line De1 provides a high level, the signal transmitted on the second selection signal line De2 provides a high level, the signal transmitted on the second selection signal line De3 provides a high level, the signal transmitted on the second selection signal line De4 provides a high level, the signal transmitted on the second selection signal line De5 provides a high level, the signal transmitted on the second selection signal line De6 provides a high level, the signal transmitted on the second selection signal line De7 provides a high level, the signal transmitted on the second selection signal line De8 provides a high level, the signal transmitted on the second selection signal line De9 provides a high level, the signal transmitted on the second selection signal line De10 provides a high level, the signal transmitted on the second selection signal line De11 provides a high level, and the signal transmitted on the second selection signal line De12 provides a high level. The gate control transistors M0_1-M0_12 are all turned on under the control of the high-level signal, providing the low-level first clock signal to the first node N1, so that the signal on the first node N1 is low; the first transistor M1 is turned off under the control of the low-level reset signal; the second transistor M2 is turned off under the control of the low-level signal transmitted on the first node N1; the third transistor M3 is turned off under the control of the low-level first clock signal, so that the second node N2 maintains the high level of the previous stage; the fourth transistor M4 is turned off under the control of the low-level reset signal; the fifth transistor M5 is turned off under the control of the low-level signal transmitted on the first node N1; the seventh transistor M7 is turned off under the control of the low-level reset signal; the sixth transistor M6 is turned on under the control of the high-level signal on the second node N2, and provides the reset signal to the third node N3; the second pass transistor Mt2 is turned off under the control of the low-level signal on the third node N3; the first pass transistor Mt1 is turned on under the control of the high-level signal on the second node N2, and provides the second clock signal to the drive output terminal OT, so that the signal output by the drive output terminal OT is high.

[0148] For example, because the gate control transistors M0_1-M0_12 are connected in series, if any of the gate control transistors is cut off, the gate control circuit will not function properly, i.e., the first clock signal cannot be provided to the first node N1, and the conduction control circuit will not function properly. Therefore, by controlling the signal on the first gate signal line or the second gate signal line, the gate control circuit can be controlled, thereby controlling the conduction control circuit, and then turning on the column of sub-pixels corresponding to the control circuit, thereby realizing intelligent partition control function.

[0149] For example, when the conduction control circuit includes 12 gate control transistors, the sub-pixels of the display panel can be divided into 4096 columns. As shown in FIG8 , since the signal transmitted on the second gate signal line De11 is at a low level and the signal transmitted on the second gate signal line De12 is at a low level, the conduction control circuits coupled to the second gate signal line De11 and / or the second gate signal line De12 at the gate control signal end in the conduction control circuit cannot operate normally (for example, the conduction control circuit coupled to the second gate signal line De11 corresponds to the sub-pixels in the 1025th to 2048th columns, and the conduction control circuit coupled to the second gate signal line De12 corresponds to the sub-pixels in the 2049th to 4096th columns). As a result, the sub-pixels in the columns corresponding to the conduction control circuits (for example, the sub-pixels in the 1025th to 4096th columns) cannot display normally, that is, the display panel is partitioned and controlled, so that the display panel operates in a partitioned manner.

[0150] For example, as shown in Figure 9, since the signal transmitted on the second selection signal line De1-De12 is a low level, only the conduction control circuit in which each selection control signal terminal is coupled to the first selection signal line D01-D012 can work normally, that is, only one conduction control circuit can work normally (for example, the conduction control circuit coupled to the first column of sub-pixels), and other conduction control circuits cannot work normally, then only one column of sub-pixels (for example, the first column of sub-pixels) can display normally, and the sub-pixels in other columns cannot display normally.

[0151] The present disclosure provides other structural diagrams of the conduction control circuit, as shown in Figure 10, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0152] In some embodiments of the present disclosure, as shown in FIG10 , a gate control circuit 10 includes eight gate control transistors, wherein a gate of a first gate control transistor M0_1 is coupled to a corresponding gate control signal terminal DC_1, a first electrode of the first gate control transistor M0_1 is coupled to a first clock signal terminal CLK1, a second electrode of the first gate control transistor M0_1 is coupled to a first electrode of a second gate control transistor M0_2, a gate of a second gate control transistor M0_2 ​​is coupled to a corresponding gate control signal terminal DC_2, a second electrode of the second gate control transistor M0_2 ​​is coupled to a first electrode of a third gate control transistor M0_3, a gate of a third gate control transistor M0_3 is coupled to a corresponding gate control signal terminal DC_3, and a second electrode of the third gate control transistor M0_3 is coupled to a first electrode of a fourth gate control transistor M0_4. The gate of the fourth gate control transistor M0_4 is coupled to the corresponding gate control signal terminal DC_4, and the second electrode of the fourth gate control transistor M0_4 is coupled to the first electrode of the fifth gate control transistor M0_5. The gate of the fifth gate control transistor M0_5 is coupled to the corresponding gate control signal terminal DC_5, and the second electrode of the fifth gate control transistor M0_5 is coupled to the first electrode of the sixth gate control transistor M0_6. The gate of the sixth gate control transistor M0_6 is coupled to the corresponding gate control signal terminal DC_6, and the second electrode of the sixth gate control transistor M0_6 is coupled to the first electrode of the seventh gate control transistor M0_7. The gate of the seventh gate control transistor M0_7 is coupled to the corresponding gate control signal terminal DC_7, and the second electrode of the seventh gate control transistor M0_7 is coupled to the second electrode of the seventh gate control transistor M0_7. A gate electrode of the eighth gate control transistor M0_8 is coupled to the corresponding gate control signal terminal DC_8 , and a second electrode of the eighth gate control transistor M0_8 is coupled to the first node N1 .

[0153] For example, the number of gate control transistors can be adjusted to adjust the number of partitions of the display panel. As shown in 10, since each gate control signal terminal in the conduction control circuit may be coupled to the first gate signal line or the second gate signal line, that is, each gate control signal terminal has two coupling modes, when there are 8 gate control signal terminals in the conduction control circuit, the conduction control circuit has a total of 2 gate control signal terminals. 8(i.e., 256) coupling modes. And since one conduction control circuit corresponds to one column of sub-pixels, when there are 8 strobe control signal terminals in the conduction control circuit, it corresponds to 256 columns of sub-pixels, and a maximum of 256 column partitions can be achieved. It can be seen that the timing controller only needs to provide strobe control signals for 8 first strobe signal lines and 8 second strobe signal lines to control the emission of each column of sub-pixels through the conduction control circuit, that is, reducing signal lines, thereby saving space and further reducing costs. Moreover, since the coupling modes of each conduction control circuit are not exactly the same, it can have intelligent adjustment capabilities.

[0154] For example, the conduction control circuit can be optimized and adjusted according to the needs. The number of gate control transistors in the conduction control circuit and the corresponding gate control signal terminals determine the number of column partitions. If the number of gate control transistors is N, the number of column partitions is 2. N To achieve single-point driving of sub-pixels, it is necessary to ensure 2 N Not less than V (V is the maximum number of columns corresponding to sub-pixels of the display panel).

[0155] The present disclosure provides some structural diagrams of the conduction control circuit, as shown in Figure 11, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0156] In other embodiments of the present disclosure, as shown in FIG11 , the second control circuit 220 is configured to provide a signal from the first power supply terminal VDD1 to the second node N2 in response to a signal from the first clock signal terminal CLK1 and a signal from the first node N1 .

[0157] In some embodiments of the present disclosure, as shown in FIG11 , the gate of the second transistor M2 is coupled to the first node N1 , the first electrode of the second transistor M2 is coupled to the first power supply terminal VDD1 , and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3 .

[0158] In some embodiments of the present disclosure, as shown in FIG. 11 , the present invention further includes: a reset circuit 40 configured to provide a signal from the first power supply terminal VDD1 to the third node N3 in response to a signal from the reset signal terminal RE.

[0159] In some embodiments of the present disclosure, as shown in Figure 11, the gate of the fourth transistor M4 is coupled to the reset signal terminal RE, the first electrode of the fourth transistor M4 is coupled to the first power supply terminal VDD1, and the second electrode of the fourth transistor M4 is coupled to the third node N3; the first electrode of the third capacitor C3 is coupled to the second electrode of the fourth transistor M4, and the second electrode of the third capacitor C3 is coupled to the second reference signal terminal VREF2.

[0160] In some embodiments of the present disclosure, as shown in FIG. 11 , the fourth control circuit 60 is further included, configured to control the signal of the third node N3 in response to the signals of the first node N1 , the second node N2 and the third node N3 .

[0161] In some embodiments of the present disclosure, as shown in Figure 11, the fourth control circuit 60 includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11; wherein, the gate of the eighth transistor M8 is coupled to the first node N1, the first electrode of the eighth transistor M8 is coupled to the third node N3, and the second electrode of the eighth transistor M8 is coupled to the second electrode of the ninth transistor M9; the gate of the ninth transistor M9 is coupled to the third node N3, and the first electrode of the ninth transistor M9 is coupled to the first power supply terminal VDD1; the gate of the tenth transistor M10 is coupled to the second node N2, the first electrode of the tenth transistor M10 is coupled to the reset signal terminal RE, and the second electrode of the tenth transistor M10 is coupled to the second electrode of the ninth transistor M9; the gate of the eleventh transistor M11 is coupled to the second node N2, the first electrode of the eleventh transistor M11 is coupled to the second electrode of the tenth transistor M10, and the second electrode of the eleventh transistor M11 is coupled to the third node N3.

[0162] Exemplarily, the eighth transistor can be turned on under the control of the active level of the signal transmitted on the first node, and can be turned off under the control of the inactive level of the signal transmitted on the first node. Exemplarily, if the eighth transistor is configured as a P-type transistor, the active level of the signal transmitted on the first node is a low level, and the inactive level of the signal transmitted on the first node is a high level. Alternatively, if the eighth transistor is configured as an N-type transistor, the active level of the signal transmitted on the first node is a high level, and the inactive level of the signal transmitted on the first node is a low level.

[0163] Exemplarily, the ninth transistor can be turned on under the control of the active level of the signal transmitted on the third node, and can be turned off under the control of the inactive level of the signal transmitted on the third node. Exemplarily, if the ninth transistor is configured as a P-type transistor, the active level of the signal transmitted on the third node is a low level, and the inactive level of the signal transmitted on the third node is a high level. Alternatively, if the ninth transistor is configured as an N-type transistor, the active level of the signal transmitted on the third node is a high level, and the inactive level of the signal transmitted on the third node is a low level.

[0164] Exemplarily, the tenth transistor and the eleventh transistor can be turned on under the control of the effective level of the signal transmitted on the second node, and can be turned off under the control of the ineffective level of the signal transmitted on the second node. Exemplarily, the tenth transistor and the eleventh transistor are configured as P-type transistors, then the effective level of the signal transmitted on the second node is a low level, and the ineffective level of the signal transmitted on the second node is a high level. Alternatively, the tenth transistor and the eleventh transistor are configured as N-type transistors, then the effective level of the signal transmitted on the second node is a high level, and the ineffective level of the signal transmitted on the second node is a low level.

[0165] In some embodiments of the present disclosure, as shown in FIG. 11 , the further embodiment includes: a fifth control circuit 70 configured to control the signal of the second node N2 in response to the signal of the third node N3 .

[0166] In some embodiments of the present disclosure, as shown in FIG11 , the fifth control circuit 70 includes: a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15; wherein a gate of the twelfth transistor M12 is coupled to a third node N3, a first electrode of the twelfth transistor M12 is coupled to a first electrode of the third transistor M3, and a second electrode of the twelfth transistor M12 is coupled to a second electrode of the thirteenth transistor M13; a gate of the thirteenth transistor M13 is coupled to a second node N2, and a first electrode of the thirteenth transistor M13 is coupled to a first power supply terminal VDD1; a gate of the fourteenth transistor M14 is coupled to a third node N3, a first electrode of the fourteenth transistor M14 is coupled to a second reference signal terminal VREF2, and a second electrode of the fourteenth transistor M14 is coupled to a second electrode of the thirteenth transistor M13; a gate of the fifteenth transistor M15 is coupled to a third node N3, a first electrode of the fifteenth transistor M15 is coupled to a second electrode of the fourteenth transistor M14, and a second electrode of the fifteenth transistor M15 is coupled to a second node N2.

[0167] Exemplarily, the twelfth transistor, the fourteenth transistor, and the fifteenth transistor can be turned on under the control of the effective level of the signal transmitted on the third node, and can be turned off under the control of the ineffective level of the signal transmitted on the third node. Exemplarily, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are configured as P-type transistors, then the effective level of the signal transmitted on the third node is a low level, and the ineffective level of the signal transmitted on the third node is a high level. Alternatively, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are configured as N-type transistors, then the effective level of the signal transmitted on the third node is a high level, and the ineffective level of the signal transmitted on the third node is a low level.

[0168] Exemplarily, the thirteenth transistor can be turned on under the control of the active level of the signal transmitted on the second node, and can be turned off under the control of the inactive level of the signal transmitted on the second node. Exemplarily, if the thirteenth transistor is configured as a P-type transistor, the active level of the signal transmitted on the second node is a low level, and the inactive level of the signal transmitted on the second node is a high level. Alternatively, if the thirteenth transistor is configured as an N-type transistor, the active level of the signal transmitted on the second node is a high level, and the inactive level of the signal transmitted on the second node is a low level.

[0169] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0170] For example, the circuit structure shown in FIG. 11 is applicable to an oxide backplane with a negative initial threshold voltage, etc., which is not limited here.

[0171] The present disclosure provides some structural diagrams of the conduction control circuit, as shown in Figure 12, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0172] In some embodiments of the present disclosure, as shown in FIG12 , the second control circuit 220 further includes a first capacitor C1 , wherein a first electrode of the first capacitor C1 is coupled to the first power supply terminal VDD1 , and a second electrode of the first capacitor C1 is coupled to the first node N1 .

[0173] In some embodiments of the present disclosure, as shown in FIG. 12 , the further embodiment includes: a sixth control circuit 80 configured to control the signal of the third node in response to signals of the first node, the third node and the second power supply terminal.

[0174] In some embodiments of the present disclosure, as shown in FIG12 , the sixth control circuit 80 includes: a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20; wherein a gate of the sixteenth transistor M16 is coupled to the second node N2, a first electrode of the sixteenth transistor M16 is coupled to the third reference signal terminal VREF3, and a second electrode of the sixteenth transistor M16 is coupled to a first electrode of the seventeenth transistor M17; a gate of the seventeenth transistor M17 is coupled to the second power supply terminal VDD2, a second electrode of the seventeenth transistor M17 is coupled to the second power supply terminal VDD2; a gate of the eighteenth transistor M18 is coupled to the first electrode of the seventeenth transistor M17, A first electrode of the eighteenth transistor M18 is coupled to the third node N3, and a second electrode of the eighteenth transistor M18 is coupled to the second power supply terminal VDD2; a gate of the nineteenth transistor M19 is coupled to the first node N1, a first electrode of the nineteenth transistor M19 is coupled to the first electrode of the eighteenth transistor M18, and a second electrode of the nineteenth transistor M19 is coupled to the second reference signal terminal VREF2; a gate of the twentieth transistor M20 is coupled to the second node N2, a first electrode of the twentieth transistor M20 is coupled to the third node N3, and a second electrode of the twentieth transistor M20 is coupled to the second reference signal terminal VREF2.

[0175] Exemplarily, the sixteenth transistor can be turned on under the control of the effective level of the signal transmitted on the second node, and can be turned off under the control of the ineffective level of the signal transmitted on the second node. Exemplarily, if the sixteenth transistor is configured as a P-type transistor, the effective level of the signal transmitted on the second node is a low level, and the ineffective level of the signal transmitted on the second node is a high level. Alternatively, if the sixteenth transistor is configured as an N-type transistor, the effective level of the signal transmitted on the second node is a high level, and the ineffective level of the signal transmitted on the second node is a low level.

[0176] Exemplarily, the seventeenth transistor can be turned on under the control of the active level of the signal at the second power supply terminal, and can be turned off under the control of the inactive level of the signal at the second power supply terminal. Exemplarily, if the seventeenth transistor is configured as a P-type transistor, the active level of the signal at the second power supply terminal is a low level, and the inactive level of the signal at the second power supply terminal is a high level. Alternatively, if the seventeenth transistor is configured as an N-type transistor, the active level of the signal at the second power supply terminal is a high level, and the inactive level of the signal at the second power supply terminal is a low level.

[0177] Exemplarily, the eighteenth transistor can be turned on under the control of the effective level of the signal of the first electrode of the seventeenth transistor, and can be turned off under the control of the ineffective level of the signal of the first electrode of the seventeenth transistor. Exemplarily, if the eighteenth transistor is set as a P-type transistor, the effective level of the signal of the first electrode of the seventeenth transistor is a low level, and the ineffective level of the signal of the first electrode of the seventeenth transistor is a high level. Alternatively, if the eighteenth transistor is set as an N-type transistor, the effective level of the signal of the first electrode of the seventeenth transistor is a high level, and the ineffective level of the signal of the first electrode of the seventeenth transistor is a low level.

[0178] Exemplarily, the nineteenth transistor can be turned on under the control of the effective level of the signal transmitted on the first node, and can be turned off under the control of the ineffective level of the signal transmitted on the first node. Exemplarily, if the nineteenth transistor is configured as a P-type transistor, the effective level of the signal transmitted on the first node is a low level, and the ineffective level of the signal transmitted on the first node is a high level. Alternatively, if the nineteenth transistor is configured as an N-type transistor, the effective level of the signal transmitted on the first node is a high level, and the ineffective level of the signal transmitted on the first node is a low level.

[0179] Exemplarily, the twentieth transistor can be turned on under the control of the effective level of the signal transmitted on the second node, and can be turned off under the control of the ineffective level of the signal transmitted on the second node. Exemplarily, if the twentieth transistor is configured as a P-type transistor, the effective level of the signal transmitted on the second node is a low level, and the ineffective level of the signal transmitted on the second node is a high level. Alternatively, if the twentieth transistor is configured as an N-type transistor, the effective level of the signal transmitted on the second node is a high level, and the ineffective level of the signal transmitted on the second node is a low level.

[0180] In some embodiments of the present disclosure, as shown in FIG. 12 , the seventh control circuit 90 is further included, configured to control the signal of the second node N2 in response to the signals of the second node N2 , the third node N3 and the reset signal terminal RE.

[0181] In some embodiments of the present disclosure, as shown in FIG12 , the seventh control circuit 90 includes: a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, and a twenty-fifth transistor M25; wherein the gate of the twenty-first transistor M21 is coupled to the third node N3, the first electrode of the twenty-first transistor M21 is coupled to the second reference signal terminal VREF2, the second electrode of the twenty-first transistor M21 is coupled to the first electrode of the twenty-second transistor M22, and the gate of the twenty-second transistor M22 is coupled to the third node N3. A second electrode of the twenty-second transistor M22 is coupled to the second node N2; a gate of the twenty-third transistor M23 is coupled to the second node N2, a first electrode of the twenty-third transistor M23 is coupled to the first power supply terminal VDD1, and a second electrode of the twenty-third transistor M23 is coupled to the first electrode of the twenty-second transistor M22; a gate of the twenty-fourth transistor M24 is coupled to the reset signal terminal RE, a first electrode of the twenty-fourth transistor M24 is coupled to the second reference signal terminal VREF2, and a second electrode of the twenty-fourth transistor M24 is coupled to the first electrode of the twenty-second transistor M22;

[0182] A gate of the twenty-fifth transistor M25 is coupled to the reset signal terminal RE, a first electrode of the twenty-fifth transistor M25 is coupled to the second electrode of the twenty-fourth transistor M24, and a second electrode of the twenty-fifth transistor M25 is coupled to the second node N2.

[0183] Exemplarily, the twenty-first transistor and the twenty-second transistor can be turned on under the control of the effective level of the signal transmitted on the third node, and can be turned off under the control of the ineffective level of the signal transmitted on the third node. Exemplarily, if the twenty-first transistor and the twenty-second transistor are configured as P-type transistors, the effective level of the signal transmitted on the third node is a low level, and the ineffective level of the signal transmitted on the third node is a high level. Alternatively, if the twenty-first transistor and the twenty-second transistor are configured as N-type transistors, the effective level of the signal transmitted on the third node is a high level, and the ineffective level of the signal transmitted on the third node is a low level.

[0184] Exemplarily, the twenty-third transistor can be turned on under the control of the effective level of the signal transmitted on the second node, and can be turned off under the control of the ineffective level of the signal transmitted on the second node. Exemplarily, if the twenty-third transistor is configured as a P-type transistor, the effective level of the signal transmitted on the second node is a low level, and the ineffective level of the signal transmitted on the second node is a high level. Alternatively, if the twenty-third transistor is configured as an N-type transistor, the effective level of the signal transmitted on the second node is a high level, and the ineffective level of the signal transmitted on the second node is a low level.

[0185] Exemplarily, the twenty-fourth transistor and the twenty-fifth transistor can be turned on under the control of the active level of the reset signal transmitted by the reset signal terminal, and can be turned off under the control of the inactive level of the reset signal. Exemplarily, if the twenty-fourth transistor and the twenty-fifth transistor are configured as P-type transistors, the active level of the reset signal is a low level, and the inactive level of the reset signal is a high level. Alternatively, if the twenty-fourth transistor and the twenty-fifth transistor are configured as N-type transistors, the active level of the reset signal is a high level, and the inactive level of the reset signal is a low level.

[0186] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0187] For example, the circuit structure shown in FIG12 is suitable for low-power display, etc., and is not limited here.

[0188] Based on the same concept, the embodiment of the present disclosure also provides a display device, including a display device whose principle of solving the problem is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be repeated here.

[0189] In specific implementations, in embodiments of the present invention, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are readily understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present invention.

[0190] The above is only an example to illustrate the specific structure of each module in the pixel circuit provided by the embodiment of the present invention. In specific implementation, the above specific structure is not limited to the above structure provided by the embodiment of the present invention, and can also be other structures known to those skilled in the art, which is not limited here.

[0191] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0192] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A conduction control circuit, wherein: include: a gating control circuit coupled to the first node and configured to provide a signal from a first clock signal terminal to the first node in response to signals from a plurality of different gating control signal terminals; a control circuit coupled to the first node and the second node, and configured to provide a signal at the first clock signal terminal or a signal at the first power supply terminal to the second node in response to a signal at the first node; The conduction signal output circuit is coupled to the second node and the third node, and is configured to provide the signal of the second clock signal terminal to the driving output terminal in response to the signal of the second node, and to provide the signal of the first reference signal terminal to the driving output terminal in response to the signal of the third node.

2. The conduction control circuit according to claim 1, wherein: The gating control circuit comprises: N gating control transistors; The N gate control transistors correspond one-to-one to the multiple different gate control signal terminals; The gate of the nth gate control transistor among the N gate control transistors is coupled to the corresponding gate control signal terminal; A first electrode of a first gate control transistor among the N gate control transistors is coupled to the first clock signal terminal; A second electrode of the Nth gate control transistor among the N gate control transistors is coupled to the first node; The second electrode of the nth transistor among the N gate control transistors is coupled to the first electrode of the (n+1)th transistor among the N gate control transistors.

3. The conduction control circuit according to claim 1 or 2, wherein: The control circuit comprises: a first control circuit configured to provide the signal of the first clock signal terminal to the first node in response to the signal of the reset signal terminal; a second control circuit configured to provide the signal of the first clock signal terminal or the signal of the first power supply terminal to the first node in response to the signal of the first clock signal terminal and the signal of the first node; the second node.

4. The conduction control circuit according to claim 3, wherein: The first control circuit includes: a first transistor; A gate of the first transistor is coupled to the reset signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the first clock signal terminal.

5. The conduction control circuit according to claim 3, wherein: The second control circuit includes: a second transistor and a third transistor; The gate of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the first clock signal terminal or the first power supply terminal, and the second electrode of the second transistor is coupled to the first electrode of the third transistor; A gate of the third transistor is coupled to the first clock signal terminal, and a second electrode of the third transistor is coupled to the second node.

6. The conduction control circuit according to claim 5, wherein: The second control circuit further includes: a first capacitor; A first electrode of the first capacitor is coupled to the first power supply terminal, and a second electrode of the first capacitor is coupled to the first node.

7. The conduction control circuit according to any one of claims 1 to 6, wherein: The conduction signal output circuit comprises: a first conduction transistor, a second conduction transistor and a second capacitor; The gate of the first conduction transistor is coupled to the second node, the first electrode of the first conduction transistor is coupled to the second clock signal terminal, and the second electrode of the first conduction transistor is coupled to the driving output terminal; The gate of the second conduction transistor is coupled to the third node, the first electrode of the second conduction transistor is coupled to the driving output terminal, and the second electrode of the second conduction transistor is coupled to the first reference signal terminal; A first electrode of the second capacitor is coupled to the second node, and a second electrode of the second capacitor is coupled to the driving output terminal.

8. The conduction control circuit according to any one of claims 1 to 7, wherein: Also includes: The reset circuit is configured to provide the signal of the reset signal terminal or the signal of the first power supply terminal to the third node in response to the signal of the reset signal terminal.

9. The conduction control circuit according to claim 8, wherein: The reset circuit comprises: a fourth transistor and a third capacitor; The gate of the fourth transistor is coupled to the reset signal terminal, the first electrode of the fourth transistor is coupled to the reset signal terminal or the first power supply terminal, and the second electrode of the fourth transistor is coupled to the third node; A first electrode of the third capacitor is coupled to the second electrodes of the four transistors, and a second electrode of the third capacitor is coupled to the first reference signal terminal or the second reference signal terminal.

10. The conduction control circuit according to any one of claims 1 to 9, wherein: Also includes: The third control circuit is configured to control a signal of the third node in response to signals of the first node and the third node.

11. The conduction control circuit according to claim 10, wherein: The third control circuit includes: a fifth transistor, a sixth transistor and a seventh transistor; The gate of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the reset signal terminal; The gate of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the reset signal terminal; A gate of the seventh transistor is coupled to the third node, a first electrode of the seventh transistor is coupled to the second node, and a second electrode of the seventh transistor is coupled to the first reference signal terminal.

12. The conduction control circuit according to any one of claims 1 to 11, wherein: Also includes: The fourth control circuit is configured to control a signal of the third node in response to signals of the first node, the second node, and the third node.

13. The conduction control circuit according to claim 12, wherein: The fourth control circuit includes: an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor; The gate of the eighth transistor is coupled to the first node, and the first electrode of the eighth transistor coupled to the third node, the second electrode of the eighth transistor is coupled to the second electrode of the ninth transistor; The gate of the ninth transistor is coupled to the third node, and the first electrode of the ninth transistor is coupled to the first power supply terminal; The gate of the tenth transistor is coupled to the second node, the first electrode of the tenth transistor is coupled to the reset signal terminal, and the second electrode of the tenth transistor is coupled to the second electrode of the ninth transistor; A gate of the eleventh transistor is coupled to the second node, a first electrode of the eleventh transistor is coupled to the second electrode of the tenth transistor, and a second electrode of the eleventh transistor is coupled to the third node.

14. The conduction control circuit according to any one of claims 1 to 13, wherein: Also includes: The fifth control circuit is configured to control the signal of the second node in response to the signal of the third node.

15. The conduction control circuit according to claim 14, wherein: The fifth control circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; The gate of the twelfth transistor is coupled to the third node, the first electrode of the twelfth transistor is coupled to the first electrode of the third transistor, and the second electrode of the twelfth transistor is coupled to the second electrode of the thirteenth transistor; The gate of the thirteenth transistor is coupled to the second node, and the first electrode of the thirteenth transistor is coupled to the first power supply terminal; The gate of the fourteenth transistor is coupled to the third node, the first electrode of the fourteenth transistor is coupled to the second reference signal terminal, and the second electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor; A gate of the fifteenth transistor is coupled to the third node, a first electrode of the fifteenth transistor is coupled to a second electrode of the fourteenth transistor, and a second electrode of the fifteenth transistor is coupled to the second node.

16. The conduction control circuit according to any one of claims 1 to 15, wherein: Also includes: The sixth control circuit is configured to control a signal of the third node in response to signals of the first node, the third node and a second power supply terminal.

17. The conduction control circuit according to claim 16, wherein: The sixth control circuit includes: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor; The gate of the sixteenth transistor is coupled to the second node, the first electrode of the sixteenth transistor is coupled to the third reference signal terminal, and the second electrode of the sixteenth transistor is coupled to the first electrode of the seventeenth transistor; The gate of the seventeenth transistor is coupled to the second power supply terminal, and the second electrode of the seventeenth transistor is coupled to the second power supply terminal; The gate of the eighteenth transistor is coupled to the first electrode of the seventeenth transistor, the first electrode of the eighteenth transistor is coupled to the third node, and the second electrode of the eighteenth transistor is coupled to the second power supply terminal; The gate of the nineteenth transistor is coupled to the first node, the first electrode of the nineteenth transistor is coupled to the first electrode of the eighteenth transistor, and the second electrode of the nineteenth transistor is coupled to the second reference signal terminal; A gate of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the third node, and a second electrode of the twentieth transistor is coupled to the second reference signal terminal.

18. The conduction control circuit according to any one of claims 1 to 17, wherein: Also includes: The seventh control circuit is configured to control the signal of the second node in response to the signals of the second node, the third node and the reset signal terminal.

19. The conduction control circuit according to claim 18, wherein: The seventh control circuit includes: a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor and a twenty-fifth transistor; A gate of the twenty-first transistor is coupled to the third node, a first electrode of the twenty-first transistor is coupled to the second reference signal terminal, and a second electrode of the twenty-first transistor is coupled to a first electrode of the twenty-second transistor; A gate of the 22nd transistor is coupled to the third node, and a second electrode of the 22nd transistor is coupled to the second node; A gate of the twenty-third transistor is coupled to the second node, a first electrode of the twenty-third transistor is coupled to the first power supply terminal, and a second electrode of the twenty-third transistor is coupled to the first electrode of the twenty-second transistor; A gate of the 24th transistor is coupled to the reset signal terminal, a first electrode of the 24th transistor is coupled to the second reference signal terminal, and a second electrode of the 24th transistor is coupled to a first electrode of the 22nd transistor; A gate of the 25th transistor is coupled to the reset signal terminal, a first electrode of the 25th transistor is coupled to a second electrode of the 24th transistor, and a second electrode of the 25th transistor is coupled to the second node.

20. A display panel, wherein: include: Display area and non-display area; The display area includes: a plurality of sub-pixels, each of the plurality of sub-pixels including a pixel circuit; The non-display area includes: A timing controller configured to provide a plurality of strobe control signals; A plurality of conduction control circuits as described in any one of claims 1 to 19 are coupled to the timing controller and the pixel circuit, the plurality of gating control signal terminals are used to receive the plurality of gating control signals, and the conduction control circuit is configured to provide the signal of the driving output terminal to the pixel circuit in response to the plurality of gating control signals provided by the timing controller.

21. The display panel according to claim 20, wherein: The display area further comprises: a plurality of conduction signal lines, and the pixel circuits in a column of sub-pixels are coupled to one of the conduction signal lines; One of the conduction signal lines is coupled to a driving output terminal of the conduction control circuit.

22. The display panel according to claim 20, wherein: The non-display area also includes: The data driving circuit is coupled to the pixel circuit and the timing controller, and is configured to provide a data signal to the pixel circuit in response to a data signal output by the timing controller.

23. The display panel according to claim 22, wherein: The plurality of conduction control circuits are located between the data driving circuit and the display area.

24. The display panel according to claim 22, wherein: The plurality of conduction control circuits are located at a side of the display area away from the data driving circuit.

25. A display device, wherein: Comprising a display panel as described in any one of claims 20-24.

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