Display apparatus and driving control method

Abstract

Disclosed are a display apparatus and a driving control method. The display apparatus comprises: a voltage conversion circuit (520), which is configured to receive a backlight power supply voltage, perform voltage conversion on the backlight power supply voltage, generate a first power supply voltage (AVDD), and output same; the backlight power supply voltage is configured to supply power to a backlight control circuit (530); a power management circuit (510), which is coupled to the voltage conversion circuit (520) and is configured to receive a second power supply voltage (VCC) and a first power supply voltage (AVDD), generate, on the basis of the second power supply voltage (VCC), a first driving voltage (VGZ1) and output same to a driving circuit, and generate, on the basis of the first power supply voltage (AVDD), a second driving voltage (VGZ2) and output same to a display panel.

Description

Display device and driving control method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device and a driving control method. Background Art

[0002] Displays such as liquid crystal displays (LCDs) typically include multiple pixel units. Each pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. By controlling the brightness of each sub-pixel, the desired colors are mixed to display a color image.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides a display device, including:

[0005] a voltage conversion circuit configured to receive a backlight power supply voltage, perform voltage conversion on the backlight power supply voltage, generate a first power supply voltage, and output the first power supply voltage; the backlight power supply voltage is configured to supply power to the backlight control circuit;

[0006] The power management circuit is coupled to the voltage conversion circuit and is configured to receive a second power supply voltage and the first power supply voltage, generate a first driving voltage based on the second power supply voltage and output it to the driving circuit, and generate a second driving voltage based on the first power supply voltage and output it to the display panel.

[0007] In some embodiments, the voltage conversion circuit is configured to perform a step-down conversion on the backlight power supply voltage to generate the first power supply voltage.

[0008] In some embodiments, the voltage conversion circuit includes a step-down circuit;

[0009] The input end of the step-down circuit is configured to receive the backlight power supply voltage, the output end of the step-down circuit is coupled to the power management circuit, and the output end of the step-down circuit is configured to output the first power supply voltage.

[0010] In some embodiments, the voltage conversion circuit further includes: a first voltage-dividing resistor and a second voltage-dividing resistor, and the output end of the step-down circuit is coupled to the power management circuit through the first voltage-dividing resistor;

[0011] A first end of the first voltage-dividing resistor is coupled to the output end of the step-down circuit, and a second end of the first voltage-dividing resistor is coupled to the power management circuit;

[0012] A first end of the second voltage-dividing resistor is coupled to the output end of the step-down circuit, and a second end of the second voltage-dividing resistor is coupled to the ground end.

[0013] In some embodiments, the voltage value of the first supply voltage satisfies the following formula: V out =V FB (1+r1 / r2);

[0014] Among them, V out Represents the voltage value of the first supply voltage, V FB represents the feedback reference voltage, r1 represents the resistance value of the first voltage-dividing resistor, and r2 represents the resistance value of the second voltage-dividing resistor.

[0015] In some embodiments, the power management circuit is further configured to generate and output an enable voltage according to the second supply voltage;

[0016] The voltage conversion circuit is further configured to receive the enable voltage, and in response to the enable voltage, perform voltage conversion on the backlight power supply voltage to generate and output a first power supply voltage.

[0017] In some embodiments, the power management circuit is configured to generate the enable voltage according to the second supply voltage after receiving the second supply voltage and after a delay period.

[0018] In some embodiments, the power management circuit is configured to be coupled to a gate driving circuit in the display panel;

[0019] The second driving voltage includes: at least one of a first reference voltage and a second reference voltage, the first reference voltage being greater than the second reference voltage;

[0020] The first reference voltage is configured to provide a high-level signal to the gate drive circuit;

[0021] The second reference voltage is configured to provide a low-level signal to the gate driving circuit.

[0022] In some embodiments, the driving circuit includes: a timing controller coupled to the power management circuit, and the first driving voltage includes: at least one of a timing supply voltage and a timing driving logic voltage;

[0023] The timing controller is configured to receive the timing power supply voltage, adopt the timing power supply voltage for power supply, start working in response to the timing power supply voltage, and receive the timing drive logic voltage, and output a timing control signal in response to the timing drive logic voltage.

[0024] In some embodiments, the driving circuit further includes: a level conversion circuit, the level conversion circuit being coupled to the power management circuit;

[0025] The level conversion circuit is configured to receive the timing driving logic voltage and output a clock signal in response to the timing driving logic voltage.

[0026] In some embodiments, the driving circuit includes: a source driving circuit, the source driving circuit is coupled to the power management circuit; the first driving voltage includes: a source driving supply voltage;

[0027] The source driving circuit is configured to receive the source driving power supply voltage, generate a data voltage according to the source driving power supply voltage, and output the data voltage.

[0028] In some embodiments, the display device further includes: the backlight control circuit, wherein the backlight control circuit is configured to receive the backlight power supply voltage to adopt the backlight power supply voltage for power supply.

[0029] The present disclosure also provides a driving control method for the above-mentioned display device, including:

[0030] The voltage conversion circuit receives a backlight power supply voltage, performs voltage conversion on the backlight power supply voltage, generates a first power supply voltage, and outputs the first power supply voltage; wherein the backlight power supply voltage is configured to supply power to the backlight control circuit;

[0031] The power management circuit receives a second power supply voltage and the first power supply voltage, generates a first driving voltage according to the second power supply voltage and outputs it to the driving circuit, and generates a second driving voltage according to the first power supply voltage and outputs it to the display panel.

[0032] In some embodiments, converting the backlight power supply voltage to generate the first power supply voltage includes:

[0033] The backlight power supply voltage is stepped down to generate the first power supply voltage.

[0034] In some embodiments, further comprising:

[0035] The power management circuit generates and outputs an enable voltage according to the second supply voltage;

[0036] The voltage conversion circuit receives the enable voltage, performs voltage conversion on the backlight power supply voltage in response to the enable voltage, generates a first power supply voltage, and outputs the first power supply voltage.

[0037] In some embodiments, generating an enable voltage according to the second supply voltage includes:

[0038] After receiving the second power supply voltage and after a delay period, the enable voltage is generated according to the second power supply voltage.

[0039] In some embodiments, the power management circuit is configured to be coupled to a gate driving circuit in the display panel;

[0040] The second driving voltage includes: at least one of a first reference voltage and a second reference voltage, the first reference voltage being greater than the second reference voltage;

[0041] The first reference voltage increases a level signal to the gate drive circuit;

[0042] The second reference voltage provides a low level signal to the gate driving circuit.

[0043] In some embodiments, the driving circuit includes: a timing controller coupled to the power management circuit, and the first driving voltage includes: at least one of a timing supply voltage and a timing driving logic voltage;

[0044] The drive control method further includes:

[0045] The timing controller receives the timing power supply voltage, adopts the timing power supply voltage for power supply, and starts working in response to the timing power supply voltage, and receives the timing driving logic voltage, and outputs a timing control signal in response to the timing driving logic voltage.

[0046] In some embodiments, the driving circuit includes: a source driving circuit, the source driving circuit is coupled to the power management circuit; the first driving voltage includes: a source driving supply voltage;

[0047] The drive control method further includes:

[0048] The source driving circuit receives the source driving power supply voltage, generates and outputs a data voltage according to the source driving power supply voltage.

[0049] In some embodiments, the driving control method further includes: the backlight control circuit receiving the backlight power supply voltage to adopt the backlight power supply voltage for power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram of some structures of a display device provided by an embodiment of the present disclosure;

[0051] FIG2 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0052] FIG3 is a schematic diagram of some further structures of a display device provided by an embodiment of the present disclosure;

[0053] FIG4 is a schematic diagram of some further structures of a display device provided by an embodiment of the present disclosure;

[0054] FIG5 is a schematic diagram of some structures of a display device provided by an embodiment of the present disclosure;

[0055] FIG6 is a schematic diagram of some further structures of a display device provided by an embodiment of the present disclosure;

[0056] FIG7 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0057] FIG8 is a schematic diagram of some further structures of a display device provided by an embodiment of the present disclosure;

[0058] FIG9 is a flowchart of some drive control methods provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "coupled" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0061] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0062] The present disclosure provides a display device, as shown in FIG1 and FIG2 , which may include: a display panel, a source driver circuit 120, a backlight module 200, a level shift circuit 400, and a timing controller 300. The display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (e.g., GA1, GA2, GA3, GA4), a plurality of data lines DA (e.g., DA1, DA2, DA3), and a gate driver circuit 110. The gate driver circuit 110 is coupled to the gate lines GA1, GA2, GA3, GA4, respectively, and the source driver circuit 120 is coupled to the data lines DA1, DA2, DA3, respectively. The timing controller 300 may process the received display data and output it to the source driver circuit 120. Furthermore, the timing controller 300 may input a clock signal to the gate driver circuit 110 through the level shift circuit. The gate drive circuit 110 can output gate scanning signals to the gate lines GA1, GA2, GA3, and GA4 based on input high-level signals, low-level signals, and clock signals, thereby driving the gate lines GA1, GA2, GA3, and GA4. The source drive circuit 120 can input data voltages to the data lines based on input display data and the source drive power supply voltage AVEE, thereby charging the sub-pixel SPX, causing the sub-pixel SPX to input the corresponding data voltage, thereby realizing the image display function of the display frame.

[0063] For example, two source driver circuits 120 may be provided, wherein one source driver circuit 120 is coupled to half the number of data lines, and the other source driver circuit 120 is coupled to the other half of the number of data lines. Of course, three, four, or more source driver circuits 120 may also be provided, which can be designed and determined according to the needs of actual applications and is not limited here.

[0064] Exemplarily, each pixel unit includes a plurality of sub-pixels SPX. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, thereby enabling color display by mixing red, green, and blue. Alternatively, a pixel unit may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, thereby enabling color display by mixing red, green, blue, and white. Of course, in actual applications, the luminous colors of the sub-pixels in a pixel unit can be designed and determined based on the actual application environment, and are not limited here.

[0065] As shown in FIG2 , each sub-pixel SPX includes a transistor 01 and a pixel electrode 02. A row of sub-pixels SPX corresponds to a gate line, and a column of sub-pixels SPX corresponds to a data line. The gate of transistor 01 is electrically coupled to the corresponding gate line, the source of transistor 01 is electrically coupled to the corresponding data line, and the drain of transistor 01 is electrically coupled to pixel electrode 02. It should be noted that the pixel array structure disclosed herein can also be a dual-gate structure, i.e., two gate lines are provided between two adjacent rows of pixels. This arrangement can reduce the number of data lines by half, i.e., some data lines are included between two adjacent columns of pixels, while some data lines are not included between two adjacent columns of pixels. The specific pixel arrangement structure, data lines, and scan line arrangement are not limited.

[0066] It should be noted that the display panel in the embodiment of the present disclosure may be a liquid crystal display panel. For example, a liquid crystal display panel generally includes an upper substrate and a lower substrate of a pair of cells, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate. When displaying an image, due to the voltage difference between the data voltage applied to the pixel electrode of each sub-pixel SPX and the common electrode voltage on the common electrode, this voltage difference can form an electric field, thereby causing the liquid crystal molecules to deflect under the action of the electric field. Due to the different intensities of the electric field, the degree of deflection of the liquid crystal molecules is different, resulting in different transmittances of the sub-pixels SPX, so that the sub-pixels SPX can achieve different grayscale brightness, thereby realizing image display.

[0067] In order for the timing controller, level conversion circuit, gate drive circuit and source drive circuit to work, they also need to be powered. Therefore, a power management circuit 510 is also provided in the display device. The power management circuit receives the second power supply voltage VCC to generate a corresponding voltage to power the timing controller, level conversion circuit and gate drive circuit. However, with the increase in display demand, the resolution and refresh rate of the display panel continue to increase. However, the higher the refresh rate, the greater the power consumption and the transmission loss, resulting in more serious heat generation, which will bring certain risks. For example, a high refresh rate product with a refresh rate of 480Hz (such as a gaming product), when displaying a heavy-load screen (for example, an H1line 255 heavy-load screen), due to the large input current, the second power supply voltage VCC drops significantly (Drop), resulting in a decrease in the direct current-direct current (DC-DC) conversion efficiency in the power management circuit, affecting the normal operation of the relevant modules in the power management circuit, and ultimately causing abnormal display on the display panel. To address this issue, existing solutions use two power management circuits to generate voltages for the timing controller, level conversion circuit, gate driver circuit, and source driver circuit, respectively, to distribute power to different circuits. However, using two power management circuits increases the circuit space occupied and the circuit cost. To this end, the embodiments of the present disclosure provide a display device that not only improves heat generation and reduces display anomalies, but also saves circuit space and reduces costs.

[0068] The display device provided by the embodiment of the present disclosure, as shown in FIG3 , includes: a voltage conversion circuit 520 and a power management circuit 510. The voltage conversion circuit 520 is configured to receive a backlight supply voltage VBL, convert the backlight supply voltage VBL, generate a first supply voltage AVDD, and output the first supply voltage AVDD. The backlight supply voltage VBL is configured to supply power to the backlight control circuit 530, so that the backlight control circuit 530 controls the backlight module 200 to emit light. Furthermore, the power management circuit 510 is coupled to the voltage conversion circuit 520. The power management circuit 510 is configured to receive a second supply voltage VCC and a first supply voltage AVDD, generate a first driving voltage VGZ1 based on the second supply voltage VCC, and output the first driving voltage VGZ1 to the driving circuit 600, and generate a second driving voltage VGZ2 based on the first supply voltage AVDD, and output the second driving voltage VGZ2 to the display panel 100.

[0069] The display device provided in the embodiments of the present disclosure utilizes a voltage conversion circuit, which receives a backlight supply voltage from the backlight control circuit as its power input. This allows the backlight supply voltage to be converted and then output to a first supply voltage to the power management circuit. This allows the power management circuit to have two input power voltages: one directly from the second supply voltage, and the other from the first supply voltage generated by the backlight supply voltage after conversion by the voltage conversion circuit. Consequently, the power management circuit can generate different types of driving voltages based on these two power voltages. The power management circuit generates a first driving voltage based on the second supply voltage and outputs it to the driving circuit to operate the driving circuit. Furthermore, the power management circuit generates a second driving voltage based on the first supply voltage and outputs it to the display panel to operate the display panel. This configuration alleviates the problem of excessive current at the port providing the second supply voltage, improves the efficiency of the power management circuit, mitigates heat generation, and reduces the risk of display anomalies. Furthermore, the architecture of a power management circuit coupled with a voltage conversion circuit saves circuit space and reduces costs compared to an architecture using two power management circuits.

[0070] In some examples, the second power supply voltage VCC can be set to 3.1V to 3.5V, and the backlight power supply voltage VBL can be set to 3V to 24V or 5V to 21V. Generally speaking, the second power supply voltage VCC can be set to 3.3V, and the backlight power supply voltage VBL can be set to 12V. Based on this, the voltage conversion circuit 520 can generate the first power supply voltage AVDD by stepping down the backlight power supply voltage VBL. In a specific implementation, the voltage conversion circuit 520 is configured to step down the backlight power supply voltage VBL to generate the first power supply voltage AVDD.

[0071] For example, as shown in FIG4 , the voltage conversion circuit 520 includes a step-down circuit 521. The input of the step-down circuit 521 is configured to receive the backlight supply voltage VBL. The output of the step-down circuit 521 is coupled to the power management circuit 510. Furthermore, the output of the step-down circuit 521 is configured to output the first supply voltage AVDD. This configuration allows the voltage of the first supply voltage AVDD to be lower than the voltage of the backlight supply voltage VBL and prevents the voltage of the first supply voltage AVDD from fluctuating with the voltage of the backlight supply voltage VBL, thereby achieving a constant voltage output.

[0072] For example, the step-down circuit 521 can be configured as a step-down IC (Buck IC). The power management circuit 510 can be configured as a power management IC (PMIC). This configuration enables a single PMIC+Buck IC architecture to be formed in the embodiment of the present disclosure.

[0073] In a specific implementation, the backlight power supply voltage VBL and the second power supply voltage VCC may be provided by a system circuit. For example, the system circuit may include a system on chip (SOC). Of course, the specific implementation of the system circuit may also adopt other implementation methods, which are not limited here.

[0074] In a specific implementation, as shown in FIG5 , the voltage conversion circuit 520 further includes: a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2. The output end of the step-down circuit 521 is coupled to the power management circuit 510 via the first voltage-dividing resistor R1. A first end of the first voltage-dividing resistor R1 is coupled to the output end of the step-down circuit 521, and a second end of the first voltage-dividing resistor R1 is coupled to the power management circuit 510. A first end of the second voltage-dividing resistor R2 is coupled to the output end of the step-down circuit 521, and a second end of the second voltage-dividing resistor R2 is coupled to ground. With this configuration, different resistances can be set for the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 to achieve the output of the first supply voltage AVDD of different voltages.

[0075] Furthermore, in a specific implementation, the voltage value of the first power supply voltage AVDD satisfies the following formula: out =V FB (1+r1 / r2);

[0076] Among them, V out Represents the voltage value of the first power supply voltage AVDD, V FB Represents the feedback reference voltage (e.g. V FB =0.8V), r1 represents the resistance value of the first voltage-dividing resistor R1, and r2 represents the resistance value of the second voltage-dividing resistor R2.

[0077] In addition, as shown in FIG5 , the ground port of the Buck IC in the voltage conversion circuit 520 is also coupled to the ground terminal.

[0078] In some embodiments, as shown in FIG6 , the power management circuit 510 is further configured to generate and output an enable voltage EXT_EN based on the second power supply voltage VCC. The voltage conversion circuit 520 is further configured to receive the enable voltage EXT_EN and, in response to the enable voltage EXT_EN, perform voltage conversion on the backlight power supply voltage VBL to generate and output the first power supply voltage AVDD. With this configuration, the power management circuit 510 can output the enable voltage EXT_EN to the voltage conversion circuit 520, thereby enabling the voltage conversion circuit 520 and causing the voltage conversion circuit 520 to begin operation. The voltage conversion circuit 520 then performs voltage conversion on the backlight power supply voltage VBL to generate and output the first power supply voltage AVDD.

[0079] In some embodiments, as shown in FIG7 , the power management circuit 510 is configured to generate an enable voltage EXT_EN based on the second power supply voltage VCC after receiving the second power supply voltage VCC and after a delay period DLY. It should be noted that in actual applications, when the second power supply voltage VCC is input to the power management circuit 510, there will be a buffering process, and the voltage value of the second power supply voltage VCC gradually increases from 0V to a target voltage value (e.g., 3.3V). In the embodiment of the present disclosure, the power management circuit 510 receives the second power supply voltage VCC, which may refer to the buffering process or after the second power supply voltage VCC is increased to the target voltage value. Based on this, the power management circuit 510 can control the output timing of the first power supply voltage AVDD through the enable voltage EXT_EN. In addition, the delay period can be set according to the actual pull-up time required for the first power supply voltage AVDD in actual applications.

[0080] In some embodiments, as shown in FIG3 and FIG4 , the display device further includes a backlight control circuit 530 . The backlight control circuit 530 is configured to receive a backlight supply voltage VBL and be powered by the backlight supply voltage VBL. Furthermore, the backlight control circuit 530 is coupled to the backlight module 200 . The backlight control circuit 530 operates after being powered by the backlight supply voltage VBL and can control the backlight module to emit light.

[0081] In some embodiments, as shown in FIG8 , the power management circuit 510 is configured to be coupled to the gate driving circuit 110 in the display panel. The second driving voltage VGZ2 may include a first reference voltage VGH, which is configured to increase the level of the signal to the gate driving circuit 110, thereby enabling the gate driving circuit 110 to generate a gate scanning signal in combination with the first reference voltage VGH.

[0082] In some embodiments, as shown in FIG8 , the second driving voltage VGZ2 may include: a first reference voltage VGH greater than a second reference voltage VGL. Furthermore, the second reference voltage VGL is configured to provide a low-level signal to the gate driving circuit 110, thereby enabling the gate driving circuit 110 to generate a gate scanning signal in combination with the second reference voltage VGL.

[0083] In a specific implementation, as shown in conjunction with FIG3 and FIG8 , the driver circuit 600 may include a timing controller 300 coupled to the power management circuit 510. The first drive voltage VGZ1 includes at least one of a timing supply voltage (e.g., VCORE / VDDIO) and a timing drive logic voltage DVDD. Furthermore, the timing controller 300 is configured to receive the timing supply voltage (e.g., VCORE / VDDIO), be powered by the timing supply voltage (e.g., VCORE / VDDIO), and begin operation in response to the timing supply voltage (e.g., VCORE / VDDIO). Furthermore, the timing controller 300 is configured to receive the timing drive logic voltage DVDD and output a timing control signal in response to the timing drive logic voltage DVDD. For example, the timing control signal may be input to the level shifter circuit, the gate driver circuit 110, and the source driver circuit 120 to control the operation of the level shifter circuit, the gate driver circuit 110, and the source driver circuit 120, respectively.

[0084] In a specific implementation, as shown in conjunction with FIG3 and FIG8 , the driver circuit 600 further includes a level shifter circuit 400 coupled to the power management circuit 510. The level shifter circuit 400 is configured to receive a sequential drive logic voltage DVDD and output a clock signal in response to the sequential drive logic voltage DVDD. This clock signal is input to the gate driver circuit 110, thereby enabling the gate driver circuit 110 to generate a gate scan signal in conjunction with the clock signal.

[0085] In a specific implementation, as shown in conjunction with FIG3 and FIG8 , the driver circuit 600 may include a source driver circuit 120 coupled to the power management circuit 510. The first driver voltage VGZ1 may include a source driver supply voltage AVEE. The source driver circuit 120 is configured to receive the source driver supply voltage AVEE, generate a data voltage based on the source driver supply voltage AVEE, and output the data voltage. Specifically, the source driver circuit 120 may combine the source driver supply voltage AVEE and display data to generate the data voltage, and input the data voltage to the data line of the display panel.

[0086] It should be noted that the first driving voltage VGZ1 may also include other voltages, which are not limited here.

[0087] This application takes the display device shown in Figure 8 as an example, in which the power management circuit 510 can be set to PMIC, and the buck circuit 521 can be set to a buck chip Buck IC. The single PMIC+Buck IC architecture shown in Figure 8 of the present disclosure is compared with the single PMIC architecture in the prior art: the comparison conditions and results are shown in Table 1 below: The refresh frequency of the display panel is 480Hz, and the display panel displays a heavy-load screen H1line255 as the test object, VCC is 3.0~3.6V, and the line impedance R _path Both are 0.3Ω. In the single PMIC architecture, the VCC current value Iin reaches 1.82A, and the VCC Drop voltage V drop =0.65V, Line loss P path =0.99W, PMIC efficiency P _Eff In the single PMIC+Buck IC architecture shown in FIG8 of the embodiment of the present disclosure, the VCC current value Iin is 0.93A, V drop =0V, line loss P path =0.28W, PMIC efficiency P _Eff At 80-85%. It can be seen from this that in a single PMIC architecture, when the VCC voltage drops to near the critical value, it is easy to trigger under-voltage lockout (UVLO) (generally 2.2V), which may cause a black screen risk. In the single PMIC+Buck IC architecture shown in Figure 8 of the disclosed embodiment, VBL bears part of the power consumption generated by the driver, which significantly improves the VCC voltage drop, reduces power loss, and improves efficiency.

[0088] Table 1

[0089] The single PMIC+Buck IC architecture shown in FIG8 of the present disclosure is compared with the single PMIC architecture in the prior art in terms of heat generation: the comparison conditions and results are as follows: the refresh rate of the display panel is 480Hz, and the display panel displays the heavy-load screen H1line255 as the test object, which is displayed continuously for 30 minutes. The temperature of the PMIC surface area is tested by a thermal imager, and the results are as follows: in the single PMIC architecture, the PMIC surface temperature reaches 82.7 degrees Celsius. The PMIC is likely to trigger OTP (Over Temperature Protection) when working for a long time, causing the PMIC to shut down abnormally and increasing the risk of abnormal black screen. However, in the single PMIC+Buck IC architecture in the embodiment of the present disclosure, the PMIC surface temperature is significantly reduced, and the measured temperature is only 49.5 degrees Celsius. There is no risk of overheating triggering OTP during long-term use.

[0090] Comparing the circuit space occupied by the single PMIC + Buck IC architecture shown in FIG8 of this disclosure with the dual PMIC architecture of the prior art, the single PMIC + Buck IC architecture employed in the embodiments of this application occupies less circuit space on a circuit board (e.g., a printed circuit board (PCB)). Furthermore, evaluation and calculations show that the single PMIC + Buck IC architecture can save approximately 25% of the circuit space occupied by the dual PMIC architecture.

[0091] A cost comparison is made between the single PMIC+Buck IC architecture shown in FIG8 of the present disclosure and the dual PMIC architecture in the prior art: Since the market price of PMICs used in high refresh rate products (such as gaming products) is high, while the price of Buck ICs is low, after evaluation and calculation, the cost of the single PMIC+Buck IC architecture can be reduced by approximately 30% compared to the dual PMIC architecture.

[0092] The present disclosure also provides a driving control method for a display device, as shown in FIG9 , including:

[0093] S10. The voltage conversion circuit receives a backlight power supply voltage, performs voltage conversion on the backlight power supply voltage, generates a first power supply voltage, and outputs the first power supply voltage; wherein the backlight power supply voltage is configured to supply power to the backlight control circuit;

[0094] S20 , the power management circuit receives the second power supply voltage and the first power supply voltage, generates a first driving voltage according to the second power supply voltage and outputs it to the driving circuit, and generates a second driving voltage according to the first power supply voltage and outputs it to the display panel.

[0095] In a specific implementation, performing voltage conversion on the backlight power supply voltage to generate the first power supply voltage includes:

[0096] The backlight power supply voltage is stepped down to generate a first power supply voltage.

[0097] In specific implementation, it also includes:

[0098] The power management circuit generates and outputs an enable voltage according to the second power supply voltage;

[0099] The voltage conversion circuit receives an enable voltage, performs voltage conversion on a backlight power supply voltage in response to the enable voltage, generates a first power supply voltage, and outputs the first power supply voltage.

[0100] In a specific implementation, generating the enable voltage according to the second supply voltage includes:

[0101] After receiving the second power supply voltage and after a delay period, an enable voltage is generated according to the second power supply voltage.

[0102] In a specific implementation, the power management circuit is configured to be coupled to a gate driving circuit in the display panel;

[0103] The second driving voltage includes: at least one of a first reference voltage and a second reference voltage, the first reference voltage being greater than the second reference voltage;

[0104] The first reference voltage increases the level signal to the gate drive circuit;

[0105] The second reference voltage provides a low level signal to the gate driving circuit.

[0106] In a specific implementation, the driving circuit includes: a timing controller, the timing controller is coupled to the power management circuit, and the first driving voltage includes: at least one of a timing supply voltage and a timing driving logic voltage;

[0107] The drive control method further includes:

[0108] The timing controller receives a timing power supply voltage, adopts the timing power supply voltage for power supply, and starts working in response to the timing power supply voltage, and receives a timing driving logic voltage, and outputs a timing control signal in response to the timing driving logic voltage.

[0109] In a specific implementation, the driving circuit includes: a source driving circuit coupled to a power management circuit; the first driving voltage includes: a source driving supply voltage;

[0110] The drive control method further includes:

[0111] The source driving circuit receives a source driving power supply voltage, generates a data voltage according to the source driving power supply voltage, and outputs the data voltage.

[0112] In a specific implementation, the driving control method further includes: the backlight control circuit receives a backlight power supply voltage to adopt the backlight power supply voltage for power supply.

[0113] The following describes the driving control method of the display device provided by the embodiment of the present disclosure, taking the display device shown in FIG8 as an example, wherein the power management circuit can be configured as a PMIC, and the buck circuit can be configured as a buck chip Buck IC.

[0114] After receiving the second power supply voltage VCC and a delay period DLY, the PMIC generates an enable voltage EXT_EN based on the second power supply voltage VCC and outputs the enable voltage EXT_EN to the Buck IC. The Buck IC receives the enable voltage EXT_EN and the backlight power supply voltage VBL. In response to the enable voltage EXT_EN, the Buck IC performs a step-down conversion on the backlight power supply voltage VBL using a first voltage divider resistor R1 and a second voltage divider resistor R2 to generate a first power supply voltage AVDD. The first power supply voltage AVDD is then output to the PMIC. The backlight power supply voltage VBL is also provided to the backlight control circuit 530 to power the backlight control circuit 530, enabling it to operate and control the backlight module 200 to emit light.

[0115] The PMIC receives a second power supply voltage VCC and generates a timing power supply voltage (e.g., VCORE / VDDIO), a timing drive logic voltage DVDD, and a source drive power supply voltage AVEE based on the second power supply voltage VCC. The timing controller 300 receives the timing power supply voltage (e.g., VCORE / VDDIO), uses the timing power supply voltage (e.g., VCORE / VDDIO) for power supply, and begins operation in response to the timing power supply voltage (e.g., VCORE / VDDIO). Furthermore, the timing controller 300 receives the timing drive logic voltage DVDD and outputs a timing control signal in response to the timing drive logic voltage DVDD. This timing control signal is input to the level shifter circuit, the gate driver circuit 110, and the source driver circuit 120 to control their respective operations. The source driver circuit 120 can receive the source drive power supply voltage AVEE, combine the source drive power supply voltage AVEE with display data, generate a data voltage, and input the data voltage to the data lines of the display panel.

[0116] The PMIC receives a first power supply voltage AVDD, and generates a first reference voltage VGH and a second reference voltage VGL according to the first power supply voltage AVDD. The first reference voltage VGH and the second reference voltage VGL are input to the gate drive circuit 110. The gate drive circuit 110 can output a gate scan signal to the gate line according to the input first reference voltage VGH and the second reference voltage VGL and the clock signal, thereby driving the gate line.

[0117] The present disclosure also provides a display device including the display panel provided in the present disclosure. The display device solves the problem in a similar manner to the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be repeated here.

[0118] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0119] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0120] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display device, comprising: A voltage conversion circuit is configured to receive a backlight power supply voltage, perform voltage conversion on the backlight power supply voltage, generate a first power supply voltage, and output the first power supply voltage; The backlight supply voltage is configured to supply power to a backlight control circuit; The power management circuit is coupled to the voltage conversion circuit and is configured to receive a second power supply voltage and the first power supply voltage, generate a first driving voltage according to the second power supply voltage and output it to the driving circuit, and generate a second driving voltage according to the first power supply voltage and output it to the display panel.

2. The display device according to claim 1, wherein: The voltage conversion circuit is configured to generate the first power supply voltage after performing a voltage reduction conversion on the backlight power supply voltage.

3. The display device according to claim 2, wherein: The voltage conversion circuit includes a step-down circuit; The input end of the step-down circuit is configured to receive the backlight power supply voltage, the output end of the step-down circuit is coupled to the power management circuit, and the output end of the step-down circuit is configured to output the first power supply voltage.

4. The display device according to claim 3, wherein: The voltage conversion circuit further includes: a first voltage-dividing resistor and a second voltage-dividing resistor, and the output end of the voltage-reducing circuit is coupled to the power management circuit through the first voltage-dividing resistor; A first end of the first voltage-dividing resistor is coupled to the output end of the step-down circuit, and a second end of the first voltage-dividing resistor is coupled to the power management circuit; A first end of the second voltage-dividing resistor is coupled to the output end of the voltage-reducing circuit, and a second end of the second voltage-dividing resistor is coupled to the ground end.

5. The display device according to claim 4, wherein: The voltage value of the first power supply voltage satisfies the following formula: V out =V FB (1+r1 / r2); Among them, V out represents the voltage value of the first supply voltage, V FB Represents the feedback reference voltage, r1 represents the resistance value of the first voltage-dividing resistor, and r2 represents the resistance value of the second voltage-dividing resistor.

6. The display device according to any one of claims 1 to 5, wherein: The power management circuit is further configured to generate and output an enable voltage according to the second supply voltage; The voltage conversion circuit is further configured to receive the enable voltage, and in response to the enable voltage, perform voltage conversion on the backlight power supply voltage to generate and output a first power supply voltage.

7. The display device according to claim 6, wherein: The power management circuit is configured to generate the enable voltage according to the second supply voltage after receiving the second supply voltage and a delay period has passed.

8. The display device according to any one of claims 1 to 7, wherein: The power management circuit is configured to be coupled to a gate driving circuit in the display panel; The second driving voltage includes: at least one of a first reference voltage and a second reference voltage, the first reference voltage being greater than the second reference voltage; The first reference voltage is configured to increase a level signal to the gate drive circuit; The second reference voltage is configured to provide a low level signal to the gate driving circuit.

9. The display device according to any one of claims 1 to 8, wherein: The driving circuit comprises: a timing controller, the timing controller is coupled to the power management circuit, and the first driving voltage comprises: at least one of a timing supply voltage and a timing driving logic voltage; The timing controller is configured to receive the timing power supply voltage, adopt the timing power supply voltage for power supply, start working in response to the timing power supply voltage, and receive the timing drive logic voltage, and output a timing control signal in response to the timing drive logic voltage.

10. The display device according to claim 9, wherein: The driving circuit further includes: a level conversion circuit, the level conversion circuit being coupled to the power management circuit; The level conversion circuit is configured to receive the timing driving logic voltage, and output a clock signal in response to the timing driving logic voltage.

11. The display device according to any one of claims 1 to 10, wherein: The driving circuit includes: a source driving circuit, the source driving circuit is coupled to the power management circuit; the first driving voltage includes: a source driving supply voltage; The source driving circuit is configured to receive the source driving power supply voltage, generate and output a data voltage according to the source driving power supply voltage.

12. The display device according to any one of claims 1 to 11, wherein: The display device further includes: the backlight control circuit, which is configured to receive the backlight power supply voltage to adopt the backlight power supply voltage for power supply.

13. A driving control method for a display device according to any one of claims 1 to 12, comprising: The voltage conversion circuit receives a backlight power supply voltage, performs voltage conversion on the backlight power supply voltage, generates a first power supply voltage, and outputs the first power supply voltage; wherein the backlight power supply voltage is configured to supply power to the backlight control circuit; The power management circuit receives a second power supply voltage and the first power supply voltage, generates a first driving voltage according to the second power supply voltage and outputs it to the driving circuit, and generates a second driving voltage according to the first power supply voltage and outputs it to the display panel.

14. The driving control method according to claim 13, wherein: The step of converting the backlight power supply voltage to generate a first power supply voltage comprises: The backlight power supply voltage is stepped down to generate the first power supply voltage.

15. The drive control method according to claim 13 or 14, wherein: Also includes: The power management circuit generates and outputs an enable voltage according to the second supply voltage; The voltage conversion circuit receives the enable voltage, and in response to the enable voltage, performs voltage conversion on the backlight power supply voltage to generate a first power supply voltage and outputs the first power supply voltage.

16. The driving control method according to claim 15, wherein: The step of generating an enable voltage according to the second supply voltage comprises: After receiving the second power supply voltage and after a delay period, the enable voltage is generated according to the second power supply voltage.

17. The drive control method according to any one of claims 13 to 16, wherein: The power management circuit is configured to be coupled to a gate driving circuit in the display panel; The second driving voltage includes: at least one of a first reference voltage and a second reference voltage, The first reference voltage is greater than the second reference voltage; The first reference voltage increases the level signal to the gate drive circuit; The second reference voltage provides a low level signal to the gate driving circuit.

18. The drive control method according to any one of claims 13 to 17, wherein: The driving circuit comprises: a timing controller, the timing controller is coupled to the power management circuit, and the first driving voltage comprises: at least one of a timing supply voltage and a timing driving logic voltage; The drive control method further includes: The timing controller receives the timing power supply voltage, adopts the timing power supply voltage for power supply, starts working in response to the timing power supply voltage, and receives the timing driving logic voltage, and outputs a timing control signal in response to the timing driving logic voltage.

19. The drive control method according to any one of claims 13 to 18, wherein: The driving circuit includes: a source driving circuit, the source driving circuit is coupled to the power management circuit; the first driving voltage includes: a source driving supply voltage; The drive control method further includes: The source driving circuit receives the source driving power supply voltage, generates and outputs a data voltage according to the source driving power supply voltage.

20. The drive control method according to any one of claims 13 to 19, wherein: The driving control method further includes: the backlight control circuit receiving the backlight power supply voltage to adopt the backlight power supply voltage for power supply.

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