Driving circuit and display apparatus

Abstract

A driving circuit, comprising a driving signal generation circuit, a control signal generation circuit and a control circuit, wherein under the control of a first clock signal and a second clock signal, the driving signal generation circuit generates an nth-stage driving signal and outputs same by means of an nth-stage driving signal output end, n being a positive integer; the control signal generation circuit is used for outputting a control signal to a control signal end on the basis of an enable signal; and under the control of the control signal, the control circuit outputs a signal to an nth-stage driving output end. The nth-stage driving signal or an invalid voltage signal can be accurately output to the nth-stage driving output end, so that partial refresh can be accurately performed.

Description

Driving circuit and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311170623.9 filed in China on September 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a driving circuit and a display device. Background Art

[0004] In related art, a drive circuit typically includes a drive signal generation circuit and a control circuit directly controlled by an enable signal. When the pulse width of the n-level drive signal provided by the drive signal generation circuit is 1 hour (1 hour is the scanning time for a single row), the control circuit directly controlled by the enable signal can be used to control the output of the n-level drive signal or an invalid voltage signal. However, with the development of pixels and the diversification of pixel control signals, the pulse width of the n-level drive signal may exceed 1 hour, causing the n-level drive signal waveform to cross the changing edge (rising or falling edge) of the enable signal. As a result, only a portion of the n-level drive signal can be output, which will cause abnormal pixel operation.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising a driving signal generating circuit, a control signal generating circuit, and a control circuit;

[0007] The drive signal generating circuit is electrically connected to the first clock signal line and the second clock signal line, respectively, and is configured to generate and output an n-level drive signal through the n-level drive signal output terminal under the control of a first clock signal provided by the first clock signal line and a second clock signal provided by the second clock signal line; n is a positive integer;

[0008] The control signal generating circuit is electrically connected to the enable signal line and the control signal terminal respectively, and is used to output a control signal to the control signal terminal according to the enable signal provided by the enable signal line;

[0009] The control circuit is electrically connected to the control signal terminal and the n-th stage driving signal output terminal respectively, and is used to output a signal to the n-th stage driving output terminal under the control of the control signal.

[0010] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes an output inverting circuit;

[0011] The output inversion circuit is electrically connected to the n-th stage driving signal output terminal, and is used to invert the n-th stage driving signal to obtain and output the n-th stage inverted driving signal through the n-th stage inverted signal output terminal.

[0012] Optionally, the control circuit includes a first control circuit, a second control circuit and a first energy storage circuit;

[0013] The first control circuit is electrically connected to the control signal terminal, the n-th drive signal output terminal, the first control voltage line, the second control voltage line, and the control output terminal, respectively, and is configured to control, under the control of the control signal, connection or disconnection between the control output terminal and the first control voltage line; under the control of the n-level drive signal outputted by the n-level drive signal terminal, control connection or disconnection between the control output terminal and the first control voltage line; and under the control of the n-level drive signal and the control signal, control connection or disconnection between the control output terminal and the second control voltage line;

[0014] The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line, and the second voltage line, respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal;

[0015] The first energy storage circuit is electrically connected to the control output terminal and is used to maintain the potential of the control output terminal.

[0016] Optionally, the control circuit further includes a second energy storage circuit;

[0017] The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal.

[0018] Optionally, the control signal generating circuit is also electrically connected to the n-1th level drive signal output terminal, the n-1th level inverted signal output terminal, the nth level drive signal output terminal and the nth level inverted signal output terminal, respectively, and is used to control the connection or disconnection between the enable signal line and the control signal terminal under the control of the n-1th level drive signal, the n-1th level inverted drive signal, the nth level drive signal and the nth level inverted drive signal.

[0019] Optionally, the control signal generating circuit is used to invert the enable signal to generate an inverted enable signal, and output the inverted enable signal through the control signal terminal.

[0020] Optionally, the first control circuit includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the second control circuit includes a fifth control transistor and a sixth control transistor; the first energy storage circuit includes a first capacitor; the first control voltage line is a first voltage line, and the second control voltage line is a second voltage line;

[0021] The gate of the first control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the first control transistor is electrically connected to the first voltage line, and the second electrode of the first control transistor is electrically connected to the control output terminal;

[0022] The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the second control transistor is electrically connected to the second voltage line;

[0023] The gate of the third control transistor is electrically connected to the control signal terminal, the first electrode of the third control transistor is electrically connected to the first voltage line, and the second electrode of the third control transistor is electrically connected to the control output terminal;

[0024] The gate of the fourth control transistor is electrically connected to the n-th stage driving signal output terminal, and the first electrode of the fourth control transistor is electrically connected to the control output terminal;

[0025] The gate of the fifth control transistor is electrically connected to the control output terminal, the first electrode of the fifth control transistor is electrically connected to the first voltage line, and the second electrode of the fifth control transistor is electrically connected to the nth driving output terminal;

[0026] The gate of the sixth control transistor is electrically connected to the control output terminal, the first electrode of the sixth control transistor is electrically connected to the nth driving output terminal, and the second electrode of the sixth control transistor is electrically connected to the second voltage line;

[0027] A first end of the first capacitor is electrically connected to the control output end, and a second end of the first capacitor is electrically connected to the second voltage line.

[0028] Optionally, the first control circuit includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the second control circuit includes a fifth control transistor and a sixth control transistor; the first energy storage circuit includes a first capacitor; the first control voltage line is the second voltage line, and the second control voltage line is the first voltage line;

[0029] The gate of the first control transistor is electrically connected to the control signal terminal, the first electrode of the first control transistor is electrically connected to the second electrode of the third control transistor, and the second electrode of the first control transistor is electrically connected to the control output terminal;

[0030] The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the control output terminal, and the second electrode of the second control transistor is electrically connected to the second voltage line;

[0031] The gate of the third control transistor is electrically connected to the n-th stage driving signal output terminal, and the first electrode of the third control transistor is electrically connected to the first voltage line;

[0032] The gate of the fourth control transistor is electrically connected to the n-th stage drive signal output terminal, the first electrode of the fourth control transistor is electrically connected to the control output terminal, and the second electrode of the fourth control transistor is electrically connected to the second voltage line;

[0033] The gate of the fifth control transistor is electrically connected to the control output terminal, the first electrode of the fifth control transistor is electrically connected to the first voltage line, and the second electrode of the fifth control transistor is electrically connected to the nth driving output terminal;

[0034] The gate of the sixth control transistor is electrically connected to the control output terminal, the first electrode of the sixth control transistor is electrically connected to the nth driving output terminal, and the second electrode of the sixth control transistor is electrically connected to the second voltage line;

[0035] A first end of the first capacitor is electrically connected to the control output end, and a second end of the first capacitor is electrically connected to the second voltage line.

[0036] Optionally, the second energy storage circuit includes a second capacitor;

[0037] A first end of the second capacitor is electrically connected to the control signal end, and a second end of the second capacitor is electrically connected to the second voltage line.

[0038] Optionally, the control signal generating circuit includes a seventh control transistor, an eighth control transistor, a ninth control transistor and a tenth control transistor;

[0039] The gate of the seventh control transistor is electrically connected to the (n-1)th stage driving signal output terminal, the first electrode of the seventh control transistor is electrically connected to the enable signal line, and the second electrode of the seventh control transistor is electrically connected to the first electrode of the tenth control transistor;

[0040] The gate of the eighth control transistor is electrically connected to the (n-1)th stage inverting signal output terminal, the first electrode of the eighth control transistor is electrically connected to the enable signal line, and the second electrode of the eighth control transistor is electrically connected to the first electrode of the ninth control transistor;

[0041] The gate of the ninth control transistor is electrically connected to the nth stage driving signal output terminal, the first electrode of the ninth control transistor is electrically connected to the first electrode of the tenth control transistor, and the second electrode of the ninth control transistor is electrically connected to the control signal terminal;

[0042] The gate of the tenth control transistor is electrically connected to the n-th stage inverting signal output terminal, and the second electrode of the tenth control transistor is electrically connected to the control signal terminal;

[0043] The seventh control transistor and the tenth control transistor are both n-type transistors, and the eighth control transistor and the ninth control transistor are both p-type transistors; or,

[0044] The seventh control transistor and the tenth control transistor are both p-type transistors, and the eighth control transistor and the ninth control transistor are both n-type transistors.

[0045] Optionally, the control signal generating circuit includes a seventh control transistor and an eighth control transistor;

[0046] The gate of the seventh control transistor is electrically connected to the enable signal line, the first electrode of the seventh control transistor is electrically connected to the first voltage line, and the second electrode of the seventh control transistor is electrically connected to the control signal terminal;

[0047] The gate of the eighth control transistor is electrically connected to the enable signal line, the first electrode of the eighth control transistor is electrically connected to the control signal terminal, and the second electrode of the eighth control transistor is electrically connected to the second voltage line;

[0048] The seventh control transistor is a p-type transistor, and the eighth control transistor is an n-type transistor; or the seventh control transistor is an n-type transistor, and the eighth control transistor is a p-type transistor.

[0049] Optionally, the output inverting circuit includes an eleventh control transistor and a twelfth control transistor;

[0050] The gate of the eleventh control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the eleventh control transistor is electrically connected to the n-th stage inverting signal output terminal, and the second electrode of the eleventh control transistor is electrically connected to the second voltage line;

[0051] The gate of the twelfth control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the twelfth control transistor is electrically connected to the first voltage line, and the second electrode of the twelfth control transistor is electrically connected to the n-th stage inverting signal output terminal.

[0052] Optionally, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit, and an output circuit; the first clock signal line includes a first first clock signal line, and the second clock signal line includes a first second clock signal line;

[0053] The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node;

[0054] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal, and the second voltage line, respectively, and is configured to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line;

[0055] The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node, and the first voltage line, respectively, and is configured to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0056] The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0057] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0058] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0059] Optionally, the first node control circuit includes a first transistor, a second transistor, and a third transistor; the second output node control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0060] The gate of the first transistor is electrically connected to the first first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor;

[0061] The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the first electrode of the second transistor is electrically connected to the first first clock signal line, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor;

[0062] The gate of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the first node;

[0063] The gate of the fourth transistor is electrically connected to the first first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;

[0064] The gate of the fifth transistor is electrically connected to the second voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node;

[0065] The gate of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node;

[0066] The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the first voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor;

[0067] The second node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a third capacitor;

[0068] The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the first second clock signal line, and the second electrode of the eighth transistor is electrically connected to the first intermediate node;

[0069] The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node;

[0070] The gate of the tenth transistor is electrically connected to the first first clock signal line, the first electrode of the tenth transistor is electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0071] The gate of the eleventh transistor is electrically connected to the second voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0072] The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the first intermediate node;

[0073] The first output node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fourth capacitor;

[0074] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first-second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node;

[0075] The gate of the thirteenth transistor is electrically connected to the first-second clock signal line, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node;

[0076] The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the first electrode of the fourteenth transistor is electrically connected to the first voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first output node;

[0077] The first plate of the fourth capacitor is electrically connected to the first node, and the second plate of the fourth capacitor is electrically connected to the second intermediate node;

[0078] The potential maintaining circuit includes a fifth capacitor;

[0079] The first plate of the fifth capacitor is electrically connected to the first output node, and the second plate of the fifth capacitor is electrically connected to the first voltage line;

[0080] The output circuit includes a fifteenth transistor and a sixteenth transistor;

[0081] The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage driving signal output terminal;

[0082] The gate of the sixteenth transistor is electrically connected to the second output node, the first electrode of the sixteenth transistor is electrically connected to the n-th stage driving signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage line.

[0083] Optionally, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit, and an output circuit; the first clock signal line includes a second first clock signal line, and the second clock signal line includes a second second clock signal line;

[0084] The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node;

[0085] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal, and the second voltage line, respectively, and is configured to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line;

[0086] The first output node control circuit is electrically connected to the first output node, the first node, the second second-clock signal line, the second intermediate node, the second output node, and the first voltage line, respectively, and is configured to control the second intermediate node to be connected to the second second-clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second-clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0087] The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0088] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0089] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0090] Optionally, the first node control circuit includes a first transistor, a second transistor, and a third transistor; the second output node control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0091] The gate of the first transistor is electrically connected to the second first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor;

[0092] The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the first electrode of the second transistor is electrically connected to the second first clock signal line, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor;

[0093] The gate of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the first node;

[0094] The gate of the fourth transistor is electrically connected to the second first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;

[0095] The gate of the fifth transistor is electrically connected to the second voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node;

[0096] The gate of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node;

[0097] The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the first voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor;

[0098] The second node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a third capacitor;

[0099] The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the second second clock signal line, and the second electrode of the eighth transistor is electrically connected to the first intermediate node;

[0100] The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node;

[0101] The gate of the tenth transistor is electrically connected to the second first clock signal line, the first electrode of the tenth transistor is electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0102] The gate of the eleventh transistor is electrically connected to the second voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0103] The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the first intermediate node;

[0104] The first output node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fourth capacitor;

[0105] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node;

[0106] The gate of the thirteenth transistor is electrically connected to the second second clock signal line, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node;

[0107] The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the first electrode of the fourteenth transistor is electrically connected to the first voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first output node;

[0108] The first plate of the fourth capacitor is electrically connected to the first node, and the second plate of the fourth capacitor is electrically connected to the second intermediate node;

[0109] The potential maintaining circuit includes a fifth capacitor;

[0110] The first plate of the fifth capacitor is electrically connected to the first output node, and the second plate of the fifth capacitor is electrically connected to the first voltage line;

[0111] The output circuit includes a fifteenth transistor and a sixteenth transistor;

[0112] The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage driving signal output terminal;

[0113] The gate of the sixteenth transistor is electrically connected to the second output node, the first electrode of the sixteenth transistor is electrically connected to the n-th stage driving signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage line.

[0114] Optionally, the drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit, and an output circuit; the first clock signal line includes a third first clock signal line, and the second clock signal line includes a third second clock signal line;

[0115] The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control communication between the first output node and the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control communication between the first output node and the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node;

[0116] The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node, and the first voltage line, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line;

[0117] A first end of the third energy storage circuit is electrically connected to the second output node, a second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electrical energy;

[0118] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node.

[0119] Optionally, the first output node control circuit includes a seventeenth transistor, an eighteenth transistor and a sixth capacitor;

[0120] The gate of the seventeenth transistor is electrically connected to the third first clock signal line, the first electrode of the seventeenth transistor is electrically connected to the second voltage line, and the second electrode of the seventeenth transistor is electrically connected to the first output node;

[0121] a gate of the eighteenth transistor is electrically connected to the second output node, a first electrode of the eighteenth transistor is electrically connected to the third first clock signal line, and a second electrode of the eighteenth transistor is electrically connected to the first output node;

[0122] The first plate of the sixth capacitor is electrically connected to the first output node, and the second plate of the sixth capacitor is electrically connected to the first voltage line;

[0123] The second output node control circuit includes a nineteenth transistor, a twentieth transistor, and a twenty-first transistor; the third energy storage circuit includes a seventh capacitor;

[0124] The gate of the nineteenth transistor is electrically connected to the third first clock signal line, the first electrode of the nineteenth transistor is electrically connected to the input terminal, and the second electrode of the nineteenth transistor is electrically connected to the second output node;

[0125] a gate of the twentieth transistor electrically connected to the first output node, a first electrode of the twentieth transistor electrically connected to the first voltage line, and a second electrode of the twentieth transistor electrically connected to the first electrode of the twenty-first transistor;

[0126] a gate of the twenty-first transistor is electrically connected to the third second clock signal line, and a second electrode of the twenty-first transistor is electrically connected to the second output node;

[0127] The first plate of the seventh capacitor is electrically connected to the second output node, and the second plate of the seventh capacitor is electrically connected to the n-th stage driving signal output terminal;

[0128] The output circuit includes a twenty-second transistor and a twenty-third transistor;

[0129] a gate of the twenty-second transistor is electrically connected to the first output node, a first electrode of the twenty-second transistor is electrically connected to the first voltage line, and a second electrode of the twenty-second transistor is electrically connected to the n-th stage driving signal output terminal;

[0130] a gate of the twenty-third transistor is electrically connected to the second output node, a first electrode of the twenty-third transistor is electrically connected to the n-th stage driving signal output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third second clock signal line;

[0131] The driving circuit further includes a twenty-fourth transistor;

[0132] The second electrode of the 21st transistor is electrically connected to the second output node through the 24th transistor; the gate of the 24th transistor is electrically connected to the second voltage line, the first electrode of the 24th transistor is electrically connected to the second electrode of the 21st transistor, and the second electrode of the 24th transistor is electrically connected to the second output node.

[0133] In at least one embodiment of the present disclosure, a display substrate includes a base and the above-mentioned driving circuit disposed on the base;

[0134] The display substrate includes a display area and a peripheral area; the driving circuit is arranged in the peripheral area.

[0135] Optionally, the driving circuit further includes an output inverting circuit;

[0136] The output inversion circuit is electrically connected to the n-th level driving signal output terminal and the n-th level inverted signal output terminal, respectively, and is used to invert the n-th level driving signal to obtain and output the n-th level inverted driving signal through the n-th level inverted signal output terminal;

[0137] The control signal generating circuit is further electrically connected to the n-1th level driving signal output terminal, the nth level inverted signal output terminal, the nth level driving signal output terminal and the nth level inverted signal output terminal, respectively, and is used to generate a control signal according to an enable signal provided by an enable signal line under the control of the n-1th level driving signal, the n-1th level inverted signal, the nth level driving signal and the nth level inverted signal;

[0138] The n-1th level driving signal output terminal is used to provide the n-1th level driving signal, and the n-1th level inverting signal output terminal is used to provide the n-1th level inverting signal;

[0139] The control signal generating circuit is arranged on a side of the driving signal generating circuit close to the display area.

[0140] Optionally, the control circuit in the driving circuit includes a first control circuit, a second control circuit and a first energy storage circuit; the control circuit is arranged on a side of the driving signal generating circuit close to the display area;

[0141] The first control circuit is electrically connected to the control signal terminal, the n-th drive signal output terminal, the first control voltage line, the second control voltage line, and the control output terminal, respectively, and is configured to control the connection between the control output terminal and the first control voltage line under the control of the control signal, control the connection or disconnection between the control output terminal and the first control voltage line under the control of the n-level drive signal, and control the connection or disconnection between the control output terminal and the second control voltage line under the control of the n-level drive signal and the control signal;

[0142] The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line, and the second voltage line, respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal;

[0143] The first energy storage circuit is electrically connected to the control output terminal, and is used to maintain the potential of the control output terminal;

[0144] The first control voltage line is the first voltage line, and the second control voltage line is the second voltage line; or, the first control voltage line is the second voltage line, and the second control voltage line is the first voltage line.

[0145] Optionally, the control circuit further includes a second energy storage circuit;

[0146] The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal;

[0147] The second energy storage circuit is arranged on a side of the second control circuit away from the display area.

[0148] Optionally, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; the drive signal generating circuit is arranged in the

[0149] The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node;

[0150] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal, and the second voltage line, respectively, and is configured to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line;

[0151] The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node, and the first voltage line, respectively, and is configured to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0152] The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0153] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0154] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0155] Optionally, the driving signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit;

[0156] The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node;

[0157] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal, and the second voltage line, respectively, and is configured to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line;

[0158] The first output node control circuit is electrically connected to the first output node, the first node, the second second-clock signal line, the second intermediate node, the second output node, and the first voltage line, respectively, and is configured to control the second intermediate node to be connected to the second second-clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second-clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0159] The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0160] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0161] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0162] Optionally, the drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit, and an output circuit; the drive signal generating circuit is arranged on a side of the control signal generating circuit included in the drive circuit that is away from the display area; and the transistors in the output circuit are arranged on a side of the transistors included in the drive signal generating circuit other than the transistors in the output circuit that are closer to the display area.

[0163] The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control communication between the first output node and the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control communication between the first output node and the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node;

[0164] The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node, and the first voltage line, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line;

[0165] A first end of the third energy storage circuit is electrically connected to the second output node, a second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electrical energy;

[0166] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node.

[0167] Optionally, the first voltage line includes a first first voltage line and a second first voltage line sequentially arranged in a direction away from the display area, and the second voltage line includes a first second voltage line and a second second voltage line sequentially arranged in a direction away from the display area;

[0168] The orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate;

[0169] The orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first second voltage line on the substrate;

[0170] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0171] An orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0172] Optionally, the orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0173] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0174] Optionally, an orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0175] The orthographic projection of the enabling signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0176] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0177] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0178] Optionally, an orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0179] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0180] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0181] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0182] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0183] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0184] Optionally, the first first voltage line, the second first voltage line, the first second voltage line, the second second voltage line and the enable signal line all extend along a first direction;

[0185] The width of the first first voltage line along the second direction is greater than the width of the second first voltage line along the second direction;

[0186] The width of the first second voltage line along the second direction is greater than the width of the second second voltage line along the second direction;

[0187] The first direction intersects the second direction.

[0188] Optionally, the transistor included in the second control circuit is arranged on a side of the transistor included in the first control circuit close to the display area;

[0189] The control signal generating circuit includes a transistor that is disposed on a side of the second control circuit away from the display area.

[0190] Optionally, an orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

[0191] Optionally, the second voltage line includes a third second voltage line; the third second voltage line is arranged on a side of the second second voltage line away from the display area;

[0192] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

[0193] Optionally, an orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate;

[0194] The enable signal line is arranged on a side of the second first voltage line away from the display area.

[0195] Optionally, the first voltage line includes a first first voltage line, a second first voltage line, and a third first voltage line sequentially arranged in a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged in a direction away from the display area;

[0196] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0197] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0198] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0199] An orthographic projection of the third first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0200] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate;

[0201] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the first node control circuit on the substrate;

[0202] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate.

[0203] Optionally, the first first clock signal line and the first second clock signal line are arranged between the third first voltage line and the third second voltage line;

[0204] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0205] The orthographic projection of the first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second node control circuit on the substrate;

[0206] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first output node control circuit on the substrate;

[0207] The orthographic projections of the first and second clock signal lines on the substrate at least partially overlap with the orthographic projections of the plates of the capacitors included in the first output node control circuit on the substrate;

[0208] The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate.

[0209] Optionally, the first voltage line includes a first first voltage line, a second first voltage line, and a third first voltage line sequentially arranged in a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged in a direction away from the display area;

[0210] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0211] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0212] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0213] An orthographic projection of the third first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0214] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate;

[0215] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the first node control circuit on the substrate;

[0216] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate.

[0217] Optionally, the second first clock signal line and the second second clock signal line are arranged between the third first voltage line and the third second voltage line;

[0218] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0219] An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate;

[0220] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first output node control circuit on the substrate;

[0221] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0222] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate.

[0223] Optionally, the first voltage line includes a first first voltage line, a second first voltage line, a third first voltage line, and a fourth first voltage line sequentially arranged in a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged in a direction away from the display area;

[0224] An orthographic projection of the third first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0225] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0226] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0227] An orthographic projection of the fourth first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0228] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the first node control circuit on the substrate;

[0229] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second node control circuit on the substrate.

[0230] Optionally, the display substrate further includes a first first clock signal line and a first second clock signal line arranged between the fourth first voltage line and the fourth second voltage line;

[0231] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0232] The orthographic projections of the first and second clock signal lines on the substrate at least partially overlap with the orthographic projections of the plates of the capacitors included in the first output node control circuit on the substrate;

[0233] The orthographic projections of the first and second clock signal lines on the substrate at least partially overlap with the orthographic projections of the plates of the capacitors included in the first output node control circuit on the substrate;

[0234] An orthographic projection of the first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the second node control circuit on the substrate;

[0235] An orthographic projection of the first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0236] Optionally, the first voltage line includes a first first voltage line, a second first voltage line, a third first voltage line, and a fourth first voltage line sequentially arranged in a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged in a direction away from the display area;

[0237] An orthographic projection of the third first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0238] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0239] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0240] An orthographic projection of the fourth first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0241] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the first node control circuit on the substrate;

[0242] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second node control circuit on the substrate.

[0243] Optionally, the display substrate further includes a second first clock signal line and a second second clock signal line disposed between the fourth first voltage line and the fourth second voltage line;

[0244] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0245] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0246] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0247] An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second node control circuit on the substrate;

[0248] An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0249] Optionally, the first voltage line includes a first first voltage line, and the second voltage line includes a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged in a direction away from the display area; the enable signal line is provided between the second second voltage line and the third second voltage line;

[0250] An orthographic projection of the first second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second control circuit on the substrate;

[0251] An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second control circuit on the substrate;

[0252] An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0253] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0254] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0255] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0256] The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of active patterns of at least part of the transistors included in the control signal generating circuit on the substrate;

[0257] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0258] Optionally, the first voltage line includes a first first voltage line, and the second voltage line includes a first second voltage line and a second second voltage line sequentially arranged in a direction away from the display area; the enable signal line is provided between the first second voltage line and the second second voltage line;

[0259] An orthographic projection of the first second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second control circuit on the substrate;

[0260] The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate; the orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least part of the transistor included in the control signal generating circuit on the substrate;

[0261] An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second control circuit on the substrate;

[0262] An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first control circuit on the substrate.

[0263] Optionally, the first voltage line includes a first first voltage line and a second first voltage line sequentially arranged in a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged in a direction away from the display area;

[0264] The orthographic projection of the plate of the capacitor included in the third energy storage circuit on the substrate is arranged between the orthographic projection of the third second voltage line on the substrate and the orthographic projection of the second first voltage line on the substrate;

[0265] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the first output node control circuit on the substrate;

[0266] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the output circuit on the substrate;

[0267] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0268] Optionally, the first voltage line includes a first first voltage line and a second first voltage line sequentially arranged in a direction away from the display area, and the second voltage line includes a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged in a direction away from the display area;

[0269] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the third energy storage circuit on the substrate;

[0270] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the first output node control circuit on the substrate;

[0271] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the output circuit on the substrate;

[0272] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0273] Optionally, the third first clock signal line and the third second clock signal line are arranged between the second first voltage line and the fourth second voltage line;

[0274] An orthographic projection of the third first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second output node control circuit on the substrate;

[0275] An orthographic projection of the third second clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the second output node control circuit on the substrate.

[0276] Optionally, the active pattern of at least part of the transistors included in the second control circuit includes at least two independent active pattern parts.

[0277] In a second aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0278] FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0279] FIG2 is a circuit diagram of a related pixel circuit;

[0280] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0281] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0282] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0283] FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0284] FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0285] FIG8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0286] FIG9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0287] FIG10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0288] FIG11 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0289] FIG12 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0290] FIG13 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0291] FIG14 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0292] FIG. 15 is an operation timing diagram of the driving signal generating circuit in at least one embodiment of the driving circuit shown in FIG. 14 .

[0293] 16 is an operation timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit;

[0294] FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0295] FIG18 is an operation timing diagram of a driving signal generating circuit in at least one embodiment of the driving circuit shown in FIG17 ;

[0296] FIG19 is an operation timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit;

[0297] FIG20 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0298] FIG21 is an operation timing diagram of a driving signal generating circuit in at least one embodiment of the driving circuit shown in FIG20 ;

[0299] FIG22 is an operation timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit;

[0300] FIG23 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0301] 24A, 24B, and 24C are first layout diagrams of at least one embodiment of the driving circuit shown in FIG. 14;

[0302] FIG25 is a layout diagram of the first semiconductor layer in FIG24A;

[0303] FIG26 is a layout diagram of the first gate metal layer in FIG24A ;

[0304] FIG27 is a layout diagram of the second gate metal layer in FIG24A;

[0305] FIG28 is a layout diagram of the first source / drain metal layer in FIG24A ;

[0306] FIG29 is a layout diagram of the second source / drain metal layer in FIG24A ;

[0307] FIG30 is a layout diagram of the third source / drain metal layer in FIG24A;

[0308] FIG31A is a superimposed diagram of the first semiconductor layer and the first gate metal layer in FIG24A;

[0309] FIG31B is a superimposed diagram of the first gate metal layer and the second gate metal layer in FIG24A;

[0310] FIG31C is a superimposed diagram of the second gate metal layer and the first source / drain metal layer in FIG24A;

[0311] FIG31D is a superimposed diagram of the first source / drain metal layer and the second source / drain metal layer in FIG24A;

[0312] FIG31E is a superimposed diagram of the second source / drain metal layer and the third source / drain metal layer in FIG24A;

[0313] 32A, 32B, and 32C are second layout diagrams of at least one embodiment of the driving circuit shown in FIG. 14;

[0314] FIG33 is a layout diagram of the first semiconductor layer in FIG32A;

[0315] FIG34 is a layout diagram of the first gate metal layer in FIG32A;

[0316] FIG35 is a layout diagram of the second gate metal layer in FIG32A;

[0317] FIG36 is a layout diagram of the second semiconductor layer in FIG32A;

[0318] FIG37 is a layout diagram of the third gate metal layer in FIG32A;

[0319] FIG38 is a layout diagram of the first source / drain metal layer in FIG32A ;

[0320] FIG39 is a layout diagram of the second source / drain metal layer in FIG32A ;

[0321] FIG40 is a layout diagram of the third source / drain metal layer in FIG32A;

[0322] FIG41A is a schematic diagram of the superposition of the first semiconductor layer and the first gate metal layer in FIG32A ;

[0323] FIG41B is a schematic diagram of the superposition of the first gate metal layer and the second gate metal layer in FIG32A;

[0324] FIG41C is a schematic diagram of the superposition of the second gate metal layer and the second semiconductor layer in FIG32A;

[0325] FIG41D is a schematic diagram of the superposition of the third gate metal layer and the second semiconductor layer in FIG32A;

[0326] FIG41E is a schematic diagram of the superposition of the third gate metal layer and the first source / drain metal layer in FIG32A ;

[0327] FIG41F is a schematic diagram of the superposition of the first source / drain metal layer and the second source / drain metal layer in FIG32A ;

[0328] FIG41G is a schematic diagram of the superposition of the second source / drain metal layer and the third source / drain metal layer in FIG32A ;

[0329] 42A, 42B, and 42C are first layout diagrams of at least one embodiment of the driving circuit shown in FIG. 17;

[0330] FIG43 is a layout diagram of the first semiconductor layer in FIG42A;

[0331] FIG44 is a layout diagram of the first gate metal layer in FIG42A;

[0332] FIG45 is a layout diagram of the second gate metal layer in FIG42A;

[0333] FIG46 is a layout diagram of the first source / drain metal layer in FIG42A;

[0334] FIG47 is a layout diagram of the second source / drain metal layer in FIG42A;

[0335] FIG48 is a layout diagram of the third source / drain metal layer in FIG42A;

[0336] FIG49A is a superimposed diagram of the first semiconductor layer and the first gate metal layer in FIG42A ;

[0337] FIG49B is a superimposed diagram of the first gate metal layer and the second gate metal layer in FIG42A;

[0338] FIG49C is a superimposed diagram of the second gate metal layer and the first source / drain metal layer in FIG42A ;

[0339] FIG49D is a superimposed diagram of the first source / drain metal layer and the second source / drain metal layer in FIG42A ;

[0340] FIG49E is a superimposed diagram of the second source / drain metal layer and the third source / drain metal layer in FIG42A ;

[0341] 50A, 50B, and 50C are second layout diagrams of at least one embodiment of the driving circuit shown in FIG. 17;

[0342] FIG51 is a layout diagram of the first semiconductor layer in FIG50A;

[0343] FIG52 is a layout diagram of the first gate metal layer in FIG50A;

[0344] FIG53 is a layout diagram of the second gate metal layer in FIG50A;

[0345] FIG54 is a layout diagram of the second semiconductor layer in FIG50A;

[0346] FIG55 is a layout diagram of the third gate metal layer in FIG50A;

[0347] FIG56 is a layout diagram of the first source / drain metal layer in FIG50A;

[0348] FIG57 is a layout diagram of the second source / drain metal layer in FIG50A;

[0349] FIG58 is a layout diagram of the third source / drain metal layer in FIG50A;

[0350] FIG59A is a schematic diagram showing the superposition of the first semiconductor layer and the first gate metal layer in FIG50A;

[0351] FIG59B is a schematic diagram of the superposition of the first gate metal layer and the second gate metal layer in FIG50A;

[0352] FIG59C is a schematic diagram illustrating the superposition of the second gate metal layer and the second semiconductor layer in FIG50A;

[0353] FIG59D is a schematic diagram illustrating the superposition of the third gate metal layer and the second semiconductor layer in FIG50A;

[0354] FIG59E is a schematic diagram of the superposition of the third gate metal layer and the first source / drain metal layer in FIG50A ;

[0355] FIG59F is a schematic diagram illustrating the superposition of the first source / drain metal layer and the second source / drain metal layer in FIG50A ;

[0356] FIG59G is a schematic diagram of the superposition of the second source / drain metal layer and the third source / drain metal layer in FIG50A ;

[0357] 60A, 60B, and 60C are first layout diagrams of at least one embodiment of the driving circuit shown in FIG. 20;

[0358] FIG61 is a layout diagram of the first semiconductor layer in FIG60A;

[0359] FIG62 is a layout diagram of the first gate metal layer in FIG60A;

[0360] FIG63 is a layout diagram of the second gate metal layer in FIG60A;

[0361] FIG64 is a layout diagram of the first source / drain metal layer in FIG60A ;

[0362] FIG65 is a layout diagram of the second source / drain metal layer in FIG60A;

[0363] FIG66A is a superimposed diagram of the first semiconductor layer and the first gate metal layer in FIG60A ;

[0364] FIG66B is a superimposed diagram of the first gate metal layer and the second gate metal layer in FIG60A ;

[0365] FIG66C is a superimposed diagram of the second gate metal layer and the first source / drain metal layer in FIG60A ;

[0366] FIG66D is an overlay diagram of the first source / drain metal layer and the second source / drain metal layer in FIG60A ;

[0367] 67A, 67B, and 67C are second layout diagrams of a display substrate including at least one embodiment of the driving circuit shown in FIG. 20;

[0368] FIG68 is a layout diagram of the first semiconductor layer in FIG67A;

[0369] FIG69 is a layout diagram of the first gate metal layer in FIG67A ;

[0370] FIG70 is a layout diagram of the second gate metal layer in FIG67A;

[0371] FIG71 is a layout diagram of the second semiconductor layer in FIG67A;

[0372] FIG72 is a layout diagram of the third gate metal layer in FIG67A;

[0373] FIG73 is a layout diagram of the first source / drain metal layer in FIG67A ;

[0374] FIG74 is a layout diagram of the second source / drain metal layer in FIG67A ;

[0375] FIG75A is a layout diagram of the first semiconductor layer and the first gate metal layer in FIG67A ;

[0376] FIG75B is a layout diagram of the first gate metal layer and the second gate metal layer in FIG67A ;

[0377] FIG75C is a layout diagram of the second gate metal layer and the second semiconductor layer in FIG67A ;

[0378] FIG75D is a layout diagram of the third gate metal layer and the second semiconductor layer in FIG67A;

[0379] FIG75E is a layout diagram of the third gate metal layer and the first source / drain metal layer in FIG67A ;

[0380] FIG75F is a layout diagram of the first source-drain metal layer and the second source-drain metal layer in FIG67A . DETAILED DESCRIPTION

[0381] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0382] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0383] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0384] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a driving signal generating circuit 11 , a control signal generating circuit 12 and a control circuit 13 ;

[0385] The drive signal generating circuit 11 is electrically connected to the first clock signal line CK and the second clock signal line CB, respectively, and is used to generate and output an n-level drive signal through the n-level drive signal output terminal OTn under the control of a first clock signal provided by the first clock signal line CK and a second clock signal provided by the second clock signal line CB; n is a positive integer;

[0386] The control signal generating circuit 12 is electrically connected to the enable signal line EN and the control signal terminal CS respectively, and is used to output a control signal to the control signal terminal CS according to the enable signal provided by the enable signal line EN;

[0387] The control circuit 13 is electrically connected to the control signal terminal CS and the n-th stage driving output terminal DTn, and is configured to output a signal to the n-th stage driving output terminal DTn under the control of the control signal.

[0388] When the driving circuit described in the embodiment of the present disclosure is working, the driving signal generating circuit 11 outputs the n-th level driving signal, the control signal generating circuit 12 generates a control signal according to the enable signal, and the control circuit 13 controls the output of the n-th level driving signal or the invalid voltage signal to the n-th driving output terminal DTn under the control of the control signal.

[0389] In related art, a drive circuit typically includes a drive signal generation circuit and a control circuit directly controlled by an enable signal. When the pulse width of the n-level drive signal provided by the drive signal generation circuit is 1 hour (1 hour is the scanning time for a single row), the control circuit directly controlled by the enable signal can be used to control the output of the n-level drive signal or an invalid voltage signal. However, with the development of pixels and the diversification of pixel control signals, the pulse width of the n-level drive signal may exceed 1 hour, causing the n-level drive signal waveform to cross the changing edge (rising or falling edge) of the enable signal. As a result, only a portion of the n-level drive signal can be output, which will cause abnormal pixel operation.

[0390] Based on this, the driving circuit described in the embodiment of the present disclosure is additionally provided with a control signal generating circuit 12, which generates a control signal according to the enable signal, and controls the output of the n-level driving signal or the invalid voltage signal to the n-level driving output terminal DTn through the control signal. In at least one embodiment of the present disclosure, the control signal generating circuit can be provided at the n-1-level driving signal output terminal, the n-1-level inverted driving signal (the n-1-level inverted driving signal can be inverted with the n-1-level driving signal), the n-level driving signal and the n-level inverted driving signal (the n-level inverted driving signal can be inverted with the n-level driving signal) under the control of the enable signal, and the control circuit 13 outputs the n-level driving signal or the invalid voltage signal to the n-level driving output terminal DTn under the control of the control signal, so that even when the pulse width of the n-level driving signal is greater than 1H, the n-level driving signal or the invalid voltage signal can be accurately output to the n-level driving output terminal DTn, so that local refresh can be accurately performed.

[0391] In at least one embodiment of the present disclosure, the control signal generating circuit is also electrically connected to the n-1th level drive signal output terminal, the n-1th level inverted signal output terminal, the n-level drive signal output terminal and the n-level inverted signal output terminal, respectively, and is used to control the connection or disconnection between the enable signal line and the control signal terminal under the control of the n-1th level drive signal, the n-1th level inverted drive signal, the n-level drive signal and the n-level inverted drive signal.

[0392] As shown in FIG2 , at least one embodiment of the related pixel circuit includes a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a storage capacitor Cst, and an organic light emitting diode O1.

[0393] The gate of M1 is electrically connected to the first reset terminal PR, the source of M1 is electrically connected to the first starting voltage terminal I1, and the second electrode of M1 is electrically connected to the drain of M3, wherein the first starting voltage terminal I1 is used to provide a first starting voltage Vinit1;

[0394] The gate of M2 is electrically connected to the first scanning terminal NT, the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;

[0395] The gate of M4 is electrically connected to the second scanning terminal PT, the source of M4 is electrically connected to the data line DL, and the drain of M4 is electrically connected to the source of M3;

[0396] The gate of M5 is electrically connected to the light emitting control terminal E1, the source of M5 is electrically connected to the high level terminal VDD, and the drain of M5 is electrically connected to the source of M3;

[0397] The gate of M6 is electrically connected to the light emitting control terminal E1, the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal VSS;

[0398] The gate of M7 is electrically connected to the second reset terminal HR, the source of M7 is electrically connected to the second initial voltage terminal I2, and the drain of M7 is electrically connected to the anode of O1;

[0399] The gate of M8 is electrically connected to the second reset terminal HR, the source of M8 is electrically connected to the third initial voltage terminal I3, and the drain of M8 is electrically connected to the source of M3;

[0400] The first electrode of Cst is electrically connected to the gate of M3, and the second electrode of Cst is electrically connected to the high level terminal VDD;

[0401] M1, M3, M4, M5, M6, M7 and M8 are all p-type transistors, and M2 is an n-type transistor.

[0402] In at least one embodiment of the present disclosure, the n-th stage driving output terminal DTn may be an n-th stage first scanning terminal, an n-th stage second scanning terminal, or an n-th stage first reset terminal, but is not limited thereto.

[0403] The driving circuit according to at least one embodiment of the present disclosure further includes an output inverting circuit;

[0404] The output inversion circuit is electrically connected to the n-th level driving signal output terminal and the n-th level inverted signal output terminal respectively, and is used to invert the n-th level driving signal to obtain and output the n-th level inverted driving signal through the n-th level inverted signal output terminal.

[0405] As shown in FIG3 , based on the embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure further includes an output inverting circuit 31 ;

[0406] The output inversion circuit 31 is electrically connected to the n-th stage inversion signal output terminal FOn, and is used to invert the n-th stage driving signal to obtain and output the n-th stage inversion driving signal through the n-th stage inversion signal output terminal FOn.

[0407] In at least one embodiment of the present disclosure, the control circuit includes a first control circuit, a second control circuit, and a first energy storage circuit;

[0408] The first control circuit is electrically connected to the control signal terminal, the n-th drive signal output terminal, the first control voltage line, the second control voltage line, and the control output terminal, respectively, and is configured to control, under the control of the control signal, connection or disconnection between the control output terminal and the first control voltage line; under the control of the n-level drive signal outputted by the n-level drive signal output terminal, control connection or disconnection between the control output terminal and the first control voltage line; and under the control of the n-level drive signal and the control signal, control connection or disconnection between the control output terminal and the second control voltage line;

[0409] The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line, and the second voltage line, respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal;

[0410] The first energy storage circuit is electrically connected to the control output terminal and is used to maintain the potential of the control output terminal.

[0411] Optionally, the first control voltage line is the first voltage line, and the second control voltage line is the second voltage line; or, the first control voltage line is the second voltage line, and the second control voltage line is the first voltage line.

[0412] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG3 , the control circuit includes a first control circuit 41 , a second control circuit 42 and a first energy storage circuit 44 ;

[0413] The first control circuit 41 is electrically connected to the control signal terminal CS, the n-th drive signal output terminal OTn, the first voltage line V1, the second voltage line V2, and the control output terminal CO, respectively, and is configured to control the connection between the control output terminal CO and the first voltage line V1 under the control of the control signal, control the connection or disconnection between the control output terminal CO and the first voltage line V1 under the control of the n-th level drive signal, and control the connection or disconnection between the control output terminal CO and the second voltage line V2 under the control of the n-th level drive signal and the control signal;

[0414] The second control circuit 42 is electrically connected to the control output terminal CO, the n-th stage driving output terminal DTn, the first voltage line V1, and the second voltage line V2, respectively, and is used to control the connection or disconnection between the n-th stage driving output terminal DTn and the first voltage line V1, and control the connection or disconnection between the n-th stage driving output terminal DTn and the second voltage line V2 under the control of the potential of the control output terminal CO;

[0415] The first energy storage circuit 44 is electrically connected to the control output terminal CO and is used to maintain the potential of the control output terminal CO.

[0416] Optionally, the first voltage line may be a high voltage line, and the second voltage line may be a low voltage line, but the present invention is not limited thereto.

[0417] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG3 , the control circuit includes a first control circuit 41 , a second control circuit 42 and a first energy storage circuit 44 ;

[0418] The first control circuit 41 is electrically connected to the control signal terminal CS, the n-th drive signal output terminal OTn, the first voltage line V1, the second voltage line V2, and the control output terminal CO, respectively, and is configured to control the connection between the control output terminal CO and the second voltage line V2 under the control of the control signal, control the connection or disconnection between the control output terminal CO and the second voltage line V2 under the control of the n-th level drive signal, and control the connection or disconnection between the control output terminal CO and the first voltage line V1 under the control of the n-th level drive signal and the control signal;

[0419] The second control circuit 42 is electrically connected to the control output terminal CO, the n-th stage driving output terminal DTn, the first voltage line V1, and the second voltage line V2, respectively, and is used to control the connection or disconnection between the n-th stage driving output terminal DTn and the first voltage line V1, and control the connection or disconnection between the n-th stage driving output terminal DTn and the second voltage line V2 under the control of the potential of the control output terminal CO;

[0420] The first energy storage circuit 44 is electrically connected to the control output terminal CO and is used to maintain the potential of the control output terminal CO.

[0421] Optionally, the control circuit further includes a second energy storage circuit;

[0422] The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal.

[0423] As shown in FIG6 , based on at least one embodiment of the driving circuit shown in FIG4 , the control circuit further includes a second energy storage circuit 45 ;

[0424] The second energy storage circuit 45 is electrically connected to the control signal terminal CS and is used to maintain the potential of the control signal terminal CS.

[0425] As shown in FIG7 , based on at least one embodiment of the driving circuit shown in FIG5 , the control circuit further includes a second energy storage circuit 45 ;

[0426] The second energy storage circuit 45 is electrically connected to the control signal terminal CS and is used to maintain the potential of the control signal terminal CS.

[0427] In at least one embodiment of the present disclosure,

[0428] The control signal generating circuit is also electrically connected to the n-1th level drive signal output terminal, the n-1th level inverted signal output terminal, the nth level drive signal output terminal and the nth level inverted signal output terminal, respectively, and is used to control the connection or disconnection between the enable signal line and the control signal terminal under the control of the n-1th level drive signal, the n-1th level inverted drive signal, the nth level drive signal and the nth level inverted drive signal.

[0429] As shown in Figure 8, on the basis of at least one embodiment of the driving circuit shown in Figure 6, the control signal generating circuit 12 is also electrically connected to the n-1th level driving signal output terminal OTn-1, the n-1th level inverted signal output terminal FTn-1, the n-level driving signal output terminal OTn and the n-level inverted signal output terminal FTn, respectively, and is used to control the connection or disconnection between the enable signal line EN and the control signal terminal CS under the control of the n-1th level driving signal, the n-1th level inverted driving signal, the n-1th level driving signal and the n-level inverted driving signal.

[0430] As shown in Figure 9, based on at least one embodiment of the driving circuit shown in Figure 7, the control signal generating circuit 12 is also electrically connected to the n-1th level driving signal output terminal OTn-1, the n-1th level inverted signal output terminal FTn-1, the n-level driving signal output terminal OTn and the n-level inverted signal output terminal FTn, respectively, and is used to control the connection or disconnection between the enable signal line EN and the control signal terminal CS under the control of the n-1th level driving signal, the n-1th level inverted driving signal, the n-1th level driving signal and the n-level inverted driving signal.

[0431] As shown in FIG10 , based on at least one embodiment of the driving circuit shown in FIG1 , the control circuit includes a first control circuit 41 , a second control circuit 42 and a first energy storage circuit 44 ;

[0432] The first control circuit 41 is electrically connected to the control signal terminal CS, the n-th drive signal output terminal OTn, the first voltage line V1, the second voltage line V2, and the control output terminal CO, respectively, and is configured to control the connection between the control output terminal CO and the second voltage line V2 under the control of the control signal, control the connection or disconnection between the control output terminal CO and the second voltage line V2 under the control of the n-th level drive signal, and control the connection or disconnection between the control output terminal CO and the first voltage line V1 under the control of the n-th level drive signal and the control signal;

[0433] The second control circuit 42 is electrically connected to the control output terminal CO, the n-th stage driving output terminal DTn, the first voltage line V1, and the second voltage line V2, respectively, and is used to control the connection or disconnection between the n-th stage driving output terminal DTn and the first voltage line V1, and control the connection or disconnection between the n-th stage driving output terminal DTn and the second voltage line V2 under the control of the potential of the control output terminal CO;

[0434] The first energy storage circuit 44 is electrically connected to the control output terminal CO and is used to maintain the potential of the control output terminal CO.

[0435] In at least one embodiment of the present disclosure, the control signal generating circuit is configured to invert the enable signal to generate an inverted enable signal, and output the inverted enable signal through the control signal terminal.

[0436] During specific implementation, the control signal generating circuit may invert the enable signal to generate an inverted enable signal.

[0437] Optionally, the first control circuit includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the second control circuit includes a fifth control transistor and a sixth control transistor; and the first energy storage circuit includes a first capacitor;

[0438] The gate of the first control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the first control transistor is electrically connected to the first control voltage line, and the second electrode of the first control transistor is electrically connected to the control output terminal;

[0439] The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the second control transistor is electrically connected to the second control voltage line;

[0440] The gate of the third control transistor is electrically connected to the control signal terminal, the first electrode of the third control transistor is electrically connected to the first control voltage line, and the second electrode of the third control transistor is electrically connected to the control output terminal;

[0441] The gate of the fourth control transistor is electrically connected to the n-th stage driving signal output terminal, and the first electrode of the fourth control transistor is electrically connected to the control output terminal;

[0442] The gate of the fifth control transistor is electrically connected to the control output terminal, the first electrode of the fifth control transistor is electrically connected to the first voltage line, and the second electrode of the fifth control transistor is electrically connected to the nth driving output terminal;

[0443] The gate of the sixth control transistor is electrically connected to the control output terminal, the first electrode of the sixth control transistor is electrically connected to the nth driving output terminal, and the second electrode of the sixth control transistor is electrically connected to the second voltage line;

[0444] A first end of the first capacitor is electrically connected to the control output end, and a second end of the first capacitor is electrically connected to the second voltage line.

[0445] Optionally, the first control circuit includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the second control circuit includes a fifth control transistor and a sixth control transistor; the first energy storage circuit includes a first capacitor; the first control voltage line is the second voltage line, and the second control voltage line is the first voltage line;

[0446] The gate of the first control transistor is electrically connected to the control signal terminal, the first electrode of the first control transistor is electrically connected to the second electrode of the third control transistor, and the second electrode of the first control transistor is electrically connected to the control output terminal;

[0447] The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the control output terminal, and the second electrode of the second control transistor is electrically connected to the second voltage line;

[0448] The gate of the third control transistor is electrically connected to the n-th stage driving signal output terminal, and the first electrode of the third control transistor is electrically connected to the first voltage line;

[0449] The gate of the fourth control transistor is electrically connected to the n-th stage drive signal output terminal, the first electrode of the fourth control transistor is electrically connected to the control output terminal, and the second electrode of the fourth control transistor is electrically connected to the second voltage line;

[0450] The gate of the fifth control transistor is electrically connected to the control output terminal, the first electrode of the fifth control transistor is electrically connected to the first voltage line, and the second electrode of the fifth control transistor is electrically connected to the nth driving output terminal;

[0451] The gate of the sixth control transistor is electrically connected to the control output terminal, the first electrode of the sixth control transistor is electrically connected to the nth driving output terminal, and the second electrode of the sixth control transistor is electrically connected to the second voltage line;

[0452] A first end of the first capacitor is electrically connected to the control output end, and a second end of the first capacitor is electrically connected to the second voltage line.

[0453] Optionally, the second energy storage circuit includes a second capacitor;

[0454] A first end of the second capacitor is electrically connected to the control signal end, and a second end of the second capacitor is electrically connected to the second voltage line.

[0455] Optionally, the control signal generating circuit includes a seventh control transistor, an eighth control transistor, a ninth control transistor and a tenth control transistor;

[0456] The gate of the seventh control transistor is electrically connected to the (n-1)th stage driving signal output terminal, the first electrode of the seventh control transistor is electrically connected to the enable signal line, and the second electrode of the seventh control transistor is electrically connected to the first electrode of the tenth control transistor;

[0457] The gate of the eighth control transistor is electrically connected to the (n-1)th stage inverting signal output terminal, the first electrode of the eighth control transistor is electrically connected to the enable signal line, and the second electrode of the eighth control transistor is electrically connected to the first electrode of the ninth control transistor;

[0458] The gate of the ninth control transistor is electrically connected to the nth stage driving signal output terminal, the first electrode of the ninth control transistor is electrically connected to the first electrode of the tenth control transistor, and the second electrode of the ninth control transistor is electrically connected to the control signal terminal;

[0459] The gate of the tenth control transistor is electrically connected to the n-th stage inverting signal output terminal, and the second electrode of the tenth control transistor is electrically connected to the control signal terminal;

[0460] The seventh control transistor and the tenth control transistor are both n-type transistors, and the eighth control transistor and the ninth control transistor are both p-type transistors; or,

[0461] The seventh control transistor and the tenth control transistor are both p-type transistors, and the eighth control transistor and the ninth control transistor are both n-type transistors.

[0462] Optionally, the control signal generating circuit includes a seventh control transistor and an eighth control transistor;

[0463] The gate of the seventh control transistor is electrically connected to the enable signal line, the first electrode of the seventh control transistor is electrically connected to the first voltage line, and the second electrode of the seventh control transistor is electrically connected to the control signal terminal;

[0464] The gate of the eighth control transistor is electrically connected to the enable signal line, the first electrode of the eighth control transistor is electrically connected to the control signal terminal, and the second electrode of the eighth control transistor is electrically connected to the second voltage line;

[0465] The seventh control transistor is a p-type transistor, and the eighth control transistor is an n-type transistor; or the seventh control transistor is an n-type transistor, and the eighth control transistor is a p-type transistor.

[0466] Optionally, the output inverting circuit includes an eleventh control transistor and a twelfth control transistor;

[0467] The gate of the eleventh control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the eleventh control transistor is electrically connected to the n-th stage inverting signal output terminal, and the second electrode of the eleventh control transistor is electrically connected to the second voltage line;

[0468] The gate of the twelfth control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the twelfth control transistor is electrically connected to the first voltage line, and the second electrode of the twelfth control transistor is electrically connected to the n-th stage inverting signal output terminal.

[0469] In at least one embodiment of the present disclosure, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit, and an output circuit; the first clock signal line includes a first first clock signal line, and the second clock signal line includes a first second clock signal line;

[0470] The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node;

[0471] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal, and the second voltage line, respectively, and is configured to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line;

[0472] The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node, and the first voltage line, respectively, and is configured to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0473] The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0474] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0475] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0476] As shown in FIG11 , based on at least one embodiment of the driving circuit shown in FIG8 , the driving signal generating circuit includes a first node control circuit 91, a second node control circuit 92, a first output node control circuit 93, a second output node control circuit 94, a potential maintaining circuit 95, and an output circuit 96; the first clock signal line includes a first first clock signal line CK1, and the second clock signal line includes a first second clock signal line CB1;

[0477] The first node control circuit 91 is electrically connected to the first node N1, the first first clock signal line CK1, the second voltage line V2, and the second output node NJ2, respectively, and is used to control the connection between the first node N1 and the second voltage line V2 under the control of the first clock signal provided by the first first clock signal line CK1, and to control the connection or disconnection between the first node N1 and the first first clock signal line CK1 under the control of the potential of the second output node NJ2;

[0478] The second node control circuit 92 is electrically connected to the first node N1, the first intermediate node NZ1, the first voltage line V1, the first second clock signal line CB1, the second node N2, the input terminal I0, and the second voltage line V2, respectively, and is configured to control the communication between the first intermediate node NZ1 and the first voltage line V1 under the control of the potential of the first node N1, and control the communication between the first intermediate node NZ1 and the first second clock signal line CB1 under the control of the potential of the second node N2, and control the potential of the second node N2 according to the potential of the second intermediate node NZ2, and control the communication between the input terminal I0 and the second node N2 under the control of the second clock signal provided by the first second clock signal line CB1 and the second voltage signal provided by the second voltage line V2;

[0479] The first output node control circuit 93 is electrically connected to the first output node NJ1, the first node N1, the first second clock signal line CB1, the second intermediate node NZ2, the second output node NJ2, and the first voltage line V1, respectively, and is configured to control the communication between the second intermediate node NZ2 and the first second clock signal line CB1 under the control of the potential of the first node N1, control the potential of the second intermediate node NZ2 according to the potential of the first node N1, control the communication between the second intermediate node NZ2 and the first output node NJ1 under the control of the second clock signal provided by the first second clock signal line CB1, and control the communication between the first output node NJ1 and the first voltage line V1 under the control of the potential of the second output node NJ2;

[0480] The second output node control circuit 94 is electrically connected to the first second clock signal line CB1, the input terminal I0, the control voltage line VEL, the first voltage line V1, the second node N2, and the second output node NJ2, respectively, and is configured to control the communication between the second output node NJ2 and the input terminal I0 under the control of the second clock signal provided by the first second clock signal line CB1, control the potential of the second output node NJ2 according to the potential of the second node N2, and control the communication between the second output node NJ2 and the first voltage line V1 under the control of the control voltage provided by the control voltage line VEL;

[0481] The potential maintaining circuit 95 is electrically connected to the first output node NJ1 and is used to maintain the potential of the first output node NJ1;

[0482] The output circuit 96 is electrically connected to the first output node NJ1, the second output node NJ2, the first voltage line V1, the second voltage line V2 and the n-th level drive signal output terminal OTn, respectively, and is used to control the connection between the n-level drive signal output terminal OTn and the first voltage line V1 under the control of the potential of the first output node NJ1, and to control the connection between the n-level drive signal output terminal OTn and the second voltage line V2 under the control of the potential of the second output node NJ2.

[0483] In at least one embodiment of the present disclosure, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit, and an output circuit; the first clock signal line includes a second first clock signal line, and the second clock signal line includes a second second clock signal line;

[0484] The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node;

[0485] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal, and the second voltage line, respectively, and is configured to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line;

[0486] The first output node control circuit is electrically connected to the first output node, the first node, the second second-clock signal line, the second intermediate node, the second output node, and the first voltage line, respectively, and is configured to control the second intermediate node to be connected to the second second-clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second-clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0487] The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0488] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0489] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0490] As shown in FIG12 , based on at least one embodiment of the driving circuit shown in FIG9 , the driving signal generating circuit includes a first node control circuit 91, a second node control circuit 92, a first output node control circuit 93, a second output node control circuit 94, a potential maintaining circuit 95, and an output circuit 96;

[0491] The first node control circuit 91 is electrically connected to the first node N1, the second first clock signal line CK2, the second voltage line V2, and the second output node NJ2, respectively, and is used to control the connection between the first node N1 and the second voltage line V2 under the control of the first clock signal provided by the second first clock signal line CK2, and to control the connection or disconnection between the first node N1 and the second first clock signal line CK2 under the control of the potential of the second output node NJ2;

[0492] The second node control circuit 92 is electrically connected to the first node N1, the first intermediate node NZ1, the first voltage line V1, the second second clock signal line CB2, the second node N2, the input terminal I0, and the second voltage line V2, respectively, and is configured to control the communication between the first intermediate node NZ1 and the first voltage line V1 under the control of the potential of the first node N1, and control the communication between the first intermediate node NZ1 and the second second clock signal line CB2 under the control of the potential of the second node N2, and control the potential of the second node N2 according to the potential of the second intermediate node NZ2, and control the communication between the input terminal and the second node N2 under the control of the second clock signal provided by the second second clock signal line CB2 and the second voltage signal provided by the second voltage line V2;

[0493] The first output node control circuit 93 is electrically connected to the first output node NJ1, the first node N1, the second second clock signal line CB2, the second intermediate node NZ2, the second output node NJ2, and the first voltage line V1, respectively, and is configured to control the communication between the second intermediate node NZ2 and the second second clock signal line CB2 under the control of the potential of the first node N1, control the potential of the second intermediate node NZ2 according to the potential of the first node N1, control the communication between the second intermediate node NZ2 and the first output node NJ1 under the control of the second clock signal provided by the second second clock signal line CB2, and control the communication between the first output node NJ1 and the first voltage line V1 under the control of the potential of the second output node NJ2;

[0494] The second output node control circuit 94 is electrically connected to the second second clock signal line CB2, the input terminal I0, the control voltage line VEL, the first voltage line V1, the second node N2, and the second output node NJ2, respectively, and is configured to control the communication between the second output node NJ2 and the input terminal I0 under the control of the second clock signal provided by the second second clock signal line CB2, control the potential of the second output node NJ2 according to the potential of the second node N2, and control the communication between the second output node NJ2 and the first voltage line V1 under the control of the control voltage provided by the control voltage line VEL;

[0495] The potential maintaining circuit 95 is electrically connected to the first output node NJ1 and is used to maintain the potential of the first output node NJ1;

[0496] The output circuit 96 is electrically connected to the first output node NJ1, the second output node NJ2, the first voltage line V1, the second voltage line V2 and the n-th level drive signal output terminal OTn, respectively, and is used to control the connection between the n-level drive signal output terminal OTn and the first voltage line V1 under the control of the potential of the first output node NJ1, and to control the connection between the n-level drive signal output terminal OTn and the second voltage line V2 under the control of the potential of the second output node NJ2.

[0497] Optionally, the first node control circuit includes a first transistor, a second transistor, and a third transistor; the second output node control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0498] The gate of the first transistor is electrically connected to the first first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor;

[0499] The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the first electrode of the second transistor is electrically connected to the first first clock signal line, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor;

[0500] The gate of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the first node;

[0501] The gate of the fourth transistor is electrically connected to the first first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;

[0502] The gate of the fifth transistor is electrically connected to the second voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node;

[0503] The gate of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node;

[0504] The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the first voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor;

[0505] The second node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a third capacitor;

[0506] The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the first second clock signal line, and the second electrode of the eighth transistor is electrically connected to the first intermediate node;

[0507] The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node;

[0508] The gate of the tenth transistor is electrically connected to the first first clock signal line, the first electrode of the tenth transistor is electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0509] The gate of the eleventh transistor is electrically connected to the second voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0510] The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the first intermediate node;

[0511] The first output node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fourth capacitor;

[0512] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first-second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node;

[0513] The gate of the thirteenth transistor is electrically connected to the first-second clock signal line, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node;

[0514] The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the first electrode of the fourteenth transistor is electrically connected to the first voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first output node;

[0515] The first plate of the fourth capacitor is electrically connected to the first node, and the second plate of the fourth capacitor is electrically connected to the second intermediate node;

[0516] The potential maintaining circuit includes a fifth capacitor;

[0517] The first plate of the fifth capacitor is electrically connected to the first output node, and the second plate of the fifth capacitor is electrically connected to the first voltage line;

[0518] The output circuit includes a fifteenth transistor and a sixteenth transistor;

[0519] The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage driving signal output terminal;

[0520] The gate of the sixteenth transistor is electrically connected to the second output node, the first electrode of the sixteenth transistor is electrically connected to the n-th stage driving signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage line.

[0521] Optionally, the first node control circuit includes a first transistor, a second transistor, and a third transistor; the second output node control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0522] The gate of the first transistor is electrically connected to the second first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor;

[0523] The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the first electrode of the second transistor is electrically connected to the second first clock signal line, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor;

[0524] The gate of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the first node;

[0525] The gate of the fourth transistor is electrically connected to the second first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal;

[0526] The gate of the fifth transistor is electrically connected to the second voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node;

[0527] The gate of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node;

[0528] The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the first voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor;

[0529] The second node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a third capacitor;

[0530] The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the second second clock signal line, and the second electrode of the eighth transistor is electrically connected to the first intermediate node;

[0531] The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node;

[0532] The gate of the tenth transistor is electrically connected to the second first clock signal line, the first electrode of the tenth transistor is electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor;

[0533] The gate of the eleventh transistor is electrically connected to the second voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0534] The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the first intermediate node;

[0535] The first output node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fourth capacitor;

[0536] The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node;

[0537] The gate of the thirteenth transistor is electrically connected to the second second clock signal line, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node;

[0538] The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the first electrode of the fourteenth transistor is electrically connected to the first voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first output node;

[0539] The first plate of the fourth capacitor is electrically connected to the first node, and the second plate of the fourth capacitor is electrically connected to the second intermediate node;

[0540] The potential maintaining circuit includes a fifth capacitor;

[0541] The first plate of the fifth capacitor is electrically connected to the first output node, and the second plate of the fifth capacitor is electrically connected to the first voltage line;

[0542] The output circuit includes a fifteenth transistor and a sixteenth transistor;

[0543] The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage driving signal output terminal;

[0544] The gate of the sixteenth transistor is electrically connected to the second output node, the first electrode of the sixteenth transistor is electrically connected to the n-th stage driving signal output terminal, and the second electrode of the sixteenth transistor is electrically connected to the second voltage line.

[0545] In at least one embodiment of the present disclosure, the drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit, and an output circuit; the first clock signal line includes a third first clock signal line, and the second clock signal line includes a third second clock signal line;

[0546] The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control communication between the first output node and the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control communication between the first output node and the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node;

[0547] The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node, and the first voltage line, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line;

[0548] A first end of the third energy storage circuit is electrically connected to the second output node, a second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electrical energy;

[0549] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node.

[0550] As shown in FIG13 , based on at least one embodiment of the driving circuit shown in FIG10 , the driving signal generating circuit includes a first output node control circuit 93, a second output node control circuit 94, a third energy storage circuit 90, and an output circuit 96; the first clock signal line includes a third first clock signal line CK3, and the second clock signal line includes a third second clock signal line CB3;

[0551] The first output node control circuit 93 is electrically connected to the third first clock signal line CK3, the second voltage line V2, the first output node NJ1, and the second output node NJ2, respectively, and is configured to control the connection between the first output node NJ1 and the second voltage line V2 under the control of the first clock signal provided by the third first clock signal line CK3, and to control the connection between the first output node NJ1 and the first clock signal line CK under the control of the potential of the second output node NJ2, and to maintain the potential of the first output node NJ1.

[0552] The second output node control circuit 94 is electrically connected to the second output node NJ2, the third first clock signal line CK3, the input terminal I0, the third second clock signal line CB3, the first output node NJ1, and the first voltage line V1, respectively, and is configured to control communication between the second output node NJ2 and the input terminal I0 under the control of the first clock signal, and to control communication between the second output node NJ2 and the first voltage line V1 under the control of the potential of the first output node NJ1 and the second clock signal provided by the third second clock signal line CB3;

[0553] A first end of the third energy storage circuit 90 is electrically connected to the second output node NJ2, a second end of the third energy storage circuit 90 is electrically connected to the n-th stage drive signal output terminal OTn, and the third energy storage circuit 90 is used to store electrical energy;

[0554] The output circuit 96 is electrically connected to the first output node NJ1, the second output node NJ2, the first voltage line V1, the second clock signal CB and the n-th level drive signal output terminal OTn, respectively, and is used to control the connection between the n-level drive signal output terminal OTn and the first voltage line V1 under the control of the potential of the first output node NJ1, and to control the connection between the n-level drive signal output terminal OTn and the third second clock signal line CB3 under the control of the potential of the second output node NJ2.

[0555] Optionally, the first output node control circuit includes a seventeenth transistor, an eighteenth transistor and a sixth capacitor;

[0556] The gate of the seventeenth transistor is electrically connected to the third first clock signal line, the first electrode of the seventeenth transistor is electrically connected to the second voltage line, and the second electrode of the seventeenth transistor is electrically connected to the first output node;

[0557] a gate of the eighteenth transistor is electrically connected to the second output node, a first electrode of the eighteenth transistor is electrically connected to the third first clock signal line, and a second electrode of the eighteenth transistor is electrically connected to the first output node;

[0558] The first plate of the sixth capacitor is electrically connected to the first output node, and the second plate of the sixth capacitor is electrically connected to the first voltage line;

[0559] The second output node control circuit includes a nineteenth transistor, a twentieth transistor, and a twenty-first transistor; the third energy storage circuit includes a seventh capacitor;

[0560] The gate of the nineteenth transistor is electrically connected to the third first clock signal line, the first electrode of the nineteenth transistor is electrically connected to the input terminal, and the second electrode of the nineteenth transistor is electrically connected to the second output node;

[0561] a gate of the twentieth transistor electrically connected to the first output node, a first electrode of the twentieth transistor electrically connected to the first voltage line, and a second electrode of the twentieth transistor electrically connected to the first electrode of the twenty-first transistor;

[0562] a gate of the twenty-first transistor is electrically connected to the third second clock signal line, and a second electrode of the twenty-first transistor is electrically connected to the second output node;

[0563] The first plate of the seventh capacitor is electrically connected to the second output node, and the second plate of the seventh capacitor is electrically connected to the n-th stage driving signal output terminal;

[0564] The output circuit includes a twenty-second transistor and a twenty-third transistor;

[0565] a gate of the twenty-second transistor is electrically connected to the first output node, a first electrode of the twenty-second transistor is electrically connected to the first voltage line, and a second electrode of the twenty-second transistor is electrically connected to the n-th stage driving signal output terminal;

[0566] a gate of the twenty-third transistor is electrically connected to the second output node, a first electrode of the twenty-third transistor is electrically connected to the n-th stage driving signal output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third second clock signal line;

[0567] The driving circuit further includes a twenty-fourth transistor;

[0568] The second electrode of the 21st transistor is electrically connected to the second output node through the 24th transistor; the gate of the 24th transistor is electrically connected to the second voltage line, the first electrode of the 24th transistor is electrically connected to the second electrode of the 21st transistor, and the second electrode of the 24th transistor is electrically connected to the second output node.

[0569] As shown in FIG14 , based on at least one embodiment of the driving circuit shown in FIG11 , the n-th stage driving output terminal is the n-th stage first scanning terminal NTn;

[0570] The first control circuit includes a first control transistor CT1, a second control transistor CT2, a third control transistor CT3 and a fourth control transistor CT4; the second control circuit includes a fifth control transistor CT5 and a sixth control transistor CT6; the first energy storage circuit includes a first capacitor CC1;

[0571] The gate of the first control transistor CT1 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the first control transistor CT1 is electrically connected to the high voltage line VGH, and the drain of the first control transistor CT1 is electrically connected to the control output terminal CO;

[0572] The gate of the second control transistor CT2 is electrically connected to the control signal terminal CS, the source of the second control transistor CT2 is electrically connected to the drain of the fourth control transistor CT4, and the drain of the second control transistor CT2 is electrically connected to the low voltage line VGL;

[0573] The gate of the third control transistor CT3 is electrically connected to the control signal terminal CS, the source of the third control transistor CT3 is electrically connected to the high voltage line VGH, and the drain of the third control transistor CT3 is electrically connected to the control output terminal CO;

[0574] The gate of the fourth control transistor CT4 is electrically connected to the n-th stage drive signal output terminal OTn, and the source of the fourth control transistor CT4 is electrically connected to the control output terminal CO;

[0575] The gate of the fifth control transistor CT5 is electrically connected to the control output terminal CO, the source of the fifth control transistor CT5 is electrically connected to the high voltage line VGH, and the drain of the fifth control transistor CT5 is electrically connected to the n-th stage first scanning terminal NTn;

[0576] The gate of the sixth control transistor CT6 is electrically connected to the control output terminal CO, the source of the sixth control transistor CT6 is electrically connected to the n-th stage first scanning terminal NTn, and the drain of the sixth control transistor CT6 is electrically connected to the low voltage line VGL;

[0577] A first end of the first capacitor CC1 is electrically connected to the control output terminal CO, and a second end of the first capacitor CC1 is electrically connected to the low voltage line VGL;

[0578] The second energy storage circuit includes a second capacitor CC2;

[0579] A first end of the second capacitor CC2 is electrically connected to the control signal terminal CS, and a second end of the second capacitor CC2 is electrically connected to the low voltage line VGL;

[0580] The control signal generating circuit includes a seventh control transistor CT7, an eighth control transistor CT8, a ninth control transistor CT9 and a tenth control transistor CT10;

[0581] The gate of the seventh control transistor CT7 is electrically connected to the n-1th stage drive signal output terminal OTn-1, the source of the seventh control transistor CT7 is electrically connected to the enable signal line EN, and the drain of the seventh control transistor CT7 is electrically connected to the source of the tenth control transistor CT10;

[0582] The gate of the eighth control transistor CT8 is electrically connected to the n-1th stage inverting signal output terminal FTn-1, the source of the eighth control transistor CT8 is electrically connected to the enable signal line EN, and the drain of the eighth control transistor CT8 is electrically connected to the source of the ninth control transistor CT9;

[0583] The gate of the ninth control transistor CT9 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the ninth control transistor CT9 is electrically connected to the source of the tenth control transistor CT10, and the drain of the ninth control transistor CT9 is electrically connected to the control signal terminal CS;

[0584] The gate of the tenth control transistor CT10 is electrically connected to the n-th stage inverting signal output terminal FTn, and the drain of the tenth control transistor CT10 is electrically connected to the control signal terminal CS;

[0585] The output inverting circuit includes an eleventh control transistor CT11 and a twelfth control transistor CT12;

[0586] The gate of the eleventh control transistor CT11 is electrically connected to the n-th stage driving signal output terminal OTn, the source of the eleventh control transistor CT11 is electrically connected to the n-th stage inverting signal output terminal FTn, and the drain of the eleventh control transistor CT11 is electrically connected to the low voltage line VGL;

[0587] The gate of the twelfth control transistor CT12 is electrically connected to the n-th stage driving signal output terminal OTn, the source of the twelfth control transistor CT12 is electrically connected to the high voltage line VGH, and the drain of the twelfth control transistor CT12 is electrically connected to the n-th stage inverting signal output terminal FTn;

[0588] The first node control circuit includes a first transistor T1, a second transistor T2 and a third transistor T3; the second output node control circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7;

[0589] The gate of the first transistor T1 is electrically connected to the first first clock signal line CK1, the source of the first transistor T1 is electrically connected to the low voltage line VGL, and the drain of the first transistor T1 is electrically connected to the source of the third transistor T3;

[0590] The gate of the second transistor T2 is electrically connected to the drain of the fourth transistor T4, the source of the second transistor T2 is electrically connected to the first first clock signal line CK1, and the drain of the second transistor T2 is electrically connected to the source of the third transistor T3;

[0591] The gate of the third transistor T3 is electrically connected to the low voltage line VGL, and the drain of the third transistor T3 is electrically connected to the first node N1;

[0592] The gate of the fourth transistor T4 is electrically connected to the first first clock signal line CK1, and the source of the fourth transistor T4 is electrically connected to the input terminal I0;

[0593] The gate of the fifth transistor T5 is electrically connected to the low voltage line VGL, the source of the fifth transistor T5 is electrically connected to the drain of the fourth transistor T4, and the drain of the fifth transistor T5 is electrically connected to the second output node NJ2;

[0594] The gate of the sixth transistor T6 and the source of the sixth transistor T6 are both electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the second output node NJ2;

[0595] The gate of the seventh transistor T7 is electrically connected to the control voltage line VEL, the source of the seventh transistor T7 is electrically connected to the high voltage line VGH, and the drain of the seventh transistor T7 is electrically connected to the source of the fifth transistor T5;

[0596] The second node control circuit includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a third capacitor C3;

[0597] The gate of the eighth transistor T8 is electrically connected to the second node N2, the source of the eighth transistor T8 is electrically connected to the first second clock signal line CB1, and the drain of the eighth transistor T8 is electrically connected to the first intermediate node NZ1;

[0598] The gate of the ninth transistor T9 is electrically connected to the drain of the first transistor T1, the source of the ninth transistor T9 is electrically connected to the high voltage line VGH, and the drain of the ninth transistor T9 is electrically connected to the first intermediate node NZ1;

[0599] The gate of the tenth transistor T10 is electrically connected to the first first clock signal line CK1, the source of the tenth transistor T10 is electrically connected to the input terminal I0, and the drain of the tenth transistor T10 is electrically connected to the source of the eleventh transistor T11;

[0600] The gate of the eleventh transistor T11 is electrically connected to the low voltage line VGL, and the drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0601] The first plate of the third capacitor C3 is electrically connected to the second node N2, and the second plate of the third capacitor C3 is electrically connected to the first intermediate node NZ1;

[0602] The first output node control circuit includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14 and a fourth capacitor C4;

[0603] The gate of the twelfth transistor T12 is electrically connected to the first node N1, the source of the twelfth transistor T12 is electrically connected to the first-second clock signal line CB1, and the drain of the twelfth transistor T12 is electrically connected to the second intermediate node NZ2;

[0604] The gate of the thirteenth transistor T13 is electrically connected to the first second clock signal line CB1, the source of the thirteenth transistor T13 is electrically connected to the second intermediate node NZ2, and the drain of the thirteenth transistor T13 is electrically connected to the first output node NJ1;

[0605] The gate of the fourteenth transistor T14 is electrically connected to the source of the fifth transistor T5, the source of the fourteenth transistor T14 is electrically connected to the high voltage line VGH, and the drain of the fourteenth transistor T14 is electrically connected to the first output node NJ1;

[0606] The first plate of the fourth capacitor C4 is electrically connected to the first node N1, and the second plate of the fourth capacitor C4 is electrically connected to the second intermediate node NZ2;

[0607] The potential maintaining circuit includes a fifth capacitor C5;

[0608] A first plate of the fifth capacitor C5 is electrically connected to the first output node NJ1, and a second plate of the fifth capacitor C5 is electrically connected to the high voltage line VGH;

[0609] The output circuit includes a fifteenth transistor T15 and a sixteenth transistor T16;

[0610] The gate of the fifteenth transistor T15 is electrically connected to the first output node NJ1, the source of the fifteenth transistor T15 is electrically connected to the high voltage line VGH, and the drain of the fifteenth transistor T15 is electrically connected to the n-th stage driving signal output terminal OTn;

[0611] The gate of the sixteenth transistor T16 is electrically connected to the second output node NJ2 , the source of the sixteenth transistor T16 is electrically connected to the n-th stage driving signal output terminal OTn, and the drain of the sixteenth transistor T16 is electrically connected to the low voltage line VGL.

[0612] In at least one embodiment of the driving circuit shown in Figure 14, T1-T16 can be p-type transistors, CT11 is an n-type transistor, CT12 is a p-type transistor, CT7 is an n-type transistor, CT8 is a p-type transistor, CT10 is an n-type transistor, CT9 is a p-type transistor, CT1 is a p-type transistor, CT2 is an n-type transistor, CT3 is a p-type transistor, CT4 is an n-type transistor, CT5 is a p-type transistor, and CT6 is an n-type transistor.

[0613] In at least one embodiment of the driving circuit shown in FIG14 , the driving signal generating circuit is a 16T3C circuit. In actual operation, the driving signal generating circuit may also adopt a circuit having other structures for generating an n-th level driving signal.

[0614] In at least one embodiment of the driving circuit shown in FIG. 14 , T3 and T5 may not be provided.

[0615] FIG. 15 is an operation timing diagram of the driving signal generating circuit in at least one embodiment of the driving circuit shown in FIG. 14 .

[0616] When at least one embodiment of the driving circuit shown in Figure 14 is in operation, when the display device including the driving circuit starts to operate, VEL provides a low voltage signal, T7 is turned on, so as to control the connection between the gate of T14 and VGH, so that T14 is turned off; thereafter, when the driving circuit is in operation, VEL continues to provide a high voltage signal, so that T7 is turned off.

[0617] FIG16 is an operation timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit; the structure of the nth stage driving circuit is shown in FIG14;

[0618] The structure of the n-1th stage driving circuit is the same as that of the n-th stage driving circuit shown in FIG14 . The differences between the structure of the n-1th stage driving circuit and the n-th stage driving circuit shown in FIG14 include:

[0619] The drain of T15 is electrically connected to the n-1th stage driving signal output terminal OTn-1, and the drain of CT12 is electrically connected to the n-1th stage inverting signal output terminal FTn-1;

[0620] The gate of CT9 is electrically connected to the n-2-th level drive signal output terminal OTn-2, the gate of CT8 is electrically connected to the n-2-th level inverting signal output terminal FTn-2, the gate of CT10 is electrically connected to the n-1-th level inverting signal output terminal FTn-1, the gates of CT7, CT3, and CT4 are electrically connected to the n-1-th level drive signal output terminal OTn-1, and the drain of CT5 is electrically connected to the n-1-th level first scanning terminal NTn-1.

[0621] As shown in FIG16 , when at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit are in operation,

[0622] In the first phase t1, EN outputs a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal.

[0623] In the n-1th level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned on, EN is connected to CS, and the potential of CS is high voltage; OTn-1 provides a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT4 is turned off, CT6 is turned on, CT5 is turned off, and NTn-1 outputs a low voltage signal;

[0624] In the nth-level driving circuit, CT7 and CT8 are turned off, and EN is disconnected from CS; OTn provides a low-voltage signal, CT1 is turned on, CO outputs a high-voltage signal, CT6 is turned on, and NTn outputs a low-voltage signal;

[0625] In the second phase t2, EN provides a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal.

[0626] In the n-1th level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned off, EN is disconnected from CS, and the potential of CS is maintained at a high voltage; CT3 is turned off, OTn-1 provides a high voltage signal, CT4 is turned on, CT2 is turned on, CO outputs a low voltage signal, CT5 is turned on, and NTn-1 provides a high voltage signal;

[0627] In the n-th stage driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned on, EN is connected to CS, the potential of CS is a high voltage signal, CT3 is turned off, OTn outputs a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn provides a low voltage signal;

[0628] In the third phase t3, EN provides a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal.

[0629] In the n-1th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, CC2 maintains the potential of CS at a high voltage; OTn-1 provides a high voltage signal, CT2 and CT4 are turned on, CO outputs a low voltage signal, CT5 is turned on, and NTn-1 provides a high voltage signal;

[0630] In the n-th stage driving circuit, CT9 and CT10 are turned off, EN is disconnected from CS, the potential of CS is high, OTn provides a high voltage signal, CT2 and CT4 are both turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn provides a low voltage signal;

[0631] In the fourth phase t4, EN provides a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal.

[0632] In the n-1th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, CC2 maintains the potential of CS at a low voltage; OTn-1 provides a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn-1 provides a low voltage signal;

[0633] In the n-th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, the potential of CS is high, OTn provides a high voltage signal, CT2 and CT4 are both turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn provides a low voltage signal;

[0634] In the fifth stage t5, EN provides a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal.

[0635] In the n-1th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, CC2 maintains the potential of CS at a low voltage; CT3 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn-1 provides a low voltage signal;

[0636] In the n-th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, the potential of CS is high voltage, OTn provides a low voltage signal, CT1 is turned on, CO outputs a high voltage signal, CT6 is turned on, and NTn provides a low voltage signal.

[0637] As shown in FIG16 , NTn provides an invalid voltage signal, and NTn-1 provides a valid first scanning signal of the n-1th level, which can control the transistor whose gate is electrically connected to NTn in the pixel circuit of the n-th row to be turned off so as not to perform scanning; when the potential of the first scanning signal of the n-1th level is a valid voltage, the transistor whose gate is electrically connected to NTn-1 in the pixel circuit of the n-1th row is controlled to be turned on so as to perform normal scanning, thereby achieving the purpose of partial refresh;

[0638] Since the transistor in the pixel circuit electrically connected to NTn is an n-type transistor, the invalid voltage signal provided by NTn is a low voltage signal.

[0639] As shown in FIG17 , based on at least one embodiment of the driving circuit shown in FIG12 , the n-th stage driving output terminal is the n-th stage first reset terminal PRn;

[0640] The first control circuit includes a first control transistor CT1, a second control transistor CT2, a third control transistor CT3, and a fourth control transistor CT4; the second control circuit includes a fifth control transistor CT5 and a sixth control transistor CT6; the first energy storage circuit includes a first capacitor CC1; the first control voltage line is the second voltage line, and the second control voltage line is the first voltage line;

[0641] The gate of the first control transistor CT1 is electrically connected to the control signal terminal CS, the source of the first control transistor CT1 is electrically connected to the drain of the third control transistor CT3, and the drain of the first control transistor CT1 is electrically connected to the control output terminal CO;

[0642] The gate of the second control transistor CT2 is electrically connected to the control signal terminal CS, the source of the second control transistor CT2 is electrically connected to the control output terminal CO, and the drain of the second control transistor CT2 is electrically connected to the low voltage line VGL;

[0643] The gate of the third control transistor CT3 is electrically connected to the n-th stage drive signal output terminal OTn, and the source of the third control transistor CT3 is electrically connected to the high voltage line VGH;

[0644] The gate of the fourth control transistor CT4 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the fourth control transistor CT4 is electrically connected to the control output terminal CO, and the drain of the fourth control transistor CT4 is electrically connected to the low voltage line VGL;

[0645] The gate of the fifth control transistor CT5 is electrically connected to the control output terminal CO, the source of the fifth control transistor CT5 is electrically connected to the high voltage line VGH, and the drain of the fifth control transistor CT5 is electrically connected to the n-th stage first reset terminal PRn;

[0646] The gate of the sixth control transistor CT6 is electrically connected to the control output terminal CO, the source of the sixth control transistor CT6 is electrically connected to the n-th stage first reset terminal PRn, and the drain of the sixth control transistor CT6 is electrically connected to the low voltage line VGL;

[0647] A first end of the first capacitor CC1 is electrically connected to the control output terminal CO, and a second end of the first capacitor CC1 is electrically connected to the low voltage line VGL;

[0648] The second energy storage circuit includes a second capacitor CC2;

[0649] A first end of the second capacitor CC2 is electrically connected to the control signal terminal CS, and a second end of the second capacitor CC2 is electrically connected to the low voltage line VGL;

[0650] The control signal generating circuit includes a seventh control transistor CT7, an eighth control transistor CT8, a ninth control transistor CT9 and a tenth control transistor CT10;

[0651] The gate of the seventh control transistor CT7 is electrically connected to the n-1th stage drive signal output terminal OTn-1, the source of the seventh control transistor CT7 is electrically connected to the enable signal line EN, and the drain of the seventh control transistor CT7 is electrically connected to the source of the tenth control transistor CT10;

[0652] The gate of the eighth control transistor CT8 is electrically connected to the n-1th stage inverting signal output terminal FTn-1, the source of the eighth control transistor CT8 is electrically connected to the enable signal line EN, and the drain of the eighth control transistor CT8 is electrically connected to the source of the ninth control transistor CT9;

[0653] The gate of the ninth control transistor CT9 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the ninth control transistor CT9 is electrically connected to the source of the tenth control transistor CT10, and the drain of the ninth control transistor CT9 is electrically connected to the control signal terminal CS;

[0654] The gate of the tenth control transistor CT10 is electrically connected to the n-th stage inverting signal output terminal FTn, and the drain of the tenth control transistor CT10 is electrically connected to the control signal terminal CS;

[0655] The output inverting circuit includes an eleventh control transistor CT11 and a twelfth control transistor CT12;

[0656] The gate of the eleventh control transistor CT11 is electrically connected to the n-th stage driving signal output terminal OTn, the source of the eleventh control transistor CT11 is electrically connected to the n-th stage inverting signal output terminal FTn, and the drain of the eleventh control transistor CT11 is electrically connected to the low voltage line VGL;

[0657] The gate of the twelfth control transistor CT12 is electrically connected to the n-th stage driving signal output terminal OTn, the source of the twelfth control transistor CT12 is electrically connected to the high voltage line VGH, and the drain of the twelfth control transistor CT12 is electrically connected to the n-th stage inverting signal output terminal FTn;

[0658] The first node control circuit includes a first transistor T1, a second transistor T2 and a third transistor T3; the second output node control circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7;

[0659] The gate of the first transistor T1 is electrically connected to the second first clock signal line CK2, the source of the first transistor T1 is electrically connected to the low voltage line VGL, and the drain of the first transistor T1 is electrically connected to the source of the third transistor T3;

[0660] The gate of the second transistor T2 is electrically connected to the drain of the fourth transistor T4, the source of the second transistor T2 is electrically connected to the second first clock signal line CK2, and the drain of the second transistor T2 is electrically connected to the source of the third transistor T3;

[0661] The gate of the third transistor T3 is electrically connected to the low voltage line VGL, and the drain of the third transistor T3 is electrically connected to the first node N1;

[0662] The gate of the fourth transistor T4 is electrically connected to the second first clock signal line CK2, and the source of the fourth transistor T4 is electrically connected to the input terminal I0;

[0663] The gate of the fifth transistor T5 is electrically connected to the low voltage line VGL, the source of the fifth transistor T5 is electrically connected to the drain of the fourth transistor T4, and the drain of the fifth transistor T5 is electrically connected to the second output node NJ2;

[0664] The gate of the sixth transistor T6 and the source of the sixth transistor T6 are both electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the second output node NJ2;

[0665] The gate of the seventh transistor T7 is electrically connected to the control voltage line VEL, the source of the seventh transistor T7 is electrically connected to the high voltage line VGH, and the drain of the seventh transistor T7 is electrically connected to the source of the fifth transistor T5;

[0666] The second node control circuit includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a third capacitor C3;

[0667] The gate of the eighth transistor T8 is electrically connected to the second node N2, the source of the eighth transistor T8 is electrically connected to the second second clock signal line CB2, and the drain of the eighth transistor T8 is electrically connected to the first intermediate node NZ1;

[0668] The gate of the ninth transistor T9 is electrically connected to the drain of the first transistor T1, the source of the ninth transistor T9 is electrically connected to the high voltage line VGH, and the drain of the ninth transistor T9 is electrically connected to the first intermediate node NZ1;

[0669] The gate of the tenth transistor T10 is electrically connected to the second first clock signal line CK2, the source of the tenth transistor T10 is electrically connected to the input terminal I0, and the drain of the tenth transistor T10 is electrically connected to the source of the eleventh transistor T11;

[0670] The gate of the eleventh transistor T11 is electrically connected to the low voltage line VGL, and the drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0671] The first plate of the third capacitor C3 is electrically connected to the second node N2, and the second plate of the third capacitor C3 is electrically connected to the first intermediate node NZ1;

[0672] The first output node control circuit includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14 and a fourth capacitor C4;

[0673] The gate of the twelfth transistor T12 is electrically connected to the first node N1, the source of the twelfth transistor T12 is electrically connected to the second second clock signal line CB2, and the drain of the twelfth transistor T12 is electrically connected to the second intermediate node NZ2;

[0674] The gate of the thirteenth transistor T13 is electrically connected to the second second clock signal line CB, the source of the thirteenth transistor T13 is electrically connected to the second intermediate node NZ2, and the drain of the thirteenth transistor T13 is electrically connected to the first output node NJ1;

[0675] The gate of the fourteenth transistor T14 is electrically connected to the source of the fifth transistor T5, the source of the fourteenth transistor T14 is electrically connected to the high voltage line VGH, and the drain of the fourteenth transistor T14 is electrically connected to the first output node NJ1;

[0676] The first plate of the fourth capacitor C4 is electrically connected to the first node N1, and the second plate of the fourth capacitor C4 is electrically connected to the second intermediate node NZ2;

[0677] The potential maintaining circuit includes a fifth capacitor C5;

[0678] A first plate of the fifth capacitor C5 is electrically connected to the first output node NJ1, and a second plate of the fifth capacitor C5 is electrically connected to the high voltage line VGH;

[0679] The output circuit includes a fifteenth transistor T15 and a sixteenth transistor T16;

[0680] The gate of the fifteenth transistor T15 is electrically connected to the first output node NJ1, the source of the fifteenth transistor T15 is electrically connected to the high voltage line VGH, and the drain of the fifteenth transistor T15 is electrically connected to the n-th stage driving signal output terminal OTn;

[0681] The gate of the sixteenth transistor T16 is electrically connected to the second output node NJ2 , the source of the sixteenth transistor T16 is electrically connected to the n-th stage driving signal output terminal OTn, and the drain of the sixteenth transistor T16 is electrically connected to the low voltage line VGL.

[0682] In at least one embodiment of the driving circuit shown in FIG17 , T1 - T16 are all p-type transistors, CT1 , CT3 , CT5 , CT8 , CT9 , and CT12 are p-type transistors, and CT2 , CT4 , CT6 , CT7 , CT10 , and CT11 are n-type transistors.

[0683] In at least one embodiment of the driving circuit shown in FIG17 , the driving signal generating circuit is a 16T2C circuit. In actual operation, the driving signal generating circuit may also adopt a circuit having other structures for generating an n-th level driving signal.

[0684] FIG. 18 is an operation timing diagram of the driving signal generating circuit in at least one embodiment of the driving circuit shown in FIG. 17 .

[0685] FIG19 is an operation timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit; the structure of the nth stage driving circuit is shown in FIG17;

[0686] The structure of the n-1th stage driving circuit is the same as that of the n-th stage driving circuit shown in FIG17 . The differences between the structure of the n-1th stage driving circuit and the n-th stage driving circuit shown in FIG17 include:

[0687] The drain of T15 is electrically connected to the n-1th stage driving signal output terminal OTn-1, and the drain of CT12 is electrically connected to the n-1th stage inverting signal output terminal FTn-1;

[0688] The gate of CT7 is electrically connected to the n-1th stage drive signal output terminal OTn-1, the gate of CT8 is electrically connected to the n-1th stage inverting signal output terminal FTn-1, the gate of CT10 is electrically connected to the n-2th stage inverting signal output terminal FTn-2, the gate of CT9 is electrically connected to the n-2th stage drive signal output terminal OTn-2, the drain of CT5 is electrically connected to the n-1th stage first reset terminal PRn-1, and the gates of CT3 and CT4 are electrically connected to the n-1th stage drive signal output terminal OTn-1.

[0689] As shown in FIG19 , when at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit are in operation,

[0690] In the first phase t1, EN outputs a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal.

[0691] In the n-1th level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned on, EN is connected to CS, the potential of CS is low voltage, CT1 is turned on, OTn-1 provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PRn-1 provides a high voltage signal;

[0692] In the nth-stage driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned off, and EN is disconnected from CS.

[0693] In the second phase t2, EN outputs a low voltage signal, OTn-2 provides a low voltage signal, FTn-2 provides a high voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal.

[0694] In the n-1th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, the potential of CS is maintained at a low voltage, OTn-1 provides a low voltage signal, CT1 and CT3 are turned on, CO outputs a high voltage signal, CT6 is turned on, and PRn-1 provides a low voltage signal;

[0695] In the nth-level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned on, EN is connected to CS, and the potential of CS is low voltage; OTn provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PRn provides a high voltage signal;

[0696] In the third phase t3, EN provides a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a low voltage signal, FTn-1 provides a high voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal.

[0697] In the n-1th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, the potential of CS is maintained at a low voltage, OTn-1 provides a low voltage signal, CT1 and CT3 are turned on, CO outputs a high voltage signal, CT6 is turned on, and PRn-1 provides a low voltage signal;

[0698] In the n-th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, and the potential of CS is maintained at a low voltage; OTn provides a low voltage signal, CT1 and CT2 are turned on, CO outputs a high voltage signal, CT6 is turned on, and PRn provides a low voltage signal;

[0699] In the fourth phase t4, EN provides a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a low voltage signal, and FTn provides a high voltage signal.

[0700] In the n-1th level driving circuit, CT7 and CT8 are turned on, CT9 and CT10 are turned off, EN is disconnected from CS, the potential of CS is maintained at a low voltage, OTn-1 provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PRn-1 provides a high voltage signal;

[0701] In the n-th stage driving circuit, CT7 and CT8 are turned off, EN is disconnected from CS, and the potential of CS is maintained at a low voltage; OTn provides a low voltage signal, CT1 and CT2 are turned on, CO outputs a high voltage signal, CT6 is turned on, and PRn provides a low voltage signal;

[0702] In the fifth stage t5, EN provides a high voltage signal, OTn-2 provides a high voltage signal, FTn-2 provides a low voltage signal, OTn-1 provides a high voltage signal, FTn-1 provides a low voltage signal, OTn provides a high voltage signal, and FTn provides a low voltage signal.

[0703] In the n-1th level driving circuit, CT9 and CT10 are turned on, CT11 and CT12 are turned off, EN is disconnected from CS, the potential of CS is maintained at a low voltage, CT1 is turned on, CO1 outputs a high voltage signal, CT4 is turned on, CS is connected to VGL, OTn-1 provides a high voltage signal, CT6 is turned on, CO2 outputs a low voltage signal, CT7 is turned on, and PRn-1 provides a high voltage signal;

[0704] In the n-th level driving circuit, CT9 and CT10 are turned on, CT11 and CT12 are turned off, EN is disconnected from CS, and the potential of CS is maintained at a low voltage; OTn provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PRn provides a high voltage signal.

[0705] As shown in FIG19 , PRn provides an invalid voltage signal, and PRn-1 provides a valid first reset signal of the n-1th level, which can control the transistor whose gate is electrically connected to PRn in the pixel circuit of the n-th row to be turned off so as not to perform a reset; when the potential of the first reset signal of the n-1th level is a valid voltage, the transistor whose gate is electrically connected to PRn-1 in the pixel circuit of the n-1th row is controlled to be turned on so as to perform a normal reset;

[0706] Since the transistors in the pixel circuit electrically connected to PRn are p-type transistors, the invalid voltage signal provided by PRn is a high voltage signal.

[0707] As shown in FIG20 , based on at least one embodiment of the driving circuit shown in FIG13 , the n-th stage driving output terminal is the n-th stage second scanning terminal PTn;

[0708] The first control circuit includes a first control transistor CT1, a second control transistor CT2, a third control transistor CT3 and a fourth control transistor CT4; the second control circuit includes a fifth control transistor CT5 and a sixth control transistor CT6; the first energy storage circuit includes a first capacitor CC1;

[0709] The gate of the first control transistor CT1 is electrically connected to the control signal terminal CS, the source of the first control transistor CT1 is electrically connected to the drain of the third control transistor CT3, and the drain of the first control transistor CT1 is electrically connected to the control output terminal CO;

[0710] The gate of the second control transistor CT2 is electrically connected to the control signal terminal CS, the source of the second control transistor CT2 is electrically connected to the control output terminal CO, and the drain of the second control transistor CT2 is electrically connected to the low voltage line VGL;

[0711] The gate of the third control transistor CT3 is electrically connected to the n-th stage drive signal output terminal OTn, and the source of the third control transistor CT3 is electrically connected to the high voltage line VGH;

[0712] The gate of the fourth control transistor CT4 is electrically connected to the n-th stage drive signal output terminal OTn, the source of the fourth control transistor CT4 is electrically connected to the control output terminal CO, and the drain of the fourth control transistor CT4 is electrically connected to the low voltage line VGL;

[0713] The gate of the fifth control transistor CT5 is electrically connected to the control output terminal CO, the source of the fifth control transistor CT5 is electrically connected to the high voltage line VGH, and the drain of the fifth control transistor CT5 is electrically connected to the n-th stage second scanning terminal PTn;

[0714] The gate of the sixth control transistor CT6 is electrically connected to the control output terminal CO, the source of the sixth control transistor CT6 is electrically connected to the n-th stage second scanning terminal PTn, and the drain of the sixth control transistor CT6 is electrically connected to the low voltage line VGL;

[0715] A first end of the first capacitor CC1 is electrically connected to the control output terminal CO, and a second end of the first capacitor CC1 is electrically connected to the low voltage line VGL;

[0716] The control signal generating circuit includes a seventh control transistor CT7 and an eighth control transistor CT8;

[0717] The gate of the seventh control transistor CT7 is electrically connected to the enable signal line EN, the source of the seventh control transistor CT7 is electrically connected to the high voltage line VGH, and the drain of the seventh control transistor CT7 is electrically connected to the control signal terminal CS;

[0718] The gate of the eighth control transistor CT8 is electrically connected to the enable signal line EN, the source of the eighth control transistor CT8 is electrically connected to the control signal terminal CS, and the drain of the eighth control transistor CT8 is electrically connected to the low voltage line VGL;

[0719] CT1, CT3, and CT5 are p-type transistors, CT2, CT4, and CT6 are n-type transistors; CT7 is a p-type transistor, and CT8 is an n-type transistor;

[0720] The first output node control circuit includes a seventeenth transistor T17, an eighteenth transistor T18 and a sixth capacitor C6;

[0721] The gate of the seventeenth transistor T17 is electrically connected to the third first clock signal line CK3, the source of the seventeenth transistor T17 is electrically connected to the low voltage line VGL, and the drain of the seventeenth transistor T17 is electrically connected to the first output node NJ1;

[0722] The gate of the eighteenth transistor T18 is electrically connected to the second output node NJ2, the source of the eighteenth transistor T18 is electrically connected to the third first clock signal line CK3, and the drain of the eighteenth transistor T18 is electrically connected to the first output node NJ1;

[0723] The first plate of the sixth capacitor C6 is electrically connected to the first output node NJ1, and the second plate of the sixth capacitor C6 is electrically connected to the high voltage line VGH;

[0724] The second output node control circuit includes a nineteenth transistor T19, a twentieth transistor T20 and a twenty-first transistor T21; the third energy storage circuit includes a seventh capacitor C7;

[0725] The gate of the nineteenth transistor T19 is electrically connected to the third first clock signal line CK3, the source of the nineteenth transistor T19 is electrically connected to the input terminal I0, and the drain of the nineteenth transistor T19 is electrically connected to the second output node NJ2;

[0726] a gate of the 20th transistor T20 is electrically connected to the first output node NJ1, a source of the 20th transistor T20 is electrically connected to the high voltage line VGH, and a drain of the 20th transistor T20 is electrically connected to the source of the 21st transistor T21;

[0727] A gate of the twenty-first transistor T21 is electrically connected to the third second clock signal line CB3, and a second electrode of the twenty-first transistor T21 is electrically connected to the second output node NJ2;

[0728] The first plate of the seventh capacitor C7 is electrically connected to the second output node NJ2, and the second plate of the seventh capacitor C7 is electrically connected to the n-th stage driving signal output terminal OTn;

[0729] The output circuit includes a twenty-second transistor T22 and a twenty-third transistor T23;

[0730] The gate of the 22nd transistor T22 is electrically connected to the first output node NJ1, the source of the 22nd transistor T22 is electrically connected to the high voltage line VGH, and the drain of the 22nd transistor T22 is electrically connected to the n-th stage driving signal output terminal OTn;

[0731] a gate of the twenty-third transistor T23 electrically connected to the second output node NJ2, a source of the twenty-third transistor T23 electrically connected to the n-th stage drive signal output terminal OTn, and a drain of the twenty-third transistor T23 electrically connected to the third second clock signal line CB3;

[0732] The driving circuit further includes a twenty-fourth transistor T24;

[0733] The drain of the twenty-first transistor T21 is electrically connected to the second output node NJ2 via the twenty-fourth transistor T24;

[0734] A gate of the 24th transistor T24 is electrically connected to the low voltage line VGL, a source of the 24th transistor T24 is electrically connected to the drain of the 21st transistor T21 , and a drain of the 24th transistor T24 is electrically connected to the second output node NJ2 .

[0735] In at least one embodiment of the driving circuit shown in FIG. 20 , T17 - T24 are p-type transistors, but the present invention is not limited thereto.

[0736] In at least one embodiment of the driving circuit shown in FIG. 20 , T24 may not be provided.

[0737] In at least one embodiment of the driving circuit shown in FIG20 , the driving signal generating circuit is an 8T2C circuit. In actual operation, the driving signal generating circuit may also adopt a circuit having other structures for generating an n-th level driving signal.

[0738] FIG. 21 is an operation timing diagram of a driving signal generating circuit in at least one embodiment of the driving circuit shown in FIG. 20 .

[0739] FIG22 is an operation timing diagram of at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit; the structure of the nth stage driving circuit is shown in FIG20;

[0740] The structure of the n-1th stage driving circuit is the same as that of the n-th stage driving circuit shown in FIG20 . The differences between the structure of the n-1th stage driving circuit and the n-th stage driving circuit shown in FIG20 include:

[0741] The drain of T22 is electrically connected to the n-1th stage driving signal output terminal OTn-1;

[0742] The gates of CT5 and CT6 are both electrically connected to the n-1th stage driving signal output terminal OTn-1, and the drain of CT5 is electrically connected to the n-1th stage second scanning terminal PTn-1.

[0743] As shown in FIG22 , when at least one embodiment of the n-1th stage driving circuit and at least one embodiment of the nth stage driving circuit are in operation,

[0744] In the first phase t1, EN provides a high voltage signal, OTn-1 provides a high voltage signal, and OTn provides a high voltage signal;

[0745] In the n-1th stage driving circuit, CT8 is turned on, CS is connected to VGL, the potential of CS is low, CT1 is turned on; OTn-1 provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn-1 provides a high voltage signal;

[0746] In the n-th stage driving circuit, CT8 is turned on, CS is connected to VGL, the potential of CS is low, CT1 is turned on; OTn provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn provides a high voltage signal;

[0747] In the second phase t2, EN provides a high voltage signal, OTn-1 provides a low voltage signal, and OTn provides a high voltage signal;

[0748] In the n-1th stage driving circuit, CT8 is turned on, CS is connected to VGL, the potential of CS is low, CT1 is turned on, CO outputs a high voltage signal, OTn-1 provides a low voltage signal, CT3 is turned on, CO outputs a high voltage signal, CT6 is turned on, and PTn-1 outputs a low voltage signal;

[0749] In the n-th stage driving circuit, CT8 is turned on, CS is connected to VGL, the potential of CS is low, CT1 is turned on; OTn provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn provides a high voltage signal;

[0750] In the third phase t3, EN provides a low voltage signal, OTn-1 provides a high voltage signal, and OTn provides a low voltage signal;

[0751] In the n-1th level driving circuit, CT7 is turned on, CS is connected to VGH, the potential of CS is high voltage, CT2 is turned on, CT5 is turned on, OTn-1 provides a high voltage signal, CT4 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn-1 outputs a high voltage signal;

[0752] In the n-th stage driving circuit, CT7 is turned on, CS is connected to VGH, the potential of CS is high voltage, CT2 is turned on, CO outputs a low voltage signal, CT5 is turned on, and PTn provides a high voltage signal;

[0753] In the fourth phase t4, EN provides a low voltage signal, OTn-1 provides a high voltage signal, and OTn provides a high voltage signal;

[0754] In the n-1th level driving circuit, CT7 is turned on, CS is connected to VGH, the potential of CS is high voltage, CT2 is turned on, CO outputs a low voltage signal, CT1 is turned on, OTn-1 provides a high voltage signal, CT4 is turned on, CT5 is turned on, and PTn-1 outputs a high voltage signal;

[0755] In the nth-level driving circuit, CT7 is turned on, CS is connected to VGH, the potential of CS is high voltage, CT2 is turned on, CO71 outputs a low voltage signal, CT1 is turned on, OTn provides a high voltage signal, CT4 is turned on, CT5 is turned on, and PTn provides a high voltage signal.

[0756] As shown in FIG22 , PTn provides an invalid voltage signal, and PTn-1 provides a valid second scanning signal of the n-1th level, which can control the transistor whose gate is electrically connected to PTn in the pixel circuit of the n-th row to be turned off so as not to perform scanning; when the potential of the second scanning signal of the n-1th level is a valid voltage, the transistor whose gate is electrically connected to PTn-1 in the pixel circuit of the n-1th row is controlled to be turned on so as to perform normal scanning;

[0757] Since the transistor in the pixel circuit electrically connected to PTn is a p-type transistor, the invalid voltage signal provided by PTn is a high voltage signal.

[0758] In an embodiment of the present disclosure, the display substrate includes a base and the above-mentioned driving circuit disposed on the base;

[0759] The display substrate includes a display area and a peripheral area; the driving circuit is arranged in the peripheral area.

[0760] As shown in FIG23 , the display substrate P0 includes a display area A0 and a peripheral area AZ;

[0761] The driving circuit is arranged in the peripheral area AZ;

[0762] Multiple rows and columns of pixel circuits are arranged in the display area A0.

[0763] In a specific implementation, the driving circuit may be arranged on the left side and / or the right side of the display area A01.

[0764] In at least one embodiment of the present disclosure, the driving circuit further includes an output inverting circuit;

[0765] The output inversion circuit is electrically connected to the n-th level driving signal output terminal and the n-th level inverted signal output terminal, respectively, and is used to invert the n-th level driving signal to obtain and output the n-th level inverted driving signal through the n-th level inverted signal output terminal;

[0766] The control signal generating circuit is further electrically connected to the n-1th level driving signal output terminal, the nth level inverted signal output terminal, the nth level driving signal output terminal and the nth level inverted signal output terminal, respectively, and is used to generate a control signal according to an enable signal provided by an enable signal line under the control of the n-1th level driving signal, the n-1th level inverted signal, the nth level driving signal and the nth level inverted signal;

[0767] The n-1th level driving signal output terminal is used to provide the n-1th level driving signal, and the n-1th level inverting signal output terminal is used to provide the n-1th level inverting signal;

[0768] The control signal generating circuit is arranged on a side of the driving signal generating circuit close to the display area.

[0769] Optionally, the control circuit in the driving circuit includes a first control circuit, a second control circuit and a first energy storage circuit; the control circuit is arranged on a side of the driving signal generating circuit close to the display area;

[0770] The first control circuit is electrically connected to the control signal terminal, the n-th drive signal output terminal, the first control voltage line, the second control voltage line, and the control output terminal, respectively, and is configured to control the connection between the control output terminal and the first control voltage line under the control of the control signal, control the connection or disconnection between the control output terminal and the first control voltage line under the control of the n-level drive signal, and control the connection or disconnection between the control output terminal and the second control voltage line under the control of the n-level drive signal and the control signal;

[0771] The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line, and the second voltage line, respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal;

[0772] The first energy storage circuit is electrically connected to the control output terminal, and is used to maintain the potential of the control output terminal;

[0773] The first control voltage line is the first voltage line, and the second control voltage line is the second voltage line; or, the first control voltage line is the second voltage line, and the second control voltage line is the first voltage line.

[0774] In at least one embodiment of the present disclosure, the control circuit further includes a second energy storage circuit;

[0775] The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal;

[0776] The second energy storage circuit is arranged on a side of the second control circuit away from the display area.

[0777] Optionally, the drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; the drive signal generating circuit is arranged in the

[0778] The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node;

[0779] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal, and the second voltage line, respectively, and is configured to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line;

[0780] The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node, and the first voltage line, respectively, and is configured to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0781] The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0782] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0783] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0784] Optionally, the driving signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit;

[0785] The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node;

[0786] The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal, and the second voltage line, respectively, and is configured to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line;

[0787] The first output node control circuit is electrically connected to the first output node, the first node, the second second-clock signal line, the second intermediate node, the second output node, and the first voltage line, respectively, and is configured to control the second intermediate node to be connected to the second second-clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second-clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node;

[0788] The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line;

[0789] The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node;

[0790] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

[0791] In at least one embodiment of the present disclosure, the drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit, and an output circuit; the drive signal generating circuit is arranged on a side of the control signal generating circuit included in the drive circuit that is away from the display area; and the transistors in the output circuit are arranged on a side of the transistors included in the drive signal generating circuit other than the transistors in the output circuit that are closer to the display area.

[0792] The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line, and the second output node, respectively, and is configured to control communication between the first output node and the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control communication between the first output node and the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node;

[0793] The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node, and the first voltage line, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the second output node to be connected to the first voltage line under the control of the potential of the first output node and the second clock signal provided by the third second clock signal line;

[0794] A first end of the third energy storage circuit is electrically connected to the second output node, a second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electrical energy;

[0795] The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node.

[0796] 24A , 24B and 24C are first layout diagrams of at least one embodiment of the driving circuit shown in FIG. 14 .

[0797] Figure 25 is a layout diagram of the first semiconductor layer in Figure 24A, Figure 26 is a layout diagram of the first gate metal layer in Figure 24A, Figure 27 is a layout diagram of the second gate metal layer in Figure 24A, Figure 28 is a layout diagram of the first source-drain metal layer in Figure 24A, Figure 29 is a layout diagram of the second source-drain metal layer in Figure 24A, and Figure 30 is a layout diagram of the third source-drain metal layer in Figure 24A.

[0798] Figure 31A is an overlay image of the first semiconductor layer and the first gate metal layer in Figure 24A, Figure 31B is an overlay image of the first gate metal layer and the second gate metal layer in Figure 24A, Figure 31C is an overlay image of the second gate metal layer and the first source-drain metal layer in Figure 24A, Figure 31D is an overlay image of the first source-drain metal layer and the second source-drain metal layer in Figure 24A, and Figure 31E is an overlay image of the second source-drain metal layer and the third source-drain metal layer in Figure 24A.

[0799] In FIG25 , AT1 is the active pattern of CT1, AT2 is the active pattern of CT2, AT3 is the active pattern of CT3, AT4 is the active pattern of CT4, AT5 is the active pattern of CT5, AT6 is the active pattern of CT6, AT7 is the active pattern of CT7, AT8 is the active pattern of CT8, AT9 is the active pattern of CT9, AT10 is the active pattern of CT10, AT11 is the active pattern of CT11, and AT12 is the active pattern of CT12;

[0800] A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0801] In FIG26 , CC11 is the first electrode plate of CC1 , CC21 is the first electrode plate of CC2 , C31 is the first electrode plate of C3 , C41 is the first electrode plate of C4 , and C51 is the first electrode plate of C5 .

[0802] In FIG27 , the second electrode plate labeled CC12 is CC1, the second electrode plate labeled CC22 is CC2, the second electrode plate labeled C32 is C3, the second electrode plate labeled C42 is C4, and the second electrode plate labeled C52 is C5.

[0803] In at least one embodiment of the display substrate shown in FIG24A , the first semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer are arranged in sequence in a direction away from the substrate.

[0804] At least one embodiment of the display substrate shown in FIG. 24A is a driving circuit manufactured using a CMOS (Complementary Metal Oxide Semiconductor) process.

[0805] In at least one embodiment of the present disclosure, the first semiconductor layer may be made of polysilicon, and the second semiconductor layer may be made of IGZO (indium gallium zinc oxide), but the present invention is not limited thereto.

[0806] In at least one embodiment of the present disclosure, the control signal generating circuit and the control circuit are arranged on a side of the driving signal generating circuit close to the display area, so that the control circuit provides corresponding driving signals to the pixel circuits arranged in the display area.

[0807] In at least one embodiment of the present disclosure, the first voltage lines include a first first voltage line and a second first voltage line sequentially arranged in a direction away from the display area, and the second voltage lines include a first second voltage line and a second second voltage line sequentially arranged in a direction away from the display area;

[0808] The orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate;

[0809] The orthographic projection of the active pattern of at least part of the transistor included in the second control circuit on the substrate at least partially overlaps with the orthographic projection of the first second voltage line on the substrate;

[0810] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0811] An orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0812] In at least one embodiment of the present disclosure, the orthographic projection of each signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the corresponding transistor on the substrate, and the signal line and the electrode plate of the corresponding capacitor are arranged so that the orthographic projection on the substrate at least partially overlaps, so as to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0813] Optionally, the first voltage line may be a high voltage line, and the second voltage line may be a low voltage line.

[0814] As shown in FIG. 24A to FIG. 30 , the high voltage line includes a first first voltage line V11 and a second first voltage line V21 , and the second voltage line includes a first second voltage line V12 and a second second voltage line V22 ;

[0815] V11 and V21 are arranged in sequence along a side away from the display area, and V12 and V22 are arranged in sequence along a side away from the display area;

[0816] In FIG24A to FIG30, the first scanning end labeled NTn is the nth stage;

[0817] As shown in FIG. 24A to FIG. 30 , the orthographic projection of the active pattern AT6 of CT6 on the substrate at least partially overlaps with the orthographic projection of V11 on the substrate; the orthographic projection of the active pattern AT5 of CT5 on the substrate at least partially overlaps with the orthographic projection of V11 on the substrate;

[0818] The orthographic projection of the active pattern AT6 of CT6 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the active pattern AT5 of CT5 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate;

[0819] The orthographic projection of the active pattern AT4 of CT4 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the active pattern AT2 of CT2 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate;

[0820] The orthographic projection of the first electrode plate CC11 of CC1 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the second electrode plate CC12 of CC1 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate;

[0821] The orthographic projection of the first electrode plate CC21 of CC2 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the second electrode plate CC22 of CC2 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate;

[0822] The orthographic projection of the enable signal line EN on the substrate at least partially overlaps with the orthographic projection of the active pattern of CT8 on the substrate.

[0823] In at least one embodiment of the present disclosure, an orthographic projection of the first second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second energy storage circuit on the substrate;

[0824] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0825] As shown in FIG. 24A to FIG. 30 , the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT7 of CT7 on the substrate.

[0826] In at least one embodiment of the present disclosure, an orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

[0827] As shown in FIG. 24A to FIG. 30 , the orthographic projection of the enable signal line EN on the substrate at least partially overlaps with the orthographic projection of the active pattern of CT12 on the substrate; the orthographic projection of the enable signal line EN on the substrate at least partially overlaps with the orthographic projection of the active pattern of CT11 on the substrate.

[0828] Optionally, the first first voltage line, the second first voltage line, the first second voltage line, the second second voltage line and the enable signal line all extend along a first direction;

[0829] The width of the first first voltage line along the second direction is greater than the width of the second first voltage line along the second direction;

[0830] The width of the first second voltage line along the second direction is greater than the width of the second second voltage line along the second direction;

[0831] The first direction intersects the second direction.

[0832] In at least one embodiment of the present disclosure, the first voltage line may include at least two voltage lines electrically connected to each other, and the width of at least one voltage line of the at least two voltage lines electrically connected to each other included in the first voltage line may be set to be larger along the second direction to reduce the resistance of the first voltage line;

[0833] The second voltage line may include at least two electrically connected voltage lines, and the width of at least one of the at least two electrically connected voltage lines included in the second voltage line may be set to be larger along the second direction to reduce the resistance of the second voltage line.

[0834] Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction.

[0835] As shown in FIG. 24A to FIG. 30 , V11, V21, V12, V22 and EN all extend in the vertical direction.

[0836] The width of V11 along the horizontal direction is greater than the width of V21 along the horizontal direction.

[0837] The width of V12 along the horizontal direction is greater than the width of V22 along the horizontal direction.

[0838] In at least one embodiment of the present disclosure, CT5 and CT6 are transistors electrically connected to the n-th stage driver output terminal. The orthographic projection of the active pattern AT5 of CT5 on the substrate at least partially overlaps with the orthographic projection of V11 on the substrate; the orthographic projection of the active pattern AT6 of CT6 on the substrate at least partially overlaps with the orthographic projection of V11 on the substrate; the orthographic projection of the active pattern AT5 of CT5 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the orthographic projection of the active pattern AT6 of CT6 on the substrate at least partially overlaps with the orthographic projection of V12 on the substrate; the horizontal width of V11 is set to be larger, and the horizontal width of V12 is set to be larger, so as to reduce the resistance of V11 and the resistance of V12, thereby reducing the IR drop (IR drop, which is the voltage drop caused by current and resistance) of the high voltage line and the IR drop of the low voltage line.

[0839] In at least one embodiment of the present disclosure, the transistor included in the second control circuit is arranged on a side of the transistor included in the first control circuit close to the display area;

[0840] The control signal generating circuit includes a transistor that is disposed on a side of the second control circuit away from the display area.

[0841] As shown in FIG24A to FIG30 , the fifth control transistor CT5 and the sixth control transistor CT6 included in the second control circuit are arranged on a side of the first control transistor CT1, the second control transistor CT2, the third control transistor CT3 and the fourth control transistor CT4 included in the first control circuit close to the display area;

[0842] The seventh control transistor CT7 , the eighth control transistor CT8 , the ninth control transistor CT9 and the tenth control transistor CT10 included in the control signal generating circuit are arranged on a side of the fifth control transistor CT5 and the sixth control transistor CT6 included in the second control circuit away from the display area.

[0843] In at least one embodiment of the present disclosure, the first voltage lines include a first first voltage line, a second first voltage line, and a third first voltage line sequentially arranged in a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged in a direction away from the display area;

[0844] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0845] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0846] The orthographic projection of the second first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0847] An orthographic projection of the third first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0848] The orthographic projection of the third second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate;

[0849] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the first node control circuit on the substrate;

[0850] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second node control circuit on the substrate.

[0851] In at least one embodiment of the present disclosure, each signal line and the active pattern of the corresponding transistor are arranged so that their orthographic projections on the substrate at least partially overlap, so as to facilitate the realization of a narrow frame.

[0852] As shown in FIG. 24A to FIG. 30 , the first voltage lines include a first first voltage line V11 , a second first voltage line V21 , and a third first voltage line V31 , which are sequentially arranged in a direction away from the display area.

[0853] The second voltage lines include a first second voltage line V12, a second second voltage line V22 and a third second voltage line V32 sequentially arranged in a direction away from the display area;

[0854] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate, and the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0855] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate, and the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0856] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C51 of C5 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C52 of C5 on the substrate;

[0857] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A5 of T5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A6 of T6 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A7 of T7 on the substrate;

[0858] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A4 of T4 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A1 of T1 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A8 of T8 on the substrate;

[0859] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate.

[0860] In at least one embodiment of the present disclosure, the first first clock signal line and the second clock signal line are arranged between the third first voltage line and the third second voltage line;

[0861] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0862] The orthographic projection of the first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the second node control circuit on the substrate;

[0863] The orthographic projection of the first first clock signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor included in the first output node control circuit on the substrate;

[0864] The orthographic projections of the first and second clock signal lines on the substrate at least partially overlap with the orthographic projections of the plates of the capacitors included in the first output node control circuit on the substrate;

[0865] The orthographic projection of the first second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second node control circuit on the substrate.

[0866] As shown in FIG. 24A to FIG. 30 , the first first clock signal line CK1 and the first second clock signal line CB1 are provided between the third first voltage line V31 and the third second voltage line V32 ;

[0867] The orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0868] The orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate; the orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A12 of T12 on the substrate;

[0869] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate;

[0870] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0871] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0872] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate.

[0873] Optionally, the active graphics of at least part of the transistors included in the second control circuit include at least two independent active graphic parts, and the at least two independent active graphic parts are separated by a certain distance to facilitate heat dissipation, so as to improve the performance of the transistor while ensuring the area of ​​the active graphics.

[0874] 32A , 32B and 32C are second layout diagrams of at least one embodiment of the driving circuit shown in FIG. 14 .

[0875] Figure 33 is a layout diagram of the first semiconductor layer in Figure 32A, Figure 34 is a layout diagram of the first gate metal layer in Figure 32A, Figure 35 is a layout diagram of the second gate metal layer in Figure 32A, Figure 36 is a layout diagram of the second semiconductor layer in Figure 32A, Figure 37 is a layout diagram of the third gate metal layer in Figure 32A, Figure 38 is a layout diagram of the first source-drain metal layer in Figure 32A, Figure 39 is a layout diagram of the second source-drain metal layer in Figure 32A, and Figure 40 is a layout diagram of the third source-drain metal layer in Figure 32A.

[0876] FIG41A is a schematic diagram of the superposition of the first semiconductor layer and the first gate metal layer in FIG32A ; FIG41B is a schematic diagram of the superposition of the first gate metal layer and the second gate metal layer in FIG32A ;

[0877] Figure 41C is a schematic diagram of the superposition of the second gate metal layer and the second semiconductor layer in Figure 32A; Figure 41D is a schematic diagram of the superposition of the third gate metal layer and the second semiconductor layer in Figure 32A; Figure 41E is a schematic diagram of the superposition of the third gate metal layer and the first source-drain metal layer in Figure 32A; Figure 41F is a schematic diagram of the superposition of the first source-drain metal layer and the second source-drain metal layer in Figure 32A; Figure 41G is a schematic diagram of the superposition of the second source-drain metal layer and the third source-drain metal layer in Figure 32A.

[0878] In at least one embodiment of the display substrate shown in Figure 32A, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer are arranged in sequence along the direction away from the substrate.

[0879] At least one embodiment of the display substrate shown in FIG32A is a driving circuit manufactured using an LTPO (low temperature polycrystalline oxide) process.

[0880] In at least one embodiment of the present disclosure, the first semiconductor layer may be made of polysilicon, and the second semiconductor layer may be made of IGZO (indium gallium zinc oxide), but the present invention is not limited thereto.

[0881] In FIG33 and FIG36 , reference numeral AT1 is the active pattern of CT1, reference numeral AT2 is the active pattern of CT2, reference numeral AT3 is the active pattern of CT3, reference numeral AT4 is the active pattern of CT4, reference numeral AT5 is the active pattern of CT5, reference numeral AT6 is the active pattern of CT6, reference numeral AT7 is the active pattern of CT7, reference numeral AT8 is the active pattern of CT8, reference numeral AT9 is the active pattern of CT9, reference numeral AT10 is the active pattern of CT10, reference numeral AT11 is the active pattern of CT11, and reference numeral AT12 is the active pattern of CT12;

[0882] A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0883] In FIG34 , CC11 is the first electrode plate of CC1 , CC21 is the first electrode plate of CC2 , C31 is the first electrode plate of C3 , C41 is the first electrode plate of C4 , and C51 is the first electrode plate of C5 .

[0884] In Figure 35, the second electrode plate labeled CC12 is CC1, the second electrode plate labeled CC22 is CC2, the second electrode plate labeled C32 is C3, the second electrode plate labeled C42 is C4, and the second electrode plate labeled C52 is C5.

[0885] In FIG37 , the gate electrode CT61 is represented by a reference numeral GT61 and includes a gate electrode pattern.

[0886] As shown in FIG36 , the active pattern of CT5 includes two independent active pattern portions, and the active pattern of CT6 includes two independent active pattern portions;

[0887] The two independent active pattern portions are spaced a certain distance apart to facilitate heat dissipation, thereby improving transistor performance while ensuring the area of ​​the active pattern.

[0888] As shown in FIG32 to FIG40 , the first first voltage line V11, the first second voltage line V12, the second second voltage line V22, the second first voltage line V21, the third first voltage line V31 and the third second voltage line V32 are sequentially arranged in a direction away from the display area;

[0889] V11, V12, V22, V21, V31 and V32 all extend in the vertical direction;

[0890] EN, VEL, CK1, and CB1 all extend in the vertical direction;

[0891] V11, V12, EN, V22, V21, VEL, V31, CK1, CB1 and V32 are arranged in sequence in a direction away from the display area;

[0892] The orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate, and the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0893] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate, and the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0894] The orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT8 of CT8 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT12 of CT12 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT11 of CT11 on the substrate;

[0895] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT7 of CT7 on the substrate;

[0896] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT15 of T15 on the substrate; the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT16 of T16 on the substrate;

[0897] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT15 of T15 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT16 of T16 on the substrate;

[0898] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C51 of C5 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C52 of C5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A5 of T5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A6 of T6 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A7 of T7 on the substrate;

[0899] The orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate; the orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the active pattern A12 of T12 on the substrate;

[0900] The orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CK1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0901] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0902] The orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB1 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0903] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0904] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A4 of T4 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A1 of T1 on the substrate; and the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A8 of T8 on the substrate.

[0905] In at least one embodiment of the present disclosure, the first voltage lines include a first first voltage line, a second first voltage line, a third first voltage line, and a fourth first voltage line sequentially arranged in a direction away from the display area, and the second voltage lines include a first second voltage line, a second second voltage line, a third second voltage line, and a fourth second voltage line sequentially arranged in a direction away from the display area;

[0906] An orthographic projection of the third first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0907] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the potential maintaining circuit on the substrate;

[0908] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output circuit on the substrate;

[0909] An orthographic projection of the fourth first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the second output node control circuit on the substrate;

[0910] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the first node control circuit on the substrate;

[0911] An orthographic projection of the fourth second voltage line on the substrate at least partially overlaps with an orthographic projection of a plate of a capacitor included in the second node control circuit on the substrate.

[0912] In at least one embodiment of the present disclosure, the orthographic projection of each signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the corresponding transistor on the substrate, and the signal line and the electrode plate of the corresponding capacitor are arranged so that the orthographic projection on the substrate at least partially overlaps, so as to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0913] In at least one embodiment of the present disclosure, the display substrate further includes a second first clock signal line and a second second clock signal line disposed between the fourth first voltage line and the fourth second voltage line;

[0914] The orthographic projection of the second first clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0915] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0916] The orthographic projection of the second second clock signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first output node control circuit on the substrate;

[0917] An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second node control circuit on the substrate;

[0918] An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the first output node control circuit on the substrate.

[0919] In at least one embodiment of the present disclosure, the second first clock signal line and the second second clock signal line are arranged between the second first voltage line and the fourth second voltage line;

[0920] An orthographic projection of the second first clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second output node control circuit on the substrate;

[0921] An orthographic projection of the second second clock signal line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the second output node control circuit on the substrate.

[0922] In at least one embodiment of the present disclosure, an orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0923] The orthographic projection of the enabling signal line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0924] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the second energy storage circuit on the substrate;

[0925] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0926] 42A , 42B and 42C are first layout diagrams of at least one embodiment of the driving circuit shown in FIG. 17 .

[0927] Figure 43 is a layout diagram of the first semiconductor layer in Figure 42A, Figure 44 is a layout diagram of the first gate metal layer in Figure 42A, Figure 45 is a layout diagram of the second gate metal layer in Figure 42A, Figure 46 is a layout diagram of the first source-drain metal layer in Figure 42A, Figure 47 is a layout diagram of the second source-drain metal layer in Figure 42A, and Figure 48 is a layout diagram of the third source-drain metal layer in Figure 42A.

[0928] Figure 49A is an overlay image of the first semiconductor layer and the first gate metal layer in Figure 42A, Figure 49B is an overlay image of the first gate metal layer and the second gate metal layer in Figure 42A, Figure 49C is an overlay image of the second gate metal layer and the first source-drain metal layer in Figure 42A, Figure 49D is an overlay image of the first source-drain metal layer and the second source-drain metal layer in Figure 42A, and Figure 49E is an overlay image of the second source-drain metal layer and the third source-drain metal layer in Figure 42A.

[0929] In at least one embodiment of the display substrate shown in FIG42A , the first semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer are arranged in sequence in a direction away from the substrate.

[0930] At least one embodiment of the display substrate shown in FIG. 42A is a display substrate manufactured using a CMOS process.

[0931] In FIG43 , AT1 is the active pattern of CT1, AT2 is the active pattern of CT2, AT3 is the active pattern of CT3, AT4 is the active pattern of CT4, AT5 is the active pattern of CT5, AT6 is the active pattern of CT6, AT7 is the active pattern of CT7, AT8 is the active pattern of CT8, AT9 is the active pattern of CT9, AT10 is the active pattern of CT10, AT11 is the active pattern of CT11, and AT12 is the active pattern of CT12.

[0932] A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0933] In FIG44 , CC11 is the first electrode plate of CC1 , CC21 is the first electrode plate of CC2 , C31 is the first electrode plate of C3 , C41 is the first electrode plate of C4 , and C51 is the first electrode plate of C5 .

[0934] In Figure 45, the second electrode plate labeled CC12 is CC1, the second electrode plate labeled CC22 is CC2, the second electrode plate labeled C32 is C3, the second electrode plate labeled C42 is C4, and the second electrode plate labeled C52 is C5.

[0935] As shown in Figures 42A-42B, the first voltage lines include a first first voltage line V11, a second first voltage line V21, a third first voltage line V31, and a fourth first voltage line V41, which are sequentially arranged in a direction away from the display area; the second voltage lines include a first second voltage line V12, a second second voltage line V22, a third second voltage line V32, and a fourth second voltage line V42, which are sequentially arranged in a direction away from the display area.

[0936] The orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0937] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate; the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate;

[0938] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC11 of CC1 on the substrate; the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC12 of CC1 on the substrate;

[0939] The orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT4 of CT4 on the substrate; the orthographic projection of V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT3 of CT3 on the substrate;

[0940] The orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC21 of CC2 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC22 of CC2 on the substrate;

[0941] The orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT9 of CT9 on the substrate; the orthographic projection of EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT8 of CT8 on the substrate;

[0942] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC21 of CC2 on the substrate; the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC22 of CC2 on the substrate;

[0943] The orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT10 of CT10 on the substrate; the orthographic projection of V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT7 of CT7 on the substrate;

[0944] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0945] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C51 of C5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C52 of C5 on the substrate;

[0946] The orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A5 of T5 on the substrate; the orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A6 of T6 on the substrate; the orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A7 of T7 on the substrate;

[0947] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A4 of T4 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A1 of T1 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A8 of T8 on the substrate;

[0948] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate.

[0949] As shown in FIG. 42A to FIG. 42B , the display substrate further includes a second first clock signal line CK2 and a second second clock signal line CB2 disposed between V41 and V42 ;

[0950] The orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0951] The orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate; the orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the active pattern A12 of T12 on the substrate;

[0952] The orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0953] The orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate.

[0954] In at least one embodiment of the present disclosure, the second voltage line includes a third second voltage line; the third second voltage line is disposed on a side of the second second voltage line away from the display area;

[0955] An orthographic projection of the third second voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate.

[0956] As shown in FIG42A-48 , the second voltage lines include a third second voltage line V32 , which is disposed on a side of V22 away from the display area;

[0957] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0958] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT11 of CT11 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT12 of CT12 on the substrate;

[0959] In at least one embodiment of the present disclosure, an orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0960] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0961] The orthographic projection of the second second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[0962] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0963] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[0964] An orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least a portion of transistors included in the control signal generating circuit on the substrate.

[0965] In at least one embodiment of the present disclosure, the orthographic projection of each signal line on the substrate at least partially overlaps with the orthographic projection of the active pattern of the corresponding transistor on the substrate, and the signal line and the electrode plate of the corresponding capacitor are arranged so that the orthographic projection on the substrate at least partially overlaps, so as to reduce the lateral space occupied by the driving circuit, thereby facilitating the realization of a narrow frame.

[0966] 50A , 50B and 50C are second layout diagrams of at least one embodiment of the driving circuit shown in FIG. 17 .

[0967] Figure 51 is a layout diagram of the first semiconductor layer in Figure 50A, Figure 52 is a layout diagram of the first gate metal layer in Figure 50A, Figure 53 is a layout diagram of the second gate metal layer in Figure 50A, Figure 54 is a layout diagram of the second semiconductor layer in Figure 50A, Figure 55 is a layout diagram of the third gate metal layer in Figure 50A, Figure 56 is a layout diagram of the first source-drain metal layer in Figure 50A, Figure 57 is a layout diagram of the second source-drain metal layer in Figure 50A, and Figure 58 is a layout diagram of the third source-drain metal layer in Figure 50A.

[0968] FIG59A is a schematic diagram showing the superposition of the first semiconductor layer and the first gate metal layer in FIG50A ; FIG59B is a schematic diagram showing the superposition of the first gate metal layer and the second gate metal layer in FIG50A ;

[0969] Figure 59C is a schematic diagram of the superposition of the second gate metal layer and the second semiconductor layer in Figure 50A; Figure 59D is a schematic diagram of the superposition of the third gate metal layer and the second semiconductor layer in Figure 50A; Figure 59E is a schematic diagram of the superposition of the third gate metal layer and the first source-drain metal layer in Figure 50A; Figure 59F is a schematic diagram of the superposition of the first source-drain metal layer and the second source-drain metal layer in Figure 50A; Figure 59G is a schematic diagram of the superposition of the second source-drain metal layer and the third source-drain metal layer in Figure 50A.

[0970] In at least one embodiment of the display substrate shown in Figure 50A, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer are arranged in sequence along the direction away from the substrate.

[0971] At least one embodiment of the display substrate shown in FIG50A is a driving circuit manufactured using an LTPO (low temperature polycrystalline oxide) process.

[0972] In Figures 51 and 54, AT1 is the active pattern of CT1, AT2 is the active pattern of CT2, AT3 is the active pattern of CT3, AT4 is the active pattern of CT4, AT5 is the active pattern of CT5, AT6 is the active pattern of CT6, AT7 is the active pattern of CT7, AT8 is the active pattern of CT8, AT9 is the active pattern of CT9, AT10 is the active pattern of CT10, AT11 is the active pattern of CT11, and AT12 is the active pattern of CT12;

[0973] A1 is the active pattern of T1, A2 is the active pattern of T2, A3 is the active pattern of T3, A4 is the active pattern of T4, A5 is the active pattern of T5, A6 is the active pattern of T6, A7 is the active pattern of T7, A8 is the active pattern of T8, A9 is the active pattern of T9, A10 is the active pattern of T10, A11 is the active pattern of T11, A12 is the active pattern of T12, A13 is the active pattern of T13, A14 is the active pattern of T14, A15 is the active pattern of T15, and A16 is the active pattern of T16.

[0974] In Figure 52, the first electrode plate labeled CC11 is CC1, the first electrode plate labeled CC21 is CC2, the first electrode plate labeled C31 is C3, the first electrode plate labeled C41 is C4, and the first electrode plate labeled C51 is C5.

[0975] In Figure 53, the second electrode plate labeled CC12 is CC1, the second electrode plate labeled CC22 is CC2, the second electrode plate labeled C32 is C3, the second electrode plate labeled C42 is C4, and the second electrode plate labeled C52 is C5.

[0976] As shown in FIG50A to FIG58 , the orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT4 of CT4 on the substrate; the orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT2 of CT2 on the substrate;

[0977] The orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC11 of CC1 on the substrate; the orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC12 of CC1 on the substrate;

[0978] The orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate CC21 of CC2 on the substrate; the orthographic projection of the second second voltage line V22 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate CC22 of CC2 on the substrate;

[0979] In at least one embodiment of the present disclosure, an orthographic projection of the second first voltage line on the substrate at least partially overlaps with an orthographic projection of an active pattern of at least one transistor included in the output inverter circuit on the substrate;

[0980] The enable signal line is arranged on a side of the second first voltage line away from the display area.

[0981] As shown in FIG. 50A to FIG. 58 , the orthographic projection of the second first voltage line V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT12 of CT12 on the substrate; the orthographic projection of the second first voltage line V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT11 of CT11 on the substrate;

[0982] The orthographic projection of the second first voltage line V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT10 of CT10 on the substrate; the orthographic projection of the second first voltage line V21 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT3 of CT3 on the substrate;

[0983] The enable signal line EN is disposed on a side of the second first voltage line V21 away from the display area.

[0984] As shown in FIG50A to FIG58 , the first voltage lines include a first first voltage line V11, a second first voltage line V21, a third first voltage line V31, and a fourth first voltage line V41 sequentially arranged in a direction away from the display area; the second voltage lines include a first second voltage line V12, a second second voltage line V22, a third second voltage line V32, and a fourth second voltage line V42 sequentially arranged in a direction away from the display area;

[0985] V11, V12, V22, V21, EN, V32, V31, VEL, V41, CK2, CB2 and V42 are arranged in sequence in a direction away from the display area;

[0986] V11, V12, V22, V21, EN, V32, V31, VEL, V41, CK2, CB2 and V42 are arranged in sequence along the vertical direction.

[0987] As shown in FIG. 50A to FIG. 58 , the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate; the orthographic projection of V11 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate;

[0988] The orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT6 of CT6 on the substrate; the orthographic projection of V12 on the substrate at least partially overlaps with the orthographic projection of the active pattern AT5 of CT5 on the substrate;

[0989] The orthographic projection of the enable signal line EN on the substrate at least partially overlaps with the orthographic projection of the active pattern AT9 of CT9 on the substrate;

[0990] The orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate; the orthographic projection of V32 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0991] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A15 of T15 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the active pattern A16 of T16 on the substrate;

[0992] The orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C51 of C5 on the substrate; the orthographic projection of V31 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C52 of C5 on the substrate;

[0993] The orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A5 of T5 on the substrate; the orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A6 of T6 on the substrate; the orthographic projection of V41 on the substrate at least partially overlaps with the orthographic projection of the active pattern A7 of T7 on the substrate;

[0994] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A4 of T4 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A1 of T1 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the active pattern A8 of T8 on the substrate;

[0995] The orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of V42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate;

[0996] The orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0997] The orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the active pattern A9 of T9 on the substrate; the orthographic projection of CK2 on the substrate at least partially overlaps with the orthographic projection of the active pattern A12 of T12 on the substrate;

[0998] The orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C41 of C4 on the substrate; the orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C42 of C4 on the substrate;

[0999] The orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate C31 of C3 on the substrate; the orthographic projection of CB2 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate C32 of C3 on the substrate.

[1000] As shown in FIG50A , the active pattern of CT5 includes two independent active pattern portions, and the active pattern of CT6 includes two independent active pattern portions;

[1001] The two independent active pattern portions are spaced a certain distance apart to facilitate heat dissipation, thereby improving transistor performance while ensuring the area of ​​the active pattern.

[1002] 60A , 60B and 60C are first layout diagrams of at least one embodiment of the driving circuit shown in FIG. 20 .

[1003] Figure 61 is a layout diagram of the first semiconductor layer in Figure 60A, Figure 62 is a layout diagram of the first gate metal layer in Figure 60A, Figure 63 is a layout diagram of the second gate metal layer in Figure 60A, Figure 64 is a layout diagram of the first source and drain metal layer in Figure 60A, and Figure 65 is a layout diagram of the second source and drain metal layer in Figure 60A.

[1004] Figure 66A is an overlay image of the first semiconductor layer and the first gate metal layer in Figure 60A, Figure 66B is an overlay image of the first gate metal layer and the second gate metal layer in Figure 60A; Figure 66C is an overlay image of the second gate metal layer and the first source-drain metal layer in Figure 60A; Figure 66D is an overlay image of the first source-drain metal layer and the second source-drain metal layer in Figure 60A.

[1005] In at least one embodiment of the display substrate shown in FIG60A , the first semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer are arranged in sequence in a direction away from the substrate.

[1006] At least one embodiment of the display substrate shown in FIG60A is a display substrate manufactured using a CMOS process.

[1007] In FIG61 , AT1 is the active pattern of CT1, AT2 is the active pattern of CT2, AT3 is the active pattern of CT3, AT4 is the active pattern of CT4, AT5 is the active pattern of CT5, AT6 is the active pattern of CT6, AT7 is the active pattern of CT7, and AT8 is the active pattern of CT8.

[1008] A17 is the active pattern of T17, A18 is the active pattern of T18, A19 is the active pattern of T19, A20 is the active pattern of T20, A21 is the active pattern of T21, A22 is the active pattern of T22, A23 is the active pattern of T23, and A24 is the active pattern of T24.

[1009] In FIG62 , the first electrode plate of CC1 is labeled CC11 , the first electrode plate of C6 is labeled C61 , and the first electrode plate of C7 is labeled C71 .

[1010] In FIG63 , the second electrode plate labeled CC12 is the second electrode plate of CC1, the second electrode plate labeled C62 is the second electrode plate of C6, and the second electrode plate labeled C72 is the second electrode plate of C7.

[1011] In at least one embodiment of the present disclosure, the first voltage line includes a first first voltage line, the second voltage line includes a first second voltage line, a second second voltage line, and a third second voltage line sequentially arranged in a direction away from the display area; the enable signal line is provided between the second second voltage line and the third second voltage line;

[1012] An orthographic projection of the first second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second control circuit on the substrate;

[1013] An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the second control circuit on the substrate;

[1014] An orthographic projection of the first first voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[1015] The orthographic projection of the first first voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[1016] The orthographic projection of the first second voltage line on the substrate at least partially overlaps with the orthographic projection of the plate of the capacitor included in the first energy storage circuit on the substrate;

[1017] An orthographic projection of the second second voltage line on the substrate at least partially overlaps with an orthographic projection of active patterns of at least part of transistors included in the first control circuit on the substrate;

[1018] The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of active patterns of at least part of the transistors included in the control signal generating circuit on the substrate;

[1019] An orthographic projectio...

Claims

1. A driving circuit, comprising a driving signal generating circuit, a control signal generating circuit and a control circuit; The drive signal generating circuit is electrically connected to the first clock signal line and the second clock signal line respectively, and is used to generate and output the n-th level drive signal through the n-th level drive signal output terminal under the control of the first clock signal provided by the first clock signal line and the second clock signal provided by the second clock signal line; n is a positive integer; The control signal generating circuit is electrically connected to the enable signal line and the control signal terminal respectively, and is used to output a control signal to the control signal terminal according to the enable signal provided by the enable signal line; The control circuit is electrically connected to the control signal terminal and the n-th level driving signal output terminal respectively, and is used to output a signal to the n-th level driving output terminal under the control of the control signal.

2. The driving circuit according to claim 1, wherein: Also includes an output inverting circuit; The output inversion circuit is electrically connected to the n-th level driving signal output terminal, and is used for inverting the n-th level driving signal to obtain and output the n-th level inverted driving signal through the n-th level inverted signal output terminal.

3. The driving circuit according to claim 1 or 2, wherein: The control circuit includes a first control circuit, a second control circuit and a first energy storage circuit; The first control circuit is electrically connected to the control signal terminal, the n-th drive signal output terminal, the first control voltage line, the second control voltage line and the control output terminal respectively, and is used to control the connection or disconnection between the control output terminal and the first control voltage line under the control of the control signal, control the connection or disconnection between the control output terminal and the first control voltage line under the control of the n-th level drive signal outputted by the n-th level drive signal terminal, and control the connection or disconnection between the control output terminal and the second control voltage line under the control of the n-th level drive signal and the control signal; The second control circuit is electrically connected to the control output terminal, the n-th level driving output terminal, the first voltage line and the second voltage line respectively, and is used to control the connection or disconnection between the n-th level driving output terminal and the first voltage line, and control the connection or disconnection between the n-th level driving output terminal and the second voltage line under the control of the potential of the control output terminal; The first energy storage circuit is electrically connected to the control output terminal and is used to maintain the potential of the control output terminal.

4. The driving circuit according to claim 3, wherein: The control circuit also includes a second energy storage circuit; The second energy storage circuit is electrically connected to the control signal terminal and is used to maintain the potential of the control signal terminal.

5. The driving circuit according to claim 2, wherein: The control signal generating circuit is also electrically connected to the n-1th level drive signal output terminal, the n-1th level inverted signal output terminal, the n-level drive signal output terminal and the n-level inverted signal output terminal, respectively, and is used to control the connection or disconnection between the enable signal line and the control signal terminal under the control of the n-1th level drive signal, the n-1th level inverted drive signal, the n-level drive signal and the n-level inverted drive signal.

6. The driving circuit according to claim 1, wherein: The control signal generating circuit is used to invert the enable signal to generate an inverted enable signal, and output the inverted enable signal through the control signal terminal.

7. The driving circuit according to claim 3, wherein: The first control circuit includes a first control transistor, a second control transistor, a third control transistor and a fourth control transistor; the second control circuit includes a fifth control transistor and a sixth control transistor; the first energy storage circuit includes a first capacitor; the first control voltage line is a first voltage line, and the second control voltage line is a second voltage line; The gate of the first control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the first control transistor is electrically connected to the first voltage line, and the second electrode of the first control transistor is electrically connected to the control output terminal; The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the second control transistor is electrically connected to the second voltage line; The gate of the third control transistor is electrically connected to the control signal terminal, the first electrode of the third control transistor is electrically connected to the first voltage line, and the second electrode of the third control transistor is electrically connected to the control output terminal; The gate of the fourth control transistor is electrically connected to the n-th stage drive signal output terminal, and the first electrode of the fourth control transistor is electrically connected to the control output terminal; The gate of the fifth control transistor is electrically connected to the control output terminal, the first electrode of the fifth control transistor is electrically connected to the first voltage line, and the second electrode of the fifth control transistor is electrically connected to the nth driving output terminal; The gate of the sixth control transistor is electrically connected to the control output terminal, the first electrode of the sixth control transistor is electrically connected to the nth driving output terminal, and the second electrode of the sixth control transistor is electrically connected to the second voltage line; A first end of the first capacitor is electrically connected to the control output end, and a second end of the first capacitor is electrically connected to the second voltage line.

8. The driving circuit according to claim 3, wherein: The first control circuit includes a first control transistor, a second control transistor, a third control transistor and a fourth control transistor; the second control circuit includes a fifth control transistor and a sixth control transistor; the first energy storage circuit includes a first capacitor; the first control voltage line is a second voltage line, and the second control voltage line is a first voltage line; The gate of the first control transistor is electrically connected to the control signal terminal, the first electrode of the first control transistor is electrically connected to the second electrode of the third control transistor, and the second electrode of the first control transistor is electrically connected to the control output terminal; The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the control output terminal, and the second electrode of the second control transistor is electrically connected to the second voltage line; The gate of the third control transistor is electrically connected to the nth stage drive signal output terminal, and the first electrode of the third control transistor is electrically connected to the first voltage line; The gate of the fourth control transistor is electrically connected to the n-th stage drive signal output terminal, the first electrode of the fourth control transistor is electrically connected to the control output terminal, and the second electrode of the fourth control transistor is electrically connected to the second voltage line; The gate of the fifth control transistor is electrically connected to the control output terminal, and the first electrode of the fifth control transistor is electrically connected to the control output terminal. is electrically connected to the first voltage line, and a second electrode of the fifth control transistor is electrically connected to the nth driving output terminal; The gate of the sixth control transistor is electrically connected to the control output terminal, the first electrode of the sixth control transistor is electrically connected to the nth driving output terminal, and the second electrode of the sixth control transistor is electrically connected to the second voltage line; A first end of the first capacitor is electrically connected to the control output end, and a second end of the first capacitor is electrically connected to the second voltage line.

9. The driving circuit according to claim 4, wherein: The second energy storage circuit includes a second capacitor; A first end of the second capacitor is electrically connected to the control signal end, and a second end of the second capacitor is electrically connected to the second voltage line.

10. The driving circuit according to claim 5, wherein: The control signal generating circuit includes a seventh control transistor, an eighth control transistor, a ninth control transistor and a tenth control transistor; The gate of the seventh control transistor is electrically connected to the n-1th stage driving signal output terminal, the first electrode of the seventh control transistor is electrically connected to the enable signal line, and the second electrode of the seventh control transistor is electrically connected to the first electrode of the tenth control transistor; The gate of the eighth control transistor is electrically connected to the n-1th stage inverting signal output terminal, the first electrode of the eighth control transistor is electrically connected to the enable signal line, and the second electrode of the eighth control transistor is electrically connected to the first electrode of the ninth control transistor; The gate of the ninth control transistor is electrically connected to the nth stage drive signal output terminal, the first electrode of the ninth control transistor is electrically connected to the first electrode of the tenth control transistor, and the second electrode of the ninth control transistor is electrically connected to the control signal terminal; The gate of the tenth control transistor is electrically connected to the nth stage inverting signal output terminal, and the second electrode of the tenth control transistor is electrically connected to the control signal terminal; The seventh control transistor and the tenth control transistor are both n-type transistors, and the eighth control transistor and the ninth control transistor are both p-type transistors; or, The seventh control transistor and the tenth control transistor are both p-type transistors, and the eighth control transistor and the ninth control transistor are both n-type transistors.

11. The driving circuit according to claim 6, wherein: The control signal generating circuit includes a seventh control transistor and an eighth control transistor; The gate of the seventh control transistor is electrically connected to the enable signal line, the first electrode of the seventh control transistor is electrically connected to the first voltage line, and the second electrode of the seventh control transistor is electrically connected to the control signal terminal; The gate of the eighth control transistor is electrically connected to the enable signal line, the first electrode of the eighth control transistor is electrically connected to the control signal terminal, and the second electrode of the eighth control transistor is electrically connected to the second voltage line; The seventh control transistor is a p-type transistor, and the eighth control transistor is an n-type transistor; or, the seventh control transistor is an n-type transistor, and the eighth control transistor is a p-type transistor.

12. The driving circuit according to claim 2, wherein: The output inverting circuit includes an eleventh control transistor and a twelfth control transistor; The gate of the eleventh control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the eleventh control transistor is electrically connected to the n-th stage inverting signal output terminal, and the second electrode of the eleventh control transistor is electrically connected to the second voltage line; The gate of the twelfth control transistor is electrically connected to the n-th stage driving signal output terminal, the first electrode of the twelfth control transistor is electrically connected to the first voltage line, and the second electrode of the twelfth control transistor is electrically connected to the n-th stage inverting signal output terminal.

13. The driving circuit according to claim 1, wherein: The drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; The first clock signal line includes a first first clock signal line, and the second clock signal line includes a first second clock signal line; The first node control circuit is electrically connected to the first node, the first first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the first first clock signal line, and to control the connection or disconnection between the first node and the first first clock signal line under the control of the potential of the second output node; The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the first second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the first second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the first second clock signal line and the second voltage signal provided by the second voltage line; The first output node control circuit is electrically connected to the first output node, the first node, the first second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the first second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the first second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node; The second output node control circuit is electrically connected to the first second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the first second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line; The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the second output node. Control the n-th stage driving signal output terminal to be connected to the second voltage line.

14. The driving circuit according to claim 13, wherein: The first node control circuit includes a first transistor, a second transistor and a third transistor; the second output node control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; The gate of the first transistor is electrically connected to the first first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor; The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the first electrode of the second transistor is electrically connected to the first first clock signal line, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; The gate of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the first node; The gate of the fourth transistor is electrically connected to the first first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal; The gate of the fifth transistor is electrically connected to the second voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node; The gate of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node; The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the first voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor; The second node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a third capacitor; The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the first second clock signal line, and the second electrode of the eighth transistor is electrically connected to the first intermediate node; The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node; The gate of the tenth transistor is electrically connected to the first first clock signal line, the first electrode of the tenth transistor is electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor; The gate of the eleventh transistor is electrically connected to the second voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node; The first electrode plate of the third capacitor is electrically connected to the second node, and the second electrode plate of the third capacitor is electrically connected to the first intermediate node; The first output node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fourth capacitor; The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node; The gate of the thirteenth transistor is electrically connected to the first second clock signal line, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node; The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the first electrode of the fourteenth transistor is electrically connected to the first voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first output node; The first electrode plate of the fourth capacitor is electrically connected to the first node, and the second electrode plate of the fourth capacitor is electrically connected to the second intermediate node; The potential maintaining circuit includes a fifth capacitor; The first plate of the fifth capacitor is electrically connected to the first output node, and the second plate of the fifth capacitor is electrically connected to the first voltage line; The output circuit includes a fifteenth transistor and a sixteenth transistor; The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage driving signal output terminal; A gate of the sixteenth transistor is electrically connected to the second output node, a first electrode of the sixteenth transistor is electrically connected to the nth stage driving signal output terminal, and a second electrode of the sixteenth transistor is electrically connected to the second voltage line.

15. The driving circuit according to claim 3, wherein: The drive signal generating circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, a second output node control circuit, a potential maintaining circuit and an output circuit; The first clock signal line includes a second first clock signal line, and the second clock signal line includes a second second clock signal line; The first node control circuit is electrically connected to the first node, the second first clock signal line, the second voltage line, and the second output node, respectively, and is used to control the connection between the first node and the second voltage line under the control of the first clock signal provided by the second first clock signal line, and to control the connection or disconnection between the first node and the second first clock signal line under the control of the potential of the second output node; The second node control circuit is electrically connected to the first node, the first intermediate node, the first voltage line, the second second clock signal line, the second node, the input terminal and the second voltage line respectively, and is used to control the connection between the first intermediate node and the first voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second second clock signal line under the control of the potential of the second node, and control the potential of the second node according to the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the second clock signal provided by the second second clock signal line and the second voltage signal provided by the second voltage line; The first output node control circuit is electrically connected to the first output node, the first node, the second second clock signal line, the second intermediate node, the second output node and the first voltage line respectively, and is used to control the second intermediate node to be connected to the second second clock signal line under the control of the potential of the first node, control the potential of the second intermediate node according to the potential of the first node, control the second intermediate node to be connected to the first output node under the control of the second clock signal provided by the second second clock signal line, and control the first output node to be connected to the first voltage line under the control of the potential of the second output node; The second output node control circuit is electrically connected to the second second clock signal line, the input terminal, the control voltage line, the first voltage line, the second node, and the second output node, respectively, and is used to control the second output node to be connected to the input terminal under the control of the second clock signal provided by the second second clock signal line, control the potential of the second output node according to the potential of the second node, and control the second output node to be connected to the first voltage line under the control of the control voltage provided by the control voltage line; The potential maintaining circuit is electrically connected to the first output node, and is used to maintain the potential of the first output node; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second voltage line and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the second voltage line under the control of the potential of the second output node.

16. The driving circuit according to claim 15, wherein: The first node control circuit includes a first transistor, a second transistor and a third transistor; the second output node control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; The gate of the first transistor is electrically connected to the second first clock signal line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor; The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the first electrode of the second transistor is electrically connected to the second first clock signal line, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; The gate of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the first node; The gate of the fourth transistor is electrically connected to the second first clock signal line, and the first electrode of the fourth transistor is electrically connected to the input terminal; The gate of the fifth transistor is electrically connected to the second voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node; The gate of the sixth transistor and the first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node; The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the first voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor; The second node control circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a third capacitor; The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the second second clock signal line, and the second electrode of the eighth transistor is electrically connected to the first intermediate node; The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the first voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node; The gate of the tenth transistor is electrically connected to the second first clock signal line, and the first The first electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor; The gate of the eleventh transistor is electrically connected to the second voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node; The first electrode plate of the third capacitor is electrically connected to the second node, and the second electrode plate of the third capacitor is electrically connected to the first intermediate node; The first output node control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fourth capacitor; The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second second clock signal line, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node; The gate of the thirteenth transistor is electrically connected to the second second clock signal line, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node; The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the first electrode of the fourteenth transistor is electrically connected to the first voltage line, and the second electrode of the fourteenth transistor is electrically connected to the first output node; The first electrode plate of the fourth capacitor is electrically connected to the first node, and the second electrode plate of the fourth capacitor is electrically connected to the second intermediate node; The potential maintaining circuit includes a fifth capacitor; The first plate of the fifth capacitor is electrically connected to the first output node, and the second plate of the fifth capacitor is electrically connected to the first voltage line; The output circuit includes a fifteenth transistor and a sixteenth transistor; The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the first voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage driving signal output terminal; A gate of the sixteenth transistor is electrically connected to the second output node, a first electrode of the sixteenth transistor is electrically connected to the nth stage driving signal output terminal, and a second electrode of the sixteenth transistor is electrically connected to the second voltage line.

17. The driving circuit according to claim 3, wherein: The drive signal generating circuit includes a first output node control circuit, a second output node control circuit, a third energy storage circuit and an output circuit; the first clock signal line includes a third first clock signal line, and the second clock signal line includes a third second clock signal line; The first output node control circuit is electrically connected to the third first clock signal line, the second voltage line and the second output node respectively, and is used to control the first output node to be connected to the second voltage line under the control of the first clock signal provided by the third first clock signal line, and to control the first output node to be connected to the third first clock signal line under the control of the potential of the second output node, and to maintain the potential of the first output node; The second output node control circuit is electrically connected to the second output node, the third first clock signal line, the input terminal, the third second clock signal line, the first output node and the first voltage line respectively, and is used to control the second output node to be connected to the input terminal under the control of the first clock signal, and to control the potential of the first output node to be and the second clock signal provided by the third second clock signal line, controlling the second output node to be connected to the first voltage line; The first end of the third energy storage circuit is electrically connected to the second output node, the second end of the third energy storage circuit is electrically connected to the n-th stage drive signal output terminal, and the third energy storage circuit is used to store electric energy; The output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal and the n-th level drive signal output terminal, respectively, and is used to control the connection between the n-th level drive signal output terminal and the first voltage line under the control of the potential of the first output node, and to control the connection between the n-th level drive signal output terminal and the third second clock signal line under the control of the potential of the second output node.

18. The driving circuit according to claim 17, wherein: The first output node control circuit includes a seventeenth transistor, an eighteenth transistor and a sixth capacitor; The gate of the seventeenth transistor is electrically connected to the third first clock signal line, the first electrode of the seventeenth transistor is electrically connected to the second voltage line, and the second electrode of the seventeenth transistor is electrically connected to the first output node; A gate of the eighteenth transistor is electrically connected to the second output node, a first electrode of the eighteenth transistor is electrically connected to the third first clock signal line, and a second electrode of the eighteenth transistor is electrically connected to the first output node; The first plate of the sixth capacitor is electrically connected to the first output node, and the second plate of the sixth capacitor is electrically connected to the first voltage line; The second output node control circuit includes a nineteenth transistor, a twentieth transistor, and a twenty-first transistor; the third energy storage circuit includes a seventh capacitor; The gate of the nineteenth transistor is electrically connected to the third first clock signal line, the first electrode of the nineteenth transistor is electrically connected to the input terminal, and the second electrode of the nineteenth transistor is electrically connected to the second output node; A gate of the 20th transistor is electrically connected to the first output node, a first electrode of the 20th transistor is electrically connected to the first voltage line, and a second electrode of the 20th transistor is electrically connected to a first electrode of the 21st transistor; A gate of the twenty-first transistor is electrically connected to the third second clock signal line, and a second electrode of the twenty-first transistor is electrically connected to the second output node; The first electrode plate of the seventh capacitor is electrically connected to the second output node, and the second electrode plate of the seventh capacitor is electrically connected to the n-th level driving signal output terminal; The output circuit includes a twenty-second transistor and a twenty-third transistor; A gate of the 22nd transistor is electrically connected to the first output node, a first electrode of the 22nd transistor is electrically connected to the first voltage line, and a second electrode of the 22nd transistor is electrically connected to the nth stage driving signal output terminal; a gate of the twenty-third transistor is electrically connected to the second output node, a first electrode of the twenty-third transistor is electrically connected to the n-th stage driving signal output terminal, and a second electrode of the twenty-third transistor is electrically connected to the third second clock signal line; The driving circuit further includes a twenty-fourth transistor; The second electrode of the 21st transistor is electrically connected to the second output node through the 24th transistor; the gate of the 24th transistor is electrically connected to the second voltage line, the first electrode of the 24th transistor is electrically connected to the second electrode of the 21st transistor, and the second electrode of the 24th transistor is electrically connected to the second output node.

19. A display device comprising the display substrate according to any one of claims 19 to 48.

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