Optical module, network device and data transmission method

Abstract

The present application belongs to the field of optical communications, and provides an optical module, a network device and a data transmission method. The optical module is provided with a FlexE interface, by utilizing the characteristics of FlexE channelization, a FlexE code block stream from a system side is converted into a plurality of Ethernet code block streams, electro-optical conversion is performed on the Ethernet code block streams to generate optical signals, and then the optical signals is sent out, so that an interface of the optical module docked with a network device is mapped into a plurality of optical interfaces, so that the optical interface density is improved, and the breakout of a high-density optical interface can be realized.

Description

Optical module, network device and data transmission method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 13, 2023, with application number 202311182736.0 and invention name “Optical module, network equipment and data transmission method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of optical communications, and in particular to an optical module, a network device, and a data transmission method. Background Art

[0003] In current hash optical modules, the number of channels (transmission channels for optical signals) provided by the line-side interface (optical interface) is the same as the number of channels (transmission channels for electrical signals) provided by the system-side interface (electrical interface). This results in insufficient density of the line-side interface (optical interface), limiting the interface capabilities of network devices.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide an optical module, a network device, and a data transmission method, which can improve the density of optical interfaces.

[0006] In a first aspect, an optical module is provided, comprising a flexible Ethernet (FlexE) interface, a processing circuit, an optoelectronic conversion device, and multiple optical interfaces; the FlexE interface is used to receive a first FlexE code block stream from a network device through a FlexE channel, and the FlexE interface is communicatively connected to the network device through the FlexE channel; the processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream; the optoelectronic conversion device is used to perform electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; and the multiple optical interfaces are used to send the multiple first optical signals to an optical fiber.

[0007] The FlexE interface may also be referred to as a system-side interface. The optical interface may also be referred to as a line-side interface. The optical interface may be, for example, an Ethernet interface.

[0008] First, an optical module with a FlexE interface is provided. By utilizing the FlexE channelization feature, the FlexE code block stream from the system side is converted into a multi-channel Ethernet code block stream, which is then sent out after electro-optical conversion to generate an optical signal. This allows the optical module to connect to a network device (FlexE interface) and map it to multiple optical interfaces, thereby improving the optical interface density and helping to achieve high-density optical interface hashing.

[0009] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the FlexE shim circuit is configured to obtain multiple first FlexE client code block streams based on the first FlexE code block stream, where the multiple first FlexE client code block streams include code blocks in a FlexE encoding format; and the transcoding circuit is configured to convert the encoding format of the code blocks in the multiple first FlexE client code block streams from a FlexE encoding format to an Ethernet encoding format to obtain the multiple first Ethernet code block streams.

[0010] Considering that in some scenarios, code blocks in the FlexE coding format and code blocks in the Ethernet coding format have different coding formats, the code block coding format is converted from the FlexE coding format to the Ethernet coding format using a transcoding circuit. This makes the optical interface compatible with a standard Ethernet interface (such as an Ethernet interface that complies with the IEEE 802.3 standard). This reduces the complexity of decoding the code blocks on the remote device connected to the optical module via optical fiber, and reduces the risk of decoding failure when the remote device decodes the code block stream according to the Ethernet coding format after it is transmitted to the remote device.

[0011] In some embodiments, the FlexE shim circuit is configured to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, where the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0012] By leveraging the flexible and configurable features of the FlexE shim, the conversion between the FlexE code block stream and the FlexE client code block stream is implemented based on the timeslot configuration information. This makes the number of optical interfaces and the transmission rate of the optical interfaces configurable, thereby improving flexibility.

[0013] In some embodiments, the multiple first Ethernet block streams include a first Ethernet block stream at a first transmission rate and a first Ethernet block stream at a second transmission rate, the multiple first FlexE client block streams include a first FlexE client block stream at the first transmission rate and a first FlexE client block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client block stream at the first transmission rate occupies a first number of time slots and the first FlexE client block stream at the second transmission rate occupies a second number of time slots, the second number being different from the first number.

[0014] By leveraging the time division multiplexing (TDM) characteristics of FlexE, the code blocks in the FlexE code block stream are mapped to different numbers of time slots, thereby supporting the output of multiple FlexE client code block streams at different rates. This allows a single optical module to simultaneously hash interfaces at multiple rates, helping to reduce the use of different rate interface boards and reduce costs.

[0015] In some embodiments, a transmission rate of each of the multiple first Ethernet block flows is lower than a transmission rate of the first FlexE block flow.

[0016] By converting the higher-rate FlexE code block stream into multiple lower-rate Ethernet code block streams, a hashed optical module is implemented, which helps the optical module connect to multiple remote devices.

[0017] In some embodiments, the multiple optical interfaces are further used to receive multiple second optical signals from the optical fiber, where the multiple second optical signals include multiple second Ethernet code block streams; the optoelectronic conversion device is further used to perform optoelectronic conversion on the multiple second optical signals to obtain multiple electrical signals, where the multiple electrical signals include multiple second Ethernet code block streams; the processing circuit is further used to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; and the FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

[0018] By leveraging the FlexE channelization feature, multiple Ethernet code block streams from the line side are converted into FlexE code block streams, which are then converted into electrical signals after optical-to-electrical conversion and sent out. This allows multiple optical interfaces connected to multiple remote devices to be mapped into a single interface connected to the optical module and network equipment, thus meeting the needs of multiple remote devices to communicate with the network equipment through optical modules.

[0019] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the transcoding circuit is configured to convert the encoding format of code blocks in the multiple second Ethernet code block streams from an Ethernet encoding format to a FlexE encoding format to obtain multiple second FlexE client code block streams; and the FlexE shim circuit is configured to obtain a second FlexE code block stream based on the multiple second FlexE client code block streams.

[0020] Considering that in some scenarios, code blocks in the FlexE coding format and code blocks in the Ethernet coding format have different coding formats, the coding format of the code blocks is converted from the Ethernet coding format to the FlexE coding format using a transcoding circuit, making the optical interface compatible with the standard Ethernet interface (such as an Ethernet interface that complies with the IEEE 802.3 standard), reducing the complexity of network equipment in decoding the code blocks.

[0021] In some embodiments, the optical module includes an interface chip, and the FlexE interface and the processing circuit are both provided on the interface chip.

[0022] By integrating the FlexE interface and processing circuit on the same interface chip, the layout of the optical module is simplified and the overall size of the optical module is reduced.

[0023] In a second aspect, an optical module is provided, comprising: a housing, provided with an electrical interface and multiple optical interfaces, the electrical interface being used to connect to a network device outside the optical module, and the multiple optical interfaces being used to connect to optical fibers outside the optical module; an interface chip being disposed in the housing, the interface chip comprising a Flexible Ethernet FlexE interface, a processing circuit, and multiple Ethernet interfaces, the FlexE interface being opposite to the electrical interface, the processing circuit being disposed between the FlexE interface and the multiple Ethernet interfaces, the processing circuit being used to convert a FlexE code block stream received by the FlexE interface into a multiple Ethernet code block stream and output the multiple Ethernet code block streams to the multiple Ethernet interfaces, the multiple Ethernet interfaces corresponding one-to-one to the multiple optical interfaces; an optoelectronic conversion device being disposed in the housing, one end of the optoelectronic conversion device being electrically connected to the multiple Ethernet interfaces of the interface chip, and the other end of the optoelectronic conversion device being opposite to the multiple optical interfaces.

[0024] The second aspect provides an optical module with a FlexE interface. Since one FlexE interface is mapped to multiple Ethernet interfaces, and multiple Ethernet interfaces are mapped to multiple optical interfaces, the optical interface density is improved, which helps to achieve high-density optical interface hashing.

[0025] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the FlexE shim circuit is configured to obtain multiple first FlexE client code block streams based on the first FlexE code block stream, where the multiple first FlexE client code block streams include code blocks in a FlexE encoding format; and the transcoding circuit is configured to convert the encoding format of the code blocks in the multiple first FlexE client code block streams from a FlexE encoding format to an Ethernet encoding format to obtain the multiple first Ethernet code block streams.

[0026] In some embodiments, the FlexE shim circuit is configured to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, where the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0027] In some embodiments, the multiple first Ethernet block streams include a first Ethernet block stream at a first transmission rate and a first Ethernet block stream at a second transmission rate, the multiple first FlexE client block streams include a first FlexE client block stream at the first transmission rate and a first FlexE client block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client block stream at the first transmission rate occupies a first number of time slots and the first FlexE client block stream at the second transmission rate occupies a second number of time slots, the second number being different from the first number.

[0028] In some embodiments, a transmission rate of each of the multiple first Ethernet block flows is lower than a transmission rate of the first FlexE block flow.

[0029] In some embodiments, the multiple optical interfaces are further used to receive multiple second optical signals from the optical fiber, where the multiple second optical signals include multiple second Ethernet code block streams; the optoelectronic conversion device is further used to perform optoelectronic conversion on the multiple second optical signals to obtain multiple electrical signals, where the multiple electrical signals include multiple second Ethernet code block streams; the processing circuit is further used to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; and the FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

[0030] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the transcoding circuit is configured to convert the encoding format of code blocks in the multiple second Ethernet code block streams from an Ethernet encoding format to a FlexE encoding format to obtain multiple second FlexE client code block streams; and the FlexE shim circuit is configured to obtain a second FlexE code block stream based on the multiple second FlexE client code block streams.

[0031] In some embodiments, the optical module includes an interface chip, and the FlexE interface and the processing circuit are both provided on the interface chip.

[0032] According to a third aspect, a network device is provided, including a processor, a first Flexible Ethernet FlexE interface, and an optical module. The optical module includes a second FlexE interface, a processing circuit, an optoelectronic conversion device, and multiple optical interfaces. The first FlexE interface is communicatively connected to the second FlexE interface via a FlexE channel. The processor is used to generate a first FlexE code block stream. The first FlexE interface is used to send the first FlexE code block stream to the second FlexE interface via the FlexE channel. The processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream. The optoelectronic conversion device is used to perform electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals. The multiple optical interfaces are used to send the multiple first optical signals to optical fibers.

[0033] In the network device provided by the third aspect, since an optical module with a FlexE interface is provided, the FlexE code block stream from the system side is converted into a multi-channel Ethernet code block stream by utilizing the FlexE channelization characteristics, and then an optical signal is generated after electro-optical conversion and sent out, so that an interface (FlexE interface) connecting the optical module to the network device is mapped into multiple optical interfaces, thereby improving the optical interface density and helping to achieve hashing of high-density optical interfaces.

[0034] In addition, network devices can be connected to multiple remote devices through optical modules, improving the interface capabilities and scalability of network devices and helping to support more complex network topologies.

[0035] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the FlexE shim circuit is configured to obtain multiple first FlexE client code block streams based on the first FlexE code block stream, where the multiple first FlexE client code block streams include code blocks in a FlexE encoding format; and the transcoding circuit is configured to convert the encoding format of the code blocks in the multiple first FlexE client code block streams from a FlexE encoding format to an Ethernet encoding format to obtain the multiple first Ethernet code block streams.

[0036] In some embodiments, the FlexE shim circuit is configured to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, where the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0037] In some embodiments, the multiple first Ethernet block streams include a first Ethernet block stream at a first transmission rate and a first Ethernet block stream at a second transmission rate, the multiple first FlexE client block streams include a first FlexE client block stream at the first transmission rate and a first FlexE client block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client block stream at the first transmission rate occupies a first number of time slots and the first FlexE client block stream at the second transmission rate occupies a second number of time slots, the second number being different from the first number.

[0038] In some embodiments, a transmission rate of each of the multiple first Ethernet block flows is lower than a transmission rate of the first FlexE block flow.

[0039] In some embodiments, the multiple optical interfaces are further used to receive multiple second optical signals from the optical fiber, where the multiple second optical signals include multiple second Ethernet code block streams; the optoelectronic conversion device is further used to perform optoelectronic conversion on the multiple second optical signals to obtain multiple electrical signals, where the multiple electrical signals include multiple second Ethernet code block streams; the processing circuit is further used to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; and the second FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

[0040] In some embodiments, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the transcoding circuit is configured to convert the encoding format of code blocks in the multiple second Ethernet code block streams from an Ethernet encoding format to a FlexE encoding format to obtain multiple second FlexE client code block streams; and the FlexE shim circuit is configured to obtain a second FlexE code block stream based on the multiple second FlexE client code block streams.

[0041] In some embodiments, the optical module includes an interface chip, and the second FlexE interface and the processing circuit are both provided on the interface chip.

[0042] In a fourth aspect, a data transmission method is provided, which is applied to an optical module, including: receiving a first FlexE code block stream from a first network device through a Flexible Ethernet FlexE channel, and the optical module and the first network device are communicatively connected through the FlexE channel; obtaining multiple first Ethernet code block streams based on the first FlexE code block stream; performing electro-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; and sending the multiple first optical signals to a second network device through optical fibers.

[0043] In some embodiments, obtaining multiple first Ethernet code block streams based on the first FlexE code block stream includes: obtaining multiple first FlexE client code block streams based on the first FlexE code block stream, where the multiple first FlexE client code block streams include code blocks in a FlexE coding format; and converting the coding format of the code blocks in the multiple first FlexE client code block streams from the FlexE coding format to an Ethernet coding format to obtain the multiple first Ethernet code block streams.

[0044] In some embodiments, obtaining multiple first FlexE client code block streams based on the first FlexE code block stream includes: performing time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain the multiple first FlexE client code block streams, where the time slot configuration information indicates at least one of a number of time slots occupied by the multiple first FlexE client code block streams or time slot positions occupied by the multiple first FlexE client code block streams.

[0045] In some embodiments, the multiple first FlexE client code block streams include a first FlexE client code block stream at a first transmission rate and a first FlexE client code block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client code block stream at the first transmission rate occupies a first number of time slots and the first FlexE client code block stream at the second transmission rate occupies a second number of time slots, the second number being different from the first number.

[0046] In some embodiments, a transmission rate of each first Ethernet block stream in the multiple first Ethernet block streams is less than a transmission rate of the first FlexE block stream.

[0047] In some embodiments, the method further includes: receiving multiple second optical signals from a second network device, the multiple second optical signals including multiple second Ethernet block streams; performing optical-to-electrical conversion on the multiple second optical signals to obtain multiple electrical signals, the multiple electrical signals including multiple second Ethernet block streams; obtaining a second FlexE block stream based on the multiple second Ethernet block streams; and sending the second FlexE block stream to the first network device through a FlexE channel.

[0048] In some embodiments, obtaining a second FlexE code block stream based on multiple second Ethernet code block streams includes: converting the coding format of code blocks in the multiple second Ethernet code block streams from an Ethernet coding format to a FlexE coding format to obtain multiple second FlexE client code block streams; and obtaining a second FlexE code block stream based on the multiple second FlexE client code block streams. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic diagram of a panel of a single board using a QSFP28 10×10G hashed optical module provided in an embodiment of the present application;

[0050] FIG2 is a schematic diagram of a panel of a single board using an SFP+10×10G hashed optical module provided in an embodiment of the present application;

[0051] FIG3 is a schematic diagram of the architecture of a network device provided in an embodiment of the present application;

[0052] FIG4 is a schematic diagram of an internal structure of the processing circuit in FIG3 ;

[0053] FIG5 is a schematic diagram of a FlexE encoding format provided in an embodiment of the present application;

[0054] FIG6 is a schematic diagram of an Ethernet encoding format provided in an embodiment of the present application;

[0055] FIG7 is a schematic diagram of the architecture of another network device provided in an embodiment of the present application;

[0056] FIG8 is a schematic diagram of the architecture of the interface chip inside the optical module in FIG7 ;

[0057] FIG9 is a schematic diagram of the architecture of another network device provided in an embodiment of the present application;

[0058] FIG10 is a schematic diagram of the structure of the interface chip inside the optical module in FIG9;

[0059] FIG11 is a schematic diagram of the architecture of another network device provided in an embodiment of the present application;

[0060] FIG12 is a flowchart of a data transmission method provided in an embodiment of the present application;

[0061] FIG13 is a flowchart of a data transmission method provided in an embodiment of the present application;

[0062] FIG14 is a schematic diagram of the structure of the interface chip inside the optical module in FIG11 . DETAILED DESCRIPTION

[0063] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0064] The following is an example of an application scenario of the embodiment of the present application.

[0065] The embodiments of the present application can be applied to a scenario in which a network device communicates with other network devices based on a high-density hashed optical module. The network device can be a network device such as a switch, a router, a firewall, etc. The network device can also be a component of the network device, such as a single board on the network device (including a main control board, an interface board or a line card, etc.). The network device can also be a functional module on the network device, or a media access control (MAC) chip, a network processor (NP) or a central processing unit (CPU) that supports flexible Ethernet (FlexE). The network device can also be a computing device such as a server or a terminal. The embodiments of the present application mainly take the scenario in which the network device is a single board, such as a single board communicating with a high-density hashed optical module provided on the single board, as an example.

[0066] An optical module is an electronic device used to implement photoelectric conversion and / or electro-optical conversion in fiber-optic communications. It primarily consists of an electrical interface, a photoelectric conversion device, functional circuitry, and an optical interface.

[0067] The electrical interface is connected to the network equipment outside the optical module. The electrical interface is used to transmit electrical signals and can also be called a system-side interface or an electrical signal interface. An electrical interface is, for example, a serializer / deserializer (SerDes) interface. The electrical interface includes one or more pairs of serialized channels (lanes), each pair of lanes includes a receive channel and a transmit channel, and each pair of lanes includes a SerDes for transmitting and a SerDes for receiving.

[0068] An optical interface connects to an optical fiber. It transmits optical signals. It can also be called the line-side interface or optical signal interface of an optical module. An optical interface can be an Ethernet interface, and the optical signals it transmits carry a code block stream (hereafter referred to as an Ethernet code block stream) that complies with Ethernet protocol standards (e.g., IEEE 802.3).

[0069] A hash optical module is an optical module whose main function is to hash a higher-speed electrical interface into multiple lower-speed optical interfaces. For example, a hash optical module converts a set of higher-speed electrical signals received from an electrical interface into multiple lower-speed optical signals, and sends multiple lower-speed optical signals through the optical interface. Since the hash optical module provides multiple optical interfaces, or supports the output of multiple optical signals, it helps to improve the interface capabilities to a certain extent. The optical interface of the hash optical module is usually an optical interface provided by a clamping multi-fiber push-on (MPO) connector. The MPO connector uses a multi-core optical fiber structure. For example, an MPO connector has 12 optical fiber cores, thereby supporting the transmission and reception of 12 pairs of optical signals.

[0070] Currently, sparse optical modules are typically straight-through. That is, the number of channels for transmitting optical signals between the sparse optical module and the optical fiber (hereinafter referred to as line-side channels) is the same as the number of channels for transmitting electrical signals between the sparse optical module and the network equipment (hereinafter referred to as system-side channels). For example, the number of line-side channels of a sparse optical module is the same as the number of SerDes lanes. In other words, the number of optical signal paths transmitted by the sparse optical module is the same as the number of electrical signal paths, and there is a one-to-one correspondence between the optical and electrical signals.

[0071] However, when using straight-through, hashed optical modules, the number of line-side channels is the same as the number of system-side channels, resulting in a low optical interface density. This reduces the number of remote network devices supported by the hashed optical modules, impacting the interface capabilities of these devices and limiting their application. Furthermore, the transmission rate of the hashed optical module's system-side channels must be reduced to that of the line-side channels, resulting in insufficient utilization of system-side interface bandwidth resources and a loss of bandwidth.

[0072] For example, typical hashed optical modules include 40G QSFP+SR4 optical modules or 100G QSFP28 SR4 optical modules. Both 40G QSFP+SR4 optical modules and 100G QSFP28 SR4 optical modules have four pairs of serdes lanes, with the number of system-side channels and the number of line-side channels both being four. The basic principle of the 40G QSFP+SR4 optical module and the 100G QSFP28 SR4 optical module is to drive the four received electrical signals and then convert them into four parallel optical signals through optoelectronic conversion devices. The method for sending electrical signals is similar. The 40G QSFP+SR4 optical module supports hashing out four 10G Ethernet interfaces, that is, the 40G QSFP+SR4 optical module supports the transmission of four optical signals, each of which carries a 10G Ethernet code block stream. The 100G QSFP28 SR4 optical module supports hashing out four 25G Ethernet interfaces. The 100G QSFP28 SR4 optical module can transmit four optical signals, each carrying a 25G Ethernet block stream.

[0073] In order to improve the density of the optical interface of the hash optical module, in one implementation, a multi-link gearbox (MLG) chip is added inside the hash optical module. The main function of the MLG chip is signal rate conversion and channel mapping. In one example, the MLG chip uses bits as units for data distribution, such as assigning a corresponding output channel to each bit in the data stream, and sending the data carried by the bit through the output channel corresponding to the bit. For example, the optical module containing the MLG chip is a 100G SR10 optical module, and the electrical interface of the 100GSR10 optical module is an interface with a rate of 100G. The electrical interface supports the transmission of 4 Ethernet code block streams with a rate of 25G, and the optical interface supports the transmission of 10 Ethernet code block streams with a rate of 10G. When the MLG chip in a 100G SR10 optical module receives a 100G data stream from the electrical interface, it sends the first bit of the data stream to the first output channel, the second bit to the second output channel, and so on. This effectively divides the entire 100G data stream into 10 parts and distributes each bit in a cyclic manner across the 10 output channels. For MLG implementation details, refer to the OIF-MLG-03.0 standard.

[0074] However, if adding an MLG chip to the distributed optical module to increase optical interface density is adopted, the chip on the board that interfaces with the optical module must support the MLG function. If the chip on the board that interfaces with the optical module does not support the MLG function, since the MLG chip does not support MAC ports, it must rely on an external MAC chip or the MAC circuit within the NP to convert the data into 10 10G MAC layer data streams. This requires adding a separate MLG chip and MAC chip on the board, which increases the cost of the board and puts a lot of pressure on the PCB layout.

[0075] Based on this, an embodiment of the present application provides a FlexE-based hashed optical module. The hashed optical module includes a FlexE interface. The interface chip in the hashed optical module supports FlexE. The interface chip in the hashed optical module utilizes the FlexE channelization feature to map the Ethernet interface to the FlexE time slot, or to map the FlexE time slot to the Ethernet interface, thereby achieving a greater number of line-side channels of the hashed optical module than the number of system-side channels, which helps to achieve high-density fan-out of optical interfaces such as 10G, 25G, or 50G, and improve the density of the optical interface of the optical module.

[0076] In one possible implementation, the interface chip distributes the received FlexE code block stream to multiple FlexE sub-channels. For example, the chip on the single board generates a FlexE code block stream, which includes a series of 64B / 66B code blocks with a FlexE encoding format. The chip on the single board sends the FlexE code block stream to the hash optical module. After the interface chip in the hash optical module receives the FlexE code block stream, the interface chip uses 64B / 66B code blocks as units to distribute data. For example, the interface chip distributes each 64B / 66B code block in the FlexE code block stream to multiple FlexE sub-channels in sequence, generating multiple FlexE client code block streams. Each FlexE client code block stream includes some 64B / 66B code blocks in the FlexE code block stream. After the interface chip converts the encoding format of the code blocks in the multiple FlexE client code block streams into the Ethernet encoding format, it generates multiple Ethernet code block streams. After optical-to-electrical conversion, multiple Ethernet code block streams generate multiple optical signals. These optical signals are sent to the optical fiber outside the optical module through the optical interface of the hash optical module.

[0077] The FlexE channel is equivalent to the system-side channel of the interface chip in the optical module. The FlexE channel can be located between the optical module and the MAC chip on the single board that is connected to the optical module. One end of the FlexE channel can be the FlexE group interface of the interface chip, and the other end of the FlexE channel can be the FlexE group interface of the MAC chip on the single board that is connected to the interface chip. The FlexE channel can be used to transmit the FlexE code block stream between the interface chip and the single board. The transmission rate of the FlexE channel is greater than the transmission rate of the FlexE sub-channel. The 64B / 66B code block means that the code block includes 66 bits, the first two bits of the 66 bits are synchronization bits, and the last 64 bits are data bits.

[0078] A FlexE subchannel is equivalent to the line-side channel of an interface chip. A FlexE subchannel can be implemented using a FlexE shim within the interface chip. A FlexE subchannel can be located between the FlexE shim circuit within the interface chip and the remote device to which the optical interface of the optical module is connected via optical fiber. One end of a FlexE subchannel can be the FlexE shim circuit within the interface chip, and the other end can be the remote device to which the optical interface of the optical module is connected. The number of FlexE subchannels is greater than the number of FlexE channels. Each FlexE subchannel carries one FlexE client code block stream.

[0079] Because the interface chip distributes the code blocks in the FlexE code block stream to the corresponding FlexE sub-channel, it is possible to generate multiple lower-rate code block streams (FlexE client code block streams) based on a higher-rate code block stream (FlexE code block stream) input from the electrical interface, and output multiple lower-rate code block streams (FlexE client code block streams) through the optical interface, so that the number of line-side channels is greater than the number of system-side channels, thereby improving the optical interface density and helping to support the hashing of high-density optical interfaces. In addition, the interface chip implements a similar function to the MLG chip, and does not require the chip on the single board that interfaces with the hashing optical module to support MLG, thereby reducing dependence on the MLG chip to a certain extent. Since the MLG chip does not need to be deployed on the single board, the problems of complex PCB layout, power consumption and cost on the single board caused by the deployment of the MLG chip are reduced, making the implementation solution simpler, with lower cost and power consumption.

[0080] For example, if the transmission rate of a FlexE channel is 100G, the FlexE shim circuit in the interface chip cyclically distributes the FlexE code block stream received from the FlexE channel to two FlexE sub-channels, making the transmission rate of each FlexE sub-channel 50G, or generating two FlexE client code block streams with a rate of 50G. In one example, the interface chip distributes the first code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the second code block in the code block stream received from the FlexE channel to the second FlexE sub-channel, the third code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the fourth code block in the code block stream received from the FlexE channel to the second FlexE sub-channel, and so on. The interface chip converts the received FlexE code block stream at a rate of 100G into two FlexE client code block streams at a rate of 50G.

[0081] For example, if the transmission rate of a FlexE channel is 100G, the FlexE shim circuit in the interface chip will cyclically distribute the code block stream received from the FlexE channel to the four FlexE sub-channels in sequence, making the transmission rate of each FlexE sub-channel 25G, or generating four FlexE client code block streams with a rate of 25G. In an example, the interface chip distributes the first code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the interface chip distributes the second code block received from the FlexE channel to the second FlexE sub-channel, the third code block received from the FlexE channel to the third FlexE sub-channel, the fourth code block received from the FlexE channel to the fourth FlexE sub-channel, the fifth code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the interface chip distributes the sixth code block in the code block stream received from the FlexE channel to the second FlexE sub-channel, and so on. The interface chip converts a received FlexE code block stream with a rate of 100G into four FlexE client code block streams with a rate of 25G.

[0082] For example, if the transmission rate of the FlexE channel is 100G, the FlexE shim circuit in the interface chip will cyclically distribute the code block stream received from the FlexE channel to 10 FlexE sub-channels in sequence, so that the transmission rate of each FlexE sub-channel is 10G, or in other words, 10 FlexE client code block streams with a rate of 10G are generated. In one example, the interface chip distributes the first code block in the code block stream received from the FlexE channel to the first FlexE sub-channel, the interface chip distributes the second code block received from the FlexE channel to the second FlexE sub-channel, the third code block received from the FlexE channel to the third FlexE sub-channel, the fourth code block received from the FlexE channel to the fourth FlexE sub-channel, the fifth code block in the code block stream received from the FlexE channel to the fifth FlexE sub-channel, the interface chip distributes the sixth code block in the code block stream received from the FlexE channel to the sixth FlexE sub-channel, and the interface chip distributes the seventh code block received from the FlexE channel to the sixth FlexE sub-channel. The first code block is distributed to the seventh FlexE sub-channel, the eighth code block received from the FlexE channel is distributed to the eighth FlexE sub-channel, the ninth code block received from the FlexE channel is distributed to the ninth FlexE sub-channel, the tenth code block in the code block stream received from the FlexE channel is distributed to the tenth FlexE sub-channel, the eleventh code block in the code block stream received from the FlexE channel is distributed to the first FlexE sub-channel, and the twelfth code block in the code block stream received from the FlexE channel is distributed to the second FlexE sub-channel. And so on. In this way, one FlexE code block stream with a rate of 100G received by the electrical interface of the optical module is converted into ten FlexE client code block streams with a rate of 10G.

[0083] FlexE sub-channels can be further divided by dividing FlexE channels based on the time division multiplexing (TDM) mechanism. In one example, a period of time is divided into multiple time slots, each FlexE sub-channel occupies one or more time slots, and different FlexE sub-channels occupy different time slots. The interface chip can send each code block received from the FlexE channel within a period of time to the optical port through the corresponding time slot. Exemplarily, the transmission rate of the FlexE channel is 100G, and a period of time is divided into 20 time slots. The bandwidth corresponding to one time slot is 5G. The FlexE shim circuit of the interface chip can allocate the bandwidth occupied by a FlexE client code block stream at a granularity of 1 or more times of 5G. The FlexE shim circuit inside the interface chip groups every 20 64B / 66B blocks in the received FlexE block stream, maps the 20 64B / 66B blocks to timeslots 0 to 19, and distributes the 20 64B / 66B blocks sequentially through timeslots 0 to 19. This cycle repeats to form a FlexE subchannel.

[0084] In one possible implementation, the FlexE shim circuit of the interface chip performs time slot mapping on the input FlexE code block stream based on the time slot configuration information, thereby outputting a FlexE client code block stream at a specified rate. The time slot configuration information includes at least one of the number of time slots occupied by one or more FlexE client code block streams or the time slot positions occupied by one or more FlexE client code block streams. For example, if the bandwidth corresponding to a time slot is 5G, and the time slot configuration information indicates that the FlexE client code block stream occupies 2 time slots, the FlexE shim circuit selects any two time slots from time slot 0 to time slot 19 as the time slots occupied by a FlexE client code block stream, maps the FlexE client code block stream to the two time slots, and outputs the FlexE client code block stream at a rate of 5G*2=10G. For example, if the time slot configuration information indicates that the FlexE client code block stream occupies 5 time slots, the FlexE shim circuit selects any five time slots from time slot 0 to time slot 19 as the time slots occupied by a FlexE client code block stream, and maps the FlexE client code block stream to the 5 time slots, so that the output FlexE client code block stream rate is 5G*5=25G.

[0085] In one possible implementation, the FlexE shim circuit of the interface chip maps code blocks in a FlexE code block stream to different numbers of time slots based on time slot configuration information, thereby supporting the output of multiple FlexE client code block streams at different rates. Exemplarily, the time slot configuration information includes a first number of time slots occupied by a first FlexE client code block stream and a second number of time slots occupied by a second FlexE client code block stream. The FlexE shim circuit maps some code blocks in the FlexE code block stream to the first number of time slots based on the time slot configuration information, thereby obtaining a first FlexE client code block stream at a first transmission rate. The FlexE shim circuit also maps another portion of the code blocks in the FlexE code block stream to the second number of time slots based on the time slot configuration information, thereby obtaining a first FlexE client code block stream at a second transmission rate.

[0086] In an exemplary scenario, some Ethernet network devices are unable to provide more Ethernet interfaces due to the limited interface space of the single board. For example, when the Ethernet network device cannot provide a higher-density 10G SFP+ interface, the network device can use the QSFP28 100G FlexE interface (4ⅹ25G) to connect with the optical module with the package type of QSFP28. The 100G QSFP28 optical module can use the method provided in the embodiment of the present application to hash one QSFP28 100G interface into 10 Ethernet interfaces with a rate of 10G, forming a QSFP28 10ⅹ10G hashed optical module, which greatly improves the density of the 10G Ethernet interface. After the Ethernet network device is installed with a QSFP28 10ⅹ10G hashed optical module, it can be connected to the 10 10G SFP+ interfaces of the remote device through the QSFP28 10ⅹ10G hashed optical module, thereby increasing the number of devices that the Ethernet network device can connect to.

[0087] For example, please refer to Figure 1, which is a panel diagram of a single board using a QSFP28 10ⅹ10G hashed optical module provided in an embodiment of the present application. The single board shown in Figure 1 includes 4 QSFP28 100G interfaces, and each QSFP28 100G interface can be connected to a QSFP28 10ⅹ10G hashed optical module provided in an embodiment of the present application. Each QSFP28 10ⅹ10G hashed optical module can hash 10 Ethernet interfaces with a rate of 10G. The 4 QSFP28 10ⅹ10G hashed optical modules hash a total of 40 Ethernet interfaces with a rate of 10G (represented by 40ⅹ10G in the figure), so that the single board can provide a total of 40 Ethernet interfaces with a rate of 10G. Figure 2 is a panel schematic diagram of another single board provided in an embodiment of the present application. The single board shown in Figure 2 includes 10 SFP+ interfaces with a rate of 10G. A 10G Ethernet interface scattered by a QSFP28 100G interface in Figure 2 can be used to connect to a 10G SFP+ interface in Figure 2.

[0088] In another exemplary scenario, the system-side interface of the optical module is an interface with a rate of 200G, and the physical interface corresponding to the system-side interface includes 4 pairs of serializer / deserializer channels (serdes lanes) and the rate of each pair of serdes lanes is 53G. If a straight-through hashing optical module is used, in order to connect the hashing optical module with the Ethernet interface with a rate of 10G of the remote device, the transmission rate of each pair of serdes lanes in the hashing optical module needs to be reduced from 53 to 10, thereby providing 4 Ethernet interfaces with a rate of 10, resulting in the inability to fully utilize the system-side bandwidth and too few Ethernet interfaces provided. However, by using the optical module provided in the embodiment of the present application, the optical module can hash the system-side interface with a rate of 200G into 8 Ethernet interfaces with a rate of 25G, thereby not sacrificing the system-side bandwidth and increasing the number of optical interfaces.

[0089] In another exemplary scenario, a system-side interface with a rate of 400G (the physical interface includes 4 pairs of serdes lanes and the rate of each pair of serdes lanes is 112G) can be hashed into 8 optical interfaces with a rate of 50G.

[0090] To summarize the various scenarios listed above, in scenarios where the transmission rate of the system-side interface of the optical module is high and the number of serdes lanes in the system-side interface is small, if an ordinary hashing optical module is used, the serdes can only be decelerated and used, and the number of optical interfaces cannot be increased. However, the method provided by the embodiment of the present application can increase the number of optical interfaces as much as possible without sacrificing the system-side bandwidth; for example, if a 100G interface uses an ordinary hashing optical module, the rate of the four pairs of 25G serdes lanes on the system side can only be reduced from 25 to 10, and four 10G interfaces can be hashed. However, using the method provided by this embodiment, ten 10G interfaces can be hashed.

[0091] Optionally, the FlexE interface of the optical module and the processing circuit of the optical module are both provided in the interface chip, by integrating the FlexE interface and the processing circuit in the same chip, or separately providing the FlexE interface and the processing circuit in different chips.

[0092] In some embodiments, an optical module can be deployed outside a network device. For example, the optical module includes a housing; the housing is provided with an electrical interface and multiple optical interfaces, the electrical interface being used to connect to a network device outside the optical module; an interface chip is disposed within the housing, the interface chip includes a FlexE interface, a processing circuit, and multiple Ethernet interfaces, the FlexE interface being opposite the electrical interface; the processing circuit is used to convert a FlexE code block stream received by the FlexE interface into a multiple Ethernet code block stream and output the multiple Ethernet code block streams to the multiple Ethernet interfaces, the multiple Ethernet interfaces corresponding one-to-one to the multiple optical interfaces; an optoelectronic conversion device is disposed within the housing, one end of the optoelectronic conversion device is electrically connected to the multiple Ethernet interfaces of the interface chip, and the other end of the optoelectronic conversion device is opposite the multiple optical interfaces. In some embodiments, the optical module is deployed inside the network device.

[0093] The following four examples further illustrate the optical module, the network device including the optical module, and the data transmission method based on the optical module provided in the embodiments of the present application.

[0094] Example 1

[0095] FIG3 is a schematic diagram of the architecture of a network device 1 provided in an embodiment of the present application. The network device 1 shown in FIG3 includes an optical module 10 and a PCB 20.

[0096] The optical module 10 shown in FIG3 is a 10x10G hashing optical module. The optical module 10 shown in FIG3 supports hashing a 100G FlexE interface on the system side into ten 10G Ethernet interfaces on the line side. A 100G FlexE interface on the system side can be implemented using four 25G SerDes lanes. The optical module 10 shown in FIG3 can convert four 25G SerDes lanes on the system side into ten 10G Ethernet channels on the line side.

[0097] The optical module 10 can be a Quad Small Form-factor Pluggable 28 (QSFP28) optical module. The optical module 10 includes a housing 18, an interface chip 11, an optoelectronic conversion device 12, and an optical port connector 13. The optical port connector 13 includes an optical interface 14. The interface chip 11, the optoelectronic conversion device 12, and the optical port connector 13 are disposed within the housing 18. The interface chip 11 and the optoelectronic conversion device 12 are disposed within the housing 18 of the optical module 10. The interface chip 11, the optoelectronic conversion device 12, and the optical port connector 13 are connected in series in sequence. In one possible implementation, the interface chip 11, the optoelectronic conversion device 12, the optical port connector 13, and the optical interface 14 are interconnected via a path (such as a bus, optical fiber, or other type of signal line) within the optical module 10.

[0098] The interface chip 11 includes a system-side interface 111, a processing circuit 112, and a line-side interface 113. The system-side interface 111, the processing circuit 112, and the line-side interface 113 are connected in series.

[0099] The system-side interface 111 is communicatively connected to the MAC chip 21 on the PCB 20. The system-side interface 111 includes one or more FlexE interfaces. The system-side interface 111 may include a 100G FlexE interface, which is used to transmit a FlexE code block stream at a rate of 100G between the optical module 10 and the PCB 20. In one possible implementation, the interface chip 11 configures the operating mode of the system-side interface 111 to FlexE mode, so that the system-side interface 111 implements the functions of a FlexE interface. The system-side interface 111 is connected to the MAC chip 21 via a FlexE channel 310. The system-side interface 111 can be an electrical signal interface. In other words, the system-side interface 111 is used to transmit the FlexE code block stream in the form of an electrical signal between the processing circuit 112 and the MAC chip 21. The system-side interface 111 may include multiple physical interfaces. Each physical interface in the system-side interface 111 can be connected to the MAC chip 21 via a signal line. Exemplarily, the system-side interface 111 includes a 4-lane SerDes interface, which is connected to the PCB 20 via four pairs of differential signal lines. The four pairs of differential signal lines are used to transmit four pairs of electrical signals. Each pair of differential signal lines includes two signal lines, one for receiving one electrical signal and the other for transmitting one electrical signal. Referring to FIG3 , the system-side interface 111 includes Interface 0, Interface 1, Interface 2, and Interface 3 in the transmit direction, and Interface 0, Interface 1, Interface 2, and Interface 3 in the receive direction. Interface 0 in the transmit direction and Interface 0 in the receive direction belong to the SerDes interface of the first pair of lanes, while Interface 1 in the transmit direction and Interface 1 in the receive direction belong to the SerDes interface of the second pair of lanes. The receive interface and the transmit interface in the system-side interface 111 can be implemented using the same physical interface, or they can be implemented using different physical interfaces. The system-side interface 111 can include one or more FlexE group interfaces. For example, the interface chip 11 adds interface 0, interface 1, interface 2, and interface 3 to the same FlexE group. Based on the FlexE bundling feature, interface 0, interface 1, interface 2, and interface 3 work together to implement a FlexE group interface.

[0100] The processing circuit 112 is used to implement the conversion between the FlexE code block stream and the Ethernet code block stream. For example, the processing circuit 112 is used to implement the conversion between the FlexE code block stream with a rate of 100G and the 10-way Ethernet code block stream with a rate of 10G. In the process of the PCB 20 sending a signal to the optical module 10, the processing circuit 112 is used to convert the received FlexE code block stream with a rate of 100G into a 10-way Ethernet code block stream with a rate of 10G, thereby hashing the FlexE interface with a rate of 100G into a 10-way Ethernet interface with a rate of 10G. In one possible implementation, the processing circuit 112 is used to distribute the code blocks in the FlexE code block stream with a rate of 100G to 10 time slots in sequence based on the time slot mapping mechanism of the FlexE shim, so as to generate a 10-way Ethernet code block stream with a rate of 10G. In the process of the remote device sending a signal to the optical module 10 through the optical fiber 40, the processing circuit 112 is used to convert the received 10-channel Ethernet code block stream with a rate of 10G into a FlexE code block stream with a rate of 100G. The processing circuit 112 may include an integrated circuit or a microprocessor for realizing the conversion between the FlexE code block stream and the Ethernet code block stream. For example, the processing circuit 112 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general array logic (GAL) or any combination thereof.

[0101] The line-side interface 113 is communicatively connected to the optoelectronic conversion device 12. The line-side interface 113 includes one or more Ethernet interfaces. The line-side interface 113 is used to transmit Ethernet block streams between the optoelectronic conversion device 12 and the processing circuit 112. For example, the line-side interface 113 is a 10x10G Ethernet interface. The line-side interface 113 is used to transmit 10 Ethernet block streams at a rate of 10G. For example, the line-side interface 113 includes interfaces 0, 1, 2, through 9 in the transmit direction, and interfaces 0, 1, 2, through 9 in the receive direction. Interface 0 is used to transmit the first Ethernet block stream at a rate of 10G. Interface 1 is used to transmit the second Ethernet block stream at a rate of 10G. Interface 1 is used to transmit the second Ethernet block stream at a rate of 10G. Similarly, interface 9 is used to transmit the ninth Ethernet block stream at a rate of 10G. The line-side interface 113 may be an electrical signal interface. In other words, the line-side interface 113 is used to transmit the Ethernet block stream in the form of electrical signals between the processing circuit 112 and the optoelectronic conversion device 12. The receiving interface and the transmitting interface in the line-side interface 113 can be implemented through the same physical interface, or the receiving interface and the transmitting interface in the line-side interface 113 can be implemented through different physical interfaces.

[0102] The optoelectronic conversion device 12 includes an optical transmitter 121 and an optical receiver 122. One end of the optical transmitter 121 is connected to the line-side interface 113 of the interface chip 11, and the other end is connected to the optical port connector 13. The optical transmitter 121 is used to convert electrical signals from the interface chip 11 into optical signals and transmit them to the optical port connector 13. Specifically, the optical transmitter 121 receives 10 electrical signals from the line-side interface 113 of the interface chip 11, each of which includes a 10G Ethernet block stream. The optical transmitter 121 converts the 10 electrical signals into 10 optical signals, each of which includes a 10G Ethernet block stream. The optical transmitter 121 transmits the 10 optical signals to the optical port connector 13. The optical transmitter 121 may include a light source circuit. The light source circuit 1213 is a circuit element capable of generating light signals, such as a laser diode (LD) or a light emitting diode (LED). The light source circuit 1213 is configured to generate 10 optical signals based on 10 electrical signals.

[0103] The optical receiver 122 is configured to convert optical signals from the optical port connector 13 into electrical signals and transmit them to the interface chip 11. For example, the optical receiver 122 receives 10 optical signals from the optical port connector 13, each of which includes a 10G Ethernet block stream. The optical receiver 122 converts the 10 optical signals into 10 electrical signals, each of which includes a 10G Ethernet block stream. The optical receiver 122 transmits the 10 electrical signals to the line-side interface 113 of the interface chip 11. The optical receiver 122 may include a photodetection circuit. The photodetection circuit may include a photosensitive detector (such as a photodiode or a photodiode array) and related circuitry. The photodetection circuit is configured to convert the 10 optical signals into 10 electrical signals, such as current or voltage signals.

[0104] The optical port connector 13, also known as a fiber optic interface connector, is a fiber optic connector that connects to the optical module. The optical port connector 13 is used to connect to the optical fiber 40. The optical port connector 13 is used to transmit optical signals between the optical fiber 40 and the optoelectronic conversion device 12. One end of the optical port connector 13 is connected to the optoelectronic conversion device 12. The other end of the optical port connector 13 is connected to the optical fiber 40. The optical port connector 13 includes multiple optical interfaces 14. For example, the multiple optical interfaces 14 include ten optical interfaces (Optical Interface 0, Optical Interface 1, Optical Interface 9) in the transmitting direction, and ten optical interfaces (Optical Interface 0, Optical Interface 1, Optical Interface 9) in the receiving direction. Optical interface 0 is used to transmit the first optical signal between the optical fiber 40 and the optoelectronic conversion device 12. Optical interface 1 is used to transmit the second optical signal between the optical fiber 40 and the optoelectronic conversion device 12. Similarly, optical interface 9 is used to transmit the tenth optical signal between the optical fiber 40 and the optoelectronic conversion device 12. The optical port connector 13 is, for example, an MPO connector.

[0105] PCB 20 generates four electrical signals carrying a 100G FlexE block stream. PCB 20 transmits these signals to optical module 10. PCB 20 can be, for example, a main control board. It can also be an interface board. It can also be a circuit board housing a processor. For example, it can be a NP or CPU. PCB 20 includes a MAC chip 21.

[0106] The FlexE channel 310 is a FlexE channel in the sending direction (from the PCB 20 to the optical module 10). The FlexE channel 310 is used to transmit the FlexE code block stream from the PCB 20 through the optical module 10 to the optical fiber 40. The FlexE channel 310 includes a FlexE interface located on the optical module 10 and a FlexE interface located on the PCB 20. In one example, the FlexE channel 310 includes a FlexE interface located on the interface chip 11 and a FlexE interface located on the MAC chip 21. For example, the FlexE channel 310 includes four physical interfaces, namely interface 0, interface 1, interface 2, and interface 3, located on the interface chip 11. Each of the four physical interfaces is used to receive a FlexE code block stream with a rate of 25G from the PCB 20. The FlexE channel 310 can be a FlexE group channel. The FlexE channel 310 includes a FlexE group interface located on the interface chip 11 and a FlexE group interface located on the MAC chip 21.

[0107] FlexE channel 320 is a FlexE channel in the receive direction (from optical module 10 to PCB 20). FlexE channel 320 is used to transmit the FlexE code block stream from optical fiber 40 through optical module 10 to PCB 20. FlexE channel 320 includes four physical interfaces: Interface 0, Interface 1, Interface 2, and Interface 3 on interface chip 11. Each of these four physical interfaces is used to send a 25G FlexE code block stream to PCB 20. FlexE channel 320 can be a FlexE group channel. FlexE channel 320 includes a FlexE group interface on interface chip 11 and a FlexE group interface on MAC chip 21.

[0108] When PCB 20 sends a signal to optical module 10, MAC chip 21 generates four electrical signals. The four electrical signals are used to carry a FlexE code block stream with a rate of 100G. Each of the four electrical signals carries a FlexE code block stream with a rate of 25G, that is, 4×25G FlexE code block streams. MAC chip 21 sends the four electrical signals to the system-side interface 111 of interface chip 11 in optical module 10. The system-side interface 111 of interface chip 11 receives the four electrical signals from MAC chip 21 through FlexE channel 310. The system-side interface 111 of interface chip 11 sends the four electrical signals carrying the FlexE code block stream with a rate of 100G to the processing circuit 112 inside interface chip 11. For example, referring to FIG. 3 , in the transmit (TX) direction, the system-side interface 111 includes four FlexE interfaces: interface 0, interface 1, interface 2, and interface 3. Interface 0 in the system-side interface 111 receives the first electrical signal (TX0) from PCB 20. The first electrical signal (TX0) includes a FlexE block stream at a rate of 25G. Interface 0 sends the first electrical signal to the processing circuit 112. Interface 1 in the system-side interface 111 receives the second electrical signal (TX1) from PCB 20. The second electrical signal (TX1) includes a FlexE block stream at a rate of 25G. Interface 1 sends the second electrical signal to the processing circuit 112. Interface 2 in the system-side interface 111 receives the third electrical signal (TX3) from PCB 20. The third electrical signal (TX3) includes a FlexE block stream at a rate of 25G. Interface 2 sends the third electrical signal to the processing circuit 112. Interface 3 in the system-side interface 111 receives the fourth electrical signal (TX4) from PCB 20. The fourth electrical signal (TX4) includes a FlexE block stream at a rate of 25G. The interface 3 sends the fourth electrical signal to the processing circuit 112 .

[0109] Processing circuit 112 obtains FlexE block streams at a rate of 100G carried by four electrical signals. Processing circuit 112 performs time slot mapping based on the 100G FlexE block streams, resulting in 10 Ethernet block streams, each of which has a transmission rate of 10G. Processing circuit 112 then obtains 10 electrical signals based on these 10 10G Ethernet block streams. Processing circuit 112 then sends these 10 electrical signals, each carrying a 10G Ethernet block stream, to line-side interface 113 of interface chip 11. Line-side interface 113 of interface chip 11 then sends these 10 electrical signals to optical transmitter 121. For example, referring to FIG3 , in the TX direction, line-side interface 113 of interface chip 11 includes 10 Ethernet interfaces: Interface 0, Interface 1, Interface 2, Interface 9. Interface 0 in line-side interface 113 sends the first electrical signal carrying a 10G Ethernet block stream to optical transmitter 121. Interface 1 in line-side interface 113 sends the second electrical signal carrying a 10G Ethernet block stream to optical transmitter 121. Similarly, interface 9 in line-side interface 113 sends the tenth electrical signal carrying a 10G Ethernet block stream to optical transmitter 121.

[0110] Optical transmitter 121 receives 10 electrical signals from line-side interface 113. It performs electrical-to-optical conversion on the 10 electrical signals, generating 10 optical signals. Each of the 10 optical signals carries a 10G Ethernet block stream. Optical transmitter 121 transmits the 10 optical signals to optical connector 13. Optical connector 13 transmits the 10 optical signals to optical fiber 40 via optical interface 14. Optical fiber 40 transmits the 10 optical signals to a remote device (not shown).

[0111] When a remote device sends a signal to optical module 10, optical fiber 40 transmits 10 optical signals to optical interface 14. Each of these 10 optical signals carries a 10G Ethernet block stream. Optical connector 13 transmits these 10 optical signals to optical receiver 122. Optical receiver 122 receives these 10 optical signals and performs optoelectronic conversion on them, generating 10 electrical signals. Each of these electrical signals carries a 10G Ethernet block stream. Optical receiver 122 then transmits these 10 electrical signals to line-side interface 113 of interface chip 11.

[0112] The line-side interface 113 of the interface chip 11 sends 10 electrical signals to the processing circuit 112. For example, the line-side interface 113 includes 10 Ethernet interfaces: interface 0, interface 1, interface 2, interface 9, and so on. Interface 0 of the line-side interface 113 sends the first electrical signal carrying a 10G Ethernet block stream to the processing circuit 112. Interface 1 of the line-side interface 113 sends the second electrical signal carrying a 10G Ethernet block stream to the processing circuit 112. Similarly, interface 9 of the line-side interface 113 sends the tenth electrical signal carrying a 10G Ethernet block stream to the processing circuit 112.

[0113] The processing circuit 112 receives 10 electrical signals and obtains 10 Ethernet code block streams with a rate of 10G carried by the 10 electrical signals. The processing circuit 112 performs time slot mapping on the 10 Ethernet code block streams with a rate of 10G to obtain a FlexE code block stream with a rate of 100G. The processing circuit 112 obtains 4 electrical signals based on the FlexE code block stream with a rate of 100G. The 4 electrical signals are used as a whole to carry a FlexE code block stream with a rate of 100G, and each of the 4 electrical signals carries a FlexE code block stream with a rate of 25G. The processing circuit 112 sends the 4 electrical signals to the system side interface 111. The system side interface 111 sends the 4 electrical signals to the MAC chip 21 through the FlexE channel 320. For example, referring to FIG3 , in the receive (RX) direction, the system-side interface 111 includes interface 0, interface 1, interface 2, and interface 3. Interface 0 is used to receive the first electrical signal (RX0) from the processing circuit 112, and interface 0 sends the received first electrical signal (RX0) to the MAC chip 21. The first electrical signal (RX0) includes a FlexE code block stream at a rate of 25G. Interface 1 is used to receive the second electrical signal (RX1) from the processing circuit 112, and interface 1 sends the received second electrical signal (RX0) to the MAC chip 21. The second electrical signal (RX1) includes a FlexE code block stream at a rate of 25G. Interface 2 is used to receive the third electrical signal (RX2) from the processing circuit 112, and interface 2 sends the received third electrical signal (RX2) to the MAC chip 21. The third electrical signal (RX2) includes a FlexE code block stream (RX2) at a rate of 25G. Interface 3 is used to receive the fourth electrical signal (RX3) from the processing circuit 112, and interface 3 sends the received fourth electrical signal (RX3) to the MAC chip 21. The fourth electrical signal (RX3) includes a FlexE code block stream with a rate of 25G.

[0114] FIG4 is a schematic diagram of the internal structure of processing circuit 112 in FIG3 . Processing circuit 112 includes system-side PCS circuit 1121, FlexE shim circuit 1122, 64B / 66B transcoding adaptation circuit 1123, and line-side PCS circuit 1124. System-side PCS circuit 1121, FlexE shim circuit 1122, 64B / 66B transcoding adaptation circuit 1123, and line-side PCS circuit 1124 are connected in series.

[0115] The system-side PCS circuit 1121 is used to connect to the PCS circuit (not shown in the figure) in the MAC chip 21. The system-side PCS circuit 1121 performs PCS layer processing on the received FlexE code block stream.

[0116] FlexE shim circuit 1122 performs timeslot mapping to convert between a 100G FlexE block stream and ten 10G FlexE client block streams. FlexE shim circuit 1122 logically divides a 100G FlexE interface into ten FlexE client interfaces, each with a 10G transmission rate. For example, if a timeslot corresponds to 5G bandwidth, FlexE shim circuit 1122 configures each FlexE client block stream to occupy two timeslots. This allows FlexE shim circuit 1122 to increase the number of line-side channels while maintaining minimal bandwidth loss on the system side.

[0117] The 64B / 66B transcoding adapter circuit 1123 is used to convert code blocks in the FlexE encoding format to code blocks in the Ethernet encoding format. For example, the code blocks received by the FlexE interface follow the encoding format defined by the IEEE 802.3 64B / 66B block formats shown in Figure 5. The 64B / 66B encoding format of the 10G Ethernet interface 113 follows the IEEE 802.3 64B / 66B block formats shown in Figure 6. The 64B / 66B transcoding adapter circuit 1123 within the interface chip is used to convert between these two encoding formats.

[0118] The line-side PCS circuit 1124 is used to connect to the PCS circuit in the remote device. The line-side PCS circuit 1124 performs PCS layer processing on the received FlexE code block stream.

[0119] When PCB 20 sends a signal to optical module 10, processing circuit 112 receives a 100G FlexE block stream. System-side PCS circuit 1121 performs PCS layer processing on the 100G FlexE block stream and sends the processed 100G FlexE block stream to FlexE shim circuit 1122. Upon receiving the 100G FlexE block stream, FlexE shim circuit 1122 performs timeslot mapping on the 100G FlexE block stream, generating 10 10G FlexE client block streams. FlexE shim circuit 1122 sends 10 10G FlexE client block streams to 64B / 66B transcoding adaptation circuit 1123. 64B / 66B transcoding adaptation circuit 1123 receives the 10 10G FlexE client block streams and converts the encoding format of each block in each of the 10 10G FlexE client block streams from the FlexE encoding format shown in FIG5 to the Ethernet encoding format shown in FIG6, resulting in 10 10G Ethernet block streams. 64B / 66B transcoding adaptation circuit 1123 then sends the 10 10G Ethernet block streams to line-side PCS circuit 1124. Line-side PCS circuit 1124 performs PCS layer processing on 10 10G Ethernet block streams and sends them to line-side interface 113. Based on this, interface chip 11 hashes a 100G FlexE interface into 10 10G Ethernet interfaces, increasing the density of Ethernet interfaces on the line side.

[0120] During the signal transmission process from optical module 10 to PCB 20, processing circuit 112 receives 10 10G Ethernet block streams. Line-side PCS circuit 1124 performs PCS layer processing on these 10 10G Ethernet block streams and sends them to 64B / 66B transcoding adaptation circuit 1123. 64B / 66B transcoding adaptation circuit 1123 converts the encoding format of each block in each of the 10 10G Ethernet block streams from the Ethernet encoding format shown in FIG6 to the FlexE encoding format shown in FIG5 , generating 10 10G FlexE client block streams. 64B / 66B transcoding adaptation circuit 1123 then sends these 10 10G FlexE client block streams to system-side PCS circuit 1121. The system-side PCS circuit 1121 performs PCS layer processing on 10 10G FlexE client code block streams and sends them to the system-side interface 111. Based on this, the interface chip 11 implements mapping of 10 10G Ethernet interfaces to 100G FlexE interfaces.

[0121] Example 2

[0122] FIG7 is a schematic diagram of the architecture of another network device 1 provided in an embodiment of the present application. In the architecture shown in FIG7, the optical module 10 is an 8x25G hashing optical module. The optical module 10 supports hashing a 200G FlexE interface on the system side into eight 25G Ethernet interfaces. A 200G FlexE interface on the system side can be implemented using four 53G serdes lanes. The optical module 10 shown in FIG3 can convert four 53G serdes lanes on the system side into eight 25G Ethernet channels on the line side.

[0123] The system-side interface 111 of the optical module 10 is a FlexE interface with a transmission rate of 200G. This interface is used to transmit FlexE block streams at a rate of 200G between the optical module 10 and the MAC chip 21. The physical interface corresponding to the system-side interface 111 can be a 4-lane SerDes interface. The line-side interface 113 of the optical module 10 is an 8x25G Ethernet interface, which is used to transmit eight Ethernet block streams, each at a transmission rate of 25G.

[0124] When PCB 20 transmits signals to optical module 10, MAC chip 21 generates four electrical signals, which collectively carry a 200G FlexE block stream. Each of these four electrical signals carries a 53G FlexE block stream, i.e., 4 x 53G FlexE block streams. System-side interface 111 receives these four electrical signals, and processing circuit 112 obtains the 200G FlexE block streams carried by these four electrical signals. Processing circuit 112 performs time slot mapping on these 200G FlexE block streams, resulting in eight Ethernet block streams. Each of these eight Ethernet block streams operates at 25G. Processing circuit 112 transmits these eight electrical signals to line-side interface 113, each carrying one 25G Ethernet block stream. Line-side interface 113 of interface chip 11 transmits these eight electrical signals to optical transmitter 121. For example, referring to FIG7 , in the TX direction, the line-side interface 113 of the interface chip 11 includes ten Ethernet interfaces: Interface 0, Interface 1, Interface 2, Interface 7, and Interface 113. Interface 0 in the line-side interface 113 transmits the first electrical signal carrying a 25G Ethernet block stream to the optical transmitter 121. Interface 1 in the line-side interface 113 transmits the second electrical signal carrying a 25G Ethernet block stream to the optical transmitter 121. Similarly, Interface 7 in the line-side interface 113 transmits the eighth electrical signal carrying a 25G Ethernet block stream to the optical transmitter 121. Optical transmitter 121 receives eight electrical signals from the line-side interface 113. Optical transmitter 121 performs electrical-to-optical conversion on the eight electrical signals to generate eight optical signals, each of which carries a 25G Ethernet block stream. Optical transmitter 121 transmits the eight optical signals to the optical port connector 13. The optical connector 13 sends the eight optical signals to the optical fiber 40 through the optical interface 14. The optical fiber 40 sends the eight optical signals to the remote device.

[0125] When a remote device sends a signal to optical module 10, optical fiber 40 transmits eight optical signals to optical interface 14. Each of these eight optical signals carries a 25G Ethernet block stream. Optical connector 13 transmits these eight optical signals to optical receiver 122. Optical receiver 122 receives the eight optical signals and performs optoelectronic conversion on them, generating eight electrical signals. Each of these eight electrical signals carries a 25G Ethernet block stream. Optical receiver 122 transmits these eight electrical signals to line-side interface 113 of interface chip 11. Line-side interface 113 of interface chip 11 transmits these eight electrical signals to processing circuit 112. For example, line-side interface 113 includes eight Ethernet interfaces: interface 0, interface 1, and interface 2 through interface 7. Interface 0 of line-side interface 113 transmits the first electrical signal, carrying a 25G Ethernet block stream, to processing circuit 112. Interface 1 in line-side interface 113 sends the second electrical signal carrying a 25G Ethernet block stream to processing circuit 112. Similarly, interface 7 in line-side interface 113 sends the eighth electrical signal carrying a 25G Ethernet block stream to processing circuit 112. Processing circuit 112 receives the eight electrical signals and obtains the eight 25G Ethernet block streams carried by these eight electrical signals. Processing circuit 112 performs time slot mapping on the eight 25G Ethernet block streams to obtain a 200G FlexE block stream. Based on the 200G FlexE block stream, processing circuit 112 obtains four electrical signals. These four electrical signals are used to carry a 200G FlexE block stream, with each of the four electrical signals carrying a 53G FlexE block stream. Processing circuit 112 sends these four electrical signals to system-side interface 111. The system-side interface 111 sends four electrical signals to the MAC chip 21 via the FlexE channel 320. For example, referring to FIG7 , in the RX direction, the system-side interface 111 includes interface 0, interface 1, interface 2, and interface 3. Interface 0 is used to receive the first electrical signal (RX0) from the processing circuit 112 and sends the received first electrical signal (RX0) to the MAC chip 21. The first electrical signal (RX0) includes a FlexE code block stream at a rate of 53G. Interface 1 is used to receive the second electrical signal (RX1) from the processing circuit 112 and sends the received second electrical signal (RX0) to the MAC chip 21. The second electrical signal (RX1) includes a FlexE code block stream at a rate of 53G. Interface 2 is used to receive the third electrical signal (RX2) from the processing circuit 112 and sends the received third electrical signal (RX2) to the MAC chip 21. The third electrical signal (RX2) includes a FlexE code block stream (RX2) at a rate of 53G.Interface 3 is used to receive the fourth electrical signal (RX3) from the processing circuit 112, and interface 3 sends the received fourth electrical signal (RX3) to the MAC chip 21. The fourth electrical signal (RX3) includes a FlexE code block stream with a rate of 53G.

[0126] Please refer to Figure 8, which is a schematic diagram of the interface chip 11 within the optical module 10 shown in Figure 7. As shown in Figure 8, when PCB 20 sends a signal to optical module 10, system-side interface 111 sends a 200G FlexE block stream to FlexE shim circuit 1122. Based on timeslot mapping, FlexE shim circuit 1122 converts the 200G FlexE block stream into eight FlexE client block streams. Each of the eight FlexE client block streams has a transmission rate of 25G. FlexE shim circuit 1122 logically divides the 200G FlexE interface into eight FlexE client interfaces, each with a transmission rate of 25G. For example, if the bandwidth corresponding to a timeslot is 5G, FlexE shim circuit 1122 configures each FlexE client block stream to occupy five timeslots. In this way, the FlexE shim circuit 1122 increases the number of line-side channels while hardly losing bandwidth resources on the system side.

[0127] The 64B / 66B transcoding adapter circuit 1123 converts the encoding format of each block in each of the eight 25G FlexE client block streams from the FlexE encoding format shown in FIG5 to the Ethernet encoding format shown in FIG6 , resulting in eight Ethernet block streams, each at 25G. Based on this, the interface chip 11 hashes a 200G FlexE interface into eight 25G Ethernet interfaces.

[0128] During the signal transmission process from optical module 10 to PCB 20, processing circuit 112 receives eight Ethernet block streams, each of which operates at a rate of 25G. Line-side PCS circuit 1124 performs PCS layer processing on these eight 25G Ethernet block streams and sends them to 64B / 66B transcoding adaptation circuit 1123. 64B / 66B transcoding adaptation circuit 1123 converts the encoding format of each block in each of the eight 25G Ethernet block streams from the Ethernet encoding format shown in FIG6 to the FlexE encoding format shown in FIG5 , generating eight FlexE client block streams, each operating at a rate of 25G. 64B / 66B transcoding adaptation circuit 1123 then sends these eight 25G FlexE client block streams to FlexE shim circuit 1122. Based on timeslot mapping, FlexE shim circuit 1122 converts eight 25G FlexE client block streams into a single 200G FlexE block stream. System-side PCS circuit 1121 performs PCS layer processing on the single 200G FlexE block stream and sends it to system-side interface 111. Consequently, interface chip 11 maps eight 25G Ethernet interfaces into a single 200G FlexE interface.

[0129] Example 3

[0130] FIG9 is a schematic diagram of the architecture of another network device 1 provided in an embodiment of the present application. The optical module 10 in the architecture shown in FIG9 is an 8×50G hashing optical module. The optical module 10 shown in FIG9 supports hashing a FlexE interface with a system-side rate of 400G into eight Ethernet interfaces with a rate of 50G on the line side. The FlexE interface with a system-side rate of 400G can be implemented using four serdes lanes with a transmission rate of 112G. The optical module 10 shown in FIG3 can convert four serdes lanes with a transmission rate of 112G on the system side into eight Ethernet channels with a rate of 50G on the line side.

[0131] The system-side interface 111 of the optical module 10 is a FlexE interface with a transmission rate of 400G. The system-side interface 111 is used to transmit a FlexE code block stream at a rate of 400G between the optical module 10 and the MAC chip 21. The physical interface corresponding to the system-side interface 111 can be a 4-lane SerDes interface. The line-side interface 113 of the optical module 10 is an 8x50G Ethernet interface, which is used to transmit 8 Ethernet code block streams, each of which has a transmission rate of 50G. The processing circuit 112 in the interface chip 11 of the optical module 10 in Figure 9 converts the FlexE code block stream at a rate of 400G into 8 Ethernet code block streams based on time slot mapping, each of which has a transmission rate of 50G, thereby mapping one FlexE interface at a rate of 400G to eight Ethernet interfaces at a rate of 50G.

[0132] Please refer to Figure 10, which is a schematic diagram of the structure of interface chip 11 within optical module 10 in Figure 9. As shown in Figure 10, when PCB 20 sends a signal to optical module 10, system-side interface 111 sends a 400G FlexE block stream to FlexE shim circuit 1122. Based on time slot mapping, FlexE shim circuit 1122 converts the 400G FlexE block stream into eight FlexE client block streams, each of which transmits at a 50G rate. Because the 64B / 66B code blocks in the 50G Ethernet block stream use the same encoding format as the FlexE encoding format, a 64B / 66B transcoding adapter module is not required in interface chip 11.

[0133] Example 4

[0134] FIG11 is a schematic diagram of the architecture of another network device 1 provided in an embodiment of the present application. In the system architecture shown in FIG11, the optical module 10 is a multi-rate hashing optical module. In Example 4, the optical module 10 utilizes the flexible and configurable characteristics of FlexE to enable the optical module to hash a FlexE interface into Ethernet interfaces with multiple transmission rates. In FIG11, an example is used in which the optical module 10 hashes a FlexE interface with a rate of m times 100G into n1 Ethernet interfaces with a rate of 10G, n2 Ethernet interfaces with a rate of 25G, and n3 Ethernet interfaces with a rate of 25G. In other embodiments, the optical module 10 hashes a FlexE interface into two Ethernet interfaces with different rates or into Ethernet interfaces with three or more rates.

[0135] For example, as shown in FIG11 , the system-side interface 111 in the optical module 10 is a FlexE interface with a transmission rate of m times 100G. The system-side interface 111 is used to transmit a FlexE code block stream at a rate of m times 100G between the optical module 10 and the PCB 20, represented in FIG11 as an m×100G FlexE code block stream. m represents the ratio of the bandwidth occupied by the system-side interface 111 to 100G, that is, how many times the 100G bandwidth the system-side interface 111 occupies. m is a positive integer. For example, if the system-side interface 111 is a FlexE interface with a rate of 100G, a FlexE interface with a rate of 200G, a FlexE interface with a rate of 400G, or a FlexE interface with a rate of 800G, then m is 1, 2, 4, or 8, respectively.

[0136] The line-side interface 113 in the interface chip 11 includes (n1+n2+n3) Ethernet interfaces. Each of the n1 Ethernet interfaces is used to transmit a 10G Ethernet block stream. Each of the n2 Ethernet interfaces is used to transmit a 25G Ethernet block stream. Each of the n3 Ethernet interfaces is used to transmit a 50G Ethernet block stream.

[0137] n1 is the number of 10G FlexE subchannels, the number of 10G FlexE client block flows, and the number of 10G Ethernet interfaces hashed by the optical module. n1 x 10G represents the total bandwidth occupied by 10G Ethernet block flows. n1 is 0 or a positive integer.

[0138] n2 is the number of 25G FlexE subchannels, the number of 25G FlexE client block flows, and the number of 25G Ethernet interfaces hashed by the optical module. n2 x 25G represents the total bandwidth occupied by 25G Ethernet block flows. n2 is 0 or a positive integer.

[0139] n3 is the number of 50G FlexE subchannels, the number of 50G FlexE client block flows, and the number of 50G Ethernet interfaces hashed by the optical module. n3 x 50G represents the total bandwidth occupied by 50G Ethernet block flows. n3 is 0 or a positive integer.

[0140] The total bandwidth occupied by line-side interface 113 is less than the total bandwidth occupied by system-side interface 111. That is, n1 x 10G + n2 x 25G + n3 x 50G ≤ m x 100G. The sum of n1, n2, and n3 can be greater than m, meaning the number of line-side channels is greater than the number of system-side channels.

[0141] The following is an example of the process of PCB 20 sending data to optical module 10 in Figure 11. Figure 12 is a flow chart of a data transmission method provided by an embodiment of the present application. The method shown in Figure 12 is applied to the optical module 10 shown in Figure 11 and includes the following steps.

[0142] S510 , the MAC chip 21 in the PCB 20 sends a FlexE code block stream at a rate of m times 100G to the system-side interface 111 in the interface chip 11 through the FlexE channel.

[0143] S520 : The system-side interface 111 in the interface chip 11 receives a FlexE code block stream at a rate of m times 100G from the FlexE channel and sends the m times 100G FlexE code block stream to the processing circuit 112 in the interface chip 11 .

[0144] At step S530, the processing circuit 112 converts the FlexE block stream at a rate of m times 100G into n1 Ethernet block streams at a rate of 10G, n2 Ethernet block streams at a rate of 25G, and n3 Ethernet block streams at a rate of 50G, thereby hashing the FlexE interface at a rate of m times 100G on the system side into n1 Ethernet interfaces at a rate of 10G, n2 Ethernet interfaces at a rate of 25G, and n3 Ethernet interfaces at a rate of 50G on the line side.

[0145] S540 , the processing circuit 112 sends the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G to the line-side interface 113 in the interface chip 11 .

[0146] S550 , the line-side interface 113 sends the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G to the optical transmitter 121 .

[0147] At step S560, optical transmitter 121 performs electrical-to-optical conversion on the n1 10G Ethernet block stream, the n2 25G Ethernet block stream, and the n3 50G Ethernet block stream, respectively, to generate (n1+n2+n3) optical signals. Optical transmitter 121 transmits the (n1+n2+n3) optical signals to optical port connector 13.

[0148] In a possible implementation, S560 includes the following S5601 to S5603.

[0149] S5601, the 10G optical transmitter receives n1 Ethernet code block streams with a rate of 10G, performs electrical-to-optical conversion on the n1 Ethernet code block streams with a rate of 10G, and obtains n1 optical signals. Each optical signal in the n1 optical signals includes an Ethernet code block stream with a rate of 10G. The 10G optical transmitter sends the n1 optical signals to the optical port connector 13.

[0150] S5602, the 25G optical transmitter is used to receive n2 Ethernet code block streams with a rate of 25G, perform electrical-to-optical conversion on the n2 Ethernet code block streams with a rate of 25G, and obtain n2 optical signals. Each of the n2 optical signals includes an Ethernet code block stream with a rate of 25G. The 25G optical transmitter sends the n2 optical signals to the optical port connector 13.

[0151] S5603, the 50G optical transmitter is used to receive n3 Ethernet code block streams with a rate of 50G, perform electrical-to-optical conversion on the n3 Ethernet code block streams with a rate of 50G, and obtain n3 optical signals. Each of the n3 optical signals includes an Ethernet code block stream with a rate of 50G. The 50G optical transmitter sends the n3 optical signals to the optical port connector 13.

[0152] At step S570, optical connector 13 receives an optical signal from channel n1 carrying a 10G Ethernet block stream, an optical signal from channel n2 carrying a 25G Ethernet block stream, and an optical signal from channel n3 carrying a 50G Ethernet block stream. Optical connector 13 transmits the optical signal from channel n1 carrying a 10G Ethernet block stream, the optical signal from channel n2 carrying a 25G Ethernet block stream, and the optical signal from channel n3 carrying a 50G Ethernet block stream to optical fiber 40 via optical interface 14.

[0153] The method provided in this embodiment utilizes the flexible and configurable features of FlexE to enable an optical module to simultaneously hash interfaces with multiple rates.

[0154] The following is an example of the process of the optical module 10 in Figure 11 sending data to the PCB 20. Figure 13 is a flow chart of a data transmission method provided by an embodiment of the present application. The method shown in Figure 13 is applied to the optical module 10 shown in Figure 11 and includes the following steps.

[0155] S610: Optical interface 14 of optical connector 13 receives an optical signal from channel n1 carrying a 10G Ethernet block stream, an optical signal from channel n2 carrying a 25G Ethernet block stream, and an optical signal from channel n3 carrying a 50G Ethernet block stream. Optical connector 13 transmits the optical signal from channel n1 carrying a 10G Ethernet block stream, the optical signal from channel n2 carrying a 25G Ethernet block stream, and the optical signal from channel n3 carrying a 50G Ethernet block stream to optical receiver 122.

[0156] S620: The optical receiver 122 performs photoelectric conversion on the optical signal of the n1 channel carrying the Ethernet block stream with a rate of 10G, the optical signal of the n2 channel carrying the Ethernet block stream with a rate of 25G, and the optical signal of the n3 channel carrying the Ethernet block stream with a rate of 50G, to obtain (n1+n2+n3) electrical signals.

[0157] In a possible implementation, step S620 includes the following steps S6201 to S6203.

[0158] At step S6201, a 10G optical receiver receives n1 optical signals carrying a 10G Ethernet block stream. The 10G optical receiver performs optoelectronic conversion on the n1 optical signals to generate n1 electrical signals, each of which contains a 10G Ethernet block stream. The 10G optical receiver then transmits the n1 electrical signals to the 10G Ethernet interface in the line-side interface 113 of the interface chip 11.

[0159] At step S6202, the 25G optical receiver receives n2 optical signals carrying an Ethernet block stream at a rate of 25G, performs optoelectronic conversion on the n2 optical signals, and obtains n2 electrical signals. Each of the n2 electrical signals includes an Ethernet block stream at a rate of 25G. The 25G optical receiver sends the n2 electrical signals to the 25G Ethernet interface in the line-side interface 113 in the interface chip 11.

[0160] S6203, the 50G optical receiver receives n3 optical signals carrying Ethernet code block streams at a rate of 50G, performs optoelectronic conversion on the n3 optical signals, and obtains n3 electrical signals. Each of the n3 electrical signals includes an Ethernet code block stream at a rate of 50G. The 50G optical receiver sends the n3 electrical signals to the Ethernet interface with a rate of 50G in the line-side interface 113 in the interface chip 11.

[0161] S630 , the line-side interface 113 sends the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G to the processing circuit 112 in the form of electrical signals.

[0162] S640: The processing circuit 112 converts the n1 Ethernet block stream with a rate of 10G, the n2 Ethernet block stream with a rate of 25G, and the n3 Ethernet block stream with a rate of 50G into a FlexE block stream with a rate of m times 100G, thereby converting the n1 Ethernet interfaces with a rate of 10G, the n2 Ethernet interfaces with a rate of 25G, and the n3 Ethernet interfaces with a rate of 50G on the line side into FlexE interfaces with a rate of m times 100G on the system side.

[0163] S650 , the processing circuit 112 sends the FlexE code block stream at a rate of m times 100G to the system-side interface 111 in the interface chip 11 .

[0164] S660: The system-side interface 111 sends a FlexE code block stream with a rate of m times 100G to the MAC chip 21 in the PCB 20 through the FlexE channel.

[0165] Please refer to Figure 14, which is a schematic diagram of the structure of the interface chip 11 within the optical module 10 shown in Figure 11. The line-side PCS circuit 1124 in the interface chip 11 includes line-side PCS circuit A, line-side PCS circuit B, and line-side PCS circuit C. Line-side PCS circuit A is used to perform PCS layer processing on the n1 channel Ethernet block stream at a rate of 10G. Line-side PCS circuit B is used to perform PCS layer processing on the n2 channel Ethernet block stream at a rate of 25G. Line-side PCS circuit C is used to perform PCS layer processing on the n3 channel Ethernet block stream at a rate of 50G.

[0166] The 64B / 66B transcoding adaptation circuit 1123 includes a 64B / 66B transcoding adaptation circuit A and a 64B / 66B transcoding adaptation circuit B. The 64B / 66B transcoding adaptation circuit A corresponds to an Ethernet interface with a rate of 10G. The 64B / 66B transcoding adaptation circuit B corresponds to an Ethernet interface with a rate of 25G. Because the FlexE code blocks in a 50G FlexE code block stream and the Ethernet code blocks in a 50G Ethernet code block stream have the same encoding format, there is no need to deploy a 64B / 66B transcoding adaptation module for the 50G FlexE code block stream.

[0167] The following further describes step S530 of the method shown in FIG12 in conjunction with the internal structure of the chip shown in FIG14. S530 may include the following steps S530a to S530c.

[0168] S530a: FlexE shim circuit 1122 timeslot-maps the FlexE block streams at m times the 100G rate to obtain n1 FlexE client block streams at a 10G rate, n2 FlexE client block streams at a 25G rate, and n3 FlexE client block streams at a 50G rate. FlexE shim circuit 1122 sends the n1 FlexE client block stream at a 10G rate to 64B / 66B transcoding adaptation circuit A, sends the n2 FlexE client block stream at a 25G rate to 64B / 66B transcoding adaptation circuit B, and sends the n3 FlexE client block stream at a 50G rate as an Ethernet block stream to line-side PCS circuit C.

[0169] S530b: 64B / 66B transcoding adaptation circuit A converts the encoding format of each block in each of the n1 10G FlexE client block streams from the FlexE encoding format shown in FIG5 to the Ethernet encoding format shown in FIG6, thereby obtaining an n1 10G Ethernet block stream. 64B / 66B transcoding adaptation circuit A sends the n1 10G Ethernet block stream to line-side PCS circuit A. 64B / 66B transcoding adaptation circuit B converts the encoding format of each block in each of the n2 25G FlexE client block streams from the FlexE encoding format shown in FIG5 to the Ethernet encoding format shown in FIG6, thereby obtaining an n2 25G Ethernet block stream. The 64B / 66B transcoding adaptation circuit B sends n2 Ethernet code block streams with a rate of 25G to the line-side PCS circuit B.

[0170] At step S530c, line-side PCS circuit A performs PCS layer processing on the n1-channel 10G Ethernet block stream and outputs the processed n1-channel 10G Ethernet block stream to line-side interface 113. Line-side PCS circuit B performs PCS layer processing on the n2-channel 25G Ethernet block stream and outputs the processed n2-channel 25G Ethernet block stream to line-side interface 113.

[0171] The following further describes step S640 of the method shown in FIG13 in conjunction with the internal structure of the chip shown in FIG14. Step S640 may include the following steps S640a to S640c.

[0172] S640a: Line-side PCS circuit A receives n1 Ethernet block streams at a rate of 10G from line-side interface 113. Line-side PCS circuit A performs PCS layer processing on n1 Ethernet block streams at a rate of 10G, and then outputs the processed n1 Ethernet block streams at a rate of 10G to 64B / 66B transcoding adaptation circuit A. Line-side PCS circuit B receives n2 Ethernet block streams at a rate of 25G from line-side interface 113. Line-side PCS circuit B performs PCS layer processing on n2 Ethernet block streams at a rate of 25G, and then outputs the processed n2 Ethernet block streams at a rate of 25G to 64B / 66B transcoding adaptation circuit B. The line-side PCS circuit B receives the n3-channel Ethernet code block stream with a rate of 50G from the line-side interface 113. After performing PCS layer processing on the n3-channel Ethernet code block stream with a rate of 50G, the line-side PCS circuit B outputs the processed n3-channel Ethernet code block stream with a rate of 50G to the FlexE shim circuit 1122.

[0173] At S640b, 64B / 66B transcoding adaptation circuit A converts the encoding format of each block in each of the n1 10G Ethernet block streams from the Ethernet encoding format shown in FIG6 to the FlexE encoding format shown in FIG5 , thereby obtaining an n1 10G FlexE block stream. 64B / 66B transcoding adaptation circuit A sends the n1 10G FlexE block stream to FlexE shim circuit 1122. 64B / 66B transcoding adaptation circuit B converts the encoding format of each block in each of the n2 25G Ethernet block streams from the Ethernet encoding format shown in FIG6 to the FlexE encoding format shown in FIG5 , thereby obtaining an n2 25G FlexE block stream. The 64B / 66B transcoding adaptation circuit B sends n2 FlexE code block streams with a rate of 25G to the FlexE shim circuit 1122.

[0174] S640c: The FlexE shim circuit 1122 performs time slot mapping on the n1 FlexE client code block stream with a rate of 10G, the n2 FlexE client code block stream with a rate of 25G, and the n3 FlexE client code block stream with a rate of 50G, to obtain a FlexE code block stream with a rate of m times 100G.

[0175] The method provided in this embodiment enables a single optical module to hash Ethernet interfaces of multiple rates. After the optical module is installed on a single board, the single board can send multiple Ethernet code block streams of different rates through the single optical module, thereby meeting the demand for transmitting Ethernet code block streams of different rates. There is no need to deploy a corresponding interface board for each transmission rate requirement, thereby reducing the use of different rate interface boards and saving costs.

[0176] An embodiment of the present application provides an optical module, which may be the 10×10G scattered optical module shown in FIG3 of Example 1, the 8×25G scattered optical module shown in FIG7 of Example 2, the 8×50 scattered optical module shown in FIG9 of Example 3, or the scattered optical module shown in FIG11 of Example 4. The optical module includes a FlexE interface, a processing circuit, an optoelectronic conversion device, and multiple optical interfaces.

[0177] The FlexE interface is, for example, the system-side interface 111 in FIG. 3 of Example 1, and the FlexE interface can be a 100G interface. The FlexE interface is also, for example, the system-side interface 111 in FIG. 7 of Example 2, and the FlexE interface can be a 200G interface. The FlexE interface is also, for example, the system-side interface 111 in FIG. 9 of Example 3, and the FlexE interface can be a 400G interface. The FlexE interface is also, for example, the system-side interface 111 in FIG. 11 of Example 4, and the FlexE interface can be an mx100G interface. The FlexE interface is configured to receive a first FlexE code block stream from a network device via a FlexE channel, and the FlexE interface is communicatively connected to the network device via the FlexE channel.

[0178] In order to distinguish between the description of the Ethernet block stream transmitted from the network device to the optical module and the Ethernet block stream transmitted from the optical module to the network device, the Ethernet block stream transmitted from the network device to the optical module is referred to as the first Ethernet block stream, and the Ethernet block stream transmitted from the optical module to the network device is referred to as the first Ethernet block stream.

[0179] The processing circuit is, for example, the processing circuit 112 in FIG. 3 of Example 1. Another example is the processing circuit 112 in FIG. 7 of Example 2. Another example is the processing circuit 112 in FIG. 9 of Example 3. Another example is the processing circuit 112 in FIG. 11 of Example 4. The processing circuit is configured to obtain multiple first Ethernet block streams based on the first FlexE block stream; the optoelectronic conversion device is configured to perform electrical-to-optical conversion on the multiple first Ethernet block streams to obtain multiple first optical signals; and the multiple optical interfaces are configured to transmit the multiple first optical signals to optical fibers. The first Ethernet block stream refers to the Ethernet block stream transmitted from the network device to the optical module. To distinguish between the FlexE client block stream transmitted from the network device to the optical module and the FlexE client block stream transmitted from the optical module to the network device, the FlexE client block stream transmitted from the network device to the optical module is referred to as the first FlexE client block stream, and the FlexE client block stream transmitted from the optical module to the network device is referred to as the first FlexE client block stream.

[0180] In one possible implementation, the processing circuit includes a FlexE shim circuit and a transcoding circuit. The FlexE shim circuit is configured to obtain multiple first FlexE client code block streams based on the first FlexE code block stream, wherein the multiple first FlexE client code block streams include code blocks in a FlexE encoding format. The transcoding circuit is configured to convert the encoding format of the code blocks in the multiple first FlexE client code block streams from a FlexE encoding format to an Ethernet encoding format to obtain the multiple first Ethernet code block streams. The FlexE shim circuit may be the FlexE shim circuit 1122 in FIG. 4 of Example 1, the FlexE shim circuit 1122 in FIG. 8 of Example 2, the FlexE shim circuit 1122 in FIG. 10 of Example 3, or the FlexE shim circuit 1122 in FIG. 14 of Example 4. The transcoding circuit may be the 64B / 66B transcoding adaptation circuit 1123 in FIG4 of Example 1, or the 64B / 66B transcoding adaptation circuit 1123 in FIG8 of Example 2, or the 64B / 66B transcoding adaptation circuit 1123 in FIG10 of Example 3, or the 64B / 66B transcoding adaptation circuit 1123 in FIG14 of Example 4.

[0181] In one possible implementation, the FlexE shim circuit is configured to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, where the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

[0182] In one possible implementation, the multiple first FlexE client code block streams include a first FlexE client code block stream at a first transmission rate and a first FlexE client code block stream at a second transmission rate, where the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client code block stream at the first transmission rate occupies a first number of time slots and the first FlexE client code block stream at the second transmission rate occupies a second number of time slots, where the second number is different from the first number.

[0183] In a possible implementation, a transmission rate of each first Ethernet code block stream in the multiple first Ethernet code block streams is lower than a transmission rate of the first FlexE code block stream.

[0184] In one possible implementation, the multiple optical interfaces are further used to receive multiple second optical signals from the optical fiber, where the multiple second optical signals include multiple second Ethernet code block streams; the optoelectronic conversion device is further used to perform optoelectronic conversion on the multiple second optical signals to obtain multiple electrical signals, where the multiple electrical signals include multiple second Ethernet code block streams; the processing circuit is further used to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; and the FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

[0185] In one possible implementation, the processing circuit includes a FlexE shim circuit and a transcoding circuit; the transcoding circuit is configured to convert an encoding format of code blocks in the multiple second Ethernet code block streams from an Ethernet encoding format to a FlexE encoding format to obtain multiple second FlexE client code block streams; and the FlexE shim circuit is configured to obtain the second FlexE code block stream based on the multiple second FlexE client code block streams.

[0186] In a possible implementation, the optical module includes an interface chip, and the FlexE interface and the processing circuit are both provided on the interface chip.

[0187] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0188] A refers to B, which means that A is the same as B or A is a simple variant of B.

[0189] The terms "first" and "second" in the description and claims of the embodiments of this application are used to distinguish different objects, not to describe a specific order of objects, and should not be understood to indicate or imply relative importance. For example, the terms "first FlexE code block stream" and "second FlexE code block stream" are used to distinguish different FlexE code block streams, not to describe a specific order of FlexE code block streams, and should not be understood to mean that the first FlexE code block stream is more important than the second FlexE code block stream.

[0190] In the embodiments of the present application, unless otherwise specified, "at least one" means one or more, and "a plurality" means two or more. For example, multiple first Ethernet block streams means two or more first Ethernet block streams.

[0191] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in accordance with the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0192] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An optical module, characterized in that: Includes Flexible Ethernet FlexE interface, processing circuit, optoelectronic conversion device and multiple optical interfaces; The FlexE interface is used to receive a first FlexE code block stream from a network device through a FlexE channel, and the FlexE interface is communicatively connected with the network device through the FlexE channel; The processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream; The photoelectric conversion device is used to perform electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; The multiple optical interfaces are used to send the multiple first optical signals to the optical fiber.

2. The optical module according to claim 1, characterized in that: The processing circuit includes a FlexE shim circuit and a transcoding circuit; The FlexE shim circuit is used to obtain a plurality of first FlexE client code block streams based on the first FlexE code block stream, wherein the plurality of first FlexE client code block streams include code blocks having a FlexE coding format; The transcoding circuit is used for converting the coding format of the code blocks in the multiple first FlexE client code block streams from the FlexE coding format to the Ethernet coding format to obtain the multiple first Ethernet code block streams.

3. The optical module according to claim 2, characterized in that: The FlexE shim circuit is used to perform time slot mapping on the first FlexE code block stream based on time slot configuration information to obtain multiple first FlexE client code block streams, wherein the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

4. The optical module according to claim 3, characterized in that: The multiple first Ethernet block streams include a first Ethernet block stream at a first transmission rate and a first Ethernet block stream at a second transmission rate, the multiple first FlexE client block streams include a first FlexE client block stream at a first transmission rate and a first FlexE client block stream at a second transmission rate, the second transmission rate is different from the first transmission rate, the time slot configuration information indicates that the first FlexE client block stream at the first transmission rate occupies a first number of time slots and the first FlexE client block stream at the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

5. The optical module according to any one of claims 1 to 4, characterized in that: The transmission rate of each first Ethernet code block stream in the multiple first Ethernet code block streams is lower than the transmission rate of the first FlexE code block stream.

6. The optical module according to any one of claims 1 to 5, characterized in that: The plurality of optical interfaces are further used to receive multiple second optical signals from the optical fiber, wherein the multiple second optical signals include multiple second Ethernet code block streams; The photoelectric conversion device is further used to perform photoelectric conversion on the multiple second optical signals to obtain multiple electrical signals, wherein the multiple electrical signals include multiple second Ethernet code block streams; The processing circuit is further configured to obtain a second FlexE code block stream based on the multiple second Ethernet code block streams; The FlexE interface is further used to send the second FlexE code block stream to the network device through the FlexE channel.

7. The optical module according to claim 6, characterized in that: The processing circuit includes a FlexE shim circuit and a transcoding circuit; The transcoding circuit is used to convert the coding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet coding format to the FlexE coding format to obtain multiple second FlexE client code block streams; The FlexE shim circuit is used to obtain the second FlexE code block stream based on multiple second FlexE client code block streams.

8. The optical module according to claim 1, characterized in that: The optical module includes an interface chip, and the FlexE interface and the processing circuit are both arranged on the interface chip.

9. An optical module, characterized in that: include: A housing, provided with an electrical interface and a plurality of optical interfaces, wherein the electrical interface is used to connect to a network device outside the optical module, and the plurality of optical interfaces are used to connect to optical fibers outside the optical module; an interface chip, disposed in the housing, the interface chip comprising a flexible Ethernet FlexE interface, a processing circuit and a plurality of Ethernet interfaces, the FlexE interface being opposite to the electrical interface, the processing circuit being disposed between the FlexE interface and the plurality of Ethernet interfaces, the processing circuit being used for converting a FlexE code block stream received by the FlexE interface into a multi-channel Ethernet code block stream and outputting the multi-channel Ethernet code block stream to the plurality of Ethernet interfaces, the plurality of Ethernet interfaces corresponding one to one with the plurality of optical interfaces; The photoelectric conversion device is arranged in the housing, one end of the photoelectric conversion device is electrically connected to the multiple Ethernet interfaces of the interface chip, and the other end of the photoelectric conversion device is opposite to the multiple optical interfaces.

10. A network device, characterized in that: It includes a processor, a first flexible Ethernet FlexE interface and an optical module, wherein the optical module includes a second FlexE interface, a processing circuit, an optoelectronic conversion device and a plurality of optical interfaces, and the first FlexE interface is communicatively connected with the second FlexE interface through a FlexE channel; The processor is configured to generate a first FlexE code block stream; The first FlexE interface is used to send the first FlexE code block stream to the second FlexE interface through the FlexE channel; The processing circuit is used to obtain multiple first Ethernet code block streams based on the first FlexE code block stream; The photoelectric conversion device is used to perform electrical-to-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; The multiple optical interfaces are used to send the multiple first optical signals to the optical fiber.

11. A data transmission method, characterized in that: Applied to optical modules, including: Receiving a first FlexE code block stream from a first network device through a flexible Ethernet FlexE channel, wherein the optical module is communicatively connected with the first network device through the FlexE channel; Obtaining multiple first Ethernet block streams based on the first FlexE block stream; Performing electrical-optical conversion on the multiple first Ethernet code block streams to obtain multiple first optical signals; The multiple paths of first optical signals are sent to the second network device through optical fibers.

12. The method according to claim 11, characterized in that The obtaining multiple first Ethernet code block streams based on the first FlexE code block stream includes: Obtaining a plurality of first FlexE client code block streams based on the first FlexE code block stream, wherein the plurality of first FlexE client code block streams include code blocks in a FlexE coding format; The coding format of the code blocks in the multiple first FlexE client code block streams is converted from the FlexE coding format to the Ethernet coding format to obtain the multiple first Ethernet code block streams.

13. The method according to claim 12, characterized in that The obtaining a plurality of first FlexE client code block streams based on the first FlexE code block stream includes: Based on the time slot configuration information, the first FlexE code block stream is time slot mapped to obtain multiple first FlexE client code block streams, wherein the time slot configuration information indicates at least one of the number of time slots occupied by the multiple first FlexE client code block streams or the time slot positions occupied by the multiple first FlexE client code block streams.

14. The method according to claim 13, characterized in that The multiple first FlexE client code block streams include a first FlexE client code block stream at a first transmission rate and a first FlexE client code block stream at a second transmission rate, wherein the second transmission rate is different from the first transmission rate, and the time slot configuration information indicates that the first FlexE client code block stream at the first transmission rate occupies a first number of time slots and the first FlexE client code block stream at the second transmission rate occupies a second number of time slots, and the second number is different from the first number.

15. The method according to any one of claims 11 to 14, characterized in that The transmission rate of each first Ethernet code block stream in the multiple first Ethernet code block streams is lower than the transmission rate of the first FlexE code block stream.

16. The method according to any one of claims 11 to 15, characterized in that The method further comprises: receiving a plurality of second optical signals from the second network device, wherein the plurality of second optical signals include a plurality of second Ethernet code block streams; Performing photoelectric conversion on the multiple second optical signals to obtain multiple electrical signals, wherein the multiple electrical signals include multiple second Ethernet code block streams; Obtaining a second FlexE code block stream based on the multiple second Ethernet code block streams; The second FlexE code block stream is sent to the first network device through the FlexE channel.

17. The method according to claim 16, characterized in that The obtaining a second FlexE code block stream based on the multiple second Ethernet code block streams includes: Converting the encoding format of the code blocks in the multiple second Ethernet code block streams from the Ethernet encoding format to the FlexE encoding format to obtain multiple second FlexE client code block streams; The second FlexE code block stream is obtained based on multiple second FlexE client code block streams.

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