Drive circuit, display device, and electronic apparatus

Abstract

Provided is a drive circuit with reduced power consumption. The drive circuit comprises: a control circuit; a first switch; a second switch; an amplifier; and a storage circuit. An output terminal of the amplifier is electrically connected to a first terminal of the first switch, an input terminal of the amplifier is electrically connected to a first terminal of the second switch, and a second terminal of the first switch is electrically connected to a second terminal of the second switch. The control circuit has a function of calculating a gradation difference between a first image signal input to the control circuit and a second image signal input from the storage circuit. The control circuit also has a function of comparing the gradation difference with a reference value and outputting a comparison result as a first logic signal. In addition, the control circuit has a function of inputting the first logic signal to a control terminal of the first switch, and a function of generating a second logic signal in which the logic of the first logic signal is inverted and inputting the second logic signal to a control terminal of the second switch.

Description

Drive circuit, display device and electronic device

[0001] One embodiment of the present invention relates to a driver circuit, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, improvements have been made in various aspects to display devices included in wearable devices, monitors, mobile phones (e.g., smartphones), wristwatch-type information terminals, tablet-type information terminals, notebook PCs (personal computers), etc. for XR (Extended Reality or Cross Reality) such as VR (Virtual Reality) and AR (Augmented Reality). For example, display devices are being developed to improve screen resolution, color reproducibility (NTSC ratio), size of driving circuits, and power consumption.

[0004] For example, wearable devices for XR are preferably equipped with high-definition (high pixel density) display devices to enhance the sense of immersion and realism for users. High-definition display devices can make pixels less visible to users and reduce the graininess of images displayed on the display device. In display devices with many fine pixel circuits, the number of pixel circuits connected to a single data line (sometimes referred to herein as a source line, image signal line, etc.) increases, making attenuation of image signals transmitted to the data line more likely. Patent Document 1 discloses an invention in which a display device includes a data driver circuit (sometimes referred to herein as a source driver circuit, etc.) and a load circuit in each of multiple display units, and the display units, data driver circuit, and load circuit are overlapped to reduce the number of columns per display unit and suppress attenuation of image signals transmitted to the data line. Patent Document 1 also discloses a configuration in which a buffer amplifier (sometimes referred to herein as an amplifier or amplifier) ​​for amplifying image signals is not connected to the data line, which can suppress attenuation of image signals.

[0005] International Publication No. 2021 / 191721

[0006] When a display device is configured without connecting a buffer amplifier (hereinafter referred to as an amplifier) ​​for amplifying an image signal to a data line, depending on the image to be displayed, the generation of the image signal may not be completed in time for the image to be rewritten. For example, when the luminance of an image signal transmitted to a data line changes from the lowest luminance to the highest luminance, the charging of the data line transmitting the image signal must be completed within the time required to raise the potential of the data line from the lowest to the highest. Also, when the luminance of an image signal transmitted to a data line changes from the highest to the lowest luminance, the discharging of the data line transmitting the image signal must be completed within the time required to lower the potential of the data line from the highest to the lowest. In other words, when the change in the gradation of an image transmitted to a data line is greater than a certain level, the charging and discharging of the data line may not be completed in time without an amplifier.

[0007] On the other hand, if the change in the gradation of the image data before and after it is transmitted to the data line is less than a certain level, the data line may be charged and discharged in time without an amplifier. Therefore, by configuring the drive circuit to determine whether to use an amplifier in accordance with the change in gradation of the image data before and after it is transmitted to the data line, it is possible to realize a display device that drives the amplifier when the change in gradation of the image data is large.

[0008] An object of one embodiment of the present invention is to provide a driver circuit with reduced power consumption. Another object of one embodiment of the present invention is to provide a display device including the driver circuit. Another object of one embodiment of the present invention is to provide a display device with high image quality. Another object of one embodiment of the present invention is to provide a display device with a reduced circuit area. Another object of one embodiment of the present invention is to provide a display device with a high driving frequency. Another object of one embodiment of the present invention is to provide an electronic device including the display device. Another object of one embodiment of the present invention is to provide a novel driver circuit, a novel display device, or a novel electronic device.

[0009] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems. Therefore, one embodiment of the present invention does not necessarily solve all of the above problem and other problems.

[0010] One embodiment of the present invention is a driver circuit that determines whether to use an amplifier in accordance with a change in the gray level of image data before and after the data line is transmitted. Therefore, the driver circuit includes a circuit that calculates the difference in gray level (or luminance) between the image data before and after the data line. The driver circuit also includes a circuit that determines whether the calculated gray level difference indicates the need to quickly charge and discharge the data line (whether an amplifier is required). The driver circuit can be a comparison circuit that determines whether the gray level difference is greater than or equal to a predetermined value (which may be referred to as a threshold value, a reference value, or the like in this specification) set in advance by a user. For example, the comparison circuit preferably outputs a signal that drives the amplifier when the gray level difference is equal to or greater than the predetermined value, or outputs a signal that does not drive the amplifier when the gray level difference is less than the predetermined value.

[0011] A typical example of a configuration according to one embodiment of the present invention will be described below.

[0012] (1) One embodiment of the present invention is a driver circuit including a control circuit, a first switch, a second switch, an amplifier, and a memory circuit, wherein an output terminal of the amplifier is electrically connected to a first terminal of the first switch, an input terminal of the amplifier is electrically connected to a first terminal of the second switch, and a second terminal of the first switch is electrically connected to a second terminal of the second switch.

[0013] The control circuit has a function of acquiring a first image signal corresponding to image data of a first coordinate input to the control circuit and a second image signal corresponding to image data of a second coordinate read from the memory circuit, thereby calculating a difference in gradation between the first image signal and the second image signal. The control circuit also has a function of comparing the magnitude of the difference in gradation with a reference value and outputting the comparison result as a first logic signal. The control circuit also has a function of inputting the first logic signal to a control terminal of a first switch and a function of inputting a second logic signal, the logic of which is the inverse of the first logic signal, to a control terminal of a second switch. The memory circuit has a function of acquiring the first image signal and storing the image data of the first coordinate.

[0014] (2) Alternatively, according to one embodiment of the present invention, in the above-described (1), the control circuit may include a subtraction circuit, a comparison circuit, a first flip-flop circuit, a first latch circuit, and an inverter circuit.

[0015] In particular, the subtraction circuit preferably functions as the first input terminal of the comparison circuit, calculating the difference in grayscale between the first image signal input to its first input terminal and the second image signal input to its second input terminal. The comparison circuit preferably functions to compare the grayscale difference input to its first input terminal with a reference value input to its second input terminal, and transmit the comparison result as a first logic signal to the first input terminal of the first flip-flop circuit. The first flip-flop circuit preferably functions to hold the first logic signal transmitted to its first input terminal, and transmit the first logic signal to the first input terminal of the first latch circuit when the potential of the second input terminal of the first flip-flop circuit rises or falls. The first latch circuit preferably has a function of holding a first logic signal transmitted to a first input terminal of the first latch circuit, and a function of transmitting the first logic signal to a control terminal of the first switch and an input terminal of the inverter circuit when a first potential is input to a second input terminal of the first latch circuit. The inverter circuit preferably has a function of generating a second logic signal using the first logic signal and transmitting the second logic signal to the control terminal of the second switch.

[0016] (3) Alternatively, according to one embodiment of the present invention, in the above-described (2), a second flip-flop circuit, a second latch circuit, and a digital-analog conversion circuit may be included.

[0017] In particular, it is preferable that a first wiring be electrically connected to each second input terminal of the first flip-flop circuit and the second flip-flop circuit, and that a second wiring be electrically connected to each second input terminal of the first latch circuit and the second latch circuit. It is also preferable that the second flip-flop circuit has a function of acquiring a first image signal from the first input terminal of the second flip-flop circuit and holding the first image signal, and a function of transmitting the first image signal to the first input terminal of the second latch circuit when the potential of the second input terminal of the second flip-flop circuit rises or falls. It is preferable that the second latch circuit has a function of holding the first image signal transmitted to the first input terminal of the second latch circuit, and a function of transmitting the first image signal to the digital-analog conversion circuit when the first potential is input to the second input terminal of the second latch circuit. It is preferable that the digital-analog conversion circuit has a function of converting the first image signal into an analog potential and outputting the analog potential to the input terminal of the amplifier and the first terminal of the second switch.

[0018] (4) Alternatively, according to one embodiment of the present invention, the pixel circuit according to the above-described (3) may further include a level shifter circuit. In particular, the level shifter circuit preferably has a function of level-shifting a potential corresponding to the first image signal transmitted from the second latch circuit and transmitting the level-shifted potential to a digital-analog conversion circuit.

[0019] (5) Another embodiment of the present invention is a display device including the driver circuit according to any one of (1) to (4) and a pixel circuit, wherein the second terminal of the first switch and the first terminal of the second switch are electrically connected to the pixel circuit.

[0020] (6) Alternatively, in one embodiment of the present invention, in the above-described (5), the pixel circuit may include a first transistor and a second transistor.

[0021] In particular, it is preferable that the first terminal of the first transistor is electrically connected to the second terminal of the first switch and the second terminal of the second switch, and that the second terminal of the first transistor is electrically connected to the gate of the second transistor. Furthermore, it is preferable that the channel formation regions of the first transistor and the second transistor each have a semiconductor layer containing an oxide semiconductor. Furthermore, in a cross-sectional view in the channel width direction, the height of the semiconductor layer of the second transistor is greater than one time the width of the semiconductor layer of the second transistor.

[0022] (7) Alternatively, in one embodiment of the present invention, in the above-described (6), the oxide semiconductor may contain one or more elements selected from indium, zinc, and an element M.

[0023] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

[0024] (8) Another embodiment of the present invention is an electronic device including the display device described in (7) above and a housing.

[0025] As shown in (1) above, by providing the drive circuit with the function of calculating the difference in gradation between the previous and next image data and the function of determining whether the difference in gradation is greater than or equal to a threshold value (reference value) preset by the user, the amplifier can be driven when the difference in gradation is equal to or greater than the threshold value (reference value), and the amplifier can be prevented from being driven when the difference in gradation is less than the threshold value (reference value).In other words, when the difference in gradation between the previous and next image data is small, the amplifier is not driven, thereby reducing the power consumption of the drive circuit.

[0026] The driver circuit can be applied to a display device. Therefore, by using the driver circuit in a display device, the power consumption of the display device or the power consumption of an electronic device including the display device can be reduced.

[0027] According to one embodiment of the present invention, a driver circuit with reduced power consumption can be provided. According to one embodiment of the present invention, a display device including the driver circuit can be provided. According to one embodiment of the present invention, a display device with high image quality can be provided. According to one embodiment of the present invention, a display device with a reduced circuit area can be provided. According to one embodiment of the present invention, a display device with a high driving frequency can be provided. According to one embodiment of the present invention, an electronic device including the display device can be provided. According to one embodiment of the present invention, a novel driver circuit, a novel display device, or a novel electronic device can be provided.

[0028] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above.

[0029] FIG. 1 is a block diagram showing an example of a drive circuit. FIG. 2 is a block diagram showing an example of a display device. FIG. 3 is a perspective schematic diagram showing an example of a display device. FIG. 4 is a circuit diagram showing an example of a circuit included in a drive circuit. FIGS. 5A and 5B are circuit diagrams showing an example of a circuit included in a drive circuit. FIGS. 6A and 6B are block diagrams showing an example of a circuit included in a drive circuit. FIG. 7 is a block diagram showing an example of a circuit included in a drive circuit. FIG. 8 is a timing chart showing an operation example of a drive circuit. FIGS. 9A to 9D are circuit diagrams showing an example of a configuration of a pixel circuit. FIGS. 10A and 10B are circuit diagrams showing an example of a configuration of a pixel circuit. FIGS. 11A and 11B are circuit diagrams showing an example of a configuration of a pixel circuit. FIG. 12 is a circuit diagram showing an example of a configuration of a pixel circuit. FIGS. 13A to 13C are perspective schematic diagrams showing an example of a configuration of a display device. FIG. 14 is a block diagram showing an example of a configuration of a display device. FIG. 15 is a cross-sectional schematic diagram showing an example of a configuration of a display device. FIG. 16A is a schematic plan view showing a configuration example of a transistor, and FIGS. 16B and 16C are schematic cross-sectional views showing a configuration example of a transistor. FIG. 17A is a schematic plan view showing a configuration example of a transistor, and FIGS. 17B and 17C are schematic cross-sectional views showing a configuration example of a transistor. FIGS. 18A to 18C are schematic cross-sectional views showing a configuration example of a part of a display device. FIG. 19 is a schematic cross-sectional view showing a configuration example of a display device. FIG. 20 is a schematic cross-sectional view showing a configuration example of a display device. FIG. 21 is a schematic cross-sectional view showing a configuration example of a display device. FIG. 22A is a schematic plan view showing a configuration example of a transistor, and FIGS. 22B to 22D are schematic cross-sectional views showing an example of a transistor. FIGS. 23A to 23C are schematic cross-sectional views showing an example of a transistor. FIG. 24A is a schematic plan view showing an example of a transistor, and FIGS. 24B to 24D are schematic cross-sectional views showing an example of a transistor. FIG. 25 is a schematic cross-sectional view showing a configuration example of a display device. 26A and 26B are diagrams showing an example of the configuration of a display module, and Fig. 27A to Fig. 27I are perspective views showing an example of an electronic device.

[0030] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Also, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit, and another example of a semiconductor device is an electronic component in which a chip is housed in a package. Also, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0031] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film or a layer).

[0032] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, an inductor, a resistive element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0033] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (for example, inverters, NAND circuits, and NOR circuits), signal conversion circuits (for example, digital-analog conversion circuits, analog-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (for example, power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (for example, circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0034] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0035] Furthermore, for example, it can be expressed as follows: "X, Y, the source (e.g., sometimes referred to as one of the first terminal or the second terminal) and the drain (e.g., sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Or, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in the circuit configuration, it is possible to distinguish between the source and drain of the transistor and determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film or a layer).

[0036] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has both the function of a wiring and the function of an electrode. Therefore, in this specification, the term "electrically connected" also includes such a case where one conductive film has the functions of multiple components.

[0037] In this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0038] In this specification, a "capacitive element" can refer to a circuit element having a capacitance value higher than 0 F, for example. A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be rephrased as a "pair of electrodes," a "pair of conductive regions," a "pair of regions," or a "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0039] However, there are cases where a circuit has an area with unintended capacitance, that is, "parasitic capacitance." Examples of "parasitic capacitance" include an area including different wirings connected via an insulator, and gate capacitance occurring in a transistor. In this specification, unless otherwise specified, the term "capacitive element" is explained as not including "parasitic capacitance."

[0040] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain are sometimes interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and drain" and "the other of the source and drain" are sometimes used. Furthermore, "one of the source and drain" may be referred to as "a first terminal of the transistor" or "a first electrode of the transistor," and "the other of the source and drain" may be referred to as "a second terminal of the transistor" or "a second electrode of the transistor."

[0041] Depending on the structure of the transistor, a back gate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0042] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, the multi-gate structure can provide voltage-current characteristics with a flat slope when operating in the saturation region, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. For example, voltage-current characteristics with a flat slope can be used to realize an ideal current source circuit, an active load with a very high resistance, and the like. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0043] Furthermore, even when a circuit diagram shows a single circuit element, the circuit element may actually include multiple circuit elements. For example, when a circuit diagram shows a single resistor element, this includes two or more resistor elements connected directly in series. Furthermore, two or more resistor elements connected directly in series may be represented as a single resistor element. For example, when a circuit diagram shows a single capacitor element, this includes two or more capacitor elements connected directly in parallel. Furthermore, two or more capacitor elements connected directly in parallel may be represented as a single capacitor element. For example, when a circuit diagram shows a single transistor, this includes two or more transistors connected directly in series with their sources and drains connected together, and their gates connected together. Furthermore, when a circuit diagram shows two or more transistors connected directly in series with their sources and drains connected together, and their gates connected together, this may be represented as a single transistor. For example, when one transistor is shown on a circuit diagram, this includes a case where the first terminals of two or more transistors are directly connected to each other, the second terminals of the respective transistors are directly connected to each other, and the gates of the respective transistors are directly connected to each other. Also, a configuration in which the first terminals of two or more transistors are directly connected to each other, the second terminals of the respective transistors are directly connected to each other, and the gates of the respective transistors are directly connected to each other can sometimes be represented as a single transistor.

[0044] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling a current.

[0045] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which current can flow between the source and drain. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor are considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0047] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal, a wiring, or the like can also be referred to as a node.

[0048] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0049] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0050] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0051] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0052] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0053] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0054] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0055] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". For example, the term "insulating film" can be changed to the term "insulating layer". Furthermore, depending on the situation, the terms "film" and "layer" can be replaced with other terms without using them. For example, the terms "conductive layer" or "conductive film" can be changed to the term "conductor". Furthermore, for example, the terms "insulating layer" or "insulating film" can be changed to the term "insulator".

[0056] Furthermore, the terms "electrode," "wiring," and "terminal" used herein do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0057] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0058] In addition, in this specification, timing charts in the drawings may be used to explain an operation method of a semiconductor device. The timing charts used in the description show ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) shown in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including nodes) in the timing charts may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other may be long. For example, to clearly illustrate the timing chart, two or more overlapping signals may be intentionally shifted.

[0059] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0060] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0061] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0062] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" or "orthogonal" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "substantially perpendicular" or "substantially orthogonal" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0063] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0064] In addition, the content described in one embodiment can be applied to, combined with, or replaced with at least one of the other content described in that embodiment and the content described in one or more other embodiments.

[0065] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0066] Furthermore, a figure (part or all) described in one embodiment can be combined with another part of that figure, another figure (part or all) described in that embodiment, and at least one figure (part or all) described in one or more other embodiments to form even more figures.

[0067] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0068] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0069] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0070] Embodiment 1 In this embodiment, a driver circuit according to one embodiment of the present invention and a display device including the driver circuit will be described.

[0071] 2 is a block diagram illustrating a configuration example of a display device including a driver circuit according to one embodiment of the present invention. The display device DSP includes, for example, a pixel array PXA, a driver circuit GD, and a driver circuit SD.

[0072] The pixel array PXA, the drive circuit GD, and the drive circuit SD may be provided on the same support. Some or all of the circuits listed above may be formed directly on the support, or may be mounted on the support using a COG (chip on glass) method or the like. Some or all of the circuits listed above may be mounted on a flexible printed circuit (FPC) electrically connected to the support using a COF (chip on film) method or the like.

[0073] As an example, the pixel array PXA includes a plurality of pixel circuits PX. The plurality of pixel circuits PX are arranged in an array in the pixel array PXA. For example, the pixel array PXA includes a plurality of pixel circuits PX arranged in any one of a matrix array, a stripe array, an S-stripe array, a delta array, a Bayer array, a Pentile array, and the like. In FIG. 2 , the pixel circuit PX located in the i-th row and j-th column (i is an integer equal to or greater than 1, and j is an integer equal to or greater than 1) among the plurality of pixel circuits PX is represented as pixel circuit PX[i, j]. The pixel array PXA may include only one pixel circuit PX instead of a plurality of pixel circuits PX.

[0074] The pixel circuits PX have the function of, for example, acquiring an image signal transmitted from a drive circuit SD (described later) and emitting light of an intensity corresponding to the image signal. Note that one pixel circuit PX may include two or more sub-pixel circuits. For example, the number of sub-pixel circuits included in one pixel circuit PX and the colors of their emitted light may be determined so that the light emitted by the sub-pixel circuits combines to produce white light. For example, by setting the emission colors of the sub-pixel circuits included in the pixel circuit PX to red (R), green (G), and blue (B), the pixel circuit PX as a whole can be configured as a circuit capable of emitting white light.

[0075] The screen resolution of the display device DSP is determined according to the number of pixel circuits PX included in the pixel array PXA. For example, if the screen resolution of the display device DSP is 8K4K, the number of pixel circuits PX included in the pixel array PXA is 7680 x 4320. Furthermore, if the pixel circuit PX includes, for example, three sub-pixel circuits of red (R), green (G), and blue (B), the total number of such sub-pixel circuits included in the pixel array PXA is 7680 x 4320 x 3. The screen resolution of the display device DSP may be SD (720 x 480 pixel circuits PX), HD (1280 x 720 pixel circuits PX), FHD (1920 x 1080 pixel circuits PX), or 4K2K (3840 x 2160 pixel circuits PX). Furthermore, the screen resolution of the display device DSP is not limited to the above, and may be determined arbitrarily at the design stage of the display device DSP.

[0076] The diagonal size of the display area (for example, the pixel array PXA) of the display device DSP can be determined depending on the electronic device equipped with the display device DSP. For example, in applications involving large displays such as television devices, the diagonal size of the display area can be 20 inches or more, 30 inches or more, 60 inches or more, or 100 inches or more. In applications involving small to medium-sized displays such as tablet information terminals or mobile information terminals, the diagonal size of the display area can be 3 inches or more and 13 inches or less. In applications involving small displays such as XR devices and wearable information terminals, the diagonal size can be 3 inches or less, 1.5 inches or less, or 1 inch or less, for example.

[0077] The resolution of the display area of ​​the display device DSP (sometimes referred to as pixel density) is determined by the screen resolution and diagonal size described above. For example, when the display device DSP is used in a large display, the resolution of the display area of ​​the display device DSP is preferably, for example, 50 ppi or more, more preferably 100 ppi or more, and even more preferably 150 ppi or more. When the display device DSP is used in a small or medium-sized display, the resolution of the display area of ​​the display device DSP is preferably, for example, 200 ppi or more, more preferably 400 ppi or more, and even more preferably 800 ppi or more. When the display device DSP is used in a small display, the resolution of the display area of ​​the display device DSP is preferably, for example, 1000 ppi or more, more preferably 2000 ppi or more, and even more preferably 4000 ppi or more.

[0078] Furthermore, the screen ratio (aspect ratio) of the display area (for example, the pixel array PXA) of the display device DSP is not particularly limited. For example, the display area can accommodate various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, and 32:9.

[0079] The drive circuit GD functions as, for example, a gate driver circuit for selecting a pixel circuit PX included in the pixel array PXA to which an image signal is to be written.

[0080] The drive circuit SD functions as, for example, a source driver circuit for transmitting image signals to the pixel circuits PX included in the pixel array PXA.

[0081] The pixel circuit PX[i,j] is electrically connected to the drive circuit GD via a wiring GLS[i], for example. The pixel circuit PX[i,j] is also electrically connected to the drive circuit SD via a wiring SLS[j], for example.

[0082] As an example, the wiring GLS[i] functions as a wiring (sometimes referred to as a gate line in this specification) for transmitting a selection signal from the driving circuit GD to the pixel circuit PX[i,j] to drive the pixel circuit PX[i,j].

[0083] As an example, the wiring SLS[j] functions as a wiring (sometimes referred to as a source line, data line, etc. in this specification) for transmitting an image signal from the driving circuit SD to the pixel circuit PX[i,j] to display an image on the pixel circuit PX[i,j].

[0084] Note that the wiring GLS[i] may be a single wiring or a wiring group including multiple wirings. Similarly, the wiring SLS[j] may be a single wiring or a wiring group including multiple wirings.

[0085] The display device DSP in Fig. 2 may have the configuration of the display device DSPA shown in Fig. 3. The display device DSPA in Fig. 3 has a configuration in which a pixel array PXA is divided into a plurality of display areas PXDM, and drive circuits GD and drive circuits SD are provided in the same number as the number of display areas PXDM. In particular, in Fig. 3, a circuit area CIA is provided as an area having a plurality of drive circuits GD and a plurality of drive circuits SD, and the pixel array PXA is provided so as to overlap with the circuit area CIA.

[0086] Furthermore, the circuit area CIA has the same number of drive circuit areas DRDM as the number of display areas PXDM, and each drive circuit area DRDM includes one drive circuit GD and one drive circuit SD.

[0087] Furthermore, one display region PXDM corresponds to one drive circuit region DRDM, and the pixel circuits PX included in that display region PXDM are connected to the drive circuit GD included in that drive circuit region DRDM via wiring GLS, and are also connected to the drive circuit SD via wiring SLS. Furthermore, since the display region PXDM is located above the drive circuit region DRDM, it can be said that each of the wiring SLS and the wiring GLS has a component in the height direction.

[0088] 3 is configured such that the driver circuits GD and SD are connected to each of the display regions PXDM obtained by dividing the pixel array PXA into a plurality of regions, thereby reducing the number of pixel circuits PX handled by each of the driver circuits GD and SD. Furthermore, because the driver circuits GD and SD are disposed below the pixel array PXA, the lengths of the wiring SLS and wiring GLS can be shortened. This reduces the attenuation or delay of signals transmitted from the driver circuits GD or SD to the pixel circuits PX.

[0089] 3, the driver circuit GD and the driver circuit SD are arranged below the pixel array PXA, so that the frame area of ​​the display device DSPA can be reduced. As a result, when the display device DSPA is applied to an electronic device, the housing of the electronic device can be made smaller, and therefore the electronic device can be made more compact.

[0090] <Configuration Example of Drive Circuit SD> Next, a configuration example of the drive circuit SD included in the display device DSP or the display device DSPA will be described.

[0091] 1 is a block diagram illustrating a configuration example of a driver circuit SD according to one embodiment of the present invention. Note that the driver circuit SD illustrated in FIG. 1 illustrates a configuration example in which a plurality of pixel circuits PX are arranged in N columns (N is an integer of 1 or more) in a pixel array PXA.

[0092] In FIG. 1, the driver circuit SD includes, as an example, a shift register SR, logic circuits LMP[1] to LMP[N], a control circuit CTR, a memory circuit MEM, flip-flop circuits FFA[1] to FFA[N], latch circuits LTA[1] to LTA[N], level shifter circuits LS[1] to LS[N], a digital-to-analog conversion circuit DAC, amplifiers AP[1] to AP[N], switches SWA[1] to SWA[N], and switches SWB[1] to SWB[N].

[0093] Moreover, the shift register SR has, as an example, a plurality of output terminals.

[0094] Each of the logic circuits LMP[1] to LMP[N] has, for example, a first input terminal, a second input terminal, and an output terminal.

[0095] Further, the control circuit CTR has, as an example, input terminals DI1, DI2, input terminals ET[1] to ET[N], output terminals STA[1] to STA[N], and output terminals STB[1] to STB[N].

[0096] The memory circuit MEM also has, for example, an input terminal MI and an output terminal MO.

[0097] Furthermore, each of the flip-flop circuits FFA[1] to FFA[N] has, for example, an input terminal DA, an output terminal QA, and a clock input terminal (which may be referred to as an input terminal, a strobe input terminal, etc.). In this specification and the like, in order to distinguish between the input terminal DA and the clock input terminal, the input terminal DA may be referred to as a first input terminal, and the clock input terminal may be referred to as a second input terminal.

[0098] As an example, each of the flip-flop circuits FFA[1] to FFA[N] has a function of holding a potential corresponding to a signal input to a first input terminal, and a function of outputting the held potential as a signal from an output terminal when the potential input to a second input terminal rises or falls.

[0099] Furthermore, each of the latch circuits LTA[1] to LTA[N] has, for example, an input terminal, an output terminal, and an enable input terminal (which may also be referred to as an input terminal, a clock input terminal, etc.). Furthermore, in this specification and the like, in order to distinguish between the input terminal and the enable input terminal, the input terminal may be referred to as a first input terminal, and the enable input terminal may be referred to as a second input terminal.

[0100] As an example, each of the latch circuits LTA[1] to LTA[N] has a function of holding a potential corresponding to a signal input to a first input terminal, and a function of outputting the held potential as a signal from an output terminal when a predetermined potential is input to a second input terminal.

[0101] Each of the level shifter circuits LS[1] to LS[N] has, for example, an input terminal and an output terminal.

[0102] The digital-to-analog conversion circuit DAC includes, for example, a resistor string circuit RSTR and selector circuits PTL[1] to PTL[N], each of which includes an input terminal, an output terminal, and a power supply terminal.

[0103] It should be noted that the digital-analog conversion circuit DAC can be said to have, for example, first through N-th input terminals and first through N-th output terminals. In this case, the input terminal of the selector circuit PTL[1] can be the first input terminal of the digital-analog conversion circuit DAC, and the output terminal of the selector circuit PTL[1] can be the first output terminal of the digital-analog conversion circuit DAC. Similarly, the input terminal of the selector circuit PTL[N] can be the N-th input terminal of the digital-analog conversion circuit DAC, and the output terminal of the selector circuit PTL[N] can be the N-th output terminal of the digital-analog conversion circuit DAC.

[0104] 1 (where j is an integer between 1 and N), a first input terminal of a logic circuit LMP[j] is connected to the jth output terminal of the shift register SR, a second input terminal of the logic circuit LMP[j] is connected to a wiring CKL1, and an output terminal of the logic circuit LMP[j] is connected to a wiring CKL2[j]. The wiring CKL2[j] is also connected to an input terminal ET[j] of a control circuit CTR and a clock input terminal of a flip-flop circuit FFA[j].

[0105] The input terminal DI1 of the control circuit CTR is connected to the wiring DL, the input terminal DI2 of the control circuit CTR is connected to the output terminal MO of the memory circuit MEM, the output terminal STA[j] of the control circuit CTR is connected to the control terminal of the switch SWA[j], and the output terminal STB[j] of the control circuit CTR is connected to the control terminal of the switch SWB[j].

[0106] An input terminal MI of the memory circuit MEM is connected to a wiring DL.

[0107] The input terminal DA of the flip-flop circuit FFA[j] is connected to the wiring DL, the output terminal QA of the flip-flop circuit FFA[j] is connected to the first input terminal of the latch circuit LTA[j], the output terminal of the latch circuit LTA[j] is connected to the input terminal of the level shifter circuit LS[j], and the second input terminal of the latch circuit LTA[j] is connected to the wiring LL1.

[0108] The output terminal of the level shifter circuit LS[j] is connected to the jth input terminal of the digital-to-analog conversion circuit DAC, and the jth output terminal of the digital-to-analog conversion circuit DAC is connected to the input terminal of the amplifier AP[j] and the first terminal of the switch SWB[j].

[0109] Specifically, the output terminal of the level shifter circuit LS[j] is connected to the input terminal of the selector circuit PTL[j] via the wiring SEL[j], and the output terminal of the selector circuit PTL[j] is connected to the input terminal of the amplifier AP[j] and the first terminal of the switch SWB[j]. In other words, the input terminal of the selector circuit PTL[j] can be the j-th input terminal of the digital-analog conversion circuit DAC, and the output terminal of the selector circuit PTL[j] can be the j-th output terminal of the digital-analog conversion circuit DAC.

[0110] The wiring SEL[j] functions as a wiring for transmitting an image signal output from the level shifter circuit LS[j] to the digital-analog conversion circuit DAC. In FIG. 1, the wiring SEL[1] and the wiring SEL[N] are selectively illustrated as examples of the wiring SEL[j].

[0111] Furthermore, the power supply terminal of the selector circuit PTL[j] is connected to the resistor string circuit RSTR.

[0112] The output terminal of the amplifier AP[j] is connected to the first terminal of the switch SWA[j], and the second terminal of the switch SWA[j] is connected to the second terminal of the switch SWB[j] and the line SL[j].

[0113] As will be described in detail later, the amplifier AP[j] functions as an analog buffer that amplifies an image signal having an analog potential, for example. The amplified image signal having an analog potential is transmitted to the wiring SL[j].

[0114] Furthermore, the amplifier AP[j] is controlled by setting the switch SWA[j] to one of the on and off states and the switch SWB[j] to the other of the on and off states. For example, when the difference in gradation between the previous and next image data is large, turning the switch SWA[j] on and the switch SWB[j] off establishes electrical continuity between the output terminal of the amplifier AP[j] and the wiring SL[j], allowing the amplifier AP[j] to quickly transmit an image signal to the wiring SL[j]. On the other hand, when the difference in gradation between the previous and next image data is small, turning the switch SWA[j] off and the switch SWB[j] on allows the output of the output terminal of the amplifier AP[j] to have high impedance, thereby preventing electrical continuity between the output terminal of the amplifier AP[j] and the wiring SL[j]. This stops the amplifier AP[j], allowing the image signal to be transmitted from the digital-to-analog conversion circuit DAC to the wiring SL[j] without amplification by the amplifier AP[j] (via the switch SWB[j]).

[0115] For example, the shift register SR has a function of selecting one of a plurality of output terminals and outputting a high-level potential from the selected output terminal each time a rising or falling edge of a clock signal is input. For example, if the shift register SR has first to Nth output terminals, when the first rising or falling edge of the clock signal is input to the shift register SR, the shift register SR outputs a high-level potential from the first output terminal and a low-level potential from the second to Nth output terminals. When the second rising or falling edge of the clock signal is input to the shift register SR, the shift register SR outputs a high-level potential from the second output terminal and a low-level potential from the first and third to Nth output terminals. When the jth rising or falling edge of the clock signal is input to the shift register SR, the shift register SR outputs a high-level potential from the jth output terminal and a low-level potential from the first to Nth output terminals excluding the jth output terminal.

[0116] The above operation of the shift register SR is an example, and depending on the circuit configuration of the drive circuit SD, the high level potential and the low level potential of the shift register SR may be interchanged in the above operation.

[0117] 1, for example, each of the logic circuits LMP[1] to LMP[N] is an AND circuit. For example, the logic circuit LMP[j] has a function of performing a logical AND operation on a logic corresponding to a potential transmitted from a wiring CKL1 and a logic of a signal transmitted from the j-th output terminal of the shift register SR, and outputting the operation result to a wiring CKL2[j].

[0118] For example, the wiring CKL1 functions as a wiring that applies a variable potential. The variable potential can be a clock potential (sometimes referred to as a clock signal) that transitions from a low-level potential to a high-level potential and from a high-level potential to a low-level potential.

[0119] As an example of the operation of the logic circuit LMP[j], when a high-level potential is output from the j-th output terminal of the shift register SR and input to the first input terminal of the logic circuit LMP[j], and a high-level potential is input from the wiring CKL1 to the second input terminal of the logic circuit LMP[j], the logic circuit LMP[j] outputs a high-level potential from its output terminal to the wiring CKL2[j]. Note that when a low-level potential is input to one or both of the first and second input terminals of the logic circuit LMP[j], the logic circuit LMP[j] outputs a low-level potential from its output terminal to the wiring CKL2[j].

[0120] The high-level or low-level potential output from the output terminal of the logic circuit LMP[j] to the wiring CKL2[j] functions as an enable signal input to each of the flip-flop circuit FFA[j] and the flip-flop circuit FFB[j] described later.

[0121] For example, the wiring DL functions as a wiring for transmitting an image signal. The image signal is transmitted to an input terminal DI1 of the control circuit CTR, an input terminal MI of the memory circuit MEM, and an input terminal DA of each of the flip-flop circuits FFA[1] to FFA[N]. Note that the image signal is a digital signal.

[0122] As an example, the flip-flop circuit FFA[j] has a function of holding image data corresponding to an image signal by inputting a rising or falling edge of a clock signal to the clock input terminal while the image signal is being input to the input terminal DA. Furthermore, once the flip-flop circuit FFA[j] has held the image data, it always outputs the image signal to the output terminal QA until a rising or falling edge of the clock signal is again input to the clock input terminal. Note that the image signal output from the output terminal QA of the flip-flop circuit FFA[j] is a digital signal.

[0123] For example, the latch circuit LTA[j] has a function of holding image data corresponding to an image signal by inputting an enable signal to the enable input terminal while the image signal is being input to the input terminal. Once the latch circuit LTA[j] has held the image data, it continues to output the image signal to the output terminal until the enable signal changes to a disable signal. The image signal output from the output terminal of the latch circuit LTA[j] is a digital signal.

[0124] For example, the level shifter circuit LS[j] has a function of shifting a potential corresponding to an image signal input to an input terminal to a potential at least at a level that can be handled by the digital-analog conversion circuit DAC. Note that if the potential corresponding to the image signal output from the output terminal of the latch circuit LTA[j] is at a level that can be handled by the digital-analog conversion circuit DAC, the driver circuit SD does not need to be provided with the level shifter circuit LS[j]. In other words, in this case, the output terminal of the latch circuit LTA[j] may be electrically connected directly to the wiring SEL[j].

[0125] As an example, the digital-to-analog conversion circuit DAC has the function of converting a digital image signal sent to the wiring SEL[j] into an analog potential and sending it to the input terminal of the amplifier AP[j] and the switch SWB[j].

[0126] FIG. 4 shows an example of the circuit configuration of a digital-analog conversion circuit DAC. The digital-analog conversion circuit DAC shown in FIG. 4 is configured to convert a 9-bit digital signal (image signal) into an analog potential. Specifically, FIG. 4 shows, as an example, a resistor string circuit RSTR that generates a 9-bit potential and a selector circuit PTL[j] that selects and outputs one of the 9-bit potentials. In addition, FIG. 4 also shows an amplifier AP[j], a switch SWA[j], a switch SWB[j], and a wiring SL[j] to clarify the electrical connections with the digital-analog conversion circuit DAC.

[0127] 4, the resolution of the digital-analog conversion circuit DAC is 9 bits, so the wiring SEL[j] is treated as a wiring group having wirings for 9 bits. In FIG. 4, the wiring SEL[j] is treated as a wiring group having wirings SELa_0 to SELa_8.

[0128] The signal flowing through the wiring SELa_0 is a signal corresponding to the 0th bit of digital data, and the signal flowing through the wiring SELa_8 is a signal corresponding to the 8th bit of digital data.

[0129] The selector circuit PTL[j] in Fig. 4 is a multiplexer with a tree structure of pass transistor logic. For example, in the circuit configuration of a multiplexer with a tree structure of pass transistor logic, the number of p-channel transistors and n-channel transistors required to select and output one of H bits of potential (H is an integer of 1 or more) is Σ2 （ｈ−１） (p-channel transistor and n-channel transistor combined, Σ2 ｈ (Note: Σ2 （ｈ−１） is the integer h from 1 to H. （ｈ−１） This shows the sum of the above numbers.

[0130] Specifically, in the case of a 1-bit multiplexer, one p-channel transistor and one n-channel transistor are required to select and output one potential of one bit, and in the case of a 3-bit multiplexer, two p-channel transistors and two n-channel transistors are required to select and output one potential of three bits. ０ +2 １ +2 ２ The selector circuit PTL[j] in FIG. 4 is a 9-bit multiplexer that selects and outputs one of the 9-bit potentials. Therefore, the number of p-channel transistors and n-channel transistors is 2. ０ +2 １ +2 ２ +2 ３ +2 ４ +2５ +2 ６ +2 ７ +2 ８ = 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 + 256 = 511. Note that the selector circuit PTL[j] in FIG. 4 shows some, but not all, of the transistors.

[0131] The selector circuit PTL[j] in FIG. 4 also has nine inverters for controlling the on and off states of the above-mentioned transistors.

[0132] In addition, in a multiplexer having a tree structure of H-bit pass transistor logic, the number of transistors arranged in the stage of the H-h-th bit among the H bits is 2 ｈ For example, in the case of a multiplexer with pass transistors for H=9 bits, there are two transistors arranged at the 9-1=8th bit (when h=1). One of the two transistors is a p-channel transistor, and the other is an n-channel transistor. The gates of the p-channel transistor and the n-channel transistor are connected to wiring SELa_8, which transmits the 8th bit of digital data, via the first inverter.

[0133] For example, in the case of a multiplexer with pass transistors for H=9 bits, there are 512 transistors arranged at the 0th bit (when h=9) (H-h=9-9=0th bit). Of these 512 transistors, 256 are p-channel transistors, and the remaining 256 are n-channel transistors. The gates of 128 of the 256 p-channel transistors and 128 of the 256 n-channel transistors are connected to wiring SELa_0, which transmits a signal corresponding to the 0th bit of digital data. The gates of the remaining 128 of the 256 p-channel transistors and 128 of the 256 n-channel transistors are connected to wiring SELa_0 via the 9th inverter.

[0134] As an example, the resistor string circuit RSTR has two terminals for outputting the 9-bit potential generated by the circuit itself. ９ The output terminals OT[0] to OT

[511] are 512 output terminals. Each of the output terminals OT[0] to OT

[511] is connected to one of the sources or drains of the 512 zero-bit transistors in a one-to-one relationship.

[0135] 4, the on / off state of each of the 511 p-channel transistors and the 511 n-channel transistors included in the selector circuit PTL[j] is determined by the potentials of the 9-bit image signal transmitted to the wirings SELa_0 to SELa_8. This uniquely determines a path of conduction between any one of the output terminals OT[0] to OT

[511] of the resistor string circuit RSTR and the input terminal of the amplifier AP[j]. That is, one of the 9-bit potentials generated by the resistor string circuit RSTR is selected in accordance with the potentials of the 9-bit image signal and input to the input terminal of the amplifier AP[j]. This converts the 9-bit image signal flowing through the wiring SEL[j] into an analog potential.

[0136] Next, a configuration example of the resistor string circuit RSTR will be described. Fig. 5A shows an example of a circuit configuration that can be applied to the resistor string circuit RSTR shown in Figs.

[0137] 5A includes a resistor string in which resistor elements Ra[1] to Ra

[511] are connected in series, and a resistor string in which resistor elements Rb[1] to Rb

[511] are connected in series. The resistor string circuit RSTR further includes amplifiers GAP[0] to GAP

[511] that function as gamma amplifiers.

[0138] In the resistor string of resistor elements Ra[1] to Ra

[511] , one end of resistor element Ra[1] is connected to the wiring VSE and the input terminal of amplifier GAP[0], and one end of resistor element Ra

[511] is connected to the wiring VDE and the input terminal of amplifier GAP

[511] . In addition, the input terminal of amplifier GAP[M-1] is connected to the region where resistor element Ra[M-1] (M is an integer between 2 and 511) and resistor element Ra[M] are connected to each other.

[0139] In the resistor string of resistor elements Rb[1] to Rb

[511] , one end of resistor element Rb[1] is connected to the output terminal OT[0] and the output terminal of the amplifier GAP[0], and one end of resistor element Rb

[511] is connected to the output terminal OT

[511] and the output terminal of the amplifier GAP

[511] . In addition, the connection point between resistor element Rb[M-1] and resistor element Rb[M] is connected to the output terminal OT[M-1] and the output terminal of the amplifier GAP[M-1].

[0140] In the resistor string circuit RSTR, if the amplifiers GAP[0] to GAP

[511] and the resistor elements Rb[1] to Rb

[511] are not provided, that is, if the 9-bit potential is generated by voltage division only of the resistor string of the resistor elements Ra[1] to Ra

[511] , when an image signal is transmitted to the wiring SL[j] without driving the amplifier AP[j], a voltage drop may occur in some or all of the resistor elements Ra[1] to Ra

[511] due to charging and discharging of the wiring SL[j], and the charging and discharging may be slowed down. In order to prevent a voltage drop in the resistor elements Ra[1] to Ra

[511] , it is preferable to provide the resistor string circuit RSTR with amplifiers GAP[0] to GAP

[511] and resistor elements Rb[1] to Rb

[511] , as shown in FIG. 5A, to stabilize the voltages of the resistor string of the resistor elements Ra[1] to Ra

[511] and the resistor string of the resistor elements Rb[1] to Rb

[511] .

[0141] Although the resistor string circuit RSTR in FIG. 5A has 512 amplifier GAPs, the number of amplifier GAPs may be reduced if the purpose is to stabilize the voltages of the resistor strings of resistor elements Ra[1] to Ra

[511] and the resistor strings of resistor elements Rb[1] to Rb

[511] . For example, as shown in FIG. 5B, the resistor string circuit RSTR may include 33 amplifier GAPs, i.e., amplifier GAPA[1] to amplifier GAPA

[33] . In FIG. 5B, amplifier GAPA[1] may be amplifier GAP[0] in FIG. 5A, amplifier GAPA[2] ​​may be amplifier GAP

[16] (not shown) in FIG. 5A, amplifier GAPA

[32] may be amplifier GAP

[496] (not shown) in FIG. 5A, and amplifier GAPA

[33] may be amplifier GAP

[511] in FIG. 5A. As shown in FIG. 5B, by reducing the amplifier GAP (amplifier GAPA) of the resistor string circuit RSTR, the power consumption in the resistor string circuit RSTR can be reduced.

[0142] Consider a comparison of the number of amplifiers GAPA included in the resistor string circuit RSTR of FIG. 5B and the number of amplifiers AP included in the drive circuit SD of FIG. 1. While the number of amplifiers GAPA included in the resistor string circuit RSTR of FIG. 5B is 33, the number of amplifiers GAP included in the drive circuit SD is equal to the number of columns in the pixel array PXA. For example, if the screen resolution is HD standard (1280 x 720), the number of amplifiers GAP included in the drive circuit SD is 1280. Furthermore, if the pixel circuit includes, for example, three sub-pixel circuits for red, green, and blue, 1280 x 3 amplifiers GAP are required. As described above, when the difference in gradation between image data before and after transmission to the source line is small, the image signal can be amplified with only 33 amplifiers GAPA included in the resistor string circuit RSTR, thereby significantly reducing power consumption by the amplifiers AP.

[0143] For example, the control circuit CTR has a function of calculating the difference in grayscale of image data at two coordinates in different rows in the jth column of the pixel array PXA, determining whether the difference in grayscale is greater than or equal to a predetermined amount (sometimes referred to as a threshold value, reference value, etc. in this specification) or less than the predetermined amount, and outputting the comparison result as a first logic signal to the output terminal STA[j]. Furthermore, for example, the control circuit CTR has a function of generating a second logic signal in which the logic of the first logic signal is inverted, and outputting the second logic signal to the output terminal STB[j]. As a result, the first logic signal is input to the control terminal of the switch SWA[j], and the second logic signal is input to the control terminal of the switch SWB[j].

[0144] Here, the image data at two coordinates in different rows may be, for example, image data at row i and column j (sometimes referred to as the first coordinate) input from the wiring DL to the input terminal DI1, and image data at row k and column j (sometimes referred to as the second coordinate, where k is an integer greater than or equal to 1 and not i) read from the memory circuit MEM and input to the input terminal DI2. In the description of the control circuit CTR, a signal corresponding to the image data at the first coordinate is referred to as the first image signal, and a signal corresponding to the image data at the second coordinate is referred to as the second image signal. The first image signal transmitted to the wiring DL and the second image signal read from the memory circuit MEM may each be a digital signal.

[0145] For example, the memory circuit MEM has a function of acquiring a first image signal input to an input terminal MI from a wiring DL and storing image data of a first coordinate, and also has a function of reading out the stored image data of a second coordinate and outputting it as a second image signal to an output terminal MO.

[0146] Here, an example of a specific circuit configuration of the control circuit CTR will be described.

[0147] Fig. 6A is a block diagram showing an example of the control circuit CTR of the driver circuit SD in Fig. 1. As an example, the control circuit CTR includes a circuit DFR, flip-flop circuits FFB[1] to FFB[N], latch circuits LTB[1] to LTB[N], and inverter circuits NT[1] to NT[N].

[0148] For example, the circuit DFR has a first input terminal, a second input terminal, and an output terminal. Each of the flip-flop circuits FFB[1] to FFB[N] has an input terminal DB, an output terminal QB, and a clock input terminal. Each of the latch circuits LTB[1] to LTB[N] has an input terminal, an output terminal, and an enable input terminal.

[0149] 6A, the first input terminal of the circuit DFR is connected to the input terminal DI1 of the control circuit CTR, the second input terminal of the circuit DFR is electrically connected to the input terminal DI2 of the control circuit CTR, and the output terminal of the circuit DFR is connected to the input terminal DB of the flip-flop circuit FFB[j]. The output terminal QB of the flip-flop circuit FFB[j] is connected to the input terminal of the latch circuit LTB[j], and the clock input terminal of the flip-flop circuit FFB[j] is connected to the input terminal ET[j] of the control circuit CTR. As described above, the input terminal ET[j] of the control circuit CTR is connected to the wiring CKL2[j].

[0150] The enable input terminal of the latch circuit LTB[j] is connected to the line LL2. The output terminal of the latch circuit LTB[j] is connected to the output terminal STA[j] of the control circuit CTR and the output terminal of the inverter circuit NT[j]. The output terminal of the inverter circuit NT[j] is connected to the output terminal STB[j] of the control circuit CTR.

[0151] As an example, the circuit DFR has a function of calculating the difference in gradation between a first image signal input from the input terminal DI1 of the control circuit CTR and a second image signal read out from the memory circuit MEM and input to the input terminal DI2, and a function of determining whether the difference in gradation is greater than or equal to a threshold value (reference value) or less than the threshold value (reference value) (by comparing the magnitude of the difference in gradation with the threshold value (reference value)), and generating the comparison result as a first logic signal.

[0152] Next, an example of a circuit configuration applicable to the circuit DFR will be described. The circuit DFR shown in Figure 7 is an example of a circuit configuration applicable to the circuit DFR of Figure 6A, and the circuit DFR has a subtraction circuit DIF and a comparison circuit COMP. In order to clarify the electrical connections of the circuit DFR, Figure 7 also shows input terminals DI1 and DI2 of the control circuit CTR and a flip-flop circuit FFB.

[0153] A first input terminal of the subtraction circuit DIF is connected to an input terminal DI1 of the control circuit CTR, a second input terminal of the subtraction circuit DIF is connected to an input terminal DI2 of the control circuit CTR, and an output terminal of the subtraction circuit DIF is connected to a first input terminal of the comparison circuit COMP, whose output terminal is also connected to an input terminal DB of the flip-flop circuit FFB.

[0154] The digital signal Sth is input to the second input terminal of the comparator circuit COMP as a threshold value (reference value). As mentioned above, the threshold value (reference value) can be set in advance by the user or can be determined during the design stage of the control circuit CTR.

[0155] As an example, the subtraction circuit DIF has the function of calculating the difference in gradation between the first image signal input from the input terminal DI1 and the second image signal input from the input terminal DI2, and outputting the result of this calculation as an absolute value to the output terminal.

[0156] The comparator circuit COMP compares the absolute value (difference in gradation) of the calculation result of the subtractor circuit DIF, which is input to its first input terminal, with a value corresponding to the digital signal Sth, which is input to its second input terminal, determines whether the difference in gradation is equal to or greater than a threshold value (reference value) or less than the threshold value (reference value), and outputs a first logic signal. For example, if the difference in gradation is less than the threshold value (reference value), the first logic signal is output as a low-level potential, and if the difference in gradation is equal to or greater than the threshold value (reference value), the first logic signal is output as a high-level potential. The first logic signal is also input to the input terminal DB of the flip-flop circuit FFB.

[0157] Since the image signals are input as digital signals to the input terminals DI1 and DI2, it is preferable that the subtraction circuit DIF be a circuit that performs digital calculations rather than analog calculations. In other words, in this case, since analog-to-digital conversion is not required, the control circuit CTR can be configured without an analog-to-digital conversion circuit. This reduces the power consumption of the control circuit CTR. Furthermore, since the output signal of the comparison circuit COMP is also a digital signal, it is preferable that the comparison circuit COMP is also a digital circuit.

[0158] On the other hand, since analog circuits can sometimes reduce the circuit area compared to digital circuits, the circuit DFR may be configured as an analog circuit. In this case, the subtraction circuit DIF may convert the image signals input to the input terminals DI1 and DI2 into analog potentials and calculate the difference between the analog potentials using a differential amplifier circuit or the like. The absolute value of the difference can be calculated using an absolute value circuit using a differential amplifier circuit or the like. At this time, the subtraction circuit DIF outputs an analog potential as the difference in gradation. Furthermore, since the digital signal Sth is input to the second input terminal of the comparison circuit COMP, it is preferable that the digital signal Sth be subjected to digital-to-analog conversion. This allows the comparison circuit COMP to be an analog circuit.

[0159] As an example, the flip-flop circuit FFB[j] has a function of holding the data of the first logic signal by inputting a rising or falling edge of a clock signal from the input terminal ET[j] of the control circuit CTR to the clock input terminal while the first logic signal is being input to the input terminal DB. Furthermore, once the flip-flop circuit FFB[j] has held the data, it always outputs the data to the output terminal QB until a rising or falling edge of a clock signal is again input from the input terminal ET[j] of the control circuit CTR to the clock input terminal. The data signal output from the output terminal QB of the flip-flop circuit FFB[j] is a digital signal, which is also referred to as the first logic signal.

[0160] As an example, the latch circuit LTB[j] has a function of holding data corresponding to the first logic signal by inputting an enable signal from the wiring LL2 to the enable input terminal while the first logic signal is being input to the input terminal. Once the latch circuit LTB[j] has held the data, it always outputs the first logic signal to the output terminal until the enable signal from the wiring LL2 changes to a disable signal. The first logic signal output from the output terminal QB of the latch circuit LTB[j] is a digital signal.

[0161] Note that the latch circuits LTB[1] to LTB[N] preferably operate in synchronization with the latch circuits LTA[1] to LTA[N]. Therefore, it is preferable that the wiring LL2 connected to the enable input terminals of the latch circuits LTB[1] to LTB[N] is connected to the wiring LL1 connected to the enable input terminals of the latch circuits LTA[1] to LTA[N]. Note that the wiring LL2 and the wiring LI1 may be the same wiring.

[0162] The first logic signal output from the output terminal QB of the latch circuit LTB[j] is output to the output terminal STA[j] of the control circuit CTR. The first logic signal output from the output terminal QB of the latch circuit LTB[j] is converted by the inverter circuit NT[j] into a second logic signal whose logic is inverted, and is output to the output terminal STB[j] of the control circuit CTR.

[0163] In the block diagram of Fig. 6A, the input terminal MI of the memory circuit MEM is connected to the wiring DL, but the connection configuration between the control circuit CTR and the memory circuit MEM may be as shown in the block diagram of Fig. 6B. In the block diagram of Fig. 6B, the control circuit CTR has an output terminal DO, and the wiring DL is connected to the input terminal MI of the memory circuit MEM via the input terminal DI1 and the output terminal DO. In other words, the wiring DL may be directly connected to the input terminal MI of the memory circuit MEM as shown in Fig. 6A, or may be connected to the input terminal MI of the memory circuit MEM via the control circuit CTR as shown in Fig. 6B.

[0164] <Example of Operation of Drive Circuit SD> Next, an example of operation of the drive circuit SD will be described.

[0165] Fig. 8 is a timing chart showing an example of operation of the driver circuit SD in Fig. 1. The timing chart shown in Fig. 8 shows changes in potentials of the wiring CKL1, the wiring CKL2[1], the wiring CKL2[2], the wiring CKL2[N], the wiring LL1 (wiring LL2), the output terminal STA[1], the output terminal STB[1], the output terminal STA[2], the output terminal STB[2], the output terminal STA[N], and the output terminal STB[N] before time T01, from time T01 to time T08, and after time T08, respectively.

[0166] 8 also shows image data transmitted to the wiring DL and the terminal DI2 at times T01 to T08. In FIG. 8, as an example, image data D[i,1] to D[i,N] to be written to the i-th row of the pixel array PXA are sequentially transmitted to the wiring DL, and image data D[k,1] to D[k,N] are transmitted from the memory circuit MEM to the terminal DI2. The image data D[k,1] to D[k,N] are image data written to the k-th row of the pixel array PXA before the image data D[i,1] to D[i,N] are written to the i-th row of the pixel array PXA.

[0167] Furthermore, before time T07 in the timing chart of Figure 8, the potentials of the output terminals STA[1], STB[1], STA[2], STB[2], STA[N], and STB[N] are undefined, and are therefore indicated by hatching.

[0168] 8, after time T07 in the timing chart, the output terminals STA[1] and STB[1] output signals whose logic is inverted from each other, so that when the output terminal STA[1] is at a high potential (thick solid line), the output terminal STB[1] becomes a low potential (thick solid line), and when the output terminal STA[1] is at a low potential (thick dashed line), the output terminal STB[1] becomes a high potential (thick dashed line). Similarly, the output terminals STA[2] and STB[2] output signals whose logic is inverted from each other, so that when the output terminal STA[2] is at a high potential (thick solid line), the output terminal STB[2] becomes a low potential (thick solid line), and when the output terminal STA[2] is at a low potential (thick dashed line), the output terminal STB[2] becomes a high potential (thick dashed line). Similarly, the output terminals STA[N] and STB[N] output signals with inverted logic, so that when the output terminal STA[N] is at a high level potential (thick solid line), the output terminal STB[N] is at a low level potential (thick dashed line), and when the output terminal STA[N] is at a low level potential (thick dashed line), the output terminal STB[N] is at a high level potential (thick dashed line).

[0169] Note that after time T07 in the timing chart of FIG. 8 , the changes in the potentials of the output terminals STA[1], STB[1], STA[2], STB[2], STA[N], and STB[N] are shown using solid and dashed lines, but the potentials of the output terminals STA[1], STA[2], and STA[N] are independent of each other. In other words, the potentials of the output terminals STB[1], STB[2], and STB[N] are independent of each other. For example, even if the potential of the output terminal STA[1] is high, the potential of the output terminal STA[2] may be low or high. Similarly, even if the potential of the output terminal STA[1] is high, the potential of the output terminal STA[N] may be low or high.

[0170]

[0046] Between time T01 and time T07, a high-level potential (denoted as "High" in FIG. 8) is input to the wiring CKL1, so that the high-level potential from the wiring CKL1 is input to the second terminals of the logic circuits LMP[1] to LMP[N] included in the control circuit CTR.

[0171] [Between time T02 and time T03] Between time T02 and time T03, image data D[i,1] is transmitted to the wiring DL, and the image data D[i,1] is input to the input terminal DI1 of the control circuit CTR and the input terminals DA of the flip-flop circuits FFA[1] to FFA[N]. In addition, image data D[k,1] is read from the memory circuit MEM and input to the input terminal DI2 of the control circuit CTR.

[0172] Also, assume that a high-level potential is output from the first output terminal of the shift register SR between time T02 and time T03. As a result, a high-level potential is input to the first input terminal of the logic circuit LMP[1]. Also, assume that a low-level potential is input to the second input terminals of each of the logic circuits LMP[2] to LMP[N]. As a result, the logic circuit LMP[1] outputs a high-level potential from its output terminal, and the logic circuits LMP[2] to LMP[N] output a low-level potential from their output terminals. As a result, the potential of the wiring CKL2[1] becomes a high-level potential, and the potentials of the wirings CKL2[2] to CKL2[N] become low-level potentials (denoted as "Low" in FIG. 8).

[0173] Therefore, a high-level potential is input from the line CKL2[1] to the clock input terminal of the flip-flop circuit FFA[1]. As a result, the flip-flop circuit FFA[1] holds the image data D[i,1] input to the input terminal DA and outputs the image data D[i,1] to the output terminal QA. In addition, the image data D[i,1] is input to the input terminal of the latch circuit LTA[1].

[0174] On the other hand, since the potentials of the wirings CKL2[2] to CKL2[N] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFA[2] to FFA[N]. Therefore, the flip-flop circuits FFA[2] to FFA[N] do not hold the image data D[i,1] transmitted to the wiring DL.

[0175] Next, between time T02 and time T03, in the control circuit CTR, the image data D[i,1] is input to the first input terminal of the circuit DFR, and the image data D[k,1] is input to the second input terminal. Therefore, the circuit DFR calculates the difference in gradation between the image data D[i,1] and the image data D[k,1], and determines whether the difference in gradation is less than a threshold value (reference value) or greater than or equal to the threshold value (reference value). As a result, the circuit DFR outputs a first logic signal including the result of this determination to the output terminal. Here, the signal including the result of the determination of the image data for the first column is referred to as the first logic signal LSG[1].

[0176] Furthermore, the first logic signal LSG[1] output from the output terminal of the circuit DFR is input to the input terminal DB of each of the flip-flop circuits FFB[1] to FFB[N]. Between time T02 and time T03, a high-level potential is input from the line CKL2[1] to the clock input terminal of the flip-flop circuit FFB[1] via the input terminal ET[1] of the control circuit CTR. This causes the flip-flop circuit FFB[1] to hold the first logic signal LSG[1] input to the input terminal DB and output the first logic signal LSG[1] to the output terminal QB. Furthermore, the first logic signal LSG[1] is input to the input terminal of the latch circuit LTB[1].

[0177] On the other hand, since the potentials of the wirings CKL2[2] to CKL2[N] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFB[2] to FFB[N]. Therefore, the flip-flop circuits FFB[2] to FFB[N] do not hold the first logic signal LSG[1] input to their input terminals DB.

[0178] [Between time T03 and time T04] Between time T03 and time T04, image data D[i,2] is transmitted to the wiring DL, and the image data D[i,2] is input to the input terminal DI1 of the control circuit CTR and the input terminals DA of the flip-flop circuits FFA[1] to FFA[N]. In addition, image data D[k,2] is read out from the memory circuit MEM and input to the input terminal DI2 of the control circuit CTR.

[0179] Furthermore, between time T03 and time T04, a high-level potential is output from the second output terminal of the shift register SR. As a result, a high-level potential is input to the first input terminal of the logic circuit LMP[2]. Also, a low-level potential is input to the second input terminals of the logic circuit LMP[1] and the logic circuits LMP[3] to LMP[N]. As a result, the logic circuit LMP[2] outputs a high-level potential from its output terminal, and the logic circuit LMP[1] and the logic circuits LMP[3] to LMP[N] output a low-level potential from their output terminals. As a result, the potential of the wiring CKL2[2] becomes a high-level potential, and the potentials of the wirings CKL2[1] and the wirings CKL2[3] to CKL2[N] become low-level potentials.

[0180] Therefore, a high-level potential is input from the line CKL2[2] to the clock input terminal of the flip-flop circuit FFA[2]. As a result, the flip-flop circuit FFA[2] holds the image data D[i,2] input to the input terminal DA and outputs the image data D[i,2] to the output terminal QA. In addition, the image data D[i,2] is input to the input terminal of the latch circuit LTA[2].

[0181] On the other hand, because the potentials of the wirings CKL2[1] and CKL2[3] to CKL2[N] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFA[1] and FFA[3] to FFA[N]. Therefore, the flip-flop circuits FFA[1] and FFA[3] to FFA[N] do not hold the image data D[i,2] transmitted to the wiring DL.

[0182] Next, between time T03 and time T04, in the control circuit CTR, the image data D[i,2] is input to the first input terminal of the circuit DFR, and the image data D[k,2] is input to the second input terminal. Therefore, the circuit DFR calculates the difference in gradation between the image data D[i,2] and the image data D[k,2], and determines whether the difference in gradation is less than a threshold value (reference value) or greater than or equal to the threshold value (reference value). As a result, the circuit DFR outputs a first logic signal including the result of this determination to the output terminal. Here, the signal including the result of the determination of the image data for the second column is referred to as the first logic signal LSG[2].

[0183] Furthermore, the first logic signal LSG[2] output from the output terminal of the circuit DFR is input to the input terminal DB of each of the flip-flop circuits FFB[1] to FFB[N]. Between time T03 and time T04, a high-level potential is input from the line CKL2[2] to the clock input terminal of the flip-flop circuit FFB[2] via the input terminal ET[2] of the control circuit CTR. This causes the flip-flop circuit FFB[2] to hold the first logic signal LSG[2] input to the input terminal DB and output the first logic signal LSG[2] to the output terminal QB. Furthermore, the first logic signal LSG[2] is input to the input terminal of the latch circuit LTB[2].

[0184] On the other hand, because the potentials of the wirings CKL2[1] and CKL2[3] to CKL2[N] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFB[1] and FFB[3] to FFB[N]. Therefore, the flip-flop circuits FFB[1] and FFB[3] to FFB[N] do not hold the first logic signal LSG[2] input to their input terminals DB.

[0185] [Between time T04 and time T05] Between time T04 and time T05, image data D[i,3] to D[i,N-1] are sequentially transmitted to the wiring DL. In addition, image data D[k,3] to D[k,N-1] are sequentially read out from the memory circuit MEM and sequentially input to the input terminal DI2 of the control circuit CTR.

[0186] Also, between time T04 and time T05, high-level potentials are sequentially output from the third output terminal to the (N-1)th output terminal of the shift register SR. Note that low-level potentials are output to the output terminals to which no high-level potentials are output. As a result, high-level potentials are sequentially input to the first input terminals of the logic circuits LMP[3] to LMP[N-1]. Therefore, the potentials of the wirings CKL2[3] to CKL2[N-1] sequentially become high-level potentials.

[0187] As described above, similar to the flip-flop circuit FFA[1] from time T02 to time T03, or the flip-flop circuit FFA[2] from time T03 to time T04, the image data D[i,3] to D[i,N-1] are held in the flip-flop circuits FFA[3] to FFA[N-1], respectively, in the third to (N-1)th columns of the drive circuit SD from time T04 to time T05. Furthermore, the image data D[i,3] to D[i,N-1] are transmitted from the output terminals QA of the flip-flop circuits FFA[3] to FFA[N-1] to the latch circuits LTA[3] to LTA[N-1], respectively.

[0188] Similarly to the circuit DFR between time T02 and time T03, or the circuit DFR between time T03 and time T04, the circuit DFR performs a calculation to determine the difference in gradation between the image data of the i-th row and the image data of the k-th row, and compares the difference in gradation with a threshold value (reference value) between time T04 and time T05. Similarly to the flip-flop circuit FFB[1] between time T02 and time T03, or the flip-flop circuit FFB[2] between time T03 and time T04, the first logic signal generated by the circuit DFR is held in each of the flip-flop circuits FFB[3] to FFB[N-1] in the third to (N-1)th columns. In addition, first logic signals corresponding to the respective columns are transmitted from the output terminals QB of the flip-flop circuits FFB[3] to FFB[N-1] to the latch circuits LTB[3] to LTB[N-1].

[0189] [Between time T05 and time T06] Between time T05 and time T06, image data D[i,N] is transmitted to the wiring DL, and the image data D[i,N] is input to the input terminal DI1 of the control circuit CTR and the input terminals DA of the flip-flop circuits FFA[1] to FFA[N]. In addition, image data D[k,N] is read from the memory circuit MEM and input to the input terminal DI2 of the control circuit CTR.

[0190] Also, assume that a high-level potential is output from the Nth output terminal of the shift register SR between time T05 and time T06. As a result, a high-level potential is input to the first input terminal of the logic circuit LMP[N]. Also, assume that a low-level potential is input to the second input terminal of each of the logic circuits LMP[1] to LMP[N-1]. As a result, the logic circuit LMP[N] outputs a high-level potential from its output terminal, and the logic circuits LMP[1] to LMP[N-1] output a low-level potential from their output terminals. As a result, the potential of the wiring CKL2[N] becomes a high-level potential, and the potentials of the wirings CKL2[1] to CKL2[N-1] become a low-level potential.

[0191] Therefore, a high-level potential is input from the wiring CKL2[N] to the clock input terminal of the flip-flop circuit FFA[N]. As a result, the flip-flop circuit FFA[N] holds the image data D[i,N] input to the input terminal DA and outputs the image data D[i,N] to the output terminal QA. In addition, the image data D[i,N] is input to the input terminal of the latch circuit LTA[N].

[0192] On the other hand, since the potentials of the wirings CKL2[1] to CKL2[N-1] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFA[1] to FFA[N-1], and therefore the flip-flop circuits FFA[1] to FFA[N-1] do not hold the image data D[i,N] transmitted to the wiring DL.

[0193] Next, between time T05 and time T06, in the control circuit CTR, the image data D[i,N] is input to the first input terminal of the circuit DFR, and the image data D[k,N] is input to the second input terminal. Therefore, the circuit DFR calculates the difference in gradation between the image data D[i,N] and the image data D[k,N], and determines whether the difference in gradation is less than a threshold value (reference value) or greater than or equal to the threshold value (reference value). As a result, the circuit DFR outputs a first logic signal including the result of this determination to the output terminal. Here, the signal including the result of the determination of the image data for the Nth column is referred to as the first logic signal LSG[N].

[0194] Furthermore, the first logic signal LSG[N] output from the output terminal of the circuit DFR is input to the input terminal DB of each of the flip-flop circuits FFB[1] to FFB[N]. Between time T03 and time T04, a high-level potential from the wiring CKL2[N] is input to the clock input terminal of the flip-flop circuit FFB[N] via the input terminal ET[N] of the control circuit CTR. This causes the flip-flop circuit FFB[N] to hold the first logic signal LSG[N] input to the input terminal DB and output the first logic signal LSG[N] to the output terminal QB. Furthermore, the first logic signal LSG[N] is input to the input terminal of the latch circuit LTB[N].

[0195] On the other hand, since the potentials of the wirings CKL2[1] to CKL2[N-1] are low, a low potential is input to the clock input terminals of the flip-flop circuits FFB[1] to FFB[N-1], and therefore the flip-flop circuits FFB[1] to FFB[N-1] do not hold the first logic signal LSG[N-1] input to their input terminals DB.

[0196] [Between Time T06 and Time T07] Between Time T06 and Time T07, the potential of the wiring CKL1 transitions from a high-level potential to a low-level potential. As a result, a low-level potential from the wiring CKL1 is input to each second input terminal of the logic circuits LMP[1] to LMP[N] included in the control circuit CTR. As a result, regardless of the potential (e.g., high-level potential or low-level potential) input from the output terminal of the shift register SR to each first input terminal of the logic circuits LMP[1] to LMP[N], the output terminal of each of the logic circuits LMP[1] to LMP[N] outputs a low-level potential.

[0197] That is, the potentials of the wirings CKL2[1] to CKL2[N] become low-level potentials, and low-level potentials are input to the clock input terminals of the flip-flop circuits FFA[1] to FFA[N] and the flip-flop circuits FFB[1] to FFB[N], respectively. As a result, the image data held in the flip-flop circuits FFA[1] to FFA[N] and the flip-flop circuits FFB[1] to FFB[N] are not updated.

[0198] [Between Time T07 and Time T08] Between Time T07 and Time T08, a high-level potential is applied to each of the wirings LL1 and LL2, thereby applying a high-level potential to the enable input terminals of the latch circuits LTA[1] to LTA[N] and the latch circuits LTB[1] to LTB[N].

[0199] When a high-level potential is applied to the enable input terminals of the latch circuits LTA[1] to LTA[N], the latch circuits LTA[1] to LTA[N] each hold the image data applied to their input terminals and output the image data to their output terminals. Specifically, the latch circuit LTA[1] holds the image data D[i,1] and outputs the image data D[i,1] from its output terminal. Similarly, the latch circuit LTA[2] holds the image data D[i,2] and outputs the image data D[i,2] from its output terminal, and the latch circuit LTA[N] holds the image data D[i,N] and outputs the image data D[i,N] from its output terminal.

[0200] The image data D[i,1] to D[i,N] output from the output terminals of the latch circuits LTA[1] to LTA[N] are input to the level shifter circuits LS[1] to LS[N], and the image data D[i,1] to D[i,N] are shifted to a level that can be handled by the digital-to-analog conversion circuit DAC.

[0201] Furthermore, the level-shifted image data D[i,1] to D[i,N] are converted from digital potential to analog potential by a digital-to-analog conversion circuit DAC. Each of the image data D[i,1] to D[i,N] converted to analog potential is sent to an input terminal of the amplifier AP of each column and a first input terminal of the switch SWB.

[0202] Furthermore, when a high-level potential is applied to the enable input terminal of each of the latch circuits LTB[1] to LTB[N], each of the latch circuits LTB[1] to LTB[N] holds the logic of the first logic signal applied to the input terminal and outputs the first logic signal to the output terminal. Specifically, the latch circuit LTB[1] holds the logic of the first logic signal LSG[1] and outputs the first logic signal LSG[1] from the output terminal. Similarly, the latch circuit LTB[2] holds the logic of the first logic signal LSG[2] and outputs the first logic signal LSG[2] from the output terminal, and the latch circuit LTB[N] holds the logic of the first logic signal LSG[N] and outputs the first logic signal LSG[N] from the output terminal.

[0203] The first logic signal LSG[1] output from the output terminal of the latch circuit LTB[1] is output to the output terminal STA[1] of the control circuit CTR. The first logic signal LSG[1] is input to the input terminal of the inverter circuit NT[1], whereby a signal with the logic of the first logic signal LSG[1] inverted is generated and output to the output terminal STB[1] of the control circuit CTR. Here, the signal with the logic of the first logic signal LSG[j] inverted is referred to as the second logic signal LSGB[j]. Similarly, the first logic signal LSG[2] output from the output terminal of the latch circuit LTB[2] is output to the output terminal STA[1] of the control circuit CTR, and the second logic signal LSGB[2] generated by the inverter circuit NT[2] is output to the output terminal STB[2] of the control circuit CTR. Similarly, the first logic signal LSG[N] output from the output terminal of the latch circuit LTB[N] is output to the output terminal STA[N] of the control circuit CTR, and the second logic signal LSGB[N] generated by the inverter circuit NT[N] is output to the output terminal STB[N] of the control circuit CTR.

[0204] Here, let us focus on the first column of the drive circuit SD. The control terminal of the switch SWA[1] receives the first logic signal LSG[1] output from the output terminal STA[1] of the control circuit CTR, and the control terminal of the switch SWA[1] receives the second logic signal LSGB[1] output from the output terminal STB[1] of the control circuit CTR. Furthermore, since the first logic signal LSG[1] and the second logic signal LSGB[1] have mutually inverted logic, one of the switch SWA[1] and the switch SWB[1] is turned on, and the other of the switch SWA[1] and the switch SWB[1] is turned off.

[0205] For example, when the difference in gray scale between the image data D[i,1] and the image data D[k,1] is equal to or greater than a threshold value (reference value), the first logic signal LSG[1] output from the circuit DFR becomes high-level potential, and the second logic signal LSGB[1] generated by the inverter circuit NT[1] becomes low-level potential.

[0206] As a result, a high-level potential is applied to the control terminal of the switch SWA[1], turning the switch SWA[1] on, and a low-level potential is applied to the control terminal of the switch SWB[1], turning the switch SWB[1] off. As a result, in the first column of the control circuit CTR, the image data D[i,1] converted to analog potential and output from the digital-to-analog conversion circuit DAC is transmitted to the wiring SL[1] via the amplifier AP[1] and the switch SWA[1]. On the other hand, since the switch SWB[1] is in the off state, the image data D[i,1] converted to analog potential is not transmitted to the wiring SL[1] via the switch SWB[1].

[0207] When the difference in gradation between the image data D[i,1] and the image data D[k,1] is equal to or greater than a threshold value (reference value), the amount of charging and discharging required to rewrite the image data D[k,1] to the image data D[i,1] in the line SL[1] becomes large, but as described above, by amplifying the image data D[i,1], which is an analog potential, using the amplifier AP[1] and the switch SWA[1], the time required for charging and discharging can be shortened, thereby improving the display quality of the pixel array PXA.

[0208] Furthermore, for example, when the difference in gradation between the image data D[i,1] and the image data D[k,1] is less than a threshold value (reference value) in the circuit DFR, the first logic signal LSG[1] output from the circuit DFR becomes low-level potential, and the second logic signal LSGB[1] generated by the inverter circuit NT[1] becomes high-level potential.

[0209] As a result, a low-level potential is applied to the control terminal of the switch SWA[1], turning the switch SWA[1] off, and a high-level potential is applied to the control terminal of the switch SWB[1], turning the switch SWB[1] on. As a result, in the first column of the control circuit CTR, the image data D[i,1] converted to analog potential and output from the digital-to-analog conversion circuit DAC is transmitted to the wiring SL[1] via the switch SWB[1]. On the other hand, because the switch SWA[1] is in the off state, the image data D[i,1] converted to analog potential is not transmitted to the wiring SL[1] via the amplifier AP[1] and the switch SWA[1].

[0210] When the difference in gradation between the image data D[i,1] and the image data D[k,1] is less than the threshold value (reference value), the amount of charging and discharging required to rewrite the image data D[k,1] to the image data D[i,1] in the line SL[1] is relatively small, so that the use of the amplifier AP[1] can be reduced. As described above, by turning off the switch SWA[1], the operation of the amplifier AP[1] is stopped, so that the power consumption by the amplifier AP[1] can be reduced.

[0211] Note that the above is an explanation of the first column of the driving circuit SD, but the second to Nth columns of the driving circuit SD can also operate in the same way as the first column and can obtain the same effects as the first column.

[0212] 1 in the display device DSP, the amplifier AP can be driven when the amount of change in the gradation of the image signal is large in the wiring SL that functions as a source line, and can be stopped when the amount of change in the gradation of the image signal is small. This makes it possible to reduce the operation frequency of the amplifier AP in the display device DSP, thereby reducing the power consumption of the drive circuit SD or the display device DSP that includes the drive circuit SD.

[0213] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0214] Embodiment 2 In this embodiment, a metal oxide that functions as an oxide semiconductor will be described.

[0215] <Metal Oxide> When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids.

[0216] By using a crystalline metal oxide for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure.

[0217] The metal oxide according to one embodiment of the present invention has a plurality of microcrystals. Furthermore, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer according to one embodiment of the present invention preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0218] The metal oxide according to one embodiment of the present invention has a crystal structure different from either a single crystal structure or a polycrystalline structure, and preferably has a CAAC structure.

[0219] The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the a-b plane without any clear grain boundaries. When a cross section of an oxide semiconductor layer having the CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having the CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are arranged, for example, in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0220] In addition, a structure in which metal atoms in each of the multiple microcrystals are arranged in layers parallel or approximately parallel to the surface on which the metal atoms are formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or approximately perpendicular to the surface on which the metal atoms are formed, is sometimes referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the multiple microcrystals may have a crystal structure other than a hexagonal system (e.g., a cubic system crystal structure).

[0221] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 110° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal is formed.

[0222] A polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In contrast, in the CAAC structure, crystal grain boundaries are not clearly observed in the a-b plane, so a highly reliable semiconductor device can be realized. Furthermore, because there are fewer crystal grain boundaries, the energy barrier against carrier conduction in the transistor channel is small, and an improvement in on-current is expected. Furthermore, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor using an oxide semiconductor layer can be suppressed or the initial characteristics (particularly on-state current) of the transistor can be improved, making the transistor suitable for high-speed operation.

[0223] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0224] The crystallinity of the metal oxide can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0225] When electron diffraction is performed on a metal oxide having a CAAC structure, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the surface on which the metal oxide is formed or the normal vector of the surface of the metal oxide.

[0226] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0227] A cross-sectional TEM image of a metal oxide having a CAAC structure is obtained, and an FFT pattern is created by performing FFT processing on each region within the cross-sectional TEM image. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots that are high in brightness and approximately equal distances from the center among the spots observed in the created FFT pattern is taken as the crystal axis direction. Regions where the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90° ± 20°) relative to the surface to be formed, more preferably 75° to 105° (within 90° ± 15°), more preferably 80° to 100° (within 90° ± 10°), and even more preferably 85° to 95° (within 90° ± 5°) can be considered to have a CAAC structure.

[0228] When a metal oxide having a CAAC structure is viewed in a direction perpendicular to the surface to be formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the metal oxide has crystallinity. In addition, in a Voronoi diagram created by image analysis of a TEM image of a metal oxide having a CAAC structure viewed in a direction perpendicular to the surface to be formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0229] A method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0230] As an example of the observation range of the TEM in creating the Voronoi diagram, it is preferable to observe a rectangular region of 50 nm in length and 50 nm in width, although the observation range is not limited to this.

[0231] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0232] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0233] The crystallinity of the semiconductor material of the metal oxide is not limited. The metal oxide may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). The crystallinity of the metal oxide may suppress deterioration of transistor characteristics.

[0234] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Note that element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0235] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0236] In a cross section of a metal oxide observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel or approximately parallel to the surface on which they are formed. Metal atoms are observed as bright spots in the TEM image. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0237] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable metal oxides include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as a metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as a metal oxide according to one embodiment of the present invention.

[0238] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0239] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0240] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0241] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0242] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0243] <Example of Method for Forming Oxide Semiconductor> Next, a method for forming an oxide semiconductor layer included in an active layer of an OS transistor will be described. Note that the oxide semiconductor layer can be formed by forming the above-described metal oxide using two types of film formation methods.

[0244] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is deposited. At this time, a sputtering method can be used as a deposition method, thereby forming a metal oxide having high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or the like may be used.

[0245] Here, when a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer may be formed at the interface between the metal oxide and the surface on which the metal oxide is to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By first forming a metal oxide as a first layer on the surface on which the metal oxide is to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, etc., which are described as the first film formation method, and then providing a metal oxide formed using the first film formation method as a second layer, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface on which the metal oxide is to be formed can be suppressed. Furthermore, impurities contained in the surface on which the metal oxide is to be formed can be suppressed from being mixed into the second layer. These factors can further enhance the crystallinity of the second layer.

[0246] Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method for growing a thin film whose crystalline structure reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed.The wet method is also one of the film formation methods that causes little damage to the surface on which the film is formed.An example of a wet method is a spray coating method.

[0247] A third layer can be further formed on the second layer, for example, by the second film formation method.

[0248] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0249] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (the first and third layers) can be increased by using the second layer (i.e., the CAAC) having high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer serves as a nucleus or seed to cause solid-phase growth of a metal oxide in the upper and lower oxide semiconductor layers, thereby forming oxide semiconductor layers with high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically, an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC).

[0250] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. Furthermore, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0251] Note that it is preferable to perform a treatment for improving the crystallinity of the oxide semiconductor layer during or after the formation of the oxide semiconductor layer. Examples of the treatment for improving the crystallinity of the oxide semiconductor layer include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0252] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0253] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform the treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor layer by the ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single oxide semiconductor layer or a stacked structure of three or more oxide semiconductor layers.

[0254] Treatment for increasing the crystallinity of the oxide semiconductor layer may be performed after the oxide semiconductor layer is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor layer, or may be performed through another film such as an insulating film formed on the oxide semiconductor layer. For example, microwave plasma treatment may be performed after the oxide semiconductor layer is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor layer is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor layer through the insulating film.

[0255] Note that the treatment for increasing the crystallinity of the oxide semiconductor layer can also serve as treatment for removing impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor layer can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0256] When the treatment for increasing the crystallinity of the oxide semiconductor layer is performed, the temperature of the substrate is preferably set to room temperature (for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0257] By performing treatment to increase the crystallinity of the oxide semiconductor layer in addition to the above-described method for forming the oxide semiconductor layer, a highly reliable transistor can be provided.

[0258] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0259] Embodiment Mode 3 In this embodiment mode, a configuration example that can be applied to the pixel circuit PX included in the display device described in Embodiment Mode 1 will be described.

[0260] <Configuration Example 1 of Pixel Circuit> FIG. 9A is a circuit diagram showing a configuration example of a circuit that can be applied to the pixel circuit PX of the display device DSP described in the first embodiment.

[0261] The pixel circuit PX1 shown in FIG. 9A includes, for example, a transistor Tr1, a transistor Tr2, a capacitance element Cs1, a capacitance element Cs2, and a light-emitting device ED.

[0262] Examples of the light-emitting device ED include a light-emitting device containing an organic EL material, a light-emitting device containing an inorganic EL material, and a light-emitting diode (e.g., a micro LED). The pixel circuit PX1 can be a pixel circuit to which one or more of the above-mentioned light-emitting devices ED are applied. In this embodiment, the pixel circuit PX of the pixel array PXA is described as being applied with a light-emitting device containing an organic EL material. The brightness of light emitted from a light-emitting device capable of emitting particularly high brightness light is, for example, 500 cd / m ２ or more, preferably 1000 cd / m ２ More than 10000cd / m ２ More preferably, 2000 cd / m or less ２ More than 5000cd / m ２ It can be as follows:

[0263] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is connected to wiring GL. The first terminal of transistor Tr2 is connected to wiring IL, and the second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of capacitor Cs2, and the anode of light-emitting device ED. The second terminal of capacitor Cs2 is connected to wiring VCOM. The cathode of light-emitting device ED is connected to wiring VCAT.

[0264] As an example, the wiring SL is one of the wirings SL[1] to SL[N] shown in FIG. 1 or the wiring SLS[j] shown in FIG. 2, and functions as a wiring for transmitting an image signal from the driver circuit SD shown in FIG. 2 to the pixel circuit PX[i, j].

[0265] As an example, the wiring GL is a wiring that becomes the wiring GLS[i] shown in Figure 2 and functions as a wiring for transmitting a selection signal or a non-selection signal from the driver circuit GD shown in Figure 2 to the pixel circuit PX[i, j].

[0266] The wiring IL functions as a wiring for supplying a current to the anode of the light emitting device ED, and is therefore sometimes called a current supply line.

[0267] The wiring VCOM functions as a wiring that applies a fixed potential to the second terminal of the capacitance element Cs2. In particular, this fixed potential may be called a common potential. The common potential may be, for example, a low-level potential, a ground potential, or a negative potential. The wiring VCOM may also be a wiring that applies a common potential to the second terminal of the capacitance element Cs2 provided in another pixel circuit PX1 within the same pixel array PXA.

[0268] The wiring VCAT functions as a wiring that applies a fixed potential to the cathode of the light-emitting device ED. In particular, this fixed potential may be called a cathode potential. The cathode potential may be, for example, a low-level potential, a ground potential, or a negative potential. The wiring VCAT may also be a wiring that applies a cathode potential to the cathode of a light-emitting device ED provided in another pixel circuit PX1 within the same pixel array PXA.

[0269] The common potential provided by the wiring VCOM and the cathode potential provided by the wiring VCAT may be equal to each other. In this case, the wiring VCOM and the wiring VCAT may be the same wiring (not shown).

[0270] The transistor Tr1 functions as a write transistor for an image signal in the pixel circuit PX. Therefore, when it is desired to increase the frame frequency of the display device DSP, it is preferable to use a transistor with a high drive frequency for the transistor Tr1.

[0271] Furthermore, the transistor Tr2 functions as a drive transistor for controlling the amount of current flowing between the anode and cathode of the light-emitting device ED in the pixel circuit PX. Therefore, when the potential corresponding to the image signal is high, it is preferable to use a transistor having high voltage resistance for the transistor Tr2.

[0272] <Pixel Circuit Configuration Example 2> FIG. 9B is a circuit diagram showing a circuit configuration example that can be applied to the pixel circuit PX[i, j] of the display device DSP described in the first embodiment and that is different from the pixel circuit of FIG. 9A.

[0273] The pixel circuit PX2 shown in FIG. 9B includes, for example, a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a capacitance element Cs1, a capacitance element Cs3, and a light-emitting device ED.

[0274] For the transistor Tr1, the transistor Tr2, the capacitance element Cs1, and the light-emitting device ED, the description of the transistor Tr1, the transistor Tr2, the capacitance element Cs1, and the light-emitting device ED included in the pixel circuit PX1 can be referred to.

[0275] The pixel circuit PX2 not only emits light with an intensity corresponding to an input image signal, but also has the function of correcting the threshold voltage of the transistor Tr2, which is a drive transistor.

[0276] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is connected to wiring GL1. The first terminal of transistor Tr2 is connected to the first terminal of transistor Tr3, and the second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of capacitor Cs3, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr3 is connected to wiring VEL, and the gate of transistor Tr3 is connected to wiring GL2. The second terminal of capacitor Cs3 is connected to wiring VEL. The second terminal of transistor Tr4 is connected to wiring INIL, and the gate of transistor Tr4 is connected to wiring GL3. The cathode of light-emitting device ED is connected to wiring VCAT.

[0277] For the wiring SL and the wiring VCAT, the description of the wiring SL and the wiring VCAT connected to the pixel circuit PX1 in FIG. 9A can be referred to.

[0278] For the wiring GL1, the description of the wiring GL connected to the pixel circuit PX1 in FIG. 9A can be referred to.

[0279] For example, the wiring GL2 functions as a wiring for transmitting a control signal for switching the transistor Tr3 between an on state and an off state.

[0280] For example, the wiring GL3 functions as a wiring for transmitting a control signal for switching the transistor Tr4 between an on state and an off state.

[0281] For example, the wiring VEL functions as a wiring for applying a potential to the anode of the light-emitting device ED. The potential can be the anode potential of the light-emitting device ED.

[0282] The wiring INIL functions as a wiring for applying a potential to the anode of the light-emitting device ED. In particular, the potential can be, for example, an initialization potential for resetting the anode potential of the light-emitting device ED.

[0283] It is preferable to use transistors having high voltage resistance for the transistors Tr3 and Tr4.

[0284] 10A , the pixel circuit PX2 may have a configuration in which the back gate of the transistor Tr1 is connected to the gate of the transistor Tr1 and the back gate of the transistor Tr2 is connected to the second terminal of the transistor Tr2.

[0285] <Pixel Circuit Configuration Example 3> Figure 9C is a circuit diagram showing a circuit configuration example that can be applied to the pixel circuit PX[i, j] of the display device DSP of Figure 2 described in embodiment 1, and that is different from the pixel circuits of Figures 9A and 9B.

[0286] The pixel circuit PX3 shown in FIG. 9C includes, for example, a transistor Tr1, a transistor Tr2, a transistor Tr4, a transistor Tr5, a capacitance element Cs1, and a light-emitting device ED.

[0287] For the transistors Tr1, Tr2, Tr4, the capacitance element Cs1, and the light-emitting device ED, the description of the transistors Tr1, Tr2, Tr4, the capacitance element Cs1, and the light-emitting device ED included in the pixel circuit PX2 above can be referred to.

[0288] Like the pixel circuit PX2, the pixel circuit PX3 not only emits light with an intensity corresponding to an input image signal, but also has the function of correcting the threshold voltage of the transistor Tr2, which is a drive transistor.

[0289] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the gate of transistor Tr2, the first terminal of transistor Tr5, and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is connected to wiring GL1. The first terminal of transistor Tr2 is connected to wiring VEL, and the second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr5 is connected to wiring VBL, and the gate of transistor Tr5 is connected to wiring GL4. The second terminal of transistor Tr4 is connected to wiring INIL, and the gate of transistor Tr4 is connected to wiring GL3. The cathode of light-emitting device ED is connected to wiring VCAT.

[0290] For the wiring SL, the wiring VCAT, the wiring VEL, and the wiring INIL, the description of the wiring SL, the wiring VCAT, the wiring VEL, and the wiring INIL connected to the pixel circuit PX2 in FIG. 9B can be referred to.

[0291] For the wiring GL1, the description of the wiring GL1 connected to the pixel circuit PX1 in FIG. 9A can be referred to.

[0292] For the wiring GL3, the description of the wiring GL3 connected to the pixel circuit PX2 in FIG. 9B can be referred to.

[0293] For example, the wiring GL4 functions as a wiring for transmitting a control signal for switching the transistor Tr5 between an on state and an off state.

[0294] The wiring VBL functions as a wiring for applying a fixed potential to the first terminal of the capacitor Cs1. The fixed potential is, for example, a potential input to the gate of the transistor Tr2 when correcting the threshold voltage of the transistor Tr2, and is preferably approximately equal to the potential applied by the wiring VEL.

[0295] It is preferable to use a transistor having high voltage resistance as the transistor Tr5, for example, a transistor having a thick gate insulating film as the transistor Tr5.

[0296] <Pixel Circuit Configuration Example 4> Figure 9D is a circuit diagram showing a circuit configuration example that can be applied to the pixel circuit PX[i, j] of the display device DSP of Figure 2 described in embodiment 1 and is different from the pixel circuits of Figures 9A to 9C.

[0297] The pixel circuit PX4 shown in FIG. 9D includes, for example, a transistor Tr1, a transistor Tr2, a transistor Tr4, a capacitance element Cs1, and a light-emitting device ED.

[0298] For the transistors Tr1, Tr2, Tr4, the capacitance element Cs1, and the light-emitting device ED, the description of the transistors Tr1, Tr2, Tr4, the capacitance element Cs1, and the light-emitting device ED included in the pixel circuit PX3 above can be referred to.

[0299] Like the pixel circuit PX1, the pixel circuit PX4 also has the function of emitting light with a luminous intensity according to an input image signal.

[0300] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is connected to wiring GL1. The first terminal of transistor Tr2 is connected to wiring VEL, and the second terminal of transistor Tr2 is connected to the second terminal of capacitor Cs1, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr4 is connected to wiring INIL, and the gate of transistor Tr4 is connected to wiring GL3. The cathode of light-emitting device ED is connected to wiring VCAT.

[0301] For the wiring SL, the description of the wiring SL connected to the pixel circuit PX3 in FIG. 9C can be referred to. For the wiring VCAT, the description of the wiring VCAT connected to the pixel circuit PX3 in FIG. 9C can be referred to. For the wiring INIL, the description of the wiring INIL connected to the pixel circuit PX3 in FIG. 9C can be referred to. For the wiring GL1 and the wiring GL3, the description of the wiring GL1 and the wiring GL3 connected to the pixel circuit PX3 in FIG. 9C can be referred to.

[0302] In the pixel circuit PX4, the transistor Tr2 may be a transistor having a back gate. Specifically, as shown in FIG. 10B , the pixel circuit PX4 may be configured such that the back gate of the transistor Tr2 is connected to the second terminal of the transistor Tr2.

[0303] <Pixel Circuit Configuration Example 5> Figure 11A is a circuit diagram showing a circuit configuration example that can be applied to the pixel circuit PX[i, j] of the display device DSP of Figure 2 described in embodiment 1 and is different from the pixel circuits of Figures 9A to 9D.

[0304] The pixel circuit PX5 shown in FIG. 11A includes, for example, transistors Tr1 to Tr4, a transistor Tr6, a transistor Tr7, a capacitor Cs1, and a light-emitting device ED.

[0305] Note that for the transistors Tr1 to Tr4, the capacitor Cs1, and the light-emitting device ED, the description of the transistors Tr1 to Tr4, the capacitor Cs1, and the light-emitting device ED included in the pixel circuit PX2 can be referred to.

[0306] Like the pixel circuits PX2 and PX3, the pixel circuit PX5 not only emits light with an intensity corresponding to the input image signal, but also has the function of correcting the threshold voltage of the transistor Tr2, which is a drive transistor.

[0307] The first terminal of transistor Tr1 is connected to wiring SL, the second terminal of transistor Tr1 is connected to the first terminal of transistor Tr2 and the first terminal of transistor Tr7, and the gate of transistor Tr1 is connected to wiring GL1. The second terminal of transistor Tr2 is connected to the first terminal of transistor Tr3 and the first terminal of transistor Tr6, and the gate of transistor Tr2 is connected to the second terminal of transistor Tr6 and the first terminal of capacitor Cs1. The second terminal of transistor Tr3 is connected to wiring VEL, and the gate of transistor Tr3 is connected to wiring GL2. The gate of transistor Tr6 is connected to the gate of transistor Tr4 and wiring GL3. The second terminal of transistor Tr7 is connected to the first terminal of transistor Tr4, the second terminal of capacitor Cs1, and the anode of light-emitting device ED. The second terminal of transistor Tr4 is connected to wiring INIL. The cathode of the light emitting device ED is connected to the wiring VCAT.

[0308] For the wiring SL, the description of the wiring SL connected to the pixel circuit PX2 in FIG. 9B can be referred to. For the wiring VCAT, the description of the wiring VCAT connected to the pixel circuit PX2 in FIG. 9B can be referred to. For the wiring INIL, the description of the wiring INIL connected to the pixel circuit PX2 in FIG. 9B can be referred to. For the wiring VEL, the description of the wiring VEL connected to the pixel circuit PX2 in FIG. 9B can be referred to. For the wirings GL1 to GL3, the description of the wirings GL1 to GL3 connected to the pixel circuit PX2 in FIG. 9B can be referred to.

[0309] For example, the wiring GL5 functions as a wiring for transmitting a control signal for switching the transistor Tr7 between an on state and an off state.

[0310] It is preferable that the transistors Tr6 and Tr7 be transistors with high voltage resistance, for example, transistors with thick gate insulating films.

[0311] Note that the pixel circuit of the semiconductor device of one embodiment of the present invention is not limited to the configuration of the pixel circuit PX5 illustrated in FIG. 11A, and the circuit configuration of the pixel circuit PX5 can be changed as appropriate.

[0312] 11B, a capacitance element Cs4 may be provided in the pixel circuit PX5 of FIG. 11A. A first terminal of the capacitance element Cs4 is connected to the gate of the transistor Tr1 and the wiring GL1, and a second terminal of the capacitance element Cs4 is connected to the first terminal of the transistor Tr4, the second terminal of the transistor Tr7, the second terminal of the capacitance element Cs1, and the anode of the light-emitting device ED.

[0313] 12 , the pixel circuit PX5A may have a configuration in which the back gate of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr2 is connected to the second terminal of the transistor Tr2, and the back gate of the transistor Tr6 is connected to the gate of the transistor Tr6.

[0314] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0315] Embodiment Mode 4 In this embodiment mode, an example of a cross-sectional structure of the display device described in the above embodiment mode will be described.

[0316] FIG. 13A is a schematic perspective view illustrating a display device according to one embodiment of the present invention. For example, the display device DSP1 includes a display region DIS, a driver circuit region DRV, and a terminal region TMR. The display device DSP1 also includes a substrate BS, and the display region DIS, the driver circuit region DRV, and the terminal region TMR are located on the substrate BS. The display region DIS may include, for example, the pixel array PXA shown in FIG. 2 and described in Embodiment 1. The driver circuit SD described in Embodiment 1 may be provided outside the display device DSP1 shown in FIG. 13A.

[0317] The driver circuit region DRV includes, for example, driver circuits GD1, GD2, and SD. The driver circuits GD1 and GD2 can be applied to the driver circuit GD of the display device DSP of FIG. 2 described in the first embodiment, and the driver circuit SD can be applied to the driver circuit SD of the display device DSP of FIG. 2 described in the first embodiment.

[0318] The substrate BS can be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). In addition to semiconductor substrates, other materials that can be used for the substrate BS include, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, and a paper or base film containing a fibrous material. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as an acrylic resin. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device DSP1 includes a heat treatment, it is preferable to use a material with high heat resistance for the substrate BS.

[0319] For example, when the substrate BS is a semiconductor substrate made of silicon, the transistors included in the display region DIS and the drive circuit region DRV can be formed as Si transistors on the substrate BS.

[0320] Further, for example, when the substrate BS is a glass substrate, the transistors included in the display region DIS and the driver circuit region DRV can be formed as OS transistors over the substrate BS.

[0321] One or more of the drive circuits GD1, GD2, and SD included in the drive circuit region DRV may be mounted on the substrate BS as an IC (Integrated Circuit) chip using COG technology.

[0322] The drive circuits GD1 and GD2 each function as a drive circuit for displaying an image in the display area DIS. Specifically, the drive circuits GD1 and GD2 each function as a gate driver circuit for the display area DIS. The drive circuit SD also functions as a source driver circuit for the display area DIS.

[0323] The terminal region TMR includes terminals for supplying image signals and power supply voltages from the outside of the display device DSP1 to the inside of the display device DSP1. An FPC may be connected to the terminal region TMR. An IC chip may be mounted on the FPC using COF technology. The IC chip may include, for example, a drive circuit for displaying an image in the display region DIS.

[0324] The display area DIS has, for example, a plurality of pixels, which may be arranged in a matrix in the display area DIS.

[0325] Furthermore, the multiple pixels may be pixel circuits that use one or more of a liquid crystal display device, a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting device including a light-emitting diode such as a micro LED.

[0326] Furthermore, each of the multiple pixels can express one or multiple colors. In particular, the multiple colors can be, for example, three colors: red, green, and blue. Alternatively, the multiple colors can be, for example, red, green, and blue, plus two or more colors selected from cyan, magenta, yellow, and white. Note that each pixel expressing a different color is referred to as a sub-pixel, and when white is expressed by multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively referred to as a pixel. For convenience, in this specification and the like, a sub-pixel will be referred to as a pixel in the following description.

[0327] Note that the display device of one embodiment of the present invention is not limited to the configuration of the display device DSP1 illustrated in Fig. 13A. For example, the display device of one embodiment of the present invention may have the configuration of the display device DSP2 illustrated in Fig. 13B.

[0328] 13B shows an example of a display device DSP2 that includes a display area DIS, a circuit area SIC, and a terminal area TMR. The display device DSP2 also includes a substrate BS, similar to the display device DSP1. The display device DSP2 differs from the display area DSP1 in that the circuit area SIC and the terminal area TMR are provided on the substrate BS, and the display area DIS is provided on the circuit area SIC.

[0329] The circuit region SIC includes, as an example, the drive circuit region DRV described above. The circuit region SIC may also include various functional circuits other than the drive circuit region DRV. In this embodiment, the functional circuits are included in the functional circuit region MFNC. For example, the drive circuit SD described in the first embodiment can be included in the functional circuit region MFNC.

[0330] Furthermore, for example, the functional circuit area MFNC may include a GPU (Graphics Processing Unit). Furthermore, if the display device DSP2 includes a touch panel, the functional circuit area MFNC may include a sensor controller that controls a touch sensor included in the touch panel.

[0331] Furthermore, when a light-emitting device using an organic EL material is used as a display element of the display device DSP2, the functional circuit region MFNC may include an EL correction circuit. The EL correction circuit, for example, has the function of appropriately adjusting the amount of current input to the light-emitting device containing the organic EL material. Because the brightness of a light-emitting device containing an organic EL material when emitting light is proportional to the current, poor characteristics of the drive transistor connected to the light-emitting device may result in the brightness of the light emitted by the light-emitting device being lower than desired. The EL correction circuit, for example, monitors the amount of current flowing through the light-emitting device, and when the amount of current is lower than desired, increases the amount of current flowing through the light-emitting device to increase the brightness of the light emitted by the light-emitting device. Conversely, when the amount of current is higher than desired, the EL correction circuit may decrease the amount of current flowing through the light-emitting device.

[0332] Furthermore, when a liquid crystal element is used as the display element of the display device DSP2, the functional circuit area MFNC may include a gamma correction circuit.

[0333] Fig. 14 is a block diagram showing an example of the configuration of the display device DSP2 shown in Fig. 13B. The display device DSP2 shown in Fig. 14 has, as an example, a display area DIS and a circuit area SIC. Although Fig. 14 shows a sensor PDA, the sensor PDA may be arranged inside or outside the display device DSP2.

[0334] 13A may be connected to a functional circuit region MFNC located outside the display device DSP1 via a terminal region TMR. In this case, the configuration of the display device DSP1 can be considered to be the same as the configuration of the display device DSP2 shown in FIG.

[0335] In FIG. 14, thick solid lines indicate multiple wires or bus wires.

[0336] 14, a plurality of pixel circuits PX are arranged in a matrix in the display region DIS, for example. The pixel circuits PX arranged in a matrix can be considered to be the pixel array PXA of FIG. 2 described in the first embodiment.

[0337] In addition, in FIG. 14, the circuit region SIC has a drive circuit region DRV and a functional circuit region MFNC, as described above.

[0338] The driver circuit region DRV functions as a peripheral circuit for driving the display region DIS, for example. Specifically, the driver circuit region DRV includes, for example, a driver circuit SD and a driver circuit GD. The driver circuit SD can be applied to, for example, the driver circuit SD shown in FIG. 1 or 2 described in the first embodiment, and the driver circuit GD can be applied to, for example, the driver circuit GD shown in FIG. 2 described in the first embodiment.

[0339] The functional circuit area MFNC may be provided with circuits such as a memory device that stores image data to be displayed in the display area DIS, a decoder that restores encoded image data, a GPU that processes image data, a power supply circuit, a correction circuit, or a CPU. In Fig. 14, the functional circuit area MFNC includes, as an example, a memory device MEMD, a GPU 22, an EL correction circuit ECR, a timing controller TMC, a CPU (NoffCPU (registered trademark)) 21, a sensor controller SCC, and a power supply circuit EPS.

[0340] Furthermore, the display device DSP2 in FIG. 14 is configured such that, as an example, bus lines BSL are connected to the circuits included in the drive circuit region DRV and the circuits included in the functional circuit region MFNC.

[0341] The drive circuit SD has a function of transmitting image data to the pixel circuits PX included in the display area DIS, for example, and is therefore connected to the pixel circuits PX via wirings SL.

[0342] The drive circuit SD may include a digital-to-analog conversion circuit. The digital-to-analog conversion circuit has a function of converting image data digitally processed by a GPU or a correction circuit (described later) into analog data. The image data converted into analog data is transmitted to the display area DIS via the drive circuit SD. The digital-to-analog conversion circuit may be disposed outside the drive circuit SD.

[0343] For example, the driving circuit GD has a function of selecting a pixel circuit PX in the display area DIS to which image data is to be sent, and is therefore connected to the pixel circuit PX via a wiring GL.

[0344] The drive circuit SD may include a level shifter. For example, the level shifter has a function of converting a selection signal to a pixel circuit in the display area DIS to an appropriate level. The level shifter may also have a function of converting signals input to the drive circuit SD, digital-to-analog conversion circuit, drive circuit GD, etc. to an appropriate level.

[0345] The memory device MEMD has a function of storing image data to be displayed in the display area DIS, for example. The memory device MEMD can be configured to store image data as digital data or analog data.

[0346] Furthermore, when image data is stored in the memory device MEMD, it is preferable that the memory device MEMD is a nonvolatile memory. In this case, for example, a NAND type memory or the like can be used as the memory device MEMD.

[0347] Furthermore, when temporary data generated by the GPU 22, the EL correction circuit ECR, the CPU 21, etc. is stored in the memory device MEMD, it is preferable that the memory device MEMD be a volatile memory. In this case, for example, an SRAM, a DRAM, etc. can be used as the memory device MEMD.

[0348] The GPU 22 has a function of, for example, performing processing to render image data read from the memory device MEMD in the display area DIS. In particular, the GPU 22 is configured to perform parallel pipeline processing, so that the image data to be displayed in the display area DIS can be processed at high speed. The GPU 22 can also function as a decoder to restore encoded images.

[0349] The functional circuit region MFNC may also include multiple circuits capable of improving the display quality of the display region DIS. For example, such circuits may include a correction circuit (a circuit for correcting color or dimming) that detects color unevenness in an image displayed in the display region DIS and corrects the color unevenness to create an optimal image. Furthermore, if light-emitting devices using organic EL materials are used in the pixels of the display region DIS, the functional circuit region MFNC may also include an EL correction circuit. In this embodiment, the pixel circuits PX of the display region DIS are described as being equipped with light-emitting devices containing organic EL materials, and therefore the functional circuit region MFNC includes an EL correction circuit ECR, for example.

[0350] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through a display device (or the voltage applied to the display device) provided in the pixel may be monitored and acquired, the image displayed in the display area DIS may be acquired by an image sensor or the like, the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (for example, an artificial neural network), and the output result may be used to determine whether or not to correct the image.

[0351] Furthermore, the calculations of the artificial intelligence can be applied not only to image correction but also to up-conversion processing of image data. As a result, by up-converting image data with a low screen resolution to match the screen resolution of the display area DIS, it is possible to display an image with high display quality in the display area DIS. Furthermore, the calculations of the artificial intelligence can also be applied to down-conversion processing of image data.

[0352] The above-mentioned artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit area MFNC. That is, various correction calculations (correction of color unevenness, up-conversion processing, etc.) can be performed using the GPU 22. The GPU 22 may also include a circuit 22a that corrects color unevenness and a circuit 22b that performs up-conversion processing.

[0353] In this specification, a GPU that performs calculations for artificial intelligence is referred to as an AI accelerator. That is, in this specification, a GPU provided in the functional circuit area MFNC may be described as an AI accelerator.

[0354] As an example, the timing controller TMC has a function of varying the frame rate at which images are displayed in the display area DIS. For example, when a still image is displayed in the display area DIS, the display device DSP2 can be driven by the timing controller TMC at a lower frame rate. Also, when a moving image is displayed in the display area DIS, the display device DSP2 can be driven by the timing controller TMC at an increased frame rate. In other words, by providing the timing controller TMC in the display device DSP2, the frame rate can be changed depending on whether a still image or a moving image is displayed. In particular, when a still image is displayed in the display area DIS, the display device DSP2 can be operated at a lower frame rate, thereby reducing the power consumption of the display device DSP2.

[0355] The CPU 21 has a function of performing general-purpose processing, such as executing an operating system, controlling data, and executing various calculations and programs. In the display device DSP2, the CPU 21 has a role of issuing commands such as writing or reading image data to or from the memory device MEMD, correcting image data, or operating a sensor (described later). The CPU 21 may also have a function of transmitting control signals to one or more circuits selected from the circuits included in the functional circuit area MFNC, such as the memory device, GPU, correction circuit, timing controller, and high-frequency circuit.

[0356] The CPU 21 may also have a circuit (hereinafter referred to as a backup circuit) that temporarily backs up data. It is preferable that the backup circuit be able to retain the data even if, for example, the supply of power supply voltage is stopped. For example, when a still image is displayed in the display area DIS, the CPU 21 can suspend its function until an image different from the current still image is displayed. Therefore, by temporarily saving data being processed by the CPU 21 to the backup circuit and then stopping the supply of power supply voltage to the CPU 21, the dynamic power consumption of the CPU 21 can be reduced. Furthermore, in this specification, a CPU having a backup circuit is referred to as an Noff CPU.

[0357] The sensor controller SCC has a function of controlling the sensor PDA, for example. Also, in Fig. 14, a line SNCL is shown as a line for connecting the sensor PDA and the sensor controller SCC.

[0358] Furthermore, the sensor PDA can be, for example, an illuminance sensor. In particular, by acquiring the intensity of external light illuminating the display area DIS using the illuminance sensor, the brightness (luminance) of the image displayed in the display area DIS can be changed according to the external light. For example, when the external light is bright, the luminance of the image displayed in the display area DIS can be increased to improve the visibility of the image. Conversely, when the external light is dark, the luminance of the image displayed in the display area DIS can be decreased to reduce power consumption.

[0359] Alternatively, the sensor PDA may be, for example, an image sensor. For example, by acquiring an image or the like using the image sensor, the image can be displayed in the display area DIS.

[0360] For example, the power supply circuit EPS has a function of generating voltages to be supplied to circuits included in the drive circuit region DRV, circuits included in the functional circuit region MFNC, pixels included in the display region DIS, etc. The power supply circuit EPS may also have a function of selecting the circuit to which to supply voltage. For example, during a period in which a still image is displayed in the display region DIS, the power supply circuit EPS can reduce the power consumption of the entire display device DSP by stopping the supply of voltage to each circuit included in the drive circuit region DRV (e.g., the drive circuit SD, the digital-to-analog conversion circuit, etc.) and each circuit included in the functional circuit region MFNC (e.g., the CPU 21, the GPU 22, etc.).

[0361] In addition, the display device of one embodiment of the present invention may be a display device DSP3 illustrated in FIG. 13C, which is obtained by changing the configuration of the display device DSP1 in FIG. 13A.

[0362] The display device DSP3 is a modified example of the display device DSP1, and is configured such that a sensor area TP is provided in an area overlapping the display area DIS.

[0363] The display device DSP3 also includes a drive circuit TDE and a drive circuit TDR, each of which is provided on a substrate BS. As shown in FIG. 13C, each of the drive circuits TDE and TDR is included in a drive circuit region DRV.

[0364] The driving circuit TDR has a function of sequentially transmitting pulse signals to the multiple sensors included in the sensor region TP, and the driving circuit TDE has a function of detecting changes in the amount of current flowing from the multiple sensors included in the sensor region TP.

[0365] As described above, the display device DSP3 is configured to have a touch panel as a user interface.

[0366] Although not shown, a sensor region TP may also be provided above the display region DIS of the display device DSP2. In this case, it is preferable that the drive circuits TDR and TDE are provided in the circuit region SIC.

[0367] <Cross-Sectional Configuration Example 1 of Display Device> Next, a configuration example in a cross-section of the display device DSP1 shown in FIG. 13A will be described.

[0368] The display device DSP1A shown in Fig. 15 is a cross-sectional configuration example of the display device DSP1 shown in Fig. 13A. The display device DSP1A has a configuration in which pixel circuits, drive circuits, etc. are provided on a substrate 310. The display device DSP1A in Fig. 15 also shows the drive circuit region DRV and display region DIS shown in Fig. 13A.

[0369] The substrate 310 in FIG. 15 can be the substrate BS shown in FIG. 13A . The diagonal size of the display device DSP1A can be determined, for example, by the type and size of the substrate 310. For example, when manufacturing a display device with a diagonal size of 30 inches or more, 50 inches or more, 70 inches or more, or 100 inches or more for a television device or an electronic device for digital signage, a glass substrate can be used as the substrate 310. For example, when manufacturing a display device with a diagonal size of 1.5 inches or less, 1 inch or less, or 0.5 inches or less for an XR device or a wearable information terminal, a semiconductor substrate can be used as the substrate 310.

[0370] In the description of the display device DSP1A in FIG. 15, the substrate 310 is a glass substrate.

[0371] Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display device DSP1A. For example, the display device DSP1A can support various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, or 32:9.

[0372] In the display device DSP1 of Figure 15, transistors MNy and MNx are formed on a substrate. In this specification, transistors MNy and MNx are collectively referred to as transistors MN. Furthermore, light-emitting devices 130R, 130G, and 130B are provided above transistors MNy and MNx. In this specification, light-emitting devices 130R, 130G, and 130B are collectively referred to as light-emitting devices 130.

[0373] The transistor MNx is included in the display region DIS and functions, for example, as a transistor included in the pixel circuit PX. The transistor MNy functions as a transistor included in the drive circuit region DRV. Therefore, the transistor MNy can be, for example, a transistor included in the drive circuit SD or drive circuit GD described in embodiment 1. The light-emitting device 130 can be a light-emitting device included in the pixel circuit PX.

[0374] Next, the specific configurations of transistors MNy and MNx will be described. Fig. 16A shows a schematic plan view of transistor MN. Fig. 16B is a schematic cross-sectional view corresponding to the portion of dashed-dotted line A1-A2 shown in Fig. 16A, and is also a schematic cross-sectional view of transistor MN. Fig. 16C is a schematic cross-sectional view corresponding to the portion of dashed-dotted line A3-A4 shown in Fig. 16A, and is also a schematic cross-sectional view of transistor MN.

[0375] In Figures 16A to 16C, the direction of the dashed dotted line A1-A2 is the X direction, and the direction of the dashed dotted line A3-A4 is the Y direction. The direction perpendicular to the X and Y directions is the Z direction. The X and Y directions can be perpendicular to each other. The definitions of the X, Y, and Z directions may be the same or different in subsequent drawings. In describing schematic plan views such as Figure 16A, the right side may be referred to as the +X direction, the left side as the -X direction, the upper side as the +Y direction, and the lower side as the -Y direction. In describing schematic cross-sectional views such as Figure 16B, the right side may be referred to as the +X direction, the left side as the -X direction, the upper side as the +Z direction, and the lower side as the -Z direction. In describing schematic cross-sectional views such as Figure 16C, the right side may be referred to as the +Y direction, the left side as the -Y direction, the upper side as the +Z direction, and the lower side as the -Z direction.

[0376] The transistor MN in FIGS. 16A to 16C has insulating layers IS1 to IS3, an insulating layer GI1, conductive layers ME1 to ME3, and a semiconductor layer SC1.

[0377] The insulating layer IS1 functions as, for example, a base film or an interlayer film for providing the source, drain, drain, and channel formation regions of the transistor MN thereover.

[0378] The insulating layer IS1 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer IS1 can be made of, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating. Alternatively, the insulating layer IS1 can be made of, for example, a resin. The material used for the insulating layer IS1 may also be an appropriate combination of the insulating materials described above.

[0379] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0380] Furthermore, it is preferable to use an insulating material with a low relative dielectric constant for the insulating layer IS1. By using an insulating material with a low relative dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings. Specifically, for example, the relative dielectric constant of the insulating layer IS1 is preferably less than 4, and more preferably less than 3. Examples of insulating materials with a low relative dielectric constant include silicon oxide, silicon oxynitride, and silicon nitride oxide.

[0381] The conductive layer ME1 is a conductor (which may be referred to as a terminal, wiring, etc.) that functions as one of the source and drain of the transistor MN. The conductive layer ME2 is a conductor (which may be referred to as a terminal, wiring, etc.) that functions as the other of the source and drain of the transistor MN.

[0382] 16A to 16C, the conductive layer ME1 is provided as a wiring extending in the +Y direction and the −Y direction, for example, and the conductive layer ME2 is provided as a wiring extending in the +X direction and the −Y direction, for example.

[0383] For each of the conductive layers ME1 and ME2, it is preferable to use, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more selected from the above-mentioned metal elements, or an alloy combining two or more selected from the above-mentioned metal elements. Furthermore, it is preferable to use, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel for the conductive layer ME1. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, the conductor may be a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus or arsenic), or a silicide (e.g., nickel silicide).

[0384] Moreover, the insulating layer IS2 functions as an interlayer film that separates the source and drain in the transistor MN, for example.

[0385] For the insulating layer IS2, for example, a material applicable to the insulating layer IS1 can be used.

[0386] Furthermore, an opening KK1 having a side surface that is approximately perpendicular to the X-Y plane (a taper angle of 70° or more and 110° or less) is formed in the insulating layer IS2 in a region where the transistor MN is to be provided. In particular, the area of ​​the opening KK1 can be made smaller as the taper angle becomes closer to 90°, thereby reducing the area required to form the transistor MN. Furthermore, the semiconductor layer SC1 including the channel formation region of the transistor MN is provided so as to be in contact with the conductive layers ME1 and ME2 via the opening KK1.

[0387] 16A , the shape of the opening KK1 is a perfect circle as an example, but one embodiment of the present invention is not limited to this. The shape of the opening KK1 may be, for example, a figure (including an ellipse) whose edge is a single closed curve, or a polygon with rounded corners.

[0388] The semiconductor layer SC1 can be, for example, a metal oxide that functions as an oxide semiconductor. In this case, the transistor MN is an OS transistor. For example, the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Furthermore, it is preferable that the element M is also contained. The element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony. In particular, the element M is preferably one or more of aluminum, gallium, yttrium, and tin. Furthermore, it is more preferable that the element M contains one or both of gallium and tin.

[0389] For example, it is preferable to use In—Ga—Zn oxide for the semiconductor layer SC1. In particular, it is more preferable that the In—Ga—Zn oxide be a metal oxide having a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, a composition of 4:2:3 (atomic ratio) or a composition thereabout, or a composition of 3:1:2 (atomic ratio) or a composition thereabout. Furthermore, as another example, it is preferable to use In—Zn oxide for the semiconductor layer SC1. In particular, it is more preferable that the In—Zn oxide be a metal oxide having a composition of In:Zn=4:1 (atomic ratio) or a composition thereabout.

[0390] The metal oxide functioning as an oxide semiconductor will be described in detail in Embodiment 2.

[0391] Furthermore, in the transistor MN, an insulating layer GI1 is provided on the semiconductor layer SC1. Specifically, in a plan view, the insulating layer GI1 is positioned so as to overlap a channel formation region included in the semiconductor layer SC1. Therefore, the insulating layer GI1 functions as a gate insulating film in the transistor MN.

[0392] The insulating layer GI1 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ It is preferable to use a single layer or a multilayer of an insulator containing a so-called high-k material such as BST (Bistella tetragonal silicon dioxide). Alternatively, the insulating layer GI1 may be made of an insulator having a high relative dielectric constant, such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

[0393] In addition, in the transistor MN, the conductive layer ME3 is provided on the insulating layer GI1 so as to fill the opening KK1. In addition, in the transistor MN, the conductive layer ME3 is provided on the insulating layer GI1 so as to fill the opening KK1. The conductive layer ME3 is a conductor (which may also be referred to as a terminal, wiring, etc.) that functions as a gate in each of the transistors MN.

[0394] For the conductive layer ME3, for example, a material applicable to the conductive layer ME1 or ME2 can be used.

[0395] In addition, in FIGS. 16A to 16C, the conductive layer ME3 is provided as a wiring so as to extend in the Y direction, for example.

[0396] 16A to 16C, the conductive layer ME1 functioning as one of the source and drain is located below the insulating layer IS2 that serves as an interlayer film, and the conductive layer ME2 functioning as the other of the source and drain is located above the insulating layer IS2. Therefore, the transistor MN has a configuration in which the channel formation region is provided along the opening KK1.

[0397] In this way, the transistor MN has a structure in which the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor MN can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0398] 16A to 16C, by providing the channel formation region of the transistor along the side surface of the opening in the insulator that functions as an interlayer film, the formation area of ​​the transistor can be made smaller than when the channel formation region of the transistor is provided along the X-Y plane. Furthermore, since the source electrode, semiconductor, and drain electrode of the transistor MN can be provided in an overlapping manner, the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor is arranged in a planar shape. Therefore, by forming a circuit using one or both of the transistors MN, the area of ​​the circuit can be reduced. Furthermore, as a result, it can lead to the miniaturization of a semiconductor device or display device including the circuit.

[0399] The transistor MN can be either a p-channel type or an n-channel type. Alternatively, a plurality of transistors MN may be provided and both p-channel and n-channel types may be used.

[0400] Furthermore, the transistor MN may be a transistor having a VLFET (Vertical Lateral Field Effect Transistor) structure, instead of the vertical channel transistor shown in FIGS. 16A to 16C.

[0401] The transistor MN shown in Figures 17A to 17C is a transistor with a VLFET structure, which allows current to flow both vertically and horizontally. Specifically, a semiconductor layer is positioned so as to contact the side of an opening provided in a first insulating layer and the upper surface of a second insulating layer that corresponds to the bottom of the opening, and the semiconductor layer includes a channel formation region of the transistor MN. In other words, the channel length of the transistor MN has a component along the side of the opening and a component along the bottom of the opening, making it easier to make it longer than the channel length of a conventional transistor structure. Note that the channel length here can be the length between the source and drain of the channel formation region.

[0402] In addition, for the transistor MN in FIG. 17B, the channel length CHL of the channel formation region included in the semiconductor layer SC1 is written.

[0403] By increasing the channel length, the off-state current (leakage current) of the transistor can be reduced. Therefore, for example, by applying the transistor MN shown in FIGS. 17A to 17C to the transistor Tr1 in each of the pixel circuits PX shown in FIGS. 9A to 12, the potential at the first terminal of the capacitance element Cs1 can be maintained for a long time. In other words, it is possible to prevent unintended fluctuations in the potential at the first terminal of the capacitance element Cs1 due to leakage current or the like.

[0404] Fig. 17A shows a schematic plan view of transistor MN. Fig. 17B is a schematic cross-sectional view corresponding to the portion of dashed dotted line A1-A2 shown in Fig. 17A, which is also a schematic cross-sectional view of transistor MN. Fig. 17C is a schematic cross-sectional view corresponding to the portion of dashed dotted line A3-A4 shown in Fig. 17A, which is also a schematic cross-sectional view of transistor MN.

[0405] The transistor MN in FIGS. 17A to 17C includes, as an example, insulating layers IS1 to IS3, an insulating layer GI1, a conductive layer ME2a, a conductive layer ME2b, a conductive layer ME3, and a semiconductor layer SC1.

[0406] 17A to 17C, the descriptions of the insulating layers IS1 to IS3, the insulating layer GI1, the conductive layer ME3, and the semiconductor layer SC1 shown in Figures 16A to 16C can be referred to. Also, the descriptions of the conductive layer ME2 shown in Figures 16A to 16C can be referred to.

[0407] As an example, the insulating layer IS2 functions as an insulating layer for forming the semiconductor layer SC1. As shown in Figures 17A to 17C, the insulating layer IS2 has an opening KK2, and the transistor MN has a configuration in which a portion of the semiconductor layer SC1 is included in the opening KK2. Specifically, the insulating layer IS2 has the opening KK2 so that the semiconductor layer SC1 has an area in contact with the sidewall of the insulating layer IS2, which corresponds to the side surface of the opening KK2, and the upper surface of the insulating layer IS1, which corresponds to the bottom of the opening KK2. Note that the transistor MN has a configuration in which the channel formation region of the transistor MN is included in the semiconductor layer SC1 provided inside the opening KK2.

[0408] 17A , the shape of the opening KK2 is a perfect circle as an example, but one embodiment of the present invention is not limited to this. The shape of the opening KK2 may be, for example, a figure (including an ellipse) whose edge is a single closed curve, or a polygon with rounded corners.

[0409] For example, the conductive layer ME2a functions as one of the source and drain of the transistor MN. For example, the conductive layer ME2b functions as the other of the source and drain of the transistor MN. Note that all or part of the conductive layer ME2a and the conductive layer ME2b may be referred to as, for example, an electrode, a terminal, or a wiring.

[0410] The conductive layers ME2a and ME2b are each located above the insulating layer IS2. In particular, the conductive layers ME2a and ME2b are separated by an opening KK2 to form a pair of conductive layers in the schematic top view of FIG. 17A and the schematic cross-sectional view of FIG. 17B. For this reason, in the transistor MN of FIGS. 17A to 17C, the width of each of the conductive layers ME2a and ME2b as wiring is preferably shorter than the length of the opening KK2 in the Y direction in the schematic top view of FIG. 17A. Note that in the schematic top view of FIG. 17A, as an example, the opening KK2 is a perfect circle, and the length of the opening KK2 in the Y direction can be the diameter of that circle.

[0411] 17A to 17C, the conductor ME2a is provided as a wiring extending in the −X direction, for example, and the conductor ME2b is provided as a wiring extending in the +X direction, for example.

[0412] As described above, the semiconductor layer SC1 has a region in contact with the sidewall of the insulating layer IS2, which corresponds to the side surface of the opening KK2, and the upper surface of the insulating layer IS1, which corresponds to the bottom of the opening KK2. Furthermore, the semiconductor layer SC1 has a region in contact with the upper surface of the conductive layer ME2a and the upper surface of the conductive layer ME2b. As described above, the semiconductor layer SC1 includes a channel formation region of the transistor MN. The channel length CHL of the channel formation region of the transistor MN is determined by the area of ​​the bottom of the opening KK2 and the depth of the opening KK2 (the length of the side surface of the opening KK2 or the film thickness of the insulating layer IS2).

[0413] The insulating layer GI1 also functions as a gate insulating layer (sometimes referred to as a gate insulating film) of the transistor MN, for example. The insulating layer GI1 has regions in contact with the upper surface of the semiconductor layer SC1, the upper surface of the conductor ME2a, and the upper surface of the conductor ME2b.

[0414] In particular, the thickness of the insulating layer GI1 significantly contributes to the electrical characteristics of the transistor MN. For example, if the thickness of the insulating layer GI1 is increased (if the gate insulating layer of the transistor MN is increased), the voltage gradient between the gate (conductor ME3) of the transistor MN and the channel formation region of the semiconductor layer SC1 can be made gentler, thereby improving the tolerance to the gate potential (sometimes referred to as the gate-source voltage or gate-drain voltage). On the other hand, if the gate insulating film of the transistor is made thinner, the change in the electric field applied from the gate to the channel formation region of the semiconductor when the gate potential is changed becomes faster, thereby increasing the driving frequency of the transistor.

[0415] Therefore, for example, by determining the film thickness of the insulating layer GI1, which is the gate insulating layer of each of multiple transistors MN, for each transistor MN, it is possible to easily create transistors that have high resistance to gate potential and transistors that have high driving frequencies.

[0416] 15, an insulating layer 574 is formed above the transistors MNy and MNx, and an insulating layer 581 is formed on the insulating layer 574. Openings are provided in the insulating layer IS3, the insulating layer 574, and the insulating layer 581, and a conductive layer MPG is embedded in the openings. Therefore, the conductive layer ME2 has an area in contact with the conductive layer MPG.

[0417] The insulating layer 574 preferably has a function of suppressing diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and / or hydrogen molecules). That is, the insulating layer 574 preferably functions as a barrier insulating film that suppresses the incorporation of the impurities into the transistor MN. The insulating layer 574 also preferably has a function of suppressing diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules). For example, the insulating layer 574 preferably has lower oxygen permeability than the insulating layer IS3 and the insulating layer 581. That is, the insulating layer 574 preferably has a function of suppressing oxygen from being released from the semiconductor layer SC1 and diffusing above the insulating layer IS3.

[0418] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used.

[0419] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulating layer 324 is calculated by TDS as follows: the amount of desorption converted into hydrogen atoms is 10×10 per area of ​​the insulating layer 324 when the surface temperature of the film is in the range of 50° C. to 500° C. １５ atoms / cm ２ It is preferable that the density is 5×10 or less. １５ atoms / cm ２It is more preferable to set the following:

[0420] Therefore, the insulating layer 574 may be formed of an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, either in a single layer or a stacked layer. Specifically, examples of insulators that suppress the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulators that suppress the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Furthermore, examples of insulators that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0421] In particular, it is preferable to use aluminum oxide or silicon nitride for the insulating layer 574. This can prevent impurities such as water and hydrogen from diffusing from above the insulating layer 574 to the transistor MN. Also, it can prevent oxygen from diffusing from above the insulating layer 574 to the transistor MN.

[0422] For example, the insulating layer 581 preferably has a lower dielectric constant than the insulating layer 574. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. Furthermore, the insulating layer 581 preferably has a reduced concentration of impurities such as water and hydrogen.

[0423] Therefore, the insulating layer 581 can be made of, for example, a material that can be used for any one of the insulating layers IS1 to IS3.

[0424] As the material for each plug and wiring (e.g., conductive layer MPG), one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials can be used in a single layer or a laminated layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Furthermore, it is preferable to use a low-resistance conductive material such as aluminum or copper as the material. The use of a low-resistance conductive material can reduce the wiring resistance.

[0425] An insulating layer 592 and an insulating layer 594 are stacked in this order over the insulating layer 581 and the conductive layer MPG.

[0426] Furthermore, for the insulating layer 592, it is preferable to use an insulating film (referred to as a barrier insulating film or a barrier insulating layer) that has barrier properties that prevent impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor MN to a region above the insulating layer 592 (for example, a region where the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B are provided). For this reason, for the insulating layer 592, a material that can be applied to any one of the insulating layers IS1 to IS3 can be used.

[0427] Note that the insulating layer 594 preferably has a lower dielectric constant than the insulating layer 592. The insulating layer 594 preferably has a reduced concentration of impurities such as water and hydrogen. For this reason, the insulating layer 594 can be formed using, for example, a material that can be used for the insulating layer 574.

[0428] Furthermore, a conductive layer 596 that connects to a light-emitting device or the like provided above the insulating layer 594 is embedded in the insulating layer 592 and the insulating layer 594. The conductive layer 596 functions as a plug or wiring. In addition, a plurality of conductors that function as plugs or wiring may be collectively given the same reference numeral. In this specification and the like, the wiring and the plug that connects to the wiring may be integral. That is, there are cases where a part of the conductor functions as the wiring and cases where a part of the conductor functions as the plug.

[0429] The conductive layer 596 can be made of, for example, a material that can be used for the conductive layer MPG.

[0430] An insulating layer 598 and an insulating layer 599 are formed in this order over the insulating layer 594 and the conductive layer 596 .

[0431] For example, the insulating layer 598 is preferably an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layers 581 and 592. As the insulating layer 599, an insulator with a relatively low relative dielectric constant is preferably used in order to reduce parasitic capacitance generated between wirings, similar to the insulating layer 594. For this reason, the insulating layer 598 can be made of a material that can be used for the insulating layer 581 or the insulating layer 592.

[0432] The insulating layer 599 functions as an interlayer insulating film and a planarizing film.

[0433] For example, the insulating layer 599 preferably has a lower dielectric constant than the insulating layer 598. The insulating layer 599 preferably has a reduced concentration of impurities such as water and hydrogen. For this reason, the insulating layer 599 can be formed using, for example, a material that can be used for any one of the insulating layers IS1 to IS3.

[0434] The light emitting device 130 and the connection portion 140 are formed on the insulating layer 599 .

[0435] The connection portion 140 may be referred to as a cathode contact portion, and is connected to the cathode electrodes of the light-emitting devices 130R, 130G, and 130B. In Fig. 15, the connection portion 140 includes one or more conductive layers selected from conductive layers 112a to 112c described below, at least one conductive layer selected from conductive layers 126a to 126c described below, one or more conductive layers selected from conductive layers 129a to 129c described below, a common layer 114 described below, and a common electrode 115 described below.

[0436] The connection section 140 may be provided so as to surround the four sides of the display section in a plan view, or may be provided within the display section (for example, between adjacent light-emitting devices 130).

[0437] The light-emitting device 130R includes a conductive layer 112a, a conductive layer 126a on the conductive layer 112a, and a conductive layer 129a on the conductive layer 126a. The conductive layers 112a, 126a, and 129a may all be referred to as pixel electrodes, or some of them may be referred to as pixel electrodes. The light-emitting device 130G includes a conductive layer 112b, a conductive layer 126b on the conductive layer 112b, and a conductive layer 129b on the conductive layer 126b. Similar to the light-emitting device 130R, the conductive layers 112b, 126b, and 129b may all be referred to as pixel electrodes, or some of them may be referred to as pixel electrodes. The light-emitting device 130B includes a conductive layer 112c, a conductive layer 126c on the conductive layer 112c, and a conductive layer 129c on the conductive layer 126c. As with the light-emitting devices 130R and 130G, the conductive layers 112c, 126c, and 129c may all be called pixel electrodes, or some of them may be called pixel electrodes.

[0438] The conductive layers 112a to 112c and the conductive layers 126a to 126c can be, for example, conductive layers functioning as reflective electrodes. For the conductive layers functioning as reflective electrodes, a conductor with high reflectivity to visible light, such as silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film), can be used. Furthermore, the conductive layers 112a to 112c and the conductive layers 126a to 126c can be a stacked film of aluminum sandwiched between a pair of titanium films (a stacked film of Ti, Al, and Ti in this order) or a stacked film of silver sandwiched between a pair of indium tin oxide films (a stacked film of ITO, Ag, and ITO in this order).

[0439] Alternatively, for example, a conductive layer functioning as a reflective electrode may be used as the conductive layers 112a to 112c, and a highly light-transmitting conductor may be used as the conductive layers 126a to 126c. An example of a highly light-transmitting conductor is indium tin oxide (sometimes referred to as ITO). Alternatively, an alloy of silver and magnesium may be used as the conductive layers 126a to 126c, as long as the alloy is thin enough to transmit light.

[0440] The conductive layers 129a to 129c can be, for example, a conductive layer that functions as a transparent electrode. The conductive layer that functions as a transparent electrode can be, for example, the above-described conductor with high light-transmitting properties.

[0441] The conductive layer 112a is connected to a conductive layer 596 embedded in an insulating layer 594 through an opening provided in the insulating layer 599. The end of the conductive layer 126a is located outside the end of the conductive layer 112a. The end of the conductive layer 126a and the end of the conductive layer 129a are aligned or approximately aligned.

[0442] Conductive layer 112b, conductive layer 126b, and conductive layer 129b in light-emitting device 130G, and conductive layer 112c, conductive layer 126c, and conductive layer 129c in light-emitting device 130B are similar to conductive layer 112a, conductive layer 126a, and conductive layer 129a in light-emitting device 130R, and therefore detailed description thereof will be omitted.

[0443] The conductive layers 112a, 112b, and 112c have recesses formed therein so as to cover the openings formed in the insulating layer 599. The layer 128 is buried in the recesses.

[0444] The layer 128 has a function of planarizing the recessed portions of the conductive layers 112a to 112c. The conductive layers 126a to 126c, which are in contact with the conductive layers 112a to 112c, are provided over the conductive layers 112a to 112c and over the layer 128. Therefore, the regions overlapping with the recessed portions of the conductive layers 112a to 112c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0445] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material.

[0446] An insulating layer containing an organic material can be suitably used for the layer 128. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins can be used for the layer 128. Alternatively, a photosensitive resin can be used for the layer 128. Examples of the photosensitive resin include positive-type materials and negative-type materials.

[0447] By using a photosensitive resin, the layer 128 can be formed only through exposure and development steps, and the influence of dry etching or wet etching on the surfaces of the conductive layers 112 a, 112 b, and 112 c can be reduced. Furthermore, by forming the layer 128 using a negative photosensitive resin, the layer 128 can be formed using the same photomask (exposure mask) as that used to form the opening in the insulating layer 599 in some cases.

[0448] Although Fig. 15 shows an example in which the top surface of layer 128 has a flat portion, the shape of layer 128 is not particularly limited. As shown in Fig. 18A, the top surface of layer 128 may have a shape that has a concave curved surface at the center and its vicinity in a cross-sectional view. Alternatively, as shown in Fig. 18B, layer 128 may have a shape that has a convex curved surface at the center and its vicinity in a cross-sectional view. Furthermore, as shown in Fig. 18C, layer 128 may have a shape that has a concave curved surface and a convex curved surface at the center and its vicinity.

[0449] Light-emitting device 130R has a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. Light-emitting device 130G has a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114. Light-emitting device 130B has a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

[0450] The first layer 113a is formed so as to cover the upper and side surfaces of the conductive layer 126a and the conductive layer 129a. Similarly, the second layer 113b is formed so as to cover the upper and side surfaces of the conductive layer 126b and the conductive layer 129b. Similarly, the third layer 113c is formed so as to cover the upper and side surfaces of the conductive layer 126c and the conductive layer 129c. Therefore, the entire regions where the conductive layers 126a, 126b, and 126c are provided can be used as light-emitting regions for the light-emitting devices 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0451] In the light-emitting device 130R, the first layer 113a and the common layer 114 can be collectively referred to as an EL layer. Similarly, in the light-emitting device 130G, the second layer 113b and the common layer 114 can be collectively referred to as an EL layer. Similarly, in the light-emitting device 130B, the third layer 113c and the common layer 114 can be collectively referred to as an EL layer.

[0452] The structure of the light emitting device of this embodiment is not particularly limited, and may be a single structure or a tandem structure.

[0453] The first layer 113a, the second layer 113b, and the third layer 113c are processed into island shapes by lithography. Therefore, the angle between the top surface and the side surface of each of the first layer 113a, the second layer 113b, and the third layer 113c is close to 90 degrees at the end. On the other hand, for example, an organic film formed using FMM (Fine Metal Mask) tends to gradually become thinner toward the end, and the top surface is formed in a sloped shape over a range of, for example, 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

[0454] The top surface and side surface of each of the first layer 113a, the second layer 113b, and the third layer 113c are clearly distinguishable. As a result, in adjacent first and second layers 113a and 113b, one side surface of the first layer 113a and one side surface of the second layer 113b are arranged opposite each other. This is true for any combination of the first layer 113a, the second layer 113b, and the third layer 113c.

[0455] The first layer 113a, the second layer 113b, and the third layer 113c each include at least a light-emitting layer. For example, it is preferable that the first layer 113a includes a light-emitting layer that emits red light, the second layer 113b includes a light-emitting layer that emits green light, and the third layer 113c includes a light-emitting layer that emits blue light. Furthermore, the respective light-emitting layers may be of colors other than those mentioned above, such as cyan, magenta, yellow, or white.

[0456] Each of the first layer 113a, the second layer 113b, and the third layer 113c preferably includes a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. The surfaces of the first layer 113a, the second layer 113b, and the third layer 113c may be exposed during the manufacturing process of the display device. Therefore, by providing the carrier transport layer on the light-emitting layer, the light-emitting layer can be prevented from being exposed to the outermost surface, and damage to the light-emitting layer can be reduced. This can improve the reliability of the light-emitting device.

[0457] The common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 114 is shared by the light-emitting devices 130R, 130G, and 130B.

[0458] The common electrode 115 is shared by the light-emitting devices 130R, 130G, and 130B. As shown in FIG. 15 , the common electrode 115 shared by the plurality of light-emitting devices is in contact with a conductor included in the connection portion 140.

[0459] The insulating layer 125 preferably functions as a barrier insulating layer against water and / or oxygen. The insulating layer 125 preferably has a function of suppressing diffusion of water and / or oxygen. The insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) water and / or oxygen. The insulating layer 125 has a function as a barrier insulating layer or a gettering function, which can suppress the entry of impurities (typically, water and / or oxygen) that may diffuse from the outside into each light-emitting device. This structure makes it possible to provide a highly reliable light-emitting device and a highly reliable display panel.

[0460] The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. Furthermore, by reducing the impurity concentration in the insulating layer 125, the barrier properties against water and / or oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration and / or a sufficiently low carbon concentration.

[0461] An insulating layer containing an organic material can be suitably used as the insulating layer 127. A photosensitive organic resin is preferably used as the organic material, such as a photosensitive resin composition containing an acrylic resin. The viscosity of the material for the insulating layer 127 is preferably 1 cP or more and 1500 cP or less, and more preferably 1 cP or more and 12 cP or less. By setting the viscosity of the material for the insulating layer 127 within the above range, the insulating layer 127 having a tapered shape, as described below, can be formed relatively easily. Note that in this specification and elsewhere, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0462] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface. For example, it is preferable that the structure has a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0463] As described below, the insulating layer 127 may have a tapered side surface, and the organic material that can be used for the insulating layer 127 is not limited to the above. For example, the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins. The insulating layer 127 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. The insulating layer 127 may also be made of a photosensitive resin, such as a photoresist. Examples of photosensitive resins include positive-type materials and negative-type materials.

[0464] The insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb light emitted from the light-emitting device, it is possible to suppress leakage of light from the light-emitting device to an adjacent light-emitting device through the insulating layer 127 (stray light). This can improve the display quality of the display panel. Furthermore, since the display quality can be improved without using a polarizing plate in the display panel, it is possible to reduce the weight and thickness of the display panel.

[0465] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used in color filters (sometimes called color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to obtain a black or nearly black resin layer.

[0466] The insulating layer 127 can be formed by a wet film formation method such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating. In particular, it is preferable to form the organic insulating film that becomes the insulating layer 127 by spin coating.

[0467] The insulating layer 127 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature when forming the insulating layer 127 is typically 200° C. or lower, preferably 180° C. or lower, more preferably 160° C. or lower, more preferably 150° C. or lower, and more preferably 140° C. or lower.

[0468] Below, the structure of the insulating layer 127 and other components will be described using the structure of the insulating layer 127 between the light-emitting devices 130R and 130G as an example. The same can be said for the insulating layer 127 between the light-emitting devices 130G and 130B and the insulating layer 127 between the light-emitting devices 130B and 130R. Furthermore, below, the end of the insulating layer 127 on the second layer 113b will be described as an example, but the same can be said for the end of the insulating layer 127 on the first layer 113a and the end of the insulating layer 127 on the third layer 113c.

[0469] The insulating layer 127 preferably has a tapered shape on its side surface with a taper angle θ1 in a cross-sectional view of the display device. The taper angle θ1 is the angle between the side surface of the insulating layer 127 and the substrate surface. However, it is not limited to the substrate surface, and may be the angle between the top surface of the flat portion of the insulating layer 125 or the top surface of the flat portion of the second layer 113b and the side surface of the insulating layer 127. Furthermore, by tapering the side surface of the insulating layer 127, the side surface of the insulating layer 125 and the side surface of the mask layer 118a may also be tapered.

[0470] The taper angle θ1 of the insulating layer 127 is less than 90°, preferably 60° or less, and more preferably 45° or less. By forming the side edge of the insulating layer 127 in such a forward tapered shape, the common layer 114 and the common electrode 115 provided on the side edge of the insulating layer 127 can be formed with good coverage without causing discontinuities or local thinning of the film. This improves the in-plane uniformity of the common layer 114 and the common electrode 115, thereby improving the display quality of the display device.

[0471] In addition, in a cross-sectional view of the display device, the upper surface of the insulating layer 127 preferably has a convex curved shape. The convex curved shape of the upper surface of the insulating layer 127 preferably bulges gently toward the center. Furthermore, the convex curved portion at the center of the upper surface of the insulating layer 127 preferably smoothly connects to the tapered portion at the side edge. By forming the insulating layer 127 in such a shape, the common layer 114 and the common electrode 115 can be formed with good coverage over the entire insulating layer 127.

[0472] The insulating layer 127 is formed in a region between two EL layers (for example, a region between the first layer 113a and the second layer 113b), with a portion of the insulating layer 127 being located between a side edge of one EL layer (for example, the first layer 113a) and a side edge of the other EL layer (for example, the second layer 113b).

[0473] It is also preferable that one end of the insulating layer 127 overlaps with the conductive layer 126a functioning as a pixel electrode, and the other end of the insulating layer 127 overlaps with the conductive layer 126b functioning as a pixel electrode. This structure allows the end of the insulating layer 127 to be formed on a substantially flat region of the first layer 113a (second layer 113b). Therefore, it is relatively easy to process the insulating layer 127 into a tapered shape as described above.

[0474] As described above, by providing the insulating layer 127 or the like, it is possible to prevent discontinuities and locally thin portions from being formed in the common layer 114 and the common electrode 115 from the substantially flat region of the first layer 113 a to the substantially flat region of the second layer 113 b. This makes it possible to prevent poor connection between the light-emitting devices in the common layer 114 and the common electrode 115 due to discontinuities and an increase in electrical resistance due to locally thin portions.

[0475] The display device of this embodiment can reduce the distance between light-emitting devices. Specifically, the distance between light-emitting devices, the distance between EL layers, or the distance between pixel electrodes can be less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the display device of this embodiment has a region where the distance between two adjacent island-shaped EL layers is 1 μm or less, preferably a region where the distance is 0.5 μm (500 nm) or less, and more preferably a region where the distance is 100 nm or less. In this way, by reducing the distance between each light-emitting device, a display device with high definition and a large aperture ratio can be provided.

[0476] A protective layer 131 is provided on the light-emitting device 130. The protective layer 131 is a film that functions as a passivation film that protects the light-emitting device 130. By providing the protective layer 131 that covers the light-emitting device, it is possible to prevent impurities such as water and oxygen from entering the light-emitting device, thereby improving the reliability of the light-emitting device 130. The protective layer 131 can be made of, for example, aluminum oxide, silicon nitride, or silicon nitride oxide.

[0477] The protective layer 131 and the substrate 110 are bonded via an adhesive layer 107. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting device. In FIG. 15 , the space between the substrate 310 and the substrate 110 is filled with the adhesive layer 107, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 107 may be provided so as not to overlap with the light-emitting device. Furthermore, the space may be filled with a resin different from the frame-shaped adhesive layer 107.

[0478] The adhesive layer 107 can be made of various curable adhesives, such as ultraviolet-curable photocurable adhesives, reactive curable adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Epoxy resins with low moisture permeability are particularly preferred. Two-component resins may also be used. An adhesive sheet may also be used.

[0479] The display device DSP1A is a top-emission type. Light emitted by the light-emitting device is emitted toward the substrate 110. Therefore, it is preferable to use a material that is highly transparent to visible light for the substrate 110. For example, it is preferable to select a substrate that is highly transparent to visible light for the substrate 110 from among substrates that can be used for the substrate 310 and the substrate BS. The pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0480] Note that the display device of one embodiment of the present invention may be a bottom-emission type instead of a top-emission type in which light emitted from a light-emitting device is emitted toward the substrate 310. In this case, a substrate having high transmittance to visible light is preferably selected as the substrate 310.

[0481] Next, a configuration example in a cross-sectional view of the display device DSP1 shown in FIG. 13A, which is different from the display device DSP1A shown in FIG. 15, will be described.

[0482] The display device DSP1B shown in FIG. 19 is a cross-sectional configuration example of the display device DSP1 shown in FIG. 13A, and is a display device including a transmissive liquid crystal element (sometimes called a liquid crystal display device).

[0483] The display device DSP1B has a substrate 310 and a substrate 610, and pixel circuits including liquid crystal elements and a driver circuit are sandwiched between the substrates 310 and 610.

[0484] For example, the display device DSP1B can display an image by transmitting light from a backlight (not shown) serving as a light source through liquid crystal elements 613a to 613c (described later). For this reason, it is preferable to use, for the substrate 310 and the substrate 610, a substrate having high transparency to visible light among substrates applicable to the substrate 310 of the display device DSP1A described in FIG.

[0485] 19, a liquid crystal element 613a serving as a display element includes a conductive layer 112a functioning as a first electrode, a conductive layer 631 functioning as a second electrode, and a liquid crystal layer 608. Similarly, a liquid crystal element 613b includes a conductive layer 112b functioning as a first electrode, a conductive layer 631 functioning as a second electrode, and a liquid crystal layer 608, and also includes a conductive layer 112c functioning as a first electrode, the conductive layer 631 functioning as a second electrode, and the liquid crystal layer 608.

[0486] Note that the liquid crystal elements 613 a to 613 c will hereinafter be collectively referred to as a liquid crystal element 613 .

[0487] The display device DSP1B also includes insulating layers 632 and 633 that function as alignment films and sandwich the liquid crystal layer 608. The conductive layer 631 is provided on the substrate 610 side, and the conductive layers 112a to 112c and the conductive layer 631 overlap with each other with the liquid crystal layer 608 interposed therebetween. The liquid crystal layer 608 is sealed with a sealant 605 that functions to bond the substrate 310 side and the substrate 610 side together. The transistor MNx provided in the display region DIS is connected to the liquid crystal element 613.

[0488] The conductive layers 112a to 112c and the conductive layer 631 are preferably formed using a conductive material that transmits visible light. Examples of the conductive material include a material containing one or more selected from indium (In), zinc (Zn), and tin (Sn). Specific examples include indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (ITSO), zinc oxide, and zinc oxide containing gallium. Note that the conductive layers 112a to 112c and the conductive layer 631 can be formed using a film containing graphene. The film containing graphene can be formed by reducing a film containing graphene oxide formed over a film of an insulator, a conductor, or the like.

[0489] Furthermore, it is preferable to use a highly light-transmitting material for each of the insulating layers IS1 to IS3, the insulating layer GI1, the conductive layers ME1 to ME3, the semiconductor layer SC1, the insulating layer 574, the insulating layer 581, the insulating layer 592, the insulating layer 594, the insulating layer 598, the insulating layer 599, the conductive layer 596, and the conductive layer MPG described in the display device DSP1A in FIG. 15 and the transistor MN in FIG. 16 so that light from a backlight (not shown) serving as a light source can pass through.

[0490] The liquid crystal element 613 may be, for example, a liquid crystal element to which an FFS (Fringe Field Switching) mode is applied. Generally, liquid crystal materials are classified into positive-type liquid crystal materials having a positive anisotropy (Δε) of dielectric constant and negative-type liquid crystal materials having a negative anisotropy. The liquid crystal element 613 shown in this embodiment mode can be applied with either of these materials, and an optimum liquid crystal material can be used depending on the applied mode and design.

[0491] In the display device described in this embodiment, it is preferable to use a negative liquid crystal material. Negative liquid crystals can suppress the influence of the flexoelectric effect caused by the polarization of liquid crystal molecules, and there is almost no difference in transmittance due to polarity. Therefore, it is possible to suppress flicker from being visible to users of the display device. The flexoelectric effect is a phenomenon that is mainly caused by molecular shape and causes polarization due to orientation distortion. Negative liquid crystal materials are less likely to cause orientation distortion due to spreading deformation and bending deformation.

[0492] Although an element to which the FFS mode is applied is used as the liquid crystal element 613 here, the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a liquid crystal element to which a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Opticaly Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an ECB (Electrically Controlled Birefringence) mode, a VA-IPS mode, a guest-host mode, or the like is applied can be used.

[0493] The display device described in this embodiment may be a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode. As the vertical alignment mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an advanced super view (ASV) mode, or the like may be used.

[0494] A liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field (including a horizontal electric field, a vertical electric field, or an oblique electric field) applied to the liquid crystal. Examples of liquid crystals that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystals (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, and the like, depending on the conditions.

[0495] Although FIG. 19 illustrates an example of a display device having a vertical-field liquid crystal element, a display device having a horizontal-field liquid crystal element can also be used in one embodiment of the present invention. When the horizontal-field mode is employed, a liquid crystal exhibiting a blue phase without an alignment film may be used. The blue phase is a liquid crystal phase that appears immediately before a cholesteric liquid crystal transitions from a cholesteric phase to an isotropic phase as the temperature of the liquid crystal increases. Because the blue phase appears only within a narrow temperature range, a liquid crystal composition containing 5 wt % or more of a chiral dopant is used for the liquid crystal layer 608 to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral dopant has a short response time and optical isotropy. Furthermore, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral dopant does not require an alignment treatment and has low viewing angle dependence. Furthermore, since an alignment film is not required, a rubbing treatment is also unnecessary. This can prevent electrostatic breakdown caused by the rubbing treatment, thereby reducing defects or damage to the liquid crystal display device during the manufacturing process.

[0496] The spacers 635 are columnar spacers obtained by selectively etching an insulating layer, and are provided to control the distance (cell gap) between the conductive layers 112a to 112c and the conductive layer 631. Note that spherical spacers may also be used.

[0497] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarizing component, a retardation component, and an anti-reflection component may be appropriately provided as needed. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. A backlight unit, a sidelight unit, or the like may be used as the light source (not shown). Micro LEDs or the like may be used as the backlight unit and the sidelight unit. In the case of the display device DSP1B of FIG. 19 , for example, a polarizing substrate is preferably provided on the front side of the substrate 610 (the side opposite to the side on which the colored layer 666R, the colored layer 666G, the colored layer 666B, and the light-shielding layer 642 are provided) and on the back side of the substrate 310 (the side opposite to the side on which the transistors MNx and MNy are provided), and a backlight unit is preferably provided on the back side of the substrate 310 via the polarizing substrate (not shown).

[0498] In the display device shown in FIG. 19, a light-shielding layer 642 , a colored layer 666 R, a colored layer 666 G, a colored layer 666 B, and an insulating layer 641 are provided between a substrate 610 and a conductive layer 631 .

[0499] Materials that can be used for the light-shielding layer 642 include carbon black, titanium black, metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. The light-shielding layer 642 may also be a laminated film of films containing one of the materials of the colored layers 666R to 666B. For example, a laminated structure may be used in which a film containing the material used for the colored layer 666R that transmits light of one color and a film containing the material used for the colored layer 666G that transmits light of another color. Using the same material for the colored layers 666R to 666B and the light-shielding layer 642 allows for the use of common equipment and simplifies the process, which is preferable.

[0500] Materials that can be used for the colored layers 666R to 666B include metal materials, resin materials, and resin materials containing pigments or dyes. The light-shielding layer and the colored layers may be formed in the same manner as the above-described methods for forming each layer. For example, they may be formed by an inkjet method or the like.

[0501] The insulating layer 641 is preferably an overcoat having a planarizing function. The planarizing function of the insulating layer 641 allows a flat insulating film to be formed on the surface on which the colored layers 666R to 666B and the light-shielding layer 642, each having a different thickness, are formed. The planarization of the insulating layer 641 allows the conductive layer 631 to be formed flat, thereby reducing variations in the thickness of the liquid crystal layer 608. Examples of such an insulating layer 641 include an acrylic resin.

[0502] <Second Cross-Sectional Configuration Example of Display Device> Next, a configuration example in a cross-sectional view of the display device DSP2 shown in FIG. 13B will be described.

[0503] The display device DSP2A shown in Fig. 20 is a cross-sectional configuration example of the display device DSP2 shown in Fig. 13B. The display device DSP2A has a configuration in which pixel circuits, drive circuits, etc. are provided on a substrate 310. Note that the display device DSP2A in Fig. 20 also shows a wiring area LIN in addition to the circuit area SIC and display area DIS shown in Fig. 13B.

[0504] The circuit region SIC includes, for example, a substrate 310, and a transistor 300d is formed on the substrate 310. A wiring region LIN is provided above the transistor 300d, and wiring is provided in the wiring region LIN to connect the transistor 300d, a transistor 500x (described later), the light-emitting device 130R, the light-emitting device 130G, or the light-emitting device 130B. A display region DIS is provided above the wiring region LIN, and the display region DIS includes, for example, the transistor 500x and the light-emitting device 130 (in FIG. 20 , the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B).

[0505] That is, the transistor 300d can be a transistor included in the circuit region SIC. The transistor 500x can be a transistor included in the pixel circuit PX shown in each of Figures 9A to 12. For example, the transistor 500x can be the transistor Tr2 included in the pixel circuit PX. The light-emitting device 130 can be a light-emitting device included in the pixel circuit PX.

[0506] 15. For the light-emitting devices 130 (light-emitting devices 130R, 130G, and 130B in FIG. 20) located above the transistor 500x, the description of the light-emitting devices 130 in FIG. 15 can be referred to.

[0507] The substrate 310 can be, for example, a substrate that can be used for the substrate BS. In this embodiment, the substrate 310 will be described as a semiconductor substrate made of silicon. Therefore, the transistors included in the circuit region SIC can be Si transistors. For example, Si transistors include transistors whose channel formation region includes single crystal silicon or transistors whose channel formation region includes low-temperature polysilicon (LTPS).

[0508] Therefore, the transistor 300d formed on the substrate 310 has a structure different from the transistors MNx and MNy shown in Fig. 15. In the display device DSP2A of Fig. 20, the transistors included in the circuit region SIC may be the transistors MNx and MNy shown in Fig. 15. In this case, the substrate 310 is preferably a glass substrate.

[0509] For the screen ratio (aspect ratio) of the display device DSP2A, the description of the screen ratio of the display device DSP1A can be referred to. Also, for the diagonal size of the display device DSP2A, the description of the diagonal size of the display device DSP1A can be referred to.

[0510] The transistor 300d includes an element isolation layer 312, a conductive layer 316, an insulating layer 315, an insulating layer 317, a semiconductor region 313 formed of a part of the substrate 310, and low-resistance regions 314a and 314b that function as source and drain regions. Therefore, the transistor 300d is a Si transistor. Note that although FIG. 20 illustrates a structure in which one of the source and drain of the transistor 300d is connected to a conductive layer 330 and a conductive layer 356, which will be described later, via a conductive layer 328, which will be described later, the electrical connection structure of the display device of one embodiment of the present invention is not limited thereto. In the display device of one embodiment of the present invention, for example, the gate of the transistor 300d may be connected to the conductive layer 328.

[0511] The transistor 300d can be made into a fin type by, for example, configuring the top surface and the side surface in the channel width direction of the semiconductor region 313 to be covered with a conductive layer 316 via an insulating layer 315 that functions as a gate insulator. By configuring the transistor 300d as a fin type, the effective channel width can be increased, and the on-characteristics of the transistor 300d can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-characteristics of the transistor 300d can be improved. The transistor 300d may be a planar type instead of a fin type.

[0512] Note that the transistor 300d can be either a p-channel transistor or an n-channel transistor, or a plurality of transistors 300d may be provided and both p-channel and n-channel transistors may be used.

[0513] The region where the channel of the semiconductor region 313 is formed, the region nearby, and the low-resistance region 314a and low-resistance region 314b that become the source region and drain region preferably contain a silicon-based semiconductor, specifically, single-crystal silicon. Alternatively, each of the above-mentioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Alternatively, a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300d may be, for example, a high electron mobility transistor (HEMT) using gallium arsenide and aluminum gallium arsenide.

[0514] The conductive layer 316 functioning as a gate electrode can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum. Alternatively, the conductive layer 316 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0515] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0516] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0517] An insulating layer 320 and an insulating layer 322 are stacked in this order from the substrate 310 side over a transistor 300d shown in FIG.

[0518] The insulating layer 320 and the insulating layer 322 can be formed using, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride.

[0519] The insulating layer 322 may function as a planarizing film that planarizes steps caused by the insulating layer 320 and the transistor 300d covered by the insulating layer 322. For example, the top surface of the insulating layer 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0520] A conductive layer 328 connected to the transistor 500x and the like provided above the insulating layer 322 is buried in the insulating layer 320 and the insulating layer 322. Note that the conductive layer 328 functions as a plug or a wiring. For this reason, the conductive layer 328 can be formed using a material that can be used for the conductive layer MPG described above.

[0521] In the display device DSP2A, a wiring region LIN is provided over the transistor 300d. The wiring region LIN includes, for example, an insulating layer 324, an insulating layer 326, a conductive layer 330, an insulating layer 350, an insulating layer 352, an insulating layer 354, and a conductive layer 356.

[0522] An insulating layer 324 and an insulating layer 326 are stacked in this order over the insulating layer 322 and the conductive layer 328. An opening is formed in the insulating layer 324 and the insulating layer 326 in a region overlapping with the conductive layer 328. A conductive layer 330 is embedded in the opening.

[0523] Moreover, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. Furthermore, openings are formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354 in regions overlapping with the conductive layer 330. Furthermore, a conductive layer 356 is embedded in the openings.

[0524] The conductive layer 330 and the conductive layer 356 function as a plug or a wiring connected to the transistor 300d. Note that the conductive layer 330 and the conductive layer 356 can be formed using a material similar to that of the conductive layer 328 or the conductive layer 596 described above.

[0525] Note that, for example, the insulating layers 324 and 350 are preferably made of an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulating layer 592. Similarly to the insulating layer 594, the insulating layers 326, 352, and 354 are preferably made of an insulator having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulating layers 326, 352, and 354 function as an interlayer insulating film and a planarizing film. The insulating layers 326, 352, and 354 preferably include an insulating layer having a barrier property against one or more selected from hydrogen, oxygen, and water.

[0526] An insulating layer 512 and an insulating layer 514 are stacked in this order over the insulating layer 354 and the conductive layer 356. A transistor 500x is provided over the insulating layer 514.

[0527] The insulating layer 512 functions as a planarizing film that flattens steps caused by the transistor 300d, a plug, and the like, similarly to the insulating layers 320 and 322. For this reason, the insulating layer 512 can be formed using a material that functions as a planarizing film, similarly to the insulating layers 320 and 322.

[0528] Furthermore, it is preferable that an insulator having a relatively low dielectric constant is used for the insulating layer 512. Therefore, the insulating layer 512 can be made of an insulator having a relatively low dielectric constant, similar to the insulating layer 594.

[0529] For the insulating layer 514, an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water can be used, similarly to the insulating layer 324, the insulating layer 350, and the insulating layer 592. Therefore, for the insulating layer 514, an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water can be used, similarly to the insulating layer 324, the insulating layer 350, and the insulating layer 592.

[0530] The transistor 500x is a transistor in which an island-shaped semiconductor layer formed on an insulating layer 512 and an insulating layer 514 are used as base films and an active layer is an island-shaped semiconductor layer formed on the base films. The gate of the transistor 500x is provided so as to surround the top surface and side surfaces of a portion of the island-shaped semiconductor layer. In FIG. 20 , a conductive layer functioning as the gate is provided on the top surface of a portion of the island-shaped semiconductor layer. A conductive layer functioning as one of the source and drain and a conductive layer functioning as the other of the source and drain are provided on another top surface of the island-shaped semiconductor layer. The conductive layer functioning as one of the source and drain and the conductive layer functioning as the other of the source and drain are provided so as to sandwich the gate.

[0531] 20 includes an island-shaped semiconductor layer and an interlayer film covering the semiconductor layer, and has an opening in the interlayer film for embedding a conductive layer that functions as a gate. After the opening is formed, the conductive layer is formed, so that the conductive layer is formed in a self-aligned manner within the opening. In this specification and elsewhere, the transistor 500x having a gate formed in a self-aligned manner within the opening may be referred to as a transistor with a top gate self-aligned (TGSA) structure.

[0532] In particular, in a transistor with a TGSA structure, an insulating layer functioning as a gate insulating film is formed in the opening, followed by a conductive layer functioning as a gate. In other words, the insulating layer is located between the semiconductor layer and the conductive layer. The insulating layer functioning as a gate insulating film significantly contributes to the electrical characteristics of the transistor 500x. For example, if the insulating layer is made thicker (if the gate insulating film of the transistor MN is made thicker), the voltage gradient between the gate of the transistor 500x and the channel formation region of the semiconductor layer can be made gentler, thereby improving the tolerance to the gate potential (sometimes referred to as the gate-source voltage or gate-drain voltage). On the other hand, if the gate insulating film of the transistor is made thinner, the change in the electric field applied from the gate to the channel formation region of the semiconductor when the gate potential is changed becomes faster, thereby increasing the driving frequency of the transistor.

[0533] 20, the transistor 500x included in the display region DIS may be the transistor MNx and the transistor MNy shown in FIG. 15. In particular, since the channel lengths of the transistors MNx and MNy are shorter than the channel length of the transistor 500x, the area of ​​the pixel circuit included in the display region DIS can be reduced. Furthermore, in the display device DSP2A of FIG. 20, if it is desired to increase the on-current of the transistor 500x included in the display region DIS, it is preferable to change the transistor 500x to the transistor MN.

[0534] An insulating layer 574, an insulating layer 581, an insulating layer 592, an insulating layer 594, an insulating layer 598, and an insulating layer 599 are formed in this order above the transistor 500x. A conductive layer MPG is embedded in the insulating layers 574 and 581, and a conductive layer 596 is embedded in the insulating layers 592 and 594.

[0535] Note that for the insulating layer 574, the insulating layer 581, the insulating layer 592, the insulating layer 594, the insulating layer 598, the insulating layer 599, the conductive layer MPG, and the conductive layer 596, the description of the display device DSP1A in Figure 15 can be referred to.

[0536] <Cross-Sectional Configuration Example 3 of Display Device> Next, a configuration example in a cross-sectional view of the display device DSP2 shown in FIG. 13B, which is different from FIG. 20, will be described.

[0537] The display device DSP2B shown in Fig. 21 is a cross-sectional configuration example of the display device DSP2 shown in Fig. 13B, which is different from Fig. 20. The display device DSP2B has a configuration in which the transistor 500x included in the display region DIS in the display device DSP2A is changed to a different transistor structure.

[0538] Therefore, for the display device DSP2A in FIG. 20, which has the same configuration as the display device DSP2B in FIG. 21, reference can be made to the display device DSP2A in FIG.

[0539] An insulating layer 516, an insulating layer 521, and an insulating layer 522 are stacked in this order over the insulating layer 514. A transistor 500mf is provided over the insulating layer 522 as a substitute for the transistor 500x of the display device DSP2A.

[0540] That is, the transistor 500mf can be a transistor included in the pixel circuit PX. In particular, the transistor structure of the transistor 500mf is preferably used for the transistor Tr2, which is the drive transistor of the pixel circuit PX shown in each of FIGS. 9A to 12. As will be described in detail later, the transistor 500mf has a large on-state current, and therefore, by using the transistor 500mf as the drive transistor of the pixel circuit PX, the luminance of light emitted from the pixel circuit PX can be increased. Furthermore, because the transistor 500mf has a high drive frequency, it can be used with the drive circuits SD and GD, which have high frame frequencies.

[0541] The transistor 500mf is a transistor having a fin-shaped semiconductor layer formed on an insulating layer 514 as a base film as an active layer. The gate of the transistor 500mf is provided so as to surround the top surface and side surfaces of a portion of the fin-shaped semiconductor layer. In FIG. 21 , a conductive layer functioning as the gate is provided on the top surface of a portion of the fin-shaped semiconductor layer. Another conductive layer functioning as one of the source and drain and another conductive layer functioning as the other of the source and drain are provided on another top surface of the fin-shaped semiconductor layer. The conductive layer functioning as one of the source and drain and the conductive layer functioning as the other of the source and drain are provided so as to sandwich the gate.

[0542] That is, the transistor 500mf included in the display region DIS of the display device DSP2B has multiple fin-shaped semiconductor layers, and the semiconductor layers include the channel formation regions of the transistor 500mf. Therefore, the transistor 500mf functions as a multi-channel transistor.

[0543] 21 includes a fin-shaped semiconductor layer and an interlayer film covering the semiconductor layer, and has an opening in the interlayer film for embedding a conductive layer that functions as a gate. Furthermore, by forming the conductive layer after forming the opening, the conductive layer is formed in a self-aligned manner within the opening. The transistor 500mf, in which the gate is formed in a self-aligned manner within the opening, may be referred to as a TGSA transistor, similar to the transistor 500x.

[0544] Next, a specific configuration example of the transistor 500mf in Fig. 21 will be described. Fig. 22A is a schematic plan view of the transistor 500mf shown in the display device DSP2B in Fig. 21, and Figs. 22B to 22D are schematic cross-sectional views of the transistor 500mf shown in the display device DSP2B in Fig. 21. In particular, Fig. 22B is a schematic cross-sectional view of the portion indicated by dashed-dotted line A1-A2 in Fig. 22A, and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 22C is a schematic cross-sectional view of the portion indicated by dashed-dotted line A3-A4 in Fig. 22A, and is also a schematic cross-sectional view of the transistor 500mf in the channel width direction. Fig. 22D is a schematic cross-sectional view of the portion indicated by dashed-dotted line A5-A6 in Fig. 22A, and is also a schematic cross-sectional view of the transistor 500mf in the channel length direction. Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the schematic plan view of FIG. 22A, some elements are omitted for clarity, and some elements are shown transparently. Also, FIG. 23A shows an enlarged view of the vicinity of the conductive layer 560 in FIG. 22D. Also, FIG. 23B shows an enlarged view of the vicinity of the semiconductor layer 530 in FIG. 22B. Also, FIG. 23C shows an enlarged view of the vicinity of the semiconductor layer 530 in FIG. 22C.

[0545] The transistor 500mf includes an insulating layer 516 over the insulating layer 514, an insulating layer 521 over the insulating layer 516, an insulating layer 522 over the insulating layer 521, a semiconductor layer 530 over the insulating layer 522, conductive layers 542a and 542b over the semiconductor layer 530 and the insulating layer 522, an insulating layer 550 over the semiconductor layer 530, and a conductive layer 560 (conductive layer 560a and conductive layer 560b) over the insulating layer 550. Note that hereinafter, the conductive layer 542a and the conductive layer 542b may be collectively referred to as the conductive layer 542.

[0546] An insulating layer 575 is provided over the conductive layer 542, and an insulating layer 580 is provided over the insulating layer 575. The insulating layer 550 and the conductive layer 560 are disposed inside openings provided in the insulating layer 580 and the insulating layer 575. The openings reach the semiconductor layer 530, and the insulating layer 550 is in contact with the semiconductor layer 530 within the openings. An insulating layer 582 is provided over the insulating layer 580 and the conductive layer 560. An insulating layer 583 is provided over the insulating layer 582.

[0547] An insulating layer 541a is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540a is provided in contact with the side surface of the insulating layer 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulating layer 541b is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540b is provided in contact with the side surface of the insulating layer 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that hereinafter, the conductive layers 540a and 540b may be collectively referred to as the conductive layer 540. The insulating layers 541a and 541b may be collectively referred to as the insulating layer 541.

[0548] For the insulating layers 541 a and 541 b, an insulating film having a function of suppressing oxygen permeation is preferably used to prevent a decrease in conductivity due to oxidation of the conductive layers 542 a and 542 b. For example, a silicon nitride film is preferably formed by a PEALD method.

[0549] The insulating layer 516 functions as a planarizing film that flattens steps caused by the transistor 300d, plugs, and the like, similarly to the insulating layers 320 and 322. For this reason, the insulating layer 516 can be made of a material that functions as a planarizing film, similarly to the insulating layers 320 and 322. Furthermore, by using a material with a low dielectric constant for the insulating layer 516, the parasitic capacitance between wirings can be reduced. From the above, the insulating layer 516 can be made of, for example, a material that can be used for the insulating layer IS1 described above.

[0550] For the insulating layers 521 and 522, an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water can be used, similarly to the insulating layers 324, 350, and 592. Therefore, for the insulating layers 521 and 522, an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water can be used, similarly to the insulating layers 324, 350, and 592.

[0551] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500mf. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 500mf. The insulating layer 550 has a region that functions as a first gate insulator of the transistor 500mf.

[0552] In particular, a metal oxide functioning as an oxide semiconductor can be used for the semiconductor layer 530. In this case, the transistor 500mf is an OS transistor. Note that the semiconductor layer 530 can be formed using, for example, a material that can be used for the semiconductor layer SC1.

[0553] The semiconductor layer 530 can be formed using the oxide semiconductor which is AG CAAC described in Embodiment 2. For example, as shown in FIG. 23B , the semiconductor layer 530 can have a structure including a semiconductor layer 530a, a semiconductor layer 530b in contact with the semiconductor layer 530a, and a semiconductor layer 530c in contact with the semiconductor layer 530b. The side surfaces of the semiconductor layer 530 (semiconductor layers 530a to 530c) are also preferably perpendicular or substantially perpendicular to the surface of the substrate.

[0554] As described above, in the cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel to or substantially parallel to the formation surface. In other words, in the cross section of the semiconductor layer 530 (semiconductor layers 530a to 530c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction perpendicular to or substantially perpendicular to the substrate surface. It can also be said that the c-axis of AG CAAC is substantially parallel to the normal direction to the side surface of the semiconductor layer 530.

[0555] In this way, by using the semiconductor layer 530 made of AG CAAC in the channel formation region of the transistor 500mf, a transistor with large on-state current, high field-effect mobility, a good S value, high frequency characteristics, and good reliability can be provided. Note that the S value is a subthreshold swing value, which indicates the amount of change in gate voltage in the subthreshold region required to change the drain current by one order of magnitude at a constant drain voltage. The smaller the S value, the steeper the slope of the drain current with respect to the gate voltage, resulting in better switching characteristics.

[0556] The semiconductor layers 530a to 530c can be formed, for example, by providing a pillar that functions as a sacrificial layer on the insulating layer 522, depositing a first semiconductor film that will become the semiconductor layer 530a, a second semiconductor film that will become the semiconductor layer 530b, and a third semiconductor film that will become the semiconductor layer 530c on the side surfaces of the pillar in this order, removing the first to third semiconductor films located on the top surfaces of the insulating layer 522 and the pillars, and then removing the pillars.

[0557] Furthermore, when the semiconductor layer 530 has a three-layer structure of semiconductor layers 530a to 530c as described above, the semiconductor layer 530 is formed in the order of semiconductor layer 530a, semiconductor layer 530b, and semiconductor layer 530c, with the region where the pillars were formed at the center. In other words, as shown in Fig. 22A , the semiconductor layer 530 has a structure that surrounds the region where the pillars were formed in plan view.

[0558] A channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the semiconductor layer 530. At least a part of the channel formation region overlaps with the conductive layer 560. The source region overlaps with the conductive layer 542a, and the drain region overlaps with the conductive layer 542b. Note that the source region and the drain region can be interchanged.

[0559] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0560] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0561] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0562] Note that when the carrier concentration of the semiconductor layer 530 is reduced, the impurity concentration in the semiconductor layer 530 is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0563] In order to stabilize the electrical characteristics of the transistor 500mf, it is effective to reduce the impurity concentration in the channel formation region in the semiconductor layer 530. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 530, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 530 refer to, for example, elements other than the main components constituting the semiconductor layer 530. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0564] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0565] In a transistor using an oxide semiconductor for the semiconductor layer 530, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, when oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor tends to have normally-on characteristics (a channel exists even when the gate-source voltage is 0 V, and current flows between the source and drain of the transistor). Therefore, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and the channel formation region be i-type (intrinsic) or substantially i-type.

[0566] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 500 mf may decrease. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of a semiconductor device including the transistor may vary. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, and its conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0567] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. Furthermore, it is preferable to suppress a decrease in the conductivity of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. For example, it is preferable to suppress oxidation of the conductive layer 560, the conductive layer 542a, the conductive layer 542b, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0568] 23B , the insulating layer 550 includes an insulating layer 550a, an insulating layer 550b, an insulating layer 550c, and an insulating layer 550d. The insulating layers 550a to 550d function as part of a first gate insulator. The insulating layers 550a to 550d are provided in an opening formed in the insulating layer 580, similar to the conductive layer 560 described later. To miniaturize the transistor 500mf, the insulating layers 550a to 550d are preferably thin. The thicknesses of the insulating layers 550a to 550d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is only necessary that at least a part of each of the insulating layers 550a to 550d has a region with the above-described thickness.

[0569] The thickness of the silicon oxide film used as the insulating layer 550 is preferably 0.7 nm to 3 nm.

[0570] In order to thin the insulating layers 550a to 550d as described above, it is preferable to form the insulating layers 550a to 550d by atomic layer deposition (ALD). Furthermore, it is preferable to form the insulating layers 550a to 550d in openings such as the insulating layer 580 by ALD. Examples of ALD include thermal ALD, which uses only thermal energy to cause a reaction between a precursor and a reactant, and plasma-enhanced ALD, which uses a plasma-excited reactant. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0571] The ALD method can deposit atoms layer by layer, and therefore has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, it is possible to form a film at a low temperature, etc. Therefore, the insulating layer 550 can be formed with good coverage on the side surface of the opening formed in the insulating layer 580 and with the thin film thickness as described above.

[0572] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0573] Although the insulating layer 550 has been described above as having a four-layer structure of insulating layers 550a to 550d, the present invention is not limited to this. The insulating layer 550 may have a structure including at least one of the insulating layers 550a to 550d. By forming the insulating layer 550 using one, two, or three of the insulating layers 550a to 550d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0574] For example, the insulating layer 550 may have a three-layer structure. In this case, it is preferable that the insulating layer 550 has a laminated structure of an insulating layer 550a, an insulating layer 550b on the insulating layer 550a, and an insulating layer 550c on the insulating layer 550b. In other words, this is a structure obtained by removing the insulating layer 550d from the structure shown in FIG. 23A.

[0575] It is preferable to use the ALD process two or more times in forming the insulating layer 550. For example, the insulating layer 550 preferably has a stacked structure of a plurality of insulating films, and it is preferable that two or more of the plurality of insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 550. Furthermore, it is possible to increase productivity by successively forming two or more different films, for example, two or more insulating films, using the ALD process.

[0576] For example, the insulating layer 550a is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550b is preferably made of silicon oxide, which has a high dielectric strength. The insulating layer 550c is preferably made of hafnium oxide, which has a high ability to capture or fix hydrogen. The insulating layer 550d is preferably made of silicon nitride, which has a high hydrogen barrier property.

[0577] 22D and other figures show the conductive layer 560 as having a two-layer structure. Here, the conductive layer 560 preferably includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, the conductive layer 560a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 560b. In this case, the conductive layer 560a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion.

[0578] The conductive layer 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0579] Furthermore, since the conductive layer 560a has the function of suppressing oxygen diffusion, it is possible to suppress the conductive layer 560b from being oxidized by oxygen contained in the insulating layer 580 or the like, which would cause a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include preferably titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Furthermore, the conductive layer 560a may be made of a material that can be used for the conductive layer ME1 described above.

[0580] The conductive layer 560b is preferably made of a conductor with high conductivity. For example, the conductive layer 560b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductive layer 560b may be made of a material that can be used for the conductive layer ME1 described above.

[0581] In the transistor 500mf, the conductive layer 560 is formed in a self-aligned manner to fill an opening formed in the insulating layer 580 or the like. Here, the side surfaces of the insulating layer 580 in the openings coincide or substantially coincide with the side surfaces of the conductive layers 542a and 542b. Therefore, the conductive layer 560 can be arranged to overlap the region between the conductive layers 542a and 542b without alignment.

[0582] The conductive layer 542a has a region functioning as one of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540a functions as a plug connected to the conductive layer 542a. The conductive layer 542b has a region functioning as the other of the source electrode and drain electrode of the transistor 500mf. The conductive layer 540b functions as a plug connected to the conductive layer 542b.

[0583] For the conductive layers 542a and 542b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 542a and 542b. When a conductive material containing metal and nitrogen is used for the conductive layers 542a and 542b, the conductive layers 542a and 542b become conductors containing at least metal and nitrogen. For example, it is preferable to select, as the material used for the conductive layers 542a and 542b, a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion from the materials that can be used for the conductive layer ME1 described above.

[0584] The conductive layers 540a and 540b are preferably made of a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 540 may also have a layered structure in which a first conductive layer is provided in contact with the side surface of the insulating layer 541 and a second conductive layer is provided further inside. In this case, the above-mentioned conductive material may be used as the second conductive layer. The conductive layers 540a and 540b may also be made of a material applicable to the above-mentioned conductive layer ME1. Here, the first conductor corresponds to the conductive layer 540a1 shown in FIG. 23A , and the second conductor corresponds to the conductive layer 540a2 shown in FIG. 23A .

[0585] Furthermore, when the conductive layer 540 has a stacked structure, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is preferably used for the first conductor disposed near the insulating layer 583, the insulating layer 582, the insulating layer 580, and the insulating layer 575. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulating layer 583 can be prevented from entering the semiconductor layer 530 through the conductive layer 540a and the conductive layer 540b.

[0586] For example, the insulating layer 575 is preferably a barrier insulating layer against oxygen. Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0587] For example, the insulating layer 580 preferably has a lower dielectric constant than the insulating layer 522. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 580 preferably uses, as a material with a low dielectric constant, one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies.

[0588] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0589] The upper surfaces of the insulating layers 580 may be planarized, so that the insulating layers 580 also function as planarizing films.

[0590] As described above, the insulating layer 580 can be formed using a material similar to that of the insulating layer 516 .

[0591] One or both of the insulating layers 582 and 583 preferably function as a barrier insulator that suppresses diffusion of oxygen from above the insulating layers 582 and 583 to the transistor 500mf or the like. Therefore, one or both of the insulating layers 582 and 583 can be resistant to hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0592] The insulating layer 582 and the insulating layer 583 each preferably include an insulator that has a function of suppressing diffusion of oxygen and impurities such as water and hydrogen, and can be, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide. For example, the insulating layer 583 is preferably made of silicon nitride, which has a higher hydrogen barrier property. Furthermore, the insulating layer 582 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen.

[0593] The semiconductor layer 530 is formed on and in contact with the insulating layer 522. As shown in Figures ...

Claims

a control circuit, a first switch, a second switch, an amplifier, and a memory circuit; an output terminal of the amplifier electrically connected to a first terminal of the first switch; an input terminal of the amplifier electrically connected to a first terminal of the second switch; a second terminal of the first switch electrically connected to a second terminal of the second switch; The control circuit includes: a function of acquiring a first image signal corresponding to image data of a first coordinate input to the control circuit, and acquiring a second image signal corresponding to image data of a second coordinate read from the memory circuit, thereby calculating a difference in gradation between the first image signal and the second image signal; a function of comparing the difference in gray scale with a reference value and outputting a comparison result as a first logic signal; inputting the first logic signal to a control terminal of the first switch; a function of inputting a second logic signal obtained by inverting the logic of the first logic signal to a control terminal of the second switch; The memory circuit has a function of acquiring the first image signal and storing image data of the first coordinates. Drive circuit. 　 In claim 1, the control circuit includes a subtraction circuit, a comparison circuit, a first flip-flop circuit, a first latch circuit, and an inverter circuit; the subtraction circuit has a function of calculating a difference in grayscale between the first image signal input to a first input terminal of the subtraction circuit and the second image signal input to a second input terminal of the subtraction circuit, and transmitting the difference to a first input terminal of the comparison circuit; the comparison circuit has a function of comparing the grayscale difference input to a first input terminal of the comparison circuit with the reference value input to a second input terminal of the comparison circuit, and transmitting a comparison result as the first logic signal to a first input terminal of the first flip-flop circuit; the first flip-flop circuit has a function of holding the first logic signal transmitted to a first input terminal of the first flip-flop circuit, and a function of transmitting the first logic signal to a first input terminal of the first latch circuit when a potential of a second input terminal of the first flip-flop circuit rises or falls; the first latch circuit has a function of holding the first logic signal transmitted to a first input terminal of the first latch circuit, and a function of transmitting the first logic signal to a control terminal of the first switch and an input terminal of the inverter circuit when a first potential is input to a second input terminal of the first latch circuit, the inverter circuit has a function of generating the second logic signal using the first logic signal and transmitting the second logic signal to a control terminal of the second switch; Drive circuit. 　 In claim 2, a second flip-flop circuit, a second latch circuit, and a digital-to-analog conversion circuit; a first wiring is electrically connected to a second input terminal of each of the first flip-flop circuit and the second flip-flop circuit; a second wiring is electrically connected to each of the second input terminals of the first latch circuit and the second latch circuit; the second flip-flop circuit has a function of acquiring the first image signal from a first input terminal of the second flip-flop circuit and holding the first image signal, and a function of transmitting the first image signal to a first input terminal of the second latch circuit when a potential of a second input terminal of the second flip-flop circuit rises or falls; the second latch circuit has a function of holding the first image signal transmitted to a first input terminal of the second latch circuit, and a function of transmitting the first image signal to the digital-to-analog conversion circuit when the first potential is input to a second input terminal of the second latch circuit; the digital-to-analog conversion circuit has a function of converting the first image signal into an analog potential and outputting the analog potential to an input terminal of the amplifier and a first terminal of the second switch; Drive circuit. 　 In claim 3, A level shifter circuit is provided. the level shifter circuit has a function of level-shifting a potential corresponding to the first image signal transmitted from the second latch circuit and transmitting the level-shifted potential to the digital-to-analog conversion circuit. Drive circuit. 　 A pixel circuit comprising: a driver circuit according to any one of claims 1 to 4; a second terminal of the first switch and a first terminal of the second switch are each electrically connected to the pixel circuit; Display device. 　 In claim 5, The pixel circuit includes a first transistor and a second transistor, a first terminal of the first transistor is electrically connected to a second terminal of the first switch and a second terminal of the second switch, a second terminal of the first transistor electrically connected to a gate of the second transistor; a channel formation region of each of the first transistor and the second transistor includes a semiconductor layer including an oxide semiconductor; In a cross-sectional view in a channel width direction, a height of the semiconductor layer of the second transistor is greater than one time a width of the semiconductor layer of the second transistor. Display device. 　 In claim 6, the oxide semiconductor contains one or more selected from indium, zinc, and an element M; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony; Display device. 　 A display device comprising the display device according to claim 7 and a housing. electronic equipment.

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