Display device

Abstract

[Problem] To provide a display device capable of holding a threshold voltage Vth and a signal voltage Vsig in separate capacitors, thereby enabling low power consumption and high image quality. [Solution] The display device of the present disclosure is a display device provided with a pixel circuit. The pixel circuit comprises: a first transistor that samples a signal voltage; a P-channel type second transistor that drives a light-emitting element; an eighth transistor that controls light emission and non-light emission of the light-emitting element; a first capacitor that holds the threshold voltage of the second transistor; a second capacitor that holds the signal voltage written by the first transistor; and a third transistor for disconnecting the first capacitor, which holds the threshold voltage, from the current path. The first capacitor is connected between a fixed potential and the source / drain of the third transistor, and the source of the second transistor is connected to the fixed potential.

Description

display device

[0001] The present disclosure relates to a display device.

[0002] One type of flat display device is a display device that uses, as the light-emitting portion of a pixel circuit, a current-driven electro-optical element whose light-emitting brightness changes depending on the value of a current flowing through the light-emitting portion (light-emitting element). Known current-driven electro-optical elements include, for example, organic EL elements that utilize the electroluminescence (EL) of organic materials and that emit light when an electric field is applied to an organic thin film.

[0003] Generally, in a pixel circuit including an organic EL element, the threshold voltage Vth and the signal voltage Vsig are held in the same capacitance, and the Vth correction operation is performed for each frame, which limits the speed and resolution that can be achieved.

[0004] JP 2015-34861 A

[0005] However, this pixel circuit is affected by capacitive coupling determined by the storage capacitance and auxiliary capacitance when writing a signal, so only a portion of the input signal contributes to light emission, and is also affected by the substrate bias effect because the source potential of the drive transistor fluctuates during the operation from the correction of the threshold voltage Vth to the start of light emission.Furthermore, these pixel circuits are affected by parasitic capacitance added to the gate of the drive transistor by the bootstrap operation when light is emitted, so the corrected threshold voltage Vth cannot be fully maintained, which can result in a decrease in image quality.

[0006] In view of these problems, the present disclosure provides a display device that holds the threshold voltage Vth and the signal voltage Vsig in separate capacitors, thereby enabling low power consumption and high image quality.

[0007] A display device according to a first aspect of the present disclosure is a display device including a pixel circuit, the pixel circuit including a first transistor for sampling a signal voltage, a P-channel second transistor for driving a light-emitting element, an eighth transistor for controlling the light-emitting element to emit or not emit light, a first capacitor for holding a threshold voltage of the second transistor, a second capacitor for holding the signal voltage written by the first transistor, and a third transistor for isolating the first capacitor holding the threshold voltage from a current path, the first capacitor being connected between a fixed potential and the source / drain of the third transistor, and the source of the second transistor being connected to the fixed potential. This allows the pixel circuit to hold these voltages in separate capacitors, eliminating the need to perform a Vth correction operation every frame and enabling the display device to operate at a higher speed and with a higher resolution. Furthermore, the pixel circuit is not affected by the substrate bias effect because the source potential of the second transistor is fixed at a fixed potential. Similarly, because the source potential of the second transistor is fixed to a fixed potential, the pixel circuit is not affected by parasitic capacitance that occurs during bootstrap operation when emitting light, and therefore the corrected threshold voltage and sampled signal voltage are maintained. Furthermore, because the pixel circuit maintains the threshold voltage in the first capacitor and the signal voltage in the second capacitor, it is not affected by capacitive coupling during signal writing, and all of the input signal contributes to light emission. Furthermore, the pixel circuit 20 does not require complex constant design to suppress degradation of image quality due to the substrate bias effect, capacitive coupling during signal writing, and the influence of parasitic capacitance during bootstrap operation when emitting light.

[0008] In addition, in this first aspect, the pixel circuit further includes a fourth transistor that controls a potential between the source / drain of the third transistor and the second capacitor to the fixed potential, the fourth transistor being turned on before a write period of a signal voltage Vsig based on operation of the first transistor begins, and being turned off before a light emission period of the light emitting element begins. This allows the pixel circuit to hold the threshold voltage and the signal voltage in separate capacitors, thereby eliminating the need to perform a Vth correction operation for each frame, and enabling a display device to operate at a higher speed and with a higher resolution.

[0009] In this first aspect, the pixel circuit further includes a sixth transistor connecting the drain of the second transistor and the gate of the second transistor, a seventh transistor controlling the gate potential of the second transistor to an initialization potential, and a fifth transistor controlling the potential between the source / drain of the third transistor and second capacitor 12 based on the gate potential of the second transistor, the fifth transistor and the sixth transistor being turned on before an initialization period for the gate potential of the second transistor begins, and being turned off before a write period for the signal voltage Vsig based on the operation of the first transistor begins. This allows the pixel circuit to fix the initialization potential to a constant value, thereby improving the accuracy of threshold voltage correction.

[0010] In this first aspect, the seventh transistor is turned on before the initialization period and turned off before the threshold voltage correction period of the second transistor, thereby enabling the pixel circuit to fix the initialization potential at a constant value, thereby improving the accuracy of threshold voltage correction.

[0011] In addition, in the first aspect, the display device according to claim 1, wherein the third transistor is turned on before a light emitting period of the light emitting element begins, and is turned off before a write period of a signal voltage Vsig based on the operation of the first transistor begins. This allows the pixel circuit to hold the threshold voltage and the signal voltage in separate capacitors, eliminating the need to perform a Vth correction operation for each frame, and enabling the display device to operate at a higher speed and with a higher resolution.

[0012] In this first aspect, the pixel circuit further includes a sixth transistor connecting the drain of the second transistor and the gate of the second transistor, a seventh transistor controlling the gate potential of the second transistor to an initialization potential, and a ninth transistor controlling the potential between the first capacitor and the source / drain of the third transistor based on the gate potential of the second transistor, wherein the sixth transistor and the ninth transistor are turned on before an initialization period for the gate potential of the second transistor begins, and are turned off before a write period for the signal voltage Vsig based on the operation of the first transistor begins. This allows the pixel circuit to fix the initialization potential to a constant value, thereby improving the accuracy of threshold voltage correction.

[0013] In this first aspect, the seventh transistor is turned on before the initialization period and turned off before the threshold voltage correction period of the second transistor, thereby enabling the pixel circuit to fix the initialization potential at a constant value, thereby improving the accuracy of threshold voltage correction.

[0014] In this first aspect, the third transistor is turned on before the light-emitting element enters a light-emitting period and turned off before the light-extinction period of the light-emitting element enters. This allows the pixel circuit to hold the threshold voltage and the signal voltage in separate capacitors, eliminating the need to perform a Vth correction operation for each frame, and enabling a display device to operate at a higher speed and with a higher resolution.

[0015] In this first aspect, the pixel circuit further includes a fourth transistor that controls the potential between the source / drain of the third transistor and the second capacitor to the fixed potential, and the first transistor and the fourth transistor are turned on before a write period of a signal voltage Vsig based on the operation of the first transistor begins and turned off before a light emission period of the light emitting element begins. This allows the pixel circuit to store the threshold voltage and the signal voltage in separate capacitors, eliminating the need to perform a Vth correction operation every frame and enabling a display device with higher speed and higher resolution. Furthermore, the display device can reduce the number of scanners and achieve a narrower frame.

[0016] In this first aspect, the drain of the first transistor is connected between the source / drain of the third transistor and the second capacitor, and the first transistor is turned on before a write period of a signal voltage Vsig based on operation of the first transistor begins, and turned off before a light emission period of the light emitting element begins. This makes it possible to reduce the number of elements in the pixel circuit, improve pixel density in the display device, and achieve high definition.

[0017] In this first aspect, the pixel circuit further includes a sixth transistor connecting the drain of the second transistor with the gate of the second transistor, a seventh transistor controlling the gate potential of the second transistor to an initialization potential, and a ninth transistor controlling the potential between the first capacitor and the source / drain of the third transistor based on the gate potential of the second transistor, wherein the sixth transistor and the ninth transistor are turned on before an initialization period for the gate potential of the second transistor begins and turned off before the writing period begins. This allows the pixel circuit to fix the initialization potential to a constant value, thereby improving the accuracy of threshold voltage correction.

[0018] In this first aspect, the seventh transistor is turned on before the initialization period, turned off before the threshold voltage correction period of the second transistor, turned on before the writing period, and turned off before the light emission period, thereby enabling the pixel circuit to fix the initialization potential at a constant value, thereby improving the accuracy of threshold voltage correction.

[0019] In this first aspect, the third transistor is turned on before the light-emitting period and turned off before the light-extinction period of the light-emitting element. This allows the pixel circuit to store the threshold voltage and the signal voltage in separate capacitors, eliminating the need to perform a Vth correction operation for each frame, and enabling a display device to operate at a higher speed and with a higher resolution.

[0020] In this first aspect, the pixel circuit further includes a sixth transistor connecting the drain of the second transistor to the gate of the second transistor, and a ninth transistor controlling a potential between the first capacitor and the source / drain of the third transistor based on a gate potential of the second transistor, wherein the gate potential of the second transistor is controlled to an initialization potential supplied via the first transistor. This allows the display device to reduce the number of elements in the pixel circuit by having a Vsig / Vini driver supply the initialization potential via a signal line. Furthermore, the pixel density of the display device can be improved, thereby achieving high definition.

[0021] In addition, in this first aspect, the pixel circuit further includes a fourth transistor that controls a potential between the source / drain of the third transistor and the second capacitor to the fixed potential, the fourth transistor being turned on before a write period of a signal voltage Vsig based on operation of the first transistor begins, and being turned off before a light emission period of the light emitting element begins. This allows the pixel circuit to hold the threshold voltage and the signal voltage in separate capacitors, thereby eliminating the need to perform a Vth correction operation for each frame, and enabling a display device to operate at a higher speed and with a higher resolution.

[0022] In this first aspect, the sixth transistor is turned on before an initialization period for the gate potential of the second transistor and turned off before a write period for a signal voltage Vsig based on the operation of the first transistor, and the first transistor is turned on before the initialization period, turned off before a threshold voltage correction period for the second transistor, turned on before the write period, and turned off before a light emission period for the light emitting element. This allows the display device to reduce the number of elements in the pixel circuit by having the Vsig / Vini driver supply an initialization potential via a signal line. This also improves pixel density in the display device, thereby achieving higher definition.

[0023] In this first aspect, the third transistor is turned on before the light-emitting element enters a light-emitting period and turned off before the light-extinction period of the light-emitting element enters. This allows the pixel circuit to hold the threshold voltage and the signal voltage in separate capacitors, eliminating the need to perform a Vth correction operation for each frame, and enabling a display device to operate at a higher speed and with a higher resolution.

[0024] In addition, according to this first aspect, the display device further includes a tenth transistor that controls the supply of a signal voltage Vsig from the drain of the first transistor to the gate of the second transistor, the first transistor being conductive before an initialization period for the gate potential of the second transistor and a write period for the signal voltage Vsig based on the operation of the first transistor, and being non-conductive before an emission period for the light-emitting element, and the tenth transistor being conductive before the emission period and being non-conductive before an extinction period for the light-emitting element. This allows the pixel circuit to write the signal voltage Vsig to the second capacitor during the threshold correction period, thereby providing a longer write time. Therefore, signal writing is possible even when the wiring connected to the pixel circuit is long and the time constant of the signal voltage is large, making it possible to realize a large display device.

[0025] In addition, in this first aspect, the pixel circuit further includes a fourth transistor that controls a potential between the third transistor and the second capacitor to the fixed potential, the fourth transistor being turned on before the writing period and turned off before the light-emitting period. This allows the pixel circuit to hold a threshold voltage and a signal voltage in separate capacitors, eliminating the need to perform a Vth correction operation for each frame, and enabling a display device to operate at a higher speed and with a higher resolution.

[0026] In this first aspect, the pixel circuit further includes a sixth transistor connecting the drain of the second transistor and the gate of the second transistor, a seventh transistor controlling the gate potential of the second transistor to an initialization potential, and a ninth transistor controlling the potential between the first capacitor and the source / drain of the third transistor based on the gate potential of the second transistor, wherein the sixth transistor and the ninth transistor are turned on before the initialization period begins and turned off after the threshold voltage correction period of the second transistor ends. This allows the pixel circuit to fix the initialization potential to a constant value, thereby improving the accuracy of threshold voltage correction.

[0027] FIG. 1 is a schematic configuration diagram of a display device according to a first embodiment. FIG. 2 is an example of a circuit diagram of a pixel circuit according to the first embodiment. FIG. 3 is an example of a circuit diagram showing a timing chart of a pixel circuit according to the first embodiment and a conductive state of the corresponding pixel circuit. FIG. 4 is another example of a circuit diagram showing a conductive state of a pixel circuit according to the first embodiment. FIG. 5 is an example of a circuit diagram of a pixel circuit according to a second embodiment. FIG. 6 is an example of a circuit diagram showing a timing chart of a pixel circuit according to the second embodiment and a conductive state of the corresponding pixel circuit. FIG. 7 is another example of a circuit diagram showing a conductive state of a pixel circuit according to the second embodiment. FIG. 8 is an example of a circuit diagram of a pixel circuit according to a third embodiment. FIG. 9 is an example of a circuit diagram showing a timing chart of a pixel circuit according to the third embodiment and a conductive state of the corresponding pixel circuit. FIG. 10 is another example of a circuit diagram showing a conductive state of a pixel circuit according to the third embodiment. FIG. 11 is an example of a circuit diagram of a pixel circuit according to a fourth embodiment. FIG. 12 is an example of a circuit diagram showing a timing chart of a pixel circuit according to the fourth embodiment and a conductive state of the corresponding pixel circuit. FIG. 13 is another example of a circuit diagram showing a conductive state of a pixel circuit according to the fourth embodiment. 10 is an example of a circuit diagram showing a timing chart of a pixel circuit and a conduction state of the corresponding pixel circuit in the fifth embodiment. 11 is another example of a circuit diagram showing a conduction state of a pixel circuit in the fifth embodiment. 12 is another example of a circuit diagram showing a conduction state of a pixel circuit in the sixth embodiment. 13 is an example of a circuit diagram showing a timing chart of a pixel circuit and a conduction state of the corresponding pixel circuit in the sixth embodiment. 14 is another example of a circuit diagram showing a conduction state of a pixel circuit in the sixth embodiment. 15 is a diagram showing the appearance of a head-mounted display, which is an example of an electronic device to which the display device according to the first to sixth embodiments is applied. 16 is a diagram showing the appearance of a head-mounted display, which is another example of an electronic device to which the display device according to the first to sixth embodiments is applied. 17 is a diagram showing the appearance of a digital camera, which is an example of an electronic device to which the display device according to the first to sixth embodiments is applied. 18 is a diagram showing the appearance of a television, which is an example of an electronic device to which the display device according to the first to sixth embodiments is applied. 19 is a diagram showing the appearance of a smartphone, which is an example of an electronic device to which the display device according to the first to sixth embodiments is applied. 19 is a diagram showing an example of a vehicle to which the display device according to the first to sixth embodiments is applied.

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The following description will focus on the main components of a display device, etc. However, the display device, etc. may have components or functions that are not shown or described. The following description does not exclude components or functions that are not shown or described.

[0029] First Embodiment FIG. 1 is a schematic diagram of a display device according to a first embodiment.

[0030] 1 is a block diagram showing the overall configuration of an embodiment of a display device 10 according to the present invention. A television device 140, which will be described later, is an example of the display device 10. As shown in the figure, the display device 10 in this embodiment is an active matrix type, and is composed of a pixel array 30, which is the main component, and a peripheral circuit section. The peripheral circuit section includes a Vsig driver 61, a DS scanner 41, a W1S scanner 42, a W2S scanner 43, an AZ1 scanner 51, and an AZ2 scanner 52, etc.

[0031] In this example, an active matrix organic EL display device will be described, which uses organic EL elements, which are current-driven electro-optical elements whose light emission luminance changes according to the value of the current flowing through the device, as the light-emitting portions (light-emitting elements) of the pixel circuits. Hereinafter, the "pixel circuit" may be simply referred to as the "pixel."

[0032] The pixel array 30 is composed of pixels R, G, and B arranged in a matrix at the intersections of row-like scanning lines W1S and W2S and column-like signal lines Data. Each of the pixels R, G, and B is composed of a pixel circuit 20. The signal lines Data are voltage-driven by a Vsig driver 61. In other words, the Vsig driver 61 supplies a signal voltage Vsig to the signal lines Data.

[0033] In this example, the pixel circuit 20 is connected to two scanning lines. The scanning line W1S is scanned by a W1S scanner 42. The scanning line W2S is scanned by a W2S scanner 43. The control signals supplied to these scanning lines have different timings. In addition, other scanning lines DS, AZ1S, and AZ2S are wired in parallel to the scanning lines W1S and W2S. The scanning line DS is scanned by a DS scanner 41. The DS scanner 41 controls the light-emitting period of the light-emitting elements included in each pixel. The scanning lines AZ1S and AZ2S are scanned by an AZ1 scanner 51 and a ZA2 scanner 52, respectively.

[0034] The DS scanner 41, W1S scanner 42, W2S scanner 43, AZ1 scanner 51, and AZ2 scanner 52 together form a scanner section, which sequentially scans the rows of the pixel circuits 20 for each horizontal period.

[0035] FIG. 2 is an example of a circuit diagram of a pixel circuit according to the first embodiment.

[0036] For the sake of explanation, Figure 2 focuses on one pixel circuit 20 included in the pixel array 30 shown in Figure 1. As shown in Figure 2, the pixel circuit 20 in this embodiment includes a first transistor 22, a second transistor 23, a third transistor 24, a fourth transistor 25, a fifth transistor 26, a sixth transistor 27, a seventh transistor 28, and an eighth transistor 29 as elements that constitute a circuit that drives an organic EL element 21, as well as a first capacitor 11 and a second capacitor 12. The first transistor 22 is also called a sampling transistor, the second transistor 23 is also called a drive transistor, and the eighth transistor 29 is also called a light-emission control transistor. The first transistor 22 and the third transistor 24 to the seventh transistor 28 are also called switching transistors.

[0037] In this example, it is assumed that the transistors are formed on a semiconductor such as silicon, rather than on an insulator such as a glass substrate, and an example will be described in which a P-channel transistor is used as the second transistor 23. Similarly, the second transistor 23 to the eighth transistor 29 will also be described as an example in which P-channel transistors are used. The second transistor 23 to the eighth transistor 29 are not limited to P-channel transistors. For example, the second transistor 23 to the seventh transistor 28 may be N-channel transistors, or may be configured with a mixture of P-channel and N-channel transistors.

[0038] In addition, peripheral circuits such as a Vsig driver 61, a DS scanner 41, a W1S scanner 42, a W2S scanner 43, an AZ1 scanner 51, and an AZ2 scanner 52 are connected to the pixel circuit 20, and supply control signals to each scanning line to control the light emission period of the organic EL element 21 included in the pixel circuit 20.

[0039] In this example, potential V1 indicates the potential between the first capacitor 11 and one of the source / drain terminals of the third transistor 24, and potential V2 indicates the gate potential of the second transistor 23.

[0040] The first transistor 22 samples the signal voltage Vsig supplied from the Vsig driver 61 through the signal line Data, thereby writing the signal to the second capacitor 12. The source of the first transistor 22 is connected to the signal line Data, and the drain is connected to the second capacitor 12, the source / drain of the fifth transistor 26, and the gate of the second transistor 23. The gate of the first transistor 22 is connected to the W1S scanner 42 through the scanning line W1S.

[0041] When a drive voltage is applied between the drain and source of the second transistor 23, the second transistor 23 applies a current to the organic EL element 21 according to the gate-source voltage, thereby driving the organic EL element 21. One source of the second transistor 23 is connected to a fixed potential VCC. The drain of the second transistor 23 is connected to one source / drain of the sixth transistor 27 and also connected to the anode side of the organic EL element 21 via one source / drain of the eighth transistor 29. The cathode of the organic EL element 21 is grounded. The cathode ground potential of the organic EL element 21 may be represented by Vcath. The gate of the second transistor 23 is connected to the second capacitor 12.

[0042] The third transistor 24 separates the first capacitor 11, which holds the threshold voltage, from the current path. One source / drain of the third transistor 24 is connected to a fixed potential VCC via the first capacitor 11, and the other source / drain of the third transistor 24 is connected to the second capacitor 12. In addition, the gate of the third transistor 24 is connected to the W2S scanner 43 via the scanning line W2S.

[0043] The fourth transistor 25 controls the potential between the other drain / source of the third transistor 24 and the second capacitor 12 to a fixed potential VCC. One source / drain of the fourth transistor 25 is connected to the fixed potential VCC, and the other source / drain is connected between the second capacitor 12 and the third transistor 24. In addition, the gate of the fourth transistor 25 is connected to the W1S scanner 42 via the scanning line W1S.

[0044] The fifth transistor 26 controls the potential between the other source / drain of the third transistor 24 and the second capacitor 12 to a potential Vini or VCC-Vth, which is an initialization potential, based on the gate potential of the second transistor 23. The fifth transistor 26 connects the gap between the other source / drain of the third transistor 24 and the second capacitor 12 to ground, or connects the gap between the other source / drain of the third transistor 24 and the second capacitor 12 to the gate of the second transistor 23.

[0045] The sixth transistor 27 connects the drain of the second transistor 23 to the ground or connects the drain of the second transistor 23 to the gate of the second transistor 23. One source / drain of the sixth transistor 27 is connected to the drain of the second transistor 23, and the other source / drain of the sixth transistor 27 is connected to the ground via the seventh transistor 28 and is connected to the second capacitor 12 via the gate of the second transistor 23. In addition, the gate of the sixth transistor 27 is connected to the AZ1 scanner 51 via the scanning line AZ1S.

[0046] The seventh transistor 28 controls the gate potential of the second transistor 23 to the potential Vini and writes the potential Vini to the second capacitor 12. One source / drain of the seventh transistor 28 is connected to the other source / drain of the sixth transistor 27 and the gate of the second transistor 23, and the other source / drain of the seventh transistor 28 is grounded to Vini. In addition, the gate of the seventh transistor 28 is connected to the AZ2 scanner 52 via the scanning line AZ2S.

[0047] The eighth transistor 29 controls whether the organic EL element 21 emits light or not. One source / drain of the eighth transistor 29 is connected to the other source / drain of the second transistor 23, and the other source / drain of the eighth transistor 29 is connected to the anode of the organic EL element 21. In addition, the gate of the eighth transistor 29 is connected to a DS scanner 41 via a scanning line DS.

[0048] The first capacitor 11 holds the threshold voltage Vth of the second transistor 23. One end of the first capacitor 11 is connected to a fixed potential, and the other end is connected to one of the source / drain of the third transistor 24.

[0049] The second capacitor 12 holds the signal voltage Vsig written by the first transistor 22. One end of the second capacitor is connected to the other source / drain of the third transistor 24, and the other end is connected to the gate of the second transistor 23.

[0050] FIG. 3 is an example of a timing chart of a pixel circuit according to the first embodiment and a circuit diagram showing the conduction state of the corresponding pixel circuit.

[0051] The timing chart of FIG. 3A shows potentials V1 and V2 in addition to potentials VW1S, VW2S, VAZ1, VAZ2, VData, and VDS on the scanning lines W1S, W2S, AZ1S, AZ2S, signal lines Data, and DS.

[0052] 3B shows the conduction state of each transistor during the light emission period, the extinction period, the initialization period, the threshold voltage correction period, the write period, and the light emission period. For the sake of explanation, in FIG. 3B, transistors in a conducting state are shown with their switches turned on, and transistors in a non-conducting state are shown with their switches turned off.

[0053] The light-emitting period is a period during which the organic EL element 21 is controlled to be in an emitting state. The light-extinguishing period is a period during which the organic EL element 21 is controlled to be in an extinguished state. The threshold voltage correction period is a period during which threshold voltage correction control is performed to correct variations in the threshold voltage of the second transistor 23. The initialization period is a period during which the potential V2 of the second transistor 23 is set to the potential Vini and the source potential Vs of the second transistor 23 is controlled to the fixed potential VCC. The write period is a period during which writing of the signal voltage Vsig to the second capacitor 12 is controlled based on the first transistor 22.

[0054] In this example, the first transistor 22 to the eighth transistor 29 are P-channel transistors, and therefore a low potential state of the scanning line W1S, etc. results in a conductive state, and a high potential state of the scanning line W1S, etc. results in a non-conductive state. Furthermore, the signals that drive each transistor in the pixel circuit 20 are active when the scanning line, etc., is in a conductive state, and are inactive when the scanning line, etc., is in a non-conductive state.

[0055] Before the light emission period from time T1 to T2 begins, the potential VDS of the scanning line DS and the voltage VW2S of the scanning line W2S transition from high to low, and the eighth transistor 29 and the third transistor 24 become conductive. During the light emission period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). Here, in the second transistor 23, W is the channel width, L is the channel length, Cox is the gate insulating film capacitance per unit area, μ is the mobility, and Vth is the threshold. Vgs=Vsig+Vth (1) Ids=½×μ×W / L×Cox×(Vgs-Vth)^2 (2)

[0056] The light emission current Iel is expressed by the following equation (3): Iel=1 / 2×μ×W / L×Cox×[(Vsig+Vth)−Vth]^2=1 / 2×μ×W / L×Cox×(Vsig)^2 (3)

[0057] The second transistor 23 is, for example, a TFT with a polycrystalline silicon thin film as an active layer. Low-temperature polysilicon crystallized by laser annealing is often used as the polycrystalline silicon thin film. Generally, low-temperature polysilicon TFTs tend to have variations in threshold voltage Vth and mobility μ for each device. In other words, the threshold voltage Vth and mobility μ of the second transistor 23 differ for each individual pixel circuit 20.

[0058] Before the light-off period from time T2 to time T3 begins, the potential VDS of the scanning line DS transitions from low to high, and the eighth transistor 29 enters a non-conductive state, thereby causing the organic EL element 21 to enter a non-emitting state.

[0059] Before entering the initialization period from time T3 to time T4, the potential VAZ1 of the scanning line AZ1S and the potential VAZ2 of the scanning line AZ2S transition from high to low, and the fifth transistor 26, the sixth transistor 27, and the seventh transistor 28 become conductive, thereby initializing the potentials V1 and V2 and setting them to the potential Vini.

[0060] Before the threshold voltage correction period from time T4 to time T5 begins, the scanning line AZ2S transitions from a low potential to a high potential, and the seventh transistor 28 enters a non-conducting state. During the threshold voltage correction period, a drain current Ids flows from the fixed potential VCC, charging the first capacitor 11. This causes the potential V2 to rise, and when the potential difference between the source potential Vs and the gate potential V2 of the second transistor 23 reaches the threshold voltage Vth, the rise in the potential V2 stops and the potential V1 is set to VCC-Vth. This correction operation writes a potential to cancel the threshold voltage Vth of the second transistor 23 to the first capacitor 11. Because the threshold voltage Vth of the second transistor 23 is canceled by the correction operation, any variations in Vth have no effect.

[0061] Before entering the write period from time T5 to time T6, the potential VW1S of the scanning line W1S transitions from a high potential to a low potential, and the first transistor 22 and the fourth transistor 25 are turned on. Furthermore, the scanning lines W2S and AZ1S transition from a low potential to a high potential, and the third transistor 24, the fifth transistor 26, and the sixth transistor 27 are turned off. This sets the potential between the other drain / source of the third transistor 24 and the second capacitor 12 to the fixed potential VCC. Furthermore, a signal voltage Vsig is written into the pixel circuit 20 from the signal line Data. The write operation of the signal voltage Vsig by the first transistor 22 sets the potential V2 to VCC-Vsig.

[0062] Before the light-emitting period from time T6 to T7 begins, the potential VDS of the scanning line DS and the voltage VW2S of the scanning line W2S transition from high to low, causing the eighth transistor 29 and the third transistor 24 to enter a conductive state. Furthermore, the voltage VW2S of the scanning line W1S transitions from low to high, causing the fourth transistor 25 to enter a non-conductive state. At this time, the potential V2 becomes VCC-Vsig-Vth. Furthermore, during the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). Furthermore, the light-emitting current Iel is expressed by equation (3).

[0063] FIG. 4 is another example of a circuit diagram showing the conductive state of the pixel circuit in the first embodiment.

[0064] In this example, the threshold voltage Vth corrected in the previous frame is held in the first capacitor 11, and the signal voltage Vsig is written to the second capacitor 12 in the next frame. Unlike the case of Figure 3B, the pixel circuit 20 does not perform initialization or threshold correction. Furthermore, the operations during the light-emitting period, light-extinction period, and writing period are the same as those in Figure 3B, and therefore will not be described here.

[0065] After the write period ends and before the light emission period begins, the potential VDS of the scanning line DS and the voltage VW2S of the scanning line W2S transition from high to low, causing the eighth transistor 29 and the third transistor 24 to enter a conductive state. Furthermore, the potential VW1S of the scanning line W1S transitions from low to high, causing the fourth transistor 25 to enter a non-conductive state. With the third transistor 24 entering a conductive state, the potential V2 becomes VCC-Vsig-Vth based on the threshold voltage Vth held by the first capacitor 11 in the previous frame.

[0066] According to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12. Because the pixel circuit 20 can hold these voltages in separate capacitors, it is not necessary to perform a Vth correction operation for each frame, and the display device 10 can be made to operate at a higher speed and with a higher resolution.

[0067] Furthermore, according to this embodiment, the pixel circuit 20 is not affected by the substrate bias effect because the source potential of the second transistor 23 is fixed at the fixed potential VCC. Similarly, because the source potential of the second transistor 23 is fixed at the fixed potential VCC, the pixel circuit 20 is not affected by the parasitic capacitance in the bootstrap operation during light emission because the rise in the gate potential V2 of the second transistor 23 due to capacitive coupling does not occur.

[0068] Furthermore, according to this embodiment, the pixel circuit 20 can fix the potential Vini to a constant value, thereby improving the accuracy of threshold voltage correction.

[0069] Furthermore, according to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12, so that the pixel circuit 20 is not affected by capacitive coupling when writing a signal, and all of the input signal contributes to light emission.

[0070] Furthermore, according to this embodiment, the pixel circuit 20 does not require complex constant design to suppress degradation of image quality due to the influence of the substrate bias effect, capacitive coupling during signal writing, and parasitic capacitance in the bootstrap operation during light emission.

[0071] Second Embodiment FIG. 5 is an example of a circuit diagram of a pixel circuit according to a second embodiment.

[0072] As shown in FIG. 5 , the pixel circuit 20 in this embodiment includes a first transistor 22, a second transistor 23, a third transistor 24, a fourth transistor 25, a sixth transistor 27, a seventh transistor 28, an eighth transistor 29, a first capacitor 11, a second capacitor 12, and a ninth transistor 13 as elements that constitute a circuit that drives an organic EL element 21.

[0073] Unlike the first embodiment, the display device 10 in this embodiment includes a WS scanner 44 instead of the W1S scanner 42 and the W2S scanner 43. Therefore, the pixel circuits 20 are connected to the WS scanner 44 instead of being connected to the two scanners, the W1S scanner 42 and the W2S scanner 43.

[0074] Also, unlike the first embodiment, the pixel circuit 20 in this embodiment includes a ninth transistor 13 instead of the fifth transistor 26 .

[0075] The ninth transistor 13 controls the potential between the first capacitor 11 and one of the sources / drains of the third transistor 24 based on the gate potential of the second transistor 23. One of the sources / drains of the ninth transistor 13 is connected between the first capacitor 11 and one of the sources / drains of the third transistor 24. The other source / drain of the ninth transistor 13 is connected to the gate of the second transistor 23. The gate of the ninth transistor 13 is connected to the AZ1 scanner 51 via the scanning line AZ1S.

[0076] One source / drain of the first transistor 22 is connected to the signal line Data, and the other source / drain is connected to the second capacitor 12 and the gate of the second transistor 23. Also, unlike the first embodiment, the gate of the first transistor 22 is connected to the WS scanner 44 via the scanning line WS.

[0077] One of the source / drain terminals of the third transistor 24 is connected to a fixed potential VCC via the first capacitor 11, and the other of the source / drain terminals of the third transistor 24 is connected to the second capacitor 12. Also, unlike the first embodiment, the gate of the third transistor 24 is connected to the DS scanner 41 via the scanning line DS.

[0078] One of the source / drain terminals of the fourth transistor 25 is connected to a fixed potential VCC, and the other of the source / drain terminals is connected between the second capacitor 12 and the third transistor 24. Also, unlike the first embodiment, the gate of the fourth transistor 25 is connected to the WS scanner 44 via the scanning line WS.

[0079] FIG. 6 is an example of a timing chart of a pixel circuit according to the second embodiment and a circuit diagram showing the conduction state of the corresponding pixel circuit.

[0080] The timing chart of FIG. 6A shows potentials V1 and V2 in addition to potentials VWS, VAZ1, VAZ2, VData, and VDS on the scanning line WS, scanning line AZ1S, scanning line AZ2S, signal line Data, and scanning line DS.

[0081] Before the light-emitting period from time T1 to time T2 begins, the potential VDS of the scanning line DS transitions from high to low, and the eighth transistor 29 and the third transistor 24 become conductive. During the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs to the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). The light-emitting current Iel is expressed by equation (3).

[0082] Before the light-off period from time T2 to time T3 begins, the potential VDS of the scanning line DS transitions from a low potential to a high potential, and the eighth transistor 29 and the third transistor 24 become non-conductive, thereby causing the organic EL element 21 to become non-emitting.

[0083] Before entering the initialization period from time T3 to time T4, the potential VAZ1 of the scanning line AZ1S and the potential VAZ2 of the scanning line AZ2S transition from high to low, and the sixth transistor 27, the ninth transistor 13, and the seventh transistor 28 become conductive, thereby initializing the potentials V1 and V2 and setting them to the potential Vini.

[0084] Before the threshold voltage correction period from time T4 to time T5 begins, the scanning line AZ2S transitions from a low potential to a high potential, and the seventh transistor 28 enters a non-conducting state. During the threshold voltage correction period, a drain current Ids flows from the fixed potential VCC, charging the first capacitor 11. This causes the potential V2 to rise, and when the potential difference between the source potential Vs and the gate potential V2 of the second transistor 23 becomes just the threshold voltage Vth, the rise in the potential V2 stops and the potential V1 is set to VCC-Vth. This correction operation writes a potential to the first capacitor 11 to cancel the threshold voltage Vth of the second transistor 23.

[0085] Before entering the write period from time T5 to T6, the potential VWS of the scanning line WS transitions from high to low, and the first transistor 22 and the fourth transistor 25 become conductive. In addition, the scanning line AZ1S transitions from low to high, and the ninth transistor 13 and the sixth transistor 27 become non-conductive. As a result, the signal voltage Vsig is written into the pixel circuit 20 from the signal line Data. This operation of writing the signal voltage Vsig by the first transistor 22 causes the potential V2 to become VCC-Vsig.

[0086] Before the light-emitting period from time T6 to T7 begins, the potential VWS of the scanning line WS transitions from low to high, causing the first transistor 22 and the fourth transistor 25 to become non-conductive. Furthermore, the potential VDS of the scanning line DS transitions from high to low, causing the third transistor 24 and the eighth transistor 29 to become conductive. At this time, the potential V2 becomes VCC-Vsig-Vth. Furthermore, during the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). Furthermore, the light-emitting current Iel is expressed by equation (3).

[0087] FIG. 7 is another example of a circuit diagram showing the conductive state of the pixel circuit according to the second embodiment.

[0088] In this example, the threshold voltage Vth corrected in the previous frame is held in the first capacitor 11, and the signal voltage Vsig is written to the second capacitor 12 in the next frame. Unlike the case of Fig. 6B , the pixel circuit 20 does not perform initialization or threshold correction. Furthermore, the operations during the light-emitting period, light-extinction period, and writing period are the same as those in Fig. 6B , and therefore will not be described here.

[0089] After the write period ends, during the light emission period, the potential VWS of the scanning line WS transitions from a low potential to a high potential, and the first transistor 22 and the fourth transistor 25 are brought into a non-conductive state. Also, the potential VDS of the scanning line DS transitions from a high potential to a low potential, and the third transistor 24 and the eighth transistor 29 are brought into a conductive state. As the third transistor 24 is brought into a conductive state, the potential V2 becomes VCC-Vsig-Vth based on the threshold voltage Vth held in the first capacitor 11 in the previous frame.

[0090] According to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12. Because the pixel circuit 20 can hold these voltages in separate capacitors, it is not necessary to perform a Vth correction operation for each frame, and the display device 10 can be made to operate at a higher speed and with a higher resolution.

[0091] Furthermore, according to this embodiment, the pixel circuit 20 is not affected by the substrate bias effect because the source potential of the second transistor 23 is fixed at the fixed potential VCC. Similarly, because the source potential of the second transistor 23 is fixed at the fixed potential VCC, the pixel circuit 20 is not affected by the parasitic capacitance due to the bootstrap operation during light emission because the gate potential V2 of the second transistor 23 does not increase due to capacitive coupling.

[0092] Furthermore, according to this embodiment, the pixel circuit 20 can fix the initialization potential Vini to a constant value, thereby improving the accuracy of threshold voltage correction.

[0093] Furthermore, according to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12, so that the pixel circuit 20 is not affected by capacitive coupling when writing a signal, and all of the input signal contributes to light emission.

[0094] Furthermore, according to this embodiment, the pixel circuit 20 does not require complex constant design to suppress degradation of image quality due to the influence of parasitic capacitance caused by the substrate bias effect, capacitive coupling during signal writing, and bootstrap operation during light emission.

[0095] Furthermore, according to this embodiment, the pixel circuit 20 shares the gate of the first transistor 22 and the gate of the fourth transistor 25 and connects them to the WS scanner 44. The pixel circuit 20 also connects the gate of the ninth transistor 13 to the AZ1 scanner 51. This allows the display device 10 to reduce the number of scanners and achieve a narrower frame.

[0096] Third Embodiment FIG. 8 is an example of a circuit diagram of a pixel circuit according to a third embodiment.

[0097] As shown in Figure 8, the pixel circuit 20 in this embodiment includes a first transistor 22, a second transistor 23, a third transistor 24, a sixth transistor 27, a seventh transistor 28, an eighth transistor 29, a first capacitor 11, a second capacitor 12, and a ninth transistor 13 as elements that constitute a circuit that drives an organic EL element 21.

[0098] Unlike the first embodiment, the display device 10 in this embodiment includes a WS scanner 44 instead of the W1S scanner 42 and the W2S scanner 43. Therefore, the pixel circuits 20 are connected to the WS scanner 44 instead of being connected to the two scanners, the W1S scanner 42 and the W2S scanner 43.

[0099] Also, unlike the first embodiment, the pixel circuit 20 in this embodiment includes a ninth transistor 13 instead of the fourth transistor 25 and the fifth transistor 26 .

[0100] Furthermore, potential V1' indicates the potential between one source / drain of the third transistor 24 and the first capacitor 11. Furthermore, potential V2' indicates the potential between the other source / drain of the third transistor 24 and the second capacitor 12. Furthermore, potential V3' indicates the potential of the gate of the second transistor 23.

[0101] The source of the first transistor 22 is connected to the signal line Data, and, unlike the first embodiment, the drain is connected between the other source / drain of the third transistor 24 and the second capacitor 12. In addition, the gate of the first transistor 22 is connected to the WS scanner 44 via the scanning line WS.

[0102] One of the source / drain terminals of the third transistor 24 is connected to a fixed potential VCC via the first capacitor 11, and the other of the source / drain terminals of the third transistor 24 is connected to the second capacitor 12. Also, unlike the first embodiment, the gate of the third transistor 24 is connected to the DS scanner 41 via the scanning line DS.

[0103] FIG. 9 is an example of a timing chart of a pixel circuit according to the third embodiment and a circuit diagram showing the conduction state of the corresponding pixel circuit.

[0104] The timing chart of FIG. 9A shows potentials V1' to V3' in addition to potentials VWS, VAZ1, VAZ2, VData, and VDS on the scanning line WS, scanning line AZ1S, scanning line AZ2S, signal line Data, and scanning line DS.

[0105] FIG. 9B shows the conduction state of each transistor during the light emission period, the extinction period, the initialization period, the threshold voltage correction period, the writing period, and the light emission period.

[0106] Before the light-emitting period from time T1 to T2 begins, the potential VDS of the scanning line DS transitions from high to low, and the eighth transistor 29 and the third transistor 24 become conductive. During the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). The light-emitting current Iel is expressed by equation (3).

[0107] Before the light-off period from time T2 to time T3 begins, the potential VDS of the scanning line DS transitions from a low potential to a high potential, and the eighth transistor 29 and the third transistor 24 become non-conductive, thereby causing the organic EL element 21 to become non-emitting.

[0108] Before entering the initialization period from time T3 to time T4, the scanning lines AZ1S and AZ2S transition from high potential to low potential, and the sixth transistor 27, the seventh transistor 28, and the ninth transistor 13 become conductive, thereby initializing the potentials V1' and V3' and setting them to the potential Vini.

[0109] Before the threshold voltage correction period from time T4 to time T5 begins, the potential VAZ2 of the scanning line AZ2S transitions from a low potential to a high potential, and the seventh transistor 28 enters a non-conducting state. During the threshold voltage correction period, a drain current Ids flows from the fixed potential VCC, charging the first capacitor 11. This causes the potential V3' to rise, and when the potential difference between the source potential Vs and the gate potential V3' of the second transistor 23 reaches the threshold voltage Vth, the rise in the potential V3' stops and the potential V1' is set to VCC-Vth. This correction operation writes a potential to the first capacitor 11 to cancel the threshold voltage Vth of the second transistor 23.

[0110] Before entering the write period from time T5 to T6, the potential VWS of the scanning line WS and the potential VAZ2 of the scanning line AZ2S transition from high to low, and the first transistor 22 and the seventh transistor 28 become conductive. Furthermore, the scanning line AZ1S transitions from low to high, and the sixth transistor 27 and the ninth transistor 13 become non-conductive. As a result, the potential V1' remains set to VCC-Vth, and the potential V3' is set to the potential Vini. Furthermore, the signal voltage Vsig is written into the pixel circuit 20, and the potential difference between the potential V2' and the potential V3' becomes Vsig.

[0111] Before the light-emitting period from time T6 to T7 begins, the potential VWS of the scanning line WS and the potential VAZ2 of the scanning line AZ2S transition from low to high, causing the first transistor 22 and the seventh transistor 28 to enter a non-conductive state. Furthermore, the potential VDS of the scanning line DS transitions from high to low, causing the third transistor 24 and the eighth transistor 29 to enter a conductive state. At this time, the potential V3' becomes VCC-Vsig-Vth. Furthermore, during the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). Furthermore, the light-emitting current Iel is expressed by equation (3).

[0112] FIG. 10 is another example of a circuit diagram showing the conductive state of the pixel circuit according to the third embodiment.

[0113] In this example, the threshold voltage Vth corrected in the previous frame is held in the first capacitor 11, and the signal voltage Vsig is written to the second capacitor 12 in the next frame. Unlike the case of Figure 9B, the pixel circuit 20 does not perform initialization or threshold correction. Furthermore, the operations during the light-emitting period, light-extinction period, and writing period are the same as those in Figure 9B, and therefore will not be described here.

[0114] After the end of the writing period, during the light emission period, the potential VWS of the scanning line WS and the potential VAZ2 of the scanning line AZ2S transition from low to high, and the first transistor 22 and the seventh transistor 28 become non-conductive. Furthermore, the potential VDS of the scanning line DS transitions from high to low, and the third transistor 24 and the eighth transistor 29 become conductive. With the third transistor 24 in the conductive state, the potential V3' becomes VCC-Vsig-Vth based on the threshold voltage Vth held by the first capacitor 11 in the previous frame.

[0115] According to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12. Because the pixel circuit 20 can hold these voltages in separate capacitors, it is not necessary to perform a Vth correction operation for each frame, and the display device 10 can be made to operate at a higher speed and with a higher resolution.

[0116] Furthermore, according to this embodiment, the pixel circuit 20 is not affected by the substrate bias effect because the source potential of the second transistor 23 is fixed at the fixed potential VCC. Similarly, because the source potential of the second transistor 23 is fixed at the fixed potential VCC, the pixel circuit 20 is not affected by the parasitic capacitance due to the bootstrap operation during light emission because the gate potential V2 of the second transistor 23 does not increase due to capacitive coupling.

[0117] Furthermore, according to this embodiment, the pixel circuit 20 can fix the potential Vini to a constant value, thereby improving the accuracy of threshold voltage correction.

[0118] Furthermore, according to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12, so that the pixel circuit 20 is not affected by capacitive coupling when writing a signal, and all of the input signal contributes to light emission.

[0119] Furthermore, according to this embodiment, the pixel circuit 20 does not require complex constant design to suppress degradation of image quality due to the influence of parasitic capacitance caused by the substrate bias effect, capacitive coupling during signal writing, and bootstrap operation during light emission.

[0120] Furthermore, according to this embodiment, the pixel circuit 20 writes the signal voltage Vsig to the potential V2', which is the potential between the other source / drain of the third transistor and the second capacitor 12, and sets the potential V3', which is the gate potential of the second transistor 23, to the potential Vini, thereby making it possible to reduce the number of elements. This improves the pixel density in the display device 10 and enables higher definition to be achieved.

[0121] Fourth Embodiment FIG. 11 is an example of a circuit diagram of a pixel circuit according to a fourth embodiment.

[0122] As shown in FIG. 11 , the pixel circuit 20 in this embodiment includes a first transistor 22, a second transistor 23, a third transistor 24, a fourth transistor 25, a sixth transistor 27, an eighth transistor 29, a first capacitor 11, a second capacitor 12, and a ninth transistor 13 as elements that constitute a circuit that drives an organic EL element 21.

[0123] Unlike the first embodiment, the display device 10 in this embodiment includes a WS scanner 44 instead of a W1S scanner 42 and a W2S scanner 43. Therefore, the pixel circuits 20 are connected to the WS scanner 44 via the scanning line WS. Furthermore, the display device 10 includes an AZ scanner 53 instead of an AZ1 scanner 51 and an AZ2 scanner 52. Therefore, the pixel circuits 20 are connected to the AZ scanner 53 via the scanning line AZS. Furthermore, the display device 10 includes a Vsig / Vini driver 62 instead of a Vsig driver 61. Therefore, the pixel circuits 20 are connected to the Vsig / Vini driver 62.

[0124] Unlike the first embodiment, the pixel circuit 20 in this embodiment includes a ninth transistor 13 instead of the fifth transistor 26 and the seventh transistor 28 .

[0125] One source / drain of the first transistor 22 is connected to the signal line Data, and the other source / drain is connected to the second capacitor 12 and the gate of the second transistor 23. Also, unlike the first embodiment, the gate of the first transistor 22 is connected to the WS scanner 44 via the scanning line WS.

[0126] One of the source / drain terminals of the third transistor 24 is connected to a fixed potential VCC via the first capacitor 11, and the other of the source / drain terminals of the third transistor 24 is connected to the second capacitor 12. Also, unlike the first embodiment, the gate of the third transistor 24 is connected to the DS scanner 41 via the scanning line DS.

[0127] The sixth transistor 27 connects the drain of the second transistor 23 to the gate of the second transistor 23. One source / drain of the sixth transistor 27 is connected to the drain of the second transistor 23, and the other source / drain of the sixth transistor 27 is connected to the second capacitor 12 and the ninth transistor 13 via the gate of the second transistor 23. In addition, the gate of the sixth transistor 27 is connected to the AZ scanner 53 via the scanning line AZS.

[0128] In this example, the other source / drain of the sixth transistor 27 is not grounded, but instead a Vsig / Vini driver 62 supplies a potential Vini via a signal line Data.

[0129] FIG. 12 is an example of a timing chart of a pixel circuit according to the fourth embodiment and a circuit diagram showing the conduction state of the corresponding pixel circuit.

[0130] The timing chart of FIG. 12A shows potentials V1 and V2 in addition to the potentials VWS, VAZ, VData, and VDS on the scanning line WS, scanning line AZ, signal line Data, and scanning line DS.

[0131] FIG. 12B shows the conduction state of each transistor during the light emission period, the extinction period, the initialization period, the threshold voltage correction period, the writing period, and the light emission period.

[0132] Before the light-emitting period from time T1 to time T2 begins, the potential VDS of the scanning line DS transitions from a high potential to a low potential, and the third transistor 24 and the eighth transistor 29 become conductive. During the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs to the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). The light-emitting current Iel is expressed by equation (3).

[0133] Before the light-off period from time T2 to time T3 begins, the potential VDS of the scanning line DS transitions from a low potential to a high potential, and the third transistor 24 and the eighth transistor 29 enter a non-conductive state, thereby causing the organic EL element 21 to enter a non-emitting state.

[0134] Before the initialization period from time T3 to time T4 begins, the voltage VAZ of the scanning line AZS transitions from high to low, causing the sixth transistor 27 and the ninth transistor 13 to become conductive. Also, the potential VWS of the scanning line WS transitions from high to low, causing the first transistor 22 and the fourth transistor 25 to become conductive. The Vsig / Vini driver 62 sets the potential of the signal line Data to the potential Vini, and the first transistor 22 becomes conductive, causing the potentials V1 and V2 to be initialized and set to the potential Vini.

[0135] Before entering the threshold voltage correction period from time T4 to time T5, the potential VWS of the scanning line WS transitions from a low potential to a high potential, and the first transistor 22 and the fourth transistor 25 enter a non-conducting state. During the threshold voltage correction period, a drain current Ids flows from the fixed potential VCC, charging the first capacitor 11. This causes the potential V2 to rise, and when the potential difference between the source potential Vs and the gate potential V2 of the second transistor 23 reaches the threshold voltage Vth, the rise in the potential V2 stops and the potential V1 is set to VCC-Vth. This correction operation writes a potential to the first capacitor 11 to cancel the threshold voltage Vth of the second transistor 23.

[0136] Before entering the write period from time T5 to T6, the potential VWS of the scanning line WS transitions from high to low, and the first transistor 22 and the fourth transistor 25 are turned on. Furthermore, the scanning line AZS transitions from low to high, and the sixth transistor 27 and the ninth transistor 13 are turned off. This sets the potential between the other drain / source of the third transistor 24 and the first capacitor 11 to VCC-Vth. Furthermore, a signal voltage Vsig is written into the pixel circuit 20 from the signal line Data. This operation of writing the signal voltage Vsig by the first transistor 22 sets the potential V2 to VCC-Vsig.

[0137] Before the light-emitting period from time T6 to T7 begins, the potential VWS of the scanning line WS transitions from low to high, causing the first transistor 22 and the fourth transistor 25 to become non-conductive. Furthermore, the potential VDS of the scanning line DS transitions from high to low, causing the third transistor 24 and the eighth transistor 29 to become conductive. At this time, the potential V2 becomes VCC-Vsig-Vth. Furthermore, during the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). Furthermore, the light-emitting current Iel is expressed by equation (3).

[0138] FIG. 13 is another example of a circuit diagram showing the conductive state of the pixel circuit according to the fourth embodiment.

[0139] In this example, the threshold voltage Vth corrected in the previous frame is held in the first capacitor 11, and the signal voltage Vsig is written to the second capacitor 12 in the next frame. Unlike the case of Fig. 12B, the pixel circuit 20 does not perform initialization or threshold correction. Furthermore, the operations during the light-emitting period, the light-extinction period, and the writing period are the same as those in Fig. 12B, and therefore will not be described here.

[0140] After the write period ends, during the light emission period, the potential VWS of the scanning line WS transitions from a low potential to a high potential, and the first transistor 22 and the fourth transistor 25 are brought into a non-conductive state. Also, the potential VDS of the scanning line DS transitions from a high potential to a low potential, and the third transistor 24 and the eighth transistor 29 are brought into a conductive state. As the third transistor 24 is brought into a conductive state, the potential V2 becomes VCC-Vsig-Vth based on the threshold voltage Vth held by the first capacitor 11 in the previous frame.

[0141] According to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12. Because the pixel circuit 20 can hold these voltages in separate capacitors, it is not necessary to perform a Vth correction operation for each frame, and the display device 10 can be made to operate at a higher speed and with a higher resolution.

[0142] Furthermore, according to this embodiment, the pixel circuit 20 is not affected by the substrate bias effect because the source potential of the second transistor 23 is fixed at the fixed potential VCC. Similarly, because the source potential of the second transistor 23 is fixed at the fixed potential VCC, the pixel circuit 20 is not affected by the parasitic capacitance due to the bootstrap operation during light emission because the gate potential V2 of the second transistor 23 does not increase due to capacitive coupling.

[0143] Furthermore, according to this embodiment, the pixel circuit 20 can fix the potential Vini to a constant value, thereby improving the accuracy of threshold voltage correction.

[0144] Furthermore, according to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12, so that the pixel circuit 20 is not affected by capacitive coupling when writing a signal, and all of the input signal contributes to light emission.

[0145] Furthermore, according to this embodiment, the pixel circuit 20 does not require complex constant design to suppress degradation of image quality due to the influence of parasitic capacitance caused by the substrate bias effect, capacitive coupling during signal writing, and bootstrap operation during light emission.

[0146] Furthermore, according to this embodiment, the pixel circuit 20 shares the gate of the first transistor 22 and the gate of the fourth transistor 25 and connects them to the WS scanner 44. The pixel circuit 20 also connects the gate of the ninth transistor 13 to the AZ scanner 53. This allows the display device 10 to reduce the number of scanners and achieve a narrower frame.

[0147] Furthermore, according to the present embodiment, the display device 10 can reduce the number of elements in the pixel circuit 20 by having the Vsig / Vini driver 62 supply the potential Vini via the signal line Data, thereby improving the pixel density in the display device 10 and achieving higher definition.

[0148] Fifth Embodiment FIG. 14 is an example of a circuit diagram of a pixel circuit according to a fifth embodiment.

[0149] As shown in FIG. 14 , the pixel circuit 20 in this embodiment includes a first transistor 22, a second transistor 23, a third transistor 24, a fourth transistor 25, a sixth transistor 27, a seventh transistor 28, an eighth transistor 29, a ninth transistor 13, a first capacitor 11, a second capacitor 12, and a tenth transistor 15 as elements that constitute a circuit that drives an organic EL element 21.

[0150] Unlike the first embodiment, the display device 10 in this embodiment includes a WS scanner 44 instead of the W1S scanner 42 and the W2S scanner 43. Therefore, the pixel circuits 20 are connected to the WS scanner 44 via the scanning lines WS.

[0151] One of the source / drain terminals of the first transistor 22 is connected to the signal line Data, and, unlike the first embodiment, the other of the source / drain terminals is connected to the second capacitor 12 and one of the gate / drain terminals of the tenth transistor 15. In addition, the gate of the first transistor 22 is connected to the WS scanner 44 via the scanning line WS.

[0152] One of the source / drain terminals of the third transistor 24 is connected to a fixed potential VCC via the first capacitor 11, and the other of the source / drain terminals of the third transistor 24 is connected to the second capacitor 12. Also, unlike the first embodiment, the gate of the third transistor 24 is connected to the DS scanner 41 via the scanning line DS.

[0153] One of the source / drain terminals of the fourth transistor 25 is connected to a fixed potential VCC, and the other of the source / drain terminals is connected between the second capacitor 12 and the other of the source / drain terminals of the third transistor 24. Also, unlike the first embodiment, the gate of the fourth transistor 25 is connected to the WS scanner 44 via the scanning line WS.

[0154] The tenth transistor 15 controls the supply of a signal voltage Vsig from the drain of the first transistor 22 to the gate of the second transistor 23. One source / drain of the tenth transistor 15 is connected to the gate of the second transistor 23, and the other source / drain of the fifth transistor 26 is connected to the second capacitor 12 and the other source / drain of the first transistor 22. In addition, the gate of the tenth transistor 15 is connected to the DS scanner 41 via the scanning line DS.

[0155] Also, in this example, potential V1'' indicates the potential between the first capacitor 11 and one of the source / drains of the third transistor 24, and potential V2'' indicates the potential between the drain of the first transistor 22 and one of the source / drains of the tenth transistor 15.

[0156] Generally, in a display device, as the display image becomes larger, the wiring becomes longer and the time constant for the rise of the signal voltage Vsig becomes larger. Therefore, the display device requires more time to write the signal voltage Vsig. In this example, the pixel circuit 20 starts the signal write period in accordance with the timing of the initialization period, and provides a long signal write period.

[0157] FIG. 15 is an example of a timing chart of a pixel circuit according to the fifth embodiment and a circuit diagram showing the conduction state of the corresponding pixel circuit.

[0158] The timing chart of FIG. 15A shows potentials V1'' to V2'' in addition to potentials VWS, VAZ1, VAZ2, VData, and VDS on the scanning line WS, scanning line AZ1S, scanning line AZ2S, signal line Data, and scanning line DS.

[0159] FIG. 15B shows the conduction state of each transistor during the light emission period, the extinction period, the initialization period, the threshold voltage correction period, the writing period, and the light emission period.

[0160] Before the light-emitting period from time T1 to T2 begins, the potential VDS of the scanning line DS transitions from a high potential to a low potential, and the third transistor 24, the eighth transistor 29, and the tenth transistor 15 become conductive. During the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). The light-emitting current Iel is expressed by equation (3).

[0161] Before the light-off period from time T2 to time T3 begins, the potential VDS of the scanning line DS transitions from low to high, and the third transistor 24, the eighth transistor 29, and the tenth transistor 15 are turned off, thereby turning the organic EL element 21 into a non-emitting state.

[0162] Before the initialization period from time T3 to time T4 begins, the potential VAZ1 of the scanning line AZ1S transitions from high to low, causing the sixth transistor 27 and the ninth transistor 13 to become conductive. Also, the potential VAZ2 of the scanning line AZ2S transitions from high to low, causing the seventh transistor 28 to become conductive. As a result, the potential V1 is initialized and set to the potential Vini.

[0163] Furthermore, the period from time T3 to time T6 is also used as a write period. Before entering the period from time T3 to time T6, the potential VWS of the scanning line WS transitions from a high potential to a low potential, and the first transistor 22 and the fourth transistor 25 become conductive. As a result, the signal voltage Vsig is written into the pixel circuit 20 from the signal line Data. Because the tenth transistor 15 is in a non-conductive state, the potential V2'' becomes VCC-Vsig due to the writing operation of the signal voltage Vsig by the first transistor 22.

[0164] Before the threshold voltage correction period from time T4 to time T5 begins, the potential VAZ2 of the scanning line AZ2S transitions from low to high, and the seventh transistor 28 enters a non-conductive state. During the threshold voltage correction period, a drain current Ids flows from the fixed potential VCC, charging the first capacitor 11. This causes the gate potential of the second transistor 23 to rise, and when the potential difference between the source potential Vs and the gate potential of the second transistor 23 reaches the threshold voltage Vth, the rise in the gate potential stops and the potential V1 is set to VCC-Vth. After the threshold voltage correction period ends, the potential VAZ1 of the scanning line AZ1S transitions from low to high, and the sixth transistor 27 and the ninth transistor 13 enter a non-conductive state. This correction operation writes a potential to the first capacitor 11 to cancel the threshold voltage Vth of the second transistor 23.

[0165] Before the light-emitting period from time T6 to T7 begins, the potential VDS of the scanning line DS transitions from a high potential to a low potential, and the third transistor 24, the eighth transistor 29, and the tenth transistor 15 become conductive. Furthermore, the potential VWS of the scanning line WS transitions from a low potential to a high potential, and the first transistor 22 and the fourth transistor 25 become non-conductive. At this time, the potential V2'' becomes VCC-Vsig-Vth. Furthermore, during the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). Furthermore, the light-emitting current Iel is expressed by equation (3).

[0166] FIG. 16 is another example of a circuit diagram showing the conductive state of the pixel circuit according to the fifth embodiment.

[0167] In this example, the threshold voltage Vth corrected in the previous frame is held in the first capacitor 11, and the signal voltage Vsig is written to the second capacitor 12 in the next frame. Unlike the case of Fig. 15B, the pixel circuit 20 does not perform initialization or threshold correction. Furthermore, the operations during the light-emitting period, the light-extinction period, and the writing period are the same as those in Fig. 12B, and therefore will not be described here.

[0168] After the end of the writing period, during the light emission period, the potential VDS of the scanning line DS transitions from a high potential to a low potential, and the third transistor 24, the eighth transistor 29, and the tenth transistor 15 are brought into a conductive state. Furthermore, the potential VWS of the scanning line WS transitions from a low potential to a high potential, and the first transistor 22 and the fourth transistor 25 are brought into a non-conductive state. As the third transistor 24 transitions into a conductive state, the potential V2" becomes VCC-Vsig-Vth based on the threshold voltage Vth held by the first capacitor 11 in the previous frame.

[0169] According to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12. Because the pixel circuit 20 can hold these voltages in separate capacitors, it is not necessary to perform a Vth correction operation for each frame, and the display device 10 can be made to operate at a higher speed and with a higher resolution.

[0170] Furthermore, according to this embodiment, the pixel circuit 20 is not affected by the substrate bias effect because the source potential of the second transistor 23 is fixed at the fixed potential VCC. Similarly, because the source potential of the second transistor 23 is fixed at the fixed potential VCC, the pixel circuit 20 is not affected by the parasitic capacitance due to the bootstrap operation during light emission because the gate potential V2 of the second transistor 23 does not increase due to capacitive coupling.

[0171] Furthermore, according to this embodiment, the pixel circuit 20 can fix the potential Vini to a constant value, thereby improving the accuracy of threshold voltage correction.

[0172] Furthermore, according to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12, so that the pixel circuit 20 is not affected by capacitive coupling when writing a signal, and all of the input signal contributes to light emission.

[0173] Furthermore, according to this embodiment, the pixel circuit 20 does not require complex constant design to suppress degradation of image quality due to the influence of parasitic capacitance caused by the substrate bias effect, capacitive coupling during signal writing, and bootstrap operation during light emission.

[0174] Furthermore, according to this embodiment, the pixel circuit 20 includes a tenth transistor 15 that controls the supply of the signal voltage Vsig to the gate of the second transistor 23. This enables the pixel circuit 20 to write the signal voltage Vsig to the second capacitor 12 during the threshold correction period, allowing for a longer write time. Therefore, even if the wiring connected to the pixel circuit 20 is long and the time constant of the signal voltage Vsig is large, signal writing is possible, and a large display device 10 can be realized.

[0175] Sixth Embodiment FIG. 17 is an example of a circuit diagram of a pixel circuit according to a sixth embodiment.

[0176] FIG. 17A shows an example of a circuit diagram of a pixel circuit in the sixth embodiment, and FIG. 17B shows an example of a board mounting diagram of the pixel circuit in the sixth embodiment.

[0177] In the first embodiment, an example was shown in which P-channel transistors were used as the first transistor 22 and the third transistor 24 to the seventh transistor 28, but in this embodiment, N-channel transistors are used for these channels, as shown in Fig. 17A. For the sake of explanation, in this embodiment, the respective transistors are treated as the first transistor 22' and the third transistor 24' to the seventh transistor 28'.

[0178] Unlike the first embodiment, the drain of the first transistor 22′ is connected to the signal line Data, and the source is connected to the second capacitor 12, the source / drain of the fifth transistor 26′, and the gate of the second transistor 23. The other configurations are the same as those of the first embodiment.

[0179] In this embodiment, the pixel circuit 20 uses IGZO (Indium Gallium Zinc Oxide) as an example of a metal oxide semiconductor, and employs an IGZO / Si stacked structure. The elements are disposed on an OLED substrate 310, an IGZO substrate 320, and a Si substrate 330. The OLED substrate 310, the IGZO substrate 320, and the Si substrate 330 may be referred to as a first substrate, a second substrate, and a third substrate, respectively.

[0180] For example, in each pixel circuit 20 included in the display device, the light-emitting element EL is disposed on an OLED substrate 310. Furthermore, in each pixel circuit 20, the second transistor 23 and the eighth transistor 29, which are P-channel transistors, are disposed on a Si substrate 330. Furthermore, in each pixel circuit 20, the first transistor 22′ and the third transistor 24′ to the seventh transistor 28′, which are N-channel transistors, are disposed on an IGZO substrate 320. Furthermore, the Vsig driver 61, the DS scanner 41, the W2S scanner 42, the W1S scanner 43, the AZ1 scanner 51, and the AZ2 scanner 52 (collectively referred to as drive circuits) are disposed on the Si substrate 330.

[0181] FIG. 18 is an example of a timing chart of a pixel circuit according to the sixth embodiment and a circuit diagram showing the conduction state of the corresponding pixel circuit.

[0182] The timing chart in Fig. 18A shows potentials V1 to V2 in addition to potentials VW1S, VW2S, VAZ1, VAZ2, VData, and VDS on the scanning lines W1S, W2S, AZ1S, AZ2S, signal lines Data, and DS. Fig. 18B shows the conduction states of each transistor in the light-emitting period, extinction period, initialization period, threshold voltage correction period, write period, and light-emitting period.

[0183] In this example, the eighth transistor 29 is a P-channel transistor, so that a low potential state of the scanning line DS results in a conductive state, and a high potential state results in a non-conductive state. Also, the first transistor 22′ and the third transistor 24′ to the seventh transistor 28′ are N-channel transistors, so that a high potential state of the scanning line W1S and the like results in a conductive state, and a low potential state results in a non-conductive state.

[0184] Before the light-emitting period from time T1 to time T2 begins, the voltage VW2S of the potential VDS of the scanning line DS transitions from high to low, and the eighth transistor 29 enters a conductive state. The potential of the scanning line W2S transitions from low to high, and the third transistor 24' enters a conductive state. During the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). The light-emitting current Iel is expressed by equation (3).

[0185] Before the light-off period from time T2 to time T3 begins, the potential VDS of the scanning line DS transitions from low to high, and the eighth transistor 29 enters a non-conductive state, thereby causing the organic EL element 21 to enter a non-emitting state.

[0186] Before the initialization period from time T3 to time T4 begins, the potential VAZ1 of the scanning line AZ1S and the potential VAZ2 of the scanning line AZ2S transition from low to high, and the fifth transistor 26′, the sixth transistor 27′, and the seventh transistor 28′ are brought into a conductive state, thereby initializing the potentials V1 and V2 and setting them to the potential Vini.

[0187] Before the threshold voltage correction period from time T4 to time T5 begins, the scanning line AZ2S transitions from a high potential to a low potential, and the seventh transistor 28' becomes non-conductive. During the threshold voltage correction period, a drain current Ids flows from the fixed potential VCC, charging the first capacitor 11. This causes the potential V2 to rise, and when the potential difference between the source potential Vs and the gate potential V2 of the second transistor 23 becomes just the threshold voltage Vth, the rise in the potential V2 stops, and the potential V1 is set to VCC-Vth.

[0188] Before the write period from time T5 to time T6 begins, the potential VW1S of the scanning line W1S transitions from low to high, causing the first transistor 22' and the fourth transistor 25' to be conductive. Furthermore, the scanning lines W2S and AZ1S transition from high to low, causing the third transistor 24', the fifth transistor 26', and the sixth transistor 27' to be non-conductive. This sets the potential between the other drain / source of the third transistor 24' and the second capacitor 12 to the fixed potential VCC. Furthermore, a signal voltage Vsig is written into the pixel circuit 20 from the signal line Data. Due to the write operation of the signal voltage Vsig by the first transistor 22', the potential V2 becomes VCC-Vsig.

[0189] Before the light-emitting period from time T6 to T7 begins, the potential VDS of the scanning line DS transitions from high to low, causing the eighth transistor 29 to enter a conductive state. Furthermore, the voltage VW2S of the scanning line W2S transitions from low to high, causing the third transistor 24' to enter a conductive state. Furthermore, the voltage VW2S of the scanning line W1S transitions from high to low, causing the fourth transistor 25' to enter a non-conductive state. At this time, the potential V2 becomes VCC-Vsig-Vth. Furthermore, during the light-emitting period, the second transistor 23 passes a drain current Ids corresponding to the gate-source voltage Vgs through the organic EL element 21. The gate-source voltage Vgs of the second transistor 23 is expressed by equation (1), and the drain current Ids of the second transistor 23 is expressed by equation (2). Furthermore, the light-emitting current Iel is expressed by equation (3).

[0190] FIG. 19 is another example of a circuit diagram showing the conductive state of the pixel circuit according to the sixth embodiment.

[0191] In this example, the threshold voltage Vth corrected in the previous frame is held in the first capacitor 11, and the signal voltage Vsig is written to the second capacitor 12 in the next frame. Unlike the case of Fig. 18B, the pixel circuit 20 does not perform initialization or threshold correction. Furthermore, the operations during the light-emitting period, the light-extinction period, and the writing period are the same as those in Fig. 18B, and therefore will not be described here.

[0192] After the write period ends and before the light emission period begins, the potential VDS of the scanning line DS transitions from high to low, causing the eighth transistor 29 to enter a conductive state. Furthermore, the voltage VW2S of the scanning line W2S transitions from low to high, causing the third transistor 24' to enter a conductive state. Furthermore, the potential VW1S of the scanning line W1S transitions from high to low, causing the fourth transistor 25' to enter a non-conductive state. With the third transistor 24' entering a conductive state, the potential V2 becomes VCC-Vsig-Vth based on the threshold voltage Vth held by the first capacitor 11 in the previous frame.

[0193] According to this embodiment, the pixel circuit 20 holds the threshold voltage Vth in the first capacitor 11 and the signal voltage Vsig in the second capacitor 12. Because the pixel circuit 20 can hold these voltages in separate capacitors, it is not necessary to perform a Vth correction operation for each frame, and the display device 10 can be made to operate at a higher speed and with a higher resolution.

[0194] Furthermore, according to this embodiment, the pixel circuit 20 is not affected by the substrate bias effect because the source potential of the second transistor 23 is fixed at the fixed potential VCC. Similarly, because the source potential of the second transistor 23 is fixed at the fixed potential VCC, the pixel circuit 20 is not affected by the parasitic capacitance due to the bootstrap operation during light emission because the gate potential V2 of the second transistor 23 does not increase due to capacitive coupling.

[0195] Furthermore, according to this embodiment, the pixel circuit 20 can fix the potential Vini to a constant value, thereby improving the accuracy of threshold voltage correction.

[0196] Furthermore, according to this embodiment, the pixel circuit 20 can achieve high definition in the display device by arranging switching transistors and the like on an IGZO substrate with low leakage, and can also achieve high yield during manufacturing.

[0197] (Application Example 1) Next, an application example of the display system described in the above embodiment will be described.

[0198] 20 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0199] (Application Example 2) FIG. 21 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0200] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0201] (Application Example 3) Figures 22A and 22B show an example of the appearance of a digital still camera 130, with Figure 22A showing a front view and Figure 22B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 311. The grip 133 is provided on the left side of the front of the camera body 311, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 14 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0202] 23 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0203] 24 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0204] (Application Example 6) Figures 25A and 25B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 25A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 25B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0205] The vehicle in Figures 25A and 25B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0206] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 25A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0207] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0208] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0209] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0210] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0211] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0212] The rear entertainment display 206 is attached to the back side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurements of the body temperature of the rear seat passengers by the temperature sensor 5.

[0213] The techniques according to the above-described embodiments can be applied to the center display 201, the console display 202, the head-up display 203, the digital rearview mirror 204, the steering wheel display 205, and the rear entertainment display 206.

[0214] The present disclosure has been described above by way of embodiments, application examples, and application examples, but the present disclosure is not limited to the above embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0215] Furthermore, for example, the present disclosure can be configured as follows.

[0216] (1) A display device including a pixel circuit, the pixel circuit including: a first transistor that samples a signal voltage; a P-channel second transistor that drives a light-emitting element; an eighth transistor that controls light emission and non-emission of the light-emitting element; a first capacitance that holds a threshold voltage of the second transistor; a second capacitance that holds the signal voltage written by the first transistor; and a third transistor that separates the first capacitance that holds the threshold voltage from a current path, the first capacitance being connected between a fixed potential and a source / drain of the third transistor, and the source of the second transistor being connected to the fixed potential.

[0217] (2) The display device according to (1), wherein the pixel circuit further includes a fourth transistor that controls a potential between a source / drain of the third transistor and the second capacitance to the fixed potential, and the fourth transistor is turned on before a writing period of a signal voltage Vsig based on an operation of the first transistor begins, and is turned off before a light emitting period of the light emitting element begins.

[0218] (3) The display device according to (1), wherein the pixel circuit further includes: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; a seventh transistor controlling the gate potential of the second transistor to an initialization potential; and a fifth transistor controlling the potential between the source / drain of the third transistor and a second capacitor 12 based on the gate potential of the second transistor, wherein the fifth transistor and the sixth transistor are rendered conductive before an initialization period for the gate potential of the second transistor begins, and are rendered non-conductive before a writing period for a signal voltage Vsig based on the operation of the first transistor begins.

[0219] (4) The display device according to (3), wherein the seventh transistor is turned on before the initialization period begins and turned off before the threshold voltage correction period of the second transistor begins.

[0220] (5) The display device according to (1), wherein the third transistor is turned on before a light emitting period of the light emitting element begins, and is turned off before a writing period of a signal voltage Vsig based on the operation of the first transistor begins.

[0221] (6) The display device according to (1), wherein the pixel circuit further includes: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; a seventh transistor controlling the gate potential of the second transistor to an initialization potential; and a ninth transistor controlling the potential between the first capacitor and the source / drain of the third transistor based on the gate potential of the second transistor, wherein the sixth transistor and the ninth transistor are rendered conductive before an initialization period for the gate potential of the second transistor begins, and are rendered non-conductive before a writing period for a signal voltage Vsig based on the operation of the first transistor begins.

[0222] (7) The display device according to (6), wherein the seventh transistor is turned on before the initialization period begins and turned off before the threshold voltage correction period of the second transistor begins.

[0223] (8) The display device according to (7), wherein the third transistor is turned on before the light emitting element enters a light emitting period, and is turned off before the light emitting element enters a light extinction period.

[0224] (9) The display device according to (7), wherein the pixel circuit further includes a fourth transistor that controls a potential between the source / drain of the third transistor and the second capacitance to the fixed potential, and the first transistor and the fourth transistor are turned on before a writing period of a signal voltage Vsig based on operation of the first transistor begins, and are turned off before a light emitting period of the light emitting element begins.

[0225] (10) The display device according to (1), wherein the drain of the first transistor is connected between the source / drain of the third transistor and the second capacitor, and the first transistor is turned on before a write period of a signal voltage Vsig based on operation of the first transistor begins, and is turned off before a light emission period of the light emitting element begins.

[0226] (11) The display device according to (10), wherein the pixel circuit further comprises: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; a seventh transistor controlling the gate potential of the second transistor to an initialization potential; and a ninth transistor controlling the potential between the first capacitor and the source / drain of the third transistor based on the gate potential of the second transistor, wherein the sixth transistor and the ninth transistor are rendered conductive before entering an initialization period for the gate potential of the second transistor, and are rendered non-conductive before entering the writing period.

[0227] (12) The display device according to (11), wherein the seventh transistor is turned on before the initialization period begins, turned off before a threshold voltage correction period for the second transistor begins, turned on before the writing period begins, and turned off before the light emission period begins.

[0228] (13) The display device according to (10), wherein the third transistor is turned on before the light-emitting period begins and turned off before the light-extinguishing period of the light-emitting element begins.

[0229] (14) The display device according to (1), wherein the pixel circuit further includes: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; and a ninth transistor controlling a potential between the first capacitor and the source / drain of the third transistor based on a gate potential of the second transistor, and the gate potential of the second transistor is controlled to an initialization potential supplied via the first transistor.

[0230] (15) The display device according to (14), wherein the pixel circuit further includes a fourth transistor that controls a potential between the source / drain of the third transistor and the second capacitance to the fixed potential, and the fourth transistor is turned on before a write period of a signal voltage Vsig based on the operation of the first transistor begins, and is turned off before a light emission period of the light emitting element begins.

[0231] (16) The display device according to (14), wherein the sixth transistor is turned on before entering an initialization period of the gate potential of the second transistor and turned off before entering a writing period of the signal voltage Vsig based on the operation of the first transistor, and the first transistor is turned on before entering the initialization period, turned off before entering a threshold voltage correction period of the second transistor, turned on before entering the writing period, and turned off before entering a light emission period of the light emitting element.

[0232] (17) The display device according to (14), wherein the third transistor is turned on before the light-emitting period of the light-emitting element begins, and is turned off before the light-off period of the light-emitting element begins.

[0233] (18) The display device according to (1), further comprising a tenth transistor that controls the supply of a signal voltage Vsig from the drain of the first transistor to the gate of the second transistor, wherein the first transistor is turned on before entering an initialization period for the gate potential of the second transistor and a writing period for the signal voltage Vsig based on the operation of the first transistor, and is turned off before entering an emission period for the light-emitting element, and the tenth transistor is turned on before entering the emission period, and is turned off before entering an extinction period for the light-emitting element.

[0234] (19) The display device according to (18), wherein the pixel circuit further includes a fourth transistor that controls a potential between the third transistor and the second capacitance to the fixed potential, and the fourth transistor is turned on before entering the writing period and turned off before entering the light-emitting period.

[0235] (20) The display device according to (18), wherein the pixel circuit further includes: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; a seventh transistor controlling the gate potential of the second transistor to an initialization potential; and a ninth transistor controlling the potential between the first capacitor and the source / drain of the third transistor based on the gate potential of the second transistor, wherein the sixth transistor and the ninth transistor are rendered conductive before the initialization period begins and rendered non-conductive after the threshold voltage correction period of the second transistor ends.

[0236] 5: temperature sensor, 10: display device, 11: first capacitor, 12: second capacitor, 13: ninth transistor, 14: monitor, 15: tenth transistor, 20: pixel circuit, 21: organic EL element, 22: first transistor, 22': first transistor, 23: second transistor, 24: third transistor, 24': third transistor, 25: fourth transistor, 25': fourth transistor, 26: fifth transistor, 26': fifth transistor, 27: sixth transistor, 27': sixth transistor, 28: seventh transistor, 28': seventh transistor, 29: eighth transistor, 30: pixel array, 41: DS scanner, 42: W1S scanner, 43: W2S scanner, 44: WS scanner, 51: AZ1 scanner, 52: AZ2 scanner, 53: AZ scanner, 61: Vsig driver, 62: Vsig / Vini driver, 110: head-mounted display, 111: display unit, 112: ear hook unit, 120: head-mounted display, 121: main body unit, 122: arm unit, 123: lens barrel unit, 128: glasses, 129: lens, 130: digital still camera, 131: camera main body unit, 132: photographing lens unit, 133: grip unit, 134: monitor, 135: electronic viewfinder, 140: television device, 141: video display screen unit, 142: front panel, 143: filter glass, 150: smartphone, 151: display unit, 152: operation unit, 200: vehicle, 201: center display, 202: console display, 203: head-up display, 204: digital rearview mirror, 205: steering wheel display, 206: Rear entertainment display, 261: Dashboard, 262: Driver's seat, 263: Passenger seat, 264: Center console, 265: Shift lever, 266: Windshield, 267: Steering wheel, 310: OLED substrate, 320: IGZO substrate, 330: Si substrate

Claims

1. A display device comprising a pixel circuit, the pixel circuit comprising: a first transistor for sampling a signal voltage; a P-channel second transistor for driving a light-emitting element; an eighth transistor for controlling light emission and non-emission of the light-emitting element; a first capacitance for holding a threshold voltage of the second transistor; a second capacitance for holding the signal voltage written by the first transistor; and a third transistor for isolating the first capacitance holding the threshold voltage from a current path, the first capacitance being connected between a fixed potential and a source / drain of the third transistor, and the source of the second transistor being connected to the fixed potential.

2. The display device according to claim 1, wherein the pixel circuit further comprises a fourth transistor that controls the potential between the source / drain of the third transistor and the second capacitance to the fixed potential, and the fourth transistor is turned on before entering a writing period of a signal voltage Vsig based on the operation of the first transistor, and is turned off before entering a light emission period of the light emitting element.

3. The display device of claim 1, wherein the pixel circuit further comprises: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; a seventh transistor controlling the gate potential of the second transistor to an initialization potential; and a fifth transistor controlling the potential between the source / drain of the third transistor and a second capacitor 12 based on the gate potential of the second transistor, the fifth transistor and the sixth transistor being rendered conductive before entering an initialization period for the gate potential of the second transistor, and being rendered non-conductive before entering a write period for the signal voltage Vsig based on the operation of the first transistor.

4. The display device according to claim 3, wherein the seventh transistor is turned on before the initialization period begins, and is turned off before the threshold voltage correction period of the second transistor begins.

5. A display device according to claim 1, wherein the third transistor is rendered conductive before the light-emitting period of the light-emitting element begins, and is rendered non-conductive before the writing period of the signal voltage Vsig based on the operation of the first transistor begins.

6. The display device of claim 1, wherein the pixel circuit further comprises: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; a seventh transistor controlling the gate potential of the second transistor to an initialization potential; and a ninth transistor controlling the potential between a first capacitor and the source / drain of a third transistor based on the gate potential of the second transistor, the sixth transistor and the ninth transistor being rendered conductive before entering an initialization period for the gate potential of the second transistor, and being rendered non-conductive before entering a write period for a signal voltage Vsig based on the operation of the first transistor.

7. The display device according to claim 6, wherein the seventh transistor is rendered conductive before the initialization period begins, and is rendered non-conductive before the threshold voltage correction period of the second transistor begins.

8. The display device according to claim 7, wherein the third transistor is turned on before the light emitting element enters a light emitting period, and is turned off before the light emitting element enters a light extinction period.

9. The display device according to claim 7, wherein the pixel circuit further comprises a fourth transistor that controls the potential between the source / drain of the third transistor and the second capacitance to the fixed potential, and the first transistor and the fourth transistor are turned on before entering a writing period of a signal voltage Vsig based on the operation of the first transistor, and turned off before entering a light emission period of the light emitting element.

10. The display device according to claim 1, wherein the drain of the first transistor is connected between the source / drain of the third transistor and the second capacitance, and the first transistor is turned on before entering a write period of a signal voltage Vsig based on the operation of the first transistor, and turned off before entering a light emission period of the light emitting element.

11. The display device of claim 10, wherein the pixel circuit further comprises: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; a seventh transistor controlling the gate potential of the second transistor to an initialization potential; and a ninth transistor controlling the potential between the first capacitor and the source / drain of the third transistor based on the gate potential of the second transistor, the sixth transistor and the ninth transistor being rendered conductive before entering an initialization period for the gate potential of the second transistor and being rendered non-conductive before entering the write period.

12. The display device according to claim 11, wherein the seventh transistor is turned on before entering the initialization period, turned off before entering the threshold voltage correction period of the second transistor, turned on before entering the writing period, and turned off before entering the light emission period.

13. The display device according to claim 10, wherein the third transistor is turned on before the light emitting period and turned off before the light emitting element enters a non-light emitting period.

14. The display device of claim 1, wherein the pixel circuit further comprises: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; and a ninth transistor controlling a potential between a first capacitor and the source / drain of a third transistor based on a gate potential of the second transistor, and the gate potential of the second transistor is controlled to an initialization potential supplied via the first transistor.

15. The display device according to claim 14, wherein the pixel circuit further comprises a fourth transistor that controls the potential between the source / drain of the third transistor and the second capacitance to the fixed potential, and the fourth transistor is rendered conductive before entering a write period of a signal voltage Vsig based on the operation of the first transistor, and is rendered non-conductive before entering a light emission period of the light-emitting element.

16. The display device of claim 14, wherein the sixth transistor is turned on before entering an initialization period of the gate potential of the second transistor, and is turned off before entering a writing period of a signal voltage Vsig based on the operation of the first transistor, and the first transistor is turned on before entering the initialization period, is turned off before entering a threshold voltage correction period of the second transistor, is turned on before entering the writing period, and is turned off before entering a light emission period of the light emitting element.

17. The display device according to claim 14, wherein the third transistor is turned on before the light emitting element enters a light emitting period, and turned off before the light emitting element enters a light off period.

18. The display device of claim 1, further comprising a tenth transistor that controls the supply of a signal voltage Vsig from the drain of the first transistor to the gate of the second transistor, the first transistor being turned on before entering an initialization period for the gate potential of the second transistor and a writing period for the signal voltage Vsig based on the operation of the first transistor, and being turned off before entering an emission period of the light-emitting element, and the tenth transistor being turned on before entering the emission period, and being turned off before entering an extinction period of the light-emitting element.

19. The display device according to claim 18, wherein the pixel circuit further comprises a fourth transistor that controls a potential between the third transistor and the second capacitance to the fixed potential, and the fourth transistor is rendered conductive before entering the writing period and is rendered non-conductive before entering the light emission period.

20. The display device of claim 18, wherein the pixel circuit further comprises: a sixth transistor connecting the drain of the second transistor and the gate of the second transistor; a seventh transistor controlling a gate potential of the second transistor to an initialization potential; and a ninth transistor controlling a potential between a first capacitor and the source / drain of a third transistor based on the gate potential of the second transistor, the sixth transistor and the ninth transistor being rendered conductive before entering the initialization period and being rendered non-conductive after completion of a threshold voltage correction period of the second transistor.

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