Data driving device and display device

Abstract

A data driving device according to an embodiment may drive a display panel comprising a plurality of gate lines and a plurality of data lines. The data driving device may comprise: a plurality of output buffers for outputting, to a plurality of data lines, a plurality of channel data voltages respectively corresponding to a plurality of channel data signals for each gate line provided from a data processing device; and a controller for controlling the plurality of output buffers. The controller may adjust a slew rate of each of the plurality of channel data voltages outputted from the plurality of output buffers on the basis of position information of the gate line and power control information of each of the plurality of channel data signals.

Description

Data drive and display devices

[0001] The embodiment relates to a data drive device and a display device.

[0002] The display device can display an image on a display panel using a data voltage provided from a data driving device.

[0003] A display panel includes a plurality of data lines for transmitting data voltages. The data voltage provided from a display driver exhibits an RC delay due to the resistance or capacitance of the data lines. This delay increases with distance from the data driver. Accordingly, the transition time for the data voltage to change to a desired voltage level increases with distance from the data driver. As such, as the distance from the data driver increases, the transition time of the data voltage increases, which causes a problem in that the charging rate of the pixel decreases with distance from the data driver, resulting in a deterioration in the image quality. In particular, as the resolution of the display device increases and 1 horizontal period (1H) decreases, this deterioration in image quality becomes more severe.

[0004] A data driving device outputs multiple channel data voltages for each gate line through multiple channels corresponding to multiple data lines. Outputting multiple channel data voltages for each gate line means that multiple channel data voltages are output for each line or each horizontal period (1H).

[0005] Meanwhile, since the RC delay characteristics between multiple data lines are different, there is a problem in that the transition time of multiple channel data voltages differs for each data line, i.e., for each channel.

[0006] In addition, there is a problem of increased power consumption because the channel data voltage is output at a preset slew rate even when there is no or small difference between the channel data voltages of each of at least two gate lines included in a given area.

[0007] The present invention aims to solve the above-mentioned and other problems.

[0008] Another object of the embodiment is to provide a data drive device and a display device capable of reducing power consumption.

[0009] Another object of the present invention is to provide a data drive device and a display device capable of improving image quality.

[0010] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0011] According to a first aspect of the embodiment to achieve the above or other purposes, a data driving device for driving a display panel including a plurality of gate lines and a plurality of data lines includes a plurality of output buffers for outputting a plurality of channel data voltages corresponding to a plurality of channel data signals respectively to the plurality of data lines for each of the gate lines provided from a data processing device; and a controller for controlling the plurality of output buffers; wherein the controller adjusts a slew rate of each of the plurality of channel data voltages output from the plurality of output buffers based on positional information of the gate lines and power control information of each of the plurality of channel data signals.

[0012] According to a second aspect of the embodiment to achieve the above or other purposes, a data driving device for driving a display panel including a plurality of gate lines and a plurality of data lines includes a plurality of output buffers for outputting a plurality of channel data voltages corresponding to a plurality of channel data signals respectively to the plurality of data lines for each of the gate lines provided from a data processing device; and a controller for controlling the plurality of output buffers; wherein the controller adjusts a slew rate of each of the plurality of channel data voltages output from the plurality of output buffers based on position information and power control information of the gate lines of each of the plurality of channel data signals.

[0013] According to a third aspect of the embodiment to achieve the above or other purposes, a display device includes: a display panel including a plurality of gate lines and a plurality of data lines; a data driving device for driving the display panel; and a data processing device for controlling the data driving device; wherein the data processing device provides a plurality of channel data signals to the data driving device for each of the gate lines, each of the plurality of channel data signals including power control information; and wherein the data driving device includes a plurality of output buffers for outputting a plurality of channel data voltages corresponding to the plurality of channel data signals to the plurality of data lines for each of the gate lines; and a controller for controlling the plurality of output buffers; wherein the controller adjusts a slew rate of each of the plurality of channel data voltages output from the plurality of output buffers based on positional information of the gate lines and the power control information of each of the plurality of channel data signals.

[0014] The effects of the data drive device and display device according to the embodiment are described as follows.

[0015] According to at least one of the embodiments, there is an advantage in that the image quality can be improved and power consumption can be reduced by providing the output data voltage at different slew rates depending on the distance from the data driving device on the display panel.

[0016] According to at least one of the embodiments, the output data voltage is provided at different slew rates depending on the distance from the data driving device for each of the plurality of channels, thereby providing an advantage in that not only is power consumption drastically reduced, but also optimized power consumption management is possible.

[0017] According to at least one of the embodiments, by providing position information of a gate line from a data processing device, there is an advantage in that a counter does not need to be provided in the data driving device, thereby drastically reducing the size of the data driving device, simplifying the circuit, and reducing the computational burden.

[0018] FIG. 1 is a block diagram illustrating a display device according to a first embodiment.

[0019] FIG. 2 shows a plurality of channel data signals included in one horizontal period according to the first embodiment.

[0020] Figure 3 shows that the transition time of the channel data voltage is different depending on the position of the display panel.

[0021] Figures 4a to 4c show that the transition time of the channel data voltage is different depending on the position of the display panel.

[0022] FIG. 5 is a flowchart illustrating an operation method in a data processing device according to the first embodiment.

[0023] Figures 6a and 6b show that the transition time of the channel data voltage is the same regardless of the position of the display panel according to the first embodiment.

[0024] Fig. 7 is a block diagram illustrating a display device according to a second embodiment.

[0025] FIG. 8 shows a plurality of channel data signals included in one horizontal period according to the second embodiment.

[0026] The sizes, shapes, and dimensions of components depicted in the drawings may differ from the actual components. Furthermore, even if the same components are depicted with different sizes, shapes, and dimensions across drawings, this is merely an example within the drawings, and the same components may have the same sizes, shapes, and dimensions across drawings.

[0027] Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers and redundant descriptions thereof will be omitted. The suffixes 'module' and 'part' used for components in the following description are given or used interchangeably in consideration of the ease of writing the specification, and do not have distinct meanings or roles in themselves. In addition, the attached drawings are intended to make it easier to understand the embodiments disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited by the attached drawings. In addition, when an element such as a layer, region, or substrate is referred to as existing 'on' another element, this includes that it may be directly on the other element or that other intermediate elements may exist therebetween.

[0028] In the following description, the gate driving device may be referred to as a scan driving device, and the data driving device may be referred to as a source driving device.

[0029] [Example 1]

[0030] FIG. 1 is a block diagram illustrating a display device according to a first embodiment.

[0031] Referring to FIG. 1, a display device (100) according to the first embodiment may include a data processing device (110), a gate driving device (120), a data driving device (130), and a display panel (140).

[0032] The data processing device (110) can control the gate driving device (120) and the data driving device (130). Although not shown, the data processing device (110) may include, but is not limited to, a processor, a timing controller, memory, etc. The data processing device (110) may be referred to as a host.

[0033] The data processing device (110) can process an image signal provided from the outside to fit the size of the display panel (140), etc. The image signal can include a plurality of channel data signals (DATA-CH1 to DATA-CHn) for each of a plurality of horizontal periods for each frame. The data processing device (110) can generate a gate control signal (GCS) and provide the gate control signal (GCS) to the gate driving device (120). The data processing device (110) can generate a data control signal (DCS) and provide the data control signal (DCS) to the data driving device (130).

[0034] Meanwhile, the data processing device (110) can separate a plurality of channel data signals (DATA-CH1 to DATA-CHn) for each of a plurality of horizontal periods per frame from an externally provided video signal. The data processing device (110) can obtain channel digital data (DCH1 to DCHn) from each of the plurality of channel data signals (DATA-CH1 to DATA-CHn). Since this technology is widely known, a detailed description thereof is omitted.

[0035] For example, if 100 gate lines (GL1 to GLm) and 200 data lines (DL1 to DLn) are provided on the display panel (140), 200 channel digital data (DCH1 to DCHn) can be obtained for each of 100 horizontal periods from an image signal corresponding to one frame. One frame can include a plurality of horizontal periods equal to the number of gate lines (GL1 to GLm).

[0036] Meanwhile, the data processing device (110) can obtain power control information (PCI1 to PCIn in FIG. 2) for each of a plurality of channel digital data (DCH1 to DCHn) separated by gate line (GL1 to GLm) or by 1 horizontal period (1H). 1 horizontal period (1H) may refer to the time required to write data to pixels connected to one gate line of the display panel (140). That is, during 1 horizontal period (1H), one scan signal is provided to one gate line to select pixels on one gate line, which may refer to activation of the corresponding gate line. A plurality of channel data voltages (DV_CH1 to DV_CHn) corresponding to the plurality of channel digital data (DCH1 to DCHn) may be provided to the selected pixels.

[0037] Figure 3 shows that the transition time of the channel data voltage is different depending on the position of the display panel.

[0038] Referring to FIG. 3, when multiple channel data signals are input for each horizontal period of one frame (S151), the data processing device (110) can obtain multiple channel digital data (DCH1 to DCHn) for each gate line from the multiple channel data signals for each horizontal period of one frame (S152). For example, the data processing device (110) can obtain multiple channel digital data (DCH1 to DCHn) for each of the multiple horizontal periods. The channel data voltages (DV_CH1 to DV_CHn) may be analog voltages.

[0039] The data processing device (110) can determine whether the difference between the plurality of channel digital data (DCH1 to DCHn) on the current gate line and the plurality of channel digital data (DCH1 to DCHn) on the previous gate line is less than a set value (S153).

[0040] The comparison between the multiple channel digital data on the current gate line and the multiple channel digital data on the previous gate line may be a comparison between the multiple channel digital data on the current gate line and the multiple channel digital data on the previous gate line on the same channel.

[0041] Assume that first channel digital data included in a first horizontal period, second channel digital data included in a second horizontal period, and third channel digital data included in a third horizontal period are provided. For example, second channel digital data on a second gate line as a current gate line can be compared with first channel digital data on a first gate line as a previous gate line. For example, third channel digital data on a third gate line as a current gate line can be compared with second channel digital data on a second gate line as a previous gate line.

[0042] The setting value can be 0 or a value greater than 0. For example, if the channel digital data is a digital value having 0 to 255 gradations, the setting value can be set to a digital value corresponding to 10 gradations, but is not limited thereto.

[0043] The data processing device (110) can obtain power control information (PCI1 to PCIn) that is OFF when the difference between the plurality of channel digital data on the current gate line and the plurality of channel digital data on the previous gate line is less than a set value (S154).

[0044] The data processing device (110) can obtain power control information (PCI1 to PCIn) that is ON when the difference between the plurality of channel digital data on the current gate line and the plurality of channel digital data on the previous gate line is greater than or equal to a set value (S155).

[0045] Power control information (PCI1 to PCIn) can be obtained for each of multiple channel digital data (DCH1 to DCHn).

[0046] The data processing device (110) may generate a plurality of channel data signals (DATA-CH1 to DATA-CHn) including power control information (PCI1 to PCIn) and channel digital data (DCH1 to DCHn) at each of a plurality of horizontal periods according to a preset data format, as illustrated in FIG. 2, and provide the plurality of channel data signals (DATA-CH1 to DATA-CHn) to the data driving device (130). For example, the power control information (PCI1 to PCIn) may be configured with 2 bits, and may be set to '01' when OFF, and '10' when ON, but is not limited thereto.

[0047] After multiple channel data signals (DATA-CH1 to DATA-CHn) for each of multiple horizontal periods included in one frame are provided, the data processing device (110) can determine whether there is a next frame (S157).

[0048] When there is a next frame, the data processing device (110) can repeat S152 to S156 to provide a plurality of channel data signals (DATA-CH1 to DATA-CHn) each including power control information (PCI1 to PCIn) and channel digital data (DCH1 to DCHn) for each of a plurality of horizontal periods.

[0049] Meanwhile, the data processing device (110) and the data driving device (130) may be capable of serial data communication using a high-speed communication interface such as LVDS or mini-LVDS, but are not limited thereto. Using the high-speed communication interface, a plurality of channel data signals (DATA-CH1 to DATA-CHn) may be serially transmitted to the data driving device (130) for each of a plurality of horizontal periods per frame.

[0050] Referring again to FIG. 1, the display panel (140) may include a plurality of gate lines (GL1 to GLm) arranged along a second direction (Y-axis direction) and a plurality of data lines (DL1 to DLn) arranged along a first direction (X-axis direction). A plurality of pixels may be connected to the plurality of gate lines (GL1 to GLm) and the plurality of data lines (DL1 to DLn).

[0051] The gate driving device (120) can generate a scan signal based on a gate control signal (GCS) provided from the data processing device (110). The scan signal can have a high level for one horizontal period (1H). Accordingly, since the high level of the scan signal is provided through each of the plurality of gate lines (GL1 to GLm), the plurality of gate lines (GL1 to GLm) can be activated for one horizontal period (1H), respectively. Here, activation may mean that pixels connected to specific gate lines among the plurality of gate lines (GL1 to GLm) are selected so that a plurality of channel data voltages (DV_CH1 to DV_CHn) for one line can be supplied. Since the plurality of gate lines (GL1 to GLm) are sequentially activated in response to the scan signal, a plurality of channel data voltages (DV_CH1 to DV_CHn) for one line each can be sequentially provided to the pixels connected to each of the plurality of gate lines (GL1 to GLm).

[0052] Meanwhile, the data driving device (130) can provide multiple channel data voltages (DV_CH1 to DV_CHn) corresponding to multiple channel digital data (DCH1 to DCHn) of one line to multiple data lines (DL1 to DLn) according to a data control signal (DCS) provided from the data processing device (110).

[0053] The data driving device (130) may include a channel data voltage generating unit (134). When the channel data voltage generating unit (134) receives channel data signals (DATA-CH1 to DATA-CHn) for each gate line or for each line from the data processing device (110), the channel data voltage generating unit (134) may generate a plurality of channel data voltages (DV_CH1 to DV_CHn) corresponding to a plurality of channel digital data (DCH1 to DCHn) of the corresponding channel data signals (DATA-CH1 to DATA-CHn). The plurality of channel data voltages (DV_CH1 to DV_CHn) generated for each line may be provided to the display panel for each of a plurality of horizontal periods included in one frame.

[0054] The channel data voltage generation unit (134) may include a plurality of output buffers (135-1 to 135-n). The plurality of output buffers (135-1 to 135-n) may be connected to a plurality of data lines (DL1 to DLn), respectively. The plurality of output buffers (135-1 to 135-n), each connected to a plurality of data lines (DL1 to DLn), may form a plurality of channels. The plurality of channels may be passages for connecting the plurality of output buffers (135-1 to 135-n) and the plurality of data lines (DL1 to DLn). For example, one channel may be formed by the first output buffer (135-1) of the data driving device (130) and the first data line (DL1) of the display panel (140). Therefore, a plurality of channel data voltages (DV_CH1 to DV_CHn) may be output to the display panel (140) through the plurality of channels.

[0055] The plurality of output buffers (135-1 to 135-n) of the data driving device (130) can each adjust the slew rate of the plurality of channel data voltages (DV_CH1 to DV_CHn). The slew rate may refer to the rate of change of the channel data voltages (DV_CH1 to DV_CHn) with respect to a unit time. A small or low slew rate may refer to a small rate of change of the channel data voltages (DV_CH1 to DV_CHn) with respect to a unit time. A large or high slew rate may refer to a large rate of change of the channel data voltages (DV_CH1 to DV_CHn) with respect to a unit time. As will be described later, the slew rate may be adjusted by a bias current. For example, the larger the bias current, the more the slew rate can be adjusted.

[0056] Previously, channel data voltages (DV_CH1 to DV_CHn) were output at a preset slew rate regardless of the position on the display panel (140). In this case, as illustrated in FIGS. 4A and 4B , the transition time (T1) of the channel data voltages (DV_CH1 to DV_CHn) provided to a position (P1) close to the data driving device (130) or the output buffers (135-1 to 135-n) is short, whereas as illustrated in FIGS. 4A and 4C , the transition time (T2) of the channel data voltages (DV_CH1 to DV_CHn) provided to a position (P2) far from the data driving device (130) or the output buffers (135-1 to 135-n) is long. Here, the positions (P1, P2) may be one pixel (or subpixel) or an area including at least two or more pixels.

[0057] 1 Horizontal period (1H) is the same regardless of the position on the display panel (140), whereas the transition time (T2) of the channel data voltage (DV_CH1 to DV_CHn) at a position (P2) far from the data driving device (130) or the output buffer (135-1 to 135-n) is long, so that the desired amount of charge is not secured during 1 horizontal period (1H), and an image having the desired gradation is not displayed. Accordingly, there is a problem that the amount of charge of the data voltage is different depending on the position (P1, P2) on the display panel (140), and the image quality deteriorates. In particular, in the past, the difference in the transition time of the channel data voltage according to each channel, i.e., the channel data voltage output from each output buffer (135-1 to 135-n), was not taken into consideration, and thus there was a problem that the image quality was further deteriorated.

[0058] In addition, there is a problem in that power consumption is not efficiently managed because the slew rate is not adjusted according to the position (P1, P2) on the display panel (140) or each channel, resulting in wasted power consumption.

[0059] In an embodiment, the data driving device (130) can prevent image quality degradation and reduce power consumption by adjusting the slew rate according to the position on the display panel (140) and / or each channel.

[0060] Specifically, the data driving device (130) may include a channel data voltage generation unit (134) and a controller (132). The controller (132) may control the channel data voltage generation unit (134).

[0061] The channel data voltage generation unit (134) can generate a plurality of channel data voltages (DV_CH1 to DV_CHn). The channel data voltage generation unit (134) can generate a plurality of channel data voltages (DV_CH1 to DV_CHn) based on a plurality of channel data signals (DATA-CH1 to DATA-CHn) provided from the data processing device (110). The channel data voltage generation unit (134) can generate a plurality of channel data voltages (DV_CH1 to DV_CHn) respectively corresponding to a plurality of channel digital data of the plurality of channel data signals (DATA-CH1 to DATA-CHn) based on a plurality of gamma voltages (not shown). The plurality of channel data voltages (DV_CH1 to DV_CHn) can be provided to a plurality of data lines (DL1 to DLn) on the display panel (140). For each of the plurality of horizontal periods included in one frame, a plurality of channel data signals (DATA-CH1 to DATA-CHn) can be provided from the data processing device (110) to the data driving device (130).

[0062] The channel data voltage generation unit (134) may include a plurality of output buffers (135-1 to 135-n). The plurality of output buffers (135-1 to 135-n) may output a plurality of channel data voltages (DV_CH1 to DV_CHn).

[0063] The plurality of output buffers (135-1 to 135-n) can adjust the slew rate of the plurality of channel data voltages (DV_CH1 to DV_CHn). In an embodiment, the plurality of output buffers (135-1 to 135-n) can adjust the slew rate of the plurality of channel data voltages (DV_CH1 to DV_CHn) under the control of the controller (132).

[0064] To this end, the data driving device (130) may include a bias current control unit (133). The bias current control unit (133) may adjust the bias current of each of the plurality of channel data voltages (DV_CH1 to DV_CHn). The bias current control unit (133) may maintain, increase, or decrease the bias current at a preset bias current. The plurality of output buffers (135-1 to 135-n) may adjust the slew rate of the plurality of channel data voltages (DV_CH1 to DV_CHn) according to the plurality of bias currents adjusted by the bias current control unit (133), and output the plurality of channel data voltages using the adjusted slew rate.

[0065] The bias current control unit (133) can adjust the bias current of each of the plurality of channel data voltages (DV_CH1 to DV_CHn) based on the power control information (PCI1 to PCIn) of each of the plurality of channel data signals (DATA-CH1 to DATA-CHn). When the power control information (PCI1 to PCIn) is OFF, the bias current of the corresponding channel data voltage can be maintained as a current with a preset bias. When the power control information (PCI1 to PCIn) is ON, the bias current of the corresponding channel data voltage can be increased or decreased. As will be described later, the bias current of the corresponding channel data voltage can be increased or decreased based on the position information of the gate line. For example, the larger the bias current, the larger the slew rate of the channel data voltage (DV_CH1 to DV_CHn).

[0066] Meanwhile, the data driving device (130) may include a counter (131). The counter (131) may be provided to obtain position information of a gate line. For example, the counter (131) may count each of a plurality of horizontal periods included in one frame. As an example, each frame information and the plurality of horizontal period information included in each frame information may be included in a data control signal (DCS) and provided from the data processing device (110). As another example, each frame information and the plurality of horizontal period information included in each frame information may be provided from the data processing device (110) separately from the data control signal (DCS). Accordingly, the counter (131) may count each of a plurality of horizontal periods included in one frame provided from the data processing device (110).

[0067] The controller (132) can obtain position information of the gate line based on the counted number information from the counter (131). That is, the controller (132) can recognize the gate line (GL1 to GLm) that is currently activated by providing the scan signal based on the counted number information. For example, if the counted number from the counter (131) is 10, the 10th gate line (GL1 to GLm) may be currently activated.

[0068] The controller (132) can adjust the slew rate of each of the plurality of channel data voltages (DV_CH1 to DV_CHn) output from the plurality of output buffers (135-1 to 135-n) based on the position information of the gate line and the power control information (PCI1 to PCIn) of each of the plurality of channel data signals (DATA-CH1 to DATA-CHn). The operating method of the controller (132) is described with reference to FIG. 5.

[0069] FIG. 5 is a flowchart illustrating an operation method in a data processing device according to the first embodiment.

[0070] Referring to FIGS. 1 and 5, the controller (132) can determine the position of a currently activated gate line among a plurality of gate lines (GL1 to GLm) based on the position information of the gate line (S161). As described above, the controller (132) can receive counted number information from the counter (131). The controller (132) can obtain position information of the gate line based on the counted number information.

[0071] The controller (132) can select at least one output buffer (135-1 to 135-n) for adjusting the slew rate among the plurality of output buffers (135-1 to 135-n) based on the power control information (PCI1 to PCIn) of each of the plurality of channel data (S162).

[0072] The power control information (PCI1 to PCIn) may include information on whether to adjust the slew rate. For example, when the power control information (PCI1 to PCIn) includes OFF, the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from the corresponding output buffers (135-1 to 135-n) may not be adjusted but may be adjusted to a preset slew rate, i.e., a fourth slew rate. For example, when the power control information (PCI1 to PCIn) includes ON, the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from the corresponding output buffers (135-1 to 135-n) may be adjusted to a slew rate different from the fourth slew rate, e.g., a first slew rate, a second slew rate, and a third slew rate. Accordingly, the controller (132) may obtain power control information set to ON from among the power control information (PCI1 to PCIn) of each of the plurality of channel data. The controller (132) can select the corresponding output buffer based on the power control information set to ON and the channel digital data constituting the power control information and the channel data signal.

[0073] The controller (132) can receive a plurality of channel data signals (DATA-CH1 to DATA-CHn) for each horizontal period included in each frame from the data processing device (110). The controller (132) can obtain power control information (PCI1 to PCIn) and channel digital data (DCH1 to DCHn) from each of the plurality of channel data signals (DATA-CH1 to DATA-CHn) (Fig. 2). The obtained plurality of channel digital data (DCH1 to DCHn) can be provided to the channel data voltage generation unit (134) and converted into a plurality of channel data voltages (DV_CH1 to DV_CHn).

[0074] The controller (132) can adjust the slew rate of the channel data voltage (DV_CH1 to DV_CHn) output from at least one selected output buffer (135-1 to 135-n) according to the position of the currently activated gate line determined above (S163).

[0075] Meanwhile, the display panel (140) may include a plurality of regions in which the length direction of a plurality of data lines (DL1 to DLn) is distinguished. The plurality of regions may be a plurality of gate line groups, and each of the plurality of gate line groups may include at least two gate lines (GL1 to GLm). The plurality of gate groups may be composed of, for example, three or more.

[0076] In this case, the controller (132) can differently adjust the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from at least one selected output buffer (135-1 to 135-n) according to the gate line group including the currently activated gate line (GL1 to GLm) among the plurality of gate line groups.

[0077] As a first example, the controller (132) can adjust the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from the selected at least one output buffer (135-1 to 135-n) to the first slew rate when the gate line group including the currently activated gate lines (GL1 to GLm) is located in the middle among the plurality of gate line groups. Specifically, when the gate line group including the currently activated gate lines (GL1 to GLm) is located in the middle among the plurality of gate line groups, the controller (132) can control the bias current control unit (133) to adjust the bias current of the channel data voltages (DV_CH1 to DV_CHn) output from the selected at least one output buffer (135-1 to 135-n) to the first bias current. The above-mentioned selected at least one output buffer (135-1 to 135-n) can adjust the slew rate of the channel data voltage (DV_CH1 to DV_CHn) output from the above-mentioned selected at least one output buffer (135-1 to 135-n) to a first slew rate according to the first bias current.

[0078] As a second example, the controller (132) can adjust the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from the selected at least one output buffer (135-1 to 135-n) to a second slew rate lower than the first slew rate as the gate line group included in the currently activated gate line (GL1 to GLm) is closer to the selected at least one output buffer (135-1 to 135-n). Specifically, when a gate line group including a currently activated gate line (GL1 to GLm) is close to at least one selected output buffer (135-1 to 135-n), the controller (132) can control the bias current control unit (133) to adjust the bias current of the channel data voltage (DV_CH1 to DV_CHn) output from the at least one selected output buffer (135-1 to 135-n) to a second bias current lower than the first bias current. The at least one selected output buffer (135-1 to 135-n) can adjust the slew rate of the channel data voltage (DV_CH1 to DV_CHn) output from the at least one selected output buffer (135-1 to 135-n) to a second slew rate lower than the first slew rate according to the second bias current.

[0079] As a third example, the controller (132) can adjust the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from the selected at least one output buffer (135-1 to 135-n) to a third slew rate that is higher than the first slew rate as the gate line group included in the currently activated gate line (GL1 to GLm) moves away from the selected at least one output buffer (135-1 to 135-n). Specifically, when a gate line group including a currently activated gate line (GL1 to GLm) is far from the at least one selected output buffer (135-1 to 135-n), the controller (132) can control the bias current control unit (133) to adjust the bias current of the channel data voltage (DV_CH1 to DV_CHn) output from the at least one selected output buffer (135-1 to 135-n) to a third bias current higher than the first bias current. The at least one selected output buffer (135-1 to 135-n) can adjust the slew rate of the channel data voltage (DV_CH1 to DV_CHn) output from the at least one selected output buffer (135-1 to 135-n) to a third slew rate higher than the first slew rate according to the third bias current.

[0080] Meanwhile, in S162 of FIG. 6, in the case of an unselected output buffer (135-1 to 135-n) among a plurality of output buffers (135-1 to 135-n), that is, an output buffer (135-1 to 135-n) whose slew rate is not adjusted, the controller (132) can maintain the slew rate of the channel data voltage (DV_CH1 to DV_CHn) output from the unselected output buffer (135-1 to 135-n) at the fourth slew rate according to the position of the currently activated gate line.

[0081] For example, the fourth slew rate may be a value set as default. In the case of an unselected output buffer (135-1 to 135-n) among the plurality of output buffers (135-1 to 135-n), regardless of which gate line group the currently activated gate line (GL1 to GLm) is included in among the plurality of gate line groups, the slew rate of the channel data voltage (DV_CH1 to DV_CHn) output from the unselected output buffer (135-1 to 135-n) may be maintained at the fourth slew rate.

[0082] For example, the fourth slew rate may be a value between the second slew rate and the third slew rate, and may be a default value. For example, the fourth slew rate may be the same as the first slew rate, but this is not limited thereto.

[0083] Meanwhile, it is assumed that the display panel (140) is divided into a first gate line group, a second gate line group, and a third gate line group in a direction away from the data driving device (130).

[0084] If the gate line group included in the currently activated gate line is the second gate line group, the controller (132) can adjust the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from the selected at least one output buffer (135-1 to 135-n) to the first slew rate. Accordingly, the channel data voltages (DV_CH1 to DV_CHn) adjusted to the first slew rate from the selected at least one output buffer (135-1 to 135-n) can be provided to the pixels connected to the currently activated gate line.

[0085] If the gate line group included in the currently activated gate line is the first gate line group, the controller (132) can adjust the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from the selected at least one output buffer (135-1 to 135-n) to a second slew rate lower than the first slew rate. Therefore, as shown in FIG. 6A, even if the second slew rate is adjusted lower than the first slew rate, since the RC delay is small due to proximity to the data driving device (130), the transition time (T11) of the channel data voltages (DV_CH1 to DV_CHn) output from the selected at least one output buffer (135-1 to 135-n) is short, so that an image having a desired gradation can be displayed, thereby improving the picture quality. In addition, power consumption can be reduced by outputting channel data voltages (DV_CH1 to DV_CHn) adjusted to a second slew rate lower than the first slew rate from at least one of the selected output buffers (135-1 to 135-n).

[0086] If the currently activated gate line is included in a third gate line group located further from the data driving device (130) than the second gate line group, the RC delay in the third gate line group is greater than the RC delay in the first gate line group. In this case, if the gate line group including the currently activated gate line is the third gate line group, the controller (132) can adjust the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output from the at least one selected output buffer (135-1 to 135-n) to a third slew rate higher than the first slew rate. Accordingly, as shown in Fig. 6b, by adjusting to a third slew rate that is higher than the first slew rate, even if the RC delay is large, the transition time (T12) of the channel data voltage (DV_CH1 to DV_CHn) output from at least one selected output buffer (135-1 to 135-n) is shortened, so that an image having a desired grayscale can be displayed, thereby improving the image quality.

[0087] According to the first embodiment, the output data voltage is provided at different slew rates depending on the distance from the data driving device (130) on the display panel, thereby improving the picture quality and reducing the power consumption.

[0088] According to the first embodiment, whether to adjust the slew rate of each of the plurality of channel data voltages (DV_CH1 to DV_CHn) output from the plurality of output buffers (135-1 to 135-n) is determined based on the power control information (PCI1 to PCIn) provided from the data processing device (110), thereby significantly reducing power consumption. For example, depending on the plurality of channels, there may be no or minimal change in the grayscale of the image for each line, or the grayscale change may be large. Therefore, by determining whether to adjust the slew rate for each gate line for each of the plurality of channels based on the power control information (PCI1 to PCIn) provided for each of the plurality of channels from the data processing device (110), not only can power consumption be significantly reduced, but also optimized power consumption management can be enabled.

[0089]

[0090] [Example 2]

[0091] Fig. 7 is a block diagram illustrating a display device according to a second embodiment.

[0092] The second embodiment is identical to the first embodiment except that the position information of the gate lines (LI1 to LIn in FIG. 8) is provided from the data processing device (110A) to the data driving device (130A). In the second embodiment, components having the same functions as those in the first embodiment are given the same drawing reference numerals and detailed descriptions are omitted.

[0093] Referring to FIG. 7, a display device (100A) according to the second embodiment may include a data processing device (110A), a gate driving device (120), a data driving device (130A), and a display panel (140).

[0094] The data processing device (110A) may include a counter (111), a processor (112), and a channel data signal (DATA-CH1 to DATA-CHn) generation unit (113).

[0095] The counter (111) may have the same function as the counter (111) of the first embodiment (Fig. 1). That is, the counter (111) may count each of a plurality of horizontal periods included in one frame. Information on the plurality of horizontal periods may be included in an externally provided video signal or provided by the processor (112).

[0096] The processor (112) can manage or control the display device (100A) according to the second embodiment as a whole. The processor (112) can obtain a plurality of channel data signals (DATA-CH1 to DATA-CHn) for each of a plurality of horizontal periods per frame from an externally provided video signal. The plurality of channel data signals (DATA-CH1 to DATA-CHn) can include a plurality of channel digital data (DCH1 to DCHn).

[0097] The processor (112) can obtain position information (LI1 to LIn) of the gate line based on the count information from the counter (111).

[0098] The processor (112) can acquire power control information (PCI1 to PCIn) for each of multiple channel digital data (DCH1 to DCHn). Since acquisition of power control information (PCI1 to PCIn) has been described above (Fig. 5), a detailed description thereof is omitted.

[0099] The processor (112) can control the channel data signal (DATA-CH1 to DATA-CHn) generation unit (113) to generate new multiple channel data signals (DATA-CH1 to DATA-CHn) that are different from the multiple channel data signals (DATA-CH1 to DATA-CHn) obtained from the image signal, and provide the new multiple channel data signals (DATA-CH1 to DATA-CHn) to the data driving device (130A). The new multiple channel data signals (DATA-CH1 to DATA-CHn) can be provided to the data driving device (130A) for each horizontal period. The multiple channel data signals (DATA-CH1 to DATA-CHn) obtained from the image signal may be named multiple first channel data signals (DATA-CH1 to DATA-CHn), and the new multiple channel data signals (DATA-CH1 to DATA-CHn) may be named multiple second channel data signals (DATA-CH1 to DATA-CHn), or vice versa.

[0100] Each of the new multiple channel data signals (DATA-CH1 to DATA-CHn) may include power control information (PCI1 to PCIn), gate line position information (LI1 to LIn), and multiple channel digital data (DCH1 to DCHn), as illustrated in FIG. 8. The temporal order of the power control information (PCI1 to PCIn) and the gate line position information (LI1 to LIn) may be changed.

[0101] The data driving device (130A) may include a controller (132), a bias current control unit (133), and a channel data voltage generation unit (134). The channel data voltage generation unit (134) may include a plurality of output buffers (135-1 to 135-n).

[0102] The controller (132) can receive a plurality of second channel data signals (DATA-CH1 to DATA-CHn) from the data processing device (110A) every horizontal period (1H). The controller (132) can obtain power control information (PCI1 to PCIn), position information of gate lines (LI1 to LIn), and channel digital data (DCH1 to DCHn) from each of the plurality of second channel data signals (DATA-CH1 to DATA-CHn). The plurality of channel digital data (DCH1 to DCHn) can be provided to the channel data voltage generation unit (134) every horizontal period (1H).

[0103] The channel data voltage generation unit (134) can provide a plurality of channel data voltages (DV_CH1 to DV_CHn) corresponding to a plurality of channel digital data of a plurality of second channel data signals (DATA-CH1 to DATA-CHn) to the display panel (140) through a plurality of channels, i.e., a plurality of output buffers (135-1 to 135-n). The plurality of channel data voltages (DV_CH1 to DV_CHn) can be provided to the display panel (140) in units of one horizontal period (1H), i.e., one line.

[0104] Meanwhile, the controller (132) may adjust the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output to the selected output buffer (135-1 to 135-n) among the plurality of output buffers (135-1 to 135-n) based on the power control information (PCI1 to PCIn) and the position information (LI1 to LIn) of the gate line, and may maintain the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output to the unselected output buffer (135-1 to 135-n) among the plurality of output buffers (135-1 to 135-n) at the default value, i.e., the fourth set value. Since the method of adjusting the slew rate of the channel data voltages (DV_CH1 to DV_CHn) output to the selected output buffer (135-1 to 135-n) has been described above, a detailed description thereof will be omitted.

[0105] Meanwhile, typically, the line width of the circuit pattern of the data processing device (110A) is about 3 to 10 times larger than the line width of the circuit pattern of the data processing device (110A). Accordingly, when a counter (111) having the same structure is designed for each of the data processing device (110A) and the data driving device (130A), the occupied area of ​​the counter (111) of the data driving device (130A) is 3 to 10 times larger than the occupied area of ​​the counter (111) of the data processing device (110A).

[0106] According to the second embodiment, since the counter (111) for counting the number of times of a plurality of horizontal periods is not provided in the data driving device (130A) but is provided in the data processing device (110A), the size of the data driving device (130A) can be drastically reduced. In addition, since the counter (111) is not provided in the data driving device (130A), the circuit can be simplified and the computational burden can be reduced. Meanwhile, in the case where the data driving device (130A) is provided with a plurality of source drivers (or source driving circuits), since the counter is provided in the data processing device (110A), it does not need to be provided in each source driver, and thus the area efficiency can be good overall.

[0107] The above detailed description should not be construed as limiting in any respect and should be considered illustrative only. The scope of the embodiments should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalency range of the embodiments are intended to be included within the scope of the embodiments.

Claims

1. In a data driving device for driving a display panel including a plurality of gate lines and a plurality of data lines, A plurality of output buffers that output a plurality of channel data voltages corresponding to a plurality of channel data signals for each gate line provided from a data processing device to the plurality of data lines; and a controller for controlling the plurality of output buffers; The above controller, Controlling the slew rate of each of the plurality of channel data voltages output from the plurality of output buffers based on the position information of the gate line and the power control information of each of the plurality of channel data signals. Data driven device.

2. In paragraph 1, The above controller, Based on the position information of the above gate lines, the position of the currently activated gate line among the plurality of gate lines is determined, Selecting at least one output buffer for adjusting the slew rate among the plurality of output buffers based on the power control information of each of the plurality of channel data signals, Adjusting the slew rate of the channel data voltage output from the selected at least one output buffer according to the position of the currently activated gate line determined above. Data driven device.

3. In paragraph 2, The display panel includes a plurality of gate line groups separated along the length direction of the plurality of data lines, The above controller, Differently controlling the slew rate of the channel data voltage output from the selected at least one output buffer according to the gate line group including the currently activated gate line among the plurality of gate line groups. Data driven device.

4. In paragraph 3, The above controller, In the case where the gate line group is close to at least one output buffer selected based on the middle gate line group among the plurality of gate line groups, the slew rate of the channel data voltage output from the at least one selected output buffer is adjusted to the first slew rate, In the case where the gate line group is far from the at least one output buffer selected based on the intermediate gate line group, the slew rate of the channel data voltage output from the at least one output buffer selected is adjusted to a second slew rate higher than the first slew rate. Data driven device.

5. In paragraph 1, 1. A counter counting each horizontal period; The above controller, Obtaining position information of the gate line based on the number of counted 1 horizontal periods above, Data driven device.

6. In paragraph 1, A bias current control unit that controls a bias current to be provided to each of the plurality of output buffers based on the position information of the gate line and the power control information of each of the plurality of channel data signals; The slew rate of each of the plurality of channel data voltages is adjusted according to the above-mentioned adjusted bias current. Data driven device.

7. In paragraph 1, At least one of the position information of the gate line and the power control information is provided from the data processing device. Data driven device.

8. In paragraph 1, At least one of the position information of the gate line and the power control information is included in each of the plurality of channel data signals for each gate line provided from the data processing device. Data driven device.

9. A display panel including a plurality of gate lines and a plurality of data lines; A data driving device for driving the above display panel; and A data processing device that controls the data driving device; The above data processing device, Provides multiple channel data signals to the data driving device for each gate line, Each of the above multiple channel data signals includes power control information, The above data driving device, A plurality of output buffers that output a plurality of channel data voltages corresponding to a plurality of channel data signals for each of the gate lines to the plurality of data lines; and a controller for controlling the plurality of output buffers; The above controller, Controlling the slew rate of each of the plurality of channel data voltages output from the plurality of output buffers based on the position information of the gate line and the power control information of each of the plurality of channel data signals. Display device.

10. In paragraph 9, The above controller, Based on the position information of the above gate lines, the position of the currently activated gate line among the plurality of gate lines is determined, Selecting at least one output buffer for adjusting the slew rate among the plurality of output buffers based on the power control information of each of the plurality of channel data signals, Adjusting the slew rate of the channel data voltage output from the selected at least one output buffer according to the position of the currently activated gate line determined above. Display device.

Images