Display apparatus

Abstract

Disclosed is a display apparatus comprising: a substrate; a semiconductor layer disposed on the substrate and having a first region, a second region, and a channel region; a gate electrode disposed on the semiconductor layer and overlapping the channel region; and a pixel electrode electrically connected to the first region located in one direction from the channel region of the semiconductor layer, wherein the second region is located farther from the channel region than the first region.

Description

display device

[0001] Embodiments of the present invention relate to a display device, and more particularly, to a display device that can be used for a long time even using a conventional battery.

[0002] Typically, a display device has a display panel and operates by receiving power from a power source. Portable display devices may include a battery or other power source.

[0003] However, since the power dissipation of these batteries is limited, there was a problem that the batteries had to be replaced or charged to continue using the display device.

[0004] The present invention aims to address various issues, including those described above, by providing a display device that can be used for extended periods of time even using a conventional battery. However, these challenges are exemplary and should not be construed as limiting the scope of the present invention.

[0005] According to one aspect of the present invention, a display device is provided, comprising: a substrate; a semiconductor layer disposed on the substrate and having a first region, a second region, and a channel region; a gate electrode disposed on the semiconductor layer and overlapping the channel region; and a pixel electrode electrically connected to the first region located in one direction from the channel region of the semiconductor layer, wherein the second region is located farther from the channel region than the first region.

[0006] The second region may be located in the one direction from the channel region.

[0007] It may further include a first electrode contacting the first region and electrically connected to the pixel electrode, and a second electrode contacting the second region.

[0008] The above substrate may include a first substrate, a second substrate on top of the first substrate, and a substrate intermediate layer between the first substrate and the second substrate.

[0009] The above substrate intermediate layer may include amorphous silicon or crystalline silicon.

[0010] The above channel region may be doped with a first type, which is either an n type or a p type, and the first region and the second region may be doped with a second type, which is the other of the n type and the p type.

[0011] The doping concentration in the second region may be higher than the doping concentration in the first region.

[0012] A third region located in a different direction from the above channel region can be doped with the second type.

[0013] The doping concentration in the second region may be higher than the doping concentration in the third region.

[0014] The doping concentration in the first region and the doping concentration in the third region may be substantially the same.

[0015] A battery for driving the above display device may be further provided, and the second region may be electrically connected to the battery.

[0016] The second region may be electrically connected to a rectifier circuit, and the rectifier circuit may be electrically connected to the battery.

[0017] The above gate electrode may be a gate electrode of a driving transistor.

[0018] A display device is provided, comprising a substrate, a gate electrode on the substrate, a semiconductor layer including a channel region disposed between the substrate and the gate electrode and overlapping the gate electrode, a first region positioned in one direction from the channel region, and a second region positioned further from the channel region than the first region, a charge connection electrode contacting the second region, and a battery electrically connected to the charge connection electrode.

[0019] The second region may be located in the one direction from the channel region.

[0020] It may further include a transmission line contacting the first region and a pixel electrode electrically connected to the transmission line.

[0021] The above substrate may include a first substrate, a second substrate on top of the first substrate, and a substrate intermediate layer between the first substrate and the second substrate.

[0022] The above substrate intermediate layer may include amorphous silicon or crystalline silicon.

[0023] The above channel region may be doped with a first type, which is either an n type or a p type, and the first region and the second region may be doped with a second type, which is the other of the n type and the p type.

[0024] The doping concentration in the second region may be higher than the doping concentration in the first region.

[0025] Other aspects, features and advantages other than those described above will become apparent from the following detailed description, claims and drawings for carrying out the invention.

[0026] According to one embodiment of the present invention, as described above, a display device capable of long-term use can be implemented even using a conventional battery. Of course, the scope of the present invention is not limited by these effects.

[0027] FIG. 1 is a plan view schematically illustrating a display panel included in a display device according to one embodiment of the present invention.

[0028] Figure 2 is an equivalent circuit diagram of one pixel included in the display panel of Figure 1.

[0029] FIG. 3 is a layout diagram schematically showing the locations of transistors, capacitors, etc. in the pixels included in the display panel of FIG. 1.

[0030] Figures 4 to 10 are schematic layout diagrams showing components such as transistors and capacitors of the display panel illustrated in Figure 3 in layers.

[0031] FIG. 11 is a cross-sectional view schematically illustrating a cross-section taken along line II' of the display panel illustrated in FIG. 3.

[0032] Figure 12 is a conceptual diagram schematically illustrating a display device according to one embodiment of the present invention.

[0033] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The embodiments are provided by way of illustration so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, components, and techniques that are not necessary for a full understanding of the aspects and features of the present disclosure may not be described. Unless otherwise stated, the same reference numbers designate the same components in the accompanying drawings and description, and thus, a redundant description thereof will not be repeated.

[0034] The embodiments are capable of various modifications and implementations in different forms, and are not limited to the described embodiments. The use of "can," "may," or "may not" in describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure includes all modifications, equivalents, and alternatives within the spirit and technical scope of the present disclosure. Furthermore, the features of the various embodiments of the present disclosure may be partially or wholly combined with each other, and various technical combinations and separations are possible. Each embodiment may be implemented independently of each other or may be implemented in combination with each other.

[0035] In the drawings, the relative sizes, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified for clarity. Furthermore, the use of hatching in the drawings generally serves to clarify boundaries between adjacent components. Therefore, the use of hatching or hatching elements, unless otherwise specified, does not imply any particular material, material property, size, characteristic, commonality between the depicted components, and / or the characteristics, features, etc. of the components.

[0036] Various embodiments are described with reference to schematic drawings and / or cross-sectional views of intermediate structures of the embodiments. Therefore, various variations from the illustrated shapes can be expected, such as as a result of manufacturing techniques and / or tolerances. Furthermore, the description of specific structures or functions disclosed is for illustrative purposes only, for the purpose of explaining embodiments according to the concept of the present disclosure. Therefore, embodiments of the present disclosure should not be construed as limited to the illustrated shapes of components, layers, or regions, and may include variations in shapes resulting from, for example, manufacturing processes.

[0037] For example, an injection zone depicted as a rectangle may typically have rounded or curved edges, and the injection concentration at that edge may change gradually (gradiently) rather than in a two-part transition from the injected zone to the non-injected zone. Similarly, a buried zone formed by an injection may result in the injection occurring in the region between the buried zone and the surface where the injection was performed.

[0038] Spatially relative terms such as "below," "lower," "under," "above," "top," and the like may be used for convenience in describing the relationship of an element or feature depicted in the drawings to other element(s) or features. The spatially relative terms should be understood to encompass not only the orientation depicted in the drawings, but also different orientations of the device when in use or operation. For example, if the device in the drawings were turned over, other elements or features described as "below" or "under" or "below" may now be positioned "above" the other elements or features. Thus, the exemplary terms "below" and "bottom" can encompass both the above and below orientations. The device may be positioned in different orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein should be interpreted accordingly. Similarly, when the first part is described as being placed "above" the second part, this is not limited to the upper side based on the direction of gravity, but means that the first part is placed above or below the second part.

[0039] Additionally, the phrase "in plan view" means a top view of an object, and the phrase "in schematic cross-section" means a side view of a schematic cross-section taken by cutting vertically through a portion of an object. The terms "overlap" or "superimposed" may mean that a first object can be positioned above or below a second object, or vice versa. Furthermore, the term "overlap" may include stack, facing, extending upward, covering, or partially covering, or other suitable terms that would be expected and understood by a person skilled in the art. The term "non-overlap" may include "spaced apart," "away from," or "offset," and other suitable terms that would be expected and understood by a person skilled in the art. The term "facing" may mean that a first object directly or indirectly faces a second object. When a third object intervenes between a first object and a second object, the first object and the second object can be understood as still facing each other, but indirectly facing each other.

[0040] When a component, layer, region, or component is "formed on," "positioned on," "connected to," or "(operably or communicatively) coupled to" another component, layer, region, or component, it can be directly formed on, positioned on, connected to, or coupled to the other component, layer, region, or component, or there can be other intervening components, layers, regions, or components that are indirectly formed on, positioned on, connected to, or coupled to the other component, layer, region, or component. Furthermore, this can collectively mean direct or indirect coupling or connection, and can mean integral or inhomogeneous coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or coupled to that other layer, region, and / or component, or there can be one or more intervening layers, regions, or components. The one or more intervening components can include switches, resistors, capacitors, etc. In describing the embodiments, the term "connection" refers to an electrical connection unless there is a clear description of a direct connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or coupled to another component, or is located directly on another component, without any intermediate components.

[0041] Furthermore, in the present specification, when a part of a layer, film, region, plate, etc. is formed on another part, the direction of formation is not limited to the upper direction, and includes forming the part on the side or forming it in the lower direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "underneath" another part, it includes not only the case where the part is formed "directly underneath" the other part, but also the case where another part exists between the part and the other part. Meanwhile, other expressions describing the relationship between components, such as "between," "directly between," or "adjacent" and "directly adjacent," may be interpreted similarly. When an element or layer is referred to as being located "between" two elements or layers, it may be the only element or layer between those two elements or layers, or there may be one or more intervening elements or layers.

[0042] For the purposes of this disclosure, when phrases such as "at least one," "any one," or "one or more" precede a list of elements, they modify the list of elements as a whole, but do not modify individual elements of the list. For example, phrases such as "at least one of X, Y, and Z," "at least one of X, Y, or Z," "one or more selected from the group consisting of X, Y, and Z," and "one or more selected from the group consisting of X, Y, or Z" can mean X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, phrases such as "at least one of A and B" and "at least one of A or B" can include A, B, or A and B. Herein, "or" generally means "and / or," and the term "and / or" can include any and all combinations of one or more of the associated elements. For example, "A and / or B" can include A, B, or both A and B. Similarly, expressions such as "at least one," "a plurality of," "an," and other phrases, when preceded by a list of elements, can modify the list of elements as a whole, but do not modify individual elements of the list.

[0043] Although terms such as "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, such elements, components, regions, layers, and / or portions are not limited by such terms. These terms do not correspond to any particular order, position, or priority, but may be used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, first component, first region, first layer, or first portion described below may also be referred to as a second element, second component, second region, second layer, or second portion, without departing from the spirit and scope of the present disclosure. A description of an element as a "first" element does not require or imply the presence of a second element or other elements. Terms such as "first," "second," etc. may be used to differentiate different categories or sets of elements. For brevity, the terms "first", "second", etc. may represent "first category (or first set)", "second category (or second set)", etc., respectively.

[0044] In the embodiment, the x-axis, y-axis, and z-axis are not limited to three axes on an orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other. The same can be applied to the first direction, the second direction, and / or the third direction.

[0045] The terminology used in this disclosure is for the purpose of describing embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well, unless the context clearly dictates otherwise. In the following description, the terms "comprises" or "has" and the like, when used in the detailed description, mean that features, integers, steps, operations, elements, and / or components described in the specification are present, but do not preclude the possibility that one or more other features, integers, steps, operations, elements, and / or components, and groups thereof, may be added.

[0046] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation, not degrees, and are intended to account for the inherent variation in a measured or calculated value that would be recognized by one of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% of the corresponding value. "About" or "approximately" means within an acceptable range of variation for a particular value as determined by one of ordinary skill in the art, including the stated value, taking into account the error associated with the measurement in question and the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or can mean within +-30%, +-20%, +-10%, or +-5% of the stated numerical value. Additionally, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure."

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined to be so. FIG. 1 is a plan view schematically illustrating a display panel (10) included in a display device according to one embodiment of the present invention. The display device according to this embodiment includes a display panel (10). Such a display device may be any device that includes a display panel (10). For example, the display device may be a variety of products such as a smartphone, a tablet, a laptop, or a portable television.

[0048] The display panel (10) includes a display area (DA) and a peripheral area (PA) outside the display area (DA) (e.g., in a plan view). The display area (DA) is a portion that displays an image, and a plurality of pixels may be arranged in the display area (DA). When viewed from a direction approximately perpendicular to the display panel (10), the display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a geometric shape. FIG. 1 illustrates that the display area (DA) has an approximately rectangular shape with rounded corners.

[0049] The peripheral area (PA) may be located outside the display area (DA). A portion of the peripheral area (PA) may have a width (in the x-axis direction) narrower than the width (in the x-axis direction) of the display area (DA). This structure allows at least a portion of the peripheral area (PA) to be bent, if necessary.

[0050] Of course, since the display panel (10) includes a substrate (100, see, for example, FIG. 11), it can be said that the substrate (100) has a display area (DA) and a peripheral area (PA) as described above. Hereinafter, for convenience, the substrate (100) is described as having a display area (DA) and a peripheral area (PA).

[0051] In the display area (DA), a plurality of data lines (DL) may be arranged to cross the display area (DA). Similarly, in the display area (DA), a plurality of power lines (PL) may be arranged to cross the display area (DA). In Fig. 1, for convenience, the data lines (DL) are indicated with solid lines and the power lines (PL) are indicated with dotted lines. However, the data lines (DL) and the power lines (PL) may be formed simultaneously or substantially simultaneously on the same layer using the same material.

[0052] The display panel (10) may also be said to have, if necessary, a main region (MR), a bending region (BR) outside the main region (MR), and a sub-region (SR) located on the opposite side of the main region (MR) with the bending region (BR) as the center. In the bending region (BR), the display panel (10) may be bent so that at least a portion of the sub-region (SR) overlaps the main region (MR) when viewed in the z-axis direction. Of course, the present invention is not limited to a bent display device, and may also be applied to a non-bent display device. The sub-region (SR) may be a non-display region. By bending the display panel (10) in the bending region (BR), the non-display region may not be visible when the display device is viewed from the front (in the -z direction), or even if it is visible, the visible area may be minimized.

[0053] A driving chip (20) or the like may be placed in the sub-region (BR) of the display panel (10). The driving chip (20) may include an integrated circuit that drives the display panel (10). This integrated circuit may be a data driving integrated circuit that generates a data signal, but the present invention is not limited thereto.

[0054] The driving chip (20) can be mounted on the sub-region (SR) of the display panel (10). The driving chip (20) is mounted on the same surface as the display surface of the display area (DA), but as the display panel (10) is bent in the bending area (BR) as described above, the driving chip (20) can be positioned on the back surface of the main area (MR).

[0055] A printed circuit board (30) or the like may be attached to an end of a sub-region (SR) of a display panel (10). This printed circuit board (30) or the like may be electrically connected to a driving chip (20) or the like through a plurality of pads arranged along one edge of the board.

[0056] Hereinafter, an organic light emitting display device according to an embodiment of the present invention will be described as an example, but the display device of the present invention is not limited thereto. As another embodiment, the display device of the present invention may be an inorganic light emitting display device (Inorganic Light Emitting Display or Inorganic EL Display device) or a display device such as a quantum dot light emitting display device (Quantum dot Light Emitting Display). For example, the light emitting layer of a display element included in the display device may include an organic material or an inorganic material. In addition, the display device may include a light emitting layer and a quantum dot layer positioned on a path of light emitted from the light emitting layer.

[0057] As described above, the display panel (10) includes a substrate (100). Various components included in the display panel (10) may be positioned on the substrate (100). The substrate (100) may include glass, metal, or polymer resin. As described above, when the display panel (10) is bent in the bending region (BR), the substrate (100) needs to have flexible or bendable characteristics. In this case, the substrate (100) may include a polymer resin such as, for example, polyethersulphone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0058] The display area (DA) contains multiple pixels. Each pixel is referred to as a subpixel and may include a display element such as an organic light-emitting diode (OLED). A pixel may emit light of, for example, red, green, blue, or white.

[0059] The pixel can be electrically connected to peripheral circuits arranged in a peripheral area (PA). A scan driving circuit, an emission control driving circuit, pads, a power supply line, and a common voltage line can be arranged in the peripheral area (PA). The scan driving circuit can provide a scan signal to the pixel through a scan line. The emission control driving circuit can provide an emission control signal to the pixel through a emission control line. The pad arranged in the peripheral area (PA) of the substrate (100) is exposed without being covered by an insulating layer and can be electrically connected to a printed circuit board (30). A terminal of the printed circuit board (30) can be electrically connected to a pad of the display panel (10).

[0060] The printed circuit board (30) transmits a signal or power of the control unit to the display panel (10). The control signal generated by the control unit can be transmitted to each of the driving circuits through the printed circuit board (30). In addition, the control unit can transmit a first power voltage to a power supply line and provide a second power voltage to a common voltage line. The first power voltage (e.g., ELVDD or driving voltage) is transmitted to each pixel through a power line (see PL of FIG. 1, voltage line (1830) of FIG. 10) connected to the power supply line, and the second power voltage (e.g., ELVSS or common voltage) can be transmitted to a common electrode (330, counter electrode, see FIG. 11) of the pixel connected to the common voltage line. The common voltage line may have a loop shape with one side, where the driving chip (20), etc., is located, open, and may have a shape that partially surrounds the display area (DA).

[0061] Meanwhile, the control unit generates a data signal, and the generated data signal can be transmitted to the pixel through the driving chip (20) and the data line (see DL of FIG. 1, data line (1810) of FIG. 10).

[0062] Note that "line" may mean "wiring." This also applies to the embodiments and variations thereof described below.

[0063] Fig. 2 is an equivalent circuit diagram of one pixel included in the display panel of Fig. 1. As illustrated in Fig. 2, one pixel (PX) may include a pixel circuit (PC) and an organic light-emitting diode (OLED) electrically connected thereto.

[0064] The pixel circuit (PC) may include a plurality of thin film transistors (T1 to T7) and a storage capacitor (Cst), as illustrated in FIG. 2. The plurality of thin film transistors (T1 to T7) and the storage capacitor (Cst) may be connected to signal lines (SL1, SL2, SLp, SLn, EL, DL), a first initialization voltage line (VL1), a second initialization voltage line (VL2), and a driving voltage line (PL). At least one of these lines, for example, the driving voltage line (PL), may be shared by neighboring pixels (PX).

[0065] The plurality of thin film transistors (T1 to T7) may include a driving transistor (T1), a switching transistor (T2), a compensation transistor (T3), a first initialization transistor (T4), an operation control transistor (T5), an emission control transistor (T6), and a second initialization transistor (T7).

[0066] An organic light-emitting diode (OLED) may include a pixel electrode and a counter electrode, and the pixel electrode of the OLED may be connected to a driving transistor (T1) via a light emission control transistor (T6) to receive a driving current, and the counter electrode may receive a second power supply voltage (ELVSS). The organic light-emitting diode (OLED) may generate light having a brightness corresponding to the driving current.

[0067] Some of the plurality of thin film transistors (T1 to T7) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs). For example, among the plurality of thin film transistors (T1 to T7), the compensation transistor (T3) and the first initialization transistor (T4) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs). Alternatively, among the plurality of thin film transistors (T1 to T7), the compensation transistor (T3), the first initialization transistor (T4), and the second initialization transistor (T7) may be NMOS and the rest may be PMOS. Alternatively, all of the plurality of thin film transistors (T1 to T7) may be NMOS or all of them may be PMOS. The plurality of thin film transistors (T1 to T7) may include amorphous silicon or polysilicon. If necessary, the thin film transistor that is an NMOS may include an oxide semiconductor. In the following, for convenience, the compensation transistor (T3) and the first initialization transistor (T4) are NMOS (n-channel MOSFETs) including oxide semiconductors, and the rest are PMOS (p-channel MOSFETs).

[0068] The signal lines may include a first scan line (SL1) transmitting a first scan signal (Sn), a second scan line (SL2) transmitting a second scan signal (Sn'), a previous scan line (SLp) transmitting a previous scan signal (Sn-1) to a first initialization transistor (T4), a subsequent scan line (SLn) transmitting a subsequent scan signal (Sn+1) to a second initialization transistor (T7), an emission control line (EL) transmitting an emission control signal (En) to an operation control transistor (T5) and an emission control transistor (T6), and a data line (DL) intersecting the first scan line (SL1) and transmitting a data signal (Dm).

[0069] The driving voltage line (PL) transmits a driving voltage (ELVDD) to the driving transistor (T1), the first initialization voltage line (VL1) transmits a first initialization voltage (Vint1) that initializes the driving transistor (T1), and the second initialization voltage line (VL2) can transmit a second initialization voltage (Vint2) that initializes a pixel electrode of an organic light-emitting diode (OLED).

[0070] A driving gate electrode of a driving transistor (T1) is connected to a storage capacitor (Cst) via a second node (N2), one of a source region and a drain region of the driving transistor (T1) is connected to a driving voltage line (PL) via a first node (N1) and an operation control transistor (T5), and the other of the source region and the drain region of the driving transistor (T1) can be electrically connected to a pixel electrode of an organic light-emitting diode (OLED) via a third node (N3) and an emission control transistor (T6). The driving transistor (T1) can receive a data signal (Dm) according to a switching operation of the switching transistor (T2) and supply a driving current to the organic light-emitting diode (OLED). That is, the driving transistor (T1) can control the amount of current flowing from the first node (N1) electrically connected to the driving voltage line (PL) to the organic light-emitting diode (OLED) in response to the voltage applied to the second node (N2) that changes according to the data signal (Dm).

[0071] The switching gate electrode of the switching transistor (T2) is connected to the first scan line (SL1) that transmits the first scan signal (Sn), one of the source region and the drain region of the switching transistor (T2) is connected to the data line (DL), and the other of the source region and the drain region of the switching transistor (T2) is connected to the driving transistor (T1) through the first node (N1) and can be connected to the driving voltage line (PL) via the operation control transistor (T5). The switching transistor (T2) can transmit the data signal (Dm) from the data line (DL) to the first node (N1) in response to the voltage applied to the first scan line (SL1). That is, the switching transistor (T2) can be turned on according to the first scan signal (Sn) received through the first scan line (SL1) and perform a switching operation to transmit the data signal (Dm) transmitted through the data line (DL) to the driving transistor (T1) through the first node (N1).

[0072] The compensation gate electrode of the compensation transistor (T3) is connected to the second scan line (SL2). Either the source region or the drain region of the compensation transistor (T3) can be connected to a pixel electrode of an organic light-emitting diode (OLED) via a third node (N3) and an emission control transistor (T6). The other of the source region or the drain region of the compensation transistor (T3) can be connected to a first capacitor electrode (CE1) of a storage capacitor (Cst) and a driving gate electrode of a driving transistor (T1) via a second node (N2). The compensation transistor (T3) can be turned on according to a second scan signal (Sn') received through the second scan line (SL2) to diode-connect the driving transistor (T1).

[0073] The first initialization gate electrode of the first initialization transistor (T4) may be connected to the previous scan line (SLp). Either the source region or the drain region of the first initialization transistor (T4) may be connected to the first initialization voltage line (VL1). The other of the source region or the drain region of the first initialization transistor (T4) may be connected to the first capacitor electrode (CE1) of the storage capacitor (Cst) and the driving gate electrode of the driving transistor (T1) via the second node (N2). The first initialization transistor (T4) may apply the first initialization voltage (Vint1) from the first initialization voltage line (VL1) to the second node (N2) in response to the voltage applied to the previous scan line (SLp). That is, the first initialization transistor (T4) can be turned on according to the previous scan signal (Sn-1) received through the previous scan line (SLp) and perform an initialization operation of transmitting the first initialization voltage (Vint1) to the driving gate electrode of the driving transistor (T1) to initialize the voltage of the driving gate electrode of the driving transistor (T1).

[0074] The operation control gate electrode of the operation control transistor (T5) is connected to the light emission control line (EL), and one of the source region and the drain region of the operation control transistor (T5) is connected to the driving voltage line (PL), and the other can be connected to the driving transistor (T1) and the switching transistor (T2) via the first node (N1).

[0075] The light emission control gate electrode of the light emission control transistor (T6) is connected to the light emission control line (EL), one of the source region and the drain region of the light emission control transistor (T6) is connected to the driving transistor (T1) and the compensation transistor (T3) via the third node (N3), and the other of the source region and the drain region of the light emission control transistor (T6) can be electrically connected to the pixel electrode of the organic light emitting diode (OLED).

[0076] The motion control transistor (T5) and the light emission control transistor (T6) are turned on simultaneously or substantially simultaneously according to the light emission control signal (En) received through the light emission control line (EL), so that the driving voltage (ELVDD) is transmitted to the organic light emitting diode (OLED) and the driving current flows to the organic light emitting diode (OLED).

[0077] The second initialization gate electrode of the second initialization transistor (T7) is connected to the subsequent scan line (SLn), one of the source region and the drain region of the second initialization transistor (T7) is connected to the pixel electrode of the organic light-emitting diode (OLED), and the other of the source region and the drain region of the second initialization transistor (T7) is connected to the second initialization voltage line (VL2) so as to receive the second initialization voltage (Vint2). The second initialization transistor (T7) is turned on according to the scan signal (Sn+1) received through the subsequent scan line (SLn) to initialize the pixel electrode of the organic light-emitting diode (OLED). The subsequent scan line (SLn) may be the same as the first scan line (SL1). In this case, the scan line transmits the same electrical signal with a time difference, and may function as the first scan line (SL1) or the next scan line (SLn). That is, the next scan line (SLn) may be the first scan line of a pixel adjacent to the pixel (PX) illustrated in FIG. 2 and electrically connected to the data line (DL).

[0078] The second initialization transistor (T7) may be connected to the first scan line (SL1) as illustrated in Fig. 2. However, the present invention is not limited thereto, and the second initialization transistor (T7) may be connected to the emission control line (EL) and driven according to the emission control signal (En).

[0079] The storage capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) of the storage capacitor (Cst) is connected to a driving gate electrode of a driving transistor (T1) via a second node (N2), and the second capacitor electrode (CE2) of the storage capacitor (Cst) is connected to a driving voltage line (PL). The storage capacitor (Cst) may store a charge corresponding to a difference between a driving gate electrode voltage of the driving transistor (T1) and a driving voltage (ELVDD).

[0080] The specific operation of each pixel (PX) according to one embodiment is as follows.

[0081] During the initialization period, when the previous scan signal (Sn-1) is supplied through the previous scan line (SLp), the first initialization transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving transistor (T1) is initialized by the first initialization voltage (Vint1) supplied from the first initialization voltage line (VL1).

[0082] During the data programming period, when the first scan signal (Sn) and the second scan signal (Sn') are supplied through the first scan line (SL1) and the second scan line (SL2), the switching transistor (T2) and the compensation transistor (T3) are turned on in response to the first scan signal (Sn) and the second scan signal (Sn'). At this time, the driving transistor (T1) is diode-connected by the turned-on compensation transistor (T3) and is forward biased. Then, the compensation voltage (Dm+Vth, Vth is a (-) value) that is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data signal (Dm) supplied from the data line (DL) is applied to the driving gate electrode of the driving transistor (T1). A driving voltage (ELVDD) and a compensation voltage (Dm+Vth) are applied to both ends of the storage capacitor (Cst), and a charge corresponding to the voltage difference between the two ends is stored in the storage capacitor (Cst).

[0083] During the emission period, the operation control transistor (T5) and the emission control transistor (T6) are turned on by the emission control signal (En) supplied from the emission control line (EL). A driving current is generated according to the voltage difference between the voltage of the driving gate electrode of the driving transistor (T1) and the driving voltage (ELVDD), and the driving current is supplied to the organic light-emitting diode (OLED) through the emission control transistor (T6).

[0084] As described above, some of the plurality of thin film transistors (T1 to T7) may include oxide semiconductors. For example, the compensation transistor (T3) and the first initialization transistor (T4) may include oxide semiconductors.

[0085] Since polysilicon has high reliability, it can be controlled to ensure that the intended current flows accurately. Therefore, in the case of the driving transistor (T1) that directly affects the brightness of the display device, a semiconductor layer made of polysilicon with high reliability is included, thereby enabling the implementation of a high-resolution display device. On the other hand, since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not large even if the driving time is long. That is, in the case of oxide semiconductors, even when driven at low frequencies, the color change of the image due to the voltage drop is not large, so low-frequency driving is possible. Therefore, by including oxide semiconductors in the compensation transistor (T3) and the first initialization transistor (T4), it is possible to implement a display device that prevents or reduces the occurrence of leakage current while reducing power consumption.

[0086] Meanwhile, such oxide semiconductors are sensitive to light, and thus, changes in current amount, etc. may occur due to external light. Therefore, a metal layer may be positioned under the oxide semiconductor to absorb or reflect external light. Accordingly, as illustrated in FIG. 2, each of the compensation transistor (T3) and the first initialization transistor (T4) including the oxide semiconductor may have gate electrodes positioned above and below the oxide semiconductor layer, respectively. That is, when viewed in a direction perpendicular to the upper surface of the substrate (100) (z-axis direction), the metal layer positioned under the oxide semiconductor may overlap with the oxide semiconductor.

[0087] FIG. 3 is a layout diagram schematically showing the positions of transistors and capacitors, etc., in the pixels included in the display panel of FIG. 1, FIGS. 4 to 10 are layout diagrams schematically showing components such as transistors and capacitors of the display panel illustrated in FIG. 3 layer by layer, and FIG. 11 is a cross-sectional diagram schematically showing a cross-section taken along line II' of the display panel illustrated in FIG. 3.

[0088] As illustrated in these drawings, the display device may include a first pixel (P1) and a second pixel (P2) that are adjacent to each other. The first pixel (P1) and the second pixel (P2) may be symmetrical with respect to an imaginary line as illustrated in FIG. 3, etc. Of course, the first pixel (P1) and the second pixel (P2) may have the same structure rather than a symmetrical structure. The first pixel (P1) may include a first pixel circuit (PC1), and the second pixel (P2) may include a second pixel circuit (PC2). Hereinafter, for convenience of explanation, some conductive patterns are described based on the first pixel circuit (PC1), but these conductive patterns may also be arranged symmetrically in the second pixel circuit (PC2). An organic light-emitting device (OLED) may be electrically connected to each of the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0089] A buffer layer (111, see FIG. 11) including silicon oxide, silicon nitride, or silicon oxynitride may be positioned on the substrate (100). The buffer layer (111) may prevent or reduce the phenomenon of metal atoms or impurities from diffusing from the substrate (100) to the first semiconductor layer (1100) positioned thereon. In addition, the buffer layer (111) may control the rate at which heat is provided during the crystallization process for forming the first semiconductor layer (1100), thereby allowing the first semiconductor layer (1100) to be uniformly crystallized.

[0090] A first semiconductor layer (1100) as illustrated in FIG. 4 may be disposed on a buffer layer (111). The first semiconductor layer (1100) may include a silicon semiconductor. For example, the first semiconductor layer (1100) may include amorphous silicon or polysilicon. Specifically, the first semiconductor layer (1100) may include polysilicon crystallized at a low temperature. If necessary, ions may be implanted into at least a portion of the first semiconductor layer (1100).

[0091] The driving transistor (T1), the switching transistor (T2), the operation control transistor (T5), the light emission control transistor (T6), and the second initialization transistor (T7) may be PMOS as described above, in which case these thin film transistors are positioned along the first semiconductor layer (1100) as illustrated in FIG. 4.

[0092] The semiconductor layer (1100) may include a first region (A1), a second region (A2), and a third region (A3), as illustrated in FIG. 4. This will be described later.

[0093] A first gate insulating layer (113, see, for example, FIG. 11) covers the first semiconductor layer (1100) and may be disposed on the substrate (100). The first gate insulating layer (113) may include an insulating material. For example, the first gate insulating layer (113) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0094] The first gate layer (1200) as illustrated in Fig. 5 may be positioned on the first gate insulating layer (113). In Fig. 5, the first gate layer (1200) is illustrated together with the first semiconductor layer (1100) for convenience. The first gate layer (1200) may include a first gate line (1210), a driving gate electrode (1220), a second gate line (1230), and a charging electrode (1240).

[0095] The first gate line (1210) may extend in the second direction (x-axis direction). The first gate line (1210) may be the first scan line (SL1) of FIG. 2 or a subsequent scan line (SLn). That is, for the first pixel (P1) as illustrated in FIG. 5, the first gate line (1210) may correspond to the first scan line (SL1) of FIG. 2, and for a pixel adjacent to the first pixel (P1) (in the +y direction), the first gate line (1210) may correspond to the subsequent scan line (SLn) of FIG. 2. Accordingly, the first scan signal (Sn) and the subsequent scan signal (Sn+1) may be applied to the pixels through the first gate line (1210). The portions overlapping the first semiconductor layer (1100) of the first gate line (1210) may be the switching gate electrode of the switching transistor (T2) and the second initialization gate electrode of the second initialization transistor (T7).

[0096] The driving gate electrode (1220) may have an isolated shape. The driving gate electrode (1220) is the gate electrode of the driving transistor (T1). For reference, the portion of the first semiconductor layer (1100) that overlaps with the driving gate electrode (1220) and the portion therearound may be referred to as a driving semiconductor layer.

[0097] The portion corresponding to the driving gate electrode (1220) of the first semiconductor layer (1100), that is, the portion overlapping the driving gate electrode (1220) of the first semiconductor layer (1100) when viewed in the direction perpendicular to the substrate (z-axis direction), may be referred to as a channel region (CA, see FIG. 11). As illustrated in FIG. 11, the first region (A1) and the second region (A2) of the first semiconductor layer (1100) are portions of one side of the first semiconductor layer (1100) centered on the driving gate electrode (1220), and the third region (A3) of the first semiconductor layer (1100) is a portion of the other side of the first semiconductor layer (1100) centered on the driving gate electrode (1220). The second region (A2) may be located further from the channel region (CA) than the first region (A1).

[0098] Here, the fact that the second region (A2) is located further from the channel region (CA) than the first region (A1) does not necessarily mean that the straight-line distance from the channel region (CA) to the second region (A2) is longer than the straight-line distance from the channel region (CA) to the first region (A1). Since the first semiconductor layer (1100) is patterned as illustrated in FIGS. 4 and 5, this may mean that the channel region (CA), the first region (A1), and the second region (A2) are sequentially located along the patterned first semiconductor layer (1100). Of course, even if the channel region (CA), the first region (A1), and the second region (A2) are not positioned sequentially, it may mean that the distance from the channel region (CA) to the second region (A2) measured along the shape of the first semiconductor layer (1100) is longer than the distance from the channel region (CA) to the first region (A1) measured along the shape of the first semiconductor layer (1100). For convenience, the case where the channel region (CA), the first region (A1), and the second region (A2) are positioned sequentially along the patterned first semiconductor layer (1100) will be described below.

[0099] The channel region (CA) of the first semiconductor layer (1100) may be doped with Type 1, which is either the n-type or the p-type, and the first region (A1) and the second region (A2) may be doped with Type 2, which is the other of the n-type and the p-type. For example, this may be achieved by doping the entire first semiconductor layer (1100) with Type 1, forming a first gate layer (1200), and then using the first gate layer (1200) as a mask to dope a portion of the first semiconductor layer (1100) that does not overlap with the first gate layer (1200) with Type 2. Accordingly, the third region (A3) on the other side of the channel region (CA) of the first semiconductor layer (1100) centered on the first gate layer (1200) may also be doped with Type 2. Since the third region (A3) is doped simultaneously or substantially simultaneously with the first region (A1) and the second region (A2), the doping concentration in the third region (A3) may be substantially the same as the doping concentrations in the first region (A1) and the second region (A2). Of course, if necessary, additional doping may be performed in the second region (A2) using a mask or the like so that the doping concentration in the second region (A2) is higher than the doping concentration in the first region (A1). In this way, when additional doping is performed in the second region (A2), the doping concentration in the second region (A2) may be higher than the doping concentration in the third region (A3).

[0100] If necessary, the doping of the first semiconductor layer (1100) may be performed in a different manner. For example, the first semiconductor layer (1100) may be entirely doped with either the n-type or the p-type, the first type, and then the first gate layer (1200) may be formed. Then, the first gate layer (1200) may be used as a mask to dope the portion of the first semiconductor layer (1100) that does not overlap with the first gate layer (1200) with the same first type again. Since the third region (A3) on the other side of the channel region (CA) is doped simultaneously or substantially simultaneously with the first region (A1) and the second region (A2), the doping concentration in the third region (A3) may be substantially the same as the doping concentrations in the first region (A1) and the second region (A2). Accordingly, the doping concentrations in the first region (A1), the second region (A2), and the third region (A3) can be higher than the doping concentration in the channel region (CA). Of course, if necessary, additional doping can be performed in the second region (A2) using a mask or the like so that the doping concentration in the second region (A2) is higher than the doping concentration in the first region (A1). In this way, when additional doping is performed in the second region (A2), the doping concentration in the second region (A2) can be higher than the doping concentration in the third region (A3).

[0101] The second gate line (1230) may extend in the second direction (x-axis direction). The second gate line (1230) may correspond to the light emission control line (EL) of FIG. 2. The portions of the second gate line (1230) overlapping with the first semiconductor layer (1100) may be the operation control gate electrode of the operation control transistor (T5) and the light emission control gate electrode of the light emission control transistor (T6). The light emission control signal (En) may be applied to the pixels through the second gate line (1230).

[0102] The charging electrode (1240) can be electrically connected to the second region (A2) of the first semiconductor layer (1100) as described above through the charging connection electrode (1350) described later. In addition, the charging electrode (1240) can be electrically connected to the charging line through the contact hole (1250CNT). For reference, FIG. 11 illustrates that the charging electrode (1240) contacts the lower metal layer (110) located between the substrate (100) and the buffer layer (111) through the contact hole (1250CNT). This lower metal layer (110) can be patterned in a shape like a wiring and function as a charging line electrically connected to a battery (420, see FIG. 12, for example) and / or a rectifier circuit (410, see FIG. 12, for example) of the display device. Of course, the charging electrode (1240) may be connected to a charging line formed by a conductive layer other than the lower metal layer (110).

[0103] The charging electrode (1240) may be integral with the neighboring first pixel (P1) and second pixel (P2) as illustrated in FIG. 5. In this case, the charging electrode (1240) may have a contact hole (1240CNT) shared by the first pixel (P1) and the second pixel (P2), and may be electrically connected to the charging line. This is because, in the case of charge supplied to the battery (420) for charging, there is no need to distinguish between the charge from the first pixel (P1) and the charge from the second pixel (P2). In addition, by having the first pixel (P1) and the second pixel (P2) share the charging electrode (1240), the structure of the pixels capable of supplying charge to the battery (420) can be further simplified.

[0104] The first gate layer (1200) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first gate layer (1200) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first gate layer (1200) may have a multilayer structure, for example, the first gate layer (1200) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0105] The second gate insulating layer (115, see FIG. 11) covers the first gate layer (1200) and may be positioned on the first gate insulating layer (113). The second gate insulating layer (115) may include an insulating material identical / similar to the first gate insulating layer (113).

[0106] A second gate layer (1300) as illustrated in FIG. 6 may be positioned on a second gate insulating layer (115). The second gate layer (1300) may include a third gate line (1310), a fourth gate line (1320), a capacitor upper electrode (1330), a first initialization voltage line (1340) (i.e., the first initialization voltage line (VL1) of FIG. 5), and a charge connection electrode (1350).

[0107] The third gate line (1310) may extend in the second direction (x-axis direction). The third gate line (1310) may correspond to the previous scan line (SLp) of FIG. 2. When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the third gate line (1310) may be spaced apart from the first gate line (1210). The previous scan signal (Sn-1) may be applied to pixels through the third gate line (1310). A portion of the third gate line (1310) overlapping with the second semiconductor layer (1400, see FIG. 7) described below may be a first initialization lower gate electrode of the first initialization transistor (T4).

[0108] The fourth gate line (1320) may also extend in the second direction (x-axis direction) and have an isolated shape. The fourth gate line (1320) may be electrically connected to the sixth gate line (1530) described below, and may correspond to the second scan line (SL2) of FIG. 2. When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the fourth gate line (1320) may be spaced apart from the first gate line (1210) and the third gate line (1310). The second scan signal (Sn') may be applied to pixels through the fourth gate line (1320). A portion of the fourth gate line (1320) overlapping with the second semiconductor layer (1400) described below may be a compensation lower gate electrode of the compensation transistor (T3).

[0109] The third gate line (1310) and the fourth gate line (1320) are located below the second semiconductor layer (1400) described later with reference to FIG. 7, and in addition to serving as gate electrodes, they can also serve as lower protective metals that protect portions overlapping with the third gate line (1310) and the fourth gate line (1320) of the second semiconductor layer (1400).

[0110] The capacitor upper electrode (1330) overlaps with the driving gate electrode (1220) and may extend in the second direction (x-axis direction). This capacitor upper electrode (1330) may correspond to the second capacitor electrode (CE2) of FIG. 2 and may form a storage capacitor (Cst) together with the driving gate electrode (1220). The driving voltage (ELVDD) may be applied to the capacitor upper electrode (1330). In addition, a hole penetrating the capacitor upper electrode (1330) may be formed in the capacitor upper electrode (1330), and at least a portion of the driving gate electrode (1220) may overlap with this hole.

[0111] A first initialization voltage line (1340) corresponding to the first initialization voltage line (VL1) of FIG. 2 may extend in the second direction (x-axis direction). When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the first initialization voltage line (1340) may be spaced apart from the third gate line (1310). The first initialization voltage (Vint1) may be applied to pixels through the first initialization voltage line (1340). The first initialization voltage line (1340) may overlap at least partially with a second semiconductor layer (1400) to be described later, and may transmit the first initialization voltage (Vint1) to the second semiconductor layer (1400). The first initialization voltage line (1340) can be electrically connected to the second semiconductor layer (1400) through contact holes (1680CNT1, 1680CNT2, and 1680CNT3) described later with reference to FIG. 9.

[0112] The charging connection electrode (1350) can contact the second region (A2) of the first semiconductor layer (1100) at least through the contact hole (1350CNT1). And the charging connection electrode (1350) can contact the charging electrode (1240) through the contact hole (1350CNT2). Accordingly, the second region (A2) of the first semiconductor layer (1100) can be electrically connected to the charging line through the charging connection electrode (1350) and the charging electrode (1240). For reference, FIG. 11 illustrates that the charging electrode (1240) contacts the lower metal layer (110) located between the substrate (100) and the buffer layer (111) through the contact hole (1250CNT). This lower metal layer (110) can be patterned in a form similar to a wire and function as a charging line electrically connected to a battery (420, see FIG. 12, for example) and / or a rectifier circuit (410, see FIG. 12, for example) of the display device. Of course, the charging electrode (1240) can also be connected to a charging line formed of a conductive layer of a layer other than the lower metal layer (110).

[0113] The charging connection electrode (1350) may be integral with the neighboring first pixel (P1) and second pixel (P2) as illustrated in FIG. 6. In this case, the charging connection electrode (1350) may define or have a contact hole (1350CNT1) that contacts the second region (A2) of the first semiconductor layer (1100) of the first pixel (P1) and a contact hole (1350CNT1) that contacts the second region (A2) of the first semiconductor layer (1100) of the second pixel (P2). In addition, the charging connection electrode (1350) may define or have a contact hole (1350CNT2) that is shared by the first pixel (P1) and the second pixel (P2), and may be electrically connected to the charging electrode (1240). This is because, in the case of the charge supplied to the battery (420) for charging, there is no need to distinguish between the charge from the first pixel (P1) and the charge from the second pixel (P2). In addition, by having the first pixel (P1) and the second pixel (P2) share the charging connection electrode (1350), the structure of the pixels capable of supplying charge to the battery (420) can be further simplified.

[0114] For reference, just as the charging connection electrode (1350) contacts the second region (A2) of the first semiconductor layer (1100), the fourth transmission line (1650, see, for example, FIG. 9) described below can contact the first region (A1) of the first semiconductor layer (1100). From this perspective, the fourth transmission line (1650) can be referred to as the first electrode, and the charging connection electrode (1350) can be referred to as the second electrode.

[0115] The second gate layer (1300) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second gate layer (1300) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second gate layer (1300) may have a multilayer structure, for example, the second gate layer (1300) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0116] The first interlayer insulating layer (117, see, for example, FIG. 11) covers the second gate layer (1300) and may be positioned on the second gate insulating layer (115). The first interlayer insulating layer (117) may include an insulating material. For example, the first interlayer insulating layer (117) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0117] A second semiconductor layer (1400) as illustrated in FIG. 7 may be positioned on the first interlayer insulating layer (117). As described above, the second semiconductor layer (1400) may include an oxide semiconductor. The second semiconductor layer (1400) may be positioned on a different layer from the first semiconductor layer (1100), and may not overlap with the first semiconductor layer (1100) when viewed in a direction perpendicular to the substrate (100) (z-axis direction).

[0118] A third gate insulating layer (118, see, for example, FIG. 11) covers the second semiconductor layer (1400) and may be disposed on the first interlayer insulating layer (117). The third gate insulating layer (118) may include an insulating material. If necessary, unlike that illustrated in FIG. 11, the third gate insulating layer (118) may be positioned only on a portion of the second semiconductor layer (1400) and not on the first interlayer insulating layer (117). In this case, the third gate insulating layer (118) may have the same pattern as the third gate layer (1500) described below with reference to FIG. 8. That is, when viewed in a direction perpendicular to the substrate (100) (z-axis direction), the third gate insulating layer (118) may perfectly or almost perfectly overlap the third gate layer (1500). This is because the third gate insulating layer (118) and the third gate layer (1500) are patterned simultaneously. Therefore, the second semiconductor layer (1400) may not have source and drain regions covered by the third gate insulating layer (118), except for the channel regions overlapping with the third gate layer (1500). The third gate insulating layer (118) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0119] A third gate layer (1500) as illustrated in FIG. 8 may be positioned on a third gate insulating layer (118). The third gate layer (1500) may include a fifth gate line (1520), a sixth gate line (1530), and a first transmission line (1540).

[0120] The fifth gate line (1520) may extend in the second direction (x-axis direction) and may have an isolated shape. When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the fifth gate line (1520) may overlap the third gate line (1310). The portion of the fifth gate line (1520) overlapping the second semiconductor layer (1400) may be the first initialization upper gate electrode of the first initialization transistor (T4). The portion of the second semiconductor layer (1400) overlapping the fifth gate line (1520) and the vicinity thereof may be referred to as the first initialization semiconductor layer. The fifth gate line (1520) may be electrically connected to the third gate line (1310). For example, the fifth gate line (1520) may be electrically connected to the third gate line (1310) through a contact hole (1520CNT) formed in an insulating layer between the fifth gate line (1520) and the third gate line (1310). Accordingly, the fifth gate line (1520) may correspond to the previous scan line (SLp) of FIG. 2 together with the third gate line (1310). Accordingly, the previous scan signal (Sn-1) may be applied to the pixels through the fifth gate line (1520) and / or the third gate line (1310).

[0121] The sixth gate line (1530) may extend in the second direction (x-axis direction). When viewed in a direction perpendicular to the substrate (100) (z-axis direction), the sixth gate line (1530) may overlap the fourth gate line (1320). The portion of the sixth gate line (1530) that overlaps the second semiconductor layer (1400) may be a compensation upper gate electrode of the compensation transistor (T3). The sixth gate line (1530) may be electrically connected to the fourth gate line (1320). For example, the sixth gate line (1530) may be electrically connected to the fourth gate line (1320) through a contact hole (1530CNT) formed in an insulating layer between the sixth gate line (1530) and the fourth gate line (1320). Accordingly, the sixth gate line (1530) can correspond to the second scan line (SL2) of FIG. 2 together with the fourth gate line (1320). Accordingly, the second scan signal (Sn') can be applied to the pixels through the sixth gate line (1530) and / or the fourth gate line (1320).

[0122] The first transmission line (1540) can be electrically connected to the driving gate electrode (1220) through a contact hole (1540CNT) passing through an opening (1330-OP) of the capacitor upper electrode (1330, for example, see FIG. 6). The first transmission line (1540) can transmit the first initialization voltage (Vint1) transmitted through the first initialization transistor (T4) to the driving gate electrode (1220).

[0123] The third gate layer (1500) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the third gate layer (1500) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third gate layer (1500) may have a multilayer structure, for example, the third gate layer (1500) may have a two-layer structure of Mo / Al or a three-layer structure of Mo / Al / Mo.

[0124] The second interlayer insulating layer (119, see, for example, FIG. 11) may cover at least a portion of the third gate layer (1500) of FIG. 8. The second interlayer insulating layer (119) may include an insulating material. For example, the second interlayer insulating layer (119) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0125] A first connection electrode layer (1600) as illustrated in Fig. 9 may be positioned on a second interlayer insulating layer (119). The first connection electrode layer (1600) may include a horizontal connection line (1610), a second transmission line (1620), a second initialization voltage line (1630), a third transmission line (1640), a fourth transmission line (1650), a fifth transmission line (1660), a sixth transmission line (1670), and a seventh transmission line (1680).

[0126] The horizontal connection line (1610) may extend in the second direction (x-axis direction). The horizontal connection line (1610), together with the vertical connection line (1820, see, for example, FIG. 10), may serve to transmit data signals to some pixels.

[0127] The second transmission line (1620) can be electrically connected to the first semiconductor layer (1100) through a contact hole (1620CNT, for example, see FIG. 9). A data signal (Dm) from a data line (1810) described later with reference to FIG. 10 can be transmitted to the first semiconductor layer (1100) through the second transmission line (1620) and applied to the switching transistor (T2).

[0128] The second initialization voltage line (1630) can extend in the second direction (x-axis direction). The second initialization voltage line (1630), which corresponds to the second initialization voltage line (VL2) of FIG. 2, can apply the second initialization voltage (Vint2) to the pixels. The second initialization voltage line (1630) is electrically connected to the first semiconductor layer (1100) through a contact hole (1630CNT), so that the second initialization voltage (Vint2) can be transmitted to the first semiconductor layer (1100) and applied to the second initialization transistor (T7).

[0129] The third transmission line (1640) can electrically connect the second semiconductor layer (1400) and the first transmission line (1540) through contact holes (1640CNT1, 1640CNT2) formed on one side and the other side, respectively. Since the first transmission line (1540) is electrically connected to the driving gate electrode (1220), the third transmission line (1640) can consequently electrically connect the first initialization semiconductor layer, which is a part of the second semiconductor layer (1400), to the driving gate electrode. The first initialization voltage (Vint1) can be transmitted to the driving gate electrode (1220) through the second semiconductor layer (1400), the third transmission line (1640), and the first transmission line (1540).

[0130] The fourth transmission line (1650) can electrically connect the second semiconductor layer (1400) and the first semiconductor layer (1100) through contact holes (1650CNT1, 1650CNT2) formed on one side and the other side. That is, the fourth transmission line (1650) can contact the first region (A1) of the first semiconductor layer (1100) through the contact hole (1650CNT2) and can contact the second semiconductor layer (1400) through the contact hole (1650CNT1). Accordingly, the fourth transmission line (1650) can electrically connect the compensation transistor (T3) and the driving transistor (T1). In this way, the fourth transmission line (1650) that contacts the first region (A1) of the first semiconductor layer (1100) through the contact hole (1650CNT2) can be electrically connected to the pixel electrode (310) through the light-emitting control transistor (T6), the sixth transmission line (1670), and the tenth transmission line (1840, see, for example, FIG. 10). This is because the first region (A1) of the first semiconductor layer (1100) that the fourth transmission line (1650) contacts is integral with the semiconductor layer of the light-emitting control transistor (T6).

[0131] The fifth transmission line (1660) can extend in the second direction (x-axis direction). A driving voltage (ELVDD), which is a constant voltage from a driving voltage line (1830) described later with reference to FIG. 10, is transmitted to the fifth transmission line (1660), and the fifth transmission line (1660) is electrically connected to the first semiconductor layer (1100) through a contact hole (1660CNT1) to transmit the driving voltage (ELVDD) to the first semiconductor layer (1100), for example, to an operation control transistor (T5). In addition, the fifth transmission line (1660), which is electrically connected to the capacitor upper electrode (1330) (i.e., the second capacitor electrode (CE2) of FIG. 2) through a contact hole (1660CNT2), can transmit the driving voltage (ELVDD) to the capacitor upper electrode (1330).

[0132] The sixth transmission line (1670) can be electrically connected to the first semiconductor layer (1100) through a contact hole (1670CNT). The sixth transmission line (1670) can transmit a driving current or a second initialization voltage (Vint2) from the first semiconductor layer (1100) to an organic light-emitting diode (OLED).

[0133] The seventh transmission line (1680) can be electrically connected to the second semiconductor layer (1400) through contact holes (1680CNT2 and 1680CNT3). In addition, the seventh transmission line (1680) can be electrically connected to the first initialization voltage line (1340) of FIG. 6 through the contact hole (1680CNT1). Through this, the seventh transmission line (1680) can transmit the first initialization voltage (Vint1) from the first initialization voltage line (1340) to the first initialization transistor (T4).

[0134] The first connection electrode layer (1600) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first connection electrode layer (1600) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first connection electrode layer (1600) may have a multilayer structure, for example, the first connection electrode layer (1600) may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0135] The third interlayer insulating layer (121) covers the first connection electrode layer (1600) and may be positioned on the second interlayer insulating layer (119). The third interlayer insulating layer (121) may include an insulating material. For example, the third interlayer insulating layer (121) may include silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. Of course, the third interlayer insulating layer (121) may include an organic insulating material as needed. For example, the third interlayer insulating layer (121) may include photoresist, BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0136] A second connection electrode layer (1800) as illustrated in Fig. 10 may be positioned on a third interlayer insulating layer (121). The second connection electrode layer (1800) may include a data line (1810), a vertical connection line (1820), a driving voltage line (1830), and a tenth transmission line (1840).

[0137] The data line (1810) may extend in the first direction (y-axis direction). The data line (1810) may correspond to the data line (DL) of FIG. 2. The data line (1810) is electrically connected to the second transmission line (1620) through a contact hole (1810CNT), so that a data signal (Dm) from the data line (1810) may be transmitted to the first semiconductor layer (1100) through the second transmission line (1620) and applied to the switching transistor (T2).

[0138] The vertical connection line (1820) may extend approximately in the first direction (y-axis direction). The vertical connection line (1820), together with the horizontal connection line (1610), may serve to transmit data signals to some pixels. To this end, the corresponding vertical connection line (1820) and the corresponding horizontal connection line (1610) may be interconnected through a contact hole.

[0139] The driving voltage line (1830) may extend approximately in the first direction (y-axis direction). The driving voltage line (1830) may correspond to the driving voltage line (PL) of FIG. 2. The driving voltage line (1830) may apply a driving voltage (ELVDD) to pixels. The driving voltage line (1830) may be electrically connected to the fifth transmission line (1660) through a contact hole (1830CNT), so that the driving voltage (ELVDD) may be transmitted to the operation control transistor (T5) and the capacitor upper electrode (1330) as described above. The driving voltage line (1830) of the first pixel circuit (PC1) may be integral with the driving voltage line (1830) of the adjacent second pixel circuit (PC2).

[0140] The tenth transmission line (1840) is electrically connected to the sixth transmission line (1670) through a contact hole (1840CNT1) and can receive a driving current or a second initialization voltage (Vint2) from the first semiconductor layer (1100) from the sixth transmission line (1670). In addition, the tenth transmission line (1840) can transmit the driving current or the second initialization voltage (Vint2) from the first semiconductor layer (1100) to a pixel electrode of an organic light-emitting diode (OLED) through a contact hole (1840CNT2) formed in an insulating layer positioned thereon.

[0141] The second connection electrode layer (1800) may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second connection electrode layer (1800) may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second connection electrode layer (1800) may have a multilayer structure, for example, the second connection electrode layer (1800) may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0142] A planarization insulating layer (125) as illustrated in FIG. 11 covers the second connection electrode layer (1800) and may be disposed on the third interlayer insulating layer (121). The planarization insulating layer (125) may include an organic insulating material. For example, the planarization insulating layer (125) may include BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0143] As illustrated in Fig. 11, an organic light-emitting diode (OLED) may be positioned on the planarization insulating layer (125). The organic light-emitting diode (OLED) may include a pixel electrode (310), an intermediate layer (320) including a light-emitting layer, and a counter electrode (330).

[0144] The pixel electrode (310) may be a (semi)transparent electrode or a reflective electrode. For example, the pixel electrode (310) may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer positioned on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO or ZnO2), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode (310) may have a three-layer structure of ITO / Ag / ITO.

[0145] A pixel definition film (127) may be disposed on the planarization insulating layer (125). The pixel definition film (127) may have an opening (OP) that exposes the central portion of the pixel electrode (310). This pixel definition film (127) may serve to prevent or reduce the occurrence of arcs or the like at the edge of the pixel electrode (310) by increasing the distance between the edge of the pixel electrode (310) and the counter electrode (330) above the pixel electrode (310).

[0146] The pixel definition film (127) is made of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, or phenol resin, and can be formed by a method such as spin coating.

[0147] At least a portion of the intermediate layer (320) of the organic light-emitting diode (OLED) may be positioned within an opening (OP) formed by a pixel definition film (127). The light-emitting area of ​​the organic light-emitting diode (OLED) may be defined by the opening (OP).

[0148] The intermediate layer (320) may include a light-emitting layer. The light-emitting layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular organic material or a high-molecular organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be further optionally disposed below and above the light-emitting layer.

[0149] The light-emitting layer may have a patterned shape corresponding to each of the pixel electrodes (310). Layers other than the light-emitting layer included in the intermediate layer (320) may be modified in various ways, such as being integrally formed across a plurality of pixel electrodes (310).

[0150] The counter electrode (330) may be a transparent electrode or a reflective electrode. For example, the counter electrode (330) may be a transparent or semitransparent electrode and may include Li, Ca, LiF, Al, Ag, Mg or a compound thereof. In addition, the counter electrode (330) may further include a TCO (transparent conductive oxide) film such as ITO, IZO, ZnO or In2O3 positioned on a metal thin film. The counter electrode (330) may be formed as a single body over the entire display area (DA) and may be disposed on the intermediate layer (320) and the pixel definition film (127).

[0151] An organic light-emitting diode (OLED) may be covered with a thin film encapsulation layer or may be covered with a sealing substrate. In one embodiment, the thin film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the thin film encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer therebetween.

[0152] The first and second inorganic sealing layers are made of silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), and may be formed by chemical vapor deposition (CVD), etc. The organic encapsulating layer may include a polymer-based material. Polymer-based materials may include silicone-based resins, acrylic-based resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.), epoxy-based resins, polyimides, and polyethylene.

[0153] Each of the first inorganic encapsulating layer, the organic encapsulating layer, and the second inorganic encapsulating layer can be formed integrally to cover the display area (DA).

[0154] As described above, the channel region (CA) of the first semiconductor layer (1100) may be doped with either the n-type or the p-type, the first type, and the first region (A1) and the second region (A2) may be doped with the other of the n-type and the p-type, the second type. Accordingly, a portion corresponding to the driving transistor (T1) of the first semiconductor layer (1100) may include a PN junction region by the first region (A1), the second region (A2), and the channel region (CA). When light such as ultraviolet rays incident from the outside of the display device into the display device reaches this PN junction region, current may flow in this PN junction region. Therefore, while the display device is not displaying an image in the display region (DA), the battery (420) of the display device may be charged using the current flowing in this PN junction region, thereby implementing a display device that can be used for a long time even using a conventional battery.

[0155] In order to increase the amount of current generated in the PN junction region, it is desirable to expand the area of ​​the PN junction region or increase its length. The first region (A1) of the first semiconductor layer (1100) is an essential component for implementing the pixel circuit (PC) as described above with reference to FIG. 2. Therefore, it may be considered to implement a PN junction region for charging the battery (420) or the like using only the channel region (CA) and the first region (A1). However, in the case of the display device according to the present embodiment, the first semiconductor layer (1100) is provided with a second region (A2) in addition to the first region (A1), and the PN junction region for charging the battery (420) or the like is implemented using the channel region (CA), the first region (A1), and the second region (A2). Accordingly, the amount of current generated in the PN junction region can be effectively increased.

[0156] In addition, in the case of the display device according to the present embodiment, as described above, the second region (A2) is positioned further from the channel region (CA) than the first region (A1), so that the amount of current generated in the PN junction region can be dramatically increased. Here, the fact that the second region (A2) is positioned further from the channel region (CA) than the first region (A1) may mean that the channel region (CA), the first region (A1), and the second region (A2) are sequentially positioned along the patterned first semiconductor layer (1100) as described above. Of course, even if the channel region (CA), the first region (A1), and the second region (A2) are not sequentially located, it may mean that the distance from the channel region (CA) to the second region (A2) measured along the shape of the first semiconductor layer (1100) is longer than the distance from the channel region (CA) to the first region (A1) measured along the shape of the first semiconductor layer (1100).

[0157] In this way, in the case of the display device according to the present embodiment, the charging electrode (1240) is made to contact the second area (A2), the charging electrode (1240) is electrically connected to the lower metal layer (110) patterned in the form of a wire, and the lower metal layer (110) functioning as a charging line is electrically connected to the battery (420) and / or the rectifier circuit (410) of the display device, so that a display device that can be used for a long time can be implemented even if a conventional battery is used.

[0158] Of course, the present invention is not limited to using the lower metal layer (110) as a charging line. For example, the horizontal connection line (1610) and the vertical connection line (1820) may play a role in transmitting data signals for some pixels. However, not all horizontal connection lines (1610) and vertical connection lines (1820) play a role in transmitting data signals. Therefore, by electrically connecting the charging electrode (1240) to the horizontal connection line (1610) and / or the vertical connection line (1820) that do not transmit data signals, and electrically connecting such horizontal connection line (1610) and / or the vertical connection line (1820) to the battery (420) and / or the rectifier circuit (410) of the display device, it is possible to implement a display device that can be used for a long time even when using a conventional battery.

[0159] Additionally, the doping concentration in the second region (A2) may be made higher than the doping concentration in the first region (A1). This increases the number of electrons guided to the second region (A2), thereby enhancing the charging efficiency.

[0160] Meanwhile, as illustrated in FIG. 11, the substrate (100) may include two layers (101, 103) including the polymer resin as described above, and a substrate intermediate layer (102) interposed between the layers (101, 103). That is, the substrate (100) may include a first substrate (103), a second substrate (101) positioned thereon, and a substrate intermediate layer (102) interposed therebetween. This substrate intermediate layer (102) may serve to adhere the two layers (101, 103), and may also serve as a barrier to prevent or reduce impurities from the outside from passing through the substrate (100). Furthermore, this substrate intermediate layer (102) may include amorphous silicon or crystalline silicon. In this case, when light such as ultraviolet rays from the outside is irradiated onto the substrate intermediate layer (102), electron-hole pairs can be formed within the substrate intermediate layer (102). At this time, when an on-bias is applied from the driving transistor (T1) or the like above, electrons or holes can move. Through this, not only the charges generated in the PN junction region of the first semiconductor layer (1100) but also the charges generated in the substrate intermediate layer (102) can be used to charge a battery (420), thereby dramatically increasing the efficiency. For example, since amorphous silicon has a light absorption coefficient that is about 10 times higher than that of crystalline silicon, the efficiency can be increased by making the substrate intermediate layer (102) include amorphous silicon.

[0161] As described above, the second region (A2) of the first semiconductor layer (1100) can be electrically connected to the battery (420), and FIG. 12 is a conceptual diagram schematically illustrating such a configuration. As illustrated in FIG. 12, the display panel (10) can be electrically connected to the battery (420). Accordingly, power can be supplied from the battery (420) to display an image on the display region (DA), and when an image is not displayed on the display region (DA), charges generated using external light can be supplied to the battery (420) to charge the battery (420). Connecting the display panel (10) to the battery (420) for charging may mean that the charging electrode (1240) contacting the second region (A2) of the first semiconductor layer (1100) is electrically connected to the battery (420) via a charging line or the like. This can be understood as the second region (A2) of the first semiconductor layer (1100) being electrically connected to the battery (420). Of course, as illustrated in FIG. 12, the second region (A2) of the first semiconductor layer (1100) can be electrically connected to a rectifier circuit (410) via a charging line or the like, and the rectifier circuit (410) can be electrically connected to the battery (420). The rectifier circuit (410) can rectify an electrical signal supplied to the battery (420) using a diode or the like, and can also have a capacitor to protect the battery (420).

[0162] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible. Therefore, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims, and functionally equivalents thereof should be included therein.

[0163] The present invention can be used in the field of display devices that can be used for a long time even when using a conventional battery.

Claims

1. Substrate; A semiconductor layer disposed on the substrate and having a first region, a second region, and a channel region; A gate electrode disposed on the semiconductor layer and overlapping the channel region; and A pixel electrode electrically connected to the first region located in one direction from the channel region of the semiconductor layer; Equipped with, A display device, wherein the second region is located further away from the channel region than the first region.

2. In paragraph 1, A display device, wherein the second region is located in the one direction from the channel region.

3. In paragraph 1, A first electrode contacting the first region and electrically connected to the pixel electrode; and A second electrode contacting the second region; A display device further comprising:

4. In paragraph 1, The above substrate is, First board; A second substrate on top of the first substrate; and An intermediate layer of a substrate between the first substrate and the second substrate; A display device having a .

5. In paragraph 4, A display device, wherein the above-mentioned substrate intermediate layer comprises amorphous silicon or crystalline silicon.

6. In paragraph 1, A display device, wherein the channel region is doped with type 1, which is either an n-type or a p-type, and the first region and the second region are doped with type 2, which is the other of the n-type and the p-type.

7. In paragraph 6, A display device, wherein the doping concentration in the second region is higher than the doping concentration in the first region.

8. In paragraph 7, A display device, wherein a third region located in a different direction from the above channel region is doped with the second type.

9. In paragraph 8, A display device, wherein the doping concentration in the second region is higher than the doping concentration in the third region.

10. In paragraph 8, A display device wherein the doping concentration in the first region and the doping concentration in the third region are substantially the same.

11. In paragraph 1, A battery is further provided for driving the above display device, The second region is a display device electrically connected to the battery.

12. In paragraph 11, A display device, wherein the second region is electrically connected to a rectifier circuit, and the rectifier circuit is electrically connected to the battery.

13. In paragraph 1, A display device, wherein the above gate electrode is the gate electrode of a driving transistor.

14. Substrate; A gate electrode on the above substrate; A semiconductor layer disposed between the substrate and the gate electrode, the semiconductor layer including a channel region overlapping the gate electrode, a first region positioned in one direction from the channel region, and a second region positioned further from the channel region than the first region; A charging connection electrode contacting the second region; and A battery electrically connected to the above charging connection electrode; A display device having a .

15. In paragraph 14, A display device, wherein the second region is located in the one direction from the channel region.

16. In paragraph 14, A transmission line contacting the first area; and A pixel electrode electrically connected to the above transmission line; A display device further comprising:

17. In paragraph 14, The above substrate is, First board; A second substrate on top of the first substrate; and An intermediate layer of a substrate between the first substrate and the second substrate; A display device having a .

18. In paragraph 17, A display device, wherein the above-mentioned substrate intermediate layer comprises amorphous silicon or crystalline silicon.

19. In paragraph 14, A display device, wherein the channel region is doped with type 1, which is either an n-type or a p-type, and the first region and the second region are doped with type 2, which is the other of the n-type and the p-type.

20. In paragraph 19, A display device, wherein the doping concentration in the second region is higher than the doping concentration in the first region.

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