Incremental compilation method and system based on heterogeneous device

Abstract

Disclosed in the present invention are an incremental compilation method and system based on a heterogeneous device. The method comprises: a user using P4 to develop a network program, performing a syntax and semantic check on the network program, and converting same into an intermediate representation; allocating an intermediate representation file on the basis of constraints, such as functions and resources of a heterogeneous device; then converting the network program into different rule expressions of the heterogeneous device on the basis of the constraints of the heterogeneous device, flow table entries, etc., and loading the different rule expressions to a target device; when the user needs to incrementally deploy a network function, the user only needing to compile a new network program to regenerate rule expressions; and by means of comparing and analyzing the old and new rule expressions, forming rule expressions which can be loaded to the heterogeneous device, thereby realizing incremental deployment of the network function. In the present invention, during the process of loading a newly added network function, uninterrupted processing performed by an old network function can be realized, and incremental deployment of a network function is realized on a heterogeneous device without interrupting the network function.

Description

Incremental compilation method and system based on heterogeneous devices Technical Field

[0001] The present invention relates to the field of computer network technology, and in particular to an incremental compilation method and system based on heterogeneous devices. Background Art

[0002] In recent years, programmability in the network data plane has advanced significantly. After users develop network functions, compilers compile the program and distribute it to programmable devices, enabling the corresponding network functions. Network applications and network device hardware are no longer tightly coupled, and users no longer need to wait months for device manufacturers to update their products when network functions change. However, existing implementations still have shortcomings. This programmability is static; after a period of compilation and installation, network functions cannot be added at runtime. Adding new network functions at runtime requires recompilation and reloading to the programmable device, which inevitably causes program interruptions and prevents seamless upgrades of network applications.

[0003] Summary of the Invention

[0004] The purpose of the present invention is to address the deficiencies of the prior art and provide a heterogeneous device-based incremental compilation method and system.

[0005] To achieve the above object, the present invention provides an incremental compilation method based on heterogeneous devices, comprising the following steps:

[0006] (1) Develop network programs using P4, perform basic syntax and semantic checks on network programs, and convert them into intermediate representations;

[0007] (2) Modeling the functional constraints and resource constraints of heterogeneous devices; allocating intermediate representations to different heterogeneous device units based on the functional constraints and resource constraints of the heterogeneous devices; the heterogeneous device units include ASIC units and FPGA units;

[0008] (3) Different heterogeneous device units generate different rule expressions for heterogeneous devices based on function mapping conversion rules and flow table information, and then load the rule expressions onto the heterogeneous devices;

[0009] (4) Develop a network program containing the new network function through P4, and regenerate the rule expression of the new network function through steps (1) to (3); compare and analyze the new and old rule expressions to form a rule expression that can be loaded onto heterogeneous devices, and complete the incremental deployment of the network function.

[0010] Furthermore, in step (2), the ASIC unit and the FPGA unit are connected via a built-in Serdes interface.

[0011] Furthermore, the step (2) includes the following sub-steps:

[0012] (2.1) Modeling the functional constraints and resource constraints of heterogeneous devices, including modeling the functional constraints and resource constraints of ASIC units and FPGA units in heterogeneous devices;

[0013] (2.2) According to the functional constraints and resource constraints of the heterogeneous devices, the intermediate representation is allocated to different units of the heterogeneous devices based on the ASIC unit priority allocation principle.

[0014] Furthermore, in the sub-step (2.1), the functional constraints and resource constraints of the ASIC units in the heterogeneous devices are modeled as follows:

[0015] Constrain the addition and deletion of ASIC units, T aw Indicates the length of the starting position of the increase operation offset, T dw Indicates the length of the starting position of the deletion operation offset, T AW Indicates the maximum offset that the ASIC unit supports for the increase operation, T DW Indicates the maximum offset of the delete operation supported by the ASIC unit, T as Indicates the length of the added data segment, T ds Indicates the length of the deleted data segment, T AS Indicates the maximum length of the data segment supported by the ASIC unit, T DS Indicates the maximum length of the data segment that the ASIC unit supports deleting, F AH Indicates the operation of adding a data packet header field, F DH Indicates the operation of deleting the packet header field, m represents the functional unit placed on the heterogeneous device, x m,A ∈{0,1} indicates whether m is placed on the ASIC unit; the functional constraints of adding and deleting ASIC units are expressed as follows:

[0016] Constrain the modification function of the ASIC unit, T cw Indicates the length of the starting position of the increase operation offset, T CW Indicates the maximum offset that the ASIC unit supports modification operations, T cs Indicates the length of the modified data segment, T CS Indicates the maximum length of the data segment that the ASIC unit supports modification, F CH Indicates adding a data packet header field operation. The modified function constraint of the ASIC unit is expressed as follows:

[0017] Modeling the UDF resources of the ASIC unit, LK ∈[0,14,34] represents the offset length of the starting position of different matching offsets; S L Indicates the length of the matching offset, M L Indicates the length of the match, I LA Indicates the maximum value of the range of packet header fields that the ASIC unit supports matching, a p,A ∈{0,1} indicates whether p is placed on the ASIC unit, N MA represents the maximum number of matches that the ASIC unit can support, Θ(x) is the indicator function, M A Indicates the maximum match length supported by the ASIC unit, M m Indicates the actual length that the functional unit m needs to match, F ET represents the exact match table, F LTT represents a ternary matching table; the matching resource constraint of the ASIC unit is expressed as follows:

[0018] Furthermore, in the sub-step (2.1), the resource constraints and functional constraints of the FPGA unit in the heterogeneous device are modeled as follows:

[0019] Constraint modeling is performed on the functions of the FPGA unit, and constraints are imposed on the FPGA unit's functions of adding, modifying, and deleting data packet header fields; IL Indicates the increased data segment length, F CL Indicates the length of the modified data segment, F DL Indicates the length of the deleted data segment, G IL Indicates the maximum length of the data segment supported by the FPGA unit, G CL Indicates the maximum length of the data segment that the FPGA unit supports modification, G DL Indicates the maximum length of the data segment that the FPGA unit supports deleting, F headerG Indicates the actions supported by the FPGA unit; the functional constraints of the FPGA unit are expressed as follows:

[0020] Constraint modeling for parsing and matching resources of FPGA units, L parser Indicates the maximum jump length that the FPGA unit can support, S h represents the set of headers deployed in the FPGA unit, V(h) represents the validity of the header field h, V(h) = 1 means the header field is valid, otherwise it is invalid; the constraints on the FPGA unit header parsing are expressed as follows:

[0021] Constraint modeling of matching resources of FPGA units, K GIndicates the maximum length of the match supported by the FPGA unit, K m Indicates the actual matching length of functional unit m, N MG Indicates the maximum number of matches that the FPGA can support, a p,G ∈{0,1} indicates whether p should be placed on the FPGA unit, x m,G ∈{0,1} indicates whether m is placed on the FPGA unit; M G represents the set of all functional units placed on the FPGA unit; the constraints on the matching resources of the FPGA unit are expressed as follows:

[0022] Furthermore, in step (3), the function mapping conversion rule is specifically as follows: converting the intermediate representations assigned to different units of the heterogeneous device into json format information in combination with the corresponding flow table, and then converting it into a rule expression of the heterogeneous device.

[0023] Furthermore, the step (4) includes the following sub-steps:

[0024] (4.1) Develop a network program containing new network functions through P4 and regenerate the rule expression of the new network functions;

[0025] (4.2) Compare and analyze the new and old rule expressions; if the new and old network function rule expressions do not intersect, directly send the new network function rule expression to the corresponding heterogeneous device unit to form a rule expression that can be loaded onto the heterogeneous device, thereby realizing incremental deployment of the network function; if the new and old network function rule expressions intersect, compare and analyze the new and old rule expressions, merge or split the corresponding rule expressions to form a rule expression that can be loaded onto the heterogeneous device, thereby completing incremental deployment of the network.

[0026] To achieve the above object, the present invention further provides an incremental compilation system based on heterogeneous devices, comprising:

[0027] The front-end compilation module is used to perform basic syntax and semantic checks on network programs and convert them into intermediate representations;

[0028] A mid-end distribution module, configured to distribute the intermediate representation to different heterogeneous device units; the heterogeneous device units include ASIC units and FPGA units;

[0029] The backend compilation module is used to generate different rule expressions for heterogeneous devices based on function mapping conversion rules and flow table information, and then load the rule expressions onto the heterogeneous devices;

[0030] The rule expression strategy module is used to compare and analyze the new and old rule expressions to form a rule expression that can be loaded onto heterogeneous devices.

[0031] To achieve the above-mentioned purpose, the present invention also provides an electronic device, including a memory and a processor, wherein the memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the above-mentioned incremental compilation method based on heterogeneous devices.

[0032] To achieve the above objectives, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which implements the above-mentioned incremental compilation method based on heterogeneous devices when executed by a processor.

[0033] Compared with the existing technology, the present invention has the following advantages: It utilizes heterogeneous hardware devices, and through the collaboration of a mid-end allocation module and a rule expression policy module, it solves the problem of interruptions caused by adding new network functions to traditional devices during operation, enabling hot updates of network functions without affecting existing services. Compared with existing technologies, when adding new network functions, the present invention does not require recompiling all functional programs and loading them onto the platform, which would cause interruptions to existing services. Instead, it only compiles the new functional programs and loads them onto the heterogeneous devices, seamlessly upgrading network functions. Furthermore, by rationally modeling the resources and functional constraints of heterogeneous devices, the present invention enables the collaborative operation of heterogeneous units within heterogeneous devices, resolving the problem of network developers needing to use different development languages ​​to develop network functions for devices with different architectures. The present invention shields network developers from the differences between the underlying heterogeneous units, allowing network programmers to use a unified P4 network programming language to achieve incremental deployment of network functions on heterogeneous hardware devices without interrupting network functions. The present invention is simple to implement, has a low user threshold, and significantly guarantees the quality of network function service. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a flow chart of the method of the present invention;

[0035] FIG2 is a flow chart of the system of the present invention;

[0036] FIG3 is a flowchart of the mid-end allocation module processing of the present invention;

[0037] FIG4 is a processing flow chart of the ASIC back-end compilation module of the present invention;

[0038] FIG5 is a schematic diagram of an electronic device. DETAILED DESCRIPTION

[0039] The present invention will be described in detail below with reference to the accompanying drawings. Unless there is any conflict, the features of the following embodiments and implementations may be combined with each other.

[0040] Example 1

[0041] Referring to FIG1 , the present invention provides an incremental compilation method based on heterogeneous devices, comprising the following steps:

[0042] Step 1: Users develop network programs using the protocol-independent packet processors (P4) programming language. The front-end compilation module then performs basic syntax and semantic checks on the P4-developed network programs and converts them into an intermediate representation (IR).

[0043] Step 2: Model the resource constraints, functional constraints, and other information of heterogeneous devices. The mid-end allocation module distributes the intermediate representation (IR) to different heterogeneous device units based on the resource constraints, functional constraints, and other information of heterogeneous devices. The heterogeneous device units here include ASIC units and FPGA units. The ASIC unit has programmable parsing capabilities, and the FPGA unit has programmable packet processing capabilities. The ASIC unit and FPGA unit are connected via a built-in SerDes interface.

[0044] As shown in FIG3 , step 2 is implemented through the following sub-steps:

[0045] (2.1) Modeling information such as resource constraints and functional constraints of heterogeneous devices. The ASIC unit implements programmable parsing of data packets through UDFs and adds, deletes, and modifies data packet header fields through ACLs and FlexE. The resources and specific functional information in the ASIC unit include: the type and number of UDFs, where the type includes the match offset and match length range. Specifically, the position of the data field to be matched in the packet header is determined by the offset starting position and offset length, and the value of the target matching packet field is determined by matching the extracted length and flow table information; ACL functions include redirection, mirroring, and multicast, which primarily modify the packet forwarding path without changing the value of the packet field; programmable editing functions include support for adding, modifying, and deleting data segments of a specified length at a specified offset starting from the Layer 2, Layer 3, and Layer 4 headers of the packet. Specifically, the position of the data field to be modified in the packet header is determined by specifying the offset starting position and offset length, and the target value of the field to be modified is determined by the extracted length and flow table information. The FPGA unit mainly implements programmable parsing of data packets through a combination of LUTs, registers, and RAM. It uses LUTs to implement integer addition and subtraction operations, and uses RAM resources to implement operations on adding, deleting, and modifying data packet header fields. At the same time, the FPGA unit also supports basic operations on data packets: redirection, multicast, discard, and other functions.

[0046] (2.1.1) Model the resource and specific functional constraints of the ASIC unit of heterogeneous devices. First, constrain the modeling of the functions of the ASIC unit. The functions supported by the ASIC unit include two categories: one is not to change the value of the packet header field (redirection, mirroring, multicast); the other is to add, delete, modify the packet header field, etc. Since the former is not subject to resource constraints, the latter is the main constraint here. Constrain the addition and deletion functions of the ASIC unit, T aw Indicates the length of the starting position of the increase operation offset, T aw ∈[0,14,34] (0 means offset from the second layer header, 14 means offset from the third layer header, 34 means offset from the fourth layer header), T dw Indicates the length of the starting position of the deletion operation offset, T AW Indicates the maximum offset supported by the ASIC unit for the increase operation. In this embodiment, T AW =126B, B represents byte, T DW Indicates the maximum offset of the delete operation supported by the ASIC unit. In this embodiment, T DW =126B, T as Indicates the length of the added data segment, T ds Indicates the length of the deleted data segment, T AS Indicates the maximum length of the data segment supported by the ASIC unit. In this embodiment, T AS =48B, T DS Indicates the maximum length of the data segment that the ASIC unit supports deleting. In this embodiment, T DS =48B,F AH Indicates the operation of adding a data packet header field, F DH Indicates the operation of deleting the packet header field, m represents the functional unit placed on the heterogeneous device, x m,A ∈{0,1} indicates whether m should be placed on the ASIC unit; the constraints on adding and deleting the ASIC unit are expressed as follows:

[0047] Constrain the modification function of the ASIC unit, T cw Indicates the length of the starting position of the increase operation offset, T cw ∈[0,14,34] (0 means offset from the second layer header, 14 means offset from the third layer header, 34 means offset from the fourth layer header), T CW Indicates the maximum offset supported by the ASIC unit for modification operations. In this embodiment, T CW =96B,T cs Indicates the length of the modified data segment, T CSIndicates the maximum length of the data segment that the ASIC unit supports modification. In this embodiment, T CS =16B,F CH Indicates adding a packet header field operation. The constraint on the modification function of the ASIC unit is expressed as follows:

[0048] That is, when the length of the data packet field that needs to be added, deleted, or modified is greater than the maximum length that the ASIC unit can support, and the offset exceeds the maximum offset that the ASIC unit can support, the functional unit for adding, deleting, and modifying the data packet field is 0 on the ASIC unit, that is, the intermediate representation IR corresponding to the functional unit cannot be allocated to the ASIC unit for implementation.

[0049] Secondly, the UDF resources of the ASIC unit are modeled. K ∈[0,14,34] represents the offset length of the starting position of different matching offsets (0 means offset from the second layer header, 14 means offset from the third layer header, and 34 means offset from the fourth layer header); S L Indicates the length of the matching offset, M L Indicates the length of the match, I LA Indicates the maximum value of the range of packet header fields that the ASIC unit supports matching. In this embodiment, LA =128B; a p,A ∈{0,1} indicates whether p should be placed on the ASIC unit, where p∈m,x m,A ∈{0,1} indicates whether m should be placed on the ASIC unit; N MA Indicates the maximum number of matches that the ASIC unit can support. In this embodiment, N MA =112. Θ(x) is the indicator function, which is equal to 1 when x satisfies the condition and equal to 0 when it does not. A Indicates the maximum match length supported by the ASIC unit, M m Indicates the actual length that the functional unit m needs to match, F ET represents the exact match table, F LTT represents a ternary matching table; the matching resource constraints of the ASIC unit are expressed as follows:

[0050] (2.1.2) Modeling the resource and functional constraints of the FPGA unit in the heterogeneous device. First, the constraint modeling is performed on the function of the FPGA unit. Like the ASIC unit, the constraints are mainly on the FPGA's ability to add, modify, and delete data packet header fields; IL Indicates the increased data segment length, F CL Indicates the length of the modified data segment, F DLIndicates the length of the deleted data segment, G IL Indicates the maximum length of the data segment supported by the FPGA unit, G CL Indicates the maximum length of the data segment that the FPGA unit supports modification, G DL Indicates the maximum length of the data segment that the FPGA unit supports deleting, F headerG Indicates the actions supported by the FPGA unit, F headerG ={F AH ,F CH ,F DH}, F AH Indicates the operation of adding a data packet header field, F CH Indicates the operation of adding a data packet header field, F DH Indicates the operation of deleting the packet header field; the functional constraints of the FPGA unit are expressed as follows:

[0051] Secondly, constraint modeling is performed for the parsing and matching resources of the FPGA unit. The P4 header parsing process can be regarded as a jump of the state machine. The maximum jump length supported by the FPGA is L parser , S h Represents the set of headers deployed in the FPGA unit, V(h) represents the validity of the header field h, V(h) = 1 means the header field is valid, otherwise it is invalid. The constraints on the header parsing of the FPGA unit are expressed as follows:

[0052] Constraint modeling of FPGA matching resources, K G Indicates the maximum length of the match supported by the FPGA unit, K m Indicates the actual matching length of functional unit m, N MG Indicates the maximum number of matches that the FPGA can support, a p,G ∈{0,1} indicates whether p should be placed on the FPGA unit, where p∈m, m represents the functional unit placed on the heterogeneous device, and x m,G ∈{0,1} indicates whether m should be placed on the FPGA unit; M G Represents the set of all functional units placed on the FPGA. The constraints on the matching resources of the FPGA units are expressed as follows:

[0053] (2.2) The mid-end allocation module allocates the intermediate representation IR to different units of the heterogeneous device based on the resource constraints, functional constraints and other information of the heterogeneous device and the principle of ASIC unit priority allocation; that is, when both the ASIC unit and the FPGA unit can run the functional unit, the functional unit is allocated to the ASIC unit first.

[0054] Step 3: The back-end compilation modules of different units of heterogeneous devices generate different rule expressions for heterogeneous devices based on the function mapping conversion rules and flow table information, and finally load the rule expressions onto the heterogeneous devices to realize the loading of user functions. The function mapping conversion rules are as follows: the back-end compilation module converts the intermediate representation IR assigned to different units of the heterogeneous device into json format information in combination with the corresponding flow table information, and then converts it into the rule expression of the heterogeneous device. As shown in Figure 4, taking the intermediate representation IR assigned to the ASIC unit by the mid-end allocation module as an example, the code written by the user in P4 language is as follows: key = hdr.ipv4.dst_addr, action; ipv4_set_egress_port(bit <9> port){standard_metadata.egress_spec=port;},

[0055] The front-end compilation module compiles the above code into an intermediate representation (IR). The mid-end distribution module distributes the IR to the ASIC unit. The back-end compiler of the ASIC unit converts the corresponding flow table information into JSON format information. Specifically, p4.IngressPipeImpl.ipv4_exact.add_with_ipv4_set_egress_port(dst_addr=0x0A000003,port=3) matches the data packet with the destination IP address 10.0.0.3 and forwards it from port 3. The JSON format information is as follows:

[0056] Among them, key: user_offset in dst_addr refers to the length of the matching offset, that is, S L =240 bits, length refers to the length of the match, that is, M L =32 bits, start=L2, indicating L K =0; key: S in etherType L =96 bits, M L =16 bits, L K=0; both keys satisfy the UDF resource constraints on the ASIC unit in sub-step (2.2); the action is redirect, that is, mapped to the keyword redirect, which satisfies the function constraints on the ASIC unit in sub-step (2.2). Rule 1 udf base L2 offset 96 match 0x0800 mask ffff interface 1. Rule 1 indicates rule 1. The UDF match starts at an offset of 12 bytes from the L2 header. Because the mask is ffff, it matches the 0x0800 field exactly, that is, etherType = 0x0800. This rule is bound to port 1, implementing programmable parsing and identification of IPv4 packets. The rule redirects packets with a destination IP address of 10.0.0.3 to port 3. This is translated into an ASIC-specific function as follows: Rule 2 udf base L2 offset 240 match 0a000003 mask ffffffff action redirect interface 3. Rule 2 indicates rule 2. The UDF match starts at an offset of 240 bits from the L2 header. It matches packets with a destination IP address of 0a000003 (i.e., 10.0.0.3), redirects them, and forwards them to port 3.

[0057] Step 4: To add new network functions, users simply write a new network program. The front-end compilation module, mid-end allocation module, and back-end compilation module then regenerate the rule expression for the new network function. The rule expression strategy module compares and analyzes the old and new rule expressions, combining the capabilities of heterogeneous devices to create a rule expression that can be loaded onto them, enabling incremental deployment of network functions.

[0058] The fourth step is achieved through the following sub-steps:

[0059] (4.1) If a new network function is to be added, the user only needs to write a new program, and then the front-end compilation module, the mid-end allocation module, and the back-end compilation module will generate the rule expression of the new network function.

[0060] (4.2) The rule expression strategy module compares and analyzes the new and old rule expressions. Two scenarios may arise: First, if the new and old network function rule expressions do not intersect, the rule expression strategy module will directly distribute the new network function rule expression to the corresponding heterogeneous device units, enabling incremental deployment of network functions. Second, if the new and old network function rule expressions intersect, the rule expression strategy module will compare and analyze the new and old rule expressions and merge or split the corresponding rule expressions to enable the coexistence of the new and old network functions, completing incremental network deployment.

[0061] Example 2

[0062] In a multimodal network, dynamic addition of network modalities is necessary. Initially, the network operates in the identity network modality, enabling unicast forwarding of identity packets. Later, based on service needs, unicast forwarding of IPv4 modalities needs to be added. The heterogeneous device-based incremental compilation method proposed in this paper enables dynamic and non-disruptive addition of network modalities.

[0063] Step 1: The user develops the identity network data plane functional program through P4. This primarily performs network addressing based on the identity, a globally unique identifier (GUID) (GUID = 101). The front-end compilation module performs basic syntax and semantic checks and converts it into IR.

[0064] Step 2: The mid-end allocation module will allocate IRs based on the resource constraints and specific functional constraints of the ASIC unit and FPGA unit. Because the identity network data plane functional program mainly completes the parsing of identity data packets, the redirection of identity data packets after GUID matching, etc., the mid-end allocation module will allocate IRs to the ASIC based on the principle of ASIC unit priority allocation while meeting the ASIC unit constraints.

[0065] Step 3: The ASIC's backend compilation module generates ASIC-specific rule expressions based on the ASIC's function mapping conversion rules and flow table information. Two-level UDF matching is implemented on the ASIC. First, the packet type is determined: rule 1 udf base L2 offset 96 match 0x27c0 mask ffff interface 2. Rule 1 represents rule 1. The UDF match starts at an offset of 96 bits from L2, that is, to the etherType field. Because the mask is ffff, it indicates an exact match of 0x27c0. This rule is bound to port 2, enabling programmable parsing and identification of identity packets. Next, specific packets are processed based on the JSON information. The identity packet with GUID = 101 is network-addressed, redirecting the packet to port 3. This is converted into the ASIC's specific function expression: rule 2 udf base L2 offset 178 match 0x00000065 mask ffffffff action redirect interface 3. Rule 2 2 indicates rule 2. The UDF match starts at an offset of 178 bits from L2 and exactly matches the 0x00000065 field, which is 101. Redirect interface 3 redirects the packet with GUID 101 to port 3.

[0066] Step 4: When a user needs to add a new network mode, namely, to add parsing and processing for IPv4 packets, they simply write the IPv4 data plane program in P4. The front-end compilation module then performs basic syntax and semantic checking and converts it into IR. When writing operations on IPv4 packets, they implement the operation of decrementing the IPv4 TTL field by 1. However, this operation falls outside the specific functional constraints of the ASIC, meaning that the ASIC cannot perform integer addition and subtraction. Therefore, the mid-end distribution module converts the IR into a rule expression for the FPGA unit. These two rule expressions target different subunits and do not intersect. Therefore, the newly added rule expression for IPv4 parsing and processing can be directly loaded into the FPGA unit, enabling incremental deployment of network functions.

[0067] Example 3

[0068] Corresponding to the aforementioned embodiment of the incremental compilation method based on heterogeneous devices, the present application also provides an embodiment of an incremental compilation system based on heterogeneous devices.

[0069] Referring to FIG2 , the system may include:

[0070] The front-end compilation module is used to perform basic syntax and semantic checks on network programs and convert them into intermediate representations;

[0071] A mid-end distribution module, configured to distribute the intermediate representation to different heterogeneous device units; the heterogeneous device units include ASIC units and FPGA units;

[0072] The backend compilation module is used to generate different rule expressions for heterogeneous devices based on function mapping conversion rules and flow table information, and then load the rule expressions onto the heterogeneous devices;

[0073] The rule expression strategy module is used to compare and analyze the new and old rule expressions to form a rule expression that can be loaded onto heterogeneous devices.

[0074] Regarding the system in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0075] Example 4

[0076] Corresponding to the aforementioned embodiment of the incremental compilation method based on heterogeneous devices, the embodiment of the present application further provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the incremental compilation method based on heterogeneous devices as described above. As shown in Figure 5, a hardware structure diagram of any device with data processing capabilities in which the incremental compilation method based on heterogeneous devices provided in the embodiment of the present application is located, in addition to the processor, memory, DMA controller, disk, and non-volatile memory shown in Figure 5, any device with data processing capabilities in which the system in the embodiment is located may also include other hardware according to the actual functions of the device with data processing capabilities, which will not be described in detail.

[0077] Example 5

[0078] Corresponding to the aforementioned embodiment of the incremental compilation method based on heterogeneous devices, an embodiment of the present invention further provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the incremental compilation method based on heterogeneous devices in the aforementioned embodiment is implemented.

[0079] The computer-readable storage medium may be an internal storage unit of any device with data processing capabilities described in any of the aforementioned embodiments, such as a hard disk or memory. The computer-readable storage medium may also be any device with data processing capabilities, such as a plug-in hard disk, a smart media card (SMC), an SD card, a flash card, etc. equipped on the device. Furthermore, the computer-readable storage medium may also include both an internal storage unit of any device with data processing capabilities and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by any device with data processing capabilities, and may also be used to temporarily store data that has been output or is to be output.

[0080] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0081] The above embodiments are intended only to illustrate the design concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. The scope of protection of the present invention is not limited to the above embodiments. Therefore, any equivalent changes or modifications made based on the principles and design concepts disclosed in the present invention are within the scope of protection of the present invention.

Claims

1. An incremental compilation method based on heterogeneous devices, characterized in that: The steps include: (1) Develop network programs through P4, perform basic syntax and semantic checks on network programs, and convert them into intermediate representations; (2) Modeling the functional constraints and resource constraints of heterogeneous devices; allocating intermediate representations to different heterogeneous device units according to the functional constraints and resource constraints of the heterogeneous devices; the heterogeneous device units include ASIC units and FPGA units; (3) Different heterogeneous device units generate different rule expressions for heterogeneous devices based on function mapping conversion rules and flow table information, and then load the rule expressions onto the heterogeneous devices; (4) Develop a network program that includes the new network function through P4, and regenerate the rule expression of the new network function through steps (1) to (3); compare and analyze the new and old rule expressions to form a rule expression that can be loaded onto heterogeneous devices, thereby completing the incremental deployment of the network function.

2. The incremental compilation method based on heterogeneous devices according to claim 1, characterized in that: In the step (2), the ASIC unit and the FPGA unit are connected via a built-in Serdes interface.

3. The incremental compilation method based on heterogeneous devices according to claim 1, characterized in that: The step (2) comprises the following sub-steps: (2.1) Modeling the functional constraints and resource constraints of heterogeneous devices, including modeling the functional constraints and resource constraints of ASIC units and FPGA units in heterogeneous devices; (2.2) According to the functional constraints and resource constraints of the heterogeneous devices, the intermediate representation is allocated to different units of the heterogeneous devices based on the ASIC unit priority allocation principle.

4. The incremental compilation method based on heterogeneous devices according to claim 3, characterized in that: In the sub-step (2.1), the functional constraints and resource constraints of the ASIC units in the heterogeneous devices are modeled as follows: To constrain the addition and deletion of ASIC units, T aw Indicates the length of the starting position of the increase operation offset, T dw Indicates the length of the starting position of the deletion operation offset, T AW Indicates the maximum offset that the ASIC unit supports for increase operations, T DW Indicates the maximum offset of the delete operation supported by the ASIC unit, T as Indicates the increased data segment length, T ds Indicates the length of the deleted data segment, T AS Indicates the maximum length of the data segment supported by the ASIC unit, T DS Indicates the maximum length of the data segment that the ASIC unit supports deleting, F AH Indicates adding a packet header field operation, F DH represents the operation of deleting the packet header field, m represents the functional unit placed on the heterogeneous device, and x m,A ∈{0,1} indicates whether m is placed on the ASIC unit; the function constraints of adding and deleting the ASIC unit are expressed as follows: Constrain the modification function of the ASIC unit, T cw Indicates the length of the starting position of the increase operation offset, T CW Indicates the maximum offset that the ASIC unit supports modification operations, T cs Indicates the length of the modified data segment, T CS Indicates the maximum length of the data segment that the ASIC unit supports modification, F CH Indicates adding a packet header field operation, then the modification function constraint of the ASIC unit is expressed as follows: Modeling the UDF resources of the ASIC unit, L K ∈[0,14,34] represents the offset length occupied by the starting position of different matching offsets; S L Indicates the length of the matching offset, M L Indicates the length of the match, I LA Indicates the maximum value of the range of packet header fields that the ASIC unit supports matching. p,A ∈{0,1} indicates whether p is placed on the ASIC unit, N MA represents the maximum number of matches that the ASIC unit can support, Θ(x) is the indicator function, M A Indicates the maximum match length that the ASIC unit can support, M m Indicates the length that the functional unit m actually needs to match, F ET represents the exact match table, F LTT represents a ternary matching table; then the matching resource constraint of the ASIC unit is expressed as follows:

5. The incremental compilation method based on heterogeneous devices according to claim 3, characterized in that: In the sub-step (2.1), the resource constraints and functional constraints of the FPGA unit in the heterogeneous device are modeled as follows: Constraint modeling is performed on the functions of the FPGA unit, and constraints are imposed on the FPGA unit's functions of adding, modifying, and deleting data packet header fields; IL Indicates the increased data segment length, F CL Indicates the length of the modified data segment, F DL Indicates the length of the deleted data segment, G IL Indicates the maximum length of the data segment supported by the FPGA unit, G CL Indicates the maximum length of the data segment that the FPGA unit supports modification, G DL Indicates the maximum length of the data segment that the FPGA unit supports deleting, F headerG Indicates the actions supported by the FPGA unit; the functional constraints of the FPGA unit are expressed as follows: Constraint modeling for parsing and matching resources of FPGA units, L parser Indicates the maximum jump length that the FPGA unit can support, S h represents the set of headers deployed in the FPGA unit, V(h) represents the validity of the header field h, V(h) = 1 means that the header field is valid, otherwise it is invalid; then the constraints on the FPGA unit header parsing are expressed as follows: Constraint modeling of matching resources of FPGA units, K G Indicates the maximum length of the match supported by the FPGA unit, K m Indicates the actual matching length of functional unit m, N MG Indicates the maximum number of matches that the FPGA can support, a p,G ∈{0,1} indicates whether p should be placed on the FPGA unit, x m,G ∈{0,1} indicates whether m is placed on the FPGA unit; M G Indicates placement The set of all functional units on the FPGA unit; then the constraints on the matching resources of the FPGA unit are expressed as follows:

6. The incremental compilation method based on heterogeneous devices according to claim 1, characterized in that: In the step (3), the function mapping conversion rule is specifically: converting the intermediate representations assigned to different units of the heterogeneous device into json format information in combination with the corresponding flow table, and then converting it into the rule expression of the heterogeneous device.

7. The incremental compilation method based on heterogeneous devices according to claim 1, characterized in that: The step (4) comprises the following sub-steps: (4.1) Develop a network program containing new network functions through P4 and regenerate the rule expression of the new network functions; (4.2) Compare and analyze the new and old rule expressions; if the new and old network function rule expressions do not intersect, the new network function rule expression is directly sent to the corresponding heterogeneous device unit to form a rule expression that can be loaded on the heterogeneous device, thereby realizing incremental deployment of network functions; If the rule expressions of the new and old network functions intersect, the new and old rule expressions are compared and analyzed, and the corresponding rule expressions are merged or split to form rule expressions that can be loaded onto heterogeneous devices to complete the incremental deployment of the network.

8. An incremental compilation system based on heterogeneous devices, characterized in that: include: The front-end compilation module is used to perform basic syntax and semantic checks on network programs and convert them into intermediate representations; A mid-end distribution module, used to distribute the intermediate representation to different heterogeneous device units; the heterogeneous device units include ASIC units and FPGA units; The backend compilation module is used to generate different rule expressions for heterogeneous devices based on the function mapping conversion rules and flow table information, and then load the rule expressions onto the heterogeneous devices; The rule expression strategy module is used to compare and analyze the new and old rule expressions to form a rule expression that can be loaded onto heterogeneous devices.

9. An electronic device, comprising a memory and a processor, characterized in that: The memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the incremental compilation method based on heterogeneous devices as described in any one of claims 1-7 above.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the incremental compilation method based on heterogeneous devices is implemented as described in any one of claims 1 to 7.

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