Prefetching parameter configuration and cache prefetching method, host, and processor

Abstract

Embodiments of the present disclosure provide a prefetching parameter configuration and cache prefetching method, a host, and a processor. In the embodiments of the present disclosure, a physical processor can perform a hardware prefetching operation during operation of a virtual machine. Furthermore, a hypervisor applies for the permission to access a prefetching register from a firmware program of the prefetch register, when the permission to access the prefetch register is successfully applied for, senses an operation of configuring a prefetching strategy parameter by the virtual machine, configures a prefetch register in the physical processor to which the virtual machine is scheduled with the prefetching strategy parameter in place of the virtual machine, and transparently transmits the configuration capacity of the prefetch register to the virtual machine by means of underlying virtualization technology, so that on the basis of the scheduling condition of the virtual machine, prefetching strategies can be flexibly and dynamically configured to different virtual machines, and the problem that in the prior art, multiple application performance cannot be balanced due to prefetching strategies being unable to be flexibly and dynamically configured is solved.

Description

Prefetch parameter configuration and cache prefetch method, physical machine and processor

[0001] Cross-reference

[0002] This disclosure claims priority to Chinese patent application number 2023112267050, filed with the Patent Office of China on September 21, 2023, entitled “Prefetch parameter configuration and cache prefetch method, physical machine and processor,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the field of cloud storage technology, and in particular to a prefetch parameter configuration and cache prefetch method, a physical machine, and a processor. Background Art

[0004] In modern processor designs, memory systems with caches are usually introduced, and a hardware prefetch mechanism is supported. That is, through the hardware prefetcher inside the central processing unit (CPU), instructions or data are read from a slower storage medium (e.g., memory) to a faster storage medium (e.g., cache) in advance, thereby reducing the time the CPU waits for instructions or data to be loaded, thereby improving CPU execution performance.

[0005] In some processor designs, multiple prefetchers may be included. Among them, the adjustable parameters involved in the prefetching process of each prefetcher are also diverse. Which hardware prefetcher is used and which parameter combinations are used by the hardware prefetcher during the prefetching process will form different prefetching strategies. The memory access mode and read and write rules of the application are different. Selecting different prefetching strategies will have different performance impacts on the application. In the prior art, when the physical server is powered on, the firmware (BIOS) generally provides an option menu for the CPU hardware prefetching strategy. The user can select a fixed prefetching strategy based on the characteristics of the application.

[0006] However, when running multiple applications on a physical server, the existing approach to selecting a prefetching strategy can compromise performance for all applications. This is especially true in cloud computing scenarios, where a single physical server often hosts multiple virtual machines belonging to different tenants, each running a different set of applications. Therefore, a new prefetching strategy configuration scheme is urgently needed that can balance the performance benefits of various applications.

[0007] Summary of the Invention

[0008] Various aspects of the present disclosure provide a prefetch parameter configuration and cache prefetch method, a physical machine, and a processor for flexibly and dynamically configuring a prefetch strategy for a CPU, so that the prefetch strategy can take into account the performance advantages of various applications.

[0009] An embodiment of the present disclosure provides a physical machine, wherein the hardware resources of the physical machine include at least one physical processor, and the physical processor includes a hardware prefetcher and a prefetch register for performing prefetch control on the hardware prefetcher; the software resources of the physical machine include at least a firmware program for performing read and write control on the prefetch register and a virtualization manager for creating and managing virtualization instances; the virtualization manager is further configured to apply to the firmware program for access rights to the prefetch register, and upon successfully applying for access rights to the prefetch register, respond to the operation of the virtualization instance to configure target prefetch policy parameters for the prefetch register, and configure the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled.

[0010] An embodiment of the present disclosure provides a prefetch policy configuration method, which is applied to a virtualization manager on a physical machine for creating and managing virtualization instances. At least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for performing prefetch control on the hardware prefetcher. The method comprises: applying for access rights to the prefetch register from a firmware program in the physical machine for performing read and write control on the prefetch register; and upon successfully applying for access rights to the prefetch register, in response to an operation by the virtualization instance to configure target prefetch policy parameters for the prefetch register, configuring the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled.

[0011] An embodiment of the present disclosure provides another prefetch policy configuration method, which is applied to a firmware program in a physical machine for reading and writing prefetch registers. The physical machine also includes a virtualization manager for creating and managing virtualization instances. The method includes: when the virtualization manager applies for access rights to the prefetch registers, configuring an authorization register in at least one physical processor to a preset value representing authorization to open access rights to the prefetch registers to the virtualization manager; and returning authorization success structure information to the virtualization manager.

[0012] An embodiment of the present disclosure provides another prefetch policy configuration method, which is applied to a virtualization instance created by a virtualization manager in a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher; the method includes: in response to a prefetch policy configuration operation, obtaining target prefetch policy parameters configured for the prefetch register; based on the ability of the virtualization manager to indicate that the virtualization instance has the ability to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register, trapping to the virtualization manager so that the virtualization manager can intercept the target prefetch policy parameters and configure them to the prefetch register in the target physical processor to which the virtualization instance is scheduled.

[0013] An embodiment of the present disclosure provides a cache prefetching method, which is applied to a target physical processor in a physical machine. The target physical processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher. The target prefetch policy parameters in the prefetch register are configured according to the above-mentioned prefetch policy configuration method; the method includes: reading the target prefetch policy parameters from the prefetch register; and performing data and / or instruction prefetch operations based on the target prefetch policy parameters during the operation of the scheduled virtualization instance.

[0014] An embodiment of the present disclosure also provides a processor, which is responsible for running a virtualized instance. The processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher. The target prefetch policy parameters in the prefetch register are configured according to the steps in the prefetch policy configuration method described above; the processor is used to execute a computer program to implement the steps in the cache prefetch method.

[0015] The present disclosure also provides an electronic device. The electronic device includes: a memory and a processor, wherein:

[0016] The memory is used to store programs;

[0017] The processor is coupled to the memory and is configured to execute the program stored in the memory to implement the steps in any one of the above methods.

[0018] An embodiment of the present disclosure further provides a computer program product, comprising a computer program, which implements the steps in any one of the above methods when executed by a processor.

[0019] An embodiment of the present disclosure further provides a computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any one of the above methods are implemented.

[0020] The embodiment of the present disclosure further provides a computer program, which, when executed by a processor, implements the steps in any of the above methods.

[0021] An embodiment of the present disclosure further provides a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to implement the steps in any of the above methods.

[0022] In an embodiment of the present disclosure, a virtualization manager for creating and managing virtualized instances is deployed on a physical machine. The virtualized instances are scheduled to run on the physical processors of the physical machine. The physical processors include a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher, and are capable of performing hardware prefetching operations during the operation of the virtualized instances. Furthermore, in order to achieve dynamic configuration of the hardware prefetching strategy, the virtualization manager applies to the firmware program of the prefetch register for access rights to the prefetch registers. When the access rights to the prefetch registers are successfully applied for, the virtualization manager senses the operation of configuring the prefetching strategy parameters of the virtualized instance and configures the prefetching strategy parameters to the prefetch registers in the physical processor to which the virtualized instance is scheduled on behalf of the virtualized instance. The configuration capability of the prefetch registers is then transparently transmitted to the virtualized instance through the underlying virtualization technology, so that the prefetching strategy can be flexibly and dynamically configured for different virtualized instances according to the scheduling of the virtualized instances, thereby solving the problem in the prior art that the performance of multiple applications cannot be taken into account due to the inability to flexibly and dynamically configure the prefetching strategy. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0024] FIG1a is a schematic diagram of an instruction pipeline of a processor core provided by an exemplary embodiment of the present disclosure;

[0025] FIG1b is a schematic diagram of a register and its prefetch parameters provided by an exemplary embodiment of the present disclosure;

[0026] FIG2 is a system framework diagram of a physical machine's hardware and software structure provided by an exemplary embodiment of the present disclosure;

[0027] FIG3 is a timing diagram of a prefetch strategy configuration method provided by an exemplary embodiment of the present disclosure;

[0028] FIG4 is a flow chart of a prefetching strategy configuration method provided by an exemplary embodiment of the present disclosure;

[0029] FIG5 is a flow chart of another prefetching strategy configuration method provided by an exemplary embodiment of the present disclosure;

[0030] FIG6 is a flow chart of another prefetching strategy configuration method provided by an exemplary embodiment of the present disclosure;

[0031] FIG7 is a schematic flow chart of a cache prefetching method provided by an exemplary embodiment of the present disclosure;

[0032] FIG8 is a schematic structural diagram of a prefetching strategy configuration device provided by an exemplary embodiment of the present disclosure;

[0033] FIG9 is a schematic structural diagram of another prefetch strategy configuration device provided by an exemplary embodiment of the present disclosure;

[0034] FIG10 is a schematic structural diagram of another prefetch strategy configuration device provided by an exemplary embodiment of the present disclosure;

[0035] FIG11 is a schematic structural diagram of a cache prefetching device provided by an exemplary embodiment of the present disclosure;

[0036] FIG12 is a schematic structural diagram of a processor provided by an exemplary embodiment of the present disclosure;

[0037] FIG13 is a schematic structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions, and advantages of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the specific embodiments of the present disclosure and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0039] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0040] In cloud computing scenarios, users can purchase or deploy virtualized instances, such as virtual machines (VMs) or containers. Each virtualized instance has an independent physical operating environment and independent resources, such as independent computing resources, storage resources, and network resources. In this embodiment, the computing resources of the virtualized instance include one or more physical CPU resources. This provides the conditions for configuring prefetch policies and controlling cache prefetching from the perspective of the virtualized instance. Furthermore, considering that virtualized instances are typically scheduled according to the cluster dimension in cloud computing scenarios, cache prefetching control can be personalized or targeted for the physical CPU from the perspective of the virtualized instance. This allows the physical CPU to perform prefetch operations more reasonably during the operation of the virtualized instance, pre-reading data and / or instructions from the memory into the cache, or from the third-level cache to the second-level cache, or from the second-level cache to the first-level cache, thereby solving various memory problems encountered during the operation of the virtualized instance, such as low cache hit rate, insufficient memory bandwidth resources, and memory contention.

[0041] It should be noted that in the embodiments of the present disclosure, the correspondence between virtualized instances and physical CPUs is not limited. The same physical CPU can be assigned to a virtualized instance or dynamically assigned to different virtualized instances. Both situations are applicable to the embodiments of the present disclosure. In addition, in the embodiments of the present disclosure, one or more applications can be deployed in the virtualized instance. When performing personalized or targeted cache prefetch control on the physical CPU from the perspective of the virtualized instance, the physical CPU can be dynamically prefetched and cached according to the needs of each application in the virtualized instance.

[0042] In the embodiment of the present disclosure, the cache system of the physical CPU is a multi-level system divided according to tasks. In addition, the implementation structure of the kernel cache system of processors of different architectures, different models, and different manufacturers will be different, which is not limited in the embodiment of the present disclosure. Processors of various architectures, various models, and various scenarios are applicable to the embodiment of the present disclosure as long as they support hardware prefetch solutions and need to perform prefetch control by configuring the values ​​of prefetch registers. A processor core is shown below as an example, as shown in Figure 1a. The instruction pipeline of the processor core includes but is not limited to the following stages: fetch and decode (Fetch & Decode) stage, execution (Execution) stage, and commit and exit (Commit & Retire) stage.

[0043] The Fetch & Decode stage corresponds to the In-Order Front End (IFO) module. The IFO module 100 includes, but is not limited to, the following hardware units: a Branch Prediction Unit (BPU) 1001, a Decode, Rename & Dispatch (Decode) unit 1002, a Level 1 Instruction-Cache (L1 I-Cache) unit 1003, and a Level 1 Instruction Translation Lookaside Buffer (L1-I-TLB) unit 1004. The L1 I-Cache is used to store instructions, while the L1 D-Cache is used to store L1 cache data. The L1-I-TLB is used to cache page table entries and determine the physical addresses of L1 instructions.

[0044] The execution stage corresponds to the out-of-order back end (OOB) processing module 101, which includes but is not limited to the following hardware units: issue queue 1011, execution units 1012, load store unit 1013, level 1 data translation lookaside buffer (L1 Data-TLB, abbreviated as L1 D-TLB) unit 1014, level 2 translation lookaside buffer (L2 TLB) unit 1015, and level 1 data cache (Level 1 Data-Cache, abbreviated as L1 D-Cache) unit 1016. The L2 TLB is used to cache page table entries and determine the physical address of the L1 cache.

[0045] The Commit & Retire stage corresponds to an In-Order Instruction Retire module, and the In-Order Instruction Retire module 102 includes but is not limited to the following hardware units: a Commit & Retire unit 1021 .

[0046] The Fetch & Decode and Execution stages also correspond to the Core-Clure Interface module, which includes an L2 Cache unit 1031. Figure 1a does not show the processor's Last Level Cache (LLC), also known as the L3 cache. For some processors, the LLC is optional.

[0047] The branch prediction unit 1001 is used to predict the address of the next instruction, for example, predicting which address the CPU should prefetch instructions from. The decode, rename, and dispatch unit is primarily responsible for retrieving instructions from the L1I-Cache based on the address predicted by the branch prediction unit, identifying the instruction type, and renaming the instructions, writing the renamed instructions into the issue queue in sequence. The execution unit is responsible for executing instructions in the issue queue, and the load and store unit provides the data required by the instructions in the issue queue. The commit and retire unit is responsible for committing the execution results and retiring.

[0048] In order to improve the performance of the application, cache prefetch operations are involved in the above process. As shown in Figure 1a, cache prefetching can be summarized into the following two situations: one is to read data from the low-end storage in advance and write it to the high-end cache, referred to as cache read data, which mainly includes from L2 Cache -> L1 I-Cache / L1 D-Cache, indicating that instructions are read from L2 Cache to L1 I-Cache or data are read from L2 Cache to L1 D-Cache, and from L2 TLB -> L1 I-TLB / L1 D-TLB, indicating that instruction mapping information is read from L2 TLB to L1 I-TLB or data mapping information is read from L2 TLB to L1 D-TLB; the other is to write dirty pages in high-end storage back to low-end storage in advance, referred to as dirty page writeback, which mainly includes from L1 D-Cache -> L2 Cache, indicating that dirty pages in L1 D-Cache are pre-written back to L2 Cache, and from L1 I-TLB / L1 D-TLB -> L2 TLB means pre-writing instruction mapping information in the L1 I-TLB to the L2 TLB, or pre-writing data mapping information in the L1 D-TLB to the L2 TLB. In the embodiments of this disclosure, the focus is on the case of caching read data, that is, pre-reading data from the low-end storage and writing it to the high-end cache.

[0049] In actual applications, there are two prefetching methods: software and hardware. Software prefetching can insert prefetch instructions into the program, use prefetch instructions to perform prefetching during coding, or use optimized compilation options during compilation, and use prefetch instructions to improve the execution efficiency of the program. Hardware prefetching is implemented by a dedicated hardware prefetcher inside the physical CPU. The hardware prefetcher is mainly used to prefetch data and / or instructions, that is, to put the data that may be used in the relevant cache in advance to wait for use in the relevant cache. In the embodiment of the present disclosure, the focus is on the hardware prefetching method. The physical CPU supports multiple hardware prefetching algorithms, and different hardware prefetching algorithms are implemented by different hardware prefetchers. Which hardware prefetching algorithm (or hardware prefetcher) the physical CPU uses and how to use the hardware prefetching algorithm (or hardware prefetcher) to prefetch data and / or instructions can be controlled by a prefetch register. Based on this, in this embodiment, the physical CPU also includes: multiple prefetch registers for cache prefetch control of the physical CPU. The multiple prefetch registers in this embodiment refer to registers used to control cache prefetching of the physical CPU. It should be noted that the physical CPU may also include other registers, such as authorization registers, etc. Each prefetch register is used to control a prefetch parameter, and different prefetch registers represent different prefetch parameters. That is to say, each prefetch register corresponds to a prefetch parameter, and a prefetch parameter has at least two values. For example, if the prefetch parameter corresponding to the prefetch register is represented by 1 bit, its values ​​are: 0 and 1; if the prefetch parameter corresponding to the prefetch register is represented by 2 bits, its values ​​are four, namely: 00, 01, 10 and 11. For the same prefetch register, different values ​​are mutually exclusive, which means that at the same time, the value of the prefetch register can only be one of them. The value combination between multiple prefetch registers forms a plurality of prefetch parameter combinations, and each prefetch parameter combination represents a prefetch strategy. For example, the prefetch parameter combination may include but is not limited to: which prefetch algorithm the physical CPU uses, which data to prefetch, when to start prefetching, where the prefetched data is stored, etc. This information can be given by the values ​​of different prefetch registers.

[0050] Optionally, the multiple prefetch registers included in the physical CPU can be classified according to the prefetch parameters they represent. Specifically, the multiple prefetch registers can be divided into two types: one is a prefetch register representing a prefetch algorithm selection parameter, which is mainly used to select whether to use a certain prefetch algorithm (i.e., a hardware prefetcher). It is noted that the prefetch algorithm mentioned in the embodiments of the present disclosure mainly refers to a hardware prefetch algorithm, i.e., a prefetch algorithm implemented by a hardware prefetcher; the other is a prefetch register representing a prefetch operation execution control parameter, which is mainly used to control how the selected hardware prefetcher performs the prefetch process. There are multiple registers of this type, which are used to provide different prefetch operation execution control parameters for the hardware prefetcher, for example, determining which block of data the hardware prefetcher prefetches, when to start prefetching data, the amount of data to be prefetched, the prefetch location, and the location where the prefetched data is stored. Among them, the number of prefetch registers representing the prefetch algorithm selection parameter can be 1, and the number of prefetch registers representing the prefetch operation execution control parameter can be multiple, for example, 2, 3, or 10. Accordingly, a prefetch parameter combination, that is, a value combination of multiple prefetch registers, includes a set of values ​​corresponding to the prefetch algorithm selection parameters and the prefetch operation execution control parameters.

[0051] For example, FIG1b schematically shows the situation of some prefetch registers included in the physical CPU. The CMC_MIN_WAY register belongs to the prefetch register representing the prefetch algorithm selection parameter, indicating whether the Correlated Miss Caching (CMC) algorithm is selected. The CMC algorithm is a hardware prefetch algorithm and a type of temporal prefetcher. It uses part of the L2 cache space to store historical miss information and uses this miss information as metadata to prefetch data. If data is prefetched from the memory to the L2 cache, how many bits in the L2 cache need to be reserved for data and how many bits for instructions are controlled by the L2_DATA_PART register and the L2_INST_PART register respectively. The L2 cache data part (L2_DATA_PART) register and the L2 cache instruction part (L2_INST_PART) register are prefetch registers representing the execution control parameters of the prefetch operation. The L2_DATA_PART register The ART register and the L2_INST_PART register can have various values. In Figure 1b, assume that the parameters of the L2_DATA_PART and L2_INST_PART registers are both represented by 3 bits, each with eight possible values. If the L2_DATA_PART register value is 000, it means that 0 bits are reserved for data in the L2 cache, which is the reset value. If the L2_DATA_PART register value is 001, it means that 1 bit is reserved for data in the L2 cache. If the L2_INST_PART register value is 111, it means that 7 bits are reserved for instructions in the L2 cache. If the L2_INST_PART register value is 101, it means that 5 bits are reserved for instructions in the L2 cache. Different combinations of L2_DATA_PART and L2_INST_PART register values ​​result in different prefetch strategies, which in turn lead to different application performance during execution.

[0052] In addition, different applications have different memory access patterns and read-write rules, so different prefetching strategies need to be selected to ensure that different prefetching strategies can bring performance advantages to different applications. For example, in cloud computing scenarios, multiple virtualized instances of different tenants are often running on the same physical machine. The applications running in these virtualized instances are also different, and the prefetching strategies required by different applications are not the same. For example, in a cloud server product scenario, the product uses an ARM processor with an added hardware prefetcher, and database applications such as the Relational Database Service (RDS) are deployed on the cloud server product. Other applications are also deployed. When using a prefetching strategy represented by a specific prefetching parameter combination, it can bring 15% or even higher performance improvement to database applications such as RDS, but it does not produce performance improvement for other applications and may even bring negative performance benefits. It is further explained that different applications require different prefetching strategies, and the same prefetching strategy cannot bring performance improvements to all applications. Therefore, if the prefetching strategies can be flexibly and dynamically configured for different virtualization instances according to the scheduling of the virtualization instances, so that different virtualization instances use different prefetching strategies, and then these prefetching strategies can bring performance advantages to different application scenarios, it becomes a technical problem that needs to be solved by the embodiments of the present disclosure.

[0053] In view of the above, in an embodiment of the present disclosure, a prefetch policy configuration scheme is provided for cloud computing scenarios, which can flexibly and dynamically configure prefetch policies for physical CPUs according to the scheduling of virtualized instances. That is, when the physical CPU runs virtualized instance A, a prefetch policy adapted to virtualized instance A can be configured for the physical CPU; when the physical CPU runs virtualized instance B, a prefetch policy adapted to virtualized instance B can be configured for the physical CPU. Specifically, in a cloud computing scenario, a virtualization manager for creating and managing virtualized instances is deployed on the physical machine, and the virtualized instances are scheduled to run on the physical processors of the physical machine. In an embodiment of the present disclosure, the physical processor includes a hardware prefetcher and a prefetch register for prefetching the hardware prefetcher. Under the control of the prefetch register, the prefetcher can perform hardware prefetch operations during the operation of the virtualized instance. The hardware prefetch operation can reduce the time the physical processor waits for reading data or instructions, which is conducive to improving the execution efficiency of the physical processor and thus improving the running performance of the virtualized instance. Furthermore, in order to achieve dynamic configuration of hardware prefetch policies, in the embodiments of the present disclosure, by expanding the functions of the virtualization manager, the virtualization manager applies to the firmware program of the prefetch register for access rights to the prefetch register, and when the access rights to the prefetch register are successfully applied for, the virtualization manager senses the operation of configuring the prefetch policy parameters of the virtualization instance and configures the prefetch policy parameters to the prefetch registers in the physical processor to which the virtualization instance is scheduled on behalf of the virtualization instance, and then transmits the configuration capability of the prefetch registers to the virtualization instance through the underlying virtualization technology, so that the prefetch policies can be flexibly and dynamically configured for different virtualization instances according to the scheduling of the virtualization instance, solving the problem in the prior art that the performance of multiple applications cannot be taken into account due to the inability to flexibly and dynamically configure the prefetch policies. At the same time, in the embodiments of the present disclosure, the virtualization manager configures the prefetch policies for the prefetch registers on behalf of the virtualization instance, which can ensure the security of the physical processor.

[0054] The technical solutions provided by various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0055] Figure 2 is a diagram of the hardware and software system architecture of a physical machine provided in an exemplary embodiment of the present disclosure. As shown in Figure 2, physical machine 200 in this embodiment includes hardware resources and software resources. Hardware resources refer to the visible and tangible physical devices within the physical machine; software resources refer to programs organized to facilitate and improve the efficiency of the physical machine, as well as related documentation for development, use, and maintenance.

[0056] In the embodiment of the present disclosure, the hardware resources of the physical machine include at least at least one physical processor 201, memory, hard disk, network card and some peripheral devices (display) and so on. The hardware resources focused on in the embodiment of the present disclosure are physical processors, so the physical processors are highlighted in FIG2 , and multiple physical processors are shown in FIG2 . As shown in FIG2 , the physical processor of this embodiment includes at least one or more hardware prefetchers (Cache Prefetch) 2011 and multiple prefetch registers (Prefetch register) 2012 for performing prefetch control on the hardware prefetchers. Among them, the hardware prefetcher is used to perform prefetch operations under the control of the prefetch register, and the prefetch register is used to store prefetch parameters. Furthermore, the physical processor in this embodiment can also be the various components shown in FIG1a , which will not be repeated here.

[0057] In the embodiment of the present disclosure, the software resources of the physical machine include at least a firmware program (Bios) for reading and writing prefetch registers and a virtualization manager for creating and managing virtualization instances; further, as shown in FIG2 , the software resources of the physical machine also include various virtualization instances created by the virtualization manager, and each virtualization instance includes its own operating system (Operating System, referred to as OS). Relatively speaking, the physical machine acts as a host (Host), and its operating system can be called a host operating system (Host OS), and the virtualization instance can act as a client, and its operating system can also be called a guest operating system (Guest OS). In FIG2 , the virtualization instance is implemented as a VM as an example. In the embodiment of the present disclosure, the implementation method of the virtualization manager is not limited. For example, it can be a virtual machine monitor (VMM), or it can also be called a hypervisor. Among them, the Host OS also belongs to the software resources of the physical machine, which is illustrated in FIG2 . It should be noted that the virtualization manager is a functional module in the Host OS. In Figure 2, each software resource is hierarchically illustrated based on its privilege level, rather than based on the dimension of inclusion or ownership between software resources.

[0058] In the disclosed embodiments, the software resources of a physical machine have privilege levels. In some processor architectures, these privilege levels are also referred to as exception levels (EL). Different software resources may have different exception levels, and multiple software resources may exist under the same exception level. Privilege levels or exception levels provide a logical separation of execution permissions between software resources. Generally, the higher the privilege level or exception level, the greater the execution permission. In this embodiment, taking the processor architecture providing four exception levels as an example, it is assumed that the four exception levels are EL0, EL1, EL2, and EL3. EL0 is the level corresponding to user applications, EL1 is the level corresponding to the operating system kernel, EL2 is the level corresponding to the virtualization manager, and EL3 is the level corresponding to some firmware programs. The processor architecture providing four exception levels may be, but is not limited to, the ARM architecture. The larger the exception level number, the higher the exception level, and the greater the corresponding execution permission. In this embodiment, as shown in FIG2 , the virtual virtualization manager is at EL2, the firmware program that pre-fetches registers is at EL3, and the client operating system corresponding to the virtualized instance created by the virtualization manager is at EL1. In Figure 2, the exception level of the host operating system is not limited. In different processor architectures, the exception level of the host operating system may be different. In some processor architectures, the host operating system is in EL2, and in some processor architectures, the host operating system may be in EL1.

[0059] In the processor architecture of this embodiment, for security reasons, the EL required for reading and writing prefetch registers is higher, allowing firmware programs at EL3 to read, write, or modify them, while the virtualization manager at EL2 and the virtualization instance at EL1 do not have access to read and write prefetch registers, which can protect the security of the processor. However, in the disclosed embodiment, it is desired to flexibly and dynamically configure prefetch policies for physical processors based on the scheduling of virtualization instances. This requires the ability to configure prefetch policies for prefetch registers from the perspective of virtualization instances, that is, the virtualization instance must be able to read and write prefetch registers, which is contrary to the security of the processor architecture. To this end, in the embodiments of the present disclosure, the access of the virtualization instance to the prefetch register is trapped to the virtualization manager, and the virtualization manager configures the prefetch policy for the prefetch register on behalf of the virtualization instance. While meeting the processor security requirements, the configuration capability of the prefetch register is transparently transmitted to the virtualization instance through the underlying virtualization technology, so that the prefetch policy can be flexibly and dynamically configured for different virtualization instances according to the scheduling status of the virtualization instance, solving the problem in the prior art that the performance of multiple applications cannot be taken into account due to the inability to flexibly and dynamically configure the prefetch policy.

[0060] However, in the current processor architecture, the virtualization manager does not have access to the prefetch registers. In view of this, in the embodiments of the present disclosure, the functions of the prefetch register firmware program, the virtualization manager and the virtualization instance are improved, and with the cooperation of the three, the virtualization manager has access to the prefetch registers and can pass the configuration capabilities of the prefetch registers to the virtualization instance, thereby being able to flexibly and dynamically configure prefetch strategies for different virtualization instances according to the scheduling conditions of the virtualization instance.

[0061] Specifically, on the one hand, it is necessary to re-implement the firmware program of the prefetch register and add an authorization function in the firmware program so that the firmware program can authorize the virtualization manager to have access to the prefetch register; on the other hand, the function of the virtualization manager is expanded so that it has the ability to apply for access to the prefetch register from the firmware program of the prefetch register, and has the ability to perceive the operation of the virtualization instance accessing the prefetch register to configure the target prefetch policy parameters and to configure the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled on behalf of the virtualization instance.

[0062] Based on the above, in addition to creating and managing virtualized instances, the virtualization manager in this embodiment is also used to apply to the firmware program for access rights to prefetch registers. If the application for access rights to prefetch registers is successful, in response to the virtualized instance configuring the target prefetch policy parameters for the prefetch registers, the target prefetch policy parameters are configured for the prefetch registers in the target physical processor to which the virtualized instance is scheduled. In the disclosed embodiment, the scheduling policy for scheduling virtualized instances is not limited, but virtualized instances are dynamically scheduled, and different physical processors may be assigned to virtualized instances in different scheduling processes, or the same physical processor may be assigned to them. This is not limited. For ease of description and distinction, the physical processor to which the virtualized instance is scheduled after configuring the target prefetch policy parameters is referred to as the target physical processor. The target prefetch policy parameters are the prefetch policy parameters that the virtualized instance needs to configure, and different virtualized instances can configure different prefetch policy parameters for the physical processor to which it is scheduled. In addition, in addition to configuring the prefetch configuration policy for the physical processor based on the scheduling situation of the virtualized instance, the physical processor also has a default prefetch policy parameter. It is to be noted that the prefetching strategy parameters of this embodiment are the “prefetching parameter combination” described above, which will not be described in detail here. For related explanations, please refer to the above text.

[0063] In an embodiment of the present disclosure, to implement dynamic configuration of hardware prefetch policies, a virtualization manager applies to a firmware program for access to the prefetch registers. Upon successfully obtaining access to the prefetch registers, the virtualization manager senses the operation of configuring prefetch policy parameters by the virtualization instance and, on behalf of the virtualization instance, configures the prefetch policy parameters to the prefetch registers in the physical processor to which the virtualization instance is scheduled. This is equivalent to transparently transmitting the prefetch register configuration capability to the virtualization instance through the underlying virtualization technology, enabling flexible and dynamic configuration of prefetch policies for different virtualization instances based on the scheduling of the virtualization instances. When a physical processor runs virtualization instance A, a prefetch policy adapted to virtualization instance A is configured for the physical processor, allowing the prefetch policy to improve the performance of virtualization instance A. When a physical processor runs virtualization instance B, a prefetch policy adapted to virtualization instance B is configured for the physical processor, allowing the prefetch policy to improve the performance of virtualization instance B. This solves the problem in the prior art of being unable to balance the performance of multiple applications due to the inability to flexibly and dynamically configure prefetch policies.

[0064] In the embodiment of the present disclosure, as shown in FIG2 , each physical processor also includes an authorization register (Authorization Register) 2013. The authorization register is used to indicate whether to grant access to the prefetch register to the virtualization manager through a preset value. Based on this, when the virtualization manager requests access to the prefetch register from the firmware program, the firmware program can configure the authorization register in each physical processor to a preset value indicating authorization, thereby granting access to the prefetch register to the virtualization manager. The implementation of the authorization register may vary depending on the processor architecture, and this embodiment does not limit this. For example, taking the authorization register as 1 bit in length as an example, and assuming that the preset value indicating authorization is "1", when the virtualization manager requests access to the prefetch register from the firmware program, if the virtualization manager can be granted access, the firmware program can configure the authorization register in each physical processor to a value of "1", indicating that access to the prefetch register is granted to the virtualization manager, i.e., the virtualization manager has access to the prefetch registers in each physical processor. Of course, if the preset value indicating authorization is "1", a value of "0" in the authorization register indicates that access to the prefetch register is not granted to the virtualization manager.

[0065] In the embodiment of the present disclosure, the virtualization manager can apply to the firmware program for access rights to the prefetch registers during the initialization process. The virtualization manager will perform the initialization process when it is loaded. The situations in which the virtualization manager is loaded include but are not limited to the following two: one is when the physical machine is turned on, and the other is when the old version of the virtualization manager is replaced with the new version online. In the embodiment of the present disclosure, the implementation method of the virtualization manager applying to the firmware program for access rights to the prefetch registers during the initialization process is not limited. The following examples are provided for illustration:

[0066] In an optional embodiment, the processor architecture of the disclosed embodiment provides communication instructions for software resources at EL2 to interact with software resources at EL3. The communication instructions may include parameters, with different parameters representing different communication purposes between software resources at EL2 and software resources at EL3. Based on this, developers can pre-agreed on parameters, referred to as agreed parameters, for requesting access rights to prefetch registers from the firmware program on behalf of the virtualization manager. This allows the virtualization manager to use existing communication instructions to request access rights to prefetch registers from the firmware program. Specifically, one implementation of the virtualization manager requesting access rights to prefetch registers from the firmware program includes: during initialization, the virtualization manager sends a communication instruction to the firmware program, the communication instruction including agreed parameters indicating a request for access rights to prefetch registers; the firmware program, in response, receives the communication instruction sent by the virtualization manager and, based on the agreed parameters included in the communication instruction, configures authorization registers in each physical processor to predetermined values ​​indicating authorization, thereby granting access rights to the prefetch registers to the virtualization manager, and returns authorization success information to the virtualization manager; and the virtualization manager receives authorization success information returned by the firmware program, indicating a successful request for access rights to the prefetch registers.

[0067] For example, in an Advanced RISC Machines (ARM) processor architecture, the aforementioned communication instruction can be implemented as a Secure Monitor Call (SMC) instruction. Specifically, during initialization, the virtualization manager sends an SMC instruction to the firmware program. The SMC instruction includes agreed parameters indicating a request for access rights to prefetch registers. After receiving the SMC instruction, the firmware program parses the agreed parameters included in the SMC instruction and, based on the agreed parameters, configures the authorization register in each physical processor to "1" (assuming "1" represents a preset authorization value) to grant access rights to the corresponding prefetch registers to the virtualization manager. The firmware program then returns a default value, such as "0" by default, to the virtualization manager, indicating successful authorization. In the ARM processor architecture, the authorization register can be implemented as ACTLR_EL3, an auxiliary control register used to control whether the prefetch registers are authorized to the virtualization manager at EL2. Configuring ACTLR_EL3.ECTLREN = 1 indicates that the prefetch registers are authorized to the virtualization manager at EL2.

[0068] In another alternative embodiment, a message for inter-process communication can be added between the virtualization manager and the firmware program for prefetch registers. The virtualization manager can use this message to request access to the prefetch registers from the firmware program. This message has a specific format, which indicates that the virtualization manager is requesting access to the prefetch registers from the firmware program. Alternatively, a new instruction can be added between the virtualization manager and the firmware program for prefetch registers. The virtualization manager can use this new instruction to request access to the prefetch registers from the firmware program.

[0069] It should be noted that no matter what method is used to apply for access rights to the prefetch registers from the firmware program, the access rights to the prefetch registers applied for by the virtualization manager during the initialization process can always belong to the virtualization manager until the virtualization manager is restored to factory settings or reinitialized. At this time, the virtualization manager stops using the access rights to the prefetch registers, and during the reinitialization process, the virtualization manager can re-apply to the firmware program for access rights to the prefetch registers.

[0070] Furthermore, after the virtualization manager applies for access rights to the prefetch registers, in order to achieve dynamic configuration of the prefetch policy, it also needs to be able to perceive the operation of the virtualization instance to configure the target prefetch policy parameters for the prefetch registers, and intercept the target prefetch policy parameters configured by the virtualization instance for the prefetch registers, so as to replace the virtualization instance in configuring the target prefetch policy parameters to the prefetch registers in the target physical processor responsible for running the virtualization instance, and ultimately achieve the purpose of dynamically configuring the prefetch policy according to the scheduling situation of the virtualization instance. Based on this, when the virtualization manager responds to the operation of the virtualization instance configuring the target prefetch policy parameters for the prefetch register and configures the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled, it is used to: during the initialization process, configure the ability of the virtualization instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register. "Trap out" can be understood as a switch of execution permissions, that is, switching from executing the virtualization instance in EL1 to executing the virtualization manager in EL2; further, in response to the virtualization instance trapping out to the virtualization manager, the virtualization instance is executed. At this time, the virtualization instance can intercept the target prefetch policy parameters configured for the prefetch register by the virtualization instance where the trap occurs, and store the target prefetch policy parameters in the software data structure of the virtualization instance; thereafter, the target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualization instance where the trap occurs is scheduled, so as to realize dynamic configuration of the prefetch policy.

[0071] In an embodiment of the present disclosure, as shown in FIG2 , the hardware resources of the physical machine also include: an auxiliary authorization control register 2014 and a virtualization trap control register 2015, both of which are system registers. The auxiliary authorization control register is used to control whether to close the virtualization instance's direct access rights to the prefetch register, and the virtualization trap control register is used to control whether to allow the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register. Based on this, when configuring the virtualization instance's ability to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register, the virtualization manager is also used to: on the one hand, configure the auxiliary authorization control register to a preset value indicating prohibition of authorization to close the virtualization instance's direct access rights to the prefetch register; on the other hand, configure the virtualization trap register to a preset value indicating permission to trap to control the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register. In different processor architectures, the auxiliary authorization control register and the virtualization trap control register can have different implementations, which are not limited to this. For example, taking the ARM processor architecture as an example, the auxiliary authorization control register can be implemented as the ACTLR_EL2 register, which is an auxiliary control register used to assist in controlling whether to authorize software resources in EL1 to access prefetch registers. For example, configuring ACTLR_EL2.ACTLREN=0 means turning off or prohibiting the virtualization instance's direct access to the prefetch registers. Correspondingly, in the ARM processor architecture, the virtualization trap control register can be the HCR_EL2 register, which is also an auxiliary control register used to assist in controlling whether to allow the virtualization instance in EL1 to trap to the virtualization manager in EL2 when accessing the prefetch registers. Configuring HCR_EL2.TIDCP=1 means allowing the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch registers.

[0072] In an optional embodiment, after configuring the virtualization manager to indicate the ability of the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register, the virtualization manager can create a virtualization instance according to the user's application needs, and during the operation of the virtualization instance, monitor whether there is a virtualization instance trapping to the virtualization manager, and when it is detected that a virtualization instance has trapped, the target prefetch policy parameters configured for the prefetch register of the virtualization instance that has trapped are intercepted. More specifically, each virtualization instance has a unique identifier. When the virtualization manager detects the appearance of the identifier of the local virtualization instance, it determines that the virtualization instance has trapped to the virtualization manager, and intercepts the target prefetch policy parameters configured for the prefetch register of the virtualization instance that has trapped.

[0073] In the disclosed embodiment, a virtualization instance is created by a virtualization manager. The virtualization manager and the virtualization instance belong to the same virtualization thread, which can be referred to as a virtual central processing unit (VCPU) thread. Before trapping out, the virtualization instance can occupy physical processor resources, and the physical processor runs the virtualization instance. To facilitate distinction from the target physical processor, the physical processor at this time is referred to as the first physical processor. While the first physical processor is running the virtualization instance, the virtualization instance can initiate an operation to configure target prefetch policy parameters for prefetch registers. For example, an operation to configure target prefetch policy parameters for prefetch registers can be initiated based on the user's application requirements. It should be noted that the target prefetch policy parameters are not necessarily applicable to the parameter configuration requirements of other virtualization instances for prefetch registers. When the virtualization instance initiates an operation to configure target prefetch policy parameters for prefetch registers, based on the trapping capability configured above, the virtualization instance will trap out to the virtualization manager, that is, the first physical processor will be preempted by the virtualization manager, and the first physical processor will then run the virtualization manager. In order to facilitate the normal use of the first physical processor by other virtualized instances in the future, the prefetch registers in the first physical processor can be restored to the default prefetch policy parameters. Optionally, the default prefetch policy parameters can select relatively balanced prefetch policy parameters so as to be applicable to as many virtualized instances as possible. Based on this, the virtualization manager is also used to: when detecting that a virtualized instance has fallen out of the virtualization manager, seize the first physical processor currently occupied by the virtualized instance that has fallen out, and restore the prefetch registers in the first physical processor to the default prefetch policy parameters; wherein, the virtualization manager and the virtualized instance that has fallen out belong to different functional modules in the first virtualization thread, the first physical processor is scheduled to the first virtualization thread to be responsible for running different functional modules in the first virtualization thread, and at the same time, the first physical processor is responsible for running a functional module in the first virtualization thread.

[0074] In this embodiment, the order in which the virtualization manager restores the prefetch registers in the first physical processor to the default prefetch policy parameters and configures the target prefetch policy parameters for the prefetch registers in the virtualization instance that intercepts the trap situation is not limited. Preferably, the prefetch registers in the first physical processor can be restored to the default prefetch policy parameters first, and then the target prefetch policy parameters configured for the prefetch registers in the virtualization instance that intercepts the trap situation are configured.

[0075] Furthermore, the virtualization manager is also used to: after intercepting the target prefetch policy parameters, set a scheduling point for the first physical processor to allow other threads on the physical machine to preempt the first physical processor, and wait for the first virtualization thread to be rescheduled when the first physical processor is preempted by other threads. Accordingly, when the virtualization manager configures the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance in which the trap occurs is scheduled, it is used to: configure the target prefetch policy parameters to the prefetch registers in the target physical processor when the first virtualization thread is rescheduled to the target physical processor. The target physical processor can be the first physical processor or other physical processor different from the first physical processor, such as the second physical processor. In some application scenarios, a binding relationship between each virtualization instance and the physical processor can be established, and when the virtualization instance is scheduled for execution, it can be assigned a physical processor with which it has a binding relationship. In some other application scenarios, it is also possible not to establish a binding relationship between the virtualization instance and the physical processor. When the virtualization instance is scheduled for execution, the physical processor can be allocated to the virtualization instance randomly or according to a set resource allocation policy, such as giving priority to physical processors with lighter loads. It is explained here that since the virtualization manager is being executed when the first physical processor is preempted by other threads, when the first virtualization thread is rescheduled to the target physical processor, it will continue to be executed from the virtualization manager. Therefore, the virtualization manager can configure the target prefetch policy parameters to the prefetch registers in the target physical processor when the first virtualization thread is rescheduled to the target physical processor. Furthermore, after configuring the target prefetch policy parameters to the prefetch registers in the target physical processor, it can be switched back to the virtualization instance. At this time, the target physical processor can continue to run the virtualization instance and, in the process of running the virtualization instance, perform data and / or instruction prefetch operations according to the target prefetch policy parameters stored in the prefetch registers.

[0076] Furthermore, the virtualization manager is further configured to restore the prefetch register in the target physical processor to a default prefetch policy parameter when the virtualization instance scheduled to the target physical processor is shut down or destroyed.

[0077] In the disclosed embodiment, the virtualization manager obtains access rights to the prefetch registers of the physical processor and sets a method for trapping the access of the virtualization instance to the prefetch registers to the virtualization manager, so that the prefetch registers can be simulated and transmitted to the virtualization instance through virtualization technology, allowing the user of the virtualization instance to flexibly configure the prefetch policy, and restore the prefetch policy on the corresponding physical processor to the default value after the user destroys the virtualization instance. The prefetch policy used by the physical processor where the virtualization instance is located can be configured separately for the virtualization instance, thereby improving the prefetch efficiency and allowing the virtualization instances of different users on the physical machine to simultaneously obtain the performance improvement advantages brought by the prefetch policy when running different types of applications.

[0078] For ease of understanding, the following, in conjunction with Figure 3, takes the physical processor before and after the prefetch policy configuration scheme as an example, and illustrates the prefetch policy configuration scheme provided by the above embodiment from the perspective of the interaction between the virtual machine instance, the virtualization manager, the firmware program, and the physical processor. As shown in Figure 3, implementing dynamic configuration of the hardware prefetch policy includes the following steps:

[0079] Step 1: Initialize the virtualization manager. The initialization process of the virtualization manager mainly includes the following steps:

[0080] Step 11: The virtualization manager sends a communication instruction to the firmware program to apply for access rights to the pre-fetch register, thereby granting the firmware program access rights to the pre-fetch register.

[0081] Step 12: The firmware program configures the value of the authorization register in at least one physical processor to a preset value indicating authorization according to the communication instruction sent by the virtualization manager for applying for access rights to the prefetch register;

[0082] Step 13: When the value of the authorization register is a preset value indicating authorization, return authorization success result information to the virtualization manager to open the access right of the pre-fetch register to the virtualization manager;

[0083] Step 2: The virtualization manager reads and saves the default prefetch policy parameters of the prefetch register, referred to as default values.

[0084] Step 3: The virtualization manager configures the auxiliary authorization control register and the virtualization trap control register to enable the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register.

[0085] Step 4: The virtualization manager creates a virtual machine instance, and the virtual machine instance starts running;

[0086] Step 5: The virtualization instance configures target prefetch policy parameters for the prefetch register and traps to the virtualization manager;

[0087] Step 6: The virtualization manager intercepts the target prefetch policy parameters configured for the prefetch register of the virtualization instance;

[0088] Step 7: The virtualization manager configures the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance is scheduled;

[0089] Step 8: The virtualization manager returns the virtualized instance so that the target physical processor continues to run the virtualized instance;

[0090] Step 9: When the virtualized instance is shut down or destroyed, the virtualization manager restores the prefetch registers in the target physical processor to the default prefetch policy parameters and clears the relevant information of the virtualized instance.

[0091] At this point, the prefetching strategy configuration scheme has been executed, making it possible to flexibly and dynamically configure prefetching strategies for different virtualization instances according to the scheduling of virtualization instances, solving the problem in the existing technology that the performance of multiple applications cannot be taken into account due to the inability to flexibly and dynamically configure prefetching strategies.

[0092] FIG4 is a flow chart illustrating a method for configuring a prefetch policy according to an exemplary embodiment of the present disclosure. The method is applied to a virtualization manager for creating and managing virtualized instances on a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for controlling prefetching by the hardware prefetcher. As shown in FIG4 , the method includes:

[0093] 401. Apply for access rights to the prefetch register from a firmware program in the physical machine that is used to perform read and write control on the prefetch register;

[0094] 402. When the access right to the prefetch register is successfully applied for, in response to the operation of the virtualization instance to configure the target prefetch policy parameters for the prefetch register, the target prefetch policy parameters are configured for the prefetch register in the target physical processor to which the virtualization instance is scheduled.

[0095] In an optional embodiment, applying for access rights to prefetch registers to a firmware program in a physical machine that is used to perform read and write control on the prefetch registers includes: sending a communication instruction to the firmware program during an initialization process, the communication instruction including an agreed parameter indicating the application for access rights to the prefetch registers, so that the firmware program configures an authorization register in at least one physical processor to a preset value indicating authorization, so as to open access rights to the prefetch registers to the virtualization manager; and receiving authorization success result information returned by the firmware program.

[0096] In an optional embodiment, in response to the operation of the virtualization instance configuring target prefetch policy parameters for prefetch registers, the target prefetch policy parameters are configured to the prefetch registers in the target physical processor to which the virtualization instance is scheduled, including: during the initialization process, configuring the virtualization instance to be able to trap out to the virtualization manager when the target prefetch policy parameters are configured for the prefetch registers; in response to the virtualization instance trapping out to the virtualization manager, intercepting the target prefetch policy parameters configured for the prefetch registers by the virtualization instance in which the trap occurs; and configuring the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance in which the trap occurs is scheduled.

[0097] In an optional embodiment, during the initialization process, the ability of the virtualization instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register is configured, including: during the initialization process, configuring the auxiliary authorization control register of the physical machine to a preset value indicating that authorization is prohibited, so as to close the virtualization instance's direct access rights to the prefetch register; configuring the virtualization trap register of the physical machine to a preset value indicating that trap out is allowed, so as to control the virtualization instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register.

[0098] Optionally, in response to a virtualization instance trapping to the virtualization manager, and before intercepting the target prefetch policy parameters, the method further includes: preempting the first physical processor currently occupied by the virtualization instance where the trap occurs, and restoring the prefetch registers in the first physical processor to default prefetch policy parameters; wherein, the virtualization manager and the virtualization instance where the trap occurs belong to different functional modules in the first virtualization thread, and the first physical processor is scheduled to the first virtualization thread to be responsible for running different functional modules in the first virtualization thread.

[0099] Further optionally, after intercepting the target prefetch policy parameters, the method also includes: setting a scheduling point for the first physical processor, allowing other threads on the physical machine to preempt the first physical processor, and waiting for the first virtualization thread to be rescheduled when the first physical processor is preempted by other threads; wherein, configuring the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance in which the trap occurs is scheduled includes: configuring the target prefetch policy parameters to the prefetch register in the target physical processor when the first virtualization thread is rescheduled to the target physical processor.

[0100] Further optionally: when the virtualization instance scheduled to the target physical processor is shut down or destroyed, the prefetch register in the target physical processor is restored to the default prefetch policy parameters.

[0101] In the embodiment of the present disclosure, the privilege level of the firmware program is higher than the privilege level of the virtualization manager, and the privilege level of the virtualization manager is higher than the privilege level of the virtualization instance.

[0102] The detailed implementation and beneficial effects of each step in the method shown in FIG4 provided by the embodiment of the present disclosure have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0103] It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution entity of step 401 to step 402 can be device A.

[0104] FIG5 is a flow chart of another prefetch policy configuration method provided by an exemplary embodiment of the present disclosure. The method is applied to a firmware program in a physical machine for reading and writing prefetch registers, and the physical machine also includes a virtualization manager for creating and managing virtualized instances. As shown in FIG5 , the method includes:

[0105] 501. When the virtualization manager applies for access rights to the prefetch register, configure an authorization register in at least one physical processor to a preset value indicating authorization, so as to provide the virtualization manager with access rights to the prefetch register.

[0106] 502. Return authorization success structure information to the virtualization manager.

[0107] The detailed implementation and beneficial effects of each step in the method shown in FIG5 provided by the embodiment of the present disclosure have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0108] It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution entity of step 501 to step 502 can be device A.

[0109] FIG6 is a flow chart illustrating another prefetch policy configuration method provided by an exemplary embodiment of the present disclosure. This method is applied to a virtualization instance created by a virtualization manager in a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for controlling prefetching by the hardware prefetcher. As shown in FIG6 , the method includes:

[0110] 601. In response to a prefetch strategy configuration operation, obtain target prefetch strategy parameters configured for a prefetch register;

[0111] 602. Based on the ability of the virtualization instance to trap into the virtualization manager when configuring target prefetch policy parameters for prefetch registers, the virtualization manager is configured to allow the virtualization manager to intercept the target prefetch policy parameters and configure them to the prefetch registers in the target physical processor to which the virtualization instance is scheduled.

[0112] The detailed implementation and beneficial effects of each step in the method shown in FIG6 provided by the embodiment of the present disclosure have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0113] It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution entity of step 601 to step 602 can be device A.

[0114] FIG7 is a flow chart of a cache prefetching method provided by an exemplary embodiment of the present disclosure. The method is applied to a target physical processor in a physical machine. The target physical processor includes a hardware prefetcher and a prefetch register for controlling prefetching of the hardware prefetcher. The target prefetching policy parameters in the prefetch register are configured according to the steps of the method shown in FIG4. As shown in FIG7, the method includes:

[0115] 701. Read target prefetch strategy parameters from the prefetch register;

[0116] 702. During the execution of the scheduled virtualized instance, perform data and / or instruction prefetch operations based on target prefetch policy parameters.

[0117] The detailed implementation and beneficial effects of each step in the method shown in FIG. 7 provided by the embodiment of the present disclosure have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0118] It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution entity of steps 701 to 702 can be device A; for another example, the execution entity of step 701 can be device A, and the execution entity of step 702 can be device B; and so on.

[0119] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel. The sequence numbers of the operations, such as 401, 402, 501, 502, 601, 602, 701, 702, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to being different types.

[0120] FIG8 is a schematic diagram of a prefetch policy configuration device provided in an exemplary embodiment of the present disclosure. The device is applied to a virtualization manager for creating and managing virtualized instances on a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for controlling prefetching by the hardware prefetcher. As shown in FIG8 , the device includes:

[0121] An authorization application module 81 is used to apply for access rights to the prefetch register from a firmware program in the physical machine that is used to perform read and write control on the prefetch register;

[0122] The policy configuration module 82 is used to respond to the operation of the virtualization instance to configure the target prefetch policy parameters for the prefetch register when successfully applying for access rights to the prefetch register, and configure the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled.

[0123] In an optional embodiment, when the authorization application module 81 is used to apply for access rights to the prefetch register from a firmware program in a physical machine that is used to perform read and write control on the prefetch register, it is used to: send a communication instruction to the firmware program during the initialization process, wherein the communication instruction includes an agreed parameter indicating the application for access rights to the prefetch register, so that the firmware program configures the authorization register in the at least one physical processor to a preset value indicating authorization, so as to open access rights to the prefetch register to the virtualization manager; and receive authorization success result information returned by the firmware program.

[0124] In an optional embodiment, the policy configuration module 82, when used to respond to the operation of the virtualization instance configuring the target prefetch policy parameters for the prefetch registers and configuring the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance is scheduled, is used to: during the initialization process, configure the virtualization instance's ability to trap out to the virtualization manager when the target prefetch policy parameters are configured for the prefetch registers; in response to the virtualization instance trapping out to the virtualization manager, intercept the target prefetch policy parameters configured for the prefetch registers by the virtualization instance that has trapped out; and configure the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance that has trapped out is scheduled.

[0125] Optionally, when the policy configuration module 82 is used to configure the ability of the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register during the initialization process, it is also used to: configure the auxiliary authorization control register of the physical machine to a preset value indicating that authorization is prohibited, so as to close the virtualization instance's direct access to the prefetch register; configure the virtualization trap register of the physical machine to a preset value indicating that trap is allowed, so as to control the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register.

[0126] Optionally, in response to a virtualization instance trapping to the virtualization manager, and before intercepting the target prefetch policy parameters, a preemption module and a recovery module are provided, wherein the preemption module is used to preempt the first physical processor currently occupied by the virtualization instance where the trapping occurs, and the recovery module is used to restore the prefetch registers in the first physical processor to the default prefetch policy parameters; wherein the virtualization manager and the virtualization instance where the trapping occurs belong to different functional modules in the first virtualization thread, and the first physical processor is scheduled to the first virtualization thread to be responsible for running different functional modules in the first virtualization thread.

[0127] Further optionally, it also includes a setting module for setting a scheduling point for the first physical processor after intercepting the target prefetch policy parameters, allowing other threads on the physical machine to preempt the first physical processor, and waiting for the first virtualization thread to be rescheduled when the first physical processor is preempted by other threads; wherein, when the policy configuration module is used to configure the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance in which the trap occurs is scheduled, it is used to: when the first virtualization thread is rescheduled to the target physical processor, configure the target prefetch policy parameters to the prefetch registers in the target physical processor.

[0128] Further optionally, the restoration module is further configured to restore the prefetch registers in the target physical processor to default prefetch policy parameters when the virtualization instance scheduled to the target physical processor is shut down or destroyed.

[0129] In the embodiment of the present disclosure, the privilege level of the firmware program is higher than the privilege level of the virtualization manager, and the privilege level of the virtualization manager is higher than the privilege level of the virtualization instance.

[0130] The detailed implementation and beneficial effects of each module in the device shown in FIG8 provided by the embodiment of the present disclosure have been described in detail in the aforementioned embodiment and will not be elaborated here.

[0131] FIG9 is a schematic diagram of the structure of another prefetch policy configuration device provided by an exemplary embodiment of the present disclosure. The device is applied to a firmware program for reading and writing prefetch registers in a physical machine, and the physical machine also includes a virtualization manager for creating and managing virtualized instances. As shown in FIG9 , the device includes:

[0132] An authorization configuration module 91 is configured to configure an authorization register in at least one physical processor to a preset value indicating authorization when the virtualization manager applies for access rights to the prefetch register, so as to grant access rights to the prefetch register to the virtualization manager;

[0133] The authorization information returning module 92 is used to return authorization success structure information to the virtualization manager.

[0134] The detailed implementation and beneficial effects of each module in the device shown in FIG9 provided by the embodiment of the present disclosure have been described in detail in the aforementioned embodiment and will not be elaborated here.

[0135] FIG10 is a schematic diagram of the structure of another prefetch policy configuration device provided by an exemplary embodiment of the present disclosure. Applied to a virtualized instance created by a virtualization manager in a physical machine, at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for controlling prefetching by the hardware prefetcher. As shown in FIG10 , the device includes:

[0136] The parameter acquisition module 1001 is used to respond to the prefetch strategy configuration operation and obtain target prefetch strategy parameters configured for the prefetch register;

[0137] The trap module 1002 is used to indicate the ability of the virtualized instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch registers based on the configuration of the virtualization manager, and trap to the virtualization manager so that the virtualization manager can intercept the target prefetch policy parameters and configure them to the prefetch registers in the target physical processor to which the virtualized instance is scheduled.

[0138] The detailed implementation and beneficial effects of each module in the device shown in FIG10 provided by the embodiment of the present disclosure have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0139] FIG11 is a schematic diagram of the structure of a cache prefetching device provided by an exemplary embodiment of the present disclosure. Applied to a target physical processor in a physical machine, the target physical processor includes a hardware prefetcher and a prefetch register for controlling prefetching by the hardware prefetcher. The target prefetching policy parameters in the prefetch register are configured according to the steps of the method shown in FIG4 . As shown in FIG11 , the device includes:

[0140] Parameter acquisition strategy 1101, used to read target prefetch strategy parameters from the prefetch register;

[0141] The prefetch operation execution module 1102 is configured to execute data and / or instruction prefetch operations based on target prefetch policy parameters during the execution of the scheduled virtualized instance.

[0142] The detailed implementation and beneficial effects of each module in the device shown in FIG11 provided by the embodiment of the present disclosure have been described in detail in the aforementioned embodiments and will not be elaborated here.

[0143] Figure 12 is a schematic diagram of the structure of a processor provided by an exemplary embodiment of the present disclosure. The processor is responsible for running a virtualized instance and includes a hardware prefetcher 1201 and a prefetch register 1202 for controlling prefetches performed by the hardware prefetcher. The target prefetch policy parameters in the prefetch register are configured according to the steps of the method shown in Figure 4. The processor is configured to execute a computer program to implement the steps of the cache prefetch method shown in Figure 7.

[0144] In the embodiment of the present disclosure, the processor may execute a program for the prefetch policy configuration method and the cache prefetch method.

[0145] Optionally, the processor can be configured to perform the following steps: apply for access rights to the prefetch register from the firmware program in the physical machine that is used to control the reading and writing of the prefetch register; if the access rights to the prefetch register are successfully applied for, in response to the operation of the virtualization instance to configure the target prefetch policy parameters for the prefetch register, configure the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled.

[0146] Optionally, the processor can be configured to perform the following steps: when the virtualization manager applies for access rights to the prefetch register, configure the authorization register in at least one physical processor to a preset value indicating authorization to open access rights to the prefetch register to the virtualization manager; and return authorization success structure information to the virtualization manager.

[0147] Optionally, the processor can be configured to perform the following steps: in response to a prefetch policy configuration operation, obtain target prefetch policy parameters configured for prefetch registers; based on the ability of the virtualization instance configured in the virtualization manager to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch registers, trap to the virtualization manager so that the virtualization manager can intercept the target prefetch policy parameters and configure them to the prefetch registers in the target physical processor to which the virtualization instance is scheduled.

[0148] Optionally, the processor may be configured to perform the following steps: reading target prefetch policy parameters from a prefetch register; and performing data and / or instruction prefetch operations based on the target prefetch policy parameters during execution of the scheduled virtualized instance.

[0149] The detailed implementation and beneficial effects of each module shown in FIG12 provided in the embodiment of the present disclosure have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0150] The above-mentioned memory can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0151] FIG13 is a schematic diagram illustrating the structure of an electronic device provided in an embodiment of the present disclosure. As shown in FIG13 , the electronic device includes a memory 1301 and a processor 1302. The memory 1301 can be configured to store various other data to support operations on the electronic device. Examples of such data include instructions for any application or method operating on the electronic device. The memory 1301 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as SRAM, EEPROM, EPROM, PROM, ROM, magnetic storage, flash memory, magnetic disk, or optical disk.

[0152] The memory 1301 is used to store programs;

[0153] The processor 1302 is coupled to the memory 1301 and is configured to execute the program stored in the memory 1301 to implement the methods provided in the above method embodiments.

[0154] Optionally, the electronic device may further include other components such as a communication component 1303, a display 1304, a power supply component 1305, and an audio component 1306. FIG12 schematically illustrates only some of the components, and does not imply that the electronic device only includes the components shown in FIG12. The electronic device of this embodiment may be implemented as a terminal device such as a desktop computer, a laptop computer, a smartphone, or an IoT device, or as a server-side device such as a conventional server, a cloud server, or a server array.

[0155] The above-mentioned communication component is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G and other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology and other technologies.

[0156] The above-mentioned display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor can not only sense the boundary of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0157] The power supply assembly provides power to various components of the device in which the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located.

[0158] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) containing computer-usable program code.

[0159] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0160] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0161] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0162] In a typical configuration, a computing device includes one or more processors (Central Processing Unit, referred to as CPU), input / output interfaces, network interfaces, and memory.

[0163] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0164] Accordingly, an embodiment of the present disclosure further provides a computer-readable storage medium storing a computer program, which, when executed by a computer, can implement the steps or functions of the methods provided in the above-mentioned method embodiments.

[0165] Computer-readable storage media may also be referred to as computer storage media. They may include data signals transmitted in baseband or as part of a carrier wave, carrying readable program code. Such transmitted data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable storage media may transmit, propagate, or transfer programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0166] The program code contained in the computer-readable storage medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, radio frequency, etc., or any suitable combination of the foregoing.

[0167] The embodiments of the present disclosure further provide a computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method provided in the embodiments of the present disclosure is implemented.

[0168] The embodiments of the present disclosure further provide a computer program, which, when executed by a processor, implements the method provided in the embodiments of the present disclosure.

[0169] Optionally, the above-mentioned computer program implements the program code of the following steps when executed by the processor: applying for access rights to the prefetch register from the firmware program in the physical machine used to control the reading and writing of the prefetch register; if the access rights to the prefetch register are successfully applied for, in response to the operation of the virtualization instance to configure the target prefetch policy parameters for the prefetch register, the target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualization instance is scheduled.

[0170] Optionally, the computer program implements the following program code when executed by a processor: when the virtualization manager applies for access rights to the prefetch register, configuring the authorization register in at least one physical processor to a preset value indicating authorization, so as to open access rights to the prefetch register to the virtualization manager; and returning authorization success structure information to the virtualization manager.

[0171] Optionally, the computer program implements program code for the following steps when executed by a processor: in response to a prefetch policy configuration operation, obtaining target prefetch policy parameters configured for prefetch registers; and based on the ability of the virtualization manager configured to indicate that the virtualized instance has the ability to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch registers, trapping to the virtualization manager so that the virtualization manager can intercept the target prefetch policy parameters and configure them to the prefetch registers in the target physical processor to which the virtualized instance is scheduled.

[0172] Optionally, when the above computer program is executed by a processor, program code implementing the following steps: reading target prefetch policy parameters from a prefetch register; and performing data and / or instruction prefetch operations based on the target prefetch policy parameters during the execution of the scheduled virtualized instance.

[0173] Computer-readable storage media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

[0174] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0175] The above are merely examples of the present disclosure and are not intended to limit the present disclosure. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure are intended to be included within the scope of the claims of the present disclosure. Industrial Applicability

[0176] The solution provided by the embodiment of the present disclosure can be applied to the configuration process of the prefetch strategy, and an application for access rights to the prefetch register is made to the firmware program in the physical machine for reading and writing control of the prefetch register; when the access rights to the prefetch register are successfully applied for, the target prefetch strategy parameters are configured for the prefetch register in response to the operation of the virtualization instance to configure the prefetch strategy parameters for the prefetch register, and the target prefetch strategy parameters are configured to the prefetch register in the target physical processor to which the virtualization instance is scheduled, thereby solving the technical problem in the prior art that the performance of multiple applications cannot be taken into account due to the inability to flexibly and dynamically configure the prefetch strategy.

Claims

1. A physical machine, wherein the hardware resources of the physical machine at least include at least one physical processor, the physical processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher; the software resources of the physical machine at least include a firmware program for reading and writing control of the prefetch register and a virtualization manager for creating and managing virtualization instances; The virtualization manager is also used to apply for access rights to the prefetch register from the firmware program. When the access rights to the prefetch register are successfully applied for, the virtualization manager responds to the operation of the virtualization instance configuring target prefetch policy parameters for the prefetch register, and configures the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled.

2. The physical machine according to claim 1, wherein: The physical processor also includes a grant register; The firmware program is used to configure the authorization register in the at least one physical processor to a preset value indicating authorization when the virtualization manager applies for access rights to the pre-fetch register, so as to open the access rights to the pre-fetch register to the virtualization manager.

3. The physical machine according to claim 1, wherein: The virtualization manager, in response to the operation of the virtualization instance configuring the target prefetch policy parameter for the prefetch register, configures the target prefetch policy parameter to the prefetch register in the target physical processor to which the virtualization instance is scheduled, for: During initialization, configuring an ability to indicate to the virtualized instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register; In response to the virtualization instance trapping to the virtualization manager, intercepting the target prefetch policy parameter configured for the prefetch register by the virtualization instance where the trap occurs; The target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualized instance where the trap occurs is scheduled.

4. The physical machine according to claim 3, wherein: The hardware resources of the physical machine also include: an auxiliary authorization control register and a virtualization trap control register; The virtualization manager, when configuring the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameter for the prefetch register, is further configured to: Configuring the auxiliary authorization control register to a preset value indicating that authorization is prohibited, so as to close the direct access right of the virtualized instance to the pre-fetch register; The virtualization trap register is configured as a preset value indicating that trap is allowed, so as to control the virtualization instance to trap to the virtualization manager when the target prefetch policy parameter is configured for the prefetch register.

5. The physical machine according to claim 3 or 4, wherein: The virtualization manager is also used to: In response to the virtualization instance trapping to the virtualization manager, preempting a first physical processor currently occupied by the virtualization instance where the trapping occurs, and restoring a prefetch register in the first physical processor to a default prefetch policy parameter; The virtualization manager and the virtualization instance where the trap occurs belong to different functional modules in the first virtualization thread, and the first physical processor is scheduled to the first virtualization thread to be responsible for running the different functional modules in the first virtualization thread.

6. A prefetch policy configuration method, applied to a virtualization manager for creating and managing virtualization instances on a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher, the method comprising: Applying for access rights to the pre-fetch register from a firmware program in the physical machine for reading and writing the pre-fetch register; When the access right to the prefetch register is successfully applied for, in response to the operation of the virtualization instance configuring the target prefetch policy parameters for the prefetch register, the target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualization instance is scheduled.

7. The method according to claim 6, wherein: Applying for access rights to the pre-fetch register from a firmware program in the physical machine for reading and writing the pre-fetch register includes: Sending a communication instruction to the firmware program during the initialization process, wherein the communication instruction includes an agreed parameter indicating an application for access rights to the pre-fetch register, so that the firmware program configures the authorization register in the at least one physical processor to a preset value indicating authorization, so as to open access rights to the pre-fetch register to the virtualization manager; Receive authorization success result information returned by the firmware program.

8. The method according to claim 6, wherein: In response to the operation of configuring the target prefetch policy parameters for the prefetch register by the virtualization instance, configuring the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled, comprising: During initialization, configuring the virtualized instance to be capable of trapping to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register; In response to the virtualization instance trapping to the virtualization manager, intercepting the target prefetch policy parameter configured for the prefetch register by the virtualization instance where the trap occurs; The target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualized instance where the trap occurs is scheduled.

9. The method according to claim 8, wherein: During the initialization process, configuring the virtualization instance to be able to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register includes: During the initialization process, the auxiliary authorization control register of the physical machine is configured to a preset value indicating that authorization is prohibited, so as to close the direct access right of the virtualized instance to the pre-fetch register; The virtualization trap register of the physical machine is configured to be a preset value indicating that trapping is allowed, so as to control the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameter for the prefetch register.

10. The method according to claim 8, wherein: In response to a virtualization instance trapping to the virtualization manager, and before intercepting the target prefetch policy parameter, the method further includes: Seizing the first physical processor currently occupied by the virtualized instance in which the trap occurs, and restoring the prefetch register in the first physical processor to a default prefetch policy parameter; The virtualization manager and the virtualization instance where the trap occurs belong to different functional modules in the first virtualization thread, and the first physical processor is scheduled to the first virtualization thread to be responsible for running the different functional modules in the first virtualization thread.

11. The method according to any one of claims 6 to 10, wherein: Also includes: When the virtualized instance scheduled to the target physical processor is shut down or destroyed, the prefetch register in the target physical processor is restored to a default prefetch policy parameter.

12. A pre-fetch policy configuration method, applied to a firmware program in a physical machine for reading and writing pre-fetch registers, wherein the physical machine also includes a virtualization manager for creating and managing virtualization instances, the method comprising: When the virtualization manager applies for access rights to the pre-fetch register, configuring an authorization register in at least one physical processor to a preset value indicating authorization, so as to open access rights to the pre-fetch register to the virtualization manager; Return authorization success structure information to the virtualization manager.

13. A pre-fetch strategy configuration method, wherein: The method is applied to a virtualized instance created by a virtualization manager in a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher; the method includes: In response to the prefetch strategy configuration operation, obtaining target prefetch strategy parameters configured for the prefetch register; Based on the ability of the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch registers, the virtualization instance traps to the virtualization manager so that the virtualization manager can intercept the target prefetch policy parameters and configure them to the prefetch registers in the target physical processor to which the virtualization instance is scheduled.

14. A cache prefetching method, wherein: A target physical processor applied to a physical machine, the target physical processor comprising a hardware prefetcher and a prefetch register for prefetching the hardware prefetcher, wherein a target prefetch strategy parameter in the prefetch register is configured according to a method according to any one of claims 1 to 8; the method comprising: Reading a target prefetch strategy parameter from the prefetch register; During the running of the scheduled virtualized instance, data and / or instruction prefetch operations are performed based on the target prefetch policy parameters.

15. A processor, wherein: The processor is responsible for running the virtualization instance, and the processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher, and the target prefetch strategy parameters in the prefetch register are configured according to the method described in any one of claims 6-11; the processor is used to execute a computer program to implement the steps in the cache prefetch method described in claim 14.

16. An electronic device, comprising: A memory and a processor, wherein The memory is used to store programs; The processor is coupled to the memory and is used to execute the program stored in the memory to implement the steps in the method of any one of claims 6-11 and claims 12-14.

17. A computer program product, wherein: The method comprises a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 6 to 11 and claims 12 to 14.

18. A computer program product, wherein: The invention comprises a non-volatile computer-readable storage medium storing a computer program, wherein the computer program implements the steps of the method according to any one of claims 6 to 11 and claims 12 to 14 when executed by a processor.

19. A computer program, wherein When the computer program is executed by a processor, the steps in the method of any one of claims 6 to 11 and claims 12 to 14 are implemented.

20. A computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the processor is caused to implement the steps in the method according to any one of claims 6 to 11 and claims 12 to 14.

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