Semiconductor chip and electronic device

Abstract

Provided is a semiconductor chip in which pressure by a TEG is minimized in a region where a product circuit is formed. The semiconductor chip comprises: a first semiconductor substrate that has a first circuit formed thereon; a second semiconductor substrate that has a second circuit formed thereon and is overlaid and bonded to a first surface of the first semiconductor substrate; and a test element group that includes a device to be measured and a test circuit for testing the device to be measured, and that is formed on the first semiconductor substrate and the second semiconductor substrate. Of the device to be measured and the test circuit, only the device to be measured is formed on the second semiconductor substrate, and the test circuit is formed on the first semiconductor substrate.

Description

Semiconductor chips and electronic devices

[0001] The present technology (technology according to the present disclosure) relates to a semiconductor chip and an electronic device, and in particular to a semiconductor chip and an electronic device having a TEG.

[0002] Patent Document 1 discloses a test structure for CoW and WoW process monitors, in which a test circuit and a DUT are provided on the same plane.

[0003] JP 2015-46569 A

[0004] In Patent Document 1, the test circuit and the DUT are provided on the same plane, so there is a possibility that the area where the product circuit is configured will be compressed by the TEG.

[0005] The present technology aims to provide a semiconductor chip and electronic device in which the area where the product circuit is configured is prevented from being compressed by the TEG.

[0006] A semiconductor chip according to one aspect of the present technology comprises a first semiconductor substrate on which a first circuit is configured, a second semiconductor substrate on which a second circuit is configured and which is bonded to a first surface of the first semiconductor substrate, and a test element group having a device under test and a test circuit for testing the device under test and configured on the first semiconductor substrate and the second semiconductor substrate, wherein the second semiconductor substrate is configured with only the device under test out of the device under test and the test circuit, and the first semiconductor substrate is configured with the test circuit.

[0007] An electronic device according to an aspect of the present technology includes the semiconductor chip described above and an optical system that forms an image light from a subject on the semiconductor chip.

[0008] 5 is a chip layout diagram showing a configuration example of a semiconductor chip according to the first embodiment of the present technology. FIG. 6 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor chip according to the first embodiment of the present technology. FIG. 7 is a block diagram showing a configuration of an OCMT according to the first embodiment of the present technology. FIG. 8 is a flowchart showing a method for manufacturing a semiconductor chip according to the first embodiment of the present technology. FIG. 9 is a partially enlarged view showing an enlarged partial region of FIG. 5. FIG. 9 is a plan view showing a second semiconductor substrate obtained by singulating the second semiconductor wafer according to the first embodiment of the present technology. FIG. 10 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor chip according to a comparative example. FIG. 11 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor chip according to a first modified example of the first embodiment of the present technology. FIG. 12 is an explanatory view showing a state in which the semiconductor chip shown in FIG. 9 is mounted on an interposer. FIG. 13 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor chip according to a second modified example of the present technology. FIG. 14 is a longitudinal sectional view showing a cross-sectional configuration of a semiconductor chip according to a third modified example of the first embodiment of the present technology. FIG. 15 is a flowchart showing a method for manufacturing a semiconductor chip according to a fifth modified example of the first embodiment of the present technology. FIG. 16 is a chip layout diagram showing a configuration example of a semiconductor chip according to a second embodiment of the present technology. FIG. 17 is a block diagram showing a configuration example of a semiconductor chip according to the second embodiment of the present technology. FIG. 1 is an equivalent circuit diagram of a pixel of a semiconductor chip according to a second embodiment of the present technology. FIG. 2 is an explanatory diagram showing a stacked structure of a semiconductor chip according to a second embodiment of the present technology. FIG. 3 is a longitudinal sectional view showing a cross-sectional configuration of a part of a semiconductor chip according to a first modified example of the second embodiment of the present technology. FIG. 4 is a longitudinal sectional view showing a cross-sectional configuration of a part of a semiconductor chip according to a first modified example of the second embodiment of the present technology. FIG. 5 is a longitudinal sectional view showing a cross-sectional configuration of a part of a semiconductor chip according to a second modified example of the second embodiment of the present technology. FIG. 6 is a block diagram showing an example of a schematic configuration of an electronic device.

[0009] Hereinafter, preferred embodiments for carrying out the present technology will be described with reference to the drawings. Note that the embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0010] In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings include parts with different dimensional relationships and ratios. Furthermore, since drawings suitable for explaining the present technology are used, there may be differences in configuration between the drawings.

[0011] Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present technology can be modified in various ways within the technical scope defined by the claims.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0013] The description will be given in the following order: 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment Application examples to electronic devices

[0014] First Embodiment In this embodiment, an example in which the present technology is applied to a semiconductor chip having a structure in which a plurality of semiconductor substrates are stacked by chip-on-wafer (CoW) will be described.

[0015] On-chip monitor (TEG) There are two manufacturing methods for semiconductor chips having a stacked structure of multiple semiconductor substrates: wafer-on-wafer (WoW) technology, in which semiconductor wafers are bonded together, and chip-on-wafer (CoW) technology, in which individual semiconductor chips are bonded to a semiconductor wafer. Furthermore, semiconductor chips generally have a test pattern called a TEG (Test Element Group) to evaluate and manage circuit characteristics.

[0016] When manufacturing single-layer semiconductor chips or semiconductor chips using WoW, a TEG is generally provided in the scribe area (scribe TEG), and testing is performed using the scribe TEG. A scribe pad is provided in the scribe area for each device to be tested. Testing is performed by contacting the probe of an inspection device with the scribe pad for each device to be tested. After testing using the scribe TEG, a dicing process is performed to obtain individual semiconductor chips. The scribe TEG is destroyed in the dicing process and cannot be used thereafter.

[0017] When manufacturing semiconductor chips using CoW, the semiconductor chips bonded to the semiconductor wafer are already singulated and the scribe area is lost. Therefore, in CoW, a TEG must be provided in the area where the product circuit will be located, rather than in the scribe area. Such a TEG is known as an on-chip monitor TEG (hereinafter referred to as OCMT). Because the OCMT is not destroyed during singulation, testing using the TEG can be performed even after singulation. This allows for continuous monitoring of the circuit characteristics of the semiconductor chip. FIG. 8 is a diagram showing the longitudinal cross-sectional configuration of a semiconductor chip 2X according to a comparative example. The semiconductor chip 2X has a stacked structure in which a first semiconductor substrate A and a second semiconductor substrate B are stacked. The semiconductor chip 2X is configured with an OCMT 9X that includes a test circuit X and a device under test Y in addition to a product circuit Ba. Because the second semiconductor substrate B is configured with both the test circuit X and the device under test Y, the OCMT 9X may compress the area of ​​the second semiconductor substrate B where the product circuit Ba is located.

[0018] <Overall Configuration of Semiconductor Device> First, the overall configuration of the semiconductor device 1 will be described. As shown in FIG. 1 , the semiconductor device 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plane. That is, the semiconductor device 1 is mounted on the semiconductor chip 2. A plurality of bonding pads 14 are arranged on the edge of the semiconductor chip 2. The plurality of bonding pads 14 are arranged, for example, along four sides in the two-dimensional plane of the semiconductor chip 2. The plurality of bonding pads 14 are input / output terminals used to electrically connect the semiconductor chip 2 to an external device. The semiconductor device 1 includes an OCMT 9 that is an on-chip monitor TEG. The OCMT 9 is a test element group.

[0019] As shown in FIG. 2 , the semiconductor chip 2 has a stacked structure in which multiple semiconductor substrates are stacked. For example, the semiconductor chip 2 has a stacked structure in which a first semiconductor substrate A and a second semiconductor substrate B are stacked. One surface of the second semiconductor substrate B is bonded to the first surface S1 of the first semiconductor substrate A. The first semiconductor substrate A is an example of a first semiconductor substrate, and the second semiconductor substrate B is an example of a second semiconductor substrate. In this embodiment, the first semiconductor substrate A is a substrate manufactured in-house, and the second semiconductor substrate B is a substrate purchased from another company. Although not shown, the first semiconductor substrate A and the second semiconductor substrate B each have a stacked structure of semiconductor layers and multilayer wiring layers. The semiconductor device 1 also includes, as product circuits, a product circuit Aa and a product circuit Ba that are electrically connected to each other. The product circuit Aa is an example of a first circuit, and the product circuit Ba is an example of a second circuit. The product circuit Aa is configured on the first semiconductor substrate A, and the product circuit Ba is configured on the second semiconductor substrate B. The product circuit Aa may be the same type of electrical circuit as the product circuit Ba, or may be a different type of electrical circuit. For example, but not limited to, the product circuit Aa may be a logic circuit, and the product circuit Ba may be a memory circuit such as a dynamic random access memory (DRAM), or a system-on-chip (SoC) circuit such as an artificial intelligence (AI) or a CPU. The semiconductor chip 2 includes wiring L that forms the connection wiring for various circuits. A portion of the wiring L is used, for example, to connect the product circuit Aa and the product circuit Ba.

[0020] The OCMT 9 is configured across a first semiconductor substrate A and a second semiconductor substrate B. The OCMT 9 includes a test circuit X, a device under test (DUT) Y electrically connected to the test circuit X, and a measurement pad 14A electrically connected to the test circuit X. Of the device under test Y and the test circuit X, only the device under test Y is configured on the second semiconductor substrate B. The test circuit X is configured on the first semiconductor substrate A. More specifically, of the device under test Y and the test circuit X, only the test circuit X is configured on the first semiconductor substrate A. The OCMT 9 is a stacked test element group in which the test circuit X and the device under test Y are configured on different semiconductor substrates. The OCMT 9 is also electrically isolated from product circuits (product circuits Aa, Ba, etc.) configured on the semiconductor chip 2.

[0021] The OCMT 9 includes a wiring L1 that electrically connects the test circuit X and the measurement pad 14A, and a wiring L2 that electrically connects the test circuit X and the device under test Y. The wiring L2 is provided across the first semiconductor substrate A and the second semiconductor substrate B. The wiring L1 and the wiring L2 are other parts of the wiring L. When the wiring L1, the wiring L2, and the other wiring L are not to be distinguished from one another, they are simply referred to as wiring L. The wiring L is made of a conductor. Examples of materials that can be used to make the wiring L include metal materials.

[0022] Of the test circuit X and the device under test Y, we will first describe the device under test Y. The device under test Y is a device in which a portion of the product circuit is separately provided for testing. Although not shown, multiple devices under test Y are provided on the second semiconductor substrate B, and each of the multiple devices under test Y is connected to the test circuit X via wiring L2. The device under test Y may be a single element such as a transistor or resistor, or a circuit combining multiple elements. The device under test Y may also be a test pattern for evaluating the manufacturing process of a certain element. In this embodiment, we will describe the case where the device under test Y is a single element. The device under test Y is an element under test and is provided on an element-by-element basis. The device under test Y is an element of the same type as the element to be tested among the elements included in the product circuit Ba. Furthermore, the device under test Y is, for example, an element having the same technology node as the element included in the product circuit Baa. As an example, if an n-type MOSFET included in the product circuit Ba is to be tested, an n-type MOSFET is separately provided on the second semiconductor substrate B as the device under test Y. A device under test Y is separately provided on the same semiconductor substrate as the semiconductor substrate on which the product circuit Ba is provided. As shown in FIG. 3 , the device under test Y is, for example, an element such as a transistor Y1, a capacitor Y2, or a resistor Y3. Multiple types of devices under test Y may be provided on the second semiconductor substrate B. Furthermore, to confirm reproducibility, multiple elements of the same type may be provided on the second semiconductor substrate B as the device under test Y. For example, multiple transistors Y1, capacitors Y2, and resistors Y3 may be provided, or multiple p-type MOSFETs may be provided as the transistor Y1.

[0023] The test circuit X is an electrical circuit that performs a test on a device under test Y. As shown in FIG. 3 , the test circuit X includes, for example, a selection circuit X1, a switch X2, and an oscillation circuit X3. The selection circuit X1 has the function of selecting a portion of the multiple devices under test Y provided on the second semiconductor substrate B. The switch X2 also has a switching function for switching between the devices under test Y. The test circuit X performs a test on the selected or switched device under test Y. The following description will be given using the selection circuit X1 as an example. When a signal is input to the selection circuit X1 via the measurement pad 14A, the selection circuit selects one or more of the multiple devices under test Y in accordance with the input signal. The test circuit X then performs a test on the selected device under test Y based on the signal input to the selection circuit X1 from the outside via the measurement pad 14A. For example, if the selected element is a transistor Y1, the test circuit X tests the operation of the transistor Y1. For example, if the selected element is a capacitor Y2, the test circuit X tests the capacitance of the capacitor Y2 using the oscillation circuit X3. For example, if the selected element is resistor element Y3, test circuit X tests resistor element Y3. Then, test circuit X outputs the test result to the outside via measurement pad 14A. Note that test circuit X and device under test Y may or may not overlap in the thickness direction, as shown in FIG. 2.

[0024] The measurement pad 14A, electrically connected to the test circuit X, is provided on the semiconductor chip 2 with one surface exposed to the outside. In this embodiment, the measurement pad 14A is provided on the first semiconductor substrate A. The measurement pad 14A is a portion of the bonding pad 14 shown in FIG. 1 that is dedicated to the OCMT 9. When the measurement pad 14A is not to be distinguished from other bonding pads 14, it is simply referred to as the bonding pad 14. The measurement pad 14A is made of a conductor such as a metal. Examples of materials that can be used to make the measurement pad 14A include metals such as copper (Cu) and aluminum (Al).

[0025] <Method for Manufacturing Semiconductor Chip> Hereinafter, a method for manufacturing the semiconductor chip 2 will be described with reference to Fig. 4 to Fig. 7. Note that in this embodiment, the description will focus on CoW bonding, and descriptions of other parts may be omitted. The description will be mainly made with reference to the flowchart shown in Fig. 4.

[0026] First, a first semiconductor wafer WA and a second semiconductor wafer WB are prepared (step S101), and the second semiconductor wafer WB is singulated into second semiconductor substrates B (step S102). FIG. 5 shows the first semiconductor wafer WA, and FIG. 6 shows a more specific configuration of region WA1 in FIG. 5. As shown in FIG. 6, substrate portions that will become first semiconductor substrates A when singulated are already formed along the row and column directions on the first semiconductor wafer WA. Test circuits X are formed on each of the substrate portions that will become first semiconductor substrates A when singulated. Similarly, substrate portions that will become second semiconductor substrates B when singulated are already formed along the row and column directions on the second semiconductor wafer WB. FIG. 7 shows a portion of the substrate portion of the second semiconductor substrate B obtained by singulating the second semiconductor wafer WB. A device under test Y is formed on each of the substrate portions of the singulated second semiconductor substrates B.

[0027] 4, the individualized second semiconductor substrates B are bonded to the first semiconductor wafer WA (step S103). More specifically, from the individualized second semiconductor substrates B, only known good die (KGD) that meet the criteria are selected and bonded to the first semiconductor wafer WA. By bonding the second semiconductor substrate B to the first semiconductor wafer WA, a stacked OCMT 9 is formed on the substrate portion that will become the semiconductor chip 2 when the substrate is individualized.

[0028] Thereafter, a test is performed using the OCMT 9 (step S104). The test is performed by bringing the probes of the testing device into contact with the measurement pads 14A, for each substrate portion that will become a semiconductor chip 2 when the device is singulated. Any device Y to be tested can be selected by using at least one of the selection circuit X1 and the switch X2, so that multiple devices Y to be tested can be tested without moving the probes of the testing device.

[0029] Then, for each substrate portion that will become semiconductor chips 2 when singulated, it is determined whether the test results of the device under test Y satisfy the reference value (step S105). Substrate portions that are determined to satisfy the reference value (step S105, YES) are sequentially processed until the final product is produced (step S106). Substrate portions that are determined not to satisfy the reference value (step S105, NO) are not processed until the final product is produced. Note that the test results when it is determined not to satisfy the reference value are fed back to the manufacturing process up to that point (step S107).

[0030] <<Major Effects of the First Embodiment>> The major effects of the first embodiment will be described below, but first, an overview will be provided. In the semiconductor chip 2X according to the comparative example shown in FIG. 8 , both the test circuit X and the device under test Y are configured on the second semiconductor substrate B. Therefore, the OCMT9X may constrain the area of ​​the second semiconductor substrate B where the product circuit Ba is provided. Furthermore, when using a general-purpose product such as a DRAM or SoC as the second semiconductor substrate B, the production of the general-purpose product may be outsourced to another company, and the resulting wafers or chips may be purchased. It is not easy to configure a test circuit X, which is not easy to design, for a chip manufactured by outsourcing. Furthermore, configuring the test circuit X on a chip manufactured by outsourcing may result in the leakage of technology to the outsourcing company.

[0031] In contrast, the semiconductor chip 2 according to the first embodiment of the present technology includes an OCMT 9 having a device under test Y and a test circuit X for testing the device under test Y, and configured on a first semiconductor substrate A and a second semiconductor substrate B. Of the device under test Y and the test circuit X, only the device under test Y is configured on the second semiconductor substrate B, while the test circuit X is configured on the first semiconductor substrate A. The test circuit X and the device under test Y are configured separately on different semiconductor substrates. This prevents the OCMT 9 from constricting the area where the product circuits Aa and Ba are configured. Furthermore, the OCMT 9 is configured by utilizing free space on each of the first semiconductor substrate A and the second semiconductor substrate B where circuits such as product circuits are not yet formed. This allows the OCMT 9 to be configured while preventing the area where the product circuits Aa and Ba are configured from being constricted.

[0032] Furthermore, since the semiconductor chip 2 according to the first embodiment of the present technology has the above-described configuration, it is possible to prevent the area occupied by the OCMT 9 on the second semiconductor substrate B from becoming too large, compared to when both the test circuit X and the device under test Y are provided on the second semiconductor substrate B. This prevents the area on the second semiconductor substrate B where the product circuit Ba is configured from being compressed. More specifically, if the chip size is the same, it is possible to prevent the area on the second semiconductor substrate B where the product circuit Ba is configured from becoming insufficient. Furthermore, even when the area where the product circuit Ba is configured is secured, it is possible to prevent the chip size from becoming large.

[0033] Furthermore, since the semiconductor chip 2 according to the first embodiment of the present technology has the above-described configuration, there is more space in the second semiconductor substrate B, allowing the number of devices under test Y to be increased. This allows various types of devices under test Y to be arranged, and a wider variety of measurement items to be adopted. This also allows the number of devices under test Y of the same type to be increased, thereby improving the reliability of the test.

[0034] Furthermore, since the semiconductor chip 2 according to the first embodiment of the present technology has the above-described configuration, it is possible to reduce the design burden on the company to which production is outsourced and also to prevent technology from leaking to the company to which production is outsourced.

[0035] Furthermore, in the semiconductor chip 2 according to the first embodiment of the present technology, the OCMT 9 has a measurement pad 14A that is electrically connected to the test circuit X and is provided so that one surface thereof is exposed. Therefore, when performing a test, it is possible to perform a test on a plurality of devices under test Y without moving the probes of the testing equipment.

[0036] Furthermore, in the semiconductor chip 2 according to the first embodiment of the present technology, a plurality of devices under test Y are configured on the second semiconductor substrate B, and includes a selection circuit X1 that selects some of the plurality of devices under test Y, a switch X2 that switches between the devices under test Y, etc. Any device under test Y can be selected by the selection circuit X1 and the switch X2, so that it is possible to test the plurality of devices under test Y without moving the probes of the inspection equipment.

[0037] Furthermore, in the semiconductor chip 2 according to the first embodiment of the present technology, a second semiconductor substrate B on which a device under test Y is formed is bonded to and overlapped with a first semiconductor substrate A on which a test circuit X is formed. Therefore, the length of the wiring L2 can be shortened compared to when the first semiconductor substrate A and the second semiconductor substrate B are provided side-by-side. This reduces the electrical resistance between the test circuit X and the device under test Y, thereby suppressing power consumption. Furthermore, by arranging the test circuit X and the device under test Y so that they overlap in a planar view, the area occupied by the OCMT 9 can be prevented from becoming too large in a planar view.

[0038] Furthermore, the semiconductor chip 2 according to the first embodiment of the present technology has the OCMT 9 instead of the scribe TEG, so that testing can be performed even after singulation. Furthermore, with the scribe TEG, wiring may be extended from the scribe pad to connect to a test circuit, and the wiring must be arranged so as to pass through the guard ring arranged on the periphery of the semiconductor chip 2 without destroying it. In contrast, in the semiconductor chip 2 according to the first embodiment of the present technology, the OCMT 9 is not arranged on the scribe line and is entirely contained within the chip, so it is less likely to affect the guard ring.

[0039] <Modification of First Embodiment> Modifications of the first embodiment will be described below.

[0040] <Modification 1> In the semiconductor chip 2 according to the first embodiment, as shown in FIG. 2, the measurement pads 14A are provided on the first semiconductor substrate A, but the present technology is not limited to this. In a semiconductor chip 2 according to Modification 1 of the first embodiment shown in FIG. 9, the measurement pads 14A are provided on the second semiconductor substrate B. The wiring L1 is provided across the first semiconductor substrate A and the second semiconductor substrate B. As shown in FIG. 10, the semiconductor chip 2 according to this modification can be mounted on an interposer P to test a device under test Y. The interposer P is a substrate on which electrical wiring is routed. When the semiconductor chip 2 is mounted on the interposer P, the measurement pads 14A come into contact with the upper surface terminals Pa of the interposer P.

[0041] The semiconductor chip 2 according to the first modification of the first embodiment also provides the same effects as the semiconductor chip 2 according to the first embodiment described above.

[0042] Furthermore, in the semiconductor chip 2 according to the first modification of the first embodiment, the semiconductor chip 2 is mounted on the interposer P and tested on the device under test Y, which makes the inspection easier.

[0043] In the above-described modified example, the individual semiconductor chips 2 are mounted on the interposer P and tested on the device Y to be measured, but it is also possible to mount the wafer before being individualized on the interposer P and test the device Y to be measured.

[0044] <Modification 2> Although the semiconductor chip 2 according to the first embodiment includes a single second semiconductor substrate B as shown in Fig. 2, the present technology is not limited to this. The semiconductor chip 2 according to Modification 2 of the first embodiment shown in Fig. 11 includes a plurality of second semiconductor substrates B. That is, the plurality of second semiconductor substrates B are aligned in a plan view and bonded to the first semiconductor substrate A.

[0045] 11 shows an example in which the semiconductor chip 2 includes two second semiconductor substrates B1 and B2, but the number of second semiconductor substrates included in the semiconductor chip 2 may be three or more. One surface of each of the second semiconductor substrates B1 and B2 is bonded to and overlaps the first surface S1 of the first semiconductor substrate A. When the second semiconductor substrate B1 and the second semiconductor substrate B2 are not distinguished from each other, they are simply referred to as the second semiconductor substrate B. The second semiconductor substrates B1 and B2 have a similar configuration to the second semiconductor substrate B.

[0046] A product circuit B1a is configured on the second semiconductor substrate B1, and a product circuit B2a is configured on the second semiconductor substrate B2. The product circuit B1a may be the same type of electrical circuit as the product circuit B2a, or a different type of electrical circuit. While not limited to this, for example, the product circuit B1a may be a memory circuit such as a DRAM, and the product circuit B2a may be an SoC circuit such as an artificial intelligence or CPU. Wiring L is provided within the semiconductor chip 2, forming connection wiring for various circuits. The product circuit B1a and the product circuit Aa, and the product circuit B2a and the product circuit Aa, are connected by wiring L.

[0047] A plurality of devices under test Y are configured on each of the second semiconductor substrates B1 and B2. To distinguish between the devices under test Y configured on the second semiconductor substrate B1 and the devices under test Y configured on the second semiconductor substrate B2, the devices under test Y configured on the second semiconductor substrate B1 are referred to as devices under test Ya and Yb, respectively. When there is no need to distinguish between the devices under test Ya and Yb, they are simply referred to as devices under test Y. The OCMT 9 includes the devices under test Ya and Yb. The device under test Ya and the test circuit X are connected by wiring L21, and the device under test Yb and the test circuit X are connected by wiring L22. When there is no need to distinguish between the wiring L21 and the wiring L22, they are simply referred to as wiring L2. The device under test Ya is an element of the same type as the element to be tested, among the elements included in the product circuit B1a. The device under test Yb is an element of the same type as the element to be tested, among elements included in the product circuit B2a.

[0048] The test circuit X has a function of selecting a device under test Y formed on one of the plurality of second semiconductor substrates B1, B2 and performing a test on the selected device under test Y. For example, the test circuit X selects one of a device under test Ya formed on the second semiconductor substrate B1 and a device under test Yb formed on the second semiconductor substrate B2. The test circuit X selects the device under test Y by using at least one of a selection circuit X1 and a switch X2.

[0049] The semiconductor chip 2 according to the second modification of the first embodiment also provides the same effects as the semiconductor chip 2 according to the first embodiment described above.

[0050] Furthermore, the semiconductor chip 2 according to the second modification of the first embodiment includes a plurality of second semiconductor substrates B, and the test circuit X has a function of selecting a device under test Y formed on any one of the plurality of second semiconductor substrates B and performing a test on the selected device under test Y. In this way, one test circuit X is shared by a plurality of devices under test Y provided on a plurality of second semiconductor substrates B, so there is no need to provide a plurality of test circuits X for the first semiconductor substrate A, and it is possible to prevent the area on the first semiconductor substrate A where the product circuits Aa are formed from being compressed.

[0051] <Modification 3> Although the semiconductor chip 2 according to the first embodiment includes a single first semiconductor substrate A as shown in Fig. 2, the present technology is not limited to this. The semiconductor chip 2 according to Modification 3 of the first embodiment shown in Fig. 12 includes a plurality of first semiconductor substrates A. That is, a plurality of first semiconductor substrates A are stacked and bonded in the thickness direction.

[0052] 12 shows an example in which the semiconductor chip 2 includes two first semiconductor substrates A1 and A2, but the number of first semiconductor substrates included in the semiconductor chip 2 may be three or more. The first semiconductor substrate A2 is bonded to and overlaps the second surface S2 of the first semiconductor substrate A1, which is the surface opposite to the first surface S1. When the first semiconductor substrate A1 and the first semiconductor substrate A2 are not distinguished from each other, they will be simply referred to as the first semiconductor substrate A.

[0053] A product circuit A1a is configured on the first semiconductor substrate A1, and a product circuit A2a is configured on the first semiconductor substrate A2. The product circuit A1a may be the same type of electrical circuit as the product circuit A2a, or a different type of electrical circuit. For example, but not limited to, both the product circuit A1a and the product circuit A2a are logic circuits. Wiring L is provided within the semiconductor chip 2, forming connection wiring for various circuits. The product circuit Ba and the product circuit A1a, and the product circuit A1a and the product circuit A2a are connected by wiring L.

[0054] The test circuit X is configured on one of the multiple first semiconductor substrates A. For example, the test circuit X is configured only on the first semiconductor substrate A2 out of the first semiconductor substrate A1 and the first semiconductor substrate A2. Which semiconductor substrate among the multiple first semiconductor substrates A the test circuit X is provided on may be determined, for example, according to the technology node of the semiconductor substrate. For example, if the first semiconductor substrate A2 is the substrate with high performance, the area occupied by the test circuit X can be reduced by configuring the test circuit X on the first semiconductor substrate A2. The wiring L2 is provided from the first semiconductor substrate A2 to the second semiconductor substrate B, and electrically connects the test circuit X and the device under test Y.

[0055] The semiconductor chip 2 according to the third modification of the first embodiment also provides the same effects as the semiconductor chip 2 according to the first embodiment described above.

[0056] <Modification 4> In the semiconductor chip 2 according to Modification 3 of the first embodiment, as shown in Fig. 12, the test circuit X is configured on one of the multiple first semiconductor substrates A, but the present technology is not limited to this. In the semiconductor chip 2 according to Modification 4 of the first embodiment shown in Fig. 13, the test circuits X are provided in a distributed manner on the multiple first semiconductor substrates A.

[0057] 13 shows an example in which the semiconductor chip 2 includes two first semiconductor substrates, namely, first semiconductor substrates A1 and A2. The test circuit X is, for example, distributed across the first semiconductor substrate A1 and the first semiconductor substrate A2. The portion of the test circuit X configured on the first semiconductor substrate A1 is referred to as the test circuit Xa, and the portion of the test circuit X configured on the first semiconductor substrate A2 is referred to as the test circuit Xb, to distinguish them from each other. When the test circuits Xa and Xb are not distinguished from each other, they are simply referred to as the test circuit X. The test circuits Xa and Xb may also be collectively referred to as the test circuit X. The OCMT 9 includes a wiring L1 electrically connecting the test circuit Xb and the measurement pad 14A, a wiring L3 electrically connecting the test circuit Xb and the test circuit Xa, and a wiring L2 electrically connecting the test circuit Xa and the device under test Y.

[0058] The semiconductor chip 2 according to this fourth modification of the first embodiment also achieves the same effects as the semiconductor chip 2 according to the third modification of the first embodiment. Furthermore, in the semiconductor chip 2 according to the fourth modification of the first embodiment, the test circuits X are distributed across multiple first semiconductor substrates A, which prevents the area occupied by the test circuits X on each of the first semiconductor substrates A1 and A2 from becoming too large. This further prevents the test circuits X from constricting the areas in which the product circuits A1a and A2a are configured.

[0059] <Modification 5> In the method for manufacturing the semiconductor chip 2 according to the first embodiment, the semiconductor chip 2 is formed by CoW as shown in Fig. 4, but the present technology is not limited to this. In the method for manufacturing the semiconductor chip 2 according to Modification 5 of the first embodiment shown in Fig. 14, the semiconductor chip 2 is formed by WoW.

[0060] First, a first semiconductor wafer WA and a second semiconductor wafer WB are prepared (step S201), and the second semiconductor wafer WB is bonded to the prepared first semiconductor wafer WA (step S202). Then, a test is performed using an OCMT 9 (step S203). The process of step S203 is similar to the process of step S104 already described, and therefore will not be described again. Then, for each substrate portion that will become a semiconductor chip 2 after singulation, it is determined whether the test results of the device under test Y satisfy a reference value (step S204). Substrate portions that are determined to satisfy the reference value (step S204, YES) are sequentially processed until the final product is produced (step S205). Substrate portions that are determined not to satisfy the reference value (step S204, NO) are not processed until the final product is produced. Note that the test results for substrate portions that are determined not to satisfy the reference value are fed back to the manufacturing process up to that point (step S206).

[0061] The semiconductor chip 2 according to the fifth modification of the first embodiment also provides the same effects as the semiconductor chip 2 according to the first embodiment described above.

[0062] Furthermore, in the semiconductor chip 2 according to variant 5 of the first embodiment, an OCMT is configured instead of a scribe TEG, so that even if the semiconductor chip 2 is formed by WoW, testing can be performed using the OCMT 9 after individualization.

[0063] Second Embodiment A second embodiment of the present technology will be described below, which is shown in Figures 15 to 19. In this embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described. That is, the semiconductor device 1 is a photodetector device.

[0064] <Overall Configuration of Semiconductor Device> First, the overall configuration of a semiconductor device 1, which is a photodetector, will be described. As shown in Fig. 15 , the semiconductor device 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plane. That is, the semiconductor device 1 is mounted on the semiconductor chip 2. As shown in Fig. 23 , the semiconductor device 1 captures image light (incident light 106) from an object via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0065] As shown in FIG. 15 , the semiconductor chip 2 on which the semiconductor device 1 is mounted includes, in a two-dimensional plane including the X direction and the Y direction which intersect with each other, a square-shaped pixel region 2A provided in the center, and a peripheral region 2B provided outside the pixel region 2A so as to surround the pixel region 2A.

[0066] The pixel region 2A is a light receiving surface that receives light collected by, for example, the optical system 102 shown in FIG. 23 . In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that intersect with each other within the two-dimensional plane. In this embodiment, as an example, the X direction and the Y direction are orthogonal to each other. Furthermore, the direction orthogonal to both the X direction and the Y direction is the Z direction (thickness direction, stacking direction). Furthermore, the direction perpendicular to the Z direction is the horizontal direction.

[0067] 15, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0068] 16, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0069] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0070] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 12.

[0071] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0072] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0073] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0074] 17 is an equivalent circuit diagram showing an example of the configuration of a pixel 3. The pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion) FD that accumulates (holds) signal charges photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion element PD to the charge accumulation region FD. The pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0075] The photoelectric conversion element PD generates a signal charge according to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0076] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD, and the gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 16).

[0077] The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0078] The readout circuit 15 reads out the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are made of, for example, a silicon oxide film (SiO ２ These transistors are configured as MOSFETs having a gate insulating film made of silicon nitride (Si nitride), a gate electrode, and a pair of main electrode regions that function as a source region and a drain region. ３ N ４ Alternatively, the readout circuit 15 may be a MISFET (Metal Insulator Semiconductor FET) made of a silicon nitride (SiN) film or a stacked film of a silicon nitride film and a silicon oxide film. The readout circuit 15 may be provided for each photoelectric conversion element PD, or one readout circuit 15 may be shared by multiple photoelectric conversion elements PD. Similarly, the charge accumulation region FD may be provided for each photoelectric conversion element PD, or one charge accumulation region FD may be shared by multiple photoelectric conversion elements PD.

[0079] The amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0080] The select transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL), a drain electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a select transistor drive line among the pixel drive lines 10 (see FIG. 16 ).

[0081] The reset transistor RST has a source region electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 16 ).

[0082] <<Specific Configuration of Semiconductor Chip>> Next, a specific configuration of the semiconductor chip 2 on which the semiconductor device 1 is mounted will be described with reference to FIGS.

[0083] <Stacked Structure of Semiconductor Chip> As shown in FIG. 18 , the semiconductor chip 2 includes a first semiconductor substrate A, a third semiconductor substrate C bonded to the second surface S2 of the first semiconductor substrate A, and two second semiconductor substrates, namely, second semiconductor substrates B1 and B2. The first surface S1 and the second surface S2 are one and the other surfaces of the first semiconductor substrate A. FIG. 19 shows a longitudinal cross-sectional configuration of a portion of the pixel region 2A and the peripheral region 2B. For example, a color filter Ft and a microlens (on-chip lens) Lz are provided on one side of the third semiconductor substrate C. The color filter Ft separates light incident on the semiconductor chip 2 into different colors. The color filter Ft may be a filter for red light, a filter for green light, or a filter for blue light. The microlens Lz focuses light incident on the semiconductor chip 2 onto the pixel 3. The color filter Ft and the microlens Lz are made of, for example, a resin material.

[0084] <Third Semiconductor Substrate> The third semiconductor substrate C is an example of a third semiconductor substrate. The third semiconductor substrate C has a semiconductor layer 20C and a multilayer wiring layer 30C stacked on the other side of the semiconductor layer 20C. A product circuit Ca is configured in a portion of the third semiconductor substrate C corresponding to the pixel region 2A. The product circuit Ca is an example of a third product circuit, and includes the photoelectric conversion element PD shown in FIG. 17. The product circuit Ca includes the transfer transistor TR, charge storage region FD, readout circuit 15, etc. shown in FIG. 17 in the portion of the third semiconductor substrate C corresponding to the pixel region 2A.

[0085] The semiconductor layer 20C is formed of a semiconductor substrate. The semiconductor layer 20C is formed of, for example, a silicon (Si) substrate, although not limited thereto. A portion of the semiconductor layer 20C corresponding to the pixel region 2A is provided with a plurality of pixels 3 arranged in a matrix along the row direction (X direction) and column direction (Y direction) in a plan view. The semiconductor layer 20C includes, for example, a first conductivity type (e.g., p-type) semiconductor region and a second conductivity type (e.g., n-type) semiconductor region. A photoelectric conversion element PD is formed in the semiconductor layer 20C for each pixel 3. The photoelectric conversion element PD performs photoelectric conversion, generating signal charges according to the amount of received light. The test circuit X is not formed on the third semiconductor substrate C.

[0086] The multilayer wiring layer 30C is, but is not limited to, a multilayer wiring layer having, for example, an insulating film and wiring L provided in the insulating film. The insulating film may be made of, for example, silicon oxide (SiO ２ , SiO) film, silicon nitride (Si ３ N ４ The multilayer wiring layer 30A1 has a structure in which multiple layers of known insulating films such as silicon nitride (SiN) films and silicon oxynitride (SiON) films are stacked. The wiring L is made of a known conductive material such as a metal material such as copper (Cu), tungsten (W), or aluminum (Al). This structure also applies to the multilayer wiring layers 30A1, 30A2, and 30B described below.

[0087] <First Semiconductor Substrate> The first semiconductor substrate A has a semiconductor layer 20A, a multilayer wiring layer 30A1 stacked on one side of the semiconductor layer 20A and overlapping and joined to the multilayer wiring layer 30C, and a multilayer wiring layer 30A2 stacked on the other side of the semiconductor layer 20A. Wiring L is provided in the multilayer wiring layers 30A1 and 30A2. A product circuit Aa is configured in a portion of the first semiconductor substrate A corresponding to the pixel region 2A. The product circuit Aa includes, for example, a logic circuit 13. The semiconductor layer 20A is configured from a semiconductor substrate. The semiconductor layer 20A is configured from, for example, a silicon (Si) substrate, although not limited thereto.

[0088] <Second Semiconductor Substrate> The semiconductor chip 2 includes multiple second semiconductor substrates B, i.e., second semiconductor substrates B1 and B2. When the second semiconductor substrates B1 and B2 are not distinguished from each other, they are simply referred to as second semiconductor substrates B. The second semiconductor substrate B includes a semiconductor layer 20B and a multilayer wiring layer 30B stacked on one side of the semiconductor layer 20B and bonded to a multilayer wiring layer 30A2. Wiring L is provided in the multilayer wiring layer 30B. A product circuit B1a is configured on the second semiconductor substrate B1, and a product circuit B2a is configured on the second semiconductor substrate B2. The product circuit B1a includes a memory circuit such as a DRAM, and the product circuit B2a includes, for example, SoC circuits such as artificial intelligence and a CPU. The semiconductor layer 20B is configured, for example, but is not limited to, a silicon (Si) substrate.

[0089] <Through conductor> The semiconductor chip 2 includes a through conductor TSV that penetrates the semiconductor layer 20A in the thickness direction. The through conductor TSV is also part of the wiring L. The through conductor TSV electrically connects the wiring L provided in the multilayer wiring layer 30A1 and the wiring L provided in the multilayer wiring layer 30A2. The through conductor TSV is also part of the wiring L. The semiconductor chip 2 may include a through conductor TSV that penetrates the semiconductor layer 20B or the semiconductor layer 20C in the thickness direction.

[0090] <Connection Pads> The semiconductor chip 2 includes multiple pairs of connection pads CCa and CCb. The connection pads CCa and CCb are also part of the wiring L. In some of the multiple pairs, the connection pads CCa and CCb contact each other across the bonding surface between the first semiconductor substrate A and the second semiconductor substrate B, electrically connecting the wiring L provided in the multilayer wiring layer 30A2 to the wiring L provided in the multilayer wiring layer 30B. In other of the multiple pairs, the connection pads CCa and CCb contact each other across the bonding surface between the first semiconductor substrate A and the third semiconductor substrate C, electrically connecting the wiring L provided in the multilayer wiring layer 30A1 to the wiring L provided in the multilayer wiring layer 30C.

[0091] <OCMT> The test circuit X and measurement pads 14A of the OCMT 9 are provided on a first semiconductor substrate A, and the device under test Y is provided on a second semiconductor substrate B. The wiring L2 connecting the test circuit X and the device under test Y includes a through conductor TSV and a pair of connection pads CCa, CCb. The test circuit X and the device under test Y are electrically connected via the through conductor TSV and the pair of connection pads CCa, CCb.

[0092] <<Major Effects of Second Embodiment>> The semiconductor chip 2 according to the second embodiment also provides the same effects as the semiconductor chip 2 according to the first embodiment described above.

[0093] Although the third semiconductor substrate C includes only one semiconductor layer 20C, it may include two semiconductor layers. In this case, the photoelectric conversion element PD and the readout circuit 15 may be formed separately in one and the other of the two semiconductor layers.

[0094] <Modification of Second Embodiment> A modification of the second embodiment will now be described.

[0095] 19 , in the semiconductor chip 2 according to the second embodiment, the measurement pads 14A are provided on the first semiconductor substrate A, but the present technology is not limited to this. In the semiconductor chip 2 according to the first modification of the second embodiment, the measurement pads 14A may be provided on the second semiconductor substrate B or the third semiconductor substrate C.

[0096] 20 , the measurement pad 14A is provided on the third semiconductor substrate C. The wiring L1 is provided across the first semiconductor substrate A and the third semiconductor substrate C. The wiring L1 includes a through conductor TSV (not shown) and a pair of connection pads CCa and CCb. The test circuit X and the measurement pad 14A are electrically connected via the through conductor TSV and the pair of connection pads CCa and CCb.

[0097] 21 , the measurement pad 14A is provided on the second semiconductor substrate B. The wiring L2 is provided across the first semiconductor substrate A and the second semiconductor substrate B. The wiring L1 includes a through conductor TSV (not shown) and a pair of connection pads CCa and CCb. The test circuit X and the measurement pad 14A are electrically connected via the through conductor TSV and the pair of connection pads CCa and CCb.

[0098] The semiconductor chip 2 according to the first modification of the second embodiment also provides the same effects as the semiconductor chip 2 according to the second embodiment described above.

[0099] <Variation 2> In the semiconductor chip 2 according to Variation 2 of the second embodiment shown in FIG. 22, a single test circuit X is shared by a plurality of devices under test Y provided on a plurality of second semiconductor substrates B, as in the case of Variation 2 of the first embodiment shown in FIG.

[0100] The semiconductor chip 2 according to the second modification of the second embodiment also provides the same effects as the semiconductor chip 2 according to the second embodiment described above.

[0101] <Modification 3> In a semiconductor chip 2 according to Modification 3 of the second embodiment, the test circuit X may be configured on a third semiconductor substrate C, although not shown.

[0102] The semiconductor chip 2 according to the third modification of the second embodiment also provides the same effects as the semiconductor chip 2 according to the second embodiment described above.

[0103] Third Embodiment A third embodiment of the present technology will be described below. In this embodiment, the semiconductor chip 2 according to the first embodiment described above includes a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor. More specifically, the first semiconductor substrate A described in the first embodiment and its modifications 1 and 2 includes a photoelectric conversion element PD, similar to the third semiconductor substrate C. That is, the product circuit Aa has a configuration similar to the product circuit Ca. Furthermore, the first semiconductor substrate A2 described in modifications 3 and 4 of the first embodiment includes a photoelectric conversion element PD, similar to the third semiconductor substrate C. That is, the product circuit A2a has a configuration similar to the product circuit Ca.

[0104] The semiconductor chip 2 according to the third embodiment also provides the same effects as the semiconductor chip 2 according to the first embodiment.

[0105] [Fourth Embodiment] <1. Application Example to Electronic Device> Next, an electronic device 100 according to a fourth embodiment of the present technology shown in Fig. 23 will be described. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes, as the solid-state imaging device 101, a semiconductor chip 2 on which the above-described photodetector is mounted.

[0106] An optical lens (optical system) 102 focuses image light (incident light 106) from a subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. A shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. A drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Signal transfer from the solid-state imaging device 101 is performed in accordance with the drive signal (timing signal) supplied from the drive circuit 104. A signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0107] The electronic device 100 is not limited to a camera, but may be other electronic devices, such as an imaging device such as a camera module for a mobile device such as a mobile phone.

[0108] Furthermore, the electronic device 100 can be provided with, as the solid-state imaging device 101, a photodetector according to any one of the second embodiment to the third embodiment and the modified versions of these embodiments, or a photodetector according to a combination of at least two of the second embodiment to the third embodiment and the modified versions of these embodiments.

[0109] [Other Embodiments] As described above, the present technology has been described by the first to fourth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0110] For example, it is possible to combine the respective technical concepts described in the first to fourth embodiments. For example, Modifications 3 and 4 of the first embodiment relating to a plurality of first semiconductor substrates A may be combined with Modification 2 of the first embodiment relating to a plurality of second semiconductor substrates B. In this way, various combinations according to the respective technical concepts are possible.

[0111] Furthermore, this technology can be applied to photodetection devices in general, including not only the solid-state imaging device as the image sensor described above but also distance measurement sensors that measure distance, also known as ToF (Time of Flight) sensors. A distance measurement sensor emits light toward an object, detects the light reflected by the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until when the reflected light is received. The above-described structure can be adopted as the structure of this distance measurement sensor.

[0112] Furthermore, for example, the materials cited as constituting the above-mentioned components may contain additives, impurities, and the like.

[0113] As such, the present technology naturally includes various embodiments not described herein. Therefore, the technical scope of the present technology is defined only by the invention-specifying matters described in the claims that are appropriate from the above description.

[0114] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0115] The present technology may be configured as follows: (1) A semiconductor chip comprising: a first semiconductor substrate having a first circuit configured thereon; a second semiconductor substrate having a second circuit configured thereon and bonded to a first surface of the first semiconductor substrate; and a test element group having a device under test and a test circuit for testing the device under test, the test element group being configured on the first semiconductor substrate and the second semiconductor substrate, wherein the second semiconductor substrate is configured with only the device under test out of the device under test and the test circuit, and the first semiconductor substrate is configured with the test circuit. (2) The semiconductor chip according to (1), wherein the device under test is provided on an element-by-element basis. (3) The semiconductor chip according to (1) or (2), wherein the test element group has a measurement pad electrically connected to the test circuit and provided so that one surface is exposed. (4) The semiconductor chip according to (3), wherein the measurement pad is provided on the first semiconductor substrate or the second semiconductor substrate. (5) The semiconductor chip according to any one of (1) to (4), wherein a plurality of the devices under test are configured on the second semiconductor substrate, and the test circuit includes a selection circuit that selects some of the plurality of devices under test and has a function of performing a test on the selected device under test. (6) The semiconductor chip according to any one of (1) to (4), wherein a plurality of the devices under test are configured on the second semiconductor substrate, and the test circuit includes a switch that switches between the devices under test and has a function of performing a test on the switched device under test. (7) The semiconductor chip according to any one of (1) to (6), wherein the device under test is a capacitor, and the test circuit includes an oscillator circuit that tests the capacitance of the capacitor. (8) The semiconductor chip according to any one of (1) to (6), wherein the device under test is a transistor or a resistor. (9) The semiconductor chip according to any one of (1) to (8), comprising a plurality of the second semiconductor substrates.(10) The semiconductor chip according to (9), wherein the test circuit has a function of selecting the device under test configured on any one of the plurality of second semiconductor substrates and performing a test on the selected device under test. (11) The semiconductor chip according to (9) or (10), wherein the second circuits configured on each of the plurality of second semiconductor substrates are different types of electric circuits. (12) The semiconductor chip according to any one of (1) to (11), wherein the semiconductor chip includes a plurality of the first semiconductor substrates, the plurality of first semiconductor substrates being bonded to one another in an overlapping manner, and the test circuit is configured on at least one of the plurality of first semiconductor substrates. (13) The semiconductor chip according to any one of (1) to (12), wherein the first circuit and the second circuit are different types of electric circuits. (14) The semiconductor chip according to any one of (1) to (13), wherein the semiconductor chip includes a third semiconductor substrate on which a photoelectric conversion element is configured and bonded to a surface opposite to the first surface of the first semiconductor substrate. (15) The semiconductor chip according to (14), comprising a through conductor and a pair of connection pads, wherein the through conductor penetrates a semiconductor layer included in any of the first semiconductor substrate to the third semiconductor substrate in a thickness direction, wherein each pad of the pair of connection pads is in contact with each other across a bonding surface between the first semiconductor substrate and the second semiconductor substrate or a bonding surface between the first semiconductor substrate and the third semiconductor substrate, and wherein the test circuit and the device under test are electrically connected via at least one of the through conductor and the pair of connection pads. (16) The semiconductor chip according to (14) or (15), comprising a measurement pad electrically connected to the test circuit and provided so that one surface is exposed, wherein the measurement pad is provided on the first semiconductor substrate, the second semiconductor substrate, or the third semiconductor substrate.(17) An electronic device comprising: a semiconductor chip; and an optical system that forms an image light from a subject on the semiconductor chip, wherein the semiconductor chip comprises: a first semiconductor substrate on which a first circuit is formed; a second semiconductor substrate on which a second circuit is formed and which is bonded to a first surface of the first semiconductor substrate in a superimposed manner; and a test element group having a device under test and a test circuit that tests the device under test and which is formed on the first semiconductor substrate and the second semiconductor substrate, wherein only the device under test out of the device under test and the test circuit is formed on the second semiconductor substrate, and the test circuit is formed on the first semiconductor substrate.

[0116] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0117] 2 Semiconductor chip 14A Measurement pad 20A, 20B, 20C Semiconductor layer 100 Electronic device 102 Optical system A, A1, A2 First semiconductor substrate AMP Transistor B, B1, B2 Second semiconductor substrate C Third semiconductor substrate CCa, CCb Connection pad PD Photoelectric conversion element S1 First surface TSV Through conductor X, Xa, Xb Test circuit X1 Selection circuit X2 Switch X3 Oscillator circuit Y, Ya, Yb Device under test Y1 Transistor Y2 Capacitor Y3 Resistance element

Claims

1. A semiconductor chip comprising: a first semiconductor substrate on which a first circuit is formed; a second semiconductor substrate on which a second circuit is formed and which is bonded to a first surface of the first semiconductor substrate in a superimposed manner; and a test element group having a device under test and a test circuit for testing the device under test, the test element group being formed on the first semiconductor substrate and the second semiconductor substrate, wherein of the device under test and the test circuit, only the device under test is formed on the second semiconductor substrate, and the test circuit is formed on the first semiconductor substrate.

2. The semiconductor chip according to claim 1, wherein the device under test is provided on an element-by-element basis.

3. The semiconductor chip according to claim 1, wherein the test element group has a measurement pad electrically connected to the test circuit and provided with one surface exposed.

4. The semiconductor chip according to claim 3, wherein the measurement pad is provided on the first semiconductor substrate or the second semiconductor substrate.

5. The semiconductor chip according to claim 1, wherein a plurality of devices under test are configured on the second semiconductor substrate, and the test circuit includes a selection circuit that selects some of the plurality of devices under test, and has a function of performing a test on the selected device under test.

6. The semiconductor chip according to claim 1, wherein a plurality of devices under test are configured on the second semiconductor substrate, and the test circuit includes a switch for switching between the devices under test and has a function of performing a test on the device under test that has been switched over.

7. The semiconductor chip according to claim 1, wherein the device under test is a capacitor, and the test circuit includes an oscillator circuit that tests the capacitance of the capacitor.

8. The semiconductor chip according to claim 1, wherein the device under test is a transistor or a resistor element.

9. The semiconductor chip according to claim 1, comprising a plurality of said second semiconductor substrates.

10. The semiconductor chip according to claim 9, wherein the test circuit has a function of selecting the device under test formed on any one of the plurality of second semiconductor substrates and performing a test on the selected device under test.

11. The semiconductor chip according to claim 9, wherein the second circuits formed on each of the plurality of second semiconductor substrates are different types of electric circuits.

12. The semiconductor chip according to claim 1, comprising a plurality of the first semiconductor substrates, the plurality of first semiconductor substrates being stacked and bonded to one another, and the test circuit being configured on at least one of the plurality of first semiconductor substrates.

13. The semiconductor chip according to claim 1, wherein the first circuit and the second circuit are different types of electric circuits.

14. The semiconductor chip according to claim 1, further comprising a third semiconductor substrate having a photoelectric conversion element formed thereon and bonded to a surface of the first semiconductor substrate opposite to the first surface.

15. The semiconductor chip described in claim 14, comprising a through conductor and a pair of connection pads, the through conductor penetrating in a thickness direction through a semiconductor layer included in any one of the first semiconductor substrate to the third semiconductor substrate, each pad of the pair of connection pads being in contact with each other across a bonding surface between the first semiconductor substrate and the second semiconductor substrate or a bonding surface between the first semiconductor substrate and the third semiconductor substrate, and the test circuit and the device under test being electrically connected via at least one of the through conductor and the pair of connection pads.

16. The semiconductor chip according to claim 14, further comprising a measurement pad electrically connected to the test circuit and having one surface exposed, the measurement pad being provided on the first semiconductor substrate, the second semiconductor substrate, or the third semiconductor substrate.

17. An electronic device comprising: a semiconductor chip; and an optical system that forms an image light from a subject on the semiconductor chip, wherein the semiconductor chip comprises: a first semiconductor substrate on which a first circuit is formed; a second semiconductor substrate on which a second circuit is formed and which is bonded to and overlaid on a first surface of the first semiconductor substrate; and a test element group having a device under test and a test circuit that tests the device under test, the test element group being formed on the first semiconductor substrate and the second semiconductor substrate, wherein only the device under test of the device under test and the test circuit are formed on the second semiconductor substrate, and the test circuit is formed on the first semiconductor substrate.

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