Information processing device, control method for same, and program

Abstract

Provided is an information processing device comprising: an integrated circuit; and a bus connected to the integrated circuit. The integrated circuit comprises: a bus controller that controls communication via a bus and transitions to any of a plurality of states including an active state in which communication is possible and a power saving state in which communication is restricted; and a monitoring circuit that records history data of communication via the bus at a prescribed time interval. On the basis of the history data of the communication recorded by the monitoring circuit, it is estimated whether communication occurs at a future estimation target time point, and when it is estimated that the estimation result communication occurs, the bus controller is transitioned to the active state.

Description

Information processing device, control method thereof, and program

[0001] The present invention relates to an information processing device including an integrated circuit and a bus, a control method therefor, and a control program therefor.

[0002] Generally, an integrated circuit built into an information processing device is connected to a bus, and communication is performed with other integrated circuits and external information processing devices via this bus.

[0003] The bus controller that controls communication via the bus described above may have a function to reduce overall power consumption by transitioning to a low-power (inactive) state when communication is not required. However, such a function may cause a delay in communication when returning from a power-saving state, or may not be able to effectively reduce power consumption depending on the frequency of communication.

[0004] The present invention has been made in consideration of the above-mentioned circumstances, and one of its objects is to provide an information processing device, a control method thereof, and a control program thereof that can efficiently realize communication via a bus.

[0005] An information processing device according to one embodiment of the present invention is an information processing device comprising an integrated circuit and a bus connected to the integrated circuit, wherein the integrated circuit comprises a bus controller that controls communication via the bus and transitions to one of a number of states including an active state in which communication is possible and a power saving state in which communication is restricted, and a monitoring circuit that records historical data of communication via the bus at predetermined intervals, and the integrated circuit estimates whether communication will occur at a future target time point based on the historical data of communication recorded by the monitoring circuit, and if the estimation indicates that communication will occur, transitions the bus controller to the active state.

[0006] A control method for an information processing device according to one embodiment of the present invention is a control method for an information processing device comprising an integrated circuit and a bus connected to the integrated circuit, the integrated circuit comprising a bus controller that controls communication via the bus and transitions to one of a plurality of states including an active state in which communication is possible and a power saving state in which communication is restricted, and a monitoring circuit that records historical data of communication via the bus at predetermined intervals, wherein the integrated circuit estimates whether communication will occur at a future estimation target time based on the historical data of communication recorded by the monitoring circuit, and if the estimation results in an estimate that communication will occur, transitions the bus controller to the active state.

[0007] According to one aspect of the present invention, there is provided a program for controlling an information processing device including an integrated circuit and a bus connected to the integrated circuit, the integrated circuit including a bus controller that controls communication via the bus and transitions between a plurality of states including an active state in which communication is possible and a power-saving state in which communication is restricted, and a monitoring circuit that records history data of communication via the bus at predetermined time intervals, the program causing the integrated circuit to execute a process of estimating whether communication will occur at a future estimation target time point based on the communication history data recorded by the monitoring circuit, and transitioning the bus controller to the active state if it is estimated that communication will occur as a result of the estimation. This program may be provided by being stored on a computer-readable, non-transitory information storage medium.

[0008] It is a configuration block diagram showing an example of the configuration of an information processing device according to an embodiment of the present invention. It is a diagram showing an example of data stored in a history buffer. It is a diagram for explaining an example of a method for estimating whether or not communication will occur at an estimation target time in this embodiment. It is a flow diagram showing an example of the flow of control executed by a subchip. It is a time chart explaining an example when data is stored in three types of history buffers.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] 1 is a block diagram showing an example of the configuration of an information processing device 10 according to one embodiment of the present invention. The information processing device 10 may be a home game console, a portable information terminal, a personal computer, or the like, and as shown in the figure, includes a main chip 20, a sub-chip 30, a bus 41, a main memory 51, a USB interface 52 which is a communication interface based on the USB (registered trademark) standard, and an Ethernet interface 53 which is a communication interface based on the Ethernet (registered trademark). The sub-chip 30 in this embodiment is an example of an integrated circuit according to the present invention.

[0011] The main chip 20 is an integrated circuit incorporating a processor for executing the main information processing for realizing the functions of the information processing device 10. The sub-chip 30 is an integrated circuit incorporating a processor for realizing auxiliary functions for the main chip 20, and is implemented as an integrated circuit independent of the main chip 20. The main chip 20 and the sub-chip 30 are connected by a bus 41, and are capable of transmitting and receiving data to and from each other via this bus 41.

[0012] 1, the main chip 20 incorporates a main processor unit 21, a bus controller 22, a memory controller 23, and a DMA controller 24. The main chip 20 may incorporate various circuits other than those shown here. It may also be provided with an interface for connecting to other electronic components not shown.

[0013] The main processor unit 21 is a processor that performs various arithmetic operations according to programs stored in the main memory 51 .

[0014] The bus controller 22 is a control circuit for controlling communication with the sub-chip 30 via the bus 41 .

[0015] The bus 41 is a bus for mutual data communication between the main chip 20 and the sub-chip 30. Here, the bus 41 is a bus for data communication based on the PCI Express (registered trademark) standard, but the embodiment of the present invention is not limited to this.

[0016] The memory controller 23 is a control circuit connected to the main memory 51 and controls access to the main memory 51. The DMA controller 24 is a control circuit for realizing direct memory access. These circuits may all be realized by known techniques.

[0017] In this embodiment, the sub-chip 30 incorporates a microcontroller 31, a bus controller 32, a monitoring circuit 33, a USB controller 34, an Ethernet controller 35, an internal memory 36, a DMA controller 37, and a timer 38. The sub-chip 30 may incorporate various circuits other than those shown here. It may also be provided with an interface for connecting to other electronic components not shown.

[0018] The microcontroller 31 is a processor for controlling the overall operation of the subchip 30, and performs various arithmetic processing in accordance with programs stored in the internal memory 36 or the like.

[0019] The bus controller 32 is a control circuit for controlling communication with the main chip 20 via the bus 41. As described above, the bus controller 32 performs communication in accordance with the PCI Express standard.

[0020] In this embodiment, the bus controller 32 controls the transition of its own state to reduce power consumption. Specifically, the bus controller 32 transitions to one of multiple states depending on the situation. These multiple states include an active state in which communication with the main chip 20 is possible, and a power-saving state in which communication is restricted but consumes less power than the active state. By transitioning to the power-saving state when communication with the main chip 20 is not being performed, the bus controller 32 can reduce power consumption compared to when it always operates in the active state. If a communication request to the main chip 20 occurs while the bus controller 32 has transitioned to the power-saving state, the bus controller 32 transitions to the active state and, after the transition is complete, transmits the requested data to the main chip 20.

[0021] The monitoring circuit 33 monitors and records the status of communication via the bus controller 32. Specifically, the monitoring circuit 33 monitors at predetermined time intervals whether communication has taken place within that time interval, and records communication history data indicating the results in a pre-prepared data buffer (hereinafter referred to as the history buffer). The contents of the recorded communication history data are referenced by the microcontroller 31 and used to control the bus controller 32. Details of the contents recorded by the monitoring circuit 33 and specific examples of control using those contents will be described later.

[0022] The USB controller 34 is a control circuit connected to the USB interface 52 and performs data communication with a USB device connected to the information processing device 10 via the USB interface 52 .

[0023] The Ethernet controller 35 is a control circuit connected to the Ethernet interface 53 and executes data communication with network devices connected to the information processing device 10 via the Ethernet interface 53 .

[0024] The internal memory 36 stores some of the programs executed by the microcontroller 31 and the main processor unit 21 of the main chip 20. In particular, the microcontroller 31 may execute various control processes in accordance with the programs stored in the internal memory 36.

[0025] The DMA controller 37 is a control circuit for realizing direct memory access. The timer 38 is an electronic circuit for realizing a timekeeping function. These circuits may all be realized by known techniques.

[0026] An example of the flow of data transfer from the sub chip 30 to the main chip 20 in this embodiment will be described below. As a specific example, a case will be described in which a packet from the USB interface 52 is stored in the main memory 51 via the sub chip 30 and the main chip 20. First, a data packet to be transmitted is stored in the data buffer of the USB controller 34 of the sub chip 30. In response to this, the USB controller 34 starts data transfer by direct memory access.

[0027] At this time, if the bus controller 32 is in the active state, the data transfer continues via the bus controller 32. However, if the bus controller 32 is in the power-saving state, the bus controller 32 first receives a data transfer request and transitions from the power-saving state to the active state. Once the transition is complete, the data transfer is executed. After the data transfer is complete, and a certain period of time has elapsed, the bus controller 32 transitions again to the power-saving state, as described above.

[0028] A certain amount of time is required to transition from the power-saving state to the active state. Hereinafter, the time required to transition from the power-saving state to the active state will be referred to as the recovery time Tx. While this transition is taking place, data waiting to be transmitted is stored in the data buffer of the USB controller 34.

[0029] The USB standard supports isochronous transfer, which transfers data at fixed intervals. If a USB data transfer request occurs every 125 μs and the recovery time Tx is 70 μs, there is only a 55 μs grace period before the next packet arrives via isochronous transfer. Therefore, if the next packet arrives before the data transfer from the USB controller 34 is completed due to other data communication occurring simultaneously, the data transfer may not be completed in time, resulting in packet loss. Furthermore, when a data transfer fails, a retransmission is typically attempted after a fixed time. However, if the bus controller 32 transitions to the power-saving state again during this time, the retransmission must wait for the bus controller 32 to return to the active state, potentially resulting in repeated data transfer failures.

[0030] Therefore, in this embodiment, the microcontroller 31 predicts the timing when the next data transfer is expected to occur using the monitoring results from the monitoring circuit 33, and causes the bus controller 32 to transition to the active state in advance based on the prediction results. This makes it possible to shorten the wait time for data transfer and reduce the possibility of packet loss compared to when transition to the active state is made after a data transfer request is actually generated.

[0031] Specifically, the monitoring circuit 33 sequentially records, in the history buffer, communication history data indicating whether or not communication has occurred within a predetermined unit time Δt, where Δt indicates the period during which the monitoring circuit 33 records communication history data indicating whether or not communication has occurred.

[0032] The history buffer in which the monitoring circuit 33 stores the communication history data may be a data buffer of a predetermined size prepared in advance, which functions as a queue in which the oldest information is deleted as new information is added. This allows communication history data indicating the timing of data communications over the most recent past predetermined period to be constantly recorded.

[0033] FIG. 2 is a diagram illustrating the transition of data recorded in the history buffer. For illustrative purposes, the history buffer is simplified in this diagram and is assumed to be a right shift register capable of storing eight data items. In the diagram, a value of "1" stored in the history buffer indicates a state in which data communication is occurring, and a value of "-1" indicates a state in which data communication is not occurring. The top row of the diagram shows the contents of the history buffer at time t(N), the middle row shows the contents at time t(N+1), and the bottom row shows the contents at time t(N+2). Here, N, N+1, N+2, etc. represent the values ​​(integer values) of a time counter that is incremented each time a unit time Δt elapses.

[0034] In this example, the value of the history buffer at time t(N) indicates that data communication occurred at past times t(N-1), t(N-2), ..., t(N-8), in the order of none, none, none, none, yes, yes, yes, yes, yes. Communication occurred at time t(N), and in response, a "1" representing the state at time t(N) is stored at the left end of the history buffer at time t(N+1). Accordingly, past data is shifted one by one to the right, and the data for t(N-8) stored at the right end at time t(N) is discarded at time t(N+1). The contents of the history buffer are similarly updated from time t(N+1) to time t(N+2). As a result, at time t(N+2), the history buffer contains communication history data representing the communication states at times t(N+1), t(N), t(N-1), ..., t(N-6), starting from the left end.

[0035] Using the contents of the history buffer thus recorded, the microcontroller 31 estimates the communication status at a future time. Specifically, the microcontroller 31 estimates whether communication will occur via the bus 41 within the recovery time Tx from the present time. If the bus controller 32 is currently in the power saving state and it is estimated that communication will occur in the future, the microcontroller 31 executes control to restore the bus controller 32 to the active state.

[0036] For example, the microcontroller 31 estimates, every time a unit time Δt elapses, whether or not communication will occur at a time (estimated target time) after a return time Tx has elapsed from the current time. If it is estimated that communication will occur at the estimated target time, the microcontroller 31 immediately generates an interrupt requesting the bus controller 32 to return to the active state. This allows the bus controller 32 to return to the active state when the estimated target time actually arrives.

[0037] Furthermore, if the bus controller 32 is currently in the active state and it is estimated that no communication will occur from the present time until the recovery time Tx has elapsed, the microcontroller 31 may control the bus controller 32 to transition to the power-saving state. As a result, if it is estimated that no communication will occur for the time being, the bus controller 32 can be transitioned to the power-saving state without waiting for a predetermined waiting time.

[0038] A specific example of a method for estimating whether communication will occur at a target time point will be described with reference to FIG. 3 . For example, the microcontroller 31 performs estimation using an estimation model based on a simple perceptron. In this case, the same number of weights w as the number of data items stored in the history buffer are prepared as parameters used by the estimation model. For example, in the example history buffer of FIG. 2 , eight weights w1, w2, ..., w8 are prepared corresponding to eight data items. Using these eight weights w, the microcontroller 31 multiplies the value of the first data item (+1 or -1) in the history buffer by w1, the second data item by w2, and so on, and adds up the resulting values ​​to obtain an output value. If this output value is a positive number, it is estimated that communication will occur, and if it is a number less than or equal to 0, it is estimated that communication will not occur. This output value can be calculated with a computational effort on the order of O(n), where n is the number of data items. Therefore, estimation can be performed with a relatively small computational load even when the number of data items stored in the history buffer is increased.

[0039] If the estimation result is subsequently incorrect (i.e., if there is a discrepancy between the estimation result and the actual communication state), the microcontroller 31 corrects the weight value at that time using a given learning rate. In this way, by repeating the learning process of correcting the parameters used by the estimation model when the estimation result is incorrect, even if the estimation fails at first, the accuracy of the estimation gradually improves, and it becomes possible to estimate the presence or absence of communication with high accuracy in situations where communication is occurring periodically. Since accuracy can be improved by reflecting the learning results in this way, the initial value of the weight w when the information processing device 10 is started up may be a predetermined fixed value or a randomly determined value.

[0040] Here, estimation is performed every unit time Δt, but the microcontroller 31 may perform estimation every time a predetermined time longer than the unit time Δt has elapsed. In any case, the microcontroller 31 stores data indicating the estimation result every time estimation is performed for a period corresponding to the recovery time Tx. By referencing this stored estimation result data, it is possible to determine whether communication is estimated to occur between the present time and the time when the recovery time Tx has elapsed. Furthermore, when the target estimation time actually arrives, it is possible to verify whether the estimation was correct by referring to the stored estimation result, and to reflect the verification result in the learning process.

[0041] An example of the flow of control executed by the sub-chip 30 in this embodiment will be described below with reference to the flowchart in Fig. 4. In this example, C is a predetermined constant, and estimation is performed every time C times the unit time Δt has elapsed.

[0042] When a link is established between the main chip 20 and the sub-chip 30 via the bus 41 (S1), the following flow is steadily executed every unit time Δt until the link is disconnected.

[0043] First, the monitoring circuit 33 records new communication history data indicating whether or not there is currently data communication via the bus 42 in the history buffer (S2). The bus controller 32 then controls the state transition according to the current state. Specifically, if the current state is a power-saving state (S3) and there is data waiting to be transmitted (S4), the bus controller 32 immediately initiates a transition to the active state (S5). This transition is necessary when the estimation based on the communication history is incorrect and unexpected communication occurs.

[0044] Thereafter, the value of the time counter is incremented, and it is determined whether the value of the time counter has reached an integer multiple of a predetermined constant C. This is a determination of whether a time equivalent to C·Δt has elapsed since the previous determination was Yes and the estimation process described below was performed (S6). If the predetermined time has not yet elapsed, the process waits for the unit time Δt to elapse, and then returns to S2, and the loop is repeated.

[0045] If it is determined that the time corresponding to C·Δt has elapsed, the process branches depending on the current state of the bus controller 32 (S7).

[0046] If the bus controller 32 is currently in the active state, it is determined whether communication is expected to occur at a future time point (S8). If this determination indicates that communication will not occur at the future time point and there is no data to be transmitted at present (S9), the bus controller 32 transitions to a power-saving state (S10). Conversely, if communication is expected to occur at a future time point, there is no need to transition the state. Furthermore, if there is data to be transmitted at present, it is obviously not possible to transition to a power-saving state.

[0047] On the other hand, even if the bus controller 32 is currently in the power saving state, it is determined whether communication is estimated to occur at a future estimated time (S11). If it is determined that communication will occur at a future estimated time, a transition to the active state is initiated (S13). Also, if there is currently data to be transmitted (S12), a transition to the active state is initiated (S13). Conversely, if there is currently no data to be transmitted and it is estimated that communication will not occur until a future estimated time, there is no need to transition the state.

[0048] Thereafter, the microcontroller 31 updates the weight w in accordance with the result of comparing the past estimation result with the presence or absence of actual data communication at present (S14). After the unit time Δt has elapsed, the process returns to S2 and repeats the loop process.

[0049] This type of control continuously estimates whether communication will occur in the future, transitions the state of the bus controller 32 according to the estimation result, and if the estimation is incorrect, a learning process can be used to improve the estimation accuracy from the next time onwards.

[0050] Next, an example of performing estimation control using multiple types of history buffers will be described. Here, it is assumed that multiple types of data transfer requests occur at different cycles. As an example, a data transfer request via the USB interface 52 occurs every 1000 μs (=1 ms), and a transfer request via the Ethernet interface 53 occurs every 200 μs. Note that transfers via the Ethernet interface 53 generally include a combination of periodically occurring transfers, such as video and audio, and asynchronous transfers. However, here, a periodically occurring transfer request will be considered.

[0051] In the above explanation, communication history data is stored in a single type of history buffer with a fixed size. In this case, to estimate the timing of data transfers that occur in a 1 ms cycle, a history buffer large enough to store communication history data for a period longer than this cycle is required. Assuming that the unit time Δt is 10 μs and the presence or absence of data transfers is recorded every Δt, a history buffer capable of holding at least 100 pieces of data is required to hold communication history for a period longer than 1 ms. Furthermore, if transfer requests with longer cycles are expected, for example, to accommodate transfer requests with a 16.6 ms cycle, a history buffer capable of holding more than 1,660 pieces of data is required. Increasing the number of pieces of data that can be stored in the history buffer not only increases the size of the history buffer, but also increases the number of parameters (weights) required to estimate the presence or absence of communication, resulting in an increase in the amount of calculation required for the estimation.

[0052] By lengthening the unit time Δt, which is the period for recording whether or not a data transfer has occurred, it is possible to store a long-term communication history with a smaller number of history buffers. However, if the unit time Δt is lengthened, it becomes difficult to predict data transfers with a relatively short period. For example, to predict the timing of data communication that occurs every 200 μs, the unit time Δt must be sufficiently shorter than 200 μs.

[0053] Therefore, the monitoring circuit 33 may be provided with multiple types of history buffers that record communication history data at different time intervals. Here, as a specific example, an example in which communication history is recorded using three types of history buffers will be described. Below, the three types of history buffers are referred to as History Buffer 1, History Buffer 2, and History Buffer 3, and the time intervals at which data is recorded in these buffers are referred to as unit times Δt1, Δt2, and Δt3, respectively. Here, Δt1<Δt2<Δt3.

[0054] Every time a unit time Δt1 elapses, the monitoring circuit 33 records communication history data indicating the presence or absence of communication via the bus 41 during that unit time Δt1 in history buffer 1. In parallel with this, every time a unit time Δt2 elapses, the monitoring circuit 33 records data indicating the presence or absence of communication during that unit time Δt2 in history buffer 2. Similarly, every time a unit time Δt3 elapses, the monitoring circuit 33 records data indicating the presence or absence of communication during that unit time Δt3 in history buffer 3. These history buffers each function independently as first-in, first-out queues, so that whenever new data is added, the oldest data in the same history buffer is discarded.

[0055] For example, let Δt1 = 1 μs, Δt2 = 50 μs, and Δt3 = 1000 μs, and each history buffer stores a maximum of 300 pieces of data. In this case, history buffer 1 records communication history data for the past 300 μs at 1 μs intervals. Similarly, history buffer 2 records communication history data for the past 15 ms at 50 μs intervals, and history buffer 3 records communication history data for the past 300 ms at 1000 μs (= 1 ms) intervals. This allows communication history data for up to the past 300 ms to be recorded, while keeping the total number of data items recorded in the history buffers to 900.

[0056] The microcontroller 31 uses the data stored in each of these three types of history buffers to estimate whether data communication will occur at a future estimation time point. The timing of this estimation may be determined based on the timing at which target data is recorded in each history buffer. For example, the microcontroller 31 may perform an estimation using the data stored in history buffer 1 at each unit time Δt1, an estimation using the data stored in history buffer 2 at each unit time Δt2, and an estimation using the data stored in history buffer 3 at each unit time Δt3. If any of the estimations indicates that future communication will occur, the microcontroller 31 controls the bus controller 32 to return from the power saving state to the active state.

[0057] Furthermore, the microcontroller 31 may perform estimation based on these communication history data recorded at different cycles, targeting different estimation target times. In the explanation above, it was assumed that the bus controller 32 takes only two states: an active state and one power-saving state, and the estimation target time was set to a time in the future by the recovery time Tx required to return from the power-saving state to the active state. However, the bus controller 32 may have multiple states in which it operates in a power-saving mode. These power-saving states have different power consumptions, and generally, the lower the power consumption of a state, the longer the recovery time required to return from that state to the active state.

[0058] As a specific example, the bus controller 32 is assumed to be capable of operating in one of three power-saving states. Hereinafter, the three power-saving states will be referred to as power-saving state 1, power-saving state 2, and power-saving state 3, and the times required to return from these states to the active state will be referred to as recovery times Tx1, Tx2, and Tx3, respectively. Here, Tx1<Tx2<Tx3. That is, power-saving state 1 allows the bus controller 32 to return to the active state the fastest, but consumes more power than the other power-saving states.

[0059] In this example, the microcontroller 31 may control the transition to each of the multiple power-saving states using the results of estimation based on communication history data stored in the corresponding one of the multiple history buffers. Specifically, when estimation is performed using communication history data recorded over a relatively short period of time, it is possible to predict the immediate future, but it is difficult to accurately predict the distant future. Therefore, when determining whether to transition to a power-saving state that can transition to the active state in a relatively short recovery time Tx, it is appropriate to use the results of estimation performed using a history buffer in which communication history data is recorded over a short period of time. Conversely, to control the transition to a power-saving state with a long recovery time Tx, it is desirable to use the results of estimation using communication history data recorded over a relatively long period of time.

[0060] Therefore, based on the communication history data recorded in history buffer 1, the microcontroller 31 estimates whether communication will occur, setting a future estimation target time point that is the time when recovery time Tx1 has elapsed from the current time point. If the bus controller 32 is currently in the active state, the microcontroller 31 determines whether to transition to power saving state 1 based on the results of this estimation. That is, if the estimation using the communication history data in history buffer 1 predicts that no communication will occur between the current time point and the time when recovery time Tx1 has elapsed, the microcontroller 31 transitions the bus controller 32 to power saving state 1. Similarly, the microcontroller 31 uses the communication history data in history buffer 2 to estimate a time point that is the time when recovery time Tx2 has elapsed from the current time point, and controls transition to power saving state 2 based on the estimation result. Furthermore, based on the communication history data in history buffer 3, the microcontroller 31 uses the communication history data in history buffer 3 to estimate a time point that is the time when recovery time Tx3 has elapsed from the current time point, and controls transition to power saving state 3 based on the estimation result.

[0061] To effectively perform this estimation, it is preferable to determine the time interval for recording communication history data in each history buffer based on the recovery time Tx required for transitioning from each power-saving state to the active state. That is, the cycle for storing communication history data in each history buffer (i.e., unit time periods Δt1, Δt2, and Δt3) is determined so that communication history data can be recorded at intervals sufficiently shorter than the recovery time Tx from the corresponding power-saving state. This allows for effective estimation processing for future estimation target points corresponding to the recovery time Tx from each power-saving state. The monitoring circuit 33 may also determine the cycle for recording communication history data in each history buffer by referring to values ​​stored in registers or the like. In this way, the microcontroller 31 can dynamically change the cycle for recording communication history data by updating the register values ​​based on, for example, the operating status of the information processing device 10 and the contents of the communication history.

[0062] Furthermore, when controlling transitions to power-saving states using these multiple types of communication history data, priority may be given to control using communication history data recorded at relatively long time intervals. That is, if it is determined that transitions to multiple power-saving states are possible based on the estimation results of the communication history data in each history buffer, the transition to the power-saving state with the lowest power consumption is performed. For example, if the estimation results based on the communication history data in each of history buffers 1, 2, and 3 predict that no communication will occur within the estimation period, the bus controller 32 is transitioned to power-saving state 3. This further reduces power consumption by the bus controller 32.

[0063] If the estimation based on the communication history data in any of the history buffers indicates that communication will occur after the corresponding recovery time Tx has elapsed, the microcontroller 31 must transition to the active state according to that timing. Therefore, regardless of priority, if any estimation indicates that communication will occur, the microcontroller 31 transitions the bus controller 32 to the active state.

[0064] FIG. 5 is a diagram illustrating a specific example of communication history data stored in the three types of history buffers described above. In this example, data communication occurs every 1000 μs via the USB controller 34, taking 300 μs per communication. Data communication occurs every 200 μs via the Ethernet controller 35, taking 40 μs per communication. History buffers 1, 2, and 3 record communication history data at 1 μs, 50 μs, and 1000 μs intervals, respectively. For simplicity, time t0 is set as the current time, and the communication history data for the past 10 communication sessions is recorded. In this example, a value of "1" indicates that data communication has occurred in the communication history data stored in the history buffer, and a value of "0" indicates that data communication has not occurred. The shaded areas in the diagram represent older communication history data that has been discarded after more than 10 sessions.

[0065] In the example shown in this figure, the communication history data stored in history buffer 3 indicates that communication is always occurring. Therefore, it is considered that transition control to power saving state 3 will not be performed based on the communication history data in history buffer 3 at this time. On the other hand, since there is a time period in which no communication occurs for a maximum of 160 μs, there is a time period in which communication history data indicating no communication occurs in history buffer 2, which records communication history data in a shorter unit time of 50 μs. Depending on the timing of the estimation, it may be determined that transition control to power saving state 2 is performed. Furthermore, even if it is determined that transition to power saving state 2 is not possible based on the communication history data in history buffer 2, transition control to power saving state 1 is performed if it is estimated that no communication will occur for the recovery time Tx1 based on the communication history data in history buffer 1. As a result, if it is estimated that returning to the active state within the recovery time Tx2 will not be possible in time, power consumption can be reduced by transitioning the bus controller 32 to power saving state 1, which allows return to the active state within the shorter recovery time Tx1.

[0066] As described above, the information processing device 10 according to this embodiment estimates whether or not communication will occur at a future time point based on communication history data recorded at predetermined time intervals, and controls the bus controller 32 to transition to the active state based on the estimation result, thereby reducing the waiting time during which communication is not possible until the state transition is complete.Furthermore, by controlling the bus controller 32 to transition to the power-saving state based on the estimation result, power consumption by the bus controller 32 can be further reduced.

[0067] The embodiments of the present invention are not limited to those described above, and various modifications are possible. For example, the number of types of power-saving states, the number of history buffers, and the value of the unit time Δt, which is the period for storing data in the history buffer, are all examples, and may be various values ​​depending on the specifications of the actual bus controller. Furthermore, the method described above for estimating whether communication will occur at a future time point using communication history data is also merely an example, and estimation may be performed using a different method.

[0068] In the above description, the microcontroller 31 in the subchip 30 executes a pre-prepared control program to estimate whether communication has occurred based on communication history data and to control the transition of the bus controller 32 based on the estimation results. However, in this embodiment, some or all of the control executed by the microcontroller 31 may be realized by a control circuit implemented as hardware. In this case, the control circuit performs the estimation process based on a fixed algorithm, but various parameters required for the operation may be stored in registers or the like and updated as needed. This allows the processing content to be changed depending on conditions, even when the control circuit that performs the estimation process is implemented as hardware.

[0069] In the above description, the bus 41 connects the sub-chip 30 and the main chip 20 so that data can be communicated between them and is used for communication between these chips. However, the bus in the present invention is not limited to this and may be, for example, a bus for connecting an information processing device and an external device. Even in this case, when the bus controller that controls communication via the bus transitions to the active state or the power-saving state, the monitoring circuit monitors the communication and obtains communication history data to estimate whether communication will occur at a future estimation target time point. By controlling the state of the bus controller based on the estimation result, the waiting time for returning to the active state can be reduced.

[0070] 10 Information processing device, 20 Main chip, 21 Main processor unit, 22 Bus controller, 23 Memory controller, 25 DMA controller, 30 Subchip, 31 Microcontroller, 32 Bus controller, 32 Monitoring circuit, 34 USB controller, 35 Ethernet controller, 36 Internal memory, 37 DMA controller, 38 Timer, 41 Bus, 51 Main memory, 52 USB interface, 53 Ethernet interface.

Claims

1. An information processing device comprising an integrated circuit and a bus connected to the integrated circuit, wherein the integrated circuit comprises: a bus controller that controls communication via the bus and transitions to one of a number of states including an active state in which communication is possible and a power saving state in which communication is restricted; and a monitoring circuit that records historical data of communication via the bus at predetermined time intervals, wherein the integrated circuit estimates whether or not communication will occur at a future estimation target time point based on the historical data of communication recorded by the monitoring circuit, and if it is estimated as a result of the estimation that communication will occur, transitions the bus controller to the active state.

2. An information processing device according to claim 1, wherein said integrated circuit transitions said bus controller to said power saving state when it is estimated from said estimation result that no communication will occur until said estimation target time.

3. An information processing device according to claim 1, wherein the estimation target time point is determined according to a time required for the bus controller to transition from the power saving state to the active state.

4. An information processing device according to claim 1, wherein the integrated circuit executes the estimation based on an estimation model that uses given parameters, and executes a learning process to correct the parameters if the result of the estimation is incorrect.

5. An information processing device according to claim 1, wherein the monitoring circuit records history data of a plurality of types of communication at different time intervals, and the integrated circuit performs the estimation using each of the history data of the plurality of types of communication.

6. An information processing device according to claim 5, wherein the integrated circuit estimates whether or not a communication will occur at different estimation target times using each of the history data of the plurality of types of communication.

7. An information processing device according to claim 6, wherein the bus controller transitions to one of a plurality of states including a plurality of power saving states each having a different power consumption, and the integrated circuit transitions the bus controller to one of the plurality of power saving states based on a result of the estimation using each of the history data of the plurality of types of communication.

8. An information processing device according to claim 7, wherein the estimation target time point at which the estimation is performed using each of the multiple types of communication history data is determined based on the time required for the bus controller to transition from each of the multiple power saving states to the active state.

9. A method for controlling an information processing device comprising an integrated circuit and a bus connected to the integrated circuit, the integrated circuit comprising: a bus controller that controls communication via the bus and transitions to one of a number of states including an active state in which communication is possible and a power saving state in which communication is restricted; and a monitoring circuit that records historical data of communication via the bus at predetermined time intervals, wherein the integrated circuit estimates whether communication will occur at a future estimated time point based on the historical data of communication recorded by the monitoring circuit, and if it is estimated as a result of the estimation that communication will occur, transitions the bus controller to the active state.

10. A program for controlling an information processing device comprising an integrated circuit and a bus connected to the integrated circuit, the integrated circuit comprising: a bus controller that controls communication via the bus and transitions to one of a number of states including an active state in which communication is possible and a power saving state in which communication is restricted; and a monitoring circuit that records history data of communication via the bus at predetermined time intervals, the program causing the integrated circuit to execute a process of estimating whether or not communication will occur at a future estimation target time point based on the communication history data recorded by the monitoring circuit, and transitioning the bus controller to the active state if it is estimated as a result of the estimation that communication will occur.

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