Display panel and preparation method therefor

Abstract

Provided in the present application are a display panel and a preparation method therefor. A thin-film transistor comprises a gate electrode, an active layer, a source electrode and a drain electrode, and a photodetector comprises a first electrode, a photodetection layer and a second electrode. The active layer is located on the side of the gate electrode facing away from a substrate, the photodetection layer is located on the side of the first electrode facing away from the substrate, the second electrode is located on the side of the photodetection layer away from the first electrode, and the gate electrode and the first electrode are arranged in the same layer and comprise the same material.

Description

Display panel and manufacturing method thereof Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Art

[0002] Photodetectors have broad application prospects in areas such as cameras, computer vision, human-computer interaction, touchless touchscreens, and smart screens with recognition capabilities. However, photodetectors typically require integration with transistor technology to achieve signal addressing and processing. As the most mature technology in the display industry, amorphous silicon transistors have attracted widespread attention due to their advantages such as small layout requirements, stable process, and low cost.

[0003] However, the photodetector is integrated on top of the amorphous silicon transistor, that is, the photodetector and the amorphous silicon transistor are stacked in the direction perpendicular to the substrate, which often requires the cost of 4-5 more masks, thus becoming a huge bottleneck limiting its application. SUMMARY OF THE INVENTION

[0004] The purpose of this application is to provide a display panel and a method for manufacturing the same, aiming to reduce the number of masks used for integrating thin film transistors and photodetectors, thereby reducing process costs.

[0005] In one aspect, the present application provides a display panel, comprising:

[0006] substrate,

[0007] The thin film transistor and the photodetector are arranged on the same side of the substrate and adjacent to each other in a direction parallel to the substrate;

[0008] The thin film transistor includes a gate, an active layer located on the side of the gate facing away from the substrate, and a source electrode and a drain electrode spaced apart on the active layer; the photodetector includes a first electrode, a photodetection layer located on the side of the first electrode facing away from the substrate, and a second electrode located on the side of the photodetection layer facing away from the first electrode;

[0009] The gate and the first electrode are arranged in the same layer and comprise the same material.

[0010] In some embodiments, a top-view pattern of the second electrode is the same as a top-view pattern of the photodetection layer.

[0011] In some embodiments, the first electrode includes a protrusion extending from the photodetection layer in a direction close to the gate, and the display panel further includes:

[0012] a first extraction electrode connected to the protruding portion of the first electrode through a first via hole;

[0013] The second lead-out electrode is connected to the second electrode through a second via hole.

[0014] In some embodiments, the display panel further comprises:

[0015] a dielectric layer covering the second electrode, the protrusion of the first electrode, and the gate;

[0016] a protective layer, covering the dielectric layer, the source electrode and the drain electrode;

[0017] The first via hole and the second via hole both penetrate the dielectric layer and the protective layer.

[0018] In some embodiments, the display panel further comprises:

[0019] a pixel electrode connected to the source electrode through a third via hole, wherein the third via hole penetrates the protective layer;

[0020] The first extraction electrode, the second extraction electrode and the pixel electrode are all located on the protection layer and are arranged in the same layer.

[0021] In some embodiments, the first lead-out electrode is connected to the drain electrode through a fourth via hole, or the second lead-out electrode is connected to the drain electrode through a fourth via hole.

[0022] In some embodiments, the photodetection layer includes one of intrinsic hydrogenated amorphous silicon, phosphorus-doped hydrogenated amorphous silicon, boron-doped hydrogenated amorphous silicon, fluorine-doped amorphous silicon, or a stack of any two or three thereof.

[0023] In some embodiments, the active layer includes intrinsic hydrogenated amorphous silicon.

[0024] In another aspect, the present application provides a method for manufacturing a display panel, the method comprising:

[0025] Providing a substrate,

[0026] forming a buffer layer on the substrate;

[0027] forming a first electrode and a gate arranged in the same layer on the buffer layer using a mask;

[0028] forming a second electrode and a photodetection layer located between the second electrode and the first electrode in sequence on the first electrode by an etching process using a mask;

[0029] forming a dielectric layer covering the second electrode and the gate;

[0030] forming an active layer corresponding to the gate on the dielectric layer, and a source electrode and a drain electrode spaced apart from each other on the active layer;

[0031] forming a protective layer covering the first electrode, the source electrode, and the drain electrode;

[0032] forming a first via hole exposing the first electrode, a second via hole exposing the second electrode, a third via hole exposing the source electrode, and a fourth via hole exposing the drain electrode in the protective layer;

[0033] An electrode layer is formed on the protective layer, in the first via hole, the second via hole, the third via hole and the fourth via hole, and the electrode layer includes a first lead-out electrode connected to the first electrode, a second lead-out electrode connected to the second electrode, and a pixel electrode connected to the source electrode, and the first lead-out electrode is also connected to the drain electrode through the fourth via hole.

[0034] In some embodiments, the step of forming an active layer corresponding to the gate on the dielectric layer, and a source electrode and a drain electrode spaced apart on the active layer, comprises:

[0035] Depositing active layer materials and source / drain metal materials in sequence on the dielectric layer;

[0036] An active layer corresponding to the gate electrode and a source electrode and a drain electrode spaced apart from each other on the active layer are formed by etching using a half-tone mask. Beneficial effects

[0037] The present application provides a display panel and a method for manufacturing the same display panel. The display panel includes a substrate, and a thin-film transistor (TFT) and a photodetector (PD) disposed on the same side of the substrate, the TFT and the photodetector being adjacent in a direction parallel to the substrate. The TFT includes a gate, an active layer, a source electrode, and a drain electrode, while the photodetector includes a first electrode, a photodetection layer, and a second electrode. The active layer is located on the side of the gate facing away from the substrate, and the source and drain electrodes are located on the active layer and spaced apart. The photodetection layer is located on the side of the first electrode facing away from the substrate, and the second electrode is located on the side of the photodetection layer facing away from the first electrode. This display panel integrates the TFT and the photodetector in a direction parallel to the substrate. Compared to the stacked integration structure in the prior art, this application can simplify the structure and reduce the thickness of the display panel. The gate and the first electrode are disposed on the same layer and made of the same material, and thus can be formed together using a single mask. Compared to the process of forming a TFT, only a mask for forming the photodetection layer and the second electrode is required to integrate the photodetector and TFT, resulting in a smaller number of masks and lower process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0039] FIG1 is a schematic structural diagram of a display panel provided in some embodiments of the present application;

[0040] FIG2 is a schematic flow chart of a method for manufacturing a display panel according to some embodiments of the present application;

[0041] 3a-3d are schematic structural diagrams of the display panel during the preparation process provided by some embodiments of the present application. Modes for Carrying Out the Invention

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0043] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0044] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0045] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0046] Referring to Figure 1, which is a schematic diagram of the structure of a display panel provided in some embodiments of the present application, the display panel 100 can be applied to non-touch screens, smart screens with recognition capabilities, and the like, and has particular advantages in non-contact displays with gesture recognition capabilities.

[0047] The display panel 100 includes a substrate 10, and a thin film transistor 11 and a photodetector 12 disposed on the same side of the substrate 10. The thin film transistor 11 and the photodetector 12 are adjacent in a direction (X) parallel to the substrate 10. The photodetector 12 and the thin film transistor 11 are electrically connected to implement signal addressing and processing.

[0048] The thin film transistor 11 includes a gate 111, an active layer 112, a source electrode 113, and a drain electrode 114. The photodetector 12 includes a first electrode 121, a photodetection layer 122, and a second electrode 123. The active layer 112 is located on the side of the gate 111 facing away from the substrate 10, and the source electrode 113 and the drain electrode 114 are located on the active layer 112 and spaced apart. Therefore, the thin film transistor 11 is a bottom-gate thin film transistor. The photodetection layer 122 is located on the side of the first electrode 121 facing away from the substrate 10, and the second electrode 123 is located on the side of the photodetection layer 122 facing away from the first electrode 121.

[0049] The display panel 100 may further include a buffer layer 13 disposed on the substrate 10. The buffer layer 13 is located between the substrate 10 and the thin film transistor 11, and also between the substrate 10 and the photodetector 12. The substrate 10 may be a glass substrate, a quartz substrate, or a silicon wafer. The buffer layer 13 may be silicon nitride, silicon oxide, or a stack of silicon nitride and silicon oxide.

[0050] The gate 111 and the first electrode 121 are disposed in the same layer on the buffer layer 13. The gate 111 and the first electrode 121 may be made of the same material, for example, the gate 111 and the first electrode 121 may be made of a single metal element of molybdenum, copper, silver, aluminum, titanium, niobium, or nickel, or a molybdenum-titanium, molybdenum-niobium, or molybdenum-nickel alloy, or a combination stack of any of the above metals or alloys.

[0051] In some embodiments, the top view pattern of the second electrode 123 is the same as the top view pattern of the photodetection layer 122 , so the pattern of the second electrode 123 can be formed by an etching process using the pattern of the photodetection layer 122 , i.e., a self-alignment process, which can save a photolithography process.

[0052] The first electrode 121 can serve as a cathode, and the second electrode 123 can serve as a transparent anode. The transparent anode can be a stack of any one of the following materials or a combination thereof: tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, and aluminum indium tin zinc oxide. The photodetection layer 122 can include intrinsic hydrogenated amorphous silicon, phosphorus-doped hydrogenated amorphous silicon, boron-doped hydrogenated amorphous silicon, or fluorine-doped amorphous silicon, or a stack of any two or three thereof.

[0053] In some embodiments, the first electrode 121 includes a protrusion 1220 extending from the photodetection layer 122 in a direction close to the gate 111 , that is, the photodetection layer 122 only covers a portion of the first electrode 121 , exposing the protrusion 1220 for the extraction of the first electrode 121 .

[0054] The display panel 100 may further include a first extraction electrode 141 and a second extraction electrode 142 . The first extraction electrode 141 is connected to the protrusion 1220 of the first electrode 121 through a first via hole 1411 , and the second extraction electrode 142 is connected to the second electrode 123 through a second via hole 1420 .

[0055] The display panel 100 may further include a dielectric layer 15 and a protective layer 16. The dielectric layer 15 covers the second electrode 123, the protrusion 1220 of the first electrode 121, and the gate 111. The protective layer 16 covers the dielectric layer 15, the source electrode 113, and the drain electrode 114. The dielectric layer 15 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or scandium zirconium oxide, or a stack of any two or three thereof. The protective layer 16 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or scandium zirconium oxide, or a stack of any two or three thereof.

[0056] The first extraction electrode 141 and the second extraction electrode 142 are both located on the protection layer 16 , and the first via hole 1411 and the second via hole 1420 both penetrate the protection layer 16 and the dielectric layer 15 in sequence.

[0057] The display panel 100 may further include a pixel electrode 143 connected to the source electrode 113 via a third via hole 1430 that passes through the protective layer 16. The pixel electrode 143 is located on the protective layer 16 and is disposed on the same layer as the first extraction electrode 141 and the second extraction electrode 142.

[0058] In some embodiments, the first extraction electrode 141 is connected to the drain electrode 114 through the fourth via hole 1412 , that is, the drain electrode 114 of the thin film transistor 11 is electrically connected to the first electrode 121 serving as a cathode.

[0059] In some embodiments, the second extraction electrode 142 is connected to the drain electrode 114 through the fourth via hole 1412 , that is, the drain electrode 114 of the thin film transistor 11 is electrically connected to the second electrode 123 serving as the anode.

[0060] The display panel 100 provided in an embodiment of the present application includes a substrate 10, and a thin film transistor 11 and a photodetector 12 arranged on the same side of the substrate 10, and the thin film transistor 11 and the photodetector 12 are adjacent in a direction (X) parallel to the substrate 10. The thin film transistor 11 includes a gate 111, an active layer 112, a source 113 and a drain 114, and the photodetector 12 includes a first electrode 121, a photodetection layer 122 and a second electrode 123. Among them, the active layer 112 is located on the side of the first electrode 121 away from the substrate 10, and the source 113 and the drain 114 are located on the active layer 112 and are spaced apart. The photodetection layer 122 is located on the side of the first electrode 121 away from the substrate 10, and the second electrode 123 is located on the side of the photodetection layer 122 away from the first electrode 121. The display panel 100 realizes the integration of the thin film transistor 11 and the photodetector 12 in a direction parallel to the substrate 10. Compared with the stacked integrated structure in the prior art, the present application can simplify the structure and reduce the thickness of the display panel. Among them, the gate 111 and the first electrode 121 are arranged in the same layer and include the same material, so they can be formed together using a mask. Compared with the process of forming the thin film transistor 11 separately, it is only necessary to add a mask to form the photodetection layer 122 and the second electrode 123 to realize the integration of the photodetector 12 and the thin film transistor 11. The number of mask plates is small and the process cost is low.

[0061] Please refer to Figure 2, which is a schematic flow diagram of a method for manufacturing a display panel according to some embodiments of the present application. Please also refer to Figures 3a-3d, which are schematic structural diagrams of the display panel manufacturing process according to some embodiments of the present application. This embodiment uses the manufacturing method of the display panel 100 as an example to illustrate the manufacturing method of the display panel 100. Therefore, referring to Figures 1 and 3a-3d, the manufacturing method of the display panel 100 includes the following steps S1-S9.

[0062] Step S1: providing a substrate 10 .

[0063] Step S2: forming a buffer layer 13 on the substrate 10 .

[0064] Step S3: forming a first electrode 121 and a gate 111 on the buffer layer 13 using a mask.

[0065] As shown in Figure 3a, substrate 10 can be a glass substrate, a quartz substrate, or a silicon wafer. A buffer layer 13 is first deposited on substrate 10. A metal electrode is then deposited on buffer layer 13. The metal electrode is patterned using a mask, a photolithography process, and an etching process. One portion of the metal electrode forms the gate electrode 111 of the thin-film transistor (on the right side of Figure 1), while the other portion forms the first electrode 121 of the photodetector (on the left side of Figure 1).

[0066] The buffer layer 13 may be silicon nitride, silicon oxide, or a stack of silicon nitride and silicon oxide. The metal electrode may be a single metal of molybdenum, copper, silver, aluminum, titanium, niobium, nickel, or a molybdenum-titanium, molybdenum-niobium, or molybdenum-nickel alloy, or a stack of any of the above metals or alloys. The photolithography process may be any of extreme ultraviolet light, deep ultraviolet light, ultraviolet light, visible light, electron beam, and ion beam. The etching process may be a dry etching process, a wet etching process, or a hybrid of dry and wet etching processes.

[0067] Specifically, the dry etching process can be performed in a single gas component of chlorine, boron trichloride, hydrogen hexasulfide, carbon tetrafluoride, carbon trifluoride, nitrogen trifluoride, oxygen, argon, or nitrogen, or in a combination of any of the above gases. The wet etching process can be performed using ammonia water, sodium hydroxide, potassium hydroxide, phosphoric acid, hydrofluoric acid, nitric acid, acetic acid, hydrochloric acid, sulfuric acid, hydrogen peroxide, aqua regia solution, or a mixture of any two or three of the above.

[0068] Step S4: using a mask plate on the first electrode 121, a second electrode 123 and a photodetection layer 122 located between the second electrode 123 and the first electrode 121 are sequentially formed by an etching process.

[0069] As shown in FIG3b , a photodetection layer and a second electrode are sequentially deposited on the first electrode 121 and the gate 111 . After using a mask, a photolithography process and two etching processes, the pattern of the second electrode 123 is formed first, and then the pattern of the photodetection layer 122 is formed.

[0070] The photodetection layer 122 may be any one of intrinsic hydrogenated amorphous silicon, phosphorus-doped hydrogenated amorphous silicon, boron-doped hydrogenated amorphous silicon, fluorine-doped amorphous silicon, or a stack of any two or three of the above. The second electrode 123 may be any one of the following materials or a stack of several of the following materials: tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, and aluminum indium tin zinc oxide.

[0071] Step S5 : forming a dielectric layer 15 covering the second electrode 123 and the gate 111 .

[0072] Step S6: forming an active layer 112 corresponding to the gate 111 on the dielectric layer 15 , and a source electrode 113 and a drain electrode 114 spaced apart on the active layer 112 .

[0073] As shown in Figure 3c, a dielectric layer 15, active layer material, and source / drain metal material are successively deposited. The source / drain metal material and active layer material are patterned using a half-tone mask, a half-exposure photolithography process, and an etching process. First, source electrode 113 and drain electrode 114 are formed, followed by the patterning of active layer 112.

[0074] The dielectric layer 15 may be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or scandium zirconium oxide, or a stack of any two or three thereof. The exposure wavelength used in the semi-exposure photolithography process may be any one of extreme ultraviolet light, deep ultraviolet light, ultraviolet light, visible light, electron beam, and ion beam. The etching process may be a dry etching process, a wet etching process, or a hybrid of dry and wet etching.

[0075] Step S7 : forming a protection layer 16 covering the first electrode 121 , the source electrode 113 and the drain electrode 114 .

[0076] Step S8 : forming a first via hole 1411 exposing the first electrode 121 , a second via hole 1420 exposing the second electrode 123 , a third via hole 1430 exposing the source electrode 113 , and a fourth via hole 1412 exposing the drain electrode 114 in the protection layer 16 .

[0077] As shown in Figure 3d, a protective layer 16 is deposited on the photodetector 12 and thin-film transistor 11, covering the first electrode 121, the source electrode 113, and the drain electrode 114. A through-hole pattern (including a first via 1411, a second via 1420, a third via 1430, and a fourth via 1412) is then formed in the protective layer 16 through photolithography and etching processes. The protective layer 16 can be a single layer of silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or scandium zirconium oxide, or a stack of any two or three of these.

[0078] Step S9: An electrode layer is formed on the protective layer 16, in the first via 1411, the second via 1420, the third via 1430 and the fourth via 1412, the electrode layer including a first lead-out electrode 141 connected to the first electrode 121, a second lead-out electrode 142 connected to the second electrode 123, and a pixel electrode 143 connected to the source 113, and the first lead-out electrode 141 is also connected to the drain 114 through the fourth via 1412.

[0079] As shown in Figure 1, an electrode layer is deposited on the patterned protective layer 16. The electrode layer also fills the first via 1411, the second via 1420, the third via 1430, and the fourth via 1412. After photolithography and etching processes, the electrode layer pattern (including the first extraction electrode 141, the second extraction electrode 142, and the pixel electrode 143) is formed. The first extraction electrode 141 is connected to the first electrode 121, the second extraction electrode 142 is connected to the second electrode 123, and the pixel electrode 143 is connected to the source electrode 113. The first extraction electrode 141 is also connected to the drain electrode 114 through the fourth via 1412.

[0080] The electrode layer can be a metal electrode or a transparent oxide electrode. The metal electrode can be a single metal of molybdenum, copper, aluminum, silver, titanium, niobium, or nickel, or a molybdenum-titanium, molybdenum-niobium, or molybdenum-nickel alloy, or a laminate of any of the above metals or alloys. The transparent oxide electrode can be any of the following oxides: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, aluminum indium tin zinc oxide, zinc sulfide, barium titanate, strontium titanate, or lithium niobate.

[0081] The method for manufacturing a display panel provided in an embodiment of the present application first uses a mask to form the gate electrode 111 and the first electrode 121 arranged in the same layer, then uses a mask to form the second electrode 123 and the photodetection layer 122, then uses a mask to form the source electrode 113, the drain electrode 114, and the active layer 112, then uses a mask to form the patterned protective layer 16, and finally uses a mask to form the first extraction electrode 141, the second extraction electrode 142, and the pixel electrode 143. A total of five masks are used to form the thin film transistor 11 and the photodetector 12 adjacent in the X direction. The integration process of the two is compatible, and the layout is small, resulting in low integration process cost. In addition, compared to the separate formation process of the thin film transistor 11 (which requires four masks), only one mask is added (the mask for forming the second electrode 123 and the photodetection layer 122) to integrate the photodetector 12 with the thin film transistor 11. This integrated manufacturing method saves 3-4 masks compared to the traditional stacked integration method of the thin film transistor 11 and the photodetector 12.

[0082] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, wherein: The display panel comprises: substrate, The thin film transistor and the photodetector are arranged on the same side of the substrate and adjacent to each other in a direction parallel to the substrate; Wherein, the thin film transistor includes a gate, an active layer located on a side of the gate away from the substrate, and a source electrode and a drain electrode spaced apart on the active layer; the photodetector includes a first electrode, a photodetection layer located on a side of the first electrode away from the substrate, and a second electrode located on a side of the photodetection layer away from the first electrode; The gate and the first electrode are arranged in the same layer and include the same material.

2. The display panel according to claim 1, wherein: The top view pattern of the second electrode is the same as the top view pattern of the photodetection layer.

3. The display panel according to claim 1, wherein: The first electrode includes a protrusion extending out of the photodetection layer in a direction close to the gate, and the display panel further includes: A first lead-out electrode connected to the protruding portion of the first electrode through a first via hole; The second lead-out electrode is connected to the second electrode through a second via hole.

4. The display panel according to claim 3, wherein: The display panel further includes: a dielectric layer covering the second electrode, the protrusion of the first electrode, and the gate; A protective layer, covering the dielectric layer, the source electrode and the drain electrode; Wherein, the first via hole and the second via hole both penetrate the dielectric layer and the protective layer.

5. The display panel according to claim 4, wherein: The display panel further includes: a pixel electrode connected to the source electrode through a third via hole, wherein the third via hole penetrates the protective layer; The first lead-out electrode, the second lead-out electrode and the pixel electrode are all located on the protection layer and are arranged in the same layer.

6. The display panel according to claim 5, wherein: The first lead-out electrode is connected to the drain electrode through a fourth via hole, or the second lead-out electrode is connected to the drain electrode through a fourth via hole.

7. The display panel according to claim 1, wherein: The photoelectric detection layer includes one of intrinsic hydrogenated amorphous silicon, phosphorus-doped hydrogenated amorphous silicon, boron-doped hydrogenated amorphous silicon, fluorine-doped amorphous silicon, or a stacked layer consisting of any two or three of them.

8. The display panel according to claim 1, wherein: The active layer includes intrinsic hydrogenated amorphous silicon.

9. A method for preparing a display panel, wherein: The method for preparing the display panel includes: Providing a substrate, forming a buffer layer on the substrate; Forming a first electrode and a gate disposed in the same layer on the buffer layer using a mask; Using a mask plate on the first electrode, a second electrode and a photoelectric detection layer located between the second electrode and the first electrode are sequentially formed by an etching process; forming a dielectric layer covering the second electrode and the gate; Forming an active layer corresponding to the gate on the dielectric layer, and a source electrode and a drain electrode spaced apart on the active layer; forming a protective layer covering the first electrode, the source electrode and the drain electrode; forming a first via hole exposing the first electrode, a second via hole exposing the second electrode, a third via hole exposing the source electrode, and a fourth via hole exposing the drain electrode in the protective layer; An electrode layer is formed on the protective layer, in the first via hole, the second via hole, the third via hole and the fourth via hole, and the electrode layer includes a first lead-out electrode connected to the first electrode, a second lead-out electrode connected to the second electrode, and a pixel electrode connected to the source electrode, and the first lead-out electrode is also connected to the drain electrode through the fourth via hole.

10. The method for preparing a display panel according to claim 9, wherein: The step of forming an active layer corresponding to the gate on the dielectric layer, and a source electrode and a drain electrode spaced apart on the active layer, comprises: Depositing active layer material and source-drain metal material in sequence on the dielectric layer; An active layer corresponding to the gate electrode and a source electrode and a drain electrode spaced apart on the active layer are formed by an etching process using a half-tone mask.

11. The method for preparing a display panel according to claim 9, wherein: The top view pattern of the second electrode is the same as the top view pattern of the photodetection layer.

12. The method for preparing a display panel according to claim 9, wherein: The first electrode includes a protrusion extending out of the photodetection layer in a direction close to the gate, and the first extraction electrode is connected to the protrusion of the first electrode through the first via hole.

13. The method for preparing a display panel according to claim 9, wherein: The first extraction electrode, the second extraction electrode and the pixel electrode are all located on the protection layer and are arranged in the same layer.

14. The method for preparing a display panel according to claim 9, wherein: The photoelectric detection layer includes one of intrinsic hydrogenated amorphous silicon, phosphorus-doped hydrogenated amorphous silicon, boron-doped hydrogenated amorphous silicon, fluorine-doped amorphous silicon, or a stacked layer consisting of any two or three of them.

15. The method for preparing a display panel according to claim 9, wherein: The active layer includes intrinsic hydrogenated amorphous silicon.

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