Shift register unit, display drive circuit, and display panel

Abstract

Provided are a shift register unit, a display drive circuit, and a display panel. The shift register unit comprises an input circuit, a pull-up circuit, a pull-down circuit, a cascade output circuit and a signal output circuit, wherein the signal output circuit is connected to K clock signal ends and K output signal ends of the shift register unit and is used for generating K drive signals required for driving sub-pixels, the duty ratios of at least two output signals in the K output signal ends being different, the K drive signals comprising a gate drive signal and a light-emission control signal, and K being an integer greater than 1. At least one output unit is used for providing a signal of one of a connected clock signal end and power supply signal end to a connected output signal end under the control of a pull-up node and a pull-down node; and at least the other output unit is used for providing a signal of one of a connected clock signal end and reference signal end to a connected output signal end under the control of the pull-up node and the pull-down node.

Description

Shift register unit, display driving circuit and display panel

[0001] This application claims priority to Chinese patent application No. 2023112718801, filed on September 27, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a display driving circuit, and a display panel. Background Art

[0003] The display panel is provided with multiple sub-pixels and driving circuits for driving the sub-pixels. A single sub-pixel usually requires multiple driving signals, each of which is provided by a separate driving circuit. However, this design is not conducive to narrow bezels and low costs.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a shift register unit, comprising:

[0006] an input circuit connected to an input signal terminal of the shift register unit, and configured to input a signal from the input signal terminal to the pull-up node;

[0007] a pull-up circuit connected to the input signal terminal and a pull-down node of the shift register unit, and configured to pull up a potential of the pull-down node based on a potential of the input signal terminal;

[0008] a pull-down circuit connected to the pull-up node and the pull-down node, configured to pull down the potential of the pull-down node based on the potential of the pull-up node;

[0009] a cascade output circuit connected to the pull-up node, the pull-down node, and the power signal terminal, the reference signal terminal, and the cascade output terminal of the shift register unit, for providing a signal from one of the power signal terminal and the reference signal terminal to the cascade output terminal under the control of the pull-up node and the pull-down node; and

[0010] A signal output circuit is connected to the K clock signal terminals and the K output signal terminals of the shift register unit, and is used to generate K driving signals required to drive the sub-pixels, wherein the duty cycles of the signals output by at least two of the K output signal terminals are different, and the K driving signals include a gate driving signal and a light-emitting control signal, wherein K is an integer greater than 1.

[0011] wherein the signal output circuit comprises K output units, the kth output unit being connected to the pull-up node, the pull-down node, the kth clock signal terminal and the kth output signal terminal, wherein 1≤k≤K;

[0012] At least one of the output units is further connected to the power signal terminal, and is used to provide a signal of one of the connected clock signal terminal and the power signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node;

[0013] At least another output unit is further connected to the reference signal terminal, and is used to provide a signal from one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

[0014] For example, each output unit includes a first output subcircuit and a second output subcircuit, each of the first output subcircuit and the second output subcircuit having a control terminal, an input terminal and an output terminal and being configured to provide a signal from the input terminal to the output terminal under control of the control terminal;

[0015] in:

[0016] The control terminal of the first output sub-circuit is connected to the first pull-up node, the input terminal of the first output sub-circuit is connected to the corresponding clock signal terminal, and the output terminal of the first output sub-circuit is connected to the corresponding output signal terminal;

[0017] The control end of the second output subcircuit is connected to the pull-down node, the input end of the second output subcircuit is connected to the power signal end / or the reference signal end, and the output end of the second output subcircuit is connected to the corresponding output signal end.

[0018] For example, the first output sub-circuit includes a first transistor and a first capacitor, the gate of the first transistor serves as a control terminal of the first output sub-circuit, the first electrode of the first transistor serves as an input terminal of the first output sub-circuit, the second electrode of the first transistor serves as an output terminal of the output sub-circuit, the first electrode of the first capacitor is connected to the gate of the first transistor, and the second electrode of the first capacitor is connected to the second electrode of the first transistor;

[0019] The second output subcircuit includes a second transistor, the gate of the second transistor serves as the control terminal of the second output subcircuit, the first electrode of the second transistor serves as the input terminal of the second output subcircuit, and the second electrode of the second transistor serves as the output terminal of the second output subcircuit.

[0020] For example, one of the K clock signal terminals is electrically connected to the power signal terminal.

[0021] For example, the cascade output circuit includes:

[0022] a first cascade sub-circuit, connected to the pull-up node, the power signal terminal and the cascade output terminal, for providing a signal from the power signal terminal to the cascade output terminal under the control of the pull-up node;

[0023] The second cascade sub-circuit is connected to the pull-down node, the reference signal terminal and the cascade output terminal, and is configured to provide the signal of the reference signal terminal to the cascade output terminal under the control of the pull-down node.

[0024] For example, the first cascade sub-circuit includes a third transistor and a second capacitor, wherein the gate of the third transistor is connected to the pull-up node, the first electrode of the third transistor is connected to the power signal terminal, the second electrode of the third transistor is connected to the cascade output terminal, the first electrode of the second capacitor is connected to the gate of the third transistor, and the second electrode of the second capacitor is connected to the second electrode of the third transistor;

[0025] The second cascade sub-circuit includes a fourth transistor and a third capacitor, wherein the gate of the fourth transistor is connected to the pull-down node, the first electrode of the fourth transistor is connected to the reference signal terminal, the second electrode of the fourth transistor is connected to the cascade output terminal, the first electrode of the third capacitor is connected to the gate of the fourth transistor, and the second electrode of the third capacitor is connected to the second electrode of the fourth transistor.

[0026] For example, the second cascade sub-circuit further includes a fifth transistor and a sixth transistor,

[0027] The second electrode of the fourth transistor is connected to the cascade output terminal through the fifth transistor, wherein the first electrode of the fifth transistor is connected to the second electrode of the fourth transistor, the second electrode of the fifth transistor is connected to the cascade output terminal, and the gate of the fifth transistor is connected to the pull-down node;

[0028] A gate of the sixth transistor is connected to the cascade output terminal, a first electrode of the sixth transistor is connected to the power signal terminal, and a second electrode of the sixth transistor is connected to the pull-up node.

[0029] For example, the power signal terminal includes a first power signal terminal and a second power signal terminal, and the reference signal terminal includes a first reference signal terminal and a second reference signal terminal;

[0030] The cascade output circuit is connected to the first power signal terminal and the first reference signal terminal, and the signal output circuit is connected to the second power signal terminal and the second reference signal terminal.

[0031] For example, the pull-up circuit includes:

[0032] a first control subcircuit, connected to the input signal terminal, the power signal terminal, the second control signal terminal of the shift register unit, and an intermediate node, and configured to control a potential of the intermediate node based on signals at the input signal terminal and the second control signal terminal;

[0033] The second control subcircuit is connected to the intermediate node, the pull-down node and the first control signal terminal of the shift register unit, and is used to pull up the potential of the pull-down node based on the signals of the intermediate node and the first control signal terminal.

[0034] For example, the first control subcircuit includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is connected to the second control signal terminal, the first electrode of the seventh transistor is connected to the power signal terminal, the second electrode of the seventh transistor is connected to the intermediate node, the gate of the eighth transistor is connected to the input signal terminal, the first electrode of the eighth transistor is connected to the second control signal terminal, and the second electrode of the eighth transistor is connected to the intermediate node;

[0035] The second control subcircuit includes a ninth transistor, a tenth transistor and a fourth capacitor, the gate of the ninth transistor is connected to the intermediate node, the first electrode of the ninth transistor is connected to the first control signal terminal, the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor, the gate of the tenth transistor is connected to the first control signal terminal, the second electrode of the tenth transistor is connected to the pull-down node, the first electrode of the fourth capacitor is connected to the gate of the ninth transistor, and the second electrode of the fourth capacitor is connected to the second electrode of the ninth transistor.

[0036] For example, the first control subcircuit further includes an eleventh transistor and a twelfth transistor,

[0037] The first electrode of the eighth transistor is connected to the second control signal terminal through the eleventh transistor, the gate of the eleventh transistor is connected to the input signal terminal, the first electrode of the eleventh transistor is connected to the second control signal terminal, and the second electrode of the eleventh transistor is connected to the first electrode of the eighth transistor;

[0038] The gate of the twelfth transistor is connected to the intermediate node, the first electrode of the twelfth transistor is connected to the power signal terminal, and the second electrode of the twelfth transistor is connected to the first electrode of the eighth transistor.

[0039] For example, the pull-down circuit includes a thirteenth transistor, a gate of the thirteenth transistor is connected to the pull-up node, a first electrode of the thirteenth transistor is connected to the reference signal terminal, and a second electrode of the thirteenth transistor is connected to the pull-down node.

[0040] For example, the input circuit includes a fourteenth transistor, the gate of the fourteenth transistor is connected to the first control signal terminal of the shift register unit, the first electrode of the fourteenth transistor is connected to the input signal terminal, and the second electrode of the fourteenth transistor is connected to the pull-up node.

[0041] For example, the input circuit also includes a fifteenth transistor, the second electrode of the fourteenth transistor is connected to the pull-up node through the fifteenth transistor, wherein the gate of the fifteenth transistor is connected to the power signal terminal or the first control signal terminal, the first electrode of the fifteenth transistor is connected to the second electrode of the fourteenth transistor, and the second electrode of the fifteenth transistor is connected to the pull-up node.

[0042] For example, the shift register unit also includes: a reset circuit, which is connected to the pull-up node, the pull-down node, the power signal end, the reference signal end and the reset signal end of the shift register unit, and is used to provide the signal of the reference signal end to the pull-up node and provide the signal of the power signal end to the pull-down node under the control of the reset signal end.

[0043] For example, the reset circuit includes:

[0044] a sixteenth transistor, wherein a gate of the sixteenth transistor is connected to the reset signal terminal, a first electrode of the sixteenth transistor is connected to the reference signal terminal, and a second electrode of the sixteenth transistor is connected to the pull-up node;

[0045] A seventeenth transistor, wherein the gate of the seventeenth transistor is connected to the reset signal terminal, the first electrode of the seventeenth transistor is connected to the power signal terminal, and the second electrode of the seventeenth transistor is connected to the pull-down node.

[0046] For example, the reset circuit also includes an eighteenth transistor, the first electrode of the sixteenth transistor is connected to the reference signal terminal through the eighteenth transistor, wherein the gate of the eighteenth transistor is connected to the reset signal terminal, the first electrode of the eighteenth transistor is connected to the reference signal terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the sixteenth transistor.

[0047] For example, K=4, one or two output units are configured to provide the signal of one of the connected clock signal terminal and the power signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node, and the other output units are configured to provide the signal of one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

[0048] For example, K=3, one of the output units is configured to provide a signal from one of the connected clock signal terminal and the power signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node; the other output units are configured to provide a signal from one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

[0049] For example, the signal output circuit is used to generate a part or all of the K driving signals required to drive a single sub-pixel.

[0050] According to another aspect of the present disclosure, a display driving circuit is provided, comprising N shift register units connected in cascade, wherein the shift register units are the shift register units described above, wherein the cascade output end of the n-th stage shift register unit is connected to the input signal end of the n+i-th stage shift register unit, wherein N, n and i are all positive integers, and n<N.

[0051] For example, the display driving circuit receives M narrow clock signals and M wide clock signals that are sequentially shifted, the narrow clock signal and the wide clock signal have the same period, a duty cycle of the narrow clock signal is smaller than a duty cycle of the wide clock signal, where M is an integer multiple of K;

[0052] The N shift register units are divided into at least one group, each group comprising M shift register units connected in cascade, the M k1-th clock signal ends of each group of shift register units being configured to respectively receive the M narrow clock signals, and the M k2-th clock signal ends of each group of shift register units being configured to respectively receive the M wide clock signals, wherein k1 and k2 are positive integers, 1≤k1≤N, 1≤k2≤N, and k1≠k2.

[0053] For example, K=4, i=1, M=4;

[0054] The first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second narrow clock signal, the third narrow clock signal, the fourth narrow clock signal and the first narrow clock signal respectively;

[0055] The second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the first narrow clock signal, the second narrow clock signal, the third narrow clock signal and the fourth narrow clock signal respectively;

[0056] The third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the first wide clock signal, the second wide clock signal, the third wide clock signal and the fourth wide clock signal respectively;

[0057] The fourth clock signal terminals of the first to fourth stages of shift register units in each group are configured to receive the third narrow clock signal, the fourth narrow clock signal, the first narrow clock signal, and the second narrow clock signal, respectively.

[0058] For example, K=4, i=1, M=4;

[0059] The first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the fourth wide clock signal, the first wide clock signal, the second wide clock signal and the third wide clock signal respectively;

[0060] The second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second wide clock signal, the third wide clock signal, the fourth wide clock signal and the first wide clock signal respectively;

[0061] The third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the first wide clock signal, the second wide clock signal, the third wide clock signal and the fourth wide clock signal respectively;

[0062] The fourth clock signal terminals of the first to fourth stages of shift register units in each group are configured to receive the third narrow clock signal, the fourth narrow clock signal, the first narrow clock signal, and the second narrow clock signal, respectively.

[0063] For example, K=3, i=1, M=4;

[0064] The first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the third narrow clock signal, the fourth narrow clock signal, the first narrow clock signal, and the second narrow clock signal respectively;

[0065] The second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second wide clock signal, the third wide clock signal, the fourth wide clock signal and the first wide clock signal respectively;

[0066] The third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second narrow clock signal, the third narrow clock signal, the fourth narrow clock signal and the first narrow clock signal respectively.

[0067] For example, K=4, i=1, M=8;

[0068] The first clock signal terminals of the first to fourth stage shift register units in each group are configured to respectively receive eight wide clock signals sequentially shifted starting from the second wide clock signal;

[0069] The second clock signal terminals of the first to fourth stages of shift register units in each group are configured to respectively receive eight narrow clock signals sequentially shifted starting from the seventh narrow clock signal;

[0070] The third clock signal terminals of the first to fourth stage shift register units in each group are configured to respectively receive eight narrow clock signals sequentially shifted starting from the first narrow clock signal;

[0071] The fourth clock signal terminal of the first to fourth stage shift register units in each group is electrically connected to the power signal terminal and configured to receive the power signal.

[0072] For example, K=4, i=1, M=16;

[0073] The first clock signal terminals of the first to sixteenth stage shift register units in each group are configured to respectively receive 16 wide clock signals sequentially shifted starting from the third wide clock signal;

[0074] The second clock signal terminals of the first to sixteenth stage shift register units in each group are configured to respectively receive 16 narrow clock signals sequentially shifted starting from the fourteenth narrow clock signal;

[0075] The third clock signal terminals of the first to sixteenth stage shift register units in each group are configured to respectively receive 16 wide clock signals sequentially shifted starting from the first wide clock signal;

[0076] The fourth clock signal terminals of the first to sixteenth stage shift register units in each group are configured to respectively receive 16 narrow clock signals that are sequentially shifted starting from the first narrow clock signal.

[0077] An embodiment of the present disclosure further provides a display panel, comprising the display driving circuit as described above and a plurality of sub-pixels arranged in an array, wherein the display driving circuit is connected to the plurality of sub-pixels to provide display driving signals to the plurality of sub-pixels.

[0078] For example, the K output signal terminals of the nth stage shift register unit are connected to the nth row of sub-pixels to provide K display driving signals to the nth row of sub-pixels, wherein the K display driving signals include the gate driving signals and light emitting control signals required to drive the sub-pixels in this row.

[0079] For example, the K1 output signal terminals of the nth stage shift register unit and the K2 output signal terminals of the n+jth stage shift register unit are connected to the nth row of sub-pixels to provide K display driving signals to the nth row of sub-pixels, where K1+K2=K, and j is an integer greater than 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] FIG1A shows a circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

[0081] FIG1B shows a timing diagram of driving signals of the pixel circuit of FIG1A ;

[0082] FIG2A shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure;

[0083] FIG2B shows a timing diagram of driving signals of the pixel circuit of FIG2A ;

[0084] FIG. 3A shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

[0085] FIG3B shows a timing diagram of driving signals of the pixel circuit of FIG3A ;

[0086] FIG4 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure;

[0087] FIG5 shows a schematic block diagram of a shift register unit according to another embodiment of the present disclosure;

[0088] FIG6 shows a circuit diagram of a shift register unit according to an embodiment of the present disclosure;

[0089] FIG7 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0090] FIG8 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0091] FIG9A shows a schematic diagram of a display driving circuit according to an embodiment of the present disclosure;

[0092] FIG9B shows a signal timing diagram of the display driving circuit of FIG9A ;

[0093] FIG10A shows a schematic diagram of a display driving circuit according to another embodiment of the present disclosure;

[0094] FIG10B shows a signal timing diagram of the display driving circuit of FIG10A ;

[0095] FIG11A shows a schematic diagram of a display driving circuit according to another embodiment of the present disclosure;

[0096] FIG11B shows a signal timing diagram of the display driving circuit of FIG11A ;

[0097] FIG12A shows a schematic diagram of a display driving circuit according to another embodiment of the present disclosure;

[0098] FIG12B shows a signal timing diagram of the display driving circuit of FIG12A;

[0099] 13A and 13B are schematic diagrams showing a display driving circuit according to another embodiment of the present disclosure;

[0100] FIG13C shows a signal timing diagram of the display driving circuit of FIG13A and FIG13B;

[0101] FIG14 shows a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0102] FIG. 15 shows a schematic diagram of a display panel according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0103] While the present disclosure will be fully described with reference to the accompanying drawings that contain preferred embodiments of the present disclosure, it should be understood before this description that one of ordinary skill in the art may modify the disclosure described herein while still achieving the technical benefits of the present disclosure. Therefore, it should be understood that the above description is intended to be a broad disclosure for one of ordinary skill in the art and is not intended to limit the exemplary embodiments described herein.

[0104] In addition, in the following detailed description, for ease of explanation, numerous specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. However, it is apparent that one or more embodiments can be practiced without these specific details. In other cases, well-known structures and devices are shown in diagrammatic form to simplify the accompanying drawings.

[0105] FIG1A shows a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0106] As shown in FIG1A , the pixel circuit 10A of a sub-pixel may include a light-emitting element EL and a pixel driving circuit for driving the light-emitting element EL to emit light. According to an embodiment of the present disclosure, the pixel driving circuit may include an input sub-circuit, a driving sub-circuit, a compensation sub-circuit, and a light-emitting control sub-circuit. In FIG1A , the driving sub-circuit includes a driving transistor DTFT and a capacitor Cst. The input sub-circuit includes a transistor M1. The compensation sub-circuit includes transistors M2 and M3. The light-emitting control sub-circuit includes a transistor M4. The light-emitting element EL may be a light-emitting diode, such as an organic light-emitting diode OLED. The gate of transistor M1 receives a first gate drive signal G1, a first electrode receives a data signal DATA, and a second electrode is connected to the gate G of the driving transistor DTFT. The gate of transistor M2 receives a second gate drive signal G2, a first electrode receives an initial voltage VIN2, and a second electrode is connected to the gate of the driving transistor DTFT. The gate of transistor M3 receives a third gate drive signal G3, a first electrode receives an initial voltage VIN1, and a second electrode is connected to the source of the driving transistor DTFT. The gate of transistor M4 receives the emission control signal EM, the first electrode receives the power supply voltage VDD, and the second electrode is connected to the drain D of the driving transistor DTFT. The source S of the driving transistor DTFT is connected to the first electrode of the light emitting unit EL, and the second electrode of the light emitting unit EL receives the reference voltage VSS.

[0107] The driving signals for the pixel circuit in the above embodiment include a first gate driving signal G1, a second gate driving signal G2, a third gate driving signal G3, and an emission control signal EM. In other words, the pixel circuit emits light under the control of these driving signals. This will be described in detail below with reference to FIG. 1B.

[0108] As shown in Figure 1B, in the period P1, the first gate drive signal G1 is at a low level, the second gate drive signal G2 and the third gate drive signal G3 are at a high level, and the transistors M2 and M3 are turned on, thereby providing the initial voltage VIN2 to the gate G of the driving transistor DTFT and providing the initial voltage VIN1 to the source S of the driving transistor DTFT.

[0109] In period P2, the third gate drive signal G3 becomes a low level, the transistor M3 is turned off, and the source S of the driving transistor DTFT is charged until the potential difference between the gate G and the source S of the driving transistor DTFT is equal to the threshold voltage of the driving transistor DTFT, thereby achieving threshold voltage compensation.

[0110] In period P3, the second gate drive signal G2 becomes low, the first gate drive signal G1 becomes high, the light emitting control signal EM is low, the transistors M2 and M4 are turned off, and the transistor M1 is turned on, so that the data signal DATA is written into the gate G of the driving transistor DTFT.

[0111] During period P4, the first to third gate drive signals G1, G2, and G3 are all at low levels, the light-emission control signal EM is at a high level, the transistor M4 is turned on, and the driving transistor DTFT generates a driving current under the action of the data signal at the gate G, thereby driving the light-emitting unit EL to emit light. At this point, the display drive of the pixel circuit is completed.

[0112] In the example of FIG1B , the light-emission control signal EM maintains a high level during periods P1 to P2, and transistor M4 is in an on state. However, the embodiments of the present disclosure are not limited thereto. The light-emission control signal EM may also remain at a low level during periods P1 to P2, or switch between a high level and a low level, as long as it does not affect light-emission driving.

[0113] FIG. 2A shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

[0114] The pixel circuit 10B of FIG2A also includes a light-emitting element EL and a pixel driving circuit for driving the light-emitting element EL to emit light. The pixel driving circuit may include an input subcircuit, a driver subcircuit, a compensation subcircuit, and a light-emission control subcircuit. In the example of FIG2A , the input subcircuit includes a transistor M1. The driver subcircuit includes a driver transistor DTFT and a capacitor C2. The compensation subcircuit includes transistors M2 and M3 and a capacitor C1. The light-emission control subcircuit includes transistors M4 and M5.

[0115] The gate of transistor M1 receives a first gate drive signal G1, a first electrode receives a data signal DATA, and a second electrode is connected to the source of the driving transistor DTFT. The gate of transistor M2 receives a second gate drive signal G2, a first electrode is connected to the drain of the driving transistor DTFT, and a second electrode is connected to the gate of the driving transistor DTFT. The gate of transistor M3 receives the second gate drive signal G2, and a first electrode receives an initial voltage VINI. The first electrode of capacitor C2 is connected to the gate of the driving transistor DTFT, and the second electrode of capacitor C2 is connected to the second electrode of transistor M3. The first electrode of capacitor C1 receives the first gate drive signal G1, and the second electrode is connected to the first electrode of the light-emitting element EL. The gate of transistor M4 receives a first light-emitting control signal EM1, a first electrode receives a power supply voltage VDD, and a second electrode is connected to the drain of the driving transistor DTFT. The gate of transistor M5 receives a second light-emitting control signal EM2, a first electrode is connected to the source of the driving transistor DTFT, and a second electrode is connected to the first electrode of the light-emitting element EL. The second electrode of the light-emitting element EL is connected to a reference voltage VSS.

[0116] The driving signals for the pixel circuit in the above embodiment include a first gate drive signal G1, a second gate drive signal G2, a first light-emission control signal EM1, and a second light-emission control signal EM2. In other words, the pixel circuit emits light under the control of these driving signals. This will be described in detail below with reference to FIG2B.

[0117] As shown in Figure 2B, in the period P1, the first gate drive signal G1 and the second light-emitting control signal EM2 are at a low level, the second gate drive signal G2 and the first light-emitting control signal EM1 are at a high level, the transistors M2, M3 and M4 are turned on, the initial voltage VINI is written into the first electrode of the light-emitting unit EL, and the power supply voltage VDD is written into the gate of the driving transistor DTFT.

[0118] In period P2, the first gate drive signal G1 becomes high, the first light emitting control signal EM1 becomes low, and the transistor M1 is turned on, thereby writing the data signal DATA to the drain electrode S of the driving transistor DTFT. The transistors M4 and M5 are in the off state, thereby completing the threshold voltage compensation of the driving transistor DTFT.

[0119] In period P3, the first gate drive signal G1 and the second gate drive signal G2 become low levels, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 become high levels, the transistors M1 to M3 are turned off, the transistors M4 and M5 are turned on, and the driving transistor DTFT generates a driving current under the action of its gate voltage, thereby driving the light-emitting unit EL to emit light.

[0120] FIG. 3A shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

[0121] The pixel circuit 10C in FIG3A also includes a light-emitting element EL and a pixel driving circuit for driving the light-emitting element EL to emit light. The pixel driving circuit may include an input subcircuit, a driving subcircuit, a compensation subcircuit, and a light-emission control subcircuit. In the example of FIG3A , the input subcircuit includes a transistor M1. The driving subcircuit includes a driving transistor DTFT and a capacitor C1. The compensation subcircuit includes a transistor M2 and a capacitor C2. The light-emission control subcircuit includes a transistor M3. The gate of transistor M1 receives a first gate drive signal G1. The first electrode of transistor M1 receives a data signal DATA. The second electrode of transistor M1 is connected to the gate G of the driving transistor DTFT. The gate of transistor M2 receives a second gate drive signal G2. The first electrode of transistor M2 receives an initial voltage VINI, and the second electrode of transistor M2 is connected to the source S of the driving transistor DTFT. The gate of transistor M3 receives a light-emission control signal EM. The first electrode of transistor M3 receives a power supply voltage ELVDD, and the second electrode of transistor M3 is connected to the drain D of the driving transistor DTFT. The first electrode of capacitor C1 is connected to the gate of the driving transistor DTFT, and the second electrode is connected to the drain S of the driving transistor DTFT. The first electrode of the capacitor C2 is connected to the drain S of the driving transistor DTFT, and the second electrode receives the power supply voltage ELVDD. The first electrode of the light emitting unit EL is connected to the source of the driving transistor DTFT, and the second electrode is connected to the reference voltage ELVSS.

[0122] The driving signals of the pixel circuit in the above embodiment include a first gate driving signal G1, a second gate driving signal G2, and an emission control signal EM. In other words, the pixel circuit emits light under the control of these driving signals. This will be described in detail below with reference to FIG3B.

[0123] As shown in Figure 3B, in time period P1, the first gate drive signal G1 and the second gate drive signal G2 are at a high level, the data signal DATA is at a reference level, the light emitting control signal EM is at a low level, the transistors M1 and M2 are turned on, and the reference level Vref of the data signal DATA is written into the gate G of the driving transistor DTFT, and the initial voltage VINI is written into the source S of the driving transistor DTFT.

[0124] In time period P2, the second gate drive signal G2 becomes a low level, the light emitting control signal EM becomes a high level, the transistor M1 remains on, the transistor M2 is turned off, and the potential of the source S of the driving transistor DTFT begins to rise until the potential difference between the gate G and the source S of the driving transistor DTFT is equal to the threshold voltage Vth of the driving transistor DTFT, and the driving transistor DTFT is turned off.

[0125] During period P3, the light-emitting control signal EM becomes low, and the data signal DATA becomes a data voltage. Different data voltages cause the drive transistor DTFI to generate corresponding drive currents to drive the corresponding light-emitting element EL to display in corresponding grayscales. The light-emitting element EL can be one of red, blue, and green, so the data voltages are represented by R, G, and B in Figure 3B. The data voltage Vref causes the potential of the gate G of the drive transistor DTFT to change (gradually increasing in Figure 3B). The presence of capacitor C1 causes the potential of the source S of the drive transistor DTFT to change accordingly (also increasing in Figure 3B), so that the potential difference between the gate G and the source S is maintained at Vth.

[0126] In period P4, the light emitting control signal EM becomes high, the first gate driving signal G1 becomes low, the transistor M1 is turned off, the transistor M3 is turned on, and the driving transistor DTFT generates a driving current driven by the voltage of its gate G, thereby driving the light emitting unit EL to emit light.

[0127] The embodiments of the present disclosure further provide a shift register unit that can provide the gate drive signals and light-emitting control signals required to drive sub-pixels, for example, providing all or part of the drive signals required for the pixel circuit of any of the above embodiments. Although the pixel circuits of the above embodiments are implemented based on N-type transistors, the embodiments of the present disclosure are not limited thereto. The shift pixel unit of the embodiments of the present disclosure is also applicable to generating the required drive signals for sub-pixels having other pixel circuit structures. The embodiments of the shift register unit will be described below with reference to Figures 4 to 8.

[0128] FIG4 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.

[0129] As shown in FIG. 4 , the shift register unit includes an input circuit 110 , a pull-up circuit 120 , a pull-down circuit 130 , a cascade output circuit 140 , and a signal output circuit 150 .

[0130] The input circuit 110 is connected to the input signal terminal IN of the shift register unit and can input the signal of the input signal terminal IN to the pull-up node Q.

[0131] The pull-up circuit 120 is connected to the input signal terminal IN and the pull-down node QB of the shift register unit. The pull-up circuit 120 can pull up the potential of the pull-down node QB based on the potential of the input signal terminal IN.

[0132] The pull-down circuit 130 is connected to the pull-up node Q and the pull-down node QB. The pull-down circuit 130 can pull down the potential of the pull-down node QB based on the potential of the pull-up node Q.

[0133] The cascade output circuit 140 is connected to the pull-up node Q, the pull-down node QB, the power supply signal terminal GVDD, the reference signal terminal VGL, and the cascade output terminal CR of the shift register unit. The cascade output circuit 140 can provide a signal from one of the power supply signal terminal GVDD and the reference signal terminal VGL to the cascade output terminal CR under the control of the pull-up node Q and the pull-down node QB.

[0134] The signal output circuit 150 is connected to the K clock signal terminals and K output signal terminals of the shift register unit. The signal output circuit 150 can generate K drive signals required to drive the sub-pixels. At least two of the K output signal terminals have different duty cycles. The K drive signals include a gate drive signal and a light-emitting control signal, where K is an integer greater than 1. For example, the signal output circuit 150 may include K output units, each connected to the K clock signal terminals.

[0135] For the convenience of description, FIG4 shows an example of K==3. However, the embodiments of the present disclosure are not limited thereto, and the number of output units can be selected as needed.

[0136] As shown in FIG4 , the signal output circuit 150 includes a first output unit 150_1 , a second output unit 150_2 , and a third output unit 150_3 , which are connected to the first clock signal terminal CLK1 , the second clock signal terminal CLK2 , and the third clock signal terminal CLK3 , respectively.

[0137] The kth output unit is connected to the pull-up node Q, the pull-down node QB, the kth clock signal terminal, and the kth output signal terminal, where 1 ≤ k ≤ K. For example, in FIG4 , the first output unit 150_1 is connected to the pull-up node Q, the pull-down node QB, the first clock signal terminal CLK1, and the first output signal terminal OUT1; the second output unit 150_2 is connected to the pull-up node Q, the pull-down node QB, the second clock signal terminal CLK2, and the second output signal terminal OUT2; and the third output unit 150_3 is connected to the pull-up node Q, the pull-down node QB, the third clock signal terminal CLK3, and the third output signal terminal OUT3.

[0138] At least one output unit (e.g., first output unit 150_1) is further connected to the power signal terminal GVDD and is configured to provide a signal from either the connected clock signal terminal or the power signal terminal GVDD to the connected output signal terminal under the control of the pull-up node Q and the pull-down node QB. As shown in FIG4 , first output unit 150_1 is connected to the pull-up node Q, the pull-down node QB, the power signal terminal GVDD, the first clock signal terminal CLK1, and the first output signal terminal OUT1. First output unit 150_1 can provide a signal from either the first clock signal terminal CLK1 or the power signal terminal GVDD to the first output signal terminal OUT1 under the control of the pull-up node Q and the pull-down node QB.

[0139] At least one other output unit (e.g., the second output unit 150_2 and the third output unit 150_3) is further connected to the reference signal terminal VGL and is configured to provide a signal from one of the connected clock signal terminal and the reference signal terminal VGL to the connected output signal terminal under the control of the pull-up node Q and the pull-down node QB. For example, in FIG4 , the second output unit 150_2 is connected to the pull-up node Q, the pull-down node QB, the reference signal terminal VGL, the second clock signal terminal CLK2, and the second output signal terminal OUT2. The second output unit 150_2 can provide a signal from one of the second clock signal terminal CLK2 and the reference signal terminal VGL to the second output signal terminal OUT2 under the control of the pull-up node Q and the pull-down node QB. The third output unit 150_3 is connected to the pull-up node Q, the pull-down node QB, the reference signal terminal VGL, the third clock signal terminal CLK3, and the third output signal terminal OUT3. The third output unit 150_3 may provide a signal of one of the third clock signal terminal CLK3 and the reference signal terminal VGL to the third output signal terminal OUT3 under the control of the pull-up node Q and the pull-down node QB.

[0140] In an embodiment of the present disclosure, a signal output circuit comprising K output units is provided within a shift register unit. Each output unit has one end connected to a corresponding clock signal terminal and the other end connected to a reference signal terminal or a power signal terminal. In this manner, the shift register unit can generate the multiple display drive signals (e.g., gate drive signals and light-emitting control signals) required to drive the sub-pixels without requiring a separate shift register unit for each display drive signal, facilitating a narrow-frame design for the display panel.

[0141] FIG5 shows a schematic block diagram of a shift register unit according to another embodiment of the present disclosure.

[0142] Similar to FIG4 , the shift register unit of FIG5 also includes an input circuit 110 , a pull-up circuit 120 , a pull-down circuit 130 , a cascade output circuit 140 and a signal output circuit 150 . The above description of these circuits also applies to FIG5 .

[0143] Unlike Figure 4 , the power signal terminals in Figure 5 may include a first power signal terminal GVDD1 and a second power signal terminal GVDD2, and the reference signal terminals may include a first reference signal terminal VGL1 and a second reference signal terminal VGL2. The cascade output circuit 140 may be connected to the first power signal terminal GVDD1 and the first reference signal terminal VGL1, and the signal output circuit including K output units 150_1, 150_2, and 150_3 may be connected to the second power signal terminal GVDD2 and the second reference signal terminal VGL2. By connecting the signal output circuit to a separate set of power signal terminals and reference signal terminals, the impact of other circuits on the signal output circuit can be reduced.

[0144] As shown in FIG. 5 , the cascade output circuit 140 may include a first cascade sub-circuit 1401 and a second cascade sub-circuit 1402 .

[0145] The first cascade sub-circuit 1401 is connected to the pull-up node Q, a power signal terminal (the first power signal terminal GVDD1 in FIG5 ), and a cascade output terminal CR. Under the control of the pull-up node Q, the first cascade sub-circuit 1401 can provide a signal from the power signal terminal to the cascade output terminal CR.

[0146] The second cascade sub-circuit 1402 is connected to the pull-down node QB, a reference signal terminal (the first reference signal terminal VGL1 in FIG5 ), and the cascade output terminal CR. The second cascade sub-circuit 1402 can provide the signal of the reference signal terminal to the cascade output terminal CR under the control of the pull-down node QB.

[0147] In some embodiments, each output unit may include a first output sub-circuit and a second output sub-circuit. For example, in FIG5 , first output unit 150_1 includes a first output sub-circuit 1501_1 and a second output sub-circuit 1501_2, second output unit 1502 includes a first output sub-circuit 1502_1 and a second output sub-circuit 1502_2, and third output unit 1503 includes a first output sub-circuit 1503_1 and a second output sub-circuit 1503_2.

[0148] In some embodiments, each of the first output sub-circuit and the second output sub-circuit has a control terminal, an input terminal, and an output terminal and is configured to provide a signal at the input terminal to the output terminal under control of the control terminal.

[0149] For example, in first output unit 150_1, a control terminal of first output sub-circuit 1501_1 is connected to a first pull-up node Q, an input terminal of first output sub-circuit 1501_1 is connected to a first clock signal terminal CLK1, and an output terminal of first output sub-circuit 1501_1 is connected to a first output signal terminal OUT1. A control terminal of second output sub-circuit 1501_2 is connected to a pull-down node QB, an input terminal of second output sub-circuit 1501_2 is connected to a power signal terminal (connected to a second power signal terminal GVDD2 in FIG. 5 ), and an output terminal of second output sub-circuit 1501_2 is connected to the first output signal terminal OUT1.

[0150] In the second output unit 150_2, the control end of the first output sub-circuit 1502_1 is connected to the first pull-up node Q, the input end of the first output sub-circuit 1502_1 is connected to the second clock signal end CLK2, and the output end of the first output sub-circuit 1502_1 is connected to the second output signal end OUT; the control end of the second output sub-circuit 1502_2 is connected to the pull-down node QB, the input end of the second output sub-circuit 1502_2 is connected to the reference signal end (connected to the second reference signal end VGL2 in Figure 5), and the output end of the second output sub-circuit 1502_2 is connected to the second output signal end OUT2.

[0151] Similarly, in the third output unit 150_3, the control end of the first output sub-circuit 1503_1 is connected to the first pull-up node Q, the input end of the first output sub-circuit 1503_1 is connected to the third clock signal end CLK3, and the output end of the first output sub-circuit 1503_1 is connected to the third output signal end OUT3; the control end of the second output sub-circuit 1503_2 is connected to the pull-down node QB, the input end of the second output sub-circuit 1503_2 is connected to the reference signal end (connected to the second reference signal end VGL2 in Figure 5), and the output end of the second output sub-circuit 1503_2 is connected to the third output signal end OUT3.

[0152] In some embodiments, one of the K clock signal terminals can be electrically connected to the power signal terminal. For example, when K=4, the fourth clock signal terminal CLK4 can be electrically connected to the second power signal terminal GVDD2 to receive the second power signal. This will be described in detail below.

[0153] FIG6 shows a circuit diagram of a shift register unit according to an embodiment of the present disclosure.

[0154] The shift register unit of Figure 6 also includes an input circuit 210, a pull-up circuit 220, a pull-down circuit 230, a cascade output circuit 240 and a signal output circuit. The above description of the input circuit, pull-up circuit, pull-down circuit, cascade output circuit and signal output circuit is also applicable to this embodiment.

[0155] In FIG. 6 , K=4, and the signal output circuit includes a first output unit 250_1 , a second output unit 250_2 , a third output unit 250_3 , and a fourth output unit 250_4 .

[0156] Each output unit in Figure 6 also includes a first output sub-circuit and a second output sub-circuit. For example, the first output sub-circuit of first output unit 250_1 includes a first transistor T1_1 and a first capacitor C1_1, while the second output sub-circuit of first output unit 250_1 includes a second transistor T2_1. Similarly, the first output sub-circuit of second output unit 250_2 includes a first transistor T1_2 and a first capacitor C1_2, while the second output sub-circuit of first output unit 250_1 includes a second transistor T2_2. The first output sub-circuit of third output unit 250_3 includes a first transistor T1_3 and a first capacitor C1_3, while the second output sub-circuit of first output unit 250_3 includes a second transistor T2_3.

[0157] In each output unit, the gate of the first transistor serves as the control terminal of the first output sub-circuit, the first electrode of the first transistor serves as the input terminal of the first output sub-circuit, and the second electrode of the first transistor serves as the output terminal of the first output sub-circuit. The first electrode of the first capacitor is connected to the gate of the first transistor, and the second electrode of the first capacitor is connected to the second electrode of the first transistor. The gate of the second transistor serves as the control terminal of the second output sub-circuit, the first electrode of the second transistor serves as the input terminal of the second output sub-circuit, and the second electrode of the second transistor serves as the output terminal of the second output sub-circuit. Taking the first output unit 250_1 as an example, the gate of the first transistor T1_1 serves as the control terminal of the first output sub-circuit and is connected to the pull-up node Q. The first electrode of the first transistor T1_1 serves as the input terminal of the first output sub-circuit and is connected to the first clock signal terminal CLK1. The second electrode of the first transistor T1_1 serves as the output terminal of the first output sub-circuit and is connected to the first output signal terminal OUT1. The first electrode of the first capacitor C1_1 is connected to the gate of the first transistor T1_1, and the second electrode of the first capacitor C1_1 is connected to the second electrode of the first transistor T1_1. Taking the first output unit 250_1 as an example, the gate of the second transistor T2_1 serves as the control terminal of the second output sub-circuit and is connected to the pull-down node QB. The first electrode of the second transistor T2_1 serves as the input terminal of the second output sub-circuit and is connected to the second reference signal terminal VGL2. The second electrode of the second transistor T2_1 serves as the output terminal of the second output sub-circuit and is connected to the first output signal terminal OUT1. The first transistor, second transistor, and second capacitor of the second output unit 250_2, the third output unit 250_3, and the fourth output unit 250_4 are connected in a similar manner and are not further described here.

[0158] Continuing with FIG6 , the cascade output circuit 240 also includes a first cascade sub-circuit and a second cascade sub-circuit, wherein the first cascade sub-circuit includes a third transistor T3 and a second capacitor C2, and the second cascade sub-circuit includes a fourth transistor T4 and a third capacitor C3. As shown in FIG6 , the gate of the third transistor T3 is connected to the pull-up node Q, the first electrode of the third transistor T3 is connected to the power signal terminal (in FIG6 , the first power signal terminal GVDD1), and the second electrode of the third transistor T3 is connected to the cascade output terminal CR. The first electrode of the second capacitor C2 is connected to the gate of the third transistor T3, and the second electrode of the second capacitor C2 is connected to the second electrode of the third transistor T3. The gate of the fourth transistor T4 is connected to the pull-down node QB, the first electrode of the fourth transistor T4 is connected to the reference signal terminal (in FIG6 , the first reference signal terminal VGL1), and the second electrode of the fourth transistor T4 is connected to the cascade output terminal CR. The first electrode of the third capacitor C3 is connected to the gate of the fourth transistor T4, and the second electrode of the third capacitor C3 is connected to the second electrode of the fourth transistor T4.

[0159] In some embodiments, as shown in FIG. 6 , the pull-up circuit 220 may include a first control subcircuit 2201 and a second control subcircuit 2202 .

[0160] The first control subcircuit 2201 is connected to the input signal terminal IN, the power signal terminal (in FIG6 , the third power signal terminal VGH, which can also be implemented by other power signal terminals, such as the first power signal terminal GVDD1), the second control signal terminal CKB of the shift register unit, and the intermediate node P. The first control subcircuit 2201 can control the potential of the intermediate node P based on the signals at the input signal terminal IN and the second control signal terminal CKB. In FIG6 , the first control subcircuit 2201 includes a seventh transistor T7 and an eighth transistor T8. The gate of the seventh transistor T7 is connected to the second control signal terminal CKB, the first electrode of the seventh transistor T7 is connected to the power signal terminal VGH, and the second electrode of the seventh transistor T7 is connected to the intermediate node P. The gate of the eighth transistor T8 is connected to the input signal terminal IN, the first electrode of the eighth transistor T8 is connected to the second control signal terminal CKB, and the second electrode of the eighth transistor T8 is connected to the intermediate node P.

[0161] The second control subcircuit 2202 is connected to the intermediate node P, the pull-down node QB, and the first control signal terminal CKA of the shift register unit. The second control subcircuit 2202 can pull up the potential of the pull-down node QB based on the signals at the intermediate node P and the first control signal terminal CKA. In Figure 6, the second control subcircuit 2202 includes a ninth transistor T9, a tenth transistor T10, and a fourth capacitor C4. The gate of the ninth transistor T9 is connected to the intermediate node P, the first electrode of the ninth transistor T9 is connected to the first control signal terminal CKA, the second electrode of the ninth transistor T9 is connected to the first electrode of the tenth transistor T10, the gate of the tenth transistor T9 is connected to the first control signal terminal CKA, and the second electrode of the tenth transistor T10 is connected to the pull-down node QB. The first electrode of the fourth capacitor C4 is connected to the gate of the ninth transistor T9, and the second electrode of the fourth capacitor C4 is connected to the second electrode of the ninth transistor T9.

[0162] The pull-down circuit 230 may include a thirteenth transistor T13 having a gate connected to the pull-up node Q, a first electrode connected to the reference signal terminal (the first reference signal terminal VGL1 in FIG6 ), and a second electrode connected to the pull-down node QB.

[0163] The input circuit 210 may include a fourteenth transistor T14 , a gate of the fourteenth transistor T14 connected to the first control signal terminal CKA, a first electrode of the fourteenth transistor T14 connected to the input signal terminal IN, and a second electrode of the fourteenth transistor T14 connected to the pull-up node Q.

[0164] In some embodiments, as shown in FIG6 , the input circuit may further include a fifteenth transistor T15. In this case, the second electrode of the fourteenth transistor T14 may be connected to the pull-up node Q via the fifteenth transistor T15, wherein the gate of the fifteenth transistor T15 is connected to the power signal terminal (the first power signal terminal GVDD1 in FIG6 ), the first electrode of the fifteenth transistor T15 is connected to the second electrode of the fourteenth transistor T14, and the second electrode of the fifteenth transistor T15 is connected to the pull-up node Q. The fifteenth transistor T15 may serve as an isolation function. For example, taking the fifteenth transistor T15 as an N-type transistor as an example, when the potential of the pull-up node Q or the node QH is higher than the potential of the gate of the fifteenth transistor (i.e., the potential of the first control signal terminal CKA), the fifteenth transistor T15 is turned off, thereby isolating the pull-up node Q from the node QH to prevent the pull-up node Q potential from being too high and affecting the output signal.

[0165] In some embodiments, as shown in FIG6 , the shift register unit may further include a reset circuit 260. The reset circuit 260 is connected to the pull-up node Q, the pull-down node QB, the power signal terminal (the first power signal terminal GVDD1 in FIG6 ), the reference signal terminal (the first reference signal terminal VGL1 in FIG6 ), and the reset signal terminal TRS of the shift register unit. Under the control of the reset signal terminal TRS, the reset circuit 260 can provide a signal from the reference signal terminal (the first reference signal terminal VGL1) to the pull-up node Q and provide a signal from the power signal terminal (the first power signal terminal GVDD1) to the pull-down node QB. In the example of FIG6 , the reset circuit 260 includes a sixteenth transistor T16 and a seventeenth transistor T17. The gate of the sixteenth transistor T16 is connected to the reset signal terminal TRS, the first electrode of the sixteenth transistor T16 is connected to the reference signal terminal (the first reference signal terminal VGL1), and the second electrode of the sixteenth transistor is connected to the pull-up node Q. A gate of the seventeenth transistor T17 is connected to the reset signal terminal TRS, a first electrode of the seventeenth transistor T17 is connected to the power signal terminal (the first power signal terminal GVDD1 ), and a second electrode of the seventeenth transistor T17 is connected to the pull-down node QB.

[0166] When the shift register unit is operating, the input signal terminal IN and the first control signal terminal CKA are both at a high level, the fourteenth transistor T14 is turned on, and the gate of the fifteenth transistor T15 is turned on by the first power supply signal terminal GVDD1, thereby providing the high level of the input signal terminal IN to the pull-up node Q. The high level of the pull-up node Q turns on the first transistors T1_1, T1_2, T1_3, and T1_4 of each output unit, thereby providing the signals of the clock signal terminals CLK1 to CLK4 connected to them to the corresponding output signal terminals OUT1 to OUT4, thereby generating four output signals. During this process, the high level of the node QB turns on the thirteenth transistor T13, thereby providing the low level of the first reference signal terminal VGL1 to the pull-down node QB, causing the pull-down node QB to remain at a low level.

[0167] Next, the input signal terminal IN goes low, and the eighth transistor T8 turns off. When the second control signal terminal CKB is high, the seventh transistor T7 turns on, supplying the high level of the third power supply signal terminal VGH to the intermediate node P. The high level of the intermediate node P causes the ninth transistor T9 to turn on, awaiting the arrival of the high level of the first control signal terminal CKA. Thereafter, when the high level of the first control signal terminal CKA arrives, the fourteenth transistor T14 and the fifteenth transistor T15 both turn on, thereby supplying the low level of the input signal terminal IN to the pull-up node Q, causing the third transistor T3 and the first transistors T1_1 to T1_4 of each output unit to turn off. The high level of the first control signal terminal CKA also turns on the tenth transistor T10, thereby pulling the pull-down node QB up to a high level. The high level of the pull-down node QB turns on the fourth transistor T4, causing the cascade output terminal CR to output a low-level signal. The high level of the pull-down node QB also turns on the second transistors T2_1, T2_2, T2_3, and T2_4 of each output unit, so that the first output signal terminal OUT1 outputs a high level, and the second to fourth output signal terminals OUT2 to OUT4 all output low levels. In this way, the shift register unit generates four output signals, of which the output signal of the first output signal terminal OUT1 can be used as a low-level effective light-emitting control signal; and the output signals of the second to fourth output signal terminals OUT2 to OUT4 can be used as high-level effective gate drive signals. After a frame of display is completed, all shift register units can be reset. For example, a high-level reset signal, such as a high-level reset signal, is applied to the reset signal terminal TRS of each shift register unit, turning on the sixteenth transistor T16 and the seventeenth transistor T17 of each shift register unit. The conduction of the sixteenth transistor T16 resets the pull-up node Q to the low level of the first reference signal terminal VGL1; the conduction of the seventeenth transistor T17 resets the pull-down node QB to the high level of the first power signal terminal GVDD1, so that each output unit does not generate an output, thereby realizing the reset of the shift register unit.

[0168] FIG7 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0169] The shift register unit of Figure 7 is similar to that of Figure 6, except that two output units in Figure 7 are connected to the power signal terminal, and the other two output units are connected to the reference signal terminal. As shown in Figure 7, the circuit structure other than the fourth output unit 250_4 is the same as that of Figure 6 and will not be repeated here. The fourth output unit 250_4 is connected to the fourth clock signal terminal CLK4 and the second power signal terminal GVDD2. When the pull-up node Q is at a high level and the pull-down node QB is at a low level, transistor T1_4 is turned on and transistor T2_4 is turned off, thereby providing the signal of the fourth clock signal terminal CLK4 to the output signal terminal OUT4. When the pull-up node Q is at a low level and the pull-down node QB is at a high level, transistor T1_4 is turned off and transistor T2_4 is turned on, thereby providing the signal of the second power signal terminal GVDD2 to the output signal terminal OUT4.

[0170] The shift register described above with reference to FIG. 6 and FIG. 7 has four output signal terminals, which can generate four display driving signals required to drive a single sub-pixel, such as the driving signals required by the above-mentioned pixel circuit 10A.

[0171] FIG8 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0172] Similar to FIG6 , the shift register unit of FIG8 also includes an input circuit 310, a pull-up circuit 320, a pull-down circuit 330, a cascade output circuit, a signal output circuit, and a reset circuit 360. The difference lies in at least K=3 (i.e., the signal output circuit includes three output units), and at least one of the pull-up circuit 320, the cascade output circuit, and the reset circuit 360 may also be provided with a leakage protection structure. For ease of description, the following will primarily describe the differences in detail.

[0173] The input circuit 310 includes a fourteenth transistor T14 and a fifteenth transistor T15. Unlike FIG6 , the gate of the fifteenth transistor T15 in the input circuit 310 of FIG8 is connected to the first control signal terminal CKA. This connection of the fifteenth transistor T15 also serves as an isolation function. For example, when the first control signal terminal CKA is at a high level, the fifteenth transistor T15 turns on, allowing the high level of the input signal terminal IN to be input to the pull-up node Q through the fourteenth transistor T14 and the fifteenth transistor T15. When the first control signal terminal CKA is at a low level, the fifteenth transistor T15 turns on, thereby isolating the node QH from the pull-up node Q. In this case, even if the fourteenth transistor T14 leaks or the potential of the node QH increases due to other reasons, the presence of the fifteenth transistor T15 can prevent the node QH from affecting the potential of the pull-up node Q.

[0174] The pull-up circuit 320 includes a first control subcircuit 3201 and a second control subcircuit 3202. The second control subcircuit 3202 has the same structure as the second control subcircuit 2202 described above and will not be further described here. Unlike FIG6 , the first control subcircuit 3201 includes, in addition to the seventh transistor T7 and the eighth transistor T8, an eleventh transistor T11 and a twelfth transistor T12. The first electrode of the eighth transistor T8 is connected to the second control signal terminal CKB via the eleventh transistor T11. As shown in FIG8 , the gate of the eleventh transistor T11 is connected to the input signal terminal IN, the first electrode of the eleventh transistor T11 is connected to the second control signal terminal CKB, and the second electrode of the eleventh transistor T11 is connected to the first electrode of the eighth transistor T8. The gate of the twelfth transistor T12 is connected to the intermediate node P, the first electrode of the twelfth transistor T12 is connected to the power signal terminal, and the second electrode of the twelfth transistor T12 is connected to the first electrode of the eighth transistor. The presence of the eleventh transistor T11 and the twelfth transistor T12 can prevent leakage. For example, when the input signal terminal IN is at a low level, the intermediate node P is at a high level, and the second control signal terminal CKB is at a low level, if there are no eleventh transistor T11 and the twelfth transistor T12, the following situation will occur: the eighth transistor T8 is in the off state, but there is a large voltage difference between the first and second electrodes of the eighth transistor T8, which makes the eighth transistor T8 prone to leakage. By providing the eleventh transistor T11 and the twelfth transistor T12, in this case, the high level of the intermediate node T12 will turn on the twelfth transistor T12, so that the first and second electrodes of the eighth transistor T8 are both at a high level, reducing the voltage difference between the first and second electrodes of the eighth transistor T8, thereby preventing leakage. At the same time, the low level of the input signal terminal IN also turns off the eleventh transistor T11, thereby preventing the potential of the first electrode of the eighth transistor T8 from being affected by the second control signal terminal CKB.

[0175] The pull-down circuit 330 may have the same structure as the pull-down circuit 230 in the above embodiment, and will not be described in detail here.

[0176] The cascade output circuit includes a first cascade sub-circuit 3401 and a second cascade sub-circuit 3402. The first cascade sub-circuit 3401 includes a third transistor T3 and a second capacitor C2. The description of the first cascade sub-circuit with reference to FIG6 above also applies to this embodiment. Unlike FIG6, the second cascade sub-circuit 3402 includes, in addition to the fourth transistor T4 and the third capacitor C2, a fifth transistor T5 and a sixth transistor T6. The second electrode of the fourth transistor T4 is connected to the cascade output terminal CR via the fifth transistor T5. As shown in FIG8, the first electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5 is connected to the cascade output terminal CR, and the gate T5 of the fifth transistor is connected to the pull-down node QB. The gate of the sixth transistor T6 is connected to the cascade output terminal CR, the first electrode of the sixth transistor T6 is connected to the power signal terminal (the first power signal terminal GVDD1), and the second electrode of the sixth transistor T6 is connected to the pull-up node Q. The fifth transistor T5 and the sixth transistor T6 also serve to prevent leakage. When the cascade output terminal CR is at a high level and the pull-down node QB is at a low level, without the fifth transistor T5 and the sixth transistor T6, the following situation occurs: the fourth transistor T4 is off, but the first electrode of the fourth transistor T4 is at a low level and the second electrode is at a high level. The large potential difference between the first and second electrodes of the fourth transistor T4 makes the fourth transistor T4 susceptible to leakage. By providing the fifth transistor T5 and the sixth transistor T6, the low level of the pull-down node QB turns the fifth transistor T5 off, and the first electrode of the fifth transistor T5 receives the high level of the cascade output terminal CR. At the same time, the high level of the cascade output terminal CR turns on the sixth transistor T6, thereby providing the high level of the first power supply signal terminal GVDD1 to the first electrode of the fifth transistor T5. In this way, the fifth transistor T5 is off, and the first and second electrodes of the fifth transistor T5 are both at high levels, thereby preventing leakage of the fifth transistor T5. In this case, even if the fourth transistor T4 leaks, the presence of the fifth transistor T5 can prevent the leakage of the fourth transistor T4 from affecting the output signal of the cascade output terminal CR.

[0177] In this embodiment, K=3, and the signal output circuit includes a first output unit 350_1, a second output unit 350_2, and a third output unit 350_3. The description of the first output unit 250_1, the second output unit 250_2, and the third output unit 250_3 in the above embodiment is also applicable to this embodiment and will not be repeated here.

[0178] The reset circuit 360 is similar to the reset circuit 260 described above, except that the reset circuit 360 includes an 18th transistor T18 in addition to the 16th transistor T16 and the 17th transistor T17. The first electrode of the 16th transistor T16 is connected to the reference signal terminal (first reference signal terminal VGL1) through the 18th transistor T18. As shown in Figure 8, the gate of the 18th transistor T18 is connected to the reset signal terminal TRS, the first electrode of the 18th transistor T18 is connected to the reference signal terminal (first reference signal terminal VGL1), and the second electrode of the 18th transistor T18 is connected to the first electrode of the 16th transistor. The 18th transistor T18 can also play a role in preventing leakage. For example, when the reset signal terminal TRS is low and the pull-up node Q is high, if there is no 18th transistor T18, then the first electrode and the second electrode of the 16th transistor T16 will be level and high respectively, thereby easily leaking. By setting the eighteenth transistor T18 , the low level of the reset signal terminal TRS turns off the eighteenth transistor T18 , and both the first electrode and the second electrode of the sixteenth transistor T16 are at high levels, thereby preventing the sixteenth transistor T16 from leaking.

[0179] The shift register described above with reference to FIG8 has three output signal terminals, which are suitable for generating three driving signals, such as the driving signals required by the above-mentioned pixel circuit 10C, which will be described in detail below.

[0180] In some embodiments, the signal output circuit of the shift register unit can generate some or all of the K drive signals required to drive a single sub-pixel. For example, assuming that driving a single sub-pixel requires a first gate drive signal G1, a second gate drive signal G2, a third gate drive signal G3, and a light-emission control signal EM, a single shift register unit can be configured to generate all the drive signals required for the single sub-pixel, namely, the first gate drive signal G1, the second gate drive signal G2, the third gate drive signal G3, and the light-emission control signal EM (described in detail below with reference to Figures 9A to 12B). Alternatively, one shift register unit can be configured to generate the first gate drive signal G1, the third gate drive signal G3, and the light-emission control signal EM required for the sub-pixel, while another shift register unit can be configured to generate the second gate drive signal G2 required for the sub-pixel. In this way, the two shift register units cooperate to provide all the required drive signals for the sub-pixel (described in detail below with reference to Figures 13A to 13C).

[0181] An embodiment of the present disclosure further provides a display driving circuit, including the shift register unit of any of the above embodiments, which will be described in detail below with reference to FIG. 9A to FIG. 13C .

[0182] FIG9A shows a schematic diagram of a display driving circuit according to an embodiment of the present disclosure.

[0183] As shown in FIG9A , the display driving circuit includes N shift register units GOA connected in cascade. <1> , GOA <2> ,...,GOA <n>The shift register unit in FIG. 9A may be implemented as the shift register unit of any of the above embodiments, such as the shift register unit described above with reference to FIG. 6 .

[0184] The cascade output terminal CR of the nth stage shift register unit can be connected to the input signal terminal IN of the n+ith stage shift register unit, where N, n and i are all positive integers, and n<N. For example, in FIG9A , i=1, the first stage shift register unit GOA <1> The cascade output terminal CR is connected to the second stage shift register unit GOA <2> The input signal terminal IN, the second stage shift register unit GOA <2> The cascade output terminal CR is connected to the third-stage shift register unit GOA <3> The first stage shift register unit GOA <1> The input signal terminal IN can receive the start signal STU. Although i=1 is used as an example in FIG9A , the embodiments of the present disclosure are not limited thereto, and i can be set to other values ​​as needed.

[0185] The display driving circuit may receive multiple clock signals, such as M sequentially shifted narrow clock signals and M wide clock signals, where M is an integer multiple of K. In FIG9A , M=4, the sequentially shifted M narrow clock signals are clock signals Clks1, Clks2, Clks3, and Clks4, and the sequentially shifted M wide clock signals are Clkp1, Clkp2, Clkp3, and Clkp4.

[0186] The K clock signal terminals of each shift register unit can respectively receive K clock signals from a plurality of clock signals. For example, the N shift register units can be divided into at least one group, each group comprising M shift register units connected in cascade, the M k1-th clock signal terminals of each group of shift register units being configured to respectively receive M narrow clock signals, and the M k2-th clock signal terminals of each group of shift register units being configured to respectively receive M wide clock signals, wherein k1 and k2 are positive integers, 1≤k1≤N, 1≤k2≤N, and k1≠k2. In FIG9A , K=4, M=4, and the N shift register units are divided into multiple groups, each group comprising four shift register units, for example, the first group comprises the first to fourth stage shift register units GOA <1> to GOA <4> The second group includes the fifth to eighth stage shift register units GOA <5> to GOA <8> , and so on. The clock signal terminals CLK1 , CLK2 , and CLK4 of the shift register units in each group receive narrow clock signals, while the clock signal terminal CLK3 receives a wide clock signal.

[0187] In FIG9A , taking the first group as an example, the shift register unit GOA at the first stage <1> The first clock signal terminal CLK1 receives the second narrow clock signal Clks2, and the shift register unit GOA at the second stage <2> The first clock signal terminal CLK1 receives the third narrow clock signal Clks3, and the shift register unit GOA at the third stage <3> The first clock signal terminal CLK1 receives the fourth narrow clock signal Clks4, and the shift register unit GOA at the fourth stage <4> The first clock signal terminal CLK1 receives the first narrow clock signal Clks1. In a similar manner, the shift register unit GOA <1> to GOA <4> The second clock signal terminal CLK2 receives the first narrow clock signal Clks1, the second narrow clock signal Clks2, the third narrow clock signal Clks3 and the fourth narrow clock signal Clks4 respectively. <1> to GOA <4> The third clock signal terminal CLK3 receives the first wide clock signal Clkp1, the second wide clock signal Clkp2, the third wide clock signal Clkp3 and the fourth wide clock signal Clkp1 respectively. <1> to GOA <4> The fourth clock signal terminal CLK4 receives the third narrow clock signal Clks3, the fourth narrow clock signal Clks4, the first narrow clock signal Clks1 and the second narrow clock signal Clks2 respectively.

[0188] The first to fourth stage shift register units GOA in the second group <5> to GOA <8> The clock signal terminals of the fifth to eighth stage shift register units (that is, the entire display driving circuit) are connected in the same way. Specifically, the shift register unit GOA <5> to GOA <8> The first clock signal terminal CLK1 receives clock signals Clks2, Clks3, Clks4 and Clks1 respectively, the second clock signal terminal CLK2 receives clock signals Clks1, Clks2, Clks3, Clks4 respectively, the third clock signal terminal CLK3 receives clock signals Cklp1, Clkp2, CLkp3, Clkp4 respectively, and the fourth clock signal terminal CLK4 receives clock signals Clks3, Clks4, Clks1, Clks2 respectively. The third group of shift register units GOA <9> to GOA <12> The clock signal terminal is connected in the same way, and so on.

[0189] The first control signal terminal CKA and the second control signal terminal CKB of each shift register unit receive the first control signal Cka and the second control signal Ckb. <1> , GOA <3> , GOA <5> ...a first control signal terminal CKA receives a first control signal Cka, a second control signal terminal CKB receives a second control signal Ckb; a shift register unit GOA at an even-numbered stage <2> , GOA <4> , GOA <6> ...a first control signal terminal CKA receives a second control signal Ckb, and a second control signal terminal CKB receives a second control signal Cka. However, the embodiments of the present disclosure are not limited thereto, and the connection modes of the odd-numbered stages and the even-numbered stages can be interchanged.

[0190] Each shift register unit GOA <1> , GOA <2> ,...GOA <n>The reset signal terminal TRS receives the reset signal Trs. In conjunction with FIG6 , the power signal terminal and reference signal terminal of each shift register can receive corresponding power signals and reference signals. For example, the first power signal terminal GVDD1 can receive the first power signal, the first reference signal terminal VGL1 can receive the first reference signal, the second power signal terminal GVDD2 can receive the second power signal, and the second reference signal terminal VGL2 can receive the second reference signal. These details are not repeated here.

[0191] The display driver circuit can be used to drive multiple rows of sub-pixels, wherein the K output signal terminals of each shift register unit provide display driver signals to a corresponding row of sub-pixels in the multiple rows of sub-pixels. According to an embodiment of the present disclosure, the display driver signals include the gate driver signals and the light-emitting control signals required to drive the row of sub-pixels. For example, as shown in FIG9A , the output signal terminals OUT1, OUT2, OUT3, and OUT4 of each shift register unit can be the first gate driver signal G1, the second gate driver signal G2, the third gate driver signal G3, and the light-emitting control signal EM required by the pixel circuit described above with reference to FIG1 and FIG2 . This will be described in detail below with reference to the signal timing of FIG9B .

[0192] FIG. 9B shows a signal timing diagram of the display driving circuit of FIG. 9A .

[0193] As shown in FIG9B , the display driver circuit receives four sequentially shifted narrow clock signals Clks1 to Clks4 and four wide clock signals Clkp1 to Clkp4. The clock signals Clks1, Clks2, Clks2, Clks3, Clks4, Clkp1, Clkp2, Clkp3, and Clkp4 are sequentially shifted by H in this order. Here, H represents the unit scan time, which is the time required to scan a row of subpixels, i.e., the time interval between generating the gate drive signal for one row of subpixels and generating the gate drive signal for the next row of subpixels. The duty cycle of the narrow clock signals is smaller than that of the wide clock signals. For example, the duty cycle of the wide clock signals can be twice that of the narrow clock signals. In FIG9B , the clock periods of the narrow clock signals Clks1 to Clks14 and the wide clock signals Clkp1 to Clkp4 are both 4 hours. The active level duration of the narrow clock signals Clks1 to Clks4 is H, while the active level duration of the wide clock signals Clkp1 to Clkp4 is 2 hours.

[0194] The first control signal Clka and the second control signal Clkb may have the same period and be relatively shifted, such that during a period when one of the first control signal Clka and the second control signal Clkb is at a high level, the other is at a low level. For example, in FIG9B , the active level durations of the first control signal Clka and the second control signal Clkb may be half an H, and the shift between the two may be H, such that the first control signal Clka and the second control signal Clkb are not at a high level at the same time.

[0195] In FIG. 9B , the shift register unit GOA in FIG. 9A at the nth stage <n>The signal timing of is illustrated as an example, and the shift register unit has the circuit structure described above with reference to FIG6. Combined with FIG6 and FIG9A, assuming n=2, the shift register unit GOA <2> The clock signal terminals CLK1 to CLK4 receive clock signals Clks3, Clks2, Clkp2 and Clks4 respectively. <2> The input signal terminal IN receives the previous stage shift register unit GOA <1> The signal CR at the cascade output <1> As input signal. Shift register unit GOA <2> The first control signal terminal CKA receives the second control signal Ckb, and the second control signal terminal CKB receives the first control signal Cka.

[0196] In the period t1, the signal CR outputted from the cascade output terminal of the preceding shift register unit is <n-1>(i.e., CR <1> ) is high, that is, the shift register unit GOA of FIG. 9A <2> The input signal terminal IN is at a high level. Referring to FIG6 , the high level of the input signal terminal IN turns on the transistor T8, thereby providing the signal of the second control signal terminal CKB to the intermediate node P. As can be seen from FIG9A , the intermediate node P follows the potential of the first control signal Cka received at the second control signal terminal CKB. During this period, since the second clock signal Ckb is at a low level, the shift register unit GOA of FIG9A <2> 6 , the transistor T14 is in the off state, the pull-up node Q is maintained at a low level, the transistor T3 and the transistors T1_1 , T1_2 , T1_3 and T1_4 are all in the off state, and the cascade output terminal CR and the output signal terminals OUT1 to OUT4 are all maintained at the original potential.

[0197] In the period t2, the second control signal Ckb is at a high level, that is, the shift register unit GOA in FIG9A <2> The first control signal terminal CKA is at a high level. Referring to FIG6 , the high level of the first control signal terminal CKA turns on transistors T14 and T15, and the high level of the input signal terminal IN is provided to the pull-up node Q and the node QH. The high level of the node QH turns on transistor T13, and the pull-down node QB is pulled down to the low level of the first reference signal terminal VGL1. The high level of the pull-up node Q turns on transistor T3, thereby providing the high level of the first power supply signal terminal GVDD1 to the cascade output terminal CR (as shown in FIG9A ). <n>As shown). The high level of the pull-up node Q also turns on the transistors T1_1, T1_2, T1_3 and T1_4. However, at this time, due to the shift register unit GOA <2> The clock signals Clks3, Clks2, Clkp2 and Clks4 received by the clock signal terminals CLK1 to CLK4 are all at a low level, so the output signal terminals OUT1 to OUT4 are all at a low level.

[0198] In period t3, the shift register unit GOA <2> The clock signals Clks2 and Clkp2 received by the clock signal terminals CLK2 and CLK3 are at a high level, while the clock signals Clks3 and Clks4 received by the clock signal terminals CLK1 and CLK4 are at a low level. Referring to FIG6 , the transistors T1_2 and T1_3 in the on state provide the high-level clock signals Clks2 and Clkp2 to the output signal terminals OUT2 and OUT3, while the transistors T1_1 and T1_4 in the on state provide the low-level clock signals Clks3 and Clks4 to the output signal terminals OUT1 and OUT4. Since the output signal terminals OUT2 and OUT3 are at a high level, the bootstrap effect of the capacitors C1_2 and C1_3 further increases the potential of the pull-up node Q.

[0199] In time period t4, the clock signals Clks3 and Clkp2 are at a high level, and the clock signals Clks2 and Clks4 are at a low level. The transistors T1_3 and T1_1 in the on state provide the high-level clock signals Clks3 and Clkp2 to the output signal terminals OUT3 and OUT1, and the transistors T1_2 and T1_4 in the on state provide the low-level clock signals Clks2 and Clks4 to the output signal terminals OUT1 and OUT4.

[0200] In time period t5, the clock signal Clks4 is at a high level, and the clock signals Clks2, Clks3 and Clkp2 are all at a low level. The transistor T1_4 in the on state provides the high-level clock signal Clks4 to the output signal terminal OUT4, and the transistors T1_2, T1_3 and T1_4 in the on state provide the low-level clock signals Clks2, Clks3 and Clkp2 to the output signal terminals OUT1, OUT3 and OUT4.

[0201] During period t6, the clock signals Clks3, Clks2, Clkp2, and Clks4 are all at low levels, causing the output signal terminals OUT1 to OUT4 to all be at low levels. The bootstrap effect of capacitors C1_1 to C1_4 causes the voltage of the pull-up node Q to drop. In this process, the signal CR outputted by the cascade output terminal of the previous stage shift register unit is <n-1>(i.e., CR <1> ) is low level, that is, the shift register unit GOA of FIG. 9A <2> The input signal terminal IN is at a low level. The first control signal Cka and the second control signal Ckb are both at a low level, that is, the shift register unit GOA <2> 6 , the low level of the input signal terminal IN and the second control signal terminal CKB turns off the transistors T7 and T8, and the intermediate node P remains at the original high level.

[0202] In the period t7, the second control signal Ckb becomes high level, and the shift register unit GOA <2> When the first control signal terminal CKA is at a high level, referring to Figure 6, transistors T14 and T15 are turned on, and the low level of the input signal terminal IN is provided to the pull-up node Q and node QH. The high level of the first control signal terminal CKA also turns on transistor T10. Transistors T9 and T10, which are in the on state, provide the high level of the first control signal terminal CKA to the pull-down node QB. The high level of the pull-down node QB turns on transistor T4 as well as transistors T2_1, T2_2, T2_3, and T2_4, resulting in low levels being output at the cascade output terminal CR and the output signal terminals OUT2, OUT3, and OUT4, and a high level being output at the output signal terminal OUT1.

[0203] At this point, the shift register GOA <2> The output of the display drive signal is completed. As shown in FIG9B , the shift register GOA <2> The signals output from the output signal terminals OUT1 to OUT4 can be used as the light-emitting control signal EM, the third gate drive signal G3, the second gate drive signal G2, and the first gate drive signal G1 of the pixel drive circuit described above with reference to Figures 1 and 2, respectively. As can be seen from Figure 9B, the duty cycles of the signals output by at least two of the K output signal terminals are different. For example, the duty cycle of the signal output by the output signal terminal OUT3 is greater than the duty cycle of the signals output by the output signal terminals OUT2 and OUT4. The so-called duty cycle here refers to the ratio of the duration of the effective level within a period (for example, within a frame) to the length of the period.

[0204] The other shift registers operate in a similar manner. The sub-pixels are arranged in an array, and the sub-pixels in the same row are driven by the same set of display drive signals. Since each shift register can generate multiple display drive signals required to drive a single sub-pixel, each shift register can provide the corresponding row of pixels with the multiple display drive signals required. For example, with reference to FIG9A , the first shift register GOA <1> Generates a light emitting control signal EM for driving the first row of sub-pixels <1> , first gate drive signal G1 <1> , the second gate drive signal G2 <1> and the third gate drive signal G3 <1> ; Second stage shift register GOA <2> Generates a light emitting control signal EM for driving the second row of sub-pixels <2> , first gate drive signal G1 <2> , the second gate drive signal G2 <2> and the third gate drive signal G3 <2> , and so on.

[0205] FIG10A is a schematic diagram of a display driver circuit according to another embodiment of the present disclosure. The shift register unit in the display driver circuit can be implemented as the shift register unit of any of the above-described embodiments, such as the shift register unit described above with reference to FIG6 . The display driver circuit of FIG10A is similar to the display driver circuit of FIG9A , differing at least in the connection method of the clock signal terminal. The following will mainly describe the differences in detail.

[0206] In the example of FIG. 10A , K=4, i=1, M=4, and N shift register units are also grouped into four. Each shift register unit GOA1 <1> , GOA1 <2> ,...,GOA1 <n>The four output units receive four corresponding clock signals at the four clock signal terminals CLK1 to CLK4 and generate four output signals at the four output signal terminals OUT1 to OUT4. As shown in FIG10A , taking the first group as an example, the first-stage shift register unit GOA1 in the first group <1> The first clock signal terminal CLK1 receives the fourth wide clock signal Clkp4, and the second stage shift register unit GOA1 <2> The first clock signal terminal CLK1 receives the first wide clock signal Clkp1, and the third stage shift register unit GOA1 <3> The first clock signal terminal CLK1 receives the second wide clock signal Clkp2, and the fourth stage shift register unit GOA1 <4> The first clock signal terminal CLK1 receives the third wide clock signal Clkp3. In a similar manner, the shift register unit GOA1 <1> To GOA1 <4> The second clock signal terminal CLK2 receives the second wide clock signal Clkp2, the third wide clock signal Clkp3, the fourth wide clock signal Clkp4 and the first wide clock signal Clkp1 respectively. <1> To GOA1 <4> The third clock signal terminal CLK3 receives the first wide clock signal Clkp1, the second wide clock signal Clkp2, the third wide clock signal Clkp3 and the fourth wide clock signal Clkp4 respectively. <1> To GOA1 <4> The fourth clock signal terminal CLK4 receives the third narrow clock signal Clks3, the fourth narrow clock signal Clks4, the first narrow clock signal Clks1 and the second narrow clock signal Clks2 respectively.

[0207] The clock signal terminals of other groups of shift register units are connected in the same manner. The connection manner of the first control signal terminal CKA and the second control signal terminal CKB of each shift register unit is the same as that described above with reference to FIG. 9A , and is not repeated here.

[0208] The output signals of the output signal terminals OUT1, OUT2, OUT3, and OUT4 of each shift register unit can be used as the first gate drive signal G1, the second gate drive signal G2, the first light-emitting control signal EM1, and the second light-emitting control signal EM2 required by the pixel circuit 1B. This will be described in detail below with reference to the signal timing of FIG. 10B.

[0209] FIG10B shows a signal timing diagram of the display driver circuit of FIG10A . As shown in FIG10B , the operation of each shift register unit in the display driver circuit is similar to that described above with reference to FIG9B , except that they are controlled by different clock signals to generate different display driver signals. The following will mainly describe the differences in detail.

[0210] 6, 10A and 10B, taking n=1 as an example, the shift register unit GOA <1> The clock signal terminals CLK1 to CLK4 receive clock signals Clkp4, Clkp2, Clkp1 and Clks3 respectively.

[0211] In the period t1, the shift register unit GOA <1> The input signal terminal IN is at a high level, and the transistor T8 of the shift register unit is turned on, thereby providing the signal of the second control signal terminal CKB to the intermediate node P. As can be seen from Figure 9A, the intermediate node P follows the potential of the first control signal Ckb received at the second control signal terminal CKB. During this period, since the first clock signal Cka is at a low level, the shift register unit GOA of Figure 10A <1> 6 , the transistor T14 is in the off state, the pull-up node Q is maintained at a low level, the transistor T3 and the transistors T1_1 , T1_2 , T1_3 and T1_4 are all in the off state, and the cascade output terminal CR and the output signal terminals OUT1 to OUT4 are all maintained at the original potential.

[0212] In the period t2, the first control signal Cka is at a high level, that is, the shift register unit GOA in FIG. 10A <1> The first control signal terminal CKA is at a high level. Referring to FIG6 , the high level of the first control signal terminal CKA turns on transistors T14 and T15, and the high level of the input signal terminal IN is provided to the pull-up node Q and the node QH. The high level of the node QH turns on transistor T13, and the pull-down node QB is pulled down to the low level of the first reference signal terminal VGL1. The high level of the pull-up node Q turns on transistor T3, thereby providing the high level of the first power supply signal terminal GVDD1 to the cascade output terminal CR (as shown in FIG10B ). <n>As shown). The high level of the pull-up node Q also turns on the transistors T1_1, T1_2, T1_3 and T1_4. <1> The clock signals Clkp4 and Clkp1 received by the clock signal terminals CLK1 and CLK3 are at a high level, and the clock signals Clkp2 and Clks3 received by the clock signal terminals CLK2 and CLK4 are at a low level, so the output signal terminals OUT1 and OUT3 are at a high level, and the output signal terminals OUT2 and OUT4 are at a low level.

[0213] During the period t3 to t5, the shift register unit GOA <1> The working mode is similar to the working mode of the period t3 to t5 in Figure 9B, so that the first output unit 250_1 generates an output signal at the first output signal terminal OUT1 based on the clock signal Clkp4, the second output unit 250_2 generates an output signal at the output signal terminal OUT2 based on the clock signal Clkp2, the third output unit 250_3 generates an output signal at the output signal terminal OUT3 based on the clock signal Clkp1, and the fourth output unit 250_4 generates an output signal at the output signal terminal OUT4 based on the clock signal Clks3, as shown in Figure 10B, which will not be repeated here.

[0214] In period t6, the clock signals Clkp4 and Clkp1 are at a high level, and the clock signals Clkp2 and Clks3 are at a low level, so that the output signal terminals OUT1 and OUT3 are at a high level, and the output signal terminals OUT2 and OUT4 are at a low level. <1> The start signal received by the input signal terminal IN, the shift register unit GOA <2> 6 , the low levels of the input signal terminal IN and the second control signal terminal CKB turn off transistors T7 and T8, and the intermediate node P remains at the original high level.

[0215] In period t7, the shift register unit GOA <1> When the first control signal Clka received at the first control signal terminal CKA becomes high, referring to Figure 6, transistors T14 and T15 are turned on, and the low level of the input signal terminal IN is provided to the pull-up node Q and the node QH. The high level of the first control signal terminal CKA also turns on transistor T10. Transistors T9 and T10, which are in the on state, provide the high level of the first control signal terminal CKA to the pull-down node QB. The high level of the pull-down node QB turns on transistor T4 as well as transistors T2_1, T2_2, T2_3, and T2_4, resulting in a low level output at the cascade output terminal CR and the output signal terminals OUT2 and OUT4, and a high level output at the output signal terminals OUT1 and OUT3.

[0216] At this point, the shift register GOA <1> The output of the display drive signal is completed. As shown in FIG10B, the shift register GOA <1> The signals outputted from the output signal terminals OUT1 to OUT4 may be respectively used as the second light emitting control signal EM2, the second gate driving signal G2, the first light emitting control signal EM1 and the first gate driving signal G1 of the pixel driving circuit 10B.

[0217] The other stages of the shift register operate in a similar manner, so that each stage of the shift register can provide a plurality of display driving signals required by a corresponding row of pixels. <1> Generate a first light emitting control signal EM1 for driving the first row of sub-pixels <1> , the second light emitting control signal EM2 <1> , first gate drive signal G1 <1> and the second gate drive signal G2 <1> ; Second stage shift register GOA <2> Generate a first light emitting control signal EM1 for driving the second row of sub-pixels <2> , the second light emitting control signal EM2 <2> , first gate drive signal G1 <2> and the second gate drive signal G2 <2> , and so on.

[0218] FIG11A is a schematic diagram of a display driver circuit according to another embodiment of the present disclosure. The shift register unit in the display driver circuit can be implemented as the shift register unit of any of the above-described embodiments, such as the shift register unit described above with reference to FIG8 . The display driver circuit of FIG11A is similar to the display driver circuit of FIG9A , differing at least in the connection method of the clock signal terminal. The following will mainly describe the differences in detail.

[0219] In the example of FIG11A , K=3, i=1, and M=4. N shift register units are also grouped into four, and each shift register unit GOA1 <1> , GOA1 <2> ,...,GOA1 <n>The three output units receive three corresponding clock signals at the three clock signal terminals CLK1 to CLK3 and generate three output signals at the three output signal terminals OUT1 to OUT3. As shown in FIG11A , taking the first group as an example, the first-stage shift register unit GOA1 in the first group <1> The first clock signal terminal CLK1 receives the third narrow clock signal Clks3, and the second stage shift register unit GOA1 <2> The first clock signal terminal CLK1 receives the fourth narrow clock signal Clks4, and the third stage shift register unit GOA1 <3> The first clock signal terminal CLK1 receives the first narrow clock signal Clks1, and the fourth stage shift register unit GOA1 <4> The first clock signal terminal CLK1 receives the second narrow clock signal Clks2. In a similar manner, the shift register unit GOA1 <1> To GOA1 <4> The second clock signal terminal CLK2 receives the second wide clock signal Clkp2, the third wide clock signal Clkp3, the fourth wide clock signal Clkp4 and the first wide clock signal Clkp1 respectively. <1> To GOA1 <4> The third clock signal terminal CLK3 receives the second narrow clock signal Clks2, the third narrow clock signal Clks3, the fourth narrow clock signal Clks4 and the first narrow clock signal Clks1 respectively.

[0220] The clock signal terminals of the other groups of shift register units are connected in the same manner, which will not be described in detail here. The other signal terminals of each shift register unit, such as the control signal terminal, the power signal terminal and the reference signal terminal, can be connected in the same manner as described above with reference to FIG. 9A , which will not be described in detail here.

[0221] The output signals of the output signal terminals OUT1, OUT2 and OUT3 of the shift register unit can be used as the light emitting control signal EM, the first gate driving signal G1 and the second gate driving signal G2 required by the pixel circuit 10C, respectively.

[0222] FIG11B shows a signal timing diagram of the display driver circuit of FIG11A . As shown in FIG11B , the operation of each shift register unit in the display driver circuit is similar to that described above with reference to FIG9B , except that they are controlled by different clock signals to generate different display driver signals. The following will mainly describe the differences in detail.

[0223] 8, 11A and 11B, taking n=1 as an example, the shift register unit GOA <1> The clock signal terminals CLK1 to CLK3 receive clock signals Clks3, Clkp2 and Clks2 respectively.

[0224] In the period t1, the shift register unit GOA <1> The input signal terminal IN is at a high level, and the transistor T8 of the shift register unit is turned on, thereby providing the signal of the second control signal terminal CKB to the intermediate node P. As can be seen from Figure 9A, the intermediate node P follows the potential of the first control signal Ckb received at the second control signal terminal CKB. During this period, since the first clock signal Cka is at a low level, the shift register unit GOA <1> The first control signal terminal CKA is at a low level. Referring to FIG8 , the transistor T14 is in the off state, the pull-up node Q is maintained at a low level, the transistor T3 and the transistors T1_1, T1_2, T1_3 and T1_4 are all in the off state, and the cascade output terminal CR and the output signal terminals OUT1 to OUT4 are all maintained at the original potential.

[0225] In period t2, the shift register unit GOA <1> The first control signal Cka received by the first control signal terminal CKA is at a high level. Referring to FIG8 , the high level of the first control signal terminal CKA turns on transistors T14 and T15, and the high level of the input signal terminal IN is provided to the pull-up node Q and the node QH. The high level of the node QH turns on transistor T13, and the pull-down node QB is pulled down to the low level of the first reference signal terminal VGL1. The high level of the pull-up node Q turns on transistor T3, thereby providing the high level of the first power supply signal terminal GVDD1 to the cascade output terminal CR (as shown in FIG10B ). <n>As shown). The high level of the pull-up node Q also turns on the transistors T1_1, T1_2, T1_3 and T1_4. <1> The clock signals Clks3, Clkp2 and Clks2 received by the clock signal terminals CLK1 to CLK3 are all at a low level, so the output signal terminals OUT1 to OUT3 are all at a low level.

[0226] During the period t3 to t5, the shift register unit GOA <1> The working mode is similar to the working mode of the period t3 to t5 in Figure 9B, so that the first output unit 350_1 generates an output signal at the first output signal terminal OUT1 based on the clock signal Clks3, the second output unit 350_2 generates an output signal at the output signal terminal OUT2 based on the clock signal Clkp2, and the third output unit 350_3 generates an output signal at the output signal terminal OUT3 based on the clock signal Clks2, as shown in Figure 11B, which will not be repeated here.

[0227] In the period t6, the clock signals Clks3, Clkp2 and Clks2 are all at a low level, so that the output signal terminals OUT1 to OUT3 are all at a low level. <1> The start signal received by the input signal terminal IN, the shift register unit GOA <2> The first control signal Clka received by the first control signal terminal CKA and the second control signal Clkb received by the second control signal terminal CKB are both low. Referring to FIG8 , the low levels of the input signal terminal IN and the second control signal terminal CKB turn off transistors T7 and T8, and the intermediate node P remains at the original high level.

[0228] In period t7, the shift register unit GOA <1> When the first control signal Clka received at the first control signal terminal CKA becomes high, referring to Figure 8, transistors T14 and T15 are turned on, and the low level of the input signal terminal IN is provided to the pull-up node Q and the node QH. The high level of the first control signal terminal CKA also turns on transistor T10. Transistors T9 and T10, which are in the on state, provide the high level of the first control signal terminal CKA to the pull-down node QB. The high level of the pull-down node QB turns on transistor T4 as well as transistors T2_1, T2_2, T2_3, and T2_4, resulting in a low level output at the cascade output terminal CR and the output signal terminals OUT2 and OUT3, and a high level output at the output signal terminal OUT1.

[0229] At this point, the shift register GOA <1> The output of the display drive signal is completed. As shown in FIG11B, the shift register GOA <1> The signals outputted from the output signal terminals OUT1 to OUT3 can be used as the light emitting control signal EM, the first gate driving signal G1 and the first gate driving signal G2 of the pixel circuit 10C, respectively.

[0230] The other stages of the shift register operate in a similar manner, so that each stage of the shift register can provide a plurality of display driving signals required by a corresponding row of pixels. <1> Generates a light emitting control signal EM for driving the first row of sub-pixels <1> , first gate drive signal G1 <1> and the second gate drive signal G2 <1> ; Second stage shift register GOA <2> Generates a light emitting control signal EM for driving the second row of sub-pixels <2> , first gate drive signal G1 <2> and the second gate drive signal G2 <2> , and so on.

[0231] FIG12A is a schematic diagram of a display driver circuit according to another embodiment of the present disclosure. The shift register unit in the display driver circuit can be implemented as the shift register unit of any of the above-described embodiments, such as the shift register unit described above with reference to FIG6 . The display driver circuit of FIG12A is similar to the display driver circuit of FIG9A , differing at least in the connection method of the clock signal terminals, the number of clock signals, and the duty cycle. The differences will be described in detail below.

[0232] In the example of FIG12A, K=4, i=1, M=16, and the display driving circuit receives 16 narrow clock signals Clks1 to Clks16 and 16 wide clock signals Clkp1 to Clkp16 that are shifted sequentially. N shift register units are grouped into 16 units, for example, the first group includes shift register unit GOA1. <1> To GOA1 <16> , the second group includes shift register unit GOA1 <17> To GOA1 <32> , and so on. Each shift register unit GOA1 <1> , GOA1 <2> ,...,GOA1 <n>The four output units respectively receive four corresponding clock signals at four clock signal terminals CLK1 to CLK4 and correspondingly generate four output signals at four output signal terminals OUT1 to OUT4.

[0233] As shown in FIG12A , in the first group, the first to sixteenth shift register units GOA1 <1> To GOA1 <16> The first clock signal terminal CLK1 is respectively shifted from the third wide clock signal Clkp3 to 16 wide clock signals, namely, Clkp3, Clkp4, Clkp5, Clkp6, Clkp7, Clkp8, Clkp9, Clkp10, Clkp11, Clkp12, Clkp13, Clkp14, Clkp15, Clkp16, Clkp1, Clkp2. That is, the first stage shift register unit GOA1 <1> The first clock signal terminal CLK1 receives the third wide clock signal Clkp3; the second stage shift register unit GOA1 <2> The first clock signal terminal CLK1 receives the next clock signal shifted relative to the third wide clock signal Clkp3, that is, the fourth wide clock signal Clkp4, and so on until the 16th stage shift register unit GOA1 <16> The first clock signal terminal CLK1 receives a next clock signal shifted relative to the first wide clock signal Clkp1 , ie, the second wide clock signal Clkp2 .

[0234] In a similar manner, the shift register unit GOA1 <1> To GOA1 <16> The second clock signal terminal CLK2 receives 16 narrow clock signals sequentially shifted starting from the fourteenth narrow clock signal Clks14, namely Clks14, Clks15, Clks16, Clks1, Clks2, Clks3, Clks4, Clks5, Clks6, Clks7, Clks7, Clks8, Clks9, Clks10, Clks11, Clks12, and Clks13. The shift register unit GOA1 <1> to GOA1 <16> The third clock signal terminal CLK3 receives 16 wide clock signals, namely Clkp1 to Clkp16, which are sequentially shifted starting from the first wide clock signal Clkp1. <1> to GOA1 <16> The fourth clock signal terminal CLK4 receives 16 narrow clock signals, ie, Clks1 to Clks16, which are sequentially shifted starting from the first narrow clock signal Clks1.

[0235] The clock signal terminals of the other groups of shift register units are connected in the same way. For example, for the second group of shift register units GOA1 <17> To GOA1 <32> , GOA1 <17> The clock signal terminal is connected to GOA1 <1> Same, GOA1 <18> The clock signal terminal is connected to GOA1 <2> The other signal terminals of each shift register unit, such as the control signal terminal, the power signal terminal and the reference signal terminal, can be connected in the same manner as described above with reference to FIG9A , which will not be described in detail here.

[0236] Each shift register unit can provide the emission control signal EM, the first gate drive signal G1, the second gate drive signal G2, and the third gate drive signal G3 required by the pixel circuit described above with reference to Figures 1 and 2 at the output signal terminals OUT1, OUT2, OUT3, and OUT4. Unlike Figures 9A and 9B, the compensation period is longer, which will be explained in detail below with reference to the signal timing of Figure 12B.

[0237] FIG12B shows a signal timing diagram of the display driver circuit of FIG12A . As shown in FIG12B , the operation of each shift register unit in the display driver circuit is similar to that described above with reference to FIG9B , except that they are controlled by different clock signals to generate different display driver signals. The following will mainly describe the differences in detail.

[0238] As shown in FIG12B , the display driver circuit receives 16 sequentially shifted narrow clock signals Clks1 to Clks16 and 16 wide clock signals Clkp1 to Clkp16. The narrow clock signals Clks1 to Clks16 and the wide clock signals Clkp1 to Clkp16 have the same period, and the duty cycle of the narrow clock signals Clks1 to Clks16 is smaller than the duty cycle of the wide clock signals Clkp1 to Clkp16. In FIG12B , the clock period of the narrow clock signals Clks1 to Clks16 and the wide clock signals Clkp1 to Clkp16 are both 16 hours. The active level duration of the narrow clock signals Clks1 to Clks16 is 2 hours, while the active level duration of the wide clock signals Clkp1 to Clkp16 is 11 hours.

[0239] 6, 12A and 12B, taking n=1 as an example, the shift register unit GOA <1> The clock signal terminals CLK1 to CLK4 receive clock signals Clkp3, Clks14, Clkp1 and Clks1 respectively.

[0240] As shown in FIG12B , the shift register unit GOA <1> The operations performed in the time period t1 to t7 are substantially the same as the time period t7 to t7 described above with reference to FIG9B , so that the first output unit 250_1 generates an output signal at the first output signal terminal OUT1 based on the clock signal Clkp3, the second output unit 250_2 generates an output signal at the output signal terminal OUT2 based on the clock signal Clks14, the third output unit 250_3 generates an output signal at the output signal terminal OUT3 based on the clock signal Clkp1, and the fourth output unit 250_4 generates an output signal at the output signal terminal OUT4 based on the clock signal Clks1.

[0241] The other stages of the shift register operate in a similar manner, so that each stage of the shift register can provide a plurality of display drive signals required by a corresponding row of pixels. <1> Generates a light emitting control signal EM for driving the first row of sub-pixels <1> , first gate drive signal G1 <1> and the second gate drive signal G2 <1> ; Second stage shift register GOA <2> Generates a light emitting control signal EM for driving the second row of sub-pixels <2> , first gate drive signal G1 <2> and the second gate drive signal G2 <2> , and so on.

[0242] Compared to FIG9B , the effective level duration of the clock signal in FIG12B is longer, and the duty cycle difference between the wide clock signal and the narrow clock signal is greater. This allows the period t4 for performing threshold voltage compensation to be longer, for example, up to 9 hours, when the display drive signal output by the shift register unit is used to drive the sub-pixel for display. This helps further reduce the impact of the threshold voltage on the output signal.

[0243] Figures 13A and 13B show a circuit diagram of a display driver circuit according to another embodiment of the present disclosure. The shift register unit in the display driver circuit can be implemented as the shift register unit of any of the above-mentioned embodiments, such as the shift register unit described above with reference to Figure 6. The display driver circuit of Figures 13A and 13B is similar to the display driver circuit of Figure 9A, except that at least the fourth clock signal terminal CLK4 of each shift register unit is electrically connected to the power signal terminal (second power signal terminal GVDD2). In addition, the connection method of the clock signal terminal in Figures 13A and 13B and the number and waveform of the clock signals are also different from those in Figure 9A. The following will mainly describe the differences in detail.

[0244] In the example of FIG13A and FIG13B, K=4, i=1, M=8. The display driving circuit receives 8 narrow clock signals Clks1 to Clks8 and 8 wide clock signals Clkp1 to Clkp8 that are shifted sequentially. N shift register units are grouped into 8 units. For example, the first group includes shift register unit GOA1. <1> To GOA1 <8> , the second group includes shift register unit GOA1 <9> To GOA1 <16> Each shift register unit has four clock signal terminals CLK1 to CLK4 and four output signal terminals OUT1 to OUT4. Each shift register unit generates four output signals at the output signal terminals OUT1 to OUT4 based on the signals at the clock signal terminals CLK1 to CLK4.

[0245] As shown in FIG13A , in the first group, the first to eighth stage shift register units GOA1 <1> To GOA1 <8> The first clock signal terminal CLK1 is respectively shifted from the second wide clock signal Clkp2 to the eight wide clock signals, namely, Clkp2, Clkp3, Clkp4, Clkp5, Clkp6, Clkp7, Clkp8, Clkp1. In a similar manner, the shift register unit GOA1 <1> To GOA1 <8> The second clock signal terminal CLK2 receives eight narrow clock signals sequentially shifted starting from the seventh narrow clock signal Clks7, namely Clks7, Clks8, Clks1, Clks2, Clks3, Clks4, Clks5, and Clks6. The shift register unit GOA1 <1> To GOA1 <8> The third clock signal terminal CLK3 receives eight narrow clock signals, namely Clks1 to Clks8, which are sequentially shifted starting from the first narrow clock signal Clks1. <1> To GOA1 <8> The fourth clock signal terminal CLK4 is electrically connected to the second power signal terminal GVDD2 of the shift register unit, so that the fourth clock signal terminal CLK4 and the second power signal terminal GVDD2 receive the same signal, ie, the second power signal Gvdd2.

[0246] The clock signal terminals of the other groups of shift register units are connected in the same manner. For example, as shown in FIG13B , for the second group of shift register units GOA1 <9> To GOA1 <16> , GOA1 <9> The clock signal terminal is connected to GOA1 <1> Same, GOA1 <10> The clock signal terminal is connected to GOA1 <2> The other signal terminals of each shift register unit, such as the control signal terminal, the power signal terminal and the reference signal terminal, can receive corresponding signals in the manner described above with reference to FIG9A , which will not be described in detail here.

[0247] The output signals from the four output terminals OUT1 to OUT4 of each shift register stage can be used as the light-emission control signal EM, the first gate drive signal G1, the second gate drive signal G2, and the third gate drive signal G3 required for the aforementioned pixel circuit 10B. Unlike FIG9A , a portion of the output signal from one shift register unit and a portion of the output signal from another shift register unit together form the complete display drive signal required for a single sub-pixel. This will be described in detail below with reference to FIG13C .

[0248] FIG. 13C shows a signal timing diagram of the display driving circuit of FIG. 13A and FIG. 13B .

[0249] As shown in FIG13C , the operation mode of each shift register unit in the display driving circuit is similar to the operation mode described above with reference to FIG9B , with at least one difference being that the two shift register units cooperate with each other to provide display driving signals to the same row of sub-pixels. The following will mainly describe the differences in detail.

[0250] As shown in FIG13C , the display driver circuit receives eight narrow clock signals Clks1 to Clks8 and eight wide clock signals Clkp1 to Clkp8 that are sequentially shifted. The narrow clock signals Clks1 to Clks8 have the same period as the wide clock signals Clkp1 to Clkp8, and the duty cycle of the narrow clock signals Clks1 to Clks8 is smaller than that of the wide clock signals Clkp1 to Clkp8. In FIG13C , the duty cycle of the narrow clock signals Clks1 to Clks8 and the clock period of the wide clock signals Clkp1 to Clkp8 are both 16 hours. The active level duration of the narrow clock signals Clks1 to Clks16 is 1.5 hours, while the active level duration of the wide clock signals Clkp1 to Clkp16 is 9 hours. The shift between adjacent clock signals is 2 hours.

[0251] 6, 13A and 13B, taking n=9 as an example, the nth stage shift register unit GOA <9> With the shift register unit GOA <1> The connection mode is the same, that is, the clock signal terminals CLK1 to CLK4 receive the clock signals Clkp2, Clks7, Clks1 and the second power signal Gvdd2 respectively, the first control signal terminal CKA receives the first control signal Clka, and the second control signal terminal CKB receives the second control signal Clkb.

[0252] As shown in FIG13B, during period t1, the shift register unit GOA of FIG13A <9> The input signal terminal IN receives the signal output by the cascade output terminal of the previous stage shift register unit (ie, CR <8> ) is high. During this period, due to the shift register unit GOA <9> The first control signal Clka received by the first control signal terminal CKA is at a low level, the transistor T14 is in a turned-off state, the pull-up node Q is maintained at a low level, the transistor T3 and the transistors T1_1, T1_2, T1_3 and T1_4 are all in a turned-off state, and the cascade output terminal CR and the output signal terminals OUT1 to OUT4 are all maintained at the original potential.

[0253] In period t2, the shift register unit GOA <9> The first control signal Cka received by the first control signal terminal CKA is at a high level. Referring to Figure 6, the high level of the first control signal terminal CKA turns on the transistors T14 and T15, and the high level of the input signal terminal IN is provided to the pull-up node Q and the node QH. The high level of the node QH turns on the transistor T13, and the pull-down node QB is pulled down to the low level of the first reference signal terminal VGL1. The high level of the pull-up node Q turns on the transistor T3, thereby providing the high level of the first power supply signal terminal GVDD1 to the cascade output terminal CR. The high level of the pull-up node Q also turns on the transistors T1_1, T1_2, T1_3 and T1_4. At this time, due to the shift register unit GOA <9> The clock signals Clkp2, Clks7, and Clks1 received by the clock signal terminals CLK1 to CLK3 are all at low levels, so the output signal terminals OUT1 to OUT3 are all at low levels; <9> The second power supply signal Gvdd2 received by the clock signal terminal CLK4 is at a high level, so the output signal terminal OUT4 is at a high level.

[0254] During the period t3 to t5, the pull-up node Q is kept at a high level, and the shift register unit GOA <9> The transistors T1_1 , T1_2 , T1_3 and T1_4 in the transistor 1_1 are in the on state, thereby providing Clkp2 , Clks7 , Clks1 and Gvdd2 to the output signal terminals OUT1 and OUT4 , respectively.

[0255] In period t6, the shift register unit GOA <9> The first control signal Clka received at the first control signal terminal CKA is at a high level, and the input signal terminal IN is at a low level. Referring to Figure 6, transistors T14 and T15 are turned on, and the low level of the input signal terminal IN is provided to the pull-up node Q and the node QH. The high level of the first control signal terminal CKA also turns on transistor T10, thereby providing the high level of the first control signal terminal CKA to the pull-down node QB. The high level of the pull-down node QB turns on transistor T4 as well as transistors T2_1, T2_2, T2_3, and T2_4, resulting in a low level output at the cascade output terminal CR and the output signal terminals OUT2, OUT3, and OUT4, and a high level output at the output signal terminal OUT1.

[0256] At this point, the shift register GOA <9> The output of the display drive signal is completed.

[0257] The shift registers of other stages operate in a similar manner, thereby generating output signals at respective four output terminals OUT1 to OUT4.

[0258] The output signals of the four output terminals OUT1 to OUT4 of each stage of the shift register can serve as the light-emitting control signal EM, the first gate drive signal G1, the third gate drive signal G3, and the second gate drive signal G2, respectively. Part of the output signal of one shift register unit can be combined with part of the output signal of another shift register unit to form the display drive signal required for a single sub-pixel. For example, the nth stage shift register GOA <n>The signals outputted from the output signal terminals OUT1 to OUT3 can be used as the light emitting control signals EM for driving the sub-pixels in the n-2th row. <n-2>, first gate drive signal G1 <n-2>and the third gate drive signal G3 <n-2>, the n-2th stage shift register GOA <n-2>The output signal of the output signal terminal OUT4 can be used as the second gate driving signal G2 to drive the sub-pixels in the n-2th row. <n-2>As shown in FIG13A and FIG13B, the shift register unit GOA <1> and shift register unit GOA <3> Provide the required display driving signal to the first row of sub-pixels, specifically, the shift register unit GOA <1> The output signal of the output signal terminal OUT4 is used as the second gate drive signal G2 for driving the first row of sub-pixels <1> , shift register unit GOA <3> The output signals of the output signal terminals OUT1 to OUT3 are used as the light emitting control signals EM for driving the sub-pixels in the first row. <1> , first gate drive signal G1 <1> and the third gate drive signal G3 <1> In a similar manner, the shift register unit GOA <2> The output signal terminal OUT4 and the shift register unit GOA <4> The output signals of the output signal terminals OUT1 to OUT3 are used as the second gate drive signal G2 for driving the second row of sub-pixels <2> , light control signal EM <2> , first gate drive signal G1 <2> and the third gate drive signal G3 <2> , and so on. The first two stages of shift register unit GOA <1> and GOA <2> The output signal terminals OUT1 to OUT3 may be set to be redundant (Dummy), that is, not connected to any sub-pixel.

[0259] The embodiments of the present disclosure further provide a control method for a shift register unit, which is applicable to the shift register unit of any of the above embodiments. The method may include an input stage, an output stage, and a reset stage.

[0260] During the input phase, the input circuit inputs a first-level signal from the input signal terminal to the pull-up node. During the output phase, the potential of the pull-up node causes the pull-down circuit to pull down the potential of the pull-down node. The potentials of the pull-up and pull-down nodes cause the cascade output circuit to provide a signal from the power supply signal terminal to the cascade output terminal. The K output units of the signal output circuit each provide a signal from the clock signal terminal connected to the corresponding output signal terminal. During the reset phase, the input circuit inputs a second-level signal from the input signal terminal to the pull-up node. The pull-up circuit pulls up the potential of the pull-down node based on the potential of the input signal terminal. The potentials of the pull-up and pull-down nodes cause the cascade output circuit to provide a signal from the reference signal terminal to the cascade output terminal. The K output units of the signal output circuit each provide a signal from the power supply signal terminal or the reference signal terminal connected to the corresponding output signal terminal.

[0261] Taking the various embodiments described above with reference to Figures 9A to 12B as an example, the input phase may include period t1, the output phase may include periods t2 to t6, and the reset phase may include period t7. Taking the embodiments described above with reference to Figures 13A to 13C as an example, the input phase may include period t1, the output phase may include periods t2 to t5, and the reset phase may include period t6. The first level may be a high level, and the second level may be a low level.

[0262] FIG14 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0263] As shown in Figure 14, the display panel displays a display driving circuit 410 and a plurality of sub-pixels 420 arranged in an array. The display driving circuit 410 may be any of the above embodiments, such as the display driving circuit described above with reference to Figures 9A to 12B.

[0264] The K output signal terminals of the n-th stage shift register unit in the display driving circuit 410 are connected to the n-th row of sub-pixels to provide the K display driving signals required by the n-th row of sub-pixels. Taking the display driving circuit 410 as an example of being implemented by the display driving circuit described above with reference to FIG. 9A and FIG. 9B , as shown in FIG. 14 , the first stage shift register unit GOA <1> The four output signal terminals are connected to the first row of sub-pixels through four signal lines, respectively, to provide the first gate drive signal G1 to the first row of sub-pixels. <1> , the second gate drive signal G2 <1> , the third gate drive signal G3 <1> and the light emission control signal EM <1> ; Second stage shift register unit GOA <2> The four output signal terminals are connected to the second row of sub-pixels to provide the first gate drive signal G1 to the second row of sub-pixels. <2> , the second gate drive signal G2 <2> , the third gate drive signal G3 <2> and the light emission control signal EM <2> , and so on. However, the embodiments of the present disclosure are not limited thereto, and different display driving circuits can be provided as needed. For example, in the case where the sub-pixel 420 has the circuit structure of the above-mentioned pixel circuit 10B, the display driving circuit 410 can be implemented as the display driving circuit described above with reference to Figures 10A and 10B, and each stage of the shift register unit provides the first light-emitting control signal EM1, the second light-emitting control signal EM2, the first gate driving signal G1, and the second gate driving signal G2 to the corresponding row of sub-pixels. For another example, in the case where the sub-pixel 420 has the circuit structure of the above-mentioned pixel circuit 10C, the display driving circuit 410 can be implemented as the display driving circuit described above with reference to Figures 11A and 11B, and so on.

[0265] The plurality of sub-pixels 420 also receive data signals via a plurality of data signal lines D1 to DM. Each row of sub-pixels 420 emits light based on the received data signals under the control of the display driving signals output by the display driving circuit 410, thereby realizing image display.

[0266] Figure 15 shows a schematic diagram of a display panel according to another embodiment of the present disclosure. Unlike Figure 14, the K1 output signal terminals of the n-th stage shift register unit and the K2 output signal terminals of the n+j-th stage shift register unit are connected to the n-th row of sub-pixels to provide K display drive signals to the n-th row of sub-pixels, where K1+K2=K, and j is an integer greater than 1.

[0267] As shown in FIG15 , the display panel displays a driving circuit 510 and a plurality of sub-pixels 520 arranged in an array. The display driving circuit 510 can be the display driving circuit of any of the above embodiments, such as the display driving circuit described above with reference to FIG13A to FIG13C . In this case, j=2, K1=1, and K2=3. In conjunction with FIG13A and FIG13B , the first-stage shift register unit GOA <1> An output terminal and the third-stage shift register unit GOA <3> The three output terminals of the first row of sub-pixels are connected to provide the display driving signal EM1 to the first row of sub-pixels. <1> 、G1 <1> , G2 <1> and G3 <1> Specifically, the shift register unit GOA <1> The fourth output signal terminal OUT4 is connected to the first row of sub-pixels to provide the second gate driving signal G2 to the first row of sub-pixels. <1> , shift register unit GOA <3> The output signal terminals OUT1 to OUT3 are connected to the first row of sub-pixels to provide the light emitting control signal EM to the first row of sub-pixels. <1> , first gate drive signal G1 <1> and the third gate drive signal G3 <1> In a similar manner, the second stage shift register unit GOA <2> The output signal terminal OUT4 and the fourth stage shift register unit GOA <4> The output signal terminals OUT1 to OUT3 are connected to the second row of sub-pixels to provide the second gate driving signal G2 required to drive the second row of sub-pixels. <2> , light control signal EM <2> , first gate drive signal G1 <2> and the third gate drive signal G3 <2> , and so on. The first two stages of shift register unit GOA <1> and GOA <2> The output signal terminals OUT1 to OUT3 may be set to be redundant (Dummy), that is, not connected to any sub-pixel.

[0268] Those skilled in the art will appreciate that the embodiments described above are exemplary and that they may be improved upon. The structures described in the various embodiments may be freely combined without causing any conflict in structure or principle.

[0269] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art will clearly understand that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and that the present disclosure is not limited to the exemplary embodiments described in the specification. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A shift register unit, comprising: An input circuit, connected to an input signal terminal of the shift register unit, and used for inputting a signal of the input signal terminal to the pull-up node; a pull-up circuit connected to the input signal terminal and a pull-down node of the shift register unit, and configured to pull up the potential of the pull-down node based on the potential of the input signal terminal; a pull-down circuit, connected to the pull-up node and the pull-down node, for pulling down the potential of the pull-down node based on the potential of the pull-up node; a cascade output circuit, connected to the pull-up node, the pull-down node, and the power signal terminal, the reference signal terminal, and the cascade output terminal of the shift register unit, and configured to provide a signal of one of the power signal terminal and the reference signal terminal to the cascade output terminal under the control of the pull-up node and the pull-down node; as well as A signal output circuit is connected to the K clock signal terminals and the K output signal terminals of the shift register unit, and is used to generate K driving signals required to drive the sub-pixels, wherein the duty ratios of the signals output by at least two of the K output signal terminals are different, and the K driving signals include a gate driving signal and a light emitting control signal, wherein K is an integer greater than 1, wherein the signal output circuit comprises K output units, the kth output unit being connected to the pull-up node, the pull-down node, the kth clock signal terminal and the kth output signal terminal, wherein 1≤k≤K; At least one of the output units is further connected to a power signal terminal, and is used to provide a signal of one of the connected clock signal terminal and the power signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node; At least another output unit is also connected to a reference signal terminal, and is used to provide a signal from one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

2. The shift register unit according to claim 1, wherein: Each output unit comprises a first output subcircuit and a second output subcircuit, each of the first output subcircuit and the second output subcircuit having a control terminal, an input terminal and an output terminal and being used to provide a signal of the input terminal to the output terminal under the control of the control terminal; in: The control end of the first output sub-circuit is connected to the first pull-up node, the input end of the first output sub-circuit is connected to the corresponding clock signal end, and the output end of the first output sub-circuit is connected to the corresponding output signal end; The control end of the second output sub-circuit is connected to the pull-down node, and the input end of the second output sub-circuit is connected to the pull-down node. The output end of the second output sub-circuit is connected to the power signal end and / or the reference signal end, and the output end of the second output sub-circuit is connected to the corresponding output signal end.

3. The shift register unit according to claim 1 , wherein: The first output subcircuit includes a first transistor and a first capacitor, the gate of the first transistor serves as a control terminal of the first output subcircuit, the first electrode of the first transistor serves as an input terminal of the first output subcircuit, the second electrode of the first transistor serves as an output terminal of the output subcircuit, the first electrode of the first capacitor is connected to the gate of the first transistor, and the second electrode of the first capacitor is connected to the second electrode of the first transistor; The second output subcircuit includes a second transistor, a gate of the second transistor serves as a control terminal of the second output subcircuit, a first electrode of the second transistor serves as an input terminal of the second output subcircuit, and a second electrode of the second transistor serves as an output terminal of the second output subcircuit.

4. The shift register unit according to any one of claims 1 to 3, wherein: One of the K clock signal terminals is electrically connected to the power signal terminal.

5. The shift register unit according to any one of claims 1 to 4, wherein: The cascade output circuit comprises: A first cascade sub-circuit, connected to the pull-up node, the power signal terminal and the cascade output terminal, for providing a signal from the power signal terminal to the cascade output terminal under the control of the pull-up node; The second cascade sub-circuit is connected to the pull-down node, the reference signal terminal and the cascade output terminal, and is used for providing the signal of the reference signal terminal to the cascade output terminal under the control of the pull-down node.

6. The shift register unit according to claim 5, wherein: The first cascade sub-circuit comprises a third transistor and a second capacitor, wherein the gate of the third transistor is connected to the pull-up node, the first electrode of the third transistor is connected to the power signal terminal, the second electrode of the third transistor is connected to the cascade output terminal, the first electrode of the second capacitor is connected to the gate of the third transistor, and the second electrode of the second capacitor is connected to the second electrode of the third transistor; The second cascade sub-circuit includes a fourth transistor and a third capacitor, wherein the gate of the fourth transistor is connected to the pull-down node, the first electrode of the fourth transistor is connected to the reference signal terminal, the second electrode of the fourth transistor is connected to the cascade output terminal, the first electrode of the third capacitor is connected to the gate of the fourth transistor, and the second electrode of the third capacitor is connected to the second electrode of the fourth transistor.

7. The shift register unit according to claim 6, wherein: The second cascade sub-circuit further includes a fifth transistor and a sixth transistor, The second electrode of the fourth transistor is connected to the cascade output terminal through the fifth transistor, wherein the A first electrode of a fifth transistor is connected to a second electrode of the fourth transistor, a second electrode of the fifth transistor is connected to the cascade output terminal, and a gate of the fifth transistor is connected to the pull-down node; The gate of the sixth transistor is connected to the cascade output terminal, the first electrode of the sixth transistor is connected to the power signal terminal, and the second electrode of the sixth transistor is connected to the pull-up node.

8. The shift register unit according to any one of claims 1 to 7, wherein: The power signal terminal includes a first power signal terminal and a second power signal terminal, and the reference signal terminal includes a first reference signal terminal and a second reference signal terminal; The cascade output circuit is connected to the first power signal terminal and the first reference signal terminal, and the signal output circuit is connected to the second power signal terminal and the second reference signal terminal.

9. The shift register unit according to any one of claims 1 to 8, wherein: The pull-up circuit comprises: A first control subcircuit, connected to the input signal terminal, the power signal terminal, the second control signal terminal of the shift register unit and an intermediate node, and configured to control a potential of the intermediate node based on signals at the input signal terminal and the second control signal terminal; The second control subcircuit is connected to the intermediate node, the pull-down node and the first control signal terminal of the shift register unit, and is used to pull up the potential of the pull-down node based on the signals of the intermediate node and the first control signal terminal.

10. The shift register unit according to claim 9, wherein: The first control subcircuit comprises a seventh transistor and an eighth transistor, the gate of the seventh transistor is connected to the second control signal terminal, the first electrode of the seventh transistor is connected to the power signal terminal, the second electrode of the seventh transistor is connected to the intermediate node, the gate of the eighth transistor is connected to the input signal terminal, the first electrode of the eighth transistor is connected to the second control signal terminal, and the second electrode of the eighth transistor is connected to the intermediate node; The second control subcircuit includes a ninth transistor, a tenth transistor and a fourth capacitor, the gate of the ninth transistor is connected to the intermediate node, the first electrode of the ninth transistor is connected to the first control signal terminal, the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor, the gate of the tenth transistor is connected to the first control signal terminal, the second electrode of the tenth transistor is connected to the pull-down node, the first electrode of the fourth capacitor is connected to the gate of the ninth transistor, and the second electrode of the fourth capacitor is connected to the second electrode of the ninth transistor.

11. The shift register unit according to claim 10, wherein: The first control subcircuit further includes an eleventh transistor and a twelfth transistor, The first electrode of the eighth transistor is connected to the second control signal terminal through the eleventh transistor. The gate of the eleventh transistor is connected to the input signal terminal, the first electrode of the eleventh transistor is connected to the second control signal terminal, and the second electrode of the eleventh transistor is connected to the first electrode of the eighth transistor; The gate of the twelfth transistor is connected to the intermediate node, the first electrode of the twelfth transistor is connected to the power signal terminal, and the second electrode of the twelfth transistor is connected to the first electrode of the eighth transistor.

12. The shift register unit according to any one of claims 1 to 11, wherein: The pull-down circuit includes a thirteenth transistor, a gate of the thirteenth transistor is connected to the pull-up node, a first electrode of the thirteenth transistor is connected to the reference signal terminal, and a second electrode of the thirteenth transistor is connected to the pull-down node.

13. The shift register unit according to any one of claims 1 to 12, wherein: The input circuit includes a fourteenth transistor, a gate of the fourteenth transistor is connected to the first control signal terminal of the shift register unit, a first electrode of the fourteenth transistor is connected to the input signal terminal, and a second electrode of the fourteenth transistor is connected to the pull-up node.

14. The shift register unit according to claim 13, wherein: The input circuit also includes a fifteenth transistor, the second electrode of the fourteenth transistor is connected to the pull-up node through the fifteenth transistor, wherein the gate of the fifteenth transistor is connected to the power signal terminal or the first control signal terminal, the first electrode of the fifteenth transistor is connected to the second electrode of the fourteenth transistor, and the second electrode of the fifteenth transistor is connected to the pull-up node.

15. The shift register unit according to any one of claims 1 to 14, further comprising: A reset circuit, wherein the reset circuit is connected to the pull-up node, the pull-down node, the power signal terminal, the reference signal terminal and the reset signal terminal of the shift register unit, and is used to provide the signal of the reference signal terminal to the pull-up node and provide the signal of the power signal terminal to the pull-down node under the control of the reset signal terminal.

16. The shift register unit according to claim 15, wherein: The reset circuit comprises: a sixteenth transistor, wherein a gate of the sixteenth transistor is connected to the reset signal terminal, a first electrode of the sixteenth transistor is connected to the reference signal terminal, and a second electrode of the sixteenth transistor is connected to the pull-up node; A seventeenth transistor, wherein the gate of the seventeenth transistor is connected to the reset signal terminal, the first electrode of the seventeenth transistor is connected to the power signal terminal, and the second electrode of the seventeenth transistor is connected to the pull-down node.

17. The shift register unit according to claim 16, wherein: The reset circuit also includes an eighteenth transistor, the first electrode of the sixteenth transistor is connected to the reference signal terminal through the eighteenth transistor, wherein the gate of the eighteenth transistor is connected to the reset signal terminal, the first electrode of the eighteenth transistor is connected to the reference signal terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the sixteenth transistor.

18. The shift register unit according to any one of claims 1 to 17, wherein: K=4, one or two output units are configured to provide a signal from one of the connected clock signal terminal and the power signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node, and the other output units are configured to provide a signal from one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

19. The shift register unit according to any one of claims 1 to 17, wherein: K=3, one of the output units is configured to provide a signal from one of the connected clock signal terminal and the power signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node; the other output units are configured to provide a signal from one of the connected clock signal terminal and the reference signal terminal to the connected output signal terminal under the control of the pull-up node and the pull-down node.

20. The shift register unit according to any one of claims 1 to 17, wherein: The signal output circuit is used to generate a part or all of the K driving signals required to drive a single sub-pixel.

21. A display driving circuit, comprising N shift register units connected in cascade, wherein the shift register unit is a shift register unit as claimed in any one of claims 1 to 19, wherein: The cascade output terminal of the nth stage shift register unit is connected to the input signal terminal of the n+ith stage shift register unit, wherein N, n and i are all positive integers, and n<N.

22. The display driving circuit according to claim 21, wherein: The display driving circuit receives M narrow clock signals and M wide clock signals, the narrow clock signals and the wide clock signals have the same period, the duty cycle of the narrow clock signals is smaller than the duty cycle of the wide clock signals, wherein M is an integer multiple of K; Among them, the N shift register units are divided into at least one group, each group includes M shift register units connected in cascade, the M k1-th clock signal ends of each group of shift register units are configured to receive the M narrow clock signals respectively, and the M k2-th clock signal ends of each group of shift register units are configured to receive the M wide clock signals respectively, wherein k1 and k2 are positive integers, 1≤k1≤N, 1≤k2≤N, and k1≠k2.

23. The display driving circuit according to claim 22, wherein: K=4, i=1, M=4; The first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second narrow clock signal, the third narrow clock signal, the fourth narrow clock signal and the first narrow clock signal respectively; The second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the first narrow clock signal, the second narrow clock signal, the third narrow clock signal and the fourth narrow clock signal respectively; The third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the first wide clock signal, the second wide clock signal, the third wide clock signal and the fourth wide clock signal respectively; The fourth clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the third narrow clock signal, a fourth narrow clock signal, a first narrow clock signal, and a second narrow clock signal.

24. The display driving circuit according to claim 22, wherein: K=4, i=1, M=4; The first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the fourth wide clock signal, the first wide clock signal, the second wide clock signal and the third wide clock signal respectively; The second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second wide clock signal, the third wide clock signal, the fourth wide clock signal and the first wide clock signal respectively; The third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the first wide clock signal, the second wide clock signal, the third wide clock signal and the fourth wide clock signal respectively; The fourth clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the third narrow clock signal, the fourth narrow clock signal, the first narrow clock signal, and the second narrow clock signal, respectively.

25. The display driving circuit according to claim 22, wherein: K=3, i=1, M=4; The first clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the third narrow clock signal, the fourth narrow clock signal, the first narrow clock signal, and the second narrow clock signal respectively; The second clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second wide clock signal, the third wide clock signal, the fourth wide clock signal and the first wide clock signal respectively; The third clock signal terminals of the first to fourth stage shift register units in each group are configured to receive the second narrow clock signal, the third narrow clock signal, the fourth narrow clock signal and the first narrow clock signal respectively.

26. The display driving circuit according to claim 22, wherein: K=4, i=1, M=8; The first clock signal terminals of the first to fourth stage shift register units in each group are configured to respectively receive eight wide clock signals sequentially shifted starting from the second wide clock signal; The second clock signal terminals of the first to fourth stage shift register units in each group are configured to respectively receive eight narrow clock signals sequentially shifted starting from the seventh narrow clock signal; The third clock signal terminals of the first to fourth stage shift register units in each group are configured to respectively receive eight narrow clock signals sequentially shifted starting from the first narrow clock signal; The fourth clock signal terminal of the first to fourth stage shift register units in each group is electrically connected to the power signal terminal and is configured to receive a power signal.

27. The display driving circuit according to claim 22, wherein: K=4, i=1, M=16; The first clock signal terminals of the first to sixteenth stage shift register units in each group are configured to respectively receive 16 wide clock signals sequentially shifted starting from the third wide clock signal; The second clock signal terminals of the first to sixteenth shift register units in each group are configured to receive the clock signals from the first to sixteenth shift register units, respectively. Fourteen narrow clock signals start to shift 16 narrow clock signals in sequence; The third clock signal terminals of the first to sixteenth stage shift register units in each group are configured to respectively receive 16 wide clock signals sequentially shifted starting from the first wide clock signal; The fourth clock signal terminals of the first to sixteenth stage shift register units in each group are configured to respectively receive 16 narrow clock signals that are sequentially shifted starting from the first narrow clock signal.

28. A display panel, comprising a display driving circuit as claimed in any one of claims 21 to 27 and a plurality of sub-pixels arranged in an array, wherein the display driving circuit is connected to the plurality of sub-pixels to provide display driving signals to the plurality of sub-pixels.

29. The display panel according to claim 28, wherein: The K output signal terminals of the nth shift register unit are connected to the nth row of sub-pixels to provide K display drive signals to the nth row of sub-pixels. The K display drive signals include gate drive signals and light emitting control signals required to drive the row of sub-pixels.

30. The display panel according to claim 28, wherein: The K1 output signal terminals of the nth shift register unit and the K2 output signal terminals of the n+jth shift register unit are connected to the nth row of sub-pixels to provide K display driving signals to the nth row of sub-pixels, where K1+K2=K, and j is an integer greater than 1.

31. A method for controlling a shift register unit according to any one of claims 1 to 20, comprising: In the input stage, the input circuit inputs a first level signal of the input signal terminal to the pull-up node; In the output stage, the potential of the pull-up node causes the pull-down circuit to pull down the potential of the pull-down node, and the potentials of the pull-up node and the pull-down node cause the cascade output circuit to provide the signal of the power signal terminal to the cascade output terminal, and the K output units of the signal output circuit respectively provide the signals of the clock signal terminals connected to them to the corresponding output signal terminals; In the reset stage, the input circuit inputs the second level signal of the input signal terminal to the pull-up node, and the pull-up circuit pulls up the potential of the pull-down node based on the potential of the input signal terminal. The potentials of the pull-up node and the pull-down node enable the cascade output circuit to provide the signal of the reference signal terminal to the cascade output terminal, and the K output units of the signal output circuit respectively provide the signals of the power supply signal terminal or the reference signal terminal connected to each of them to the corresponding output signal terminal.

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