Data processing method and apparatus

Abstract

Provided in the present application are a data processing method and apparatus. The method comprises: after a first management unit sends a first request message corresponding to a first write request message, until the first management unit receives a first response message, if other write requests having the same Cacheline address as the first write request message are received, writing a plurality of pieces of data having the same Cacheline address into a cache space corresponding to the first management unit, and then writing the data into a storage space corresponding to a second management unit. Thus, the interaction with a second management unit during the process of writing a plurality of pieces of data is reduced, thereby effectively reducing a data processing delay, and increasing the overall efficiency of data processing.

Description

Data processing method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202311246217.6, filed on September 25, 2023, entitled “Data Processing Method and Apparatus”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of data storage, and more particularly to a data processing method and apparatus. Background Technology

[0003] In modern computing systems, multi-core chips utilize shared memory to improve inter-process communication efficiency. A series of memory consistency models have been defined, focusing on the order of software read / write operations and the visible order of results from hardware read / write operations. Common models include Sequential Consistency (SC), Total Store Order (TSO), and Relaxed Model (RM). When these two models interact—that is, when a sequence of Strict Order (SO) requests with strong constraints enters the weak side—the weak side must ensure that the visible order of the final processing results matches the expectations of the strong side. Processing these requests serially on the weak side would significantly impact bandwidth. A typical scenario is the interaction between multi-core chips and peripherals, where communication bandwidth is critical to system performance. Therefore, efficiently handling SO requests becomes a key factor limiting bandwidth.

[0004] Summary of the Invention

[0005] This application provides a data processing method and apparatus that can improve the processing efficiency of SO requests to a certain extent.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] In a first aspect, embodiments of this application provide a data processing method. The method includes: a first management unit receiving a first write request message, the first write request message being used to request that first data be written to a target cacheline; the first management unit, in response to the first write request message, sending a first request message to a second management unit, the first request message being used to request permissions for the target cacheline; if, before the first management unit receives a first response message from the second management unit, the first management unit receives at least one second write request, wherein the at least one second write request is used to request that at least one second piece of data be written to the target cacheline, then, after receiving the first response message, the first management unit caches the first data and at least one second piece of data in a first storage space corresponding to the first management unit; wherein the first response message is used to indicate permissions for the target cacheline; and the first management unit writes target data from the first storage space to the second management unit, the target data including the first data and at least one second piece of data.

[0008] In this way, this application can achieve parallel processing of small packets of data with consecutive cacheline addresses within a certain range, thereby improving data processing efficiency. Furthermore, this application processes small packets of data with consecutive cacheline addresses in parallel on the memory side before writing them to the storage side, reducing bus data interaction between the memory and storage sides, thus reducing processing latency and increasing data write bandwidth.

[0009] In one possible implementation, the first management unit includes a first management sub-node and a second management sub-node. After receiving a first response message, the first management unit caches the first data and at least one piece of data in the first storage space corresponding to the first management unit. This includes: the first management sub-node responding to the first response message by sending a second request message to the second management sub-node. The second request message indicates that permission to the target cacheline has been obtained and requests that the first data be written to the target cacheline. The first management sub-node receives a second response message from the second management sub-node, indicating that writing the first data is permitted. The first management sub-node responding to the second response message by requesting the second management sub-node to write at least one piece of second data. During the process of the first management sub-node requesting the second management sub-node to write at least one piece of second data, the second management sub-node obtains the first data and writes it into the first storage space. The second management sub-node obtains the second data and writes it into the second storage space.

[0010] In this way, this application completes the handshake process for small packets with the same cacheline address inside the memory side (which can also be understood as the upstream node), thereby reducing interaction with the bus, reducing latency, and increasing bandwidth.

[0011] In one possible implementation, requesting the second management sub-node to write at least one piece of second data includes: the first management sub-node sending a third request message to the second management sub-node, the third request message being used to request permissions for the target cacheline; the first management sub-node receiving a third response message sent by the second management sub-node, the third response message being used to indicate permissions for the target cacheline; the first management sub-node responding to the third response message sending a fourth request message to the second management sub-node, the fourth request message being used to indicate that a single piece of second data should be written to the target cacheline; and the second management sub-node responding to the fourth request message acquiring the single piece of second data, and writing the single piece of second data into the first storage space after the first data has been written into the first storage space.

[0012] In this way, this application can achieve parallel processing of small packets with the same cacheline address within the module on the memory side, which can effectively improve data processing efficiency.

[0013] In one possible implementation, the method further includes: if the first management unit has not received any other requests to write data to the target cacheline before receiving the first response message from the second management unit, the first management unit requests the second management unit to write the third data to the target cacheline. In this way, if no small packet with the same cacheline address is received within the merge window, the application can process it according to the original IO Cache mode, thus avoiding introducing negative benefits.

[0014] For example, small packets received outside the Merge window at the same Cacheline address are processed in the same way as the original IO Cache mode.

[0015] In one possible implementation, the first management unit requests the second management unit to write third data to the target cacheline, including: the first management unit sending a fifth request message to the second management unit, the fifth request message being used to request that the first data be written to the target cacheline; the first management unit responding to the fifth response message sent by the second management unit by sending a data transmission instruction message to the data transmission module, the data transmission instruction message being used to instruct the data transmission module to send the first data to the second management unit; and the fifth response message being used to indicate that writing the first data is permitted. In this way, this application interacts with the management unit on the storage side to write data into the storage space.

[0016] Secondly, this application provides a data processing apparatus, including a first management unit and a second management unit; the first management unit is configured to receive a first write request message, the first write request message being used to request that first data be written to a target cacheline; the first management unit is further configured to, in response to the first write request message, send a first request message to the second management unit, the first request message being used to request permissions for the target cacheline; the first management unit is further configured to, if, before receiving a first response message from the second management unit, the first management unit receives at least one second write request, wherein the at least one second write request is used to request that at least one second piece of data be written to the target cacheline, then, after receiving the first response message, the first management unit caches the first data and at least one second piece of data in a first storage space corresponding to the first management unit; wherein the first response message is used to indicate permissions for the target cacheline; the first management unit is further configured to write target data in the first storage space to the second management unit, the target data including the first data and at least one second piece of data.

[0017] In one possible implementation, the first management unit includes a first management sub-node and a second management sub-node. The first management sub-node is configured to send a second request message to the second management sub-node in response to a first response message. The second request message indicates that permission to the target cacheline has been obtained and requests that first data be written to the target cacheline. The first management sub-node is also configured to receive a second response message from the second management sub-node, indicating that writing the first data is permitted. The first management sub-node is also configured to request the second management sub-node to write at least one piece of second data in response to the second response message. During the process of the first management sub-node requesting the second management sub-node to write at least one piece of second data, the second management sub-node acquires the first data and writes the first data into the first storage space. The second management sub-node is configured to acquire the second data and write the second data into the second storage space.

[0018] In one possible implementation, the first management sub-node is further configured to send a third request message to the second management sub-node, the third request message being used to request permissions for the target cacheline; the first management sub-node is further configured to receive a third response message sent by the second management sub-node, the third response message being used to indicate permissions for the target cacheline; the first management sub-node is further configured to, in response to the third response message, send a fourth request message to the second management sub-node, the fourth request message being used to indicate that a single second data item is written to the target cacheline; the second management sub-node is further configured to, in response to the fourth request message, obtain the single second data item, and, after the first data item is written to the first storage space, write the single second data item to the first storage space.

[0019] In one possible implementation, the first management unit is further configured to request the second management unit to write the third data to the target cacheline before receiving the first response message from the second management unit and before receiving any other requests to write data to the target cacheline.

[0020] In one possible implementation, the first management unit is configured to send a fifth request message to the second management unit, the fifth request message being used to request that the first data be written to the target cacheline; the first management unit is also configured to, in response to the fifth response message sent by the second management unit, send a data transmission instruction message to the data transmission module, the data transmission instruction message being used to instruct the data transmission module to send the first data to the second management unit; the fifth response message is used to indicate that writing the first data is permitted.

[0021] Thirdly, embodiments of this application provide an electronic device. The electronic device includes: one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and when executed by the one or more processors, cause the electronic device to perform instructions of the method in the first aspect or any possible implementation thereof.

[0022] Fourthly, embodiments of this application provide a computer-readable medium for storing a computer program, the computer program including instructions for performing the method in the first aspect or any possible implementation of the first aspect.

[0023] Fifthly, embodiments of this application provide a computer program including instructions for performing the method in the first aspect or any possible implementation thereof.

[0024] In a sixth aspect, embodiments of this application provide a chip including one or more interface circuits and one or more processors; the interface circuits are used to receive signals from the memory of an electronic device and send signals to the processors, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, it causes the electronic device to execute the instructions of the method in the first aspect or any possible implementation of the first aspect. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 is a schematic flowchart illustrating an exemplary data processing method;

[0027] Figure 2 is a schematic flowchart illustrating an exemplary data processing method;

[0028] Figure 3 is a schematic flowchart illustrating an exemplary data processing method;

[0029] Figure 4 is a flowchart illustrating a data processing method according to an embodiment of this application;

[0030] Figure 5 is a flowchart illustrating a data processing method according to an embodiment of this application;

[0031] Figure 6 is a flowchart illustrating a data processing method according to an embodiment of this application;

[0032] Figure 7 is a flowchart illustrating a data processing method according to an embodiment of this application;

[0033] Figure 8 is a schematic diagram of the structure of an exemplary device. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0036] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0037] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0038] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0039] Figure 1 is a schematic flowchart of a data processing method in the prior art, as exemplarily shown. Referring to Figure 1, it specifically includes:

[0040] Node A is a node on the Model-0 side, node C is an upstream boundary node, and node B is a downstream node.

[0041] 1) Node A sends a sequence of write requests (including SO0Req and SO1Req) with order requirements to Node C.

[0042] 2) Node C serially sends a write request to node B.

[0043] Specifically, node C responds to SO0Req (Request) by sending Req0 to node B. After receiving DBID Rep0 (Response) from node B, node C sends Req1 corresponding to SO1Req to node B and receives DBID Rep1 from node B. DBID Rep carries the location of the received data (which can also be understood as the location where the data was written, within node B's storage space).

[0044] 3) Node C and Node B perform data writing operations in parallel.

[0045] For example, node C sends Write Data0 and Write Data1 to node B to request that the corresponding data be written. After node B writes the data into the storage space, it sends Comp0 (Completion) and Comp1 to node C to indicate that the corresponding data has been written.

[0046] 4) Node C sends an ACK to Node B.

[0047] For example, after receiving the completion response, upstream node C needs to send an Ack (Acknowledge) signal to node B in the order of the write requests (i.e., SO0Req and SO1Req) to inform downstream (i.e. node B) that the corresponding request result is now globally visible. The order of Ack handshakes ensures the visibility order of the request results.

[0048] In the approach shown in Figure 1, the DBID handshake ensures that data is written to node B. That is, node B writes the received data into its cache in the order of the received requests. This allows for partial parallel processing of the SO request sequence. However, this approach still has the following problems:

[0049] 1) The operations related to the next data packet need to wait for the DBID response of the previous data packet before they can continue to be processed. Therefore, there is still a serial processing part, and the latency of waiting for the response is high, resulting in low request bandwidth.

[0050] 2) Downstream node B needs to handshake with upstream node C multiple times to ensure the data writing order. This process has a large delay and involves a lot of interaction, which increases the communication burden and affects the efficiency of data writing.

[0051] Figure 2 is a flowchart illustrating another data processing method of the prior art. Referring to Figure 2, it specifically includes: based on the hardware consistency protocol, expanding the consistency range, incorporating the boundary between the two storage models into the cache consistency domain on the weak order model side, completing the order processing at the node at the boundary, and ensuring the global visible order of the results.

[0052] 1) Node C at the interface of the storage model receives a sequence of SO requests (including SO Req0, SO Req1, etc.) sent by node A on the strong order model side, and determines that it is necessary to ensure that the visible order of the results on the weak order model side meets the requirements of the strong side.

[0053] 2) After receiving the SO request sequence, node C obtains the E state (also known as CompUC, meaning exclusive state, indicating that the corresponding cacheline is allocated to node C and cannot be used by other modules) from downstream node B in parallel, completing the migration of sequential processing nodes. During this process, the CC domain (Cache Coherency) is expanded (i.e., the CC domain of node B is extended to node C), giving the boundary node C the ability to process consistency, thereby ensuring the visible order of request results.

[0054] After node C completes sequential processing, it no longer needs to guarantee the order through a serial handshake with downstream nodes. Therefore, requests can be processed in parallel on the weakly sequential model side, thereby improving the request bandwidth between models.

[0055] Referring to Figure 2, the following is a simplified explanation using the data processing flow diagram shown in Figure 3 as an example. In this scenario, when node A (an I / O device, such as a PCIe controller) interacts with the chip SOC, the I / O side SO write request enters the SOC side. Node C, as the boundary node between I / O and SOC, is used to complete sequential processing and cooperates with the internal nodes of the SOC (i.e., node B) to complete the request, improving processing bandwidth. The submodule within node C that implements this function is called the I / O Cache module. Please refer to Figure 3, which specifically includes:

[0056] 1) Node C receives multiple write requests (So0Req, SO1Req, etc.) sent by Node A.

[0057] 2) Based on multiple write requests, node C obtains E State from downstream node B in parallel (including sending CleanUqnique (to request E STATE), receiving ComRsp (to receive E state), and feeding back Comp ACK (to respond that E state has been received)), and expands the CC Domain to complete the migration of sequential processing nodes.

[0058] After node C obtains permission (i.e., E state), it sends a write back request to node B in the order of requests on the PCIe side to ensure the global visibility order of the request results and complete the request processing in parallel.

[0059] This method employs a hardware consistency scheme to manage the global visibility of operation results at the upstream node, avoiding the need to process the order through upstream and downstream handshakes, thereby enabling parallel processing of requests and improving bandwidth. However, this method cannot achieve parallel processing when faced with a sequence of SO requests with the same cacheline address.

[0060] This application provides a data processing method that enables parallel processing of consecutive SO request sequences at the same cacheline address. Figure 4 is a flowchart illustrating a data processing method according to an embodiment of this application. Referring to Figure 4, the specific steps include, but are not limited to, the following:

[0061] S401, the first management unit receives a first write request message, which is used to request that the first data be written to the target cache line.

[0062] For example, the PCIe (i.e., node A in this embodiment) sends a write request message to the first management unit to write data into the target cacheline. The first management unit (i.e., node C in this embodiment) receives the write request message and obtains the cacheline address indicated in the message. The cacheline address indicated in the write request message is all or part of the cacheline address. This embodiment uses multiple consecutive small data packets as an example; therefore, the small data packets involved in this embodiment are all data smaller than a cacheline granularity. For example, taking a cacheline length of 128 bytes (this is only an illustrative example and can be set according to actual needs; this application does not limit this), the corresponding data packets with a length less than 128 bytes are called small data packets. For example, a data packet with a length of 64 bytes is a small data packet (referred to as a small packet in this embodiment, and will not be repeated below).

[0063] S402, in response to the first write request message, the first management unit sends a first request message to the second management unit. The first request message is used to request permissions for the target Cacheline.

[0064] For example, after the first management unit receives the write request message and obtains the target cacheline address to be written, it sends a first request message (also known as an E State acquisition request message, or a cacheline status acquisition request, etc., which is not limited in this application) to the second management unit (i.e., node B in this embodiment). The first request message is used to request the status of the target cacheline (which can also be understood as permission).

[0065] In this embodiment, the second management unit manages the status (i.e., permissions) of all cachelines. It should be noted that a cacheline can only be used by one node (e.g., node C) at a time. That is, once a cacheline's usage permission is granted to a single node, other nodes cannot access (including write and read) the data in that cacheline. In this embodiment, when a node requests permission (also called usage permission) for a single cacheline from the second management unit, the second management unit checks whether the target cacheline is available. This can also be understood as checking whether the cacheline's status is unlocked, or whether the cacheline's permission has not been assigned to any node. In one example, if the second management unit detects that the target cacheline is currently available, meaning it is not occupied by other nodes or modules, the second management unit can send the target cacheline's E state to the first management unit, indicating that the first management unit is allowed to use the target cacheline. Simultaneously, the second management unit records the target cacheline's permission status as unavailable and assigns the permission to the first management unit. In another example, if the second management unit detects that the target cacheline is unavailable, it waits for the target cacheline to become available (i.e., other nodes return the usage rights to the cacheline) before sending the target cacheline's E state to the first management unit, indicating that the first management unit is allowed to use the target cacheline. Simultaneously, the second management unit records the target cacheline's permission status as unavailable and assigns the permission to the first management unit.

[0066] Therefore, in this embodiment of the application, there is a certain waiting time between the first management unit sending the first write request message and receiving the first response message (i.e., E state). This waiting time is called the merge (parallel) window in this embodiment of the application. That is, the starting point of the merge window is the time corresponding to the first management unit sending the first write request message, and the ending point is the time corresponding to the first response message being received.

[0067] S403, if the first management unit receives at least one second write request before receiving the first response message from the second management unit, wherein the at least one second write request is used to request that at least one second data be written to the target Cacheline, then after receiving the first response message, the first management unit caches the first data and at least one data in the first storage space corresponding to the first management unit; wherein the first response message is used to indicate the permissions of the target Cacheline.

[0068] For example, in this embodiment of the application, if the first management unit receives at least one second write request with the same Cacheline address as the first write request within the merge window, that is, before receiving the first response message, the first management unit can execute an internal interaction process to cache the data requested to be written to the same Cacheline in the storage space corresponding to the first management unit.

[0069] For example, if no second write request with the same address is received within the merge window, or if other write requests with different cacheline addresses are received, the process follows the existing IO Cache procedure.

[0070] It should be noted that, in the embodiments of this application, "small packets with the same cacheline address" refers to multiple small packets indicating cacheline addresses to be written within the same cacheline. For example, suppose the address of the first cacheline is 0-127 bytes. Small packet 1 indicates a cacheline address of 0-63 bytes, and small packet 2 indicates a cacheline address of 64-127 bytes. Therefore, small packets 1 and 2 indicate cacheline addresses within the same cacheline (i.e., the first cacheline). Accordingly, small packets 1 and 2 are small packets with the same cacheline address.

[0071] S404, the first management unit writes target data from the first storage space to the second management unit. The target data includes first data and at least one second data.

[0072] For example, the first management unit writes multiple data packets with the same cacheline address received within the merge window into a cache, and then writes the data in the cache into the second management unit. This enables parallel processing of multiple small packets with the same cacheline address, reduces interactions on the bus, lowers latency, and increases bandwidth (i.e., throughput).

[0073] The data processing method in this application embodiment will be described in detail below with specific examples. Figure 5 is a schematic flowchart of an exemplary data processing method. In this example, a small packet with the same cacheline address is not received in the merge window. Referring to Figure 5, the specific steps include, but are not limited to, the following:

[0074] S501, Node A sends the first write request message to Node C.

[0075] For example, when node A (e.g., PCIe) needs to write data, it sends a first write request message to node C. The first write request message requests the writing of first data. The first write request message includes, but is not limited to, the first cacheline address corresponding to the first data and other control information. Optionally, the control information includes, but is not limited to, write instructions and command identifiers.

[0076] For example, the first cacheline address is the cacheline address to which node A expects the first data to be written. Optionally, the first cacheline address includes, but is not limited to, a first start address and a first length. The first start address indicates the starting position of the cacheline to be written, and the length indicates the length occupied by the data. For example, if the first cacheline address includes a start address of 0 and a length of 64, then the first cacheline address it indicates is 0 to 63 bytes. That is, the cacheline address requested by the first write request message is 0 to 63 bytes.

[0077] For example, a write instruction is used to request the writing of data. A command identifier is used to identify the request message, which can also be understood as identifying the session. Accordingly, all subsequent interactions performed in response to the write request message must carry the command identifier to indicate that the interaction information carrying the command identifier is performed in response to the write request.

[0078] S502, Node C sends a Cacheline status request message to Node B.

[0079] For example, node C responds to the first write request message and obtains the first cacheline address and other control information.

[0080] Node C sends a Cacheline status request message (e.g., a Clean Unique message) to Node B to request the E state of the target Cacheline to which the first Cacheline belongs (see above for details). The Cacheline status request message includes, but is not limited to: Node C's identification information, the address of the first Cacheline, and an E state request indication.

[0081] For example, the identification information of node C can be the ID of node C, etc., which is not limited in this application. The E State request indicates the request for the E state of the target Cacheline, which can also be understood as a request for the use permission of the target Cacheline. Here, the target Cacheline is the Cacheline where the first Cacheline is located, which will not be repeated below.

[0082] S503, Node B sends a Cacheline status response message to Node C.

[0083] For example, as described above, node B can detect the status of the target cacheline. If the status of the target cacheline is determined to be available, node B sends a cacheline status response message to node C based on the identification information of node C. The message includes, but is not limited to, the E State of the target cacheline, which indicates that the permissions of the target cacheline be assigned to node C.

[0084] For example, node B records the status of the target cacheline, such as the correspondence between the target cacheline and the identification information of node C, which is used to indicate that the current usage rights of the target cacheline are assigned to node C.

[0085] In this embodiment, the time period between S502 and S503 is the merge window. This example illustrates the situation where no other small packets with the same cacheline address are received within the merge window.

[0086] S504, Node C sends a Write Back message to Node B.

[0087] For example, node C determines that it has acquired usage rights (or access rights) to the target cacheline based on the cacheline status response message. Node C sends a Write Back message to node B to request the writing of the first data and to indicate the release of the cacheline's E state. That is, in this embodiment, if no consecutive write requests to the same cacheline address are received within the merge window, node C releases the cacheline's usage rights.

[0088] The Write Back message includes, but is not limited to: Write Back indication information, node C's identification information, and the address of the first cacheline. The Write Back indication information is used to request the writing of data.

[0089] S505, Node B sends a CompDBID (Data buffer Identification) message to Node C.

[0090] For example, in response to the Write Back message, node B revokes the permissions of the target cacheline corresponding to node C based on the identification information of node C and the address of the first cacheline.

[0091] Furthermore, based on the first cacheline address, node B determines the corresponding data cache address in its corresponding storage space (also known as cache space). Node B sends a CompDBID message to node C to indicate permission to write the first data. The CompDBID message includes, but is not limited to, a command identifier, node B's identification information, and the data cache address.

[0092] S506, Node C sends an ACK message to Node A.

[0093] For example, in response to the CompDBID message, node C sends an ACK message to node A. The ACK message, also known as the first write response message, indicates that writing the first piece of data is permitted. The ACK message includes, but is not limited to, the command identifier, node B's identification information, and the data cache address.

[0094] S507, Node A sends a write message to Node B.

[0095] For example, in response to the ACK message, node A sends a write message (also called a W dat message, which is not limited in this application) to node B based on node B's identification information. The write message is used to instruct data to be written to a specified address. The write message includes, but is not limited to: first data, DBID, command identifier, etc.

[0096] S508, Node B writes the first data into the cache space.

[0097] For example, in response to a write message, node B writes the first data into the cache space indicated by DBID. Afterwards, node B can write the data in the cache space into memory; specific implementation methods can be found in existing technologies, and will not be elaborated upon here.

[0098] Figure 6 is a flowchart illustrating an exemplary data processing method. This example uses the reception of a small packet with the same Cacheline address in the merge window as an example. Referring to Figure 6, the specific steps include, but are not limited to, the following:

[0099] S601-1, Node A sends the first write request message to Node C.

[0100] For example, when node A (e.g., PCIe) needs to write data, it sends a first write request message to node C. The first write request message requests the writing of first data. The first write request message includes, but is not limited to, the first cacheline address corresponding to the first data and other control information. Optionally, the control information includes, but is not limited to, write instructions and command identifier 1, etc.

[0101] For example, the first cacheline address is the cacheline address to which node A expects the first data to be written. Optionally, the first cacheline address includes, but is not limited to, a first start address and a first length. The first start address indicates the starting position of the cacheline to be written, and the length indicates the length occupied by the data. For example, if the first cacheline address includes a start address of 0 and a length of 64, then the first cacheline address it indicates is 0 to 63 bytes. That is, the cacheline address requested by the first write request message is 0 to 63 bytes.

[0102] For example, a write instruction is used to request the writing of data. A command identifier is used to identify the request message, which can also be understood as identifying the session. Accordingly, all subsequent interactions performed in response to the write request message must carry the command identifier to indicate that the interaction information carrying the command identifier is performed in response to the write request.

[0103] S602-1, The requesting node sends a Cacheline status request message 1 to node B.

[0104] For example, the requesting node in node C (which may also be called the first management subunit, but is not limited in this application) responds to the first write request message and obtains the first cacheline address and other control information.

[0105] The requesting node sends a Cacheline status request message 1 (e.g., a Clean Unique message) to node B to request the E state of the target Cacheline to which the first Cacheline belongs (see above for details). The Cacheline status request message 1 includes, but is not limited to: node C's identification information, the address of the first Cacheline, and an E state request indication.

[0106] For example, the identification information of node C can be the ID of node C, etc., which is not limited in this application. The E State request indicates the request for the E state of the target Cacheline, which can also be understood as a request for the use permission of the target Cacheline. Here, the target Cacheline is the Cacheline where the first Cacheline is located, which will not be repeated below.

[0107] S601-2, Node A sends the first write request message to Node C.

[0108] In this example, node A continues to send a second write request message to node C. The second write request message is used to request the writing of second data. The second write request message includes, but is not limited to, the second cacheline address corresponding to the second data and other control information. Optionally, the control information includes, but is not limited to, write instructions and command identifier 2, etc.

[0109] For example, the second cacheline address is the cacheline address to which node A expects the second data to be written. Optionally, the second cacheline address includes, but is not limited to, a second start address and a second length. The second start address indicates the starting position of the cacheline to be written, and the length indicates the length occupied by the data. For example, if the second cacheline address includes a start address of 64 and a length of 64, then the second cacheline address it indicates is 64 to 127 bytes. That is, the cacheline address requested by the second write request message is 64 to 127 bytes.

[0110] For example, a write instruction is used to request the writing of data. A command identifier is used to identify the request message, which can also be understood as identifying the session. Accordingly, all subsequent interactions performed in response to the write request message must carry the command identifier to indicate that the interaction information carrying the command identifier is performed in response to the write request.

[0111] S603-1, Node B sends Cacheline status response message 1 to Node C.

[0112] For example, as described above, node B can detect the status of the target cacheline. If the status of the target cacheline is determined to be available, node B sends a cacheline status response message 1 to node C based on the identification information of node C. The message includes, but is not limited to, the E State of the target cacheline, which indicates that the permissions of the target cacheline are assigned to node C.

[0113] For example, node B records the status of the target cacheline, such as the correspondence between the target cacheline and the identification information of node C, which is used to indicate that the current usage rights of the target cacheline are assigned to node C.

[0114] In this embodiment, the time period between S602 and S603 is the merge window. This example illustrates receiving other small packets with the same cacheline address within the merge window. It should be noted that this example only illustrates receiving another small packet with the same cacheline address within the merge window. In other embodiments, more small packets with the same cacheline address may be received, and the processing method is similar; therefore, this application will not provide examples for each.

[0115] It should be noted that, in this example, to distinguish the steps performed on different write request messages, step "X-1" in this example represents the step performed on the first write request message, and "X-2" represents the step performed on the second write request message.

[0116] S604-1, The requesting node sends a wipe back message 1 to the cache node.

[0117] For example, after receiving the second write request message, the requesting node determines, based on the cacheline address indicated by the second write request message, that the second cacheline address indicated by the second write request message and the first cacheline address indicated by the first write request message belong to the same target cacheline. In other words, the first data (also called the first data packet) and the second data (also called the second data packet) are data written to the same cacheline. This can be understood as the first data packet and the second data packet being consecutively received data packets with the same cacheline address within the merge window.

[0118] It should be noted that in this embodiment, the example of the first data and the second data having consecutive cacheline addresses is used for illustration. In other embodiments, the first data and the second data may be non-consecutive addresses in the same cacheline, which is not limited in this application.

[0119] For example, if the requesting node determines that it has received a small packet with the same cacheline address in the merge window, it will execute the internal node data processing flow to achieve parallel processing of small packets with the same cacheline address.

[0120] Please refer to Figure 6. In the internal node data processing flow, the requesting node determines its access permission (or access control) to the target cacheline based on the cacheline status response message. Unlike the flow in Figure 5, in this example, the requesting node sends a Write Back message 1 to the cache node (also called the IO data cache node, which is not limited in this application). That is, node C still holds the access permission to the target cacheline and does not return it to node B. Thus, while node C is processing multiple data items to be written to the target cacheline internally, other modules or units cannot access the target cacheline, thereby preventing data read / write errors.

[0121] The Write Back message 1 includes, but is not limited to, Write Back instruction information and the address of the first Cacheline. The Write Back message is used to request the writing of first data and to indicate that access to the target Cacheline has been obtained. Optionally, the Write Back message may also carry an E State to indicate that access to the target Cacheline has been obtained; this application does not impose any limitations on this.

[0122] S605-1, the cache node sends a CompDBID message 1 to the requesting node.

[0123] For example, in response to Write Back message 1, the cache node determines the corresponding data cache address in its storage space based on the first cacheline address. The cache node sends a CompDBID message 1 to the requesting node to indicate permission to write the first data. The CompDBID message 1 includes, but is not limited to, a command identifier and the data cache address.

[0124] S606-1, Request node to send ACK message 1 to node A.

[0125] For example, in response to the CompDBID message, the requesting node sends an ACK message 1 to node A. ACK message 1, also known as the first write response message, indicates that writing the first piece of data is permitted. The ACK message includes, but is not limited to, the command identifier, node C's identification information, and the data cache address.

[0126] S607-1, Node A sends write message 1 to Node C.

[0127] For example, in response to ACK message 1, node A sends a write message (also called a W dat message, which is not limited in this application) to node C based on node C's identification information. The write message is used to instruct data to be written to a specified address. The write message includes, but is not limited to: first data, DBID, command identifier, etc.

[0128] S608-1, the cache node writes the first data into the cache space.

[0129] For example, in response to a write message, the cache node writes the first data into the cache space indicated by the DBID.

[0130] In this embodiment, to maintain the ordering characteristic of the same cacheline address, the cache node will only schedule the next CleanUnique request after receiving the Write Back message corresponding to the previous write request and replying with a CompDBID message. That is, as shown in Figure 6, after executing S605-1, the cache node can begin executing S602-2, which is the data processing flow corresponding to the second write request, specifically including:

[0131] S602-2, The requesting node sends a Cacheline status request message 2 to node B.

[0132] For example, the requesting node in node C (which may also be called the first sub-unit, but is not limited in this application) responds to the second write request message and obtains the second cacheline address and other control information.

[0133] The requesting node sends a Cacheline status request message 2 (e.g., a Clean Unique message) to the cache node to request the E state of the target Cacheline to which the first Cacheline belongs (see above for details). The Cacheline status request message 2 includes, but is not limited to, the address of the first Cacheline and an E state request indication.

[0134] S603-2, The cache node sends a Cacheline status response message 2 to the requesting node.

[0135] For example, as described above, in S604-1, the cache node obtains the E state of the target Cacheline. Accordingly, in this step, the cache node sends a Cacheline status response message 2 to the requesting node. The message includes, but is not limited to, the E state of the target Cacheline, which is used to indicate that the permissions of the target Cacheline are assigned to the requesting node.

[0136] S604-2, the requesting node sends a write-back message to the cache node.

[0137] For example, the requesting node determines, based on Cacheline status response message 2, that it has obtained access rights (or permission permissions) to the target Cacheline. The requesting node sends Write Back message 2 to the cache node (also known as the IO data Cache node, which is not limited in this application). Write Back message 2 includes, but is not limited to, Write Back indication information and a second Cacheline address. Write Back message 2 is used to request the writing of second data.

[0138] S605-2, The cache node sends a CompDBID message 2 to the requesting node.

[0139] For example, in response to Write Back message 2, the cache node determines the corresponding data cache address in its storage space based on the second Cacheline address. The cache node sends a CompDBID message 2 to the requesting node to indicate permission to write the second data. The CompDBID message 2 includes, but is not limited to, a command identifier and the data cache address.

[0140] In this embodiment, to ensure visibility ordering between data, the cache node controls the response CompDBID to achieve visibility ordering. In another embodiment, for the same cacheline address, the cache node can only respond with the CompDBID corresponding to the next write request after receiving the previous write data (i.e., receiving the write message). That is, after receiving a write back message, the cache node records the order in which the write back messages are received. The cache node receives the corresponding write message according to the order of the received write back messages; this can also be understood as receiving the corresponding write data before continuing to execute the following process.

[0141] For example, as shown in Figure 6, S606-1 to S607-1 corresponding to the first write request and S602-2 to S604-2 corresponding to the second write request are executed in parallel. The cache node receives the Write Back message 1 corresponding to the first write request before receiving the Write Back message 2 corresponding to the second write request. Accordingly, the order of the command identifiers recorded by the cache node (or other information recording order, which is not limited in this application) is the command identifier corresponding to Write Back message 1 (e.g., the first command identifier) ​​and the command identifier corresponding to Write Back message 2 (e.g., the second command identifier). Therefore, the cache node will execute S605-2 only after receiving the data requested to be written by Write Back message 1 (i.e., the first data). For example, assuming that S604-2 is completed before S607-1, and the cache node receives Write Back message 2, the cache node determines, based on the order of the currently recorded command identifiers (i.e., the first command identifier), that it has not yet received the write data corresponding to command identifier 1 (which can also be understood as the first write message or write back message 1). The cache node then saves the corresponding information (i.e., the second command identifier) ​​according to the order of the received write back messages. Subsequently, the cache node receives write message 1. Based on the command identifier, it can determine the data requested to be written in the write message. Corresponding to write back message 1, the cache node writes the first data in write message 1 to the storage address allocated for the first data in S605-1 (i.e., the address indicated by DBID). Furthermore, the cache node executes S605-2.

[0142] S606-2, Request node to send ACK message 2 to node A.

[0143] For example, in response to CompDBID message 2, the requesting node sends ACK message 2 to node A. ACK message 2 can also be called a second write response message, used to indicate that writing second data is permitted. ACK message 2 includes, but is not limited to: command identifier, node C's identification information, and data cache address, etc.

[0144] S607-2, Node A sends write message 2 to Node C.

[0145] For example, in response to ACK message 1, node A sends write message 2 (also called W dat message, which is not limited in this application) to node C based on node C's identification information. Write message 2 is used to instruct data to be written to a specified address. Write message 2 includes, but is not limited to: second data, DBID, command identifier, etc.

[0146] S608-1, the cache node writes the second data into the cache space.

[0147] For example, in response to write message 2, the cache node writes the second data into the cache space indicated by DBID.

[0148] S609, the cache node sends a wipe back message 3 to node B.

[0149] For example, after writing the first and second data, the cache node sends a Write Back message 3 to node B to request the writing of target data (including the first and second data). The Write Back message 3 includes, but is not limited to: a third command identifier, Write Back indication information, node C's identifier information, and a third cacheline address (including the first and second cacheline addresses). The Write Back indication information is used to request the writing of data.

[0150] S610, Node B sends CompDBID message 3 to Node C.

[0151] For example, in response to Write Back message 3, node B determines the corresponding data cache address in its storage space based on the third cacheline address. Node B then sends CompDBID message 3 to node C to indicate permission to write the target data. CompDBID message 3 includes, but is not limited to, a third command identifier, node B's identification information, and the data cache address.

[0152] S611, the cache node sends write message 3 to node B.

[0153] For example, in response to CompDBID message 3, the cache node in node C sends write message 3 (also called W dat message, which is not limited in this application) to node B based on the identification information of node B. Write message 3 is used to instruct data to be written to a specified address. Write message 3 includes, but is not limited to: target data, DBID, third command identifier, etc.

[0154] S612, Node B writes the first data into the cache space.

[0155] For example, in response to write message 3, node B writes the target data into the cache space indicated by DBID.

[0156] Figure 7 is a flowchart illustrating an exemplary data processing method. This example uses a small packet received outside the merge window at the same cacheline address as an example. Referring to Figure 7, the specific steps include, but are not limited to, the following:

[0157] S701-1, Node A sends the first write request message to Node C.

[0158] S702-1, Node B sends Cacheline status request message 1 to Node B.

[0159] S703-1, Node B sends a Cacheline status response message to Node C.

[0160] In this example, if node C (specifically, the requesting node within node C) does not receive a small packet with the same cacheline address within the merge window 1 corresponding to the first write request, then the process continues according to the flow in Figure 5.

[0161] For details not described, please refer to Figures 5 and 6, which will not be repeated here.

[0162] S704-1, Node C sends a Write Back message to Node B.

[0163] For example, node C determines that it has acquired usage rights (or access rights) to the target cacheline based on the cacheline status response message. Node C sends a Write Back message to node B to request the writing of the first data and to indicate the release of the cacheline's E state. That is, in this embodiment, if no consecutive write requests to the same cacheline address are received within the merge window, node C releases the cacheline's usage rights.

[0164] The Write Back message includes, but is not limited to: Write Back indication information, node C's identification information, and the address of the first cacheline. The Write Back indication information is used to request the writing of data.

[0165] S705-1, Node B sends a CompDBID message to Node C.

[0166] For example, in response to the Write Back message, node B revokes the permissions of the target cacheline corresponding to node C based on the identification information of node C and the address of the first cacheline.

[0167] Furthermore, based on the first cacheline address, node B determines the corresponding data cache address in its corresponding storage space (also known as cache space). Node B sends a CompDBID message to node C to indicate permission to write the first data. The CompDBID message includes, but is not limited to, a command identifier, node B's identification information, and the data cache address.

[0168] S706-1, Node C sends an ACK message to Node A.

[0169] For example, in response to the CompDBID message, node C sends an ACK message to node A. The ACK message, also known as the first write response message, indicates that writing the first piece of data is permitted. The ACK message includes, but is not limited to, the command identifier, node B's identification information, and the data cache address.

[0170] S707-1, Node A sends a write message to Node B.

[0171] For example, in response to the ACK message, node A sends a write message (also called a W dat message, which is not limited in this application) to node B based on node B's identification information. The write message is used to instruct data to be written to a specified address. The write message includes, but is not limited to: first data, DBID, command identifier, etc.

[0172] S708-1, Node B writes the first data into the cache space.

[0173] For example, in response to a write message, node B writes the first data into the cache space indicated by DBID. Afterwards, node B can write the data in the cache space into memory; specific implementation methods can be found in existing technologies, and will not be elaborated upon here.

[0174] In this embodiment, to maintain the ordering characteristic of the same cacheline address, the cache node will only schedule the next CleanUnique request after receiving the Write Back message corresponding to the previous write request and replying with a CompDBID message. That is, as shown in Figure 7, after executing S705-1, the cache node can begin executing S702-2, which is the data processing flow corresponding to the second write request, specifically including:

[0175] S702-2, Node C sends a Cacheline status request message to Node B.

[0176] For example, node C responds to the second write request message to obtain the second cacheline address and other control information.

[0177] Node C sends a Cacheline status request message (e.g., a Clean Unique message) to Node B to request the E state of the target Cacheline to which the second Cacheline address belongs (see above for details). The Cacheline status request message includes, but is not limited to, Node C's identification information, the second Cacheline address, and an E state request indication.

[0178] For example, the identification information of node C can be the ID of node C, etc., which is not limited in this application. The E State request indicates the request for the E state of the target Cacheline, which can also be understood as a request for the use permission of the target Cacheline. Here, the target Cacheline is the Cacheline where the first Cacheline is located, which will not be repeated below.

[0179] S703-2, Node B sends a Cacheline status response message to Node C.

[0180] For example, as described above, node B can detect the status of the target cacheline. If the status of the target cacheline is determined to be available, node B sends a cacheline status response message to node C based on the identification information of node C. The message includes, but is not limited to, the E State of the target cacheline, which indicates that the permissions of the target cacheline be assigned to node C.

[0181] In this embodiment, in S704-1, node C has already returned the usage rights of the target Cacheline. Accordingly, in this step, node B detects that the target Cacheline is currently available.

[0182] For example, node B records the status of the target cacheline, such as the correspondence between the target cacheline and the identification information of node C, which is used to indicate that the current usage rights of the target cacheline are assigned to node C.

[0183] S704-2, Node C sends a Write Back message to Node B.

[0184] For example, node C determines that it has acquired usage rights (or access rights) to the target cacheline based on the cacheline status response message. Node C sends a Write Back message to node B to request the writing of second data and to indicate the release of the cacheline's E state. That is, in this embodiment, if no consecutive write requests to the same cacheline address are received within the merge window, node C releases the cacheline's usage rights.

[0185] The Write Back message includes, but is not limited to: Write Back indication information, node C's identification information, and the address of the second cacheline. The Write Back indication information is used to request the writing of data.

[0186] It should be noted that in merge window 2 (i.e., between S702-2 and S703-2 after node C executes S702-2), if node C receives a write request with the same cacheline address as the second write request message, it will process the second write request and other write requests with the same cacheline address according to the internal data processing flow of the node in Figure 6. This will not be repeated here, but the specific steps can be found in Figure 6.

[0187] S705-2, Node B sends a CompDBID message to Node C.

[0188] For example, in response to the Write Back message, node B revokes the permissions of the target cacheline corresponding to node C based on node C's identification information and the second cacheline address. That is, it marks the target cacheline as available.

[0189] Furthermore, based on the second cacheline address, node B determines the corresponding data cache address in its corresponding storage space (also known as cache space). Node B sends a CompDBID message to node C to indicate permission to write the second data. The CompDBID message includes, but is not limited to, a command identifier, node B's identification information, and the data cache address.

[0190] S706-2, Node C sends an ACK message to Node A.

[0191] For example, in response to the CompDBID message, node C sends an ACK message to node A. The ACK message, also known as the first write response message, indicates that writing second data is permitted. The ACK message includes, but is not limited to, the command identifier, node B's identification information, and the data cache address.

[0192] S707-2, Node A sends a write message to Node B.

[0193] For example, in response to the ACK message, node A sends a write message (also called a W dat message, which is not limited in this application) to node B based on node B's identification information. The write message is used to instruct data to be written to a specified address. The write message includes, but is not limited to, second data, DBID, command identifier, etc.

[0194] S708-2, Node B writes the second data into the cache space.

[0195] For example, in response to a write message, node B writes the second data into the cache space indicated by DBID. Afterwards, node B can write the data in the cache space into memory; specific implementation methods can be found in existing technologies, and will not be elaborated upon here.

[0196] In summary, small packets received outside the merge window are processed according to the original IO Cache mode (i.e., in Figure 5), thus avoiding negative consequences. This can be understood as follows: in the original IO Cache mode, node C manages requests. As an upstream node, it interacts with downstream node B based on the upstream data sender (e.g., PCIe, or other modules or chips, etc., not limited in this application) to write data from the data sender into node B. In this embodiment, if multiple small packets with the same cacheline address are received within the merge window, node C will execute its internal data processing flow. That is, through internal interaction, it writes multiple data packets into the corresponding cache space of node C, and then interacts with node B to write the corresponding data. This effectively reduces the number of interactions in scenarios with multiple data packets, thereby reducing transmission latency on the bus. Furthermore, the latency of internal node interaction is significantly shortened compared to bus data interaction, further improving the overall throughput of data processing.

[0197] Figure 8 shows a schematic block diagram of an apparatus 800 according to an embodiment of this application. The apparatus 800 may include a processor 801 and a transceiver / transceiver pin 802, and optionally, a memory 803. The processor 801 can be used to execute the steps performed by the database in the methods of the foregoing embodiments, and to control the receive pin to receive signals and control the transmit pin to transmit signals.

[0198] The various components of device 800 are coupled together via bus 804, which includes a data bus, a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus system 804 in the figure.

[0199] Optionally, the memory 803 can be used for storage instructions in the foregoing method embodiments.

[0200] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0201] Based on the same technical concept, embodiments of this application also provide a computer-readable storage medium storing a computer program containing at least one piece of code that can be executed by a computer to control the computer to implement the above-described method embodiments.

[0202] Based on the same technical concept, this application also provides a computer program, which, when executed by a computer, is used to implement the above-described method embodiments.

[0203] The program may be stored, in whole or in part, on a storage medium packaged with the processor, or in part or in whole on a memory not packaged with the processor.

[0204] Based on the same technical concept, this application also provides a processor for implementing the above-described method embodiments. The processor can be a chip.

[0205] The steps of the methods or algorithms described in conjunction with the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0206] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

Claims

1. A data processing method, characterized in that, include: The first management unit receives a first write request message, which is used to request that the first data be written to the target cache line. In response to the first write request message, the first management unit sends a first request message to the second management unit, the first request message being used to request permissions for the target Cacheline; If, before the first management unit receives the first response message from the second management unit, the first management unit receives at least one second write request, wherein the at least one second write request is used to request that at least one second piece of data be written to the target cacheline, then after receiving the first response message, the first management unit caches the first data and the at least one second piece of data in the first storage space corresponding to the first management unit; wherein the first response message is used to indicate the permissions of the target cacheline; The first management unit writes the target data into the second storage space corresponding to the second management unit. The target data includes the first data and the at least one second data.

2. The method according to claim 1, characterized in that, The first management unit includes a first management sub-node and a second management sub-node. After receiving the first response message, the first management unit caches the first data and the at least one piece of data in the first storage space corresponding to the first management unit, including: In response to the first response message, the first management sub-node sends a second request message to the second management sub-node. The second request message indicates that permission to the target cacheline has been obtained and requests that the first data be written to the target cacheline. The first management sub-node receives a second response message from the second management sub-node, the second response message indicating permission to write the first data; In response to the second response message, the first management sub-node requests the second management sub-node to write the at least one second data. During the process of the first management sub-node requesting the second management sub-node to write the at least one second data, the second management sub-node obtains the first data and writes the first data into the first storage space. The second management sub-node obtains the second data and writes the second data into the second storage space.

3. The method according to claim 2, characterized in that, The step of requesting the writing of at least one second piece of data to the second management sub-node includes: The first management sub-node sends a third request message to the second management sub-node, the third request message being used to request permissions for the target Cacheline; The first management sub-node receives a third response message sent by the second management sub-node, the third response message being used to indicate the permissions of the target Cacheline; In response to the third response message, the first management sub-node sends a fourth request message to the second management sub-node, the fourth request message being used to instruct the writing of a single second data to the target cacheline; The second management sub-node responds to the fourth request message, obtains the single second data, and writes the single second data into the first storage space after the first data is written into the first storage space.

4. The method according to claim 1, characterized in that, The method further includes: If the first management unit has not received any other requests to write data to the target cacheline before receiving the first response message from the second management unit, the first management unit requests the second management unit to write the third data to the target cacheline.

5. The method according to claim 4, characterized in that, The first management unit requests the second management unit to write the third data to the target cacheline, including: The first management unit sends a fifth request message to the second management unit, the fifth request message being used to request that the first data be written to the target cacheline; In response to the fifth response message sent by the second management unit, the first management unit sends a data transmission instruction message to the data transmission module. The data transmission instruction message is used to instruct the data transmission module to send the first data to the second management unit; the fifth response message is used to indicate that writing the first data is allowed.

6. A data processing apparatus, characterized in that, It includes a first management unit and a second management unit; The first management unit is configured to receive a first write request message, the first write request message being used to request that first data be written to the target cache line; The first management unit is further configured to send a first request message to the second management unit in response to the first write request message, the first request message being used to request permissions for the target Cacheline; The first management unit is further configured to, before receiving the first response message from the second management unit, receive at least one second write request, wherein the at least one second write request is used to request that at least one second data be written to the target Cacheline, then after receiving the first response message, the first management unit caches the first data and the at least one second data in the first storage space corresponding to the first management unit; wherein the first response message is used to indicate the permissions of the target Cacheline; The first management unit is further configured to write target data from the first storage space to the second management unit, the target data including the first data and the at least one second data.

7. The apparatus according to claim 6, characterized in that, The first management unit includes a first management sub-node and a second management sub-node. The first management sub-node is configured to send a second request message to the second management sub-node in response to the first response message. The second request message is configured to indicate that permission to the target Cacheline has been obtained and to request that the first data be written to the target Cacheline. The first management sub-node is further configured to receive a second response message from the second management sub-node, the second response message being used to indicate permission to write the first data; The first management sub-node is further configured to respond to the second response message by requesting the second management sub-node to write the at least one second data, and during the process of the first management sub-node requesting the second management sub-node to write the at least one second data, the second management sub-node obtains the first data and writes the first data into the first storage space; The second management sub-node is used to obtain the second data and write the second data into the second storage space.

8. The apparatus according to claim 7, characterized in that, The first management sub-node is further configured to send a third request message to the second management sub-node, the third request message being used to request permissions for the target Cacheline; The first management sub-node is further configured to receive a third response message sent by the second management sub-node, the third response message being used to indicate the permissions of the target Cacheline; The first management sub-node is further configured to send a fourth request message to the second management sub-node in response to the third response message, the fourth request message being used to instruct the writing of a single second data to the target cacheline; The second management sub-node is further configured to respond to the fourth request message, obtain the single second data, and write the single second data into the first storage space after the first data is written into the first storage space.

9. The apparatus according to claim 6, characterized in that, The first management unit is further configured to request the second management unit to write the third data to the target cacheline if it has not received any other requests to write data to the target cacheline before receiving the first response message from the second management unit.

10. The apparatus according to claim 9, characterized in that, The first management unit is configured to send a fifth request message to the second management unit, the fifth request message being used to request that the first data be written to the target cacheline; The first management unit is further configured to send data to the data sending module in response to the fifth response message sent by the second management unit. A data transmission instruction message is sent to instruct the data transmission module to send the first data to the second management unit; the fifth response message is used to indicate that writing the first data is permitted.

11. A chip, characterized in that, The device includes one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of the electronic device and send the signals to the processors, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device performs the method according to any one of claims 1-5.

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