Method and apparatus for managing accelerators, and device and storage medium

Abstract

In the embodiments of the present disclosure, provided are a method and apparatus for managing accelerators, and a device and a storage medium. The method for managing accelerators comprises: acquiring interface information associated with a group of accelerators in a computing device, wherein the interface information indicates at least corresponding identification information and corresponding mapping information of the group of accelerators, and the mapping information of one accelerator indicates a hardware resource in the computing device that is used for the accelerator; using a driver of the computing device to initialize the group of accelerators on the basis of the interface information; and using at least some accelerators in the group of initialized accelerators to execute a task. In this way, the configuration flexibility and utilization rate of accelerators can be improved.

Description

Method, apparatus, device, and storage medium for managing accelerator

[0001] This application claims priority to the Chinese invention patent application with application number 202311270375.5 filed on September 27, 2023, entitled “Methods, devices, apparatus and storage media for managing accelerators”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] Example embodiments of the present disclosure generally relate to the field of computers, and more particularly, to methods, devices, apparatuses, and computer-readable storage media for managing accelerators. Background Art

[0003] With the rapid development of big data and artificial intelligence applications, the demand for computing power has also increased significantly. For example, processors need to be extremely efficient when handling complex data analysis, machine learning, and deep learning tasks, resulting in the desire to configure processors in a more efficient manner.

[0004] Summary of the Invention

[0005] In a first aspect of the present disclosure, a method for managing accelerators is provided. The method includes: obtaining interface information associated with a group of accelerators in a computing device, the interface information indicating at least corresponding identification information and corresponding mapping information of the group of accelerators, wherein the mapping information of an accelerator indicates hardware resources for the accelerator in the computing device; initializing the group of accelerators using a driver of the computing device according to the interface information; and executing a task using at least a portion of the initialized group of accelerators.

[0006] In a second aspect of the present disclosure, an apparatus for managing accelerators is provided. The apparatus includes: an interface information acquisition module configured to acquire interface information associated with a group of accelerators in a computing device, the interface information indicating at least corresponding identification information and corresponding mapping information of the group of accelerators, wherein the mapping information of an accelerator indicates hardware resources for the accelerator in the computing device; an accelerator initialization module configured to initialize the group of accelerators using a driver of the computing device according to the interface information; and a task execution module configured to execute a task using at least a portion of the initialized group of accelerators.

[0007] In a third aspect of the present disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit. When executed by the at least one processing unit, the instructions cause the device to perform the method of the first aspect.

[0008] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and the computer program can be executed by a processor to implement the method of the first aspect.

[0009] It should be understood that the content described in this summary section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0011] FIG1 shows a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;

[0012] FIG2 illustrates a schematic diagram of an example architecture of a processing unit including an accelerator according to some embodiments of the present disclosure;

[0013] FIG3 is a schematic diagram showing an example mapping relationship between an accelerator and other hardware resources according to some embodiments of the present disclosure;

[0014] FIG4 is a schematic diagram showing an example of interface information according to some embodiments of the present disclosure;

[0015] FIG5 shows a schematic diagram of an example for managing an accelerator according to some embodiments of the present disclosure;

[0016] FIG6 shows a flowchart of a method for managing an accelerator according to some embodiments of the present disclosure;

[0017] FIG7 shows a block diagram of an apparatus for managing an accelerator according to some embodiments of the present disclosure; and

[0018] FIG8 shows a block diagram of a device capable of implementing various embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] It is understandable that before using the technical solutions disclosed in the various embodiments of this disclosure, the type, scope of use, usage scenarios, etc. of the personal information involved in this disclosure should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.

[0020] For example, in response to a user's active request, a prompt message is sent to the user to clearly inform the user that the operation requested will require the acquisition and use of the user's personal information. This allows the user to independently choose whether to provide personal information to the electronic device, application, server, storage medium, or other software or hardware that performs the operations of the disclosed technical solution based on the prompt message.

[0021] As an optional but non-limiting implementation, in response to receiving a user's active request, the prompt information may be sent to the user in the form of a pop-up window, for example, in which the prompt information may be presented in text form. Furthermore, the pop-up window may also contain a selection control for the user to select "agree" or "disagree" to provide personal information to the electronic device.

[0022] It is understandable that the above notification and user authorization process are merely illustrative and do not limit the implementation of the present disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of the present disclosure.

[0023] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) must comply with the requirements of relevant laws, regulations and relevant provisions.

[0024] As used herein, the term "in response to" refers to a state in which a corresponding event occurs or a condition is satisfied. It will be understood that the timing of executing a subsequent action executed in response to the event or condition is not necessarily strongly correlated with the time when the event occurs or the condition is satisfied. For example, in some cases, a subsequent action may be executed immediately upon the occurrence of the event or the satisfaction of the condition; in other cases, the subsequent action may be executed some time after the occurrence of the event or the satisfaction of the condition.

[0025] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0026] It should be noted that the titles of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and any type of embodiment may be included under any section / subsection. Furthermore, the embodiments described in any section / subsection may be combined in any manner with any other embodiments described in the same section / subsection and / or in different sections / subsections.

[0027] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may be included below. The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may be included below.

[0028] As briefly mentioned above, due to the ever-increasing demand for computing power, traditional general-purpose processors may not be efficient enough when handling complex data analysis, machine learning, and deep learning tasks. Given that general-purpose processors may consume more energy when handling specific tasks, the introduction of specialized accelerators can provide higher energy efficiency and lower power consumption. This is crucial for extending battery life, reducing heat generation, and improving device performance. For example, graphics processing units (GPUs) can perform graphics rendering more efficiently than central processing units (CPUs). Another example is the tensor processing unit (TPU), designed for deep learning tasks, which can significantly accelerate the training and inference of machine learning models.

[0029] In addition, accelerators supported by some application platforms are usually programmable, allowing developers to customize and optimize them as needed. Therefore, accelerators have become an important solution to meet application needs.

[0030] Some accelerator devices, such as those targeting the Peripheral Component Interconnect Express (PPCIe) bus standard, can be configured on X86 application platforms. However, there is no universal solution for configuring accelerator devices that do not conform to the PCIe bus standard on application platforms such as those based on the Advanced Reduced Instruction Set (RISC).

[0031] In order to at least partially solve the above problems, an embodiment of the present disclosure proposes a solution for managing accelerators. According to various embodiments of the present disclosure, interface information associated with a group of accelerators in a computing device is obtained. The interface information at least indicates the corresponding identification information and corresponding mapping information of these accelerators. The mapping information of each accelerator indicates the hardware resources used for the accelerator in the computing device, such as an address translation unit, an interrupt service unit, etc. The driver of the computing device then initializes this group of accelerators based on the interface information, for example, enumerates these accelerators. Furthermore, in subsequent business processing, at least a part of this group of initialized accelerators is used to perform tasks according to actual needs. According to an embodiment of the present disclosure, the accelerator is used as a platform device, and PCIe enumeration is not required. Instead, the enumeration of the accelerator is completed by the driver. In this way, the configuration flexibility and utilization rate of the accelerator can be improved.

[0032] Example embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0033] 1 shows a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented. In environment 100, computing device 110 includes hardware for performing computing-related tasks. Such computing device 110 is, for example, a personal computer, a server, a mobile device, etc.

[0034] The computing device 110 includes one or more accelerators 130, such as accelerator 130-1, accelerator 130-2, ..., accelerator 130-N, etc. These accelerators may be individually or collectively referred to as accelerators 130. Such accelerators 130 may be utilized to increase the execution speed of specific types of tasks (such as graphics processing, machine learning, etc.) or specific types of data.

[0035] The operating system 120 may be software running on the computing device 110 for allocating resources to applications running on the computing device 110. Furthermore, the operating system 120 may utilize the computing device 110 to perform tasks and may utilize the accelerator 130 to accelerate specific types of tasks or specific types of data.

[0036] It should be understood that the structure and functionality of the environment 100 are described for exemplary purposes only and do not imply any limitation on the scope of the present disclosure. The architecture for managing accelerators will be described below from a hardware level with reference to FIG2 and FIG3 .

[0037] 2 shows a schematic diagram of an example architecture 200 of a processing unit including an accelerator according to some embodiments of the present disclosure. Architecture 200 may include multiple processing units, such as processing unit 210-1, processing unit 210-2, ..., processing unit 210-X, etc. These processing units may be individually or collectively referred to as processing units 210.

[0038] Each processing unit 210 may include multiple processing cores, such as processing core 220-1, processing core 220-2, ..., processing core 220-Y, and so on. These processing cores may be individually or collectively referred to as processing cores 220. As the basic components of processing unit 210, processing cores 220 can execute various instructions collaboratively or independently and coordinate system resources. Processing cores 220 can run multiple threads or processes simultaneously and share certain resources such as caches and registers.

[0039] Each processing unit 210 may further include a system memory management unit (SMMU) 230. The SMMU 230 may be used for address translation between an interface device and a bus, memory attribute translation, and permission checking.

[0040] Each processing unit 210 may further include an accelerator 130. In some embodiments, such as shown in FIG2 , the accelerator 130 may include multiple acceleration units, such as acceleration unit 250-1, acceleration unit 250-2, ..., acceleration unit 250-Z, etc. These acceleration units may be individually or collectively referred to as acceleration units 250. An accelerator 130 including multiple acceleration units 250 is also referred to as a first accelerator.

[0041] In some embodiments, an accelerator 130 can be considered as an independent platform device, serving as a parent device for its multiple acceleration units 250. This allows for unified acceleration unit resource management, device-wide error handling and recovery, and other operational support for the accelerator.

[0042] In some embodiments, depending on the device configuration settings in the Basic Input / Output System (BIOS) and the support of the dynamic Advanced Configuration and Power Interface (ACPI), one acceleration unit 250 can be considered an independent platform device, or a combination of multiple acceleration units 250 can be considered a platform device. Thus, one or more acceleration units 250 can be sub-devices attached to an accelerator 130.

[0043] It should be understood that although each processing unit 210 is shown as including the same number of processing cores and acceleration units, these processing units 210 may respectively include any appropriate number of processing cores and acceleration units, or may only include an appropriate number of processing cores and one accelerator, and the present disclosure is not limited to this.

[0044] 3 illustrates a schematic diagram of an example mapping relationship 300 between an accelerator and other hardware resources according to some embodiments of the present disclosure. The mapping relationship 300 generally relates to the accelerator 130, the SMMU 230, and the interrupt controller 320. With respect to the accelerator 130, the SMMU 230 and the interrupt controller 320 can be considered hardware resources available to the accelerator 130 in the computing device 110.

[0045] The accelerator 130 is mounted to the bus 310 via the SMMU 230. The SMMU 310 is used to achieve security isolation between the accelerators 130 or between the multiple acceleration units 250 contained in each accelerator 130. For example, the SMMU 310 can assign a stream ID (Stream ID, SID) to each attached or mounted accelerator 130. Thus, the SID can be used to identify different accelerators 130, thereby achieving security isolation between accelerators. For another example, the SMMU 310 can also assign a substream ID (SubStream ID, SSID) to each attached or mounted acceleration unit 250. Thus, the SSID can be used to identify different acceleration units 250, thereby achieving isolation of process address spaces.

[0046] The SMMU 230 can convert the flow identifier into a device identifier (device ID) recognizable by the interrupt controller 320 and communicate with the interrupt controller 320 via the bus 310. The interrupt controller 320 is used to manage and distribute interrupt signals generated by hardware devices. For example, when the accelerator 130 or the acceleration unit 250 triggers an interrupt signal, such an interrupt signal is sent to the interrupt controller 320 via the SMMU 230. The interrupt controller 320 provides an interrupt translation service (ITS) to facilitate the operating system 120 to determine which accelerator 130 or which acceleration unit 250 triggered the interrupt signal and execute the corresponding interrupt handler.

[0047] The above describes an example architecture for managing accelerators from a hardware perspective. The example architecture 200 and the example mapping relationship 300 can be implemented in the environment 100. Continuing with FIG1 , the operating system 120 can obtain interface information associated with a set of accelerators 130 in the computing device 110. This interface information can include identification information for the set of accelerators 130 and corresponding mapping information. The mapping information for each accelerator 130 can indicate the hardware resources in the computing device 110 for that accelerator, such as the SMMU and ITS for that accelerator.

[0048] In some embodiments, the interface information may be reported by the firmware to the operating system 120. For example, during a power-on self-test (POST) phase, the firmware may report the interface information used by the accelerator 130 to the operating system 120.

[0049] In some embodiments, the interface information may include a description table and a mapping table to help the operating system 120 identify the accelerator and determine the hardware resources for the accelerator. Figure 4 shows a schematic diagram of an example 400 of interface information according to some embodiments of the present disclosure. Example 400 may include at least one of a mapping table 410, a description table 420 (also referred to as a first description table), or a description table 430 (also referred to as a second description table).

[0050] In some embodiments, the mapping table 410 indicates the hardware resources for each accelerator in the computing device 110, such as the SMMU, the interrupt translation service provided by the interrupt controller, etc. Exemplarily, the mapping table 410 includes an ITS node 412, an SMMU node 414, and a component node 416. In the mapping table 410, the component node 416 indicates the mapping relationship between the accelerator 130 (for example, accelerator 1, accelerator 2, accelerator 3, etc. shown in Figure 4) and the SMMU and ITS. Through such a mapping table 410, it can be ensured that the accelerator 130 can normally initiate interrupts in the operating system 120, such as line interrupts and message signaled interrupts (MSIs). The SMMU node 414 indicates the SMMU hardware information in the computing device 110, and the ITS node 416 indicates the ITS-related hardware information in the computing device 110. The mapping table 410 can be, for example, an input-output remapping table (IORT).

[0051] In some embodiments, description table 420 includes a set of corresponding hardware identifiers (HIDs) and corresponding register addresses of accelerator 130 to ensure that the operating system can normally access the registers of accelerator 130. Such description table 420 may include, for example, a differentiated system description table (DSDT). In the Advanced Configuration and Power Interface (ACPI) specification, DSDT supports matching hardware identifiers defined and described to corresponding accelerators.

[0052] A hardware identifier is a unique symbol used to identify and distinguish hardware devices. It typically consists of a set of numbers and letters. Typically, a hardware identifier is assigned to each device by the device manufacturer during the manufacturing process. However, the ACPI specification does not describe accelerators 130 as platform devices.

[0053] In some embodiments, a set of customized accelerator hardware identifiers can be used to ensure that the operating system 120 can identify and run the accelerators. For example, the accelerator 130 includes three types of accelerators, such as CDA accelerators, DTE accelerators, and DLA accelerators. For CDA accelerators, their hardware identifiers are, for example, BCDA0000, BCDA0001, BCDA0002, etc. For DTE accelerators, their hardware identifiers are, for example, BDTE0000, BDTE0001, BDTE0002, etc. For DLA accelerators, their hardware identifiers are, for example, DBLA0000, DBLA0001, DBLA002, etc. This allows the accelerators to be treated as platform devices and assigned hardware identifiers.

[0054] In some embodiments, one or more of the accelerators 130 (also referred to as the first accelerator) may include multiple acceleration units 250, or multiple acceleration units of the first accelerator may need to be exposed to the operating system as platform devices. In such an embodiment, the description table 420 may include the hardware identifier of the first accelerator and the register address corresponding to the first accelerator, and may also include the register address corresponding to each acceleration unit. This allows the acceleration units to be treated as sub-devices and assigned register addresses. In this way, flexible configuration of the acceleration units is possible.

[0055] In some embodiments, description table 430 includes corresponding identifiers of hardware resources for a group of accelerators 130 in computing device 110 to ensure that the group of accelerators 130 can properly access the interrupt controller. Such description table 420 may include, for example, an Advanced Programmable Interrupt Controller Description Table (MADT). In the ACPI specification, MADT includes information related to interrupt controllers, such as the ITS indexes shown in FIG4 , such as ITS 0, ITS1, and ITS2.

[0056] The interface information associated with a set of accelerators 130 is described above through multiple embodiments. After obtaining such interface information, the operating system 120 can use the driver of the computing device 110 to initialize a set of accelerators 130 according to such interface information. In other words, the driver enumerates the reported accelerators and their acceleration units (if applicable). Exemplarily, the driver first detects the accelerators 130 in the computing device 110, and then enumerates and initializes the available accelerators 130 one by one. Further, the operating system 120 can use the initialized accelerators 130 to perform tasks. Exemplarily, after initializing the accelerators 130, the operating system 120 can select an accelerator with a suitable computing architecture and programming interface from the initialized accelerators 130 to perform calculations. A specific example is described below with reference to Figure 5.

[0057] Figure 5 shows a schematic diagram of an example 500 for managing accelerators according to some embodiments of the present disclosure. Specifically, in box 510, the firmware side reports interface information associated with the accelerator, such as IORT, MADT, DSDT, etc. in ACPI shown in Figure 4. In box 520, the driver side matches the accelerator based on the reported interface information and performs accelerator enumeration. That is, the driver side searches for all available accelerators in the computing device 110 and performs hardware enablement on the found accelerators. In box 530, the user side uses at least a portion of the enumerated accelerators to perform specific tasks, such as parallel computing tasks. Depending on the specific implementation, the user side may use one or more accelerators among the enumerated accelerators, or one or more acceleration units.

[0058] In some embodiments, the operating system 120 (e.g., a driver) can also utilize the driver to set a sharing mode for the acceleration unit. Such a sharing mode indicates whether the acceleration unit can be shared by multiple processes. In this way, the problem of limiting the number of acceleration units can be solved.

[0059] For example, the operating system 120 can set multiple acceleration units in a group of accelerators to support the shared mode as needed, so that these acceleration units can only be shared and used by multiple processes. Such multiple acceleration units can be acceleration units attached to one accelerator, or they can be acceleration units attached to different accelerators, and the present disclosure does not limit this. For another example, the firmware side can report which acceleration unit or units support the shared mode in the interface information. Furthermore, the driver side can set the shared mode based on the report from the firmware side.

[0060] In some embodiments, an accelerator or acceleration unit can be used as a standalone device. In some embodiments, one or more acceleration units can be assigned to a virtual machine for use. Referring to Figure 2 , for a processing unit 210, the operating system 120 can also assign a first number of processing cores 220 and a second number of acceleration units 250 to a virtual machine, and execute tasks through the virtual machine. This approach enables flexible use of acceleration units in different application scenarios.

[0061] For example, the operating system 120 can use the SMMU 230 to assign an SSID to each acceleration unit 250. When performing a virtualized deployment, an appropriate number of processing cores 220 and an appropriate number of acceleration units 250 are bound for use, for example, four processing cores 220 and four acceleration units 250 are assigned to one virtual machine. The operating system 120 can also dynamically configure the first number and the second number for different application scenarios. Additionally or alternatively, the first number of processing cores 220 and the second number of acceleration units 250 can also be used as a standalone device in a non-virtualized deployment.

[0062] In some embodiments, computing device 110 is based on an advanced RISC architecture (RISA), and as shown in FIG2 , computing device 110 may include multiple processing units 210, which in turn may include a set of accelerators 130. In this way, the requirements for computing power, energy efficiency, and power consumption of an RISA, as well as diverse application scenarios and programmability, can be met.

[0063] In summary, this disclosure proposes using an accelerator as a platform device and defining its hardware identity. Furthermore, based on the acquired interface information associated with the accelerator, a driver can be used to initialize the accelerator and execute tasks using the initialized accelerator. This allows for accelerator management solutions for non-PCIe bus standards without requiring PCIe bus enumeration. This approach improves accelerator configuration flexibility and utilization.

[0064] Example Process

[0065] 6 shows a flow chart of a method 600 for managing an accelerator according to some embodiments of the present disclosure. The method 600 may be implemented in the operating system 120. The method 600 is described below with reference to FIG1.

[0066] At block 610 , the operating system 120 obtains interface information associated with a set of accelerators in the computing device. The interface information indicates at least corresponding identification information and corresponding mapping information of the set of accelerators, wherein the mapping information of an accelerator indicates hardware resources for the accelerator in the computing device.

[0067] At block 620 , the operating system 120 utilizes a driver of the computing device to initialize a set of accelerators based on the interface information.

[0068] At block 630 , the operating system 120 utilizes at least a portion of the initialized set of accelerators to execute a task.

[0069] In some embodiments, the interface information is reported by the firmware to the operating system of the computing device.

[0070] In some embodiments, the interface information includes at least one of the following: a first description table including corresponding hardware identifications and corresponding register addresses of a set of accelerators, a mapping table indicating, for each accelerator in the set of accelerators, at least one hardware resource in the computing device for the accelerator, or a second description table including corresponding identifications of hardware resources in the computing device for the set of accelerators.

[0071] In some embodiments, at least a first accelerator in a group of accelerators includes multiple acceleration units, and the first description table includes at least any of the following: a hardware identification of the first accelerator, a register address corresponding to the first accelerator, or register addresses corresponding to the multiple acceleration units respectively.

[0072] In some embodiments, the at least one hardware resource includes at least one of: a system memory management unit, or an interrupt translation service.

[0073] In some embodiments, initializing a group of accelerators includes: using a driver to set corresponding sharing modes of a plurality of acceleration units, wherein the sharing mode of an acceleration unit indicates whether the acceleration unit is shared by a plurality of processes.

[0074] In some embodiments, the computing device is based on an advanced RISC architecture and includes a set of accelerators in a processing unit of the computing device.

[0075] In some embodiments, the computing device includes multiple processing cores, a second accelerator in a group of accelerators includes multiple acceleration units, and executing the task includes: allocating a first number of processing cores in the multiple processing cores and a second number of acceleration units in the multiple acceleration units to a virtual machine; and executing the task through the virtual machine.

[0076] Example devices and equipment

[0077] 7 shows a schematic structural block diagram of an apparatus 700 for managing an accelerator according to certain embodiments of the present disclosure. Apparatus 700 may be implemented as or included in operating system 120. Each module / component in apparatus 700 may be implemented by hardware, software, firmware, or any combination thereof.

[0078] As shown, apparatus 700 includes an interface information acquisition module 710 configured to acquire interface information associated with a group of accelerators in a computing device. The interface information indicates at least corresponding identification information and corresponding mapping information for the group of accelerators, wherein the mapping information for an accelerator indicates the hardware resources for that accelerator in the computing device. Apparatus 700 also includes an accelerator initialization module 720 configured to utilize a driver of the computing device to initialize the group of accelerators based on the interface information. Apparatus 700 also includes a task execution module 730 configured to utilize at least a portion of the initialized group of accelerators to execute a task.

[0079] In some embodiments, the interface information is reported by the firmware to the operating system of the computing device.

[0080] In some embodiments, the interface information includes at least one of the following: a first description table including corresponding hardware identifications and corresponding register addresses of a set of accelerators, a mapping table indicating, for each accelerator in the set of accelerators, at least one hardware resource in the computing device for the accelerator, or a second description table including corresponding identifications of hardware resources in the computing device for the set of accelerators.

[0081] In some embodiments, at least a first accelerator in a group of accelerators includes multiple acceleration units, and the first description table includes at least any of the following: a hardware identification of the first accelerator, a register address corresponding to the first accelerator, or register addresses corresponding to the multiple acceleration units respectively.

[0082] In some embodiments, the at least one hardware resource includes at least one of: a system memory management unit, or an interrupt translation service.

[0083] In some embodiments, the accelerator initialization module 720 is further configured to use a driver to set corresponding sharing modes of the multiple acceleration units, where the sharing mode of an acceleration unit indicates whether the acceleration unit is shared by multiple processes.

[0084] In some embodiments, the computing device is based on an advanced RISC architecture and includes a set of accelerators in a processing unit of the computing device.

[0085] In some embodiments, the computing device includes multiple processing cores, a second accelerator in a set of accelerators includes multiple acceleration units, and the task execution module is further configured to assign a first number of processing cores in the multiple processing cores and a second number of acceleration units in the multiple acceleration units to a virtual machine; and execute the task through the virtual machine.

[0086] FIG8 shows a block diagram of an electronic device 800 in which one or more embodiments of the present disclosure may be implemented. It should be understood that the electronic device 800 shown in FIG8 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. The electronic device 800 shown in FIG8 can be used to implement the operating system 120 of FIG1 .

[0087] As shown in FIG8 , electronic device 800 is a general-purpose electronic device. Components of electronic device 800 may include, but are not limited to, one or more processors or processing units 810, memory 820, storage device 830, one or more communication units 840, one or more input devices 850, and one or more output devices 860. Processing unit 810 may be a real or virtual processor and is capable of performing various processes according to programs stored in memory 820. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to enhance the parallel processing capabilities of electronic device 800.

[0088] The electronic device 800 typically includes a plurality of computer storage media. Such media can be any accessible media that can be obtained by the electronic device 800, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 820 can be a volatile memory (e.g., a register, a cache, a random access memory (RAM)), a non-volatile memory (e.g., a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 830 can be a removable or non-removable medium and can include a machine-readable medium, such as a flash drive, a disk, or any other medium that can be used to store information and / or data (e.g., training data for training) and can be accessed within the electronic device 800.

[0089] The electronic device 800 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not shown in FIG8 , a disk drive for reading from or writing to a removable, non-volatile disk (e.g., a “floppy disk”) and an optical drive for reading from or writing to a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data media interfaces. The memory 820 may include a computer program product 825 having one or more program modules configured to perform various methods or actions of various embodiments of the present disclosure.

[0090] The communication unit 840 enables communication with other electronic devices via a communication medium. Additionally, the functions of the components of the electronic device 800 can be implemented in a single computing cluster or multiple computing machines that can communicate via a communication connection. Thus, the electronic device 800 can operate in a networked environment using a logical connection with one or more other servers, a network personal computer (PC), or another network node.

[0091] The input device 850 may be one or more input devices, such as a mouse, keyboard, or trackball. The output device 860 may be one or more output devices, such as a display, a speaker, or a printer. The electronic device 800 may also communicate with one or more external devices (not shown) via the communication unit 840 as needed, such as a storage device, a display device, or the like, with one or more devices that allow a user to interact with the electronic device 800, or with any device that allows the electronic device 800 to communicate with one or more other electronic devices (e.g., a network card, a modem, etc.). Such communication may be performed via an input / output (I / O) interface (not shown).

[0092] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which computer-executable instructions are stored, wherein the computer-executable instructions are executed by a processor to implement the method described above. According to an exemplary implementation of the present disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the method described above.

[0093] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatuses, devices, and computer program products implemented according to the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0094] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, such that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0095] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0096] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple implementations of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part for a module, program segment or instruction, and a part for a module, program segment or instruction comprises one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0097] While various implementations of the present disclosure have been described above, the foregoing description is intended to be illustrative, not exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is selected to best explain the principles of the implementations, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A method for managing an accelerator, comprising: Acquire interface information associated with a group of accelerators in a computing device, the interface information at least indicating corresponding identification information and corresponding mapping information of the group of accelerators, wherein the mapping information of one accelerator indicates hardware resources for the accelerator in the computing device; Initializing the set of accelerators according to the interface information using a driver of the computing device; as well as A task is performed using at least a portion of the initialized set of accelerators. 2 . The method according to claim 1 , wherein the interface information is reported by firmware to an operating system of the computing device.

3. The method according to claim 1, wherein the interface information comprises at least one of the following: A first description table includes corresponding hardware identifiers and corresponding register addresses of the group of accelerators, a mapping table, for each accelerator in the set of accelerators, indicating at least one hardware resource in the computing device for the accelerator, or The second description table includes corresponding identifiers of hardware resources for the group of accelerators in the computing device.

4. The method of claim 3, wherein at least a first accelerator in the set of accelerators comprises a plurality of acceleration units, and the first description table comprises at least any one of the following: a hardware identifier of the first accelerator, corresponds to the register address of the first accelerator, or The register addresses respectively correspond to the multiple acceleration units.

5. The method according to claim 3, wherein the at least one hardware resource comprises at least one of the following: The system memory management unit, or Interruption of translation service.

6. The method of claim 4, wherein initializing the set of accelerators comprises: The driver is used to set corresponding sharing modes of the plurality of acceleration units, wherein the sharing mode of one acceleration unit indicates whether the acceleration unit is shared by a plurality of processes. 7 . The method according to claim 1 , wherein the computing device is based on an advanced reduced instruction set architecture, and the set of accelerators is included in a processing unit of the computing device.

8. The method of claim 1 , wherein the computing device comprises a plurality of processing cores, a second accelerator in the set of accelerators comprises a plurality of acceleration units, and performing the task comprises: Allocating a first number of processing cores among the plurality of processing cores and a second number of acceleration units among the plurality of acceleration units to a virtual machine; as well as The task is executed by the virtual machine.

9. A device for managing an accelerator, comprising: an interface information acquisition module, configured to acquire interface information associated with a group of accelerators in a computing device, wherein the interface information at least indicates corresponding identification information and corresponding mapping information of the group of accelerators, wherein the mapping information of one accelerator indicates hardware resources for the accelerator in the computing device; an accelerator initialization module, configured to initialize the set of accelerators according to the interface information using a driver of the computing device; as well as The task execution module is configured to execute a task using at least a portion of the initialized set of accelerators.

10. An electronic device, comprising: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 8 when executed by the at least one processing unit.

11. A computer-readable storage medium having a computer program stored thereon, wherein the computer program can be executed by a processor to implement the method according to any one of claims 1 to 8.

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