Solid-state imaging element, and method for manufacturing solid-state imaging element

Abstract

This solid-state imaging element comprises: a semiconductor substrate including a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type; a plurality of junction terminals that are electrically connected to the second regions and are respectively connected to different external terminals; and a gate terminal electrically insulated from the second regions. The plurality of junction terminals include a first terminal which, by being connected to some of the plurality of second regions, is connected to the first region by a first path via a PN junction between said second regions and the first region, and which is connected to the first region by a second path via a first resistor formed by a transistor constituting a readout circuit, the first terminal constituting the readout circuit.

Description

Solid-state imaging device and method for manufacturing the same

[0001] The present disclosure relates to a solid-state imaging device and a method for manufacturing a solid-state imaging device.

[0002] Patent Document 1 describes a back-illuminated solid-state imaging device. In this solid-state imaging device, a horizontal shift register is provided at the end of the imaging region in the charge transfer direction. Charge transfer electrodes are arranged in the horizontal shift register, and a charge readout circuit is provided at the final position of the charge transfer. The charge readout circuit includes a signal gate region located at the end of the horizontal shift register, connected to an electrode pad. A floating diffusion region is provided adjacent to this signal gate region via a MOS-FET transistor. The floating diffusion region is connected to a reset drain electrode pad via a reset transistor Q2 and is also connected to the gate electrode of an output transistor Q3. One terminal of the output transistor Q3 is connected to an overflow drain electrode pad, and the other terminal forms an output terminal. A load resistor is connected to the output terminal. A reset gate electrode pad is connected to the gate electrode of transistor Q2.

[0003] JP 2010-232495 A

[0004] As described in the above-mentioned Patent Document 1, a solid-state imaging device is provided with a plurality of connection terminals, such as an output terminal and a reset drain electrode pad. When connecting these connection terminals to external connection terminals, it is considered to form connection portions, such as solder bumps or wires, on a plating layer (UBM (Under Bump Metal)) of the connection terminals. In this case, defective connection portions may occur in some of the connection terminals.

[0005] Therefore, an object of the present disclosure is to provide a solid-state imaging element capable of suppressing defective formation of a connection portion, and a method for manufacturing the solid-state imaging element.

[0006] As a result of extensive research into solving the above-mentioned problems, the inventors of the present invention have come to the following conclusion regarding one cause of defective connection in some joint terminals. Specifically, joint terminals with defective connection tend to have a large amount of Ni detected on the surface of the plating layer. Normally, the presence of Au on the outermost surface of a joint terminal prevents Ni from oxidizing, but the presence of oxidized Ni on the outermost surface is thought to inhibit the formation of an alloy layer with solder on the surface of the plating layer, resulting in defective connection.

[0007] On the other hand, it was confirmed that among the plurality of joining terminals, some are prone to forming defective connections and others are not. For example, among the plurality of joining terminals, joining terminals that constitute a readout circuit, such as an output source (OS) terminal or an output drain (OD) terminal, are not prone to forming defective connections, whereas joining terminals that do not constitute a readout circuit, such as a reset drain (RD) terminal or an overflow drain (OFD) terminal, tend to be prone to forming defective connections.

[0008] The factors that cause this tendency are thought to be as follows: The junction terminals that constitute the readout circuit are connected to a semiconductor region including a PN junction and are also connected to a constant potential such as GND via a path other than the PN junction, which stabilizes the potential when the plating layer is formed, thereby suppressing Ni deposition on the Au, making it less likely that a defective connection will occur. On the other hand, in the case of junction terminals that do not constitute the readout circuit, conventionally, they are not connected to a constant potential via a path other than the PN junction, which does not sufficiently stabilize the potential when the plating layer is formed to suppress Ni deposition on the Au, making it more likely that a defective connection will occur.

[0009] In response to this problem, the present inventors connected junction terminals, which were not previously connected to a constant potential via a path other than a PN junction, to a constant potential via a polysilicon resistor, and found that poor connection formation was suppressed. This is thought to be due in part to the fact that, as described above, connection to a constant potential via a PN junction and connection to a constant potential via a polysilicon resistor are formed, thereby stabilizing the potential during plating layer formation. The present disclosure is the result of further investigations conducted by the present inventors based on the above findings.

[0010] That is, the solid-state imaging element according to the present disclosure is [1] "a solid-state imaging element comprising: a semiconductor substrate having a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type; a plurality of junction terminals electrically connected to the second regions and connected to different external terminals, and a gate terminal electrically insulated from the second regions, wherein the plurality of junction terminals are connected to some of the second regions, thereby being connected to the first region by a first path via a PN junction between the second region and the first region, and connected to the first region by a second path via a first resistor generated in a transistor constituting a readout circuit, and a first terminal constituting a part different from the readout circuit, wherein the plurality of junction terminals are connected to another part of the second regions, thereby being connected to the first region by a third path via a PN junction between the second region and the first region, and connected to the first region by another fourth path via a second resistor different from the first resistor."

[0011] This solid-state imaging device includes a plurality of junction terminals connected to a second region of a second conductivity type on a semiconductor substrate. The plurality of junction terminals include a first terminal constituting a readout circuit and a second terminal not constituting the readout circuit. The first terminal constituting the readout circuit is connected to the first region of the semiconductor substrate (i.e., the constant potential of the first region) by a first path via a PN junction formed in the semiconductor substrate, and is further connected to the first region by a second path via a first resistor generated in a transistor of the readout circuit. Therefore, as described above, the potential of the first terminal is stabilized when the plating layer is formed. Furthermore, the second terminal not constituting the readout circuit is connected to the first region by a third path via a PN junction formed in the semiconductor substrate, and is separately connected to the first region by a fourth path via a second resistor. Therefore, the potential of the second terminal is also stabilized when the plating layer is formed. Therefore, this solid-state imaging device suppresses defective formation of connections such as solder bumps and wires on the junction terminals. In this solid-state imaging device, the connecting terminals are connected to different external terminals, so that an optimum potential can be applied to each connecting terminal.

[0012] The solid-state imaging device according to the present disclosure may be [2] "the solid-state imaging device according to the above [1], wherein the second resistor is made of a polysilicon resistor." In this case, it becomes possible to easily form a connection to the first region via the second resistor having a suitable resistance value.

[0013] The solid-state imaging device according to the present disclosure may be [3] "the solid-state imaging device according to [1] or [2] above, wherein the resistance value of the second resistor is 1 kΩ or more and 100 kΩ or less." In this case, it is possible to preferably stabilize the potential at the first terminal and the second terminal when forming the plating layer, and it is also possible to suppress instability of operation due to a low resistance value between the second terminal and the first region.

[0014] The solid-state imaging device according to the present disclosure may be [4] "the solid-state imaging device according to any one of [1] to [3] above, in which the second terminal includes at least one of a reset drain terminal, a scupper drain terminal, and an overflow drain terminal." In this way, various terminals can be applied as the second terminal.

[0015] The solid-state imaging device according to the present disclosure may be [5] "the solid-state imaging device according to any one of [1] to [4] above, in which the joining terminals are connected to the external terminals by bump bonding." In this case, it is more effective to suppress defective formation of the connection portions (e.g., solder bumps) than when, for example, the joining terminals are connected to the external terminals by wire bonding.

[0016] The solid-state imaging device according to the present disclosure may be [6] "the solid-state imaging device according to any one of [1] to [5] above, in which the joining terminal includes a plurality of the second terminals." In this case, defective formation of the connection portion is suppressed in the joining terminal including the plurality of second terminals.

[0017] The solid-state imaging device according to the present disclosure may be [7] "the solid-state imaging device according to the above [6], in which each of the second terminals is connected to the first region by a fourth path different from each other." In this way, the second terminals do not need to share the fourth path to the first region.

[0018] The solid-state imaging device according to the present disclosure may be [8] "the solid-state imaging device according to the above [7], in which the second resistors provided in the different fourth paths have different resistance values." In this case, it is possible to set an appropriate resistance value of the second resistor for the second terminals having different allowable current values.

[0019] The solid-state imaging device according to the present disclosure may be [9] "the solid-state imaging device according to any one of [1] to [8] above, in which a wiring portion from the second terminal to the PN junction of the third path is made of only metal wiring." In this way, a resistive element does not need to be interposed in the wiring portion between the second terminal and the PN junction.

[0020] The solid-state imaging device according to the present disclosure may be

[10] "the solid-state imaging device according to any one of [1] to [9] above, in which the thickness of the first region is greater than the thickness of the second region." In this case, the potential of the first region is more likely to be stable, thereby making it possible to reliably prevent defective formation of the connection portion.

[0021] The solid-state imaging device according to the present disclosure may be

[11] "the solid-state imaging device according to any one of [1] to

[10] above, wherein the semiconductor substrate has the first conductivity type and further has a third region having an impurity concentration higher than the impurity concentration of the first region, and the first terminal is connected to the first region via the third region in the second path." In this case, it is possible to connect the first terminal and the semiconductor region with lower resistance.

[0022] A method for manufacturing a solid-state imaging device according to the present disclosure

[12] includes: "a first step of preparing a semiconductor substrate having a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type; a second step of forming, after the first step, a plurality of junction terminals electrically connected to the second region; and a third step of forming, after the second step, a plating layer on surfaces of the plurality of junction terminals, wherein the second step is performed to connect the plurality of junction terminals to some of the plurality of second regions, thereby connecting the plurality of junction terminals to the first region by a first path via a PN junction between the second region and the first region." a fourth step of forming, as the junction terminal, a first terminal constituting the readout circuit, the first terminal being connected to the first region by a second path via a first resistance generated in a transistor constituting a readout circuit; and a fifth step of forming, as the junction terminal, a second terminal being connected to another second region of the plurality of second regions, the second terminal being connected to the first region by a third path via a PN junction between the second region and the first region, and the first region by a fourth path not via the first resistance, the second terminal constituting a part different from the readout circuit.

[0023] This method for manufacturing a solid-state imaging device includes a second step of forming a plurality of junction terminals connected to a second region of a second conductivity type in a semiconductor substrate. The second step includes a fourth step of forming a first terminal constituting a readout circuit and a fifth step of forming a second terminal not constituting the readout circuit. In the fourth step, the first terminal constituting the readout circuit is formed so as to be connected to a first region of the semiconductor substrate (i.e., the constant potential of the first region) by a first path via a PN junction formed in the semiconductor substrate and further connected to the first region by a second path via a first resistance generated in a transistor of the readout circuit. As described above, this stabilizes the potential of the first terminal when forming the plating layer in the third step. Furthermore, in the fifth step, the second terminal not constituting the readout circuit is formed so as to be connected to the first region by a third path via a PN junction formed in the semiconductor substrate and separately connected to the first region by a fourth path. As a result, this stabilizes the potential of the second terminal when forming the plating layer in the third step. Therefore, in this method for manufacturing a solid-state imaging device, defective formation of the connection portions of the solder bumps, wires, etc. at the joining terminals is suppressed.

[0024] The manufacturing method of a solid-state imaging element according to the present disclosure may be

[13] "the manufacturing method of a solid-state imaging element according to the above

[12] , wherein in the fifth step, a second resistor is formed so as to be interposed in the fourth path between the second terminal and a constant potential." In this way, by interposing an appropriate second resistor between the second terminal and the first region, it is possible to preferably stabilize the potential during formation of the plating layer while suppressing instability of operation.

[0025] The manufacturing method of a solid-state imaging device according to the present disclosure may be

[14] "the manufacturing method of a solid-state imaging device according to the above

[12] or

[13] , including a sixth step of disconnecting the fourth path between the second terminal and a constant potential after the third step." In this way, by connecting the second terminal and the first region via the fourth path when forming the plating layer in the third step and then disconnecting the fourth path, it is possible to preferably stabilize the potential when forming the plating layer while suppressing instability of operation. Therefore, even if there is no space in the fourth path to provide a second resistor (or high resistor) such as a polysilicon resistor, it is possible to preferably stabilize the potential when forming the plating layer while suppressing instability of operation.

[0026] The method for manufacturing a solid-state imaging device according to the present disclosure may be

[15] "the method for manufacturing a solid-state imaging device according to any one of

[12] to

[14] above, including a seventh step of cutting the second path between the first terminal and the first region after the third step." In this way, by keeping the first terminal and the first region connected by the second path when forming the plating layer in the third step, and then cutting the second path, it is possible to preferably stabilize the potential when forming the plating layer while suppressing instability in operation.

[0027] According to the present disclosure, it is possible to provide a solid-state imaging device capable of suppressing defective formation of a connection portion, and a method for manufacturing a solid-state imaging device.

[0028] 11 is a perspective view of a solid-state imaging element according to the present embodiment; FIG. 12 is a bottom view of the solid-state imaging element shown in FIG. 1; FIG. 13 is a schematic cross-sectional view showing the mounting state of the solid-state imaging element shown in FIGS. 1 and 2; FIG. 14 is a diagram showing an imaging region and a horizontal shift register shown in FIGS. 1 and 2; FIG. 15 is a circuit diagram including a readout circuit shown in FIG. 4; FIG. 16 is a cross-sectional view of a semiconductor substrate corresponding to a portion AR of the circuit diagram shown in FIG. 5; FIG. 17 is a schematic diagram showing the connection relationship between each terminal and ground; FIG. 18 is a flowchart showing a method for manufacturing a solid-state imaging element according to the present embodiment; FIG. 19 is a flowchart showing a method for manufacturing a solid-state imaging element according to a modified example; FIG. 19 is a schematic circuit diagram showing each step shown in FIG. 9; FIG. 11 is a circuit diagram according to a modified example; and FIG. 12 is a cross-sectional view of a semiconductor substrate corresponding to a portion AR of FIG.

[0029] Hereinafter, a solid-state imaging device according to an embodiment will be described with reference to the drawings. In the description of each drawing, the same or overlapping elements are denoted by the same reference numerals, and overlapping descriptions may be omitted. In addition, each drawing may illustrate an orthogonal coordinate system consisting of an X-axis, a Y-axis, and a Z-axis.

[0030] Fig. 1 is a perspective view of a solid-state imaging element according to this embodiment. Fig. 2 is a bottom view (a plan view seen from the opposite side to the direction of light incidence) of the solid-state imaging element shown in Fig. 1. The solid-state imaging element 100 shown in Figs. 1 and 2 includes a semiconductor substrate 5. The semiconductor substrate 5 includes a front surface 5s and a back surface 5r opposite to the front surface 5s.

[0031] As an example, the solid-state imaging device 100 is a BT-CCD (charge-coupled device) in which the back surface 5r side of the semiconductor substrate 5 is thinned by etching with a KOH solution or the like. In the solid-state imaging device 100, a recess TD and a relatively thick frame portion TT that surrounds the recess TD are formed by etching on the back surface 5r of the semiconductor substrate 5. Note that the entire region of the semiconductor substrate 5 may be thinned by removing the frame portion TT by etching.

[0032] An imaging region 10, which is a photosensitive region, is formed in a recess TD of the semiconductor substrate 5. A light image L from an object is incident on the imaging region 10 from the negative direction of the Z axis. A bottom surface 101 of the recess TD of the semiconductor substrate 5 serves as a light incident surface. As will be described later, imaging CCDs consisting of multiple vertical shift registers are formed as pixels in the imaging region 10. Charges corresponding to the light image L are generated in the imaging region 10 and transferred along the negative direction of the Y axis. A horizontal shift register 20 is provided at the end of the charge transfer direction of the imaging region 10. Charges transferred vertically to the horizontal shift register 20 are sequentially transferred in the positive direction of the X axis by the horizontal shift register 20. The charges transferred by the horizontal shift register 20 are read out by a readout circuit 30 provided at the end of the horizontal shift register 20.

[0033] Known charge transfer methods for CCDs include frame transfer, interline transfer, full frame transfer, etc. Many such CCD structures are known, and although there is no particular limitation, the solid-state imaging device 100 uses a full frame transfer CCD as an example.

[0034] A plurality of terminals (electrode pads) are provided at positions corresponding to the frame portion TT on the surface 5s of the semiconductor substrate 5. The plurality of terminals include terminals P1V and P2V for applying two-phase transfer voltages to the charge transfer electrodes in the vertical shift register, terminals P1H and P2H for applying two-phase transfer voltages to the charge transfer electrodes in the horizontal shift register 20, a terminal SS for connecting the semiconductor substrate 5 to ground (constant potential), terminals SG, OG, RG, OD, and RD for reading out charges transferred in the horizontal direction, and a terminal OS for extracting output.

[0035] The plurality of terminals provided on the surface 5s of the semiconductor substrate 5 include a terminal TG for functioning as a charge transfer gate to the horizontal shift register 20, terminals ISV and ISH for inputting test signals, and terminals 1G1V, 1G2V, 1G1H and 1G2H for functioning as the charge transfer gates for these test signals. The plurality of terminals further includes terminals SD and OFD.

[0036] As shown in FIG. 3 , the solid-state imaging device 100 is mounted in a package T1 such that the surface 5s of the semiconductor substrate 5 faces the package T1. At this time, each of the plurality of terminals described above is electrically connected to the package T1 via solder bumps B, and is also connected to an external sensor driving circuit (external load resistors and power supplies) via pins of a socket T2 attached to the package T1. In other words, each of the plurality of terminals described above is connected to a plurality of different external terminals. Note that in FIG. 3 , the plurality of terminals described above are illustrated as bonding terminals 40 including a first terminal 41 and a second terminal 42, and a gate terminal 45. Details of the bonding terminal 40 and the gate terminal 45 will be described later. As shown in FIG. 3 , the bonding terminal 40 and the gate terminal 45 are connected to the external terminals by bump bonding via the solder bumps B. However, the bonding terminal 40 and the gate terminal 45 may also be connected to the external terminals by wire bonding.

[0037] Fig. 4 is a diagram showing the imaging area and horizontal shift register shown in Fig. 1 and Fig. 2. Note that Fig. 4 is a schematic diagram in which the shape of each transfer electrode extending in the X-axis direction is rectangular and is depicted as if there were gaps between them, but in reality, they overlap partly or entirely, and their shapes are set to have openings for light transmission, as will be described later.

[0038] As shown in FIG. 4, in the imaging area 10, a plurality of vertical shift registers n １ ~n Ｎ (N is an integer of 2 or more), that is, vertical charge transfer CCDs are aligned. The actual imaging area is the central area of ​​the imaging area 10, and the peripheral pixels may be shielded from light as necessary. The vertical pixels are aligned along the Y axis, and the charge transfer electrodes m １ ~m Ｍ (M is an integer of 2 or more) each extends along the X axis. １ ~m Ｍ A two-phase transfer voltage is applied from terminals P1V and P2V to the charge transfer electrode m １ ~m Ｍ The charge stored in the semiconductor region directly below is transferred in the vertical direction (negative direction of the Y axis).

[0039] In addition, the vertical shift register n １ ~n Ｎ Between the vertical CCD channels (semiconductor charge transfer regions) that make up the CCD array, isolation regions of the opposite conductivity type to the charges flowing through these CCD channels are formed, and the isolation regions prevent the charges from coming from different pixel columns from mixing with each other.

[0040] At the final position of the vertical charge transfer, a transfer gate electrode m Ｔ is provided, and the transfer gate electrode m Ｔ The horizontal shift register 20 has horizontal charge transfer CCDs aligned along the X axis, which transfer charges in the horizontal direction (positive direction of the X axis). １ ~h Ｋ (K is an integer of 2 or more) are provided, and these charge transfer electrodes are arranged along the X-axis direction.

[0041] Charge transfer electrode h １ ~h Ｋ A two-phase transfer voltage is applied from terminals P1H and P2H to the charge transfer electrode h １ ~h Ｋ The charge stored in the semiconductor region directly below the pixel is transferred in the horizontal direction (X-axis direction). A readout circuit 30 is provided at the final position of the charge transfer on the X-axis.

[0042] FIG. 5 is a circuit diagram including the readout circuit shown in FIG. 4 and a circuit different from the readout circuit. As shown in FIG. 5, the readout circuit 30 includes terminals OS and OD. The terminal OS is an output source terminal for outputting a signal, and the terminal OD is an output drain terminal, which is a terminal of the output circuit section. The terminal OS is connected to the source terminal of the transistor L6. More specifically, the source terminal of the transistor L6 is connected to an external load resistor Zr connected to ground (constant potential), and the terminal OS is connected between the source terminal and the external load resistor Zr. The external load resistor Zr is implemented in the sensor driving circuit described above. The transistors L1 to L6 have, for example, a MOS-FET structure.

[0043] Terminal OD is connected to the drain terminals of transistors L2, L4, and L6. The source terminal of transistor L2 is connected to ground (constant potential) via transistor L3, and the source terminal of transistor L4 is connected to ground (constant potential) via transistor L5. The connection relationship of terminal OD will be described in more detail.

[0044] FIG. 6 is a cross-sectional view of a semiconductor substrate corresponding to a portion AR in the circuit diagram shown in FIG. 5. FIG. 7 is a schematic diagram showing the connection relationship between each terminal and ground. (a) of FIG. 7 is a schematic cross-sectional view, and (b) and (c) of FIG. 7 are schematic circuit diagrams. As shown in FIGS. 6 and 7, the semiconductor substrate 5 has a first region 51 of a first conductivity type (e.g., P-type) and a plurality of second regions 52 (one second region 52 is shown in FIG. 6 and two second regions 52 are shown in FIG. 7) of a second conductivity type (e.g., N-type) different from the first conductivity type. In a direction intersecting the front surface 5s and rear surface 5r of the semiconductor substrate 5, the thickness of the first region 51 is greater than the thickness of the second region 52. In addition, the semiconductor substrate 5 has a first region 51 of a second conductivity type (e.g., N-type) provided in the second region 52. ＋ and third regions 54, 55, and 56 having a first conductivity type (e.g., P ＋ The fourth region 57 has an impurity concentration higher than that of the first region 51.

[0045] A gate electrode 61 is provided between the third region 54 and the third region 55, and another gate electrode 62 is provided between the third region 55 and the third region 56. As a result, a transistor L2 (MOS-FET) is formed in the region directly below the third region 54, the third region 55, and the gate electrode 61, and a transistor L3 is formed in the region directly below the third region 55, the third region 56, and the gate electrode 62. Furthermore, a metal wiring (e.g., Al wiring) 71 is connected to the third region 55, and the third region 56 is connected to the fourth region 57 via a metal wiring (e.g., Al wiring) 72. A terminal OD is connected to the third region 54.

[0046] 5 to 7, the terminal OD is connected to the first region 51 (i.e., the constant potential of the first region 51, here, ground (the same applies hereinafter)) via at least the transistor L2, the transistor L3, the metal wiring 72, and the fourth region 57. The terminal OD is also connected to the first region 51 via a PN junction 53 formed between the first region 51 and the second region 52.

[0047] That is, the terminal OD is connected to a second region 52 (third region 54) that is a part of the plurality of second regions 52 among the plurality of junction terminals 40, and is thereby connected to the first region 51 by a first path Q1 via a PN junction 53 between the second region 52 and the first region 51, and is also connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in the transistors L2 and L3 that constitute the readout circuit 30, thereby forming the first terminal 41 that constitutes the readout circuit 30. The first resistance Z1 is a resistance generated between the source and drain of the transistor. The terminal OD is connected to the first region 51 by the second path Q2 via a fourth region 57 that has a higher impurity concentration.

[0048] Similarly, the terminal OS is connected to the terminal OD via the transistor L6, and therefore, like the terminal OD, is connected to a part of the second regions 52 (the third region 54) among the plurality of second regions 52, and is thereby connected to the first region 51 by a first path Q1 via a PN junction 53 between the second region 52 and the first region 51, and is also connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in the transistors L2 and L3 constituting the readout circuit 30, thereby forming a first terminal 41 constituting the readout circuit 30. Note that, between a part of the fourth region 57 to which the metal wiring 72 is connected and the second region 52 adjacent to the part, a LOCOS (Local Oxidation of Silicon) region 58 is formed on the remaining region of the fourth region 57.

[0049] 5, the terminal RD is connected to the drain terminal of the transistor L1 and is connected to the floating diffusion region FD via the transistor L1. The terminal RD is a reset drain terminal for resetting the floating diffusion region FD. The terminal RG is connected to the gate terminal of the transistor L1.

[0050] 5 to 7, terminal RD, like terminals OS and OD, is connected to second region 52 and is therefore connected to first region 51 by third path Q3 via PN junction 53 between second region 52 and first region 51, but does not have a path to ground via first resistor Z1 generated in a transistor constituting readout circuit 30. However, terminal RD is connected to first region 51 via second resistor Z2 different from first resistor Z1. Second resistor Z2 is not particularly limited, but may be formed of a polysilicon resistor, for example.

[0051] That is, the terminal RD is connected to another part of the second regions 52 among the plurality of second regions 52, and is thereby connected to the first region 51 by a third path Q3 via a PN junction 53 between the second region 52 and the first region 51, and is also connected to the first region 51 by a fourth path Q4 via a second resistor Z2 different from the first resistor Z1, thereby forming a second terminal 42 that constitutes a part different from the readout circuit 30. As an example, the resistance value of the first resistor Z1 is 0.1 kΩ to 50 kΩ, and the resistance value of the second resistor Z2 is 1 kΩ to 100 kΩ. Note that, when the readout circuit 30 is not driven, the resistance value of the first resistor Z1 is 0.1 kΩ to 50 kΩ as described above, but is conductive when the readout circuit 30 is driven. When the readout circuit 30 is driven, a positive voltage is applied to the terminals RD and OD (when the readout circuit 30 is not driven, the solid-state imaging device 100 itself is turned off, so no voltage is applied). Furthermore, the wiring portion of the third path Q3 from the terminal RD to the PN junction 53 may be made of metal wiring only.

[0052] The terminal SD is a second conductivity type (e.g., N ＋ The terminals are connected to the pixel region (see FIG. 2) of the image pickup area 10 and are scupper drain terminals for discharging signal charges that become a noise source from the periphery of the image pickup area 10. The terminal OFD is an overflow drain terminal for discharging charges that overflow from the pixels (see FIG. 2). The terminal ISV is a vertical input source terminal for evaluating vertical charge transfer, and the terminal ISH is a horizontal input source terminal for evaluating horizontal charge transfer and amplifier characteristics.

[0053] Like terminal RD, these terminals SD, OFD, ISV, and ISH are connected to another part of the second regions 52 among the plurality of second regions 52, and are thereby connected to the first region 51 by a third path Q3 via a PN junction 53 between the second region 52 and the first region 51, and are also connected to the first region 51 by another fourth path Q4 via a second resistor Z2 different from the first resistor Z1, and are second terminals 42 that constitute a part different from the readout circuit 30.

[0054] As described above, the joining terminal 40 includes a plurality of second terminals 42 (terminals RD, SD, OFD, ISV, and ISH). Each of the plurality of second terminals 42 may be connected to the first region 51 by a different fourth path Q4 (i.e., the second terminals 42 may not share the fourth path Q4). Furthermore, the second resistors Z2 interposed in the different fourth paths Q4 may be set to have different resistance values.

[0055] Furthermore, terminals SG, OG, and RG are each gate terminals 45 that are provided on the semiconductor substrate 5 via an insulating film made of, for example, silicon oxide, and are thereby electrically insulated from the second region 52. Terminal SG is a summing gate terminal that is configured in the final stage of the horizontal shift register 20 and contributes to horizontal charge transfer driving. Terminal OG is an output gate terminal that is located between the horizontal shift register 20 and the floating diffusion region FD and contributes to charge transfer from the horizontal shift register 20 to the floating diffusion region FD. Terminal RG is a reset gate terminal that contributes to resetting the charge in the floating diffusion region FD.

[0056] As described above, the solid-state imaging device 100 includes a plurality of bonding terminals 40 including first terminals 41 (terminals OD and OS) and second terminals 42 (terminals RD, SD, OFD, ISV, and ISH), and gate terminals 45 (terminals SG, OG, and RG). The plurality of bonding terminals 40 and gate terminals 45 are bonded to solder bumps B via plating layers 46 (see FIG. 3 ) formed on their respective surfaces, and are connected to different external terminals. The plating layers 46 are formed, for example, by UBM (Under Bump Metal) processing, and are formed by forming an Au layer with a thickness of approximately 0.05 μm on an Ni layer with a thickness of approximately 5 μm.

[0057] Next, an example of a method for manufacturing the solid-state imaging device 100 will be described. Fig. 8 is a flowchart showing a method for manufacturing the solid-state imaging device according to this embodiment. As shown in Fig. 8, in this manufacturing method, first, a semiconductor substrate 5 is prepared, which has a first region 51 having a first conductivity type and a plurality of second regions 52 having a second conductivity type different from the first conductivity type (step S101: first step).

[0058] Next, by going through processes such as forming metal wiring (e.g., Al wiring) from the second region 52 of the semiconductor substrate 5 to the surface 5s of the semiconductor substrate 5, a plurality of bonding terminals 40 that are electrically connected to the second region 52 are formed on the surface 5s of the semiconductor substrate 5 (steps S102, S103: second step).

[0059] More specifically, by connecting to a part of the second regions 52 of the plurality of second regions 52 of the semiconductor substrate 5, the first terminal 41 is connected to the first region 51 by a first path Q1 via a PN junction 53 between the second region 52 and the first region 51, and is also connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in a transistor (e.g., transistors L2, L3) constituting the readout circuit 30, thereby forming the first terminal 41 constituting the readout circuit 30 as the junction terminal 40 (step S102: fourth step).

[0060] Meanwhile, a second terminal 42 that constitutes a part different from the readout circuit 30 is formed as a junction terminal 40 (step S103: fifth step). The second terminal 42 is connected to another part of the second regions 52 of the semiconductor substrate 5, thereby being connected to the first region 51 via a third path Q3 via a PN junction 53 between the second region 52 and the first region 51, and is also connected to a constant potential via a fourth path Q4 that does not pass through the first resistor Z1. Here, the fourth path Q4 that does not pass through the first resistor Z1 is a path that passes through a second resistor Z2, which is, for example, a polysilicon resistor. That is, in step S103, the second resistor Z2 is formed so as to be interposed in the fourth path Q4 between the second terminal 42 and the first region 51.

[0061] The order of steps S102 and S103 is not limited. At this time, a gate terminal 45 can be formed on the surface 5s of the semiconductor substrate 5 by a similar method. Furthermore, at this point, the external load resistor Zr shown in FIG. 5 is not connected.

[0062] Next, a plating layer 46 made of, for example, Ni / Al is formed on the surface of each of the bonding terminals 40 (for example, the Al surface of the metal wiring) by, for example, UBM processing (step S104: third step). Similarly, a plating layer 46 can also be formed on the surface of the gate terminal 45. In this way, the solid-state imaging device 100 is obtained.

[0063] As described above, the solid-state imaging device 100 according to this embodiment includes a plurality of junction terminals 40 connected to the second region 52 of the second conductivity type in the semiconductor substrate 5. The plurality of junction terminals 40 include a first terminal 41 that constitutes the readout circuit 30 and a second terminal 42 that does not constitute the readout circuit 30. The first terminal 41 that constitutes the readout circuit 30 is connected to the first region 51 of the semiconductor substrate 5 (i.e., the constant potential of the first region 51) by a first path Q1 via a PN junction 53 formed in the semiconductor substrate 5, and is further connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in a transistor (e.g., transistors L2 and L3) of the readout circuit 30.

[0064] Therefore, as described above, the potential of the first terminal 41 is stabilized when the plating layer 46 is formed. Furthermore, the second terminal 42, which does not constitute the readout circuit 30, is connected to the first region 51 by a third path Q3 via a PN junction 53 formed in the semiconductor substrate 5, and is also connected to the first region 51 by a fourth path Q4 via the second resistor Z2. Therefore, the potential of the second terminal 42 is stabilized when the plating layer 46 is formed. Therefore, in the solid-state imaging device 100, defective formation of the connection portion (solder bump B in this embodiment) of the joining terminal 40 is suppressed.

[0065] In the solid-state imaging device 100 according to this embodiment, the second resistor Z2 may be made of a polysilicon resistor. In this case, it becomes possible to easily form a connection to a constant potential via the second resistor Z2 having a suitable resistance value.

[0066] In the solid-state imaging device 100 according to this embodiment, the resistance value of the second resistor Z2 may be 1 kΩ or more and 100 kΩ or less. In this case, it is possible to preferably stabilize the potential at the first terminal 41 and the second terminal 42 when the plating layer 46 is formed, and it is also possible to suppress instability of operation due to a low resistance value between the second terminal 42 and the first region 51.

[0067] In the solid-state imaging device 100 according to this embodiment, the second terminal 42 may include at least one (in this embodiment, all) of a reset drain terminal (terminal RD), a scupper drain terminal (terminal SD), and an overflow drain terminal (terminal OFD). In this manner, various terminals may be used as the second terminal 42.

[0068] Furthermore, in the solid-state imaging device 100 according to this embodiment, the bonding terminals 40 are connected to the external terminals by bump bonding. Thus, when the bonding terminals 40 are connected to the external terminals by bump bonding, it is more effective to prevent defective connections than when the bonding terminals 40 are connected to the external terminals by wire bonding, for example. More specifically, while wire bonding may allow for re-stripping (re-forming the connection) at a different location within the same pad (plating layer 46) where Ni is not deposited, bump bonding does not allow for such re-stripping. Therefore, when the bonding terminals 40 are connected to the external terminals by bump bonding, it is more effective to prevent defective connections.

[0069] Furthermore, in the solid-state imaging device 100 according to this embodiment, the joining terminal 40 includes a plurality of second terminals 42. Therefore, in the joining terminal 40 including the plurality of second terminals 42, defective formation of the connection portion is suppressed.

[0070] Furthermore, in the solid-state imaging device 100 according to this embodiment, each of the second terminals 42 may be connected to the first region 51 by a mutually different fourth path Q4. In this way, the second terminals 42 do not necessarily share the fourth path Q4 to the first region 51.

[0071] In the solid-state imaging device 100 according to the present embodiment, the second resistors Z2 present in the different fourth paths Q4 may have different resistance values. In this case, it is possible to set an appropriate resistance value of the second resistor Z2 for the second terminals 42 having different allowable current values.

[0072] In the solid-state imaging device 100 according to this embodiment, the wiring portion of the third path Q3 from the second terminal 42 to the PN junction 53 may be made of metal wiring only. In this way, it is not necessary to interpose a resistive element in the wiring portion between the second terminal 42 and the PN junction 53.

[0073] Furthermore, in the solid-state imaging device 100 according to this embodiment, the thickness of the first region 51 is greater than the thickness of the second region 52. As a result, the potential of the first region 51 tends to be stabilized, and therefore, it is possible to reliably suppress defective formation of the connection portion.

[0074] Furthermore, in the solid-state imaging device 100 according to this embodiment, the semiconductor substrate 5 has the first conductivity type and further includes a third region (fourth region 57) having an impurity concentration higher than the impurity concentration of the first region 51, and the first terminal 41 is connected to the first region 51 via the fourth region 57 in the second path Q2. This makes it possible to connect the first terminal 41 and the semiconductor region with lower resistance.

[0075] Here, the manufacturing method of the solid-state imaging device 100 according to this embodiment includes steps S102 and S103 of forming a plurality of junction terminals 40 connected to a second region 52 of a second conductivity type in the semiconductor substrate 5. More specifically, the manufacturing method includes step S102 of forming a first terminal 41 constituting the readout circuit 30 and step S103 of forming a second terminal 42 not constituting the readout circuit 30. In step S102, the first terminal 41 constituting the readout circuit 30 is formed so as to be connected to the first region 51 by a first path Q1 via a PN junction 53 formed in the semiconductor substrate 5, and further connected to the first region 51 by a second path Q2 via a first resistance Z1 generated in a transistor (e.g., transistors L2 and L3) of the readout circuit 30. Therefore, as described above, the potential of the first terminal 41 is stabilized when the plating layer 46 is formed in step S104.

[0076] Furthermore, in step S103, the second terminal 42, which does not constitute the readout circuit 30, is connected to the first region 51 by a third path Q3 via a PN junction 53 formed in the semiconductor substrate 5, and is also formed to be connected to the first region 51 by a fourth path Q4. Thus, the potential of the second terminal 42 is stabilized when the plating layer 46 is formed in step S104. Therefore, in the manufacturing method for the solid-state imaging device 100, defective formation of the connection portion (solder bump B in this embodiment) of the joining terminal 40 is suppressed.

[0077] Furthermore, in the manufacturing method of the solid-state imaging device 100 according to this embodiment, in step S103, the second resistor Z2 is formed so as to be interposed in the fourth path Q4 between the second terminal 42 and the first region 51. In this way, by interposing an appropriate second resistor Z2 between the second terminal 42 and the first region 51, it is possible to preferably stabilize the potential during the formation of the plating layer 46 while suppressing instability in operation.

[0078] The above embodiment has been described as an embodiment according to one aspect of the present invention. Therefore, the present invention is not limited to the above embodiment and can be modified as desired. Next, modified examples will be described.

[0079] Fig. 9 is a flowchart showing a method for manufacturing a solid-state imaging device according to a modified example. Fig. 10 is a schematic circuit diagram showing the steps shown in Fig. 9. As shown in Fig. 9, in the method according to this modified example, steps S101 and S102 are performed, similarly to the method according to the above embodiment. On the other hand, in the method according to this modified example, in step S103, the second terminal 42 and the first region 51 are directly connected by a fourth path Q4 made of metal wiring W1, which does not pass through the first resistor Z1 (see (a) of Fig. 10).

[0080] Then, similarly to the method according to the above embodiment, after forming the plating layer 46 in step S104, the fourth path Q4 is cut between the second terminal 42 and the first region 51 (step S105: sixth step). In step S105, after forming the plating layer 46, the metal wiring W1 is cut by, for example, laser irradiation, etc., and an insulating portion W0 is formed in the fourth path Q4, thereby cutting the fourth path Q4.

[0081] In this way, when the plating layer 46 is formed in step S104, the second terminal 42 and the constant potential are connected by the metal wiring W1 (fourth path Q4), and then the fourth path Q4 is disconnected, thereby making it possible to preferably stabilize the potential when the plating layer 46 is formed while suppressing instability in operation.

[0082] Step S105 can also be applied to the method according to the above embodiment. That is, in step S103, while the second terminal 42 is connected to a constant potential via the fourth path Q4 including the second resistor Z2, if the second resistor Z2, such as a polysilicon resistor, is not required for driving the sensor, step S105 may be applied to disconnect the fourth path Q4.

[0083] 11 is a circuit diagram according to a modified example, and Fig. 12 is a cross-sectional view of a semiconductor substrate corresponding to a portion AR of Fig. 11. As shown in Fig. 11 and Fig. 12, terminal OD (and terminal OS) are connected to terminal Vret via transistors L2 and L3 (and transistors L4 and L5), and there are cases where connection portion 72a with fourth region 57 of metal wiring 72 is not provided. Terminal Vret is a terminal for stabilizing the potential of a constant current source configured in the output circuit section.

[0084] In this case, the terminal OD is connected to the second region 52 and is thereby connected to the first region 51 by a first path Q1 via a PN junction 53 between the second region 52 and the first region 51. However, similar to the terminals RD, SD, and OFD, the terminal OD does not have a path to the first region 51 via a first resistance Z1 generated in a transistor (e.g., transistors L2 and L3) constituting the readout circuit 30. Therefore, similar to the terminals RD, SD, and OFD, it is conceivable to form a path separate from the first path Q1 connecting to the first region 51 via, for example, a polysilicon resistor or metal wiring. In this case, after forming the plating layer 46 on the terminal OD, step S105 can be applied to disconnect the separate path.

[0085] That is, in step S102, when forming the terminal OD, a connection portion 72a of the metal wiring 72 is provided so that the terminal OD is further connected to the first region 51 via a second path Q2 via a first resistance Z1 generated in the transistor of the readout circuit 30. The connection portion 72a may include, for example, a metal wiring or a polysilicon resistor (resistor Zp in the illustrated example). Then, after forming the plating layer 46 in step S104, the second path Q2 is cut between the terminal OD and the first region 51, for example, by cutting the connection portion 72a. That is, the manufacturing method for the solid-state imaging device 100 may include, after step S104, a seventh step of cutting the second path Q2 between the first terminal 41 and the first region 51. This makes it possible to preferably stabilize the potential during the formation of the plating layer 46 while suppressing operational instability.

[0086] Although polysilicon resistors have been exemplified as the second resistor Z2 and resistor Zp above, the second resistor Z2 and resistor Zp are not limited to this and may be diode-connected resistors such as MOS-FETs.

[0087] 5...semiconductor substrate, 40...junction terminal, 41...first terminal, 42...second terminal, 45...gate terminal, 46...plating layer, 51...first region, 52...second region, 53...PN junction, 100...solid-state imaging element, Z1...first resistor, Z2...second resistor, Q1...first path, Q2...second path, Q3...third path, Q4...fourth path, RD...terminal (reset drain terminal), SD...terminal (scupper drain terminal), OFD...terminal (overflow drain terminal).

Claims

1. A solid-state imaging device comprising: a semiconductor substrate having a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type; a plurality of junction terminals electrically connected to the second region and each connected to a different external terminal; and a gate terminal electrically insulated from the second region, wherein the plurality of junction terminals are: a first terminal constituting a readout circuit by being connected to a portion of the second regions of the plurality of second regions, and connected to the first region by a first path via a PN junction between the second region and the first region, and connected to the first region by a second path via a first resistor generated in a transistor constituting a readout circuit; and a second terminal constituting a portion different from the readout circuit by being connected to another portion of the plurality of second regions of the plurality of second regions, and connected to the first region by a third path via a PN junction between the second region and the first region, and connected to the first region by another fourth path via a second resistor different from the first resistor.

2. The solid-state imaging device according to claim 1, wherein the second resistor is made of a polysilicon resistor.

3. The solid-state imaging device according to claim 1 or 2, wherein the resistance value of the second resistor is 1 kΩ or more and 100 kΩ or less.

4. The solid-state imaging device according to any one of claims 1 to 3, wherein the second terminal includes at least one of a reset drain terminal, a scupper drain terminal, and an overflow drain terminal.

5. The solid-state imaging device according to any one of claims 1 to 4, wherein the joining terminals are connected to the external terminals by bump bonding.

6. A solid-state imaging device according to any one of claims 1 to 5, wherein the joining terminal includes a plurality of the second terminals.

7. The solid-state imaging device according to claim 6, wherein each of the plurality of second terminals is connected to the first region by a fourth path different from each other.

8. The solid-state imaging device according to claim 7, wherein the second resistors present in the respective fourth paths that are different from each other have resistance values ​​different from each other.

9. The solid-state imaging device according to any one of claims 1 to 8, wherein a wiring portion of said third path from said second terminal to a PN junction is made of only metal wiring.

10. A solid-state imaging device according to any one of claims 1 to 9, wherein the thickness of the first region is greater than the thickness of the second region.

11. A solid-state imaging element as described in any one of claims 1 to 10, wherein the semiconductor substrate has the first conductivity type and further has a third region having an impurity concentration higher than an impurity concentration of the first region, and the first terminal is connected to the first region via the third region in the second path.

12. A semiconductor substrate having a first region having a first conductivity type and a plurality of second regions having a second conductivity type different from the first conductivity type, a second step of forming a plurality of junction terminals electrically connected to the second region after the first step, and a third step of forming a plating layer on surfaces of the plurality of junction terminals after the second step, the second step comprising: a fourth step of forming, as the junction terminal, a first terminal constituting a readout circuit, the first terminal being connected to a portion of the second regions among the plurality of second regions, the first terminal being connected to the first region by a first path via a PN junction between the second region and the first region, and the first region being connected to the second region by a second path via a first resistance generated in a transistor constituting a readout circuit; and a fifth step of forming, as the junction terminal, a second terminal being connected to another portion of the plurality of second regions, the first terminal being connected to the first region by a third path via a PN junction between the second region and the first region, the first region being connected to the first region by a fourth path not via the first resistance, the second terminal constituting a portion different from the readout circuit. A method for manufacturing a solid-state imaging device comprising the steps of:

13. The method for manufacturing a solid-state imaging device according to claim 12, wherein in the fifth step, a second resistor is formed between the second terminal and the first region so as to be interposed in the fourth path.

14. A method for manufacturing a solid-state imaging device according to claim 12 or 13, further comprising, after the third step, a sixth step of cutting the fourth path between the second terminal and the first region.

15. A method for manufacturing a solid-state imaging device according to any one of claims 12 to 14, further comprising a seventh step, after the third step, of cutting the second path between the first terminal and the first region.

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