Photodetection device and electronic device

Abstract

In the present invention, the performance of a photodetection device is improved. This detection device comprises: a semiconductor layer having a first surface part and a second surface part which are positioned on mutually opposite sides in one direction; an insulator provided on the first surface part side of the semiconductor layer; a photoelectric conversion part for photoelectrically converting, into signal charge, light incident from the second surface part side of the semiconductor layer; a charge-holding part provided on the first surface part side of the semiconductor layer; and a transfer transistor for transferring, to the charge-holding part, the signal charge which has been photoelectrically converted by the photoelectric conversion part. The transfer transistor has a gate electrode which is adjacent to each of the semiconductor layer and the insulator and which extends in the one direction.

Description

Photodetector and electronic equipment

[0001] The present technology (technology according to the present disclosure) relates to a photodetector and an electronic device, and in particular to a technology that is effective when applied to a photodetector having a transfer transistor and an electronic device including the same.

[0002] Photodetection devices such as solid-state imaging devices and distance measuring devices include a transfer transistor for each pixel that transfers signal charges photoelectrically converted in a photoelectric conversion unit to a charge storage unit. Patent Document 1 discloses a transfer transistor with a vertical structure in which a part of a gate electrode (transfer gate unit) is provided in a recessed portion of a semiconductor substrate (semiconductor layer) with a gate insulating film interposed therebetween.

[0003] WO2019 / 082546

[0004] Incidentally, a transfer transistor with a vertical structure is considered to be more advantageous in transferring signal charges than a transfer transistor with a horizontal structure (planar structure).

[0005] However, in conventional vertical-structure transfer transistors, the entire periphery of the transfer gate portion of the gate electrode is adjacent to the semiconductor substrate with the gate insulating film interposed between them. This results in a capacitance component (parasitic capacitance) between the semiconductor substrate and the entire periphery of the transfer gate portion of the gate electrode. If this capacitance component is large, the drive pulse applied to the gate electrode of the transfer transistor becomes dull, reducing the transfer speed (pixel drive speed) at which signal charges are transferred from the photoelectric conversion portion to the charge storage portion. This reduction in transfer speed then affects the performance of the photodetector, making the capacitance component no longer negligible.

[0006] An object of the present technology is to provide a technology that can improve the performance of a photodetector.

[0007] (1) A photodetector according to one aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction; an insulator provided on the first surface portion side of the semiconductor layer; a photoelectric conversion unit that photoelectrically converts light incident from the second surface portion side of the semiconductor layer into signal charges; a charge holding unit provided on the first surface portion side of the semiconductor layer; and a transfer transistor that transfers the signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit. The transfer transistor has gate electrodes adjacent to the semiconductor layer and the insulator, respectively, and extending in the one direction.

[0008] (2) A photodetector according to one aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region extending in the one direction. The photoelectric conversion region includes: an internal isolation barrier extending in the one direction; and a first photoelectric conversion cell and a second photoelectric conversion cell arranged adjacent to each other with the internal isolation barrier interposed therebetween in a direction intersecting the one direction, each of the first and second photoelectric conversion cells including a photoelectric conversion unit and a charge retention unit that retains signal charge photoelectrically converted in the photoelectric conversion unit. The internal isolation barrier protrudes from one of the two isolation regions located opposite each other across the photoelectric conversion region in a planar view toward the other isolation region, and the charge retention units of the first and second photoelectric conversion cells are adjacent to each other on the side of one of the isolation regions via the internal isolation barrier.

[0009] (3) A photodetector according to an aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction, an isolation region extending from the first surface portion of the semiconductor layer toward the second surface portion, and a transfer transistor provided on the first surface portion side of the semiconductor layer and configured to transfer signal charges photoelectrically converted by a photoelectric conversion unit to a charge storage unit, wherein the transfer transistor has a gate electrode provided outside the first surface portion of the semiconductor layer across the semiconductor layer and the isolation region in a plan view.

[0010] (4) An electronic device according to another aspect of the present technology includes the above-mentioned photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that performs signal processing on a signal output from the photodetector.

[0011] 5A is an enlarged plan view of a portion of FIG. 4A; FIG. 5B is an enlarged plan view of a portion of FIG. 5A; and FIG. 5C is an enlarged plan view of a portion of FIG. 5A; and FIG. 5D ... 8A . FIG. 8B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a8-a8 cutting line of FIG. 8A . FIG. 9A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a9-a9 cutting line of FIG. 9A . FIG. 10A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a10-a10 cutting line of FIG. 10A . FIG. 10B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a11-a11 cutting line of FIG. 11A . FIG. 11C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a11-a11 cutting line of FIG. 11A . FIG. 12A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a12-a12 cutting line of FIG. 12A . FIG. 12D is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a12-a12 cutting line of FIG. 12A . 10A and 10B are diagrams illustrating modified examples 1-7 and 1-8 according to the first embodiment of the present technology, and are plan views schematically illustrating one pixel.17A . FIG. 17B is a diagram illustrating a modified example 1-9 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 17C is a diagram illustrating a modified example 1-10 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 17A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a17-a17 cutting line of FIG. 17A. FIG. 17B is a diagram illustrating a modified example 1-11 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 17C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a17-a17 cutting line of FIG. 17A. FIG. 17B is a diagram illustrating a modified example 1-12 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 17C is a diagram illustrating a modified example 1-13 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 17C is an equivalent circuit diagram schematically showing a configuration example of a pixel and a pixel circuit in a solid-state imaging device according to a second embodiment of the present technology. FIG. 17D is a plan view schematically showing a configuration example of one pixel in a solid-state imaging device according to the second embodiment of the present technology. 20B. FIG. 21A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a20-a20 cutting line in FIG. 20B. FIG. 21B is a diagram showing a modified example 2-1 according to the second embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel. FIG. 21A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a21-a21 cutting line in FIG. 21A. FIG. 21B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b21-b21 cutting line in FIG. 21A. FIG. 21B is a diagram showing a modified example 2-2 according to the second embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel. FIG. 22A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a22-a22 cutting line in FIG. 22A. FIG. 23A is a diagram showing a modified example 2-3 according to the second embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel. FIG. 23A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a23-a23 cutting line in FIG. 23A. FIG. 23A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b23-b23 cutting line in FIG. 23A. 24A . FIG. 24B is a diagram illustrating a modified example 2-4 according to the second embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel. FIG. 24C is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a24-a24 cutting line in FIG. 24A. FIG. 24D is a diagram illustrating a modified example 2-5 according to the second embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 24E is a diagram illustrating a modified example 2-6 according to the second embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel.26A . FIG. 27A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a26-a26 cutting line of FIG. 26A . FIG. 27B is a diagram showing a modified example 2-7 according to the second embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel. FIG. 27B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a27-a27 cutting line of FIG. 27A . FIG. 27C is a diagram showing a modified example 2-8 according to the second embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 27D is a diagram showing a modified example 2-9 according to the second embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 27D is a diagram showing a modified example 2-10 according to the second embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 27C is a diagram showing a modified example 2-11 according to the second embodiment of the present technology, and is a plan view schematically showing one pixel. FIG. 27D is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a32-a32 cutting line of FIG. 33A 。 FIG. 33B is a diagram illustrating a modified example 3-1 according to the third embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel. FIG. 33A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a33-a33 cutting line of FIG. 33A. FIG. 33B is a diagram illustrating a modified example 3-2 according to the third embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel. FIG. 34A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a34-a34 cutting line of FIG. 34A. FIG. 34B is a diagram illustrating a modified example 3-3 according to the third embodiment of the present technology, and is a plan view schematically showing a configuration example of one pixel. FIG. 35A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a35-a35 cutting line of FIG. 35A. FIG. 36A is a longitudinal cross-sectional view schematically showing a configuration example of one pixel in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 36B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure along the a36-a36 cutting line of FIG. 36A. FIG. 36C is an exploded view schematically showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 36D is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit according to the fifth embodiment of the present technology. Fig. 10 is a diagram showing a schematic configuration of an electronic device according to a sixth embodiment of the present technology. Fig. 11 is a block diagram showing an example of a schematic configuration of a vehicle control system according to a seventh embodiment of the present technology. Fig. 12 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit. Fig. 13 is a diagram showing an example of a schematic configuration of an endoscopic surgery system according to an eighth embodiment of the present technology.FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0012] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0013] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0014] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0015] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0016] In the following embodiments, among the three directions orthogonal to each other in space, a first direction and a second direction orthogonal to each other in the same plane are referred to as the X direction and the Y direction, respectively, and a third direction orthogonal to each of the first direction and the second direction is referred to as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 21 (described later) will be described as the Z direction. In the following embodiments, the Z direction will be described as "one direction" of the present technology.

[0017] In addition, in the following embodiments, the thickness of the semiconductor layer 21 is the distance between the first surface portion S1 and the second surface portion S2, which are located on opposite sides in the Z direction, and the thickness direction of the semiconductor layer 21 is the direction representing the thickness of the semiconductor layer 21.

[0018] In the following embodiments, a plan view refers to a case where the semiconductor layer 21 is viewed from the Z direction (one direction). A cross-sectional view refers to a case where a cross section along the Z direction (one direction) is viewed from a direction perpendicular to the Z direction.

[0019] First Embodiment In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described.

[0020] <Overall Configuration of Solid-State Imaging Device> First, the overall configuration of the solid-state imaging device 1A will be described. As shown in Fig. 1 , the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in Fig. 39 , this solid-state imaging device 1A (301) captures image light (incident light 306) from a subject via an optical lens 302, converts the amount of incident light 306 formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0021] As shown in FIG. 1, a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including an X direction and a Y direction which are orthogonal to each other, a rectangular pixel array section 2A provided in the center, and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A.

[0022] Here, the semiconductor chips 2 are formed in the manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 (described later) into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. Therefore, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0023] The pixel array unit 2A shown in Fig. 1 is, for example, a light receiving surface that receives light collected by an optical lens (optical system) 302 shown in Fig. 39. The pixel array unit 2A has a plurality of pixels 3 (sensor pixels) arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0024] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal that electrically connects the semiconductor chip 2 to an external device.

[0025] <Logic Circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0026] The vertical drive circuit 4 shown in Fig. 2 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section 25 (see Fig. 3) of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via the vertical signal line 11.

[0027] 2 is arranged for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0028] 2 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0029] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 12, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0030] 2 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0031] 3, each of the plurality of pixels 3 includes a photoelectric conversion unit 25, a floating diffusion region FD serving as a charge storage unit that stores (accumulates) signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Each of the plurality of pixels 3 further includes a photoelectric conversion region (photoelectric conversion cell) 22 of a semiconductor layer 21 shown in FIG. 5A. The photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TR are each provided in the photoelectric conversion region 22, as shown in FIGS. 4A and 5A.

[0032] 3 is configured by, for example, a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge.

[0033] The photoelectric conversion unit 25 has a cathode side electrically connected to the source region of the transfer transistor TR, and an anode side electrically connected to a reference potential line (for example, ground).

[0034] 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line of the pixel drive lines 10 shown in FIG.

[0035] (Floating Diffusion Region) The floating diffusion region FD shown in FIG. 3 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0036] <Pixel Circuit> The solid-state imaging device 1A (semiconductor chip 2) according to the first embodiment includes a pixel circuit (readout circuit) 15 shown in Fig. 3. As shown in Fig. 3, the pixel circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 22.

[0037] In the first embodiment, as an example, a circuit configuration is shown in which one pixel circuit 15 is assigned to one pixel 3, but the present invention is not limited to this first embodiment. For example, a circuit configuration in which one pixel circuit 15 is shared by multiple pixels 3 may be used. Specifically, a circuit configuration in which one pixel circuit 15 is shared by one pixel group (photoelectric conversion group) in which four pixels 3 are arranged in a 2×2 array, two in each of the X and Y directions, is used. Furthermore, a circuit configuration in which one pixel circuit 15 is shared by one pixel group (photoelectric conversion group) in which two pixels 3 are used as one unit may be used. Furthermore, a circuit configuration in which one pixel circuit 15 is shared by one pixel group (photoelectric conversion group) in which four or more pixels 3 are used as one unit may be used.

[0038] 3 reads out the signal charges held in the floating diffusion region FD and outputs a pixel signal based on the read-out signal charges. In other words, the pixel circuit 15 converts the signal charges photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charges and outputs the pixel signal.

[0039] The pixel circuit 15 includes a plurality of pixel transistors Q. The pixel circuit 15 of the first embodiment includes, but is not limited to, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as the pixel transistors Q. These pixel transistors Q (AMP, SEL, RST) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of, for example, silicon oxide (SiO ２ These transistors are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４ Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0040] Of the pixel transistors Q (AMP, SEL, RST) included in the pixel circuit 15, the selection transistor SEL and the reset transistor RST mainly function as switching elements, and the remaining amplification transistor AMP mainly functions as an amplification element.

[0041] 3, the amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the floating diffusion region FD and the source region of the reset transistor RST.

[0042] 3, the source of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive lines 10 shown in FIG.

[0043] 3, the reset transistor RST has a source region electrically connected to the floating diffusion region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 shown in FIG.

[0044] When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 to the floating diffusion region FD.

[0045] When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd.

[0046] The selection transistor SEL shown in FIG. 3 controls the output timing of the pixel signal from the pixel circuit 15 .

[0047] 3 generates, as a pixel signal, a signal whose voltage corresponds to the level of the signal charge held in the floating diffusion region FD. The amplifying transistor AMP constitutes a source-follower amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated in the photoelectric conversion unit 25. When the selection transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0048] Referring to FIG. 3 , during operation of the solid-state imaging device 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 25 of the pixel 3 are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the pixel circuit 15 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 15. A horizontal line selection control signal is applied to the gate electrode of the select transistor SEL of the pixel circuit 15 from the vertical shift register. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 11. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0049] <Other Pixel Circuits> The selection transistor SEL may be omitted as necessary. In the case where the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).

[0050] A switching transistor may be provided between the reset transistor RST and the floating diffusion region FD and the gate electrode of the amplifier transistor AMP. The switching transistor controls charge retention by the floating diffusion region FD and adjusts the multiplication factor of the voltage corresponding to the potential amplified by the amplifier transistor AMP.

[0051] The switching transistor is also used to switch the conversion efficiency. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-voltage conversion, if the FD capacitance C (floating diffusion capacitance C) of the charge storage section (floating diffusion region FD) is large, the voltage V converted to voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large; therefore, if the FD capacitance C of the charge storage section is not large, the charge storage section will not be able to fully absorb the charge from the photoelectric conversion section 24 (photodiode PD). Furthermore, the FD capacitance C of the charge storage section must be large so that the voltage V converted to voltage by the amplifier transistor AMP does not become too large (in other words, to reduce it). Taking these factors into consideration, when the switching transistor is turned on, the gate capacitance of the switching transistor increases, increasing the overall FD capacitance C. On the other hand, when the switching transistor is turned off, the overall FD capacitance C decreases. In this way, by switching the switching transistor on and off, the FD capacitance C can be varied, thereby switching the conversion efficiency.

[0052] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to FIGS. 4A to 6. FIG.

[0053] For ease of understanding, the multilayer wiring layer, which will be described later, is not illustrated in Figures 4A to 6. Also, while Figure 1 illustrates the light incident surface side of the semiconductor chip 2, Figure 4A illustrates the photoelectric conversion region 22 as seen from the side opposite to the light incident surface side of the semiconductor chip 2 (the multilayer wiring layer side).

[0054] As shown in Figure 5A, the semiconductor chip 2 comprises a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located opposite each other in one direction, the Z direction (thickness direction), an inter-pixel isolation region 31 provided in the semiconductor layer 21 and serving as an isolation region extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 provided in the semiconductor layer 21 and partitioned by the inter-pixel isolation region 31, and including the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21.

[0055] Although not shown, the semiconductor chip 2 further includes a multi-layer wiring layer provided on the first surface S1 side of the semiconductor layer 21. The semiconductor chip 2 further includes a planarization film 61, an optical filter layer 63, and a lens layer 64 provided in this order from the second surface S2 side of the semiconductor layer 21.

[0056] Here, the first surface S1 of the semiconductor layer 21 is sometimes referred to as a main surface or an element forming surface, and the second surface S2 is sometimes referred to as a back surface. The solid-state imaging device 1A according to the first embodiment photoelectrically converts incident light incident from the second surface S2 side of the semiconductor layer 21 by a photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 is sometimes referred to as a light incident surface.

[0057] <Planarization Film, Optical Filter Layer, and Lens Layer> As shown in FIG. 5A , the planarization film 61 is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21, and planarizes the second surface S2 side of the semiconductor layer 21.

[0058] 5A , the optical filter layer 63 is provided on the side of the planarization film 61 opposite to the semiconductor layer 21 side. This optical filter layer 63 separates the color of incident light that is incident from the light incident surface side (second surface portion S2 side) of the semiconductor chip 2. This optical filter layer 63 includes an optical filter portion 63 a for each pixel 3 (for each photoelectric conversion region 22) that transmits light of a specific wavelength, such as, but not limited to, red (R), green (G), or blue (B).

[0059] 5A , the lens layer 64 is provided on the side of the optical filter layer 63 opposite to the planarization film 61. The lens layer 64 includes a microlens (on-chip lens) 64 a for each pixel 3 (for each photoelectric conversion region 22) that collects irradiated light and allows the collected light to efficiently enter the photoelectric conversion region 22.

[0060] That is, the pixel 3 of this first embodiment includes a photoelectric conversion region 22, a planarization film 61, an optical filter portion 63a, and a microlens 64 provided on the second surface portion S2 side of this photoelectric conversion region 22.

[0061] 5A , the semiconductor layer 21 includes an inter-pixel isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by the inter-pixel isolation region 31. The photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 may be a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21, although the present invention is not limited thereto.

[0062] 4A , in the inter-pixel isolation region 31, first extending portions 31x extending in the X direction are repeatedly arranged at predetermined intervals in the Y direction. In addition, in the inter-pixel isolation region 31, second extending portions 31y extending in the Y direction are repeatedly arranged at predetermined intervals in the X direction. In other words, the planar pattern of the inter-pixel isolation region 31 is a grid-like planar pattern in plan view.

[0063] 4A , the inter-pixel isolation region 31 corresponding to one photoelectric conversion region 22 has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22. Although not shown, the inter-pixel isolation regions 31 corresponding to four photoelectric conversion regions 22 arranged two by two in a 2×2 arrangement adjacent to each other in each of the X and Y directions in the same plane have a composite planar pattern having a cross-shaped planar pattern within the rectangular annular planar pattern.

[0064] 5A , the inter-pixel isolation region 31 extends in the thickness direction (Z direction) in which the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21 are spaced apart from each other. The inter-pixel isolation region 31 electrically and optically isolates two adjacent photoelectric conversion regions 22 when the semiconductor layer 21 is viewed in plan from the thickness direction (Z direction) of the semiconductor layer 21.

[0065] The inter-pixel isolation region 31 is configured as, for example, a trench isolation type including, but not limited to, a recessed portion 32 extending in the thickness direction (Z direction) of the semiconductor layer 21 and an isolation insulating film 33 provided in the recessed portion 32. As shown in Figures 4A and 5A, the inter-pixel isolation region 31 overlaps with an inter-element isolation region 41 provided on the first surface S1 side of the semiconductor layer 21 and extends from the bottom of the inter-element isolation region 41 to the second surface S2 of the semiconductor layer 21. The isolation insulating film 33 can be, for example, a silicon oxide film.

[0066] <Photoelectric Conversion Region> As shown in FIG. 4A , the photoelectric conversion region 22 is surrounded by the inter-pixel isolation region 31 in a plan view (when the semiconductor layer 21 is viewed from the thickness direction of the semiconductor layer 21) and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded in the inter-pixel isolation region 31 by two first extending portions 31x that extend in the X direction and are spaced apart in the Y direction, and two second extending portions 31y that extend in the Y direction and are spaced apart in the X direction. The photoelectric conversion region 22 is partitioned by the inter-pixel isolation region 31 including these first extending portions 31x and second extending portions 31y, and is separated from other photoelectric conversion regions 22. That is, the photoelectric conversion region 22 is adjacent to other photoelectric conversion regions 22 via the inter-pixel isolation region 31 in both the X direction and the Y direction.

[0067] As shown in FIG. 5A , the photoelectric conversion region 22 includes a p-type well region 23 consisting of a p-type semiconductor region provided in the semiconductor layer 21 across the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21, an n-type semiconductor region 24 provided in the p-type well region 23 at a distance from the first surface portion S1 of the semiconductor layer 21, and a photoelectric conversion unit 25 including the p-type well region 23 and the n-type semiconductor region 24 and provided in the semiconductor layer 21 at a distance from the first surface portion S1 of the semiconductor layer 21.

[0068] As shown in Figures 4A and 5A, the photoelectric conversion region 22 further includes an n-type floating diffusion region FD as a charge holding section that holds the signal charge photoelectrically converted by the photoelectric conversion section 25, and a transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion section 25 to the n-type floating diffusion region FD.

[0069] In addition, the photoelectric conversion region 22 further has an inter-element isolation region (field isolation region) 41 as an isolation region provided on the first surface S1 side of the semiconductor layer 21, and each of island-shaped element formation regions (active regions) 45a, 45b, 45c, and 45d partitioned by this inter-element isolation region 41.

[0070] The photoelectric conversion region 22 further includes, for example, an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST as the pixel transistors Q included in the pixel circuit 15 in Fig. 3. The photoelectric conversion region 22 further includes a p-type power supply contact region WC.

[0071] 4A, 5A, and 6, the inter-element isolation region 41 is provided in a surface layer portion on the first surface portion S1 side of the semiconductor layer 21. The inter-element isolation region 41 overlaps with the inter-pixel isolation region 31 in a plan view and is integrated with the inter-pixel isolation region 31.

[0072] 5A and 6 , the inter-element isolation region 41 extends from the first surface S1 side toward the second surface S2 side of the semiconductor layer 21 and has a thickness in the thickness direction (Z direction) of the semiconductor layer 21. The inter-element isolation region 41 may have, but is not limited to, an STI (Shallow Trench Isolation) structure in which an isolation insulating film 43 is selectively embedded in a shallow groove 42 recessed from the first surface S1 toward the second surface S2 of the semiconductor layer 21. Although not shown, the inter-element isolation region 41 is provided across adjacent photoelectric conversion regions 22 via the inter-pixel isolation region 31 in a planar view.

[0073] (Isolation Region) Here, the region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap can be considered as an isolation region including the inter-element isolation region 41 and the inter-pixel isolation region 31. The inter-element isolation region 41 included in this isolation region can be considered as a first isolation region, and the inter-pixel isolation region 31 included in this isolation region can be considered as a second isolation region. Furthermore, the inter-element isolation region 41 and the inter-pixel isolation region 31 can each be considered as an isolation region individually.

[0074] (Element Formation Regions) Each of the element formation regions 45a, 45b, 45c, and 45d included in the photoelectric conversion region 22 has a planar layout shown in FIG. 4A as an example, although not limited thereto.

[0075] Specifically, as shown in FIG. 4A , the element formation region 45 a is disposed on one of two sides (the right side in the drawing) of the photoelectric conversion region 22 that are opposite to each other in the X direction in a plan view, and extends in the Y direction. Also, as shown in FIG. 4A , the element formation region 5 b is disposed on one of two sides (the lower side in the drawing) of the photoelectric conversion region 22 that are opposite to each other in the Y direction in a plan view, and extends in the X direction. Also, as shown in FIG. 4A , the element formation regions 45 c and 45 d are disposed side by side in the X direction on the other side (the upper side in the drawing) of the photoelectric conversion region 22 that are opposite to each other in the Y direction in a plan view, and extend in the Y direction. Each of the element formation regions 45 b, 45 c, and 45 d is disposed between the element formation region 45 a and the inter-pixel isolation region 31 in a plan view. The planar shape of each of the element formation regions 45 a, 45 b, 45 c, and 45 d is, for example, rectangular.

[0076] 5A and 6, the p-type well region 23 is provided over a wide area in the photoelectric conversion region 22, extending from the first surface S1 side to the second surface S2 side of the semiconductor layer 21. The p-type well region 23 is in contact with the inter-pixel isolation region 31 along the thickness direction (Z direction) of the semiconductor layer 21. The p-type well region 23 is composed of a p-type semiconductor region.

[0077] 5A and 6 , the n-type semiconductor region 24 is provided in the p-type well region 23 in the photoelectric conversion region 22. That is, six sides of the n-type semiconductor region 24, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type well region 23. The n-type semiconductor region 24 is separated from the first surface S1 and second surface S2 of the semiconductor layer 21 and the inter-pixel isolation region 31.

[0078] 5A and 6 includes a p-type well region 23 and an n-type semiconductor region 24 in each photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a p-n junction photodiode (PD) including a p-n junction between the p-type well region 23 and the n-type semiconductor region 24.

[0079] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at the pn junction between the p-type well region 23 and the n-type semiconductor region 24. The photoelectric conversion unit 25 is provided in the semiconductor layer 21 at a distance from the first surface S1 of the semiconductor layer 21.

[0080] (Floating Diffusion Region) As shown in FIG. 4A , the n-type floating diffusion region FD is provided in the element formation region 45 a. The n-type floating diffusion region FD is disposed on one of two sides (the upper side in the figure) of the element formation region 45 a that are opposite each other in the Y direction. Although not shown in detail, referring to FIG. 5A , the n-type floating diffusion region FD is provided in the p-type well region 23 on the first surface portion S1 side of the semiconductor layer 21. The n-type floating diffusion region FD overlaps the photoelectric conversion unit 25 (n-type semiconductor region 24) in a plan view and is spaced from the photoelectric conversion unit 25 (n-type semiconductor region 24) in the thickness direction (Z direction) of the semiconductor layer 21. That is, the p-type well region 23 is provided between the n-type floating diffusion region FD and the n-type semiconductor region 24. The n-type floating diffusion region FD has a higher impurity concentration than the n-type semiconductor region 24.

[0081] (Power Supply Contact Region) As shown in FIG. 4A , the p-type power supply contact region WC is provided in the element formation region 45 a. The p-type power supply contact region WC is located on the other side (the lower side in the figure) of two sides of the element formation region 45 a that are opposite each other in the Y direction. While not shown in detail, referring to FIG. 5A , the p-type power supply contact region WC is provided in the p-type well region 23 on the first surface S1 side of the semiconductor layer 21. The p-type power supply contact region WC is formed of a p-type semiconductor region with a higher impurity concentration than the p-type well region 23 and is electrically connected to the p-type well region 23. A first reference potential (Vss potential), for example, 0 V, is applied to the p-type power supply contact region WC during operation as a reference potential within the semiconductor chip 2 (within the solid-state imaging device 1A). During operation, the p-type well region 23 is fixed to this first reference potential.

[0082] Pixel Transistor As shown in FIGS. 4A and 6 , among the pixel transistors Q included in the pixel circuit 15, the amplifier transistor AMP is provided in the element formation region 45b. That is, the amplifier transistor AMP is provided on the first surface S1 side of the semiconductor layer 21 in the photoelectric conversion region 22. The amplifier transistor AMP includes a gate electrode 56 provided on the upper surface side of the element formation region 45b (the first surface S1 side of the semiconductor layer 21) so as to overlap the element formation region 45b, and a gate insulating film 52 interposed between the gate electrode 56 and the element formation region 45b. The amplifier transistor AMP also includes a pair of main electrode regions 57a and 57b provided in the element formation region 45b on both sides of the gate electrode 56 in the gate length direction and functioning as a source region and a drain region. The amplifier transistor AMP also includes a channel formation region provided in the element formation region 45b so as to overlap the gate electrode 56 in a plan view.

[0083] The pair of main electrode regions 57a and 57b are spaced apart from each other via a channel forming portion. Each of the pair of main electrode regions 57a and 57b is made of an n-type semiconductor region having a higher impurity concentration than the n-type semiconductor region 24. The channel forming portion is made of a p-type well region 23.

[0084] 4A , of the pixel transistors Q included in the pixel circuit 15, the selection transistor SEL is provided in the element formation region 45 c. Also, of the pixel transistors Q included in the pixel circuit 15, the reset transistor RST is provided in the element formation region 45 d. Each of the selection transistor SEL and the reset transistor RST basically has the same configuration as the amplification transistor AMP, and therefore detailed description thereof will be omitted.

[0085] In each of the select transistor SEL and the reset transistor RST, the gate electrode and the pair of main electrode regions are assigned the same reference numerals as the gate electrode 56 and the pair of main electrode regions 57 a, 57 b of the amplifier transistor AMP. Although not shown in detail, each of the select transistor SEL and the reset transistor TST is provided on the first surface S1 side of the semiconductor layer 21 in the photoelectric conversion region 22, similar to the amplifier transistor AMP shown in FIG.

[0086] (Transfer Transistor) As shown in FIGS. 4A and 5A , the transfer transistor TR is provided on the edge of the element formation region 45 a included in the photoelectric conversion region 22. The transfer transistor TR has a gate electrode 55 extending in the thickness direction (Z direction) of the semiconductor layer 21 between the semiconductor layer 21 and the insulators (isolation insulating films 43 and 33) in the photoelectric conversion region 22 and adjacent to the semiconductor layer 21 and the insulators (isolation insulating films 43 and 33). The transfer transistor TR also has a gate insulating film 52 interposed between the gate electrode 55 and the semiconductor layer 21. The transfer transistor TR also has a p-type well region 23 functioning as a channel formation region where a channel is formed, and an n-type floating diffusion region FD and an n-type semiconductor region 24 functioning as a source region and a drain region. The transfer transistor TR has a vertical structure in which the gate electrode 55 extends in the thickness direction (Z direction) of the semiconductor layer 21.

[0087] 4A and 5A , the gate electrode 55 extends in the thickness direction (Z direction) of the semiconductor layer 21 across the isolation insulating film 43 of the inter-element isolation region 41 and the isolation insulating region 33 of the inter-pixel isolation region 31 in a region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in a plan view. The gate electrode 55 of the first embodiment is adjacent to the semiconductor layer 21 between the semiconductor layer 21 and the isolation insulating films 43 and 33, and extends in the thickness direction (Z direction) of the semiconductor layer 21 adjacent to each other and each of the isolation insulating films 43 and 33.

[0088] In the first embodiment, the isolation insulating film 43 of the inter-element isolation region 41 and the isolation insulating film 33 of the inter-pixel isolation region 31 correspond to a specific example of an "insulator" in the present technology. The isolation insulating film 43 corresponds to a specific example of a "first isolation insulating film" in the present technology, and the isolation insulating film 33 corresponds to a specific example of a "second isolation insulating film" in the present technology. In the first embodiment, the isolation insulating film 43 of the inter-element isolation region 41 and the isolation insulating film 33 of the inter-pixel isolation region 31 are integrated, so that the isolation insulating film 43 and the isolation insulating film 33 can be regarded as a single "insulator." Therefore, the gate electrode 55 in the first embodiment is adjacent to the sidewall surface portion 21 a of the semiconductor layer 21 outside the photoelectric conversion region 22, and extends along the thickness direction (Z direction) of the semiconductor layer 21 adjacent to the insulators including the isolation insulating films 43 and 33.

[0089] 4A and 4B, in the first embodiment, in a plan view of the semiconductor layer 21 viewed from the thickness direction (Z direction) of the semiconductor layer 21, a direction across an interface Lp between the semiconductor layer 21 and the insulator (the isolation insulating films 43 and 33) in the photoelectric conversion region 22 is referred to as a lateral direction A. １ The direction that intersects with this horizontal direction is called the vertical direction A ２ And, the horizontal direction A １ can be expressed as the arrangement direction in which the photoelectric conversion region 22 and the insulator (the isolation insulating film 43 and the isolation insulating film 33) are aligned in a plan view, or the separation direction away from the interface portion Lp. ２ can be expressed in other words as the extension direction in which the interface portion Lp extends in a plan view.

[0090] In FIG. 4A, the horizontal direction A crossing the interface portion Lp extending in the Y direction in a plan view. １ In this case, the horizontal direction A １ 4A, the horizontal direction crossing the interface Lp extending in the X direction in plan view is the Y direction in the figure. In other words, if the direction in which the interface Lp extends in the X direction in plan view is rotated by 90°, the horizontal direction A crossing the interface Lp will be １ Also rotated by 90°, this horizontal direction A １ Vertical direction A intersecting with ２ It also rotates 90 degrees.

[0091] Although not limited to this, the gate electrode 55 of the first embodiment protrudes upward from the insulator including the isolation insulating films 43 and 33 on the first surface S1 side of the semiconductor layer 21. In other words, the gate electrode 55 of the first embodiment extends from the inside to the outside of the insulator including the isolation insulating films 43 and 33 in the thickness direction (Z direction) of the semiconductor layer 21.

[0092] Furthermore, although not limited to this, the gate electrode 55 of this first embodiment has a straight shape that does not have a step portion due to a difference in width between the portion located outside the insulator including the isolation insulating films 43 and 33 and the portion located inside this insulator.

[0093] As shown in FIGS. 4B and 5B, the gate electrode 55 has, for example, an upper surface portion 55a, a lower surface portion 55b, and four side surface portions 55c. １ , 55c ２ , 55c ３ , 55c ４ The upper surface portion 55a and the lower surface portion 55b are located on opposite sides to each other in the thickness direction (Z direction) of the semiconductor layer 21.

[0094] Four side portions 55c １ , 55c ２ , 55c ３ and 55c ４ Among these, the side surface portion 55c １ and the side surface portion 55c ２ The horizontal direction A １The four side portions 55c are located on the opposite sides of the １ , 55c ２ , 55c ３ , 55c ４ The remaining side surface portion 55c ３ and the side surface portion 55c ４ The vertical direction A ２ are located opposite each other in

[0095] In the first embodiment, the side surface 55c of the gate electrode 55 １ corresponds to a specific example of a “first side surface portion” of the present technology, and the side surface portion 55c of the gate electrode 55 ２ corresponds to a specific example of “second side portion” of the present technology.

[0096] As shown in FIGS. 4B and 5B, the side surface 55c of the gate electrode 55 １ is located on the semiconductor layer 21 side of the photoelectric conversion region 22 and is adjacent to the sidewall surface portion 21a of the semiconductor layer 21 with the gate insulating film 52 interposed therebetween. ２ are located on the insulator side (the isolation insulating films 43 and 33 side) opposite to the semiconductor layer 21 side of the photoelectric conversion region 22.

[0097] Side portion 55c of gate electrode 55 １ The sidewall surface 21a (sidewall portion of the photoelectric conversion region) of the semiconductor layer 21 adjacent to the gate electrode 55 has a silicon crystal orientation of, for example, the (100) plane. １ are two-dimensionally adjacent to the sidewall surface portion 21 a of the semiconductor layer 21 over a wide area, with the gate insulating film 52 interposed therebetween. The sidewall surface portion 21 a of the semiconductor layer 21 can be easily formed by etching the semiconductor layer 21 under etching conditions that are along the (100) plane of silicon.

[0098] As shown in FIGS. 4B and 5B, the gate electrode 55 is formed in a vertical direction A in a plan view. ２ First width W along １ is the horizontal direction A １ Second width W along ２ In other words, the gate electrode 55 is wider than the width A in a plan view. １ Second width W along ２ is the vertical direction A２ First width W along １ In other words, the gate electrode 55 has a first width W １ The second width W is a width along the arrangement direction in which the photoelectric conversion region 22 and the insulator (the isolation insulating film 43 and the isolation insulating film 33) are aligned in a plan view or along the separation direction in which the photoelectric conversion region 22 and the insulator (the isolation insulating film 43 and the isolation insulating film 33) are separated from the interface portion Lp. ２ That is, the gate electrode 55 has a first width W １ >Second width W ２ "

[0099] 4B and 5B, the gate electrode 55 is located closer to the insulator (the isolation insulating films 43 and 33) than the interface Lp in plan view. In other words, the gate electrode 55 is provided outside the sidewall surface portion 21a of the semiconductor layer 21. Therefore, the gate electrode 55 of this first embodiment has four side surface portions 55c. １ , 55c ２ , 55c ３ and 55c ４ One of the side surfaces 55c １ adjacent to the side wall surface portion 21a of the semiconductor layer 21, and the remaining three side surface portions 55c ２ , 55c ３ and 55c ４ are adjacent to the insulators (the isolation insulating film 43 and the isolation insulating film 33).

[0100] The gate insulating film 52 is made of, for example, a silicon oxide film, and the gate electrode 55 is made of, for example, a polycrystalline silicon film into which an impurity that reduces the resistance value is introduced.

[0101] <Method for Manufacturing Solid-State Imaging Device> Next, a method for manufacturing the solid-state imaging device 1A according to the first embodiment of the present technology will be described with reference to FIGS. 7A to 7E.

[0102] In the first embodiment, the description will be focused on the manufacturing method of the solid-state imaging device 1A, specifically the manufacturing method of the gate electrodes of the transfer transistors.

[0103] Moreover, since each of the element formation regions 45a to 45d is formed in the same process, only the element formation region 45a in which the transfer transistor TR is formed will be described, and a description of each of the other element formation regions 45b to 45d will be omitted.

[0104] First, as shown in FIG. 7A , a photoelectric conversion region 22, a p-type well region 23, a photoelectric conversion section 25 including an n-type semiconductor region 24, an inter-pixel isolation region 31, an inter-element isolation region 41, an element formation region 45a, and the like are formed in the semiconductor layer 21. The inter-pixel isolation region 31 can be formed by forming a recessed portion 32 extending in the thickness direction (Z direction) of the semiconductor layer 21 in the semiconductor layer 21 and then selectively filling the recessed portion 32 with an isolation insulating film 33. The element isolation region 41 can be formed by forming a shallow groove portion 42 on the first surface S1 side of the semiconductor layer 21 and then selectively filling the shallow groove portion 42 with an isolation insulating film 43. Then, by forming the inter-pixel isolation region 31 and the inter-element isolation region 41, a photoelectric conversion region 22 is formed that is partitioned by the inter-pixel isolation region 31 and the inter-element isolation region 41 and has an element formation region 45a on the first surface S1 side of the semiconductor layer 21. The order of forming the inter-pixel isolation region 31 and the inter-element isolation region 41 may be any. In either case, an insulator including isolation insulating films 43 and 33 is formed in the region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in plan view.

[0105] Next, as shown in FIG. 7B , a dug portion (gate trench) 51 extending in the thickness direction (Z direction) of the semiconductor layer 21 is formed. The dug portion 51 is for forming the gate electrode 55 of the transfer transistor TR. In this first embodiment, the dug portion 51 is formed around the photoelectric conversion region 22 in a region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap. The dug portion 51 is formed across the inter-element isolation region 41 and the inter-pixel isolation region 31 so that the sidewall surface 21 a of the semiconductor layer 21 in the photoelectric conversion region 22 is exposed. The dug portion 51 is formed in a rectangular parallelepiped shape having four side surfaces. One of the four side surfaces is the sidewall surface 21 a of the semiconductor layer 21. The remaining three side surfaces are three sidewall surfaces of an insulator including the isolation insulating films 43 and 33. The recessed portion 51 can be formed by selectively etching the isolation insulating film 43 of the inter-element isolation region 41 and the isolation insulating film 33 of the inter-pixel isolation region 31 using, for example, well-known photolithography and anisotropic dry etching techniques under conditions that ensure a selectivity with respect to the semiconductor layer 21. In this process, the semiconductor layer 21 is also slightly etched.

[0106] Next, the native oxide film and excess insulating film in the recessed portion 51 are selectively removed by, for example, wet etching to expose the sidewall surface portion 21a of the semiconductor layer 21 in the recessed portion 51. Then, as shown in FIG. 7C , a gate insulating film 52 is formed on the sidewall surface portion 21a of the semiconductor layer 21. The gate insulating film 52 may be, for example, a silicon oxide film. A silicon oxide film can be formed by thermal oxidation or deposition, but in this first embodiment, a silicon oxide film formed by thermal oxidation is used as the gate insulating film 52. Thermal oxidation can form a silicon oxide film with better film quality than deposition. In this process, the gate insulating film 52 is also formed on the upper surface of the element formation region 45a, which is on the first surface S1 side of the semiconductor layer 21.

[0107] 7D , a conductive film 53 is formed. The conductive film 53 is formed on the first surface S1 side of the semiconductor layer 21 so as to fill the inside of the recessed portion 51. The conductive film 53 can be formed, for example, by a CVD method, and can be a polycrystalline silicon film into which an impurity that reduces the resistance value is introduced during or after the film formation.

[0108] Next, the conductive film 53 is patterned to form a gate electrode 55 extending across the inter-element isolation region 41 and inter-pixel isolation region 31 outside the photoelectric conversion region 22, as shown in FIG. 7E.

[0109] In this step, the gate electrode 55 is １ (See FIG. 5B) １ , 55c ２ and vertical direction A ２ (See FIG. 5B) ３ , 55c ４ The four side portions 55c are formed in a rectangular parallelepiped shape. １ , 55c ２ , 55c ３ and 55c ４ One of the side surfaces 55c １ are adjacent to the side wall surface portions 21a of the semiconductor layer 21 in the photoelectric conversion region 22 with the gate insulating film 52 interposed therebetween, and the remaining three side surface portions 55c ２ , 55c ３ and 55c ４ Each of these is adjacent to an insulator (the isolation insulating films 43 and 33).

[0110] Thereafter, an n-type floating diffusion region FD is formed in the element formation region 45 a of the photoelectric conversion region 22, whereby a transfer transistor TR is formed in the element formation region 45 a of the photoelectric conversion region 22, mainly including a gate insulating film 52, a gate electrode 55, an n-type semiconductor region 24 and an n-type floating diffusion region FD that function as a source region and a drain region, and a p-type well region 23 that functions as a channel formation portion.

[0111] <<Main Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described. As described above, the solid-state imaging device 1A according to the first embodiment includes a transfer transistor TR provided on the edge of the photoelectric conversion region 22. The transfer transistor TR has a gate electrode 55 extending in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22 and the insulator (isolation insulating films 43 and 33) and adjacent to the semiconductor layer 21 and the insulator (isolation insulating films 43 and 33). This reduces the area where the gate electrode 55 and the semiconductor layer 21 are adjacent by an amount corresponding to the area where the gate electrode 55 and the insulator (isolation insulating films 43 and 33) are adjacent. This reduces the capacitance component between the gate electrode 55 and the semiconductor layer 21 (parasitic capacitance with the semiconductor layer 21 as the first electrode, the gate insulating film 52 as the dielectric film, and the gate electrode 55 as the second electrode) compared to a conventional gate electrode whose entire periphery is adjacent to the semiconductor layer. This can improve the rounding of the drive pulse applied to the gate electrode 55, thereby suppressing a decrease in the transfer speed (pixel drive speed) at which signal charges are transferred from the photoelectric conversion unit 25 to the floating diffusion region FD. This suppression of a decrease in the transfer speed contributes to improving the performance of the solid-state imaging device 1A. Therefore, the solid-state imaging device 1A according to the first embodiment can improve the performance of the solid-state imaging device 1A.

[0112] In the first embodiment, the gate electrode 55 is located closer to the insulator (the isolation insulating films 43 and 33) than the interface Lp in plan view. １ , 55c ２ , 55c ３ and 55c ４ Among these, one side surface portion 55c adjacent to the semiconductor layer 21 １ The remaining three side portions 55c excluding ２ , 55c ３ and 55c ４ Each of the sidewall surfaces 55c is adjacent to the insulator (the isolation insulating films 43 and 33). ２ , 55c ３ and 55c ４The capacitance component (parasitic capacitance) between the gate electrode 55 and the semiconductor layer 21 can be reduced by an amount corresponding to the area of ​​each of the above.

[0113] Furthermore, since the gate electrode 55 extends in the thickness direction (Z direction) of the semiconductor layer 21, poor transfer of signal charges accumulated in the photoelectric conversion section 25 on the second surface S2 side of the semiconductor layer 21 to the floating diffusion region FD can be suppressed, thereby suppressing afterimages.

[0114] In addition, in a plan view of the semiconductor layer 21 viewed from the thickness direction (Z direction) of the semiconductor layer 21, a direction crossing an interface Lp between the semiconductor layer 21 and the insulator (the isolation insulating films 43 and 33) is referred to as a lateral direction A. １ In this horizontal direction A １ The direction that intersects with this is the vertical direction A. ２ , the gate electrode 55 is ２ First width W along １ is the horizontal direction A １ Second width W along ２ This increases the area where the semiconductor layer 21 of the photoelectric conversion region 22 and the gate electrode 55 face each other, improving the modulation power during transfer and enabling signal charges to be read out from a greater distance.

[0115] In addition, the first width W of the gate electrode 55 is set according to the planar size of the photoelectric conversion region 22. １ This allows for easy scalable design changes.

[0116] The first width W of the gate electrode 55 １ is the second width W ２ Since the area is wider than the area of ​​the gate electrode 55 , the freedom in arranging the contact electrodes connected to the gate electrode 55 is improved, and the freedom in routing the wiring electrically connected to the gate electrode 55 is also improved.

[0117] In addition, the side surface 55c of the gate electrode 55 １The sidewall surface portion 21a of the semiconductor layer 21 adjacent to the gate electrode 55 has a silicon crystal orientation of (100). This (100) surface has fewer dangling bonds and fewer interface states than the (111) or (110) surfaces. Therefore, when transferring signal charges from the photoelectric conversion unit 25 to the floating diffusion region FD, the sidewall surface portion 55c of the gate electrode 55 １ This reduces the probability of capturing (trapping) signal charges at the sidewall surface portions 21a of the adjacent semiconductor layers 21, thereby making it possible to suppress transfer failure of signal charges.

[0118] Furthermore, since the interface state density at the sidewall surface portion 21a of the semiconductor layer 21 is small, dark current and white spots can be suppressed, and as a result, image quality characteristics can be improved.

[0119] Furthermore, the gate electrode 55 in this first embodiment is located closer to the insulator (the isolation insulating films 43 and 33) than the interface Lp between the semiconductor layer 21 of the photoelectric conversion region 22 and the insulator (the isolation insulating films 43 and 33). Therefore, compared to the conventional case in which the gate electrode is embedded in the semiconductor layer 21 of the photoelectric conversion region 22, the volume of the photoelectric conversion unit 25 can be increased for a photoelectric conversion region 22 of the same planar size, and the saturation signal amount Qs can be increased. This allows for an expansion of the dynamic range.

[0120] In the first embodiment, the case where the sidewall surface portion 21a of the semiconductor layer 21 has a (100) crystal orientation of silicon has been described, but since the (010) and (001) crystal orientations of silicon are equivalent to the (100) plane, the sidewall surface portion 21a of the semiconductor layer 21 may have a (010) or (001) crystal orientation of silicon. That is, it is preferable that the crystal orientation of the sidewall surface portion 21a of the semiconductor layer 21 is any one of the (100), (010), and (001) crystal orientations.

[0121] <<Modification of First Embodiment>> Next, a modification of the first embodiment will be described.

[0122] 8A is a diagram showing Modification 1-1 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. Fig. 8B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a8-a8 cutting line in Fig. 8A.

[0123] 8A and 8B, in Modification 1-1, the relative positions of the gate electrode 55 and the interface Lp are changed. That is, in the first embodiment described above, the gate electrode 55 is located closer to the insulator (the isolation insulating films 43 and 33) than the interface Lp in plan view, as shown in FIGS. 4A to 5B.

[0124] 8A and 8B, in this modification 1-1, the gate electrode 55 crosses the interface Lp in a plan view. In other words, the gate electrode 55 of this modification 1-1 is located on both the photoelectric conversion region 22 side and the insulator side (the isolation insulating films 43 and 33 side) across the interface Lp in a plan view.

[0125] In this modification 1-1, compared to a conventional gate electrode whose entire periphery is adjacent to the semiconductor layer, the area where the gate electrode 55 and the semiconductor layer 21 are adjacent can be reduced by an amount equivalent to the area where the gate electrode 55 and the insulator (the isolation insulating films 43 and 33) are adjacent, and the capacitance component (parasitic capacitance) between the gate electrode 55 and the semiconductor layer 21 added to the gate electrode 55 can be reduced. Therefore, in this modification 1-1, as in the first embodiment described above, a decrease in the transfer speed (pixel drive speed) at which signal charges are transferred from the photoelectric conversion unit 25 to the floating diffusion region FD can be suppressed, and the performance of the solid-state imaging device 1A can be improved.

[0126] However, in the gate electrode 55 of this modification 1-1, the side surface portion 55c located on the side of the sidewall surface portion 21a of the semiconductor layer 21 １ In addition, the vertical direction A ２ Two side portions 55c located on the opposite sides of each other ３ and 53c ４ A part of each of these is adjacent to the semiconductor layer 21 with the gate insulating film 52 interposed therebetween. Therefore, in the case of this modified example 1-1, the effect of reducing the capacitance component between the gate electrode 55 and the semiconductor layer 21 is slightly inferior to that of the first embodiment described above.

[0127] 9A is a diagram showing Modification 1-2 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. Fig. 9B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a9-a9 cutting line in Fig. 9A.

[0128] 9A and 9B, in this modification 1-2, the relative positions of the gate electrode 55 and the interface Lp are also changed. That is, as shown in Fig. 9A and 9B, in this modification 1-2, unlike the first embodiment and modification 1-1 described above, the gate electrode 55 is located closer to the semiconductor layer 21 of the photoelectric conversion region 22 than the interface Lp in a plan view.

[0129] In this modification 1-2, compared to a conventional gate electrode whose entire periphery is adjacent to the semiconductor layer, the area where the gate electrode 55 and the semiconductor layer 21 are adjacent can be reduced by an amount equivalent to the area where the gate electrode 55 and the insulator (the isolation insulating films 43 and 33) are adjacent, and the capacitance component (parasitic capacitance) between the gate electrode 55 and the semiconductor layer 21 added to the gate electrode 55 can be reduced. Therefore, in this modification 1-2, as in the first embodiment described above, a decrease in the transfer speed (pixel drive speed) at which signal charges are transferred from the photoelectric conversion unit 25 to the floating diffusion region FD can be suppressed, and the performance of the solid-state imaging device 1A can be improved.

[0130] However, in the gate electrode 55 of this modification 1-2, the side surface portion 55c located on the side of the sidewall surface portion 21a of the semiconductor layer 21 １ In addition, two side portions 55c located opposite to each other in the longitudinal direction A2 ３ and 53c ４ are entirely adjacent to the semiconductor layer 21 with the gate insulating film 52 interposed therebetween. Therefore, in the case of this modification 1-2, the effect of reducing the capacitance component between the gate electrode 55 and the semiconductor layer 21 is slightly inferior to that of the above-described modification 1-1.

[0131] 10A is a diagram showing Modification 1-3 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. Fig. 10B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a10-a10 cutting line in Fig. 10A.

[0132] 10A and 10B, in the modification 1-3, in the region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in a plan view, the insulator including the isolation insulating films 43 and 33 is arranged such that the lateral direction A of the isolation insulating film 43 and the isolation insulating film 33 is perpendicular to the lateral direction A of the isolation insulating film 43 and the isolation insulating film 33. １ 10B ). In this modification 1-3, one end side (photoelectric conversion unit 25 side) of the gate electrode 55 terminates closer to the first surface S1 side of the semiconductor layer 21 than the step portion 36 of the insulator in the thickness direction (Z direction) of the semiconductor layer 21. In other words, the gate electrode 55 of this modification 1-3 extends in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22 and the insulator (isolation insulating film 43), adjacent to the semiconductor layer 21 of the photoelectric conversion region 22 and the insulator (isolation insulating film 43), and is located closer to the first surface S1 side of the semiconductor layer 21 than the step portion 36 of the insulator. That is, the present technology can also be applied to an insulator having a stepped structure including the step portion 36 due to the difference in width between the isolation insulating film 43 and the isolation insulating film 33. In the step portion 36, the gate electrode 55 is located between the photoelectric conversion region 22 and the insulator (isolation insulating film 43) in the lateral direction A of the isolation insulating film 43. １ The width along the lateral direction A of the isolation insulating film 33 is larger than the width along the lateral direction A of the isolation insulating film 33. １ It is wider than the width along the line.

[0133] In this modified example 1-3, the same effects as those of the above modified example 1-1 can be obtained.

[0134] In addition, in this variant 1-3, the length of the gate electrode 55 along the Z direction is simply made shorter than that of the gate electrode 55 in the above-mentioned variant 1-1, and one end side (the photoelectric conversion section 25 side) of the gate electrode 55 terminates closer to the first surface S1 of the semiconductor layer 21 than the step portion 36 of the insulator. However, it is also possible to leave the length of the gate electrode 55 along the Z direction unchanged and increase the length of the inter-element isolation region 41 along the Z direction (increase the depth of the inter-element isolation region 41 along the Z direction) so that one end side of the gate electrode 55 terminates closer to the first surface S1 of the semiconductor layer 21 than the step portion 36 of the insulator.

[0135] 11A is a diagram illustrating a modification 1-4 according to the first embodiment of the present technology, and is a plan view schematically illustrating one pixel. Fig. 11B is a longitudinal sectional view schematically illustrating a longitudinal sectional structure taken along the a11-a11 cutting line in Fig. 11A.

[0136] 11A and 11B, Modification 1-4 combines the relative positions of the gate electrode 55 and the interface portion Lp in Modification 1-2 with Modification 1-3. That is, as in Modification 1-3, in Modification 1-4, in the overlapping portion where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in a planar view, the insulator including the isolation insulating films 43 and 33 has a stepped structure including a step portion 36, and the gate electrode 55 is located closer to the first surface S1 of the semiconductor layer 21 than the step portion 36 of the insulator. Furthermore, in Modification 1-4, as in Modification 1-2, the gate electrode 55 is located closer to the semiconductor layer 22 of the photoelectric conversion region 22 than the interface portion Lp in a planar view.

[0137] In the gate electrode 55 of this modification 1-4, similarly to the above-described modification 1-2, the side surface portion 55c ２are adjacent to the insulating isolation film 43, it is possible to reduce the capacitance component (parasitic capacitance) between the gate electrode 55 and the semiconductor layer 21, compared to a conventional gate electrode whose entire periphery is adjacent to the semiconductor layer. Therefore, in this modified example 1-4 as well, it is possible to suppress a decrease in the transfer speed (pixel drive speed) at which signal charges are transferred from the photoelectric conversion unit 25 to the floating diffusion region FD, and it is possible to improve the performance of the solid-state imaging device 1A.

[0138] 12A is a diagram showing Modification 1-5 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. Fig. 12B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a12-a12 cutting line in Fig. 12A.

[0139] As shown in FIGS. 12A and 12B, this modification 1-5 is obtained by changing the length of the gate electrode 55 along the Z direction in the above modification 1-4.

[0140] 12A and 12B , in this modification 1-5, one end side (photoelectric conversion unit 25 side) of the gate electrode 55 terminates in the thickness direction (Z direction) of the semiconductor layer 21 closer to the second surface portion S2 of the semiconductor layer 21 than the step portion 36 of the insulator. In other words, the gate electrode 55 of this modification 1-5 extends in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22 and the insulator (isolation insulating film 43) adjacent to the semiconductor layer 21 of the photoelectric conversion region 22 and the insulator (isolation insulating film 43), and terminates on the second surface portion S2 of the semiconductor layer 21 closer to the step portion 36 of the insulator. That is, the length of the gate electrode 55 of this modification 1-5 in the Z direction extending from the first surface portion S1 of the semiconductor layer 21 to the second surface portion S2 is longer than the thickness of the isolation insulating film 43 in the Z direction (the thickness of the element isolation region 41). In this modified example 1-5, the semiconductor layer 21 is present between one end side of the gate electrode 55 and the isolation insulating film 33 of the insulator, closer to the second surface S2 of the semiconductor layer 21 than the step portion 36 of the insulator, and one end side of the gate electrode 55 is adjacent to the semiconductor layer 21 with the gate insulating film 52 interposed therebetween. That is, the entire periphery of the one end side (photoelectric conversion unit 25 side) of the gate electrode 55 of this modified example 1-5 is adjacent to the semiconductor layer 21 with the gate insulating film 52 interposed therebetween.

[0141] In the case of this modification 1-5, the area where the gate electrode 55 and the semiconductor layer 21 are adjacent to each other is slightly larger than in the above-described modification 1-4, and therefore the effect of reducing the capacitance component between the gate electrode 55 and the semiconductor layer 21 is slightly inferior compared to the above-described modification 1-4. However, the gate electrode 55 of this modification 1-5 is adjacent to the isolation insulating film 43 made of the insulator on the first surface portion S1 side of the semiconductor layer 21 rather than the step portion 36 made of the insulator. Therefore, compared to a conventional gate electrode whose entire periphery is adjacent to the semiconductor layer, it is possible to reduce the capacitance component (parasitic capacitance) between the gate electrode 55 and the semiconductor layer 21. Therefore, even in this modification 1-5, it is possible to suppress a decrease in the transfer speed (pixel drive speed) at which signal charges are transferred from the photoelectric conversion unit 25 to the floating diffusion region FD, thereby improving the performance of the solid-state imaging device 1A.

[0142] <Modification 1-6> FIG. 13 is a diagram showing Modification 1-6 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel.

[0143] 13, in this modification 1-6, in the above-described first embodiment, two transfer transistors TR (TR1, TR2) are provided in the element formation region 45a of the photoelectric conversion region 22. In this modification 1-6, the planar shape of the element formation region 45a is different.

[0144] That is, as shown in FIG. 13, the element forming region 45a of this modified example 1-6 has a first portion 45a extending in the Y direction on the edge side of the photoelectric conversion region 22. １ and this first portion 45a １ The second portion 45a extends in the X direction from one end side of the ２ The planar shape is an L-shape including the above.

[0145] As shown in FIG. 13, one of the two transfer transistors TR1 and TR2 is a transfer transistor TR1 located in a first portion 45a of an element forming region 45a. １ The other transfer transistor TR2 is provided in the second portion 45a of the element forming region 45a. ２That is, the transfer transistor TR1 is provided on the edge side of the photoelectric conversion region 22 located in the X direction, and the transfer transistor TR2 is provided on the edge side of the photoelectric conversion region 22 located in the Y direction.

[0146] Each of the transfer transistors TR1 and TR2 has the same configuration as the transfer transistor TR of the first embodiment described above. The transfer transistor TR1 is arranged in the same orientation as the transfer transistor TR of the first embodiment described above. That is, the transfer transistor TR1 is arranged so that the longitudinal direction of the gate electrode 55 is the Y direction in a plan view. On the other hand, the orientation of the transfer transistor TR2 is rotated by 90° compared to the transfer transistor TR2. That is, the transfer transistor TR2 is arranged so that the longitudinal direction is the X direction in a plan view.

[0147] The gate electrode 55 of the transfer transistor TR1 is located closer to the insulator (the isolation insulating films 43 and 33 side) than the interface Lp extending in the Y direction in a plan view, similar to the transfer transistor TR of the first embodiment described above. The gate electrode 55 of the transfer transistor TR2 is located closer to the insulator (the isolation insulating films 43 and 33 side) than the interface Lp extending in the X direction in a plan view. That is, although the orientations of the transfer transistors TR1 and TR2 are different, both gate electrodes 55 are located closer to the insulator (the isolation insulating films 43 and 33 side) than the interface Lp extending in the X direction in a plan view, and the four side surface portions 55c １ , 55c ２ , 55c ３ and 55c ４ Three of the side surfaces 55c ２ , 55c ３ and 55c ４ are adjacent to the insulators (isolation insulating films 43 and 33).

[0148] As shown in FIG. 13, the floating diffusion region FD of this modification is formed in a first portion 45a of the element forming region 45a in a plan view. １ and the second portion 45a ２ It is provided at the corner where and intersect.

[0149] In this modification 1-6, as in the above-described first embodiment, it is possible to reduce the capacitance component (parasitic capacitance) between the semiconductor layer 21 and the gate electrode 55. Therefore, in this modification 1-6, as in the above-described first embodiment, it is possible to suppress a decrease in the transfer speed (pixel drive speed) at which signal charges are transferred from the photoelectric conversion unit 25 to the floating diffusion region FD, thereby improving the performance of the solid-state imaging device 1A.

[0150] In addition, in this variant example 1-6, two transfer transistors TR1 and TR2 are provided in one photoelectric conversion region 22, thereby improving the transfer efficiency of transferring the signal charge photoelectrically converted in the photoelectric conversion section 25 to the floating diffusion region FD.

[0151] In addition, in this modified example 1-6, the first portion 45a of the element forming region 45a １ The transfer transistor TR1 is provided in the second portion 45a of the element forming region 45a. ２ The transfer transistor TR2 is provided in the first portion 45a of the element forming region 45a. １ and the second portion 45a ２ A floating diffusion region FD is provided at the corner where the two transfer transistors TR1 and TR2 intersect. This configuration can reduce the difference between the distance from the floating diffusion region FD to one transfer transistor TR1 and the distance from the floating diffusion region FD to the other transfer transistor TR2, or can make both distances equal, thereby further improving the transfer efficiency of transferring the signal charges photoelectrically converted in the photoelectric conversion unit 25 to the floating diffusion region FD.

[0152] In addition, in this modification 1-6, two transfer transistors TR (TR1, TR2) are provided in the same element forming region 45a, but the two transfer transistors TR1 and TR2 may be provided separately in two different element forming regions.

[0153] <Modification 1-7> FIG. 14 is a diagram showing Modification 1-7 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel.

[0154] 14, this modification 1-7 is a combination of the above-described modification 1-6 and the relative positions of the gate electrode 55 and the interface portion Lp in the above-described modification 1-1. That is, as shown in FIG. 14, in this modification 1-7, the gate electrodes 55 of the two transfer transistors TR1 and TR2 cross the interface portion Lp in a plan view, similar to the above-described modification 1-1.

[0155] In this variant 1-7, as in the above-mentioned variant 1-1, the capacitance component (parasitic capacitance) between the gate electrode 55 and the semiconductor layer 21 can be reduced, and as in the above-mentioned variant 1-6, the transfer efficiency of transferring the signal charge photoelectrically converted in the photoelectric conversion section 25 to the floating diffusion region FD can be increased.

[0156] <Modification 1-8> FIG. 15 is a diagram showing Modification 1-8 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel.

[0157] As shown in Figure 15, in this variant 1-8, the planar shape of the element formation region 45a included in the photoelectric conversion region 22 is different from that of the above-mentioned variant 1-6, and the arrangement of the other transfer transistor TR2 of the two transfer transistors TR1 and TR2 is different.

[0158] That is, as shown in FIG. 15, the element forming region 45a of this modified example 1-8 has a first portion 45a extending in the Y direction on the edge side of the photoelectric conversion region 22. １ and this first portion 45a １ a second portion 45a extending in the X direction from one end side in the Y direction of the ２ and this second portion 45a ２ First portion 45a １ a third portion 45a extending in the Y direction from one end side opposite to the ３ The first portion 45a has a C-shaped planar shape including the first and second portions 45a and 45b. １ and the third portion 45a ３ are located on opposite sides of the element isolation region 41 of the photoelectric conversion region 22 in the X direction.

[0159] The transfer transistor TR1 of this modification 1-8 is formed by the first portion 45a of the element forming region 45a in the same manner as the modification 1-6. １ On the other hand, the transfer transistor TR2 of this modification 1-8 is different from the modification 1-6 in that the third portion 45a of the element forming region 45a ３ In other words, the transfer transistor TR1 is provided on one edge side of the photoelectric conversion region 22 located in the X direction, and the transfer transistor TR2 is provided on the other edge side of the photoelectric conversion region 22 located in the X direction. In this modification 1-8, the floating diffusion region FD is provided in the second portion 45a of the element formation region 45a. ２ It is provided in the middle part of the

[0160] In this modification 1-8, similarly to the first embodiment, the gate electrode 55 of each of the two transfer transistors TR1 and TR2 has three side portions 55c. ２ , 55c ３ and 55c ４ are adjacent to the insulators (the isolation insulating films 43 and 33), the capacitance component (parasitic capacitance) between the gate electrode 55 and the semiconductor layer 21 can be reduced compared to a conventional gate electrode whose entire periphery is adjacent to the semiconductor layer.

[0161] Furthermore, in this variant 1-8, two transfer transistors TR1 and TR2 are provided in one photoelectric conversion region 22, so as in the above-mentioned variant 1-6, the transfer efficiency of transferring the signal charge photoelectrically converted in the photoelectric conversion section 25 to the floating diffusion region FD can be improved.

[0162] Furthermore, in this variant 1-8, the difference between the distance from the floating diffusion region FD to one transfer transistor TR1 and the distance from the floating diffusion region FD to the other transfer transistor TR2 can be made small, or both distances can be made equal, so as in the above-mentioned variant 1-6, the transfer efficiency of transferring the signal charge photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD can be further improved.

[0163] <Modification 1-9> FIG. 16 is a diagram showing Modification 1-9 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel.

[0164] As shown in FIG. 16, this modified example 1-9 is a combination of the above modified example 1-8 and the relative positions of the gate electrode 55 and the interface portion Lp in the above modified example 1-1.

[0165] That is, as shown in FIG. 16, in this modification 1-9, the gate electrodes 55 of the two transfer transistors TR1 and TR2 cross the interface portion Lp in a planar view, similar to the gate electrode 55 of the transfer transistor TR shown in the above-mentioned modification 1-1.

[0166] In this variant 1-9, as in the above-mentioned variant 1-1, the capacitance component (parasitic capacitance) between the semiconductor layer 21 added to the gate electrode 55 can be reduced, and as in the above-mentioned variant 1-6, the transfer efficiency of transferring the signal charge photoelectrically converted in the photoelectric conversion section 25 to the floating diffusion region FD can be increased.

[0167] 17A is a diagram showing Modification 1-10 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. Fig. 17B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a17-a17 cutting line in Fig. 17A.

[0168] As shown in FIGS. 17A and 17B, this modification 1-10 differs from the first embodiment in the configuration of the photoelectric conversion region 22 and the configuration of the inter-pixel isolation region 31.

[0169] 17A and 17B, the photoelectric conversion region 22 of this modification 1-10 does not include the inter-element isolation region 41 and the island-shaped element formation regions 45a, 45b, 45c, and 45d shown in FIGS. 4A and 5A of the first embodiment, and instead includes a p-type well region 23 that constitutes the inter-element isolation region. The inter-pixel isolation region 31 of this modification 1-10 extends from the first surface S1 toward the second surface S2 of the semiconductor layer 21. The gate electrode 55 of this modification 1-10 extends in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22 and the inter-pixel isolation region 31, adjacent to the semiconductor layer 21 of the photoelectric conversion region 22 and the isolation insulating film 33 of the inter-pixel isolation region 31. That is, this modification 1-10 includes the inter-pixel isolation region 31 as an isolation region, and the isolation insulating film 33 of the inter-pixel isolation region 31 as an insulator.

[0170] In this modification 1-10, the inter-pixel isolation region 31 corresponds to a specific example of "isolation region" in the present technology, and the isolation insulating film 33 of the inter-pixel isolation region 31 corresponds to a specific example of "insulator" in the present technology.

[0171] In this modification 1-10, the same effects as those of the first embodiment described above can be obtained. In this modification 1-10, the gate electrode 55 is located closer to the insulator (the isolation insulating films 43 and 33) than the interface Lp in plan view, as a relative position between the gate electrode 55 and the interface Lp. However, this modification 1-10 can also be applied to a case where the gate electrode 55 crosses the interface Lp in plan view, as in the above modification 1-1, or a case where the gate electrode 55 is located closer to the semiconductor layer 21 than the interface Lp in plan view, as in modification 1-2.

[0172] 18A is a diagram showing Modification 1-11 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel. Fig. 18B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a18-a18 cutting line in Fig. 18A.

[0173] As shown in FIGS. 18A and 18B, this modification 1-11 differs from the above-described modification 1-5 in the configuration of one end side (photoelectric conversion portion 25 side) of the gate electrode 55.

[0174] That is, one end of the gate electrode 55 of this modified example 1-10, which is located closer to the second surface S2 of the semiconductor layer 21 than the step portion 36 of the insulator, extends from the side surface of the isolation insulating film 43 to the underside at the step portion 36 of the insulator. In other words, the width of the gate electrode 55 of this modified example 1-10 is wider at one end than the width of the portion located between the semiconductor layer 21 of the photoelectric conversion region 22 and the isolation insulating film 43 of the element isolation region 41. The gate electrode 55 having such a shape can be made by forming the gate electrode 55 and then forming the element isolation region 41.

[0175] In this modified example 1-11, the same effects as those of the above modified example 1-5 can be obtained.

[0176] <Modification 1-12> FIG. 19A is a diagram showing Modification 1-12 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel.

[0177] In Figure 19A, in order to make the drawing easier to understand, the pixel transistors Q (AMP, SEL, RST) shown in Figure 8A are omitted from the illustration, and the inter-element isolation region 41 is omitted from the illustration except for the region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in a planar view.

[0178] As shown in FIG. 19A, in this modification 1-12, in the above modification 1-1, the transfer transistor TR is arranged at the corner of the photoelectric conversion region 22 in plan view, and the planar shape of the gate electrode 55 is made L-shaped.

[0179] 19A, in this modification 1-12, a transfer transistor TR is provided on the edge side of a corner where a peripheral edge (side) extending in the X direction of the photoelectric conversion region 22 intersects with a peripheral edge (side) extending in the Y direction in a plan view. The gate electrode 55 of this transfer transistor TR is connected to a first portion 55Y extending in the Y direction. １ and a second portion 55X extending in the X direction. １ The photoelectric conversion region 22 has an L-shaped planar shape in which one end of the photoelectric conversion region 22 intersects with the corner of the photoelectric conversion region 22 .

[0180] The gate electrode 55 of this modification 1-12 has a first portion 55Y １and the second portion 55X １ are adjacent to the semiconductor layer 21 of the photoelectric conversion region 22 and the insulator (the isolation insulating films 43 and 33) and extend in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22 and the insulator (the isolation insulating films 43 and 33). １ and the second portion 55X １ Each of the lines is in the vertical direction A in a plan view. ２ First width W along １ is the horizontal direction A １ Second width W along ２ The gate electrode 55 of this modification 1-12 has a first portion 55Y １ and the second portion 55X １ Each of these crosses the interface portion Lp in plan view.

[0181] In this modified example 1-12, the same effects as those of the above modified example 1-1 can be obtained.

[0182] In this modification 1-12, the n-type floating diffusion region FD can be disposed at any position, but is preferably disposed in the vicinity of the gate electrode 55 as shown in FIG. １ The end surface in the X direction of the gate electrode 55 is the side surface 55c ３ and the first portion 55Y of the gate electrode 55 １ The Y-direction end surface of the gate electrode 55 is the side surface 55c of the gate electrode 55. ４ This becomes:

[0183] <Modification 1-13> FIG. 19B is a diagram showing Modification 1-13 according to the first embodiment of the present technology, and is a plan view schematically showing one pixel.

[0184] In addition, in order to make the drawing easier to understand, Figure 19B also omits the illustration of the pixel transistors Q (AMP, SEL, RST) shown in Figures 4A and 4B, and also omits the illustration of the inter-element isolation region 41 other than the region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in a planar view.

[0185] As shown in FIG. 19B, in this variant 1-13, in the above-mentioned variant 1-1, a transfer transistor TR extending across each of the two corners of the photoelectric conversion region 22 is arranged on one of the two peripheral portions located opposite each other in the X direction of the photoelectric conversion region 22 in a planar view, and the planar shape of the gate electrode 55 is made C-shaped.

[0186] The gate electrode 55 of this modification 1-13 has a first portion 55Y extending from one of two peripheral portions located opposite to each other in the X direction of the photoelectric conversion region 22 in a plan view to each of two corner portions located opposite to each other in the Y direction of the photoelectric conversion region 22. １１ And this first part 55Y １１ The second portion 55X extends in the X direction from one end side of the １２ and the first portion 55Y １１ a third portion 55X extending in the X direction from the other end side of the １３ The planar shape is a C-shape having the following features:

[0187] Although not shown in detail, the gate electrode 55 of this modified example 1-13 has a first portion 55Y １１ , second part 55X １２ and the third portion 55X １３ Each of these extends in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22 and the insulator (isolation insulating films 43 and 33), adjacent to the semiconductor layer 21 of the photoelectric conversion region 22 and the insulator (isolation insulating films 43 and 33).

[0188] The first portion 55Y of the gate electrode 55 of this modification 1-13 １１ , second part 55X １２ and the third portion 55X １３ Each of the lines is in the vertical direction A in a plan view. ２ First width W along １ is the horizontal direction A １ Second width W along ２ It is wider than.

[0189] The gate electrode 55 of this modification 1-13 has a first portion 55Y １１ , second part 55X １２ and the third portion 55X１３ Each of these crosses the interface Lp between the semiconductor layer 21 and the insulator (the isolation insulating films 43 and 33).

[0190] In this modified example 1-13, the same effects as those of the above modified example 1-1 can be obtained.

[0191] In this modification 1-13, the n-type floating diffusion region FD can be disposed at any position, but is preferably disposed in the vicinity of the gate electrode 55 as shown in FIG. １２ The end surface in the X direction of the gate electrode 55 is the side surface 55c ３ and the third portion 55X of the gate electrode 55 １３ The end surface in the X direction of the gate electrode 55 is the side surface 55c ４ This becomes:

[0192] <Other Modifications> In the above-described first embodiment and its modifications (1-1 to 1-9, 1-11, and 1-12), an insulator including the isolation insulating film 43 in the inter-element isolation region 41 and the isolation insulating film 33 in the inter-pixel isolation region 41 has been described, but the present technology is not limited to the insulators of the above-described first embodiment and its modifications.

[0193] 17A and 17B , in the case where the isolation region is an inter-pixel isolation region 31 extending across the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21, the present technology can also be applied to an insulator including the isolation insulating film 33 of the inter-pixel isolation region 31. In this case, the gate electrode 55 is configured to extend in the thickness direction (Z direction) of the semiconductor layer 21 between the semiconductor layer 21 of the photoelectric conversion region 22 and the inter-pixel isolation region 31, adjacent to the isolation insulating film 33 of the inter-pixel isolation region 31 and the semiconductor layer 21.

[0194] 4A and 6B , the present technology can also be applied to an isolation region other than a region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in a plan view, that is, when the inter-element isolation region 41 is present in a central portion away from the periphery of the photoelectric conversion region 22, to an insulator including the isolation insulating film 43 of the inter-element isolation region 41. In this case, the gate electrode 55 is configured to extend in the thickness direction (Z direction) of the semiconductor layer 21 between the semiconductor layer 21 of the photoelectric conversion region 22 and the inter-element isolation region 41, adjacent to the isolation insulating film 43 of the inter-element isolation region 41 and the semiconductor layer 21.

[0195] [Second Embodiment] In this second embodiment, an example in which the present technology is applied to a solid-state imaging device including phase difference pixels will be described. Fig. 20A is an equivalent circuit diagram schematically showing an example configuration of a pixel 3B and pixel circuits (15L, 15R) in a solid-state imaging device 1B according to a second embodiment of the present technology. Fig. 20B is a plan view schematically showing an example configuration of one pixel 3B in the solid-state imaging device 1B according to the second embodiment of the present technology. Fig. 20C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a20-a20 cutting line in Fig. 20B.

[0196] In Figures 20B and 20C, in order to make the drawings easier to see, the pixel transistors Q (AMP, SEL, RST) shown in Figures 4A and 4B are omitted, and the inter-element isolation region 41 is omitted from illustration except in the region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in plan view.

[0197] A solid-state imaging device 1B according to the second embodiment of the present technology basically has the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration.

[0198] That is, as shown in Figures 20A, 20B, and 20C, the solid-state imaging device 1B according to the second embodiment of the present technology includes a pixel 3B and a pixel circuit (15L, 15R) instead of the pixel 3 and the pixel circuit 15 shown in Figures 3, 4A, and 5A of the first embodiment described above.

[0199] As shown in FIGS. 3, 4A, and 5B, the pixel 3 of the first embodiment described above has a configuration in which one photoelectric conversion unit 25 is provided in one photoelectric conversion region 22.

[0200] 20A to 20C , a pixel 3B of the second embodiment has a configuration in which, for example, two photoelectric conversion units 25L and 25R are provided as multiple photoelectric conversion units in one photoelectric conversion region 22B. The pixel 3B of the second embodiment is a phase difference pixel that detects the phase difference between the two photoelectric conversion units 25L and 25R provided in one photoelectric conversion region 22B. The present technology can also be applied to a solid-state imaging device 1B including such a phase pixel (pixel 3B).

[0201] <Pixel> As shown in FIG. 20A, the pixel 3B includes a photoelectric conversion region 22B including two photoelectric conversion cells (a first photoelectric conversion cell 26L and a second photoelectric conversion cell 26R).

[0202] (Photoelectric conversion cell) The first photoelectric conversion cell 26L includes a photoelectric conversion unit 25L (PD1) that photoelectrically converts light into signal charges, a floating diffusion region FD1 that holds (accumulates) the signal charges photoelectrically converted by this photoelectric conversion unit 25L, and a transfer transistor TR1 that transfers the signal charges photoelectrically converted by this photoelectric conversion unit 25L to the floating diffusion region FD1.

[0203] Similarly, the second photoelectric conversion cell 26R also includes a photoelectric conversion unit 25R (PD2) that photoelectrically converts light into signal charges, a floating diffusion region FD2 that holds (accumulates) the signal charges photoelectrically converted by this photoelectric conversion unit 25R, and a transfer transistor TR2 that transfers the signal charges photoelectrically converted by this photoelectric conversion unit 25R to the floating diffusion region FD2.

[0204] 20A are each configured with, for example, a pn junction photodiode (PD1, PD2), similar to the photoelectric conversion unit 25 of the first embodiment described above. The photoelectric conversion units 25L and 25R generate signal charges corresponding to the amount of light received and temporarily store (accumulate) the generated signal charges. The cathode side of the photoelectric conversion unit 25L is electrically connected to the source region of the transfer transistor TR1, and the anode side is electrically connected to a reference potential line (e.g., ground). The cathode side of the photoelectric conversion unit 25R is electrically connected to the source region of the transfer transistor TR2, and the anode side is electrically connected to a reference potential line (e.g., ground).

[0205] (Transfer Transistor) The transfer transistor TR1 shown in FIG. 20A transfers signal charges photoelectrically converted by the photoelectric conversion unit 25L to the floating diffusion region FD1. The source region of the transfer transistor TR1 is electrically connected to the cathode side of the photoelectric conversion unit 25L, and the drain region is electrically connected to the floating diffusion region FD1. The gate electrode of the transfer transistor TR1 is electrically connected to a transfer transistor drive line among the pixel drive lines 10 shown in FIG. 2. The transfer transistor TR2 shown in FIG. 20A transfers signal charges photoelectrically converted by the photoelectric conversion unit 25R to the floating diffusion region FD2. The source region of the transfer transistor TR2 is electrically connected to the cathode side of the photoelectric conversion unit 25R, and the drain region is electrically connected to the floating diffusion region FD2. The gate electrode of the transfer transistor TR2 is electrically connected to a transfer transistor drive line among the pixel drive lines 10 shown in FIG. 2.

[0206] (Floating Diffusion Region) The floating diffusion region FD1 shown in Fig. 20A temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25L via the transfer transistor TR1. The floating diffusion region FD2 shown in Fig. 20A temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25R via the transfer transistor TR2.

[0207] 20A, the pixel circuit 15L has an input stage electrically connected to the floating diffusion region FD1 of the first photoelectric conversion cell 26L. The pixel circuit 15L reads out the signal charges held in the floating diffusion region FD1 and outputs a pixel signal based on the read-out signal charges. In other words, the pixel circuit 15L converts the signal charges photoelectrically converted by the photoelectric conversion unit 25L (photodiode PD1) into a pixel signal based on these signal charges and outputs the pixel signal.

[0208] 20A, the pixel circuit 15R has an input stage electrically connected to the floating diffusion region FD2 of the second photoelectric conversion cell 26R. The pixel circuit 15R reads out the signal charges held in the floating diffusion region FD2 and outputs a pixel signal based on the read-out signal charges. In other words, the pixel circuit 15R converts the signal charges photoelectrically converted by the photoelectric conversion unit 25R (photodiode PD2) into a pixel signal based on the signal charges and outputs the pixel signal.

[0209] In this second embodiment, as an example, pixel circuits 15L and 15R are assigned separately to each of two photoelectric conversion cells 26L and 26R, and a driving method is used in which the signal charge held in the floating diffusion region FD1 of the first photoelectric conversion cell 26L and the signal charge held in the floating diffusion region FD2 of the second photoelectric conversion cell 26R are read out separately.

[0210] 20A has a configuration similar to that of the pixel circuit 15 of the first embodiment shown in FIG. 3, although not limited thereto. That is, each of the two pixel circuits 15L and 15R of the second embodiment includes, as pixel transistors Q, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. Furthermore, in each of the two pixel circuits 15L and 15R, the connection state of the pixel transistors Q is also similar to that of the pixel circuit 15 of the first embodiment, and therefore a description thereof will be omitted in the second embodiment.

[0211] However, as shown in FIG. 20A, the source region of the select transistor SEL1 included in the first photoelectric conversion cell 26L is electrically connected to the vertical signal line 11L (VSL1), and the source region of the select transistor SEL2 included in the second photoelectric conversion cell 26R is electrically connected to a vertical signal line 11R (VSL2) different from the vertical signal line 11L (VSL1).

[0212] 20B and 20C , the photoelectric conversion region 22B is provided in the semiconductor layer 21, similar to the photoelectric conversion region 22 of the first embodiment described above. Similarly to the photoelectric conversion region 22 of the first embodiment described above, the photoelectric conversion region 22B is surrounded by an inter-element isolation region 41 and an inter-pixel isolation region 31 in a planar view (a planar view when the semiconductor layer 21 is viewed from the thickness direction of the semiconductor layer 21), and has a rectangular planar shape. The photoelectric conversion region 22B has an internal isolation barrier 37 extending in the thickness direction (Z direction) of the semiconductor layer 21, and two photoelectric conversion cells (a first photoelectric conversion cell 26L and a second photoelectric conversion cell 26R) separated by the internal isolation barrier 37.

[0213] (Photoelectric Conversion Cell) As shown in Figures 20B and 20C, the first photoelectric conversion cell 26L has a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion unit 25L, a transfer transistor TR1, an n-type floating diffusion region FD1, and a p-type power supply contact region WC1, similar to the photoelectric conversion region 22 of the first embodiment described above. Similarly, the second photoelectric conversion cell 26R also has a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion unit 25R, a transfer transistor TR2, an n-type floating diffusion region FD2, and a p-type power supply contact region WC2, similar to the photoelectric conversion region 22 of the first embodiment described above. Each of the transfer transistors TR1 and TR2 has the same configuration as the transfer transistor TR of the first embodiment described above. Each of the p-type power supply contact regions WC1 and WC2 has the same configuration as the p-type power supply contact region WC of the first embodiment described above.

[0214] 20B and 20C , the internal isolation barrier 37 extends along the Y direction in plan view and is connected to the middle portions of two isolation regions (the inter-element isolation region 41 and the inter-pixel isolation region 31) located on the outer sides of the photoelectric conversion region 22B in the Y direction. The internal isolation barrier 37 is disposed between the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R, and electrically and optically separates the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R. That is, the photoelectric conversion region 22B is separated into the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R by the internal isolation barrier 37 extending along the Y direction.

[0215] The internal isolation barrier 37 includes an isolation insulating film 43 formed in the same process as the isolation insulating film 43 of the inter-element isolation region 41, and an isolation insulating film 33 formed in the same process as the isolation insulating film 33 of the inter-pixel isolation region 31. In other words, the internal isolation barrier 37 can be regarded as an insulator including the isolation insulating films 43 and 33.

[0216] Here, looking at the configuration of the internal separation barrier 37 from another perspective, the internal separation barrier 37 protrudes from one of the two separation regions located on opposite sides of the photoelectric conversion region 22B in a planar view toward the other separation region, and is integrated with this other separation region.

[0217] 20B and 20C , the transfer transistor TR1 is provided in the peripheral portion opposite the internal isolation barrier 37 of the first photoelectric conversion cell 26L. In other words, the transfer transistor TR1 is provided in the peripheral portion on the first photoelectric conversion cell 26L side of both sides of the photoelectric conversion region 22B in the X direction. As shown in FIGS. 20B and 20C , the transfer transistor TR2 is provided in the peripheral portion on the second photoelectric conversion cell 26R side of the internal isolation barrier 37. In other words, the transfer transistor TR2 is provided in the peripheral portion on the second photoelectric conversion cell 26R side of both sides of the photoelectric conversion region 22B in the X direction. That is, the transfer transistors TR1 and TR2 are each spaced apart from the internal isolation barrier 37 in the X direction and are disposed facing each other across the internal isolation barrier 37 and the two photoelectric conversion cells 26L and 26R.

[0218] Like the transfer transistor TR of the first embodiment described above, each of the transfer transistors TR1 and TR2 has a gate electrode 55 extending in the thickness direction (Z direction) of the semiconductor layer 21 between the semiconductor layer 21 of the photoelectric conversion region 22B and the insulators (isolation insulating films 43 and 33) and adjacent to each of the semiconductor layer 21 and the insulators (isolation insulating films 43 and 33). Each of the transfer transistors TR1 and TR2 also has a gate insulating film 52 interposed between the gate electrode 55 and the semiconductor layer 21. Each of the transfer transistors TR1 and TR2 also has a p-type well region 23 functioning as a channel formation portion where a channel is formed, and n-type floating diffusion regions FD1 and FD2 and an n-type semiconductor region 24 functioning as a source region and a drain region. As shown in Figures 20B and 20C, the gate electrodes 55 of each of the transfer transistors TR1 and TR2 cross the interface Lp between the semiconductor layer 21 of the photoelectric conversion region 22B and the insulator (isolation insulating films 43 and 33) in a planar view, similar to the gate electrodes 55 of the above-mentioned variant example 1-1.

[0219] 20C , similarly to the first embodiment, a microlens 64a of the lens layer 64 is provided for each pixel 3 (each photoelectric conversion region 22B). That is, in the photoelectric conversion region 22B, one microlens 64a is shared by two photoelectric conversion cells (first and second photoelectric conversion cells 26L and 26R).

[0220] 20B and 20C , the n-type floating diffusion region FD1 and the p-type power supply contact region WC1 are each provided in the first photoelectric conversion cell 26L of the photoelectric conversion region 22B. The n-type floating diffusion region FD1 is provided at a corner where one of two sides of the first photoelectric conversion cell 26L located opposite to each other in the Y direction intersects with the internal isolation barrier 37. The p-type power supply contact region WC1 is provided at a corner where the other of two sides of the first photoelectric conversion cell 26L located opposite to each other in the Y direction intersects with the internal isolation barrier 37.

[0221] 20B and 20C , the n-type floating diffusion region FD2 and the p-type power supply contact region WC2 are each provided in the second photoelectric conversion cell 26R of the photoelectric conversion region 22B. The n-type floating diffusion region FD2 is provided at a corner where one of two sides located opposite to each other in the Y direction of the first photoelectric conversion cell 26L intersects with the internal isolation barrier 37. The p-type power supply contact region WC2 is provided at a corner where the other of two sides located opposite to each other in the Y direction of the second photoelectric conversion cell 26R intersects with the internal isolation barrier 37.

[0222] 20B and 20C , the n-type floating diffusion regions FD1 and FD2 and the p-type power supply contact regions WC1 and WC2 are spaced apart in the Y direction. The n-type floating diffusion regions FD1 and FD2 are adjacent to each other in the X direction with the internal isolation barrier 37 interposed therebetween. The p-type power supply contact regions WC1 and WC2 are also adjacent to each other in the X direction with the internal isolation barrier 37 interposed therebetween.

[0223] That is, each of the n-type floating diffusion regions FD1 and FD2 is provided on one of the two isolation regions (upper side in FIG. 20B ) located on both sides of the photoelectric conversion region 22B in the Y direction in plan view, and is provided adjacent to each other on this one isolation region side with the internal isolation barrier 37 interposed therebetween. Also, each of the p-type power supply contact regions WC1 and WC2 is provided on the other of the two isolation regions (lower side in FIG. 20B ) located on both sides of the photoelectric conversion region 22B in the Y direction in plan view, and is provided adjacent to each other on this other isolation region side with the internal isolation barrier 37 interposed therebetween.

[0224] <Autofocus> In an electronic device equipped with the solid-state imaging device 1B of this second embodiment, the signal charges of the two photoelectric conversion units 25L and 25R provided in one photoelectric conversion region 22B are read out for each pixel 3B, and the phase difference is detected.

[0225] When the focus is correct, there is no difference in the amount of signal charge accumulated in photoelectric conversion unit 25L and photoelectric conversion unit 25R. In contrast, when the focus is not correct, there is a difference between the amount of signal charge Q1 accumulated in photoelectric conversion unit 25L and the amount of signal charge Q2 accumulated in photoelectric conversion unit 25R. When the focus is not correct, the electronic device performs an operation such as moving the objective lens so that Q1 and Q2 coincide with each other. This is autofocus.

[0226] <Flow of Signal Charge> In the photoelectric conversion region 22B of the second embodiment, the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R are separated by an internal isolation barrier 37 in the Y and Z directions of the photoelectric conversion region 22B. Even in this case, each of the first and second photoelectric conversion cells 26L, 26R can independently accumulate signal charge up to the height of the potential barrier. When the height of the potential barrier is exceeded, signal charge flows from the photoelectric conversion unit 25L to the floating diffusion region FD1 in the first photoelectric conversion cell 26L, and signal charge flows from the photoelectric conversion unit 25R to the floating diffusion region DF2 in the second photoelectric conversion cell 26R.

[0227] <<Main effects of the second embodiment>> Each of the transfer transistors TR1 and TR2 of the second embodiment has a gate electrode 55 that extends in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22B and the insulator (isolation insulating films 43 and 33), adjacent to the semiconductor layer 21 of the photoelectric conversion region 22B and the insulator (isolation insulating films 43 and 33).

[0228] In addition, in a plan view of the semiconductor layer 21 viewed from the thickness direction (Z direction) of the semiconductor layer 21, a direction crossing the interface Lp between the semiconductor layer 21 and the insulator (the isolation insulating films 43 and 33) is referred to as a lateral direction A. １ The direction intersecting with the horizontal direction Lp is the vertical direction A ２ When the gate electrode 55 of the second embodiment is also ２ First width W along １ is the horizontal direction A １ The second W along ２ It is wider than.

[0229] In addition, the side surface 55c of the gate electrode 55 of the second embodiment１ The sidewall surface portions 21a of the semiconductor layer 21 adjacent to each other have a silicon crystal orientation of the (100) plane.

[0230] Therefore, the solid-state imaging device 1B according to the second embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

[0231] <<Modification of Second Embodiment>> Next, a modification of the second embodiment will be described.

[0232] <Modification 2-1> Fig. 21A is a diagram showing Modification 2-1 according to the second embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel. Fig. 21B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a21-a21 cutting line in Fig. 21A. Fig. 21C is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the b21-b21 cutting line in Fig. 21A.

[0233] 21A to 21C, in this modification 2-1, instead of the internal isolation barrier 37 shown in Figures 20A and 20B of the second embodiment, an internal isolation barrier 38 is provided. In this modification 2-1, the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R share one n-type floating diffusion region FD.

[0234] As shown in Figures 21A to 21C, the internal isolation barrier 38 extends in both the Z and Y directions in the photoelectric conversion region 22B, similar to the internal isolation barrier 37 of the second embodiment. The internal isolation barrier 38 protrudes from one of two isolation regions (one and the other including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on either side of the photoelectric conversion region 22B in the Y direction in a plan view toward the other isolation region and is integrated with the other isolation region. The internal isolation barrier 38 is recessed from the first surface S1 side toward the second surface S2 side of the semiconductor layer 21 and has a recess 38a connecting the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R. That is, the height of the internal isolation barrier 38 of the second embodiment along the thickness direction (Z direction) of the semiconductor layer 21 is lowered by one step in the region of the recess 38a. The recess 38a is provided in the middle of the internal separation barrier 38 in the Y direction, for example, but is not limited to this.

[0235] The internal isolation barrier 38 is mainly made of an insulator including the isolation insulating film 33 in the region where the recess 38a is provided, and is mainly made of an insulator including the isolation insulating film 43 and the isolation insulating film 33 in the region excluding the recess 38a. Therefore, the recess 38a can be easily formed by selectively not forming a part of the isolation insulating film 43.

[0236] 21A to 21C , the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R are physically separated by an internal isolation barrier 38 and are connected to each other by a recess 38a of the internal isolation barrier 38. The p-type well region 23 of the first photoelectric conversion cell 26L and the p-type well region 23 of the second photoelectric conversion cell 26R are separated by the internal isolation barrier 38 and are integrated together by the recess 38a of the internal isolation barrier 38.

[0237] 21A to 21C, the n-type floating diffusion region FD is provided in the p-type well region 23 in the recess 38a of the internal isolation barrier 38. The n-type floating diffusion region FD is shared by the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R.

[0238] In this modification 2-1, the first and second photoelectric conversion cells 26L and 26R can also independently store signal charges up to the height of the potential barrier. When the height of the potential barrier is exceeded, the signal charges flow from the photoelectric conversion unit 25L to the floating diffusion region FD in the first photoelectric conversion cell 26L, and the signal charges flow from the photoelectric conversion unit 25R to the floating diffusion region DF in the second photoelectric conversion cell 26R.

[0239] In this modified example 2-1, the same effects as those of the second embodiment described above can be obtained.

[0240] 22A is a diagram showing Modification 2-2 according to the second embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel. Fig. 22B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a22-a22 cutting line in Fig. 22A.

[0241] As shown in FIGS. 22A and 22B, this modification 2-2 is obtained by changing the arrangement of the floating diffusion region in the above modification 2-1.

[0242] That is, as shown in FIGS. 21A and 21B, in the above-described modified example 2-1, the n-type floating diffusion region FD shared by the two photoelectric conversion cells 26L and 26R is provided in the recess 38a of the internal isolation barrier 38.

[0243] In contrast, as shown in Figures 22A and 22B, in this variant 2-2, as in the first embodiment described above, an n-type floating diffusion region FD1 is provided in the first photoelectric conversion cell 26L, and an n-type floating diffusion region FD2 is provided in the second photoelectric conversion cell 26R.

[0244] The floating diffusion region FD1 of the first photoelectric conversion cell 26L and the floating diffusion region FD2 of the second photoelectric conversion cell 26R are provided on one of the two isolation regions (upper side in Figure 22A) located on opposite sides of each other in the Y direction across the photoelectric conversion region 22B in a planar view, and are adjacent to each other on this one isolation region side via an internal isolation barrier 38.

[0245] In this modification 2-2, the p-type well regions 23 of the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R are connected by the recess 38a of the internal isolation barrier 38. Therefore, in this modification 2-2, the p-type well region 23 in the recess 38a of the internal isolation barrier 38 functions as an overflow path.

[0246] A first potential barrier can be formed in the well region 23 of the recess 38 a. The transfer transistor TR1 of the first photoelectric conversion cell 26L can form a second potential barrier higher than the first potential barrier when not transferring signal charges from the photoelectric conversion unit 25L to the floating diffusion region FD1. Furthermore, the transfer transistor TR2 of the second photoelectric conversion cell 26R can form a second potential barrier higher than the first potential barrier when not transferring signal charges from the photoelectric conversion unit 25R to the floating diffusion region FD2.

[0247] The photoelectric conversion units 25L, 25R of the first and second photoelectric conversion cells 26L, 26R can independently accumulate signal charges up to the height of the first potential barrier. When the amount of accumulated signal charges exceeds the height of the first potential barrier, the signal charges flow from one of the photoelectric conversion units 25L, 25R of the first and second photoelectric conversion cells 26L, 26R to the other via the overflow path in the recess 38a of the internal isolation barrier 38.

[0248] As described above, the internal separation barrier 38 of this variant 2-2 protrudes from one of the two separation regions located on opposite sides of the photoelectric conversion region 22B in a planar view toward the other separation region, is integrated with the other separation region, and has a recess 38a connecting the first photoelectric conversion cell 26L and the second photoelectric conversion cell 26R.

[0249] In this modified example 2-2, the same effects as those of the second embodiment described above can be obtained.

[0250] <Modification 2-3> Fig. 23A is a diagram showing Modification 2-3 according to the second embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel. Fig. 23B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a23-a23 cutting line in Fig. 23A. Fig. 23C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b23-b23 cutting line in Fig. 23A.

[0251] 23A to 23C , in Modification 2-3, the position of the recess 38a of the internal isolation barrier 38 and the positions of the power supply contact regions WC1 and WC2 are changed in the above-described Modification 2-2. That is, in the above-described Modification 2-2, as shown in FIGS. 22A and 22B , the recess 38a of the internal isolation barrier 38 is provided in the middle of the internal isolation barrier 38 in the Y direction. The floating diffusion region FD1 of the first photoelectric conversion cell 26L and the floating diffusion region FD2 of the second photoelectric conversion cell 26R are provided on one of two isolation regions (one and the other isolation regions including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on both sides of the photoelectric conversion region 22B in the Y direction, and are arranged adjacent to each other in the X direction on this one isolation region side with the internal isolation barrier 38 interposed therebetween. The power supply contact region WC1 of the first photoelectric conversion cell 26L and the power supply contact region WC2 of the second photoelectric conversion cell 26R are provided on the other of the two isolation regions (one and the other isolation region including the inter-element isolation region 43 and the inter-pixel isolation region 33) located on both sides of the photoelectric conversion region 22B in the Y direction, and are arranged adjacent to each other in the X direction on this other isolation region side via the internal isolation barrier 38.

[0252] 23A, 23B, and 23C, in this modification 2-3, the recess 38a of the internal isolation barrier 38 is provided on the other isolation region side of the two isolation regions (one and the other isolation regions including the inter-element isolation region 43 and the inter-pixel isolation region 33) located on both sides of the photoelectric conversion region 22B in the Y direction. The power supply contact region WC1 of the first photoelectric conversion cell 26L is provided at a corner where the other isolation region of the two isolation regions (one and the other isolation regions including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on both sides of the photoelectric conversion region 22B in the Y direction intersects with one isolation region of the two isolation regions (one and the other isolation regions including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on both sides of the photoelectric conversion region 22B in the X direction. The power supply contact region WC2 of the first photoelectric conversion cell 26R is provided at the corner where the other of the two isolation regions (one and the other isolation regions including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on both sides of the photoelectric conversion region 22B in the Y direction intersects with the other of the two isolation regions (one and the other isolation region including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on both sides of the photoelectric conversion region 22B in the X direction.

[0253] As in the above-mentioned variant 2-2, the floating diffusion regions FD1 and FD2 of variant 2-3 are provided on one of the two isolation regions located on both sides of the photoelectric conversion region 22B in the Y direction, and are adjacent to each other in the X direction on this one isolation region side via an internal isolation barrier.

[0254] In this modified example 2-3, the same effects as those of the second embodiment can be obtained.

[0255] <Modification 2-4> FIG. 24A is a diagram showing Modification 2-4 according to the second embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel.

[0256] FIG. 24B is a longitudinal cross-sectional view schematically showing the longitudinal cross-sectional structure taken along the a24-a24 cutting line in FIG. 24A.

[0257] As shown in FIGS. 24A and 24B, in this modified example 2-4, the internal dividing barrier 38 in the modified example 2-3 is replaced with an internal separating barrier 39.

[0258] 24A and 24B , the internal isolation barrier 39 of this modification 2-4 protrudes from one of two isolation regions (one and the other isolation regions including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on opposite sides in the Y direction with the photoelectric conversion region 22B in between in a plan view toward the other isolation region, and is spaced apart from the other isolation region. The space between the internal isolation barrier 39 and the other isolation region forms an overflow path.

[0259] In this modified example 2-4, the same effects as those of the second embodiment described above can be obtained.

[0260] 25 is a diagram illustrating a modification 2-5 according to the second embodiment of the present technology, and is a plan view schematically illustrating a configuration example of one pixel. As shown in Fig. 25, in modification 2-3 described above, modification 2-5 is configured such that one floating diffusion region FD shared by two photoelectric conversion cells 26L and 26R is provided in a recess 38a of the internal isolation barrier 38.

[0261] In this modified example 2-5, the same effects as those of the second embodiment described above can be obtained.

[0262] 26A is a diagram showing Modification 2-6 according to the second embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel. Fig. 26B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a26-a26 cutting line in Fig. 26A.

[0263] As shown in Figures 26A and 26B, this variant 2-6 is the same as the second embodiment described above, except that a transfer transistor TR1 is also provided on the internal isolation barrier 37 side of the first photoelectric conversion cell 26L, and a transfer transistor TR2 is also provided on the internal isolation barrier 37 side of the second photoelectric conversion cell 26R.

[0264] 26A and 26B , the two transfer transistors TR1 of the first photoelectric conversion cell 26L are arranged facing each other in the X direction. The transfer transistor TR1 located on the internal isolation barrier 37 side of the photoelectric conversion cell 26L has the same configuration as the transfer transistor TR1 located on the opposite side to the internal isolation barrier 37 side of the photoelectric conversion cell 26.

[0265] That is, the transfer transistor TR1 located on the internal isolation barrier 37 side of the first photoelectric conversion cell 26L also has a gate electrode 55 that is adjacent to the semiconductor layer 21 of the photoelectric conversion region 22B and the insulator (isolation insulating films 43 and 33) and extends in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22B and the insulator (isolation insulating films 43 and 33). ２ First width W along １ is the horizontal direction A １ Second width W along ２ and crosses the interface portion Lp in plan view.

[0266] The transfer transistor TR2 located on the internal isolation barrier 37 side of the second photoelectric conversion cell 26R also has a gate electrode 55 that is adjacent to the semiconductor layer 21 of the photoelectric conversion region 22B and the insulator (isolation insulating films 43 and 33) and extends in the thickness direction (Z direction) of the semiconductor layer 21 between the photoelectric conversion region 22B and the insulator (isolation insulating films 43 and 33). The gate electrode 55 of the transfer transistor TR2 located on the internal isolation barrier 37 side of the second photoelectric conversion cell 26R also extends in the vertical direction A in plan view. ２ First width W along １ is the horizontal direction A １ Second width W along ２ and crosses the interface portion Lp in plan view.

[0267] In this modified example 2-6, the same effects as those of the second embodiment described above can be obtained.

[0268] Furthermore, in this variant 2-6, two transfer transistors TR1 are provided in the photoelectric conversion cell 26L, and two transfer transistors TR2 are provided in the photoelectric conversion cell 26R, thereby improving the transfer efficiency of transferring the signal charges photoelectrically converted in the photoelectric conversion units 25L and 25R of the two photoelectric conversion cells 26L and 26R to the floating diffusion region FD.

[0269] 27A is a diagram showing Modification 2-7 according to the second embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel. Fig. 27B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a27-a27 cutting line in Fig. 27A.

[0270] As shown in Figures 27A and 27B, this variant 2-7 is a variant 2-6 described above in which the gate electrode 55 of the transfer transistor TR1 located on the internal isolation barrier 37 side of the first photoelectric conversion cell 26L and the gate electrode 55 of the transfer transistor TR2 located on the internal isolation barrier 37 side of the second photoelectric conversion cell 26R are shared.

[0271] In this modified example 2-7, the same effects as those of the above modified example 2-6 can be obtained.

[0272] <Modification 2-8> FIG. 28 is a diagram showing Modification 2-8 according to the second embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel.

[0273] As shown in Figure 28, this variant 2-8 is the same as the variant 2-2 described above, except that a transfer transistor TR1 is also provided on the internal isolation barrier 38 side of the first photoelectric conversion cell 26L, and a transfer transistor TR2 is also provided on the internal isolation barrier 38 side of the second photoelectric conversion cell 26R.

[0274] In this modification 2-8, each of the two transfer transistors TR1 and the two transfer transistors TR2 is provided on the other isolation region side (lower side in FIG. 28A ) of two isolation regions (one and the other isolation regions including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on both sides of the photoelectric conversion region 22B in the Y direction in plan view. The power supply contact region WC1 of the first photoelectric conversion cell 26L is disposed between the two transfer transistors TR1 on the other isolation region side (lower side in FIG. 28A ) of the two isolation regions (one and the other isolation regions including the inter-element isolation region 41 and the inter-pixel isolation region 31) located on both sides of the photoelectric conversion region 22B in the Y direction in plan view. The power supply contact region WC2 of the second photoelectric conversion cell 26R is arranged between the two transfer transistors TR2 on the side of the other of the two isolation regions located on both sides of the photoelectric conversion region 22B in the Y direction when viewed in a plane (the lower side in Figure 28A).

[0275] In this modification 2-8, the same effects as those of the above-mentioned modification 2-6 can be obtained.

[0276] <Modification 2-9> FIG. 29 is a diagram showing Modification 2-9 according to the second embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel.

[0277] As shown in Figure 29, this variant 2-9 is the same as the variant 2-3 described above, except that a transfer transistor TR1 is also provided on the internal isolation barrier 38 side of the first photoelectric conversion cell 26L, and a transfer transistor TR2 is also provided on the internal isolation barrier 38 side of the second photoelectric conversion cell 26R.

[0278] In this modification 2-9, the same effect as in the above modification 2-6 can be obtained.

[0279] 30 is a diagram illustrating a modification 2-10 according to the second embodiment of the present technology, and is a plan view schematically illustrating one configuration example of one pixel. As shown in Fig. 30, in this modification 2-10, in the above-described modification 2-3, the gate electrodes 55 of the transfer transistors TR1 and TR2 are each formed into an L-shaped planar shape.

[0280] In this modified example 2-10, the same effects as those of the modified example 2-2 can be obtained.

[0281] 31 is a diagram illustrating a modification 2-11 according to the second embodiment of the present technology, and is a plan view schematically illustrating a configuration example of one pixel. As shown in Fig. 31, in this modification 2-11, in the above-described modification 2-1, the gate electrodes 55 of the transfer transistors TR1 and TR2 are each formed into a C-shaped planar shape.

[0282] In this modification 2-1, the same effects as those of the above-mentioned modification 2-3 can be obtained.

[0283] [Third Embodiment] In this third embodiment, an example in which the present technology is applied to a solid-state imaging device 1C having a transfer transistor with a horizontal structure will be described. Fig. 32A is a plan view schematically showing an example of the configuration of one pixel in a solid-state imaging device according to the third embodiment of the present technology. Fig. 32B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a32-a32 cutting line in Fig. 32A.

[0284] As shown in Figures 32A and 32B, the solid-state imaging device 1C of the third embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1B of the second embodiment described above, with the following differences in configuration.

[0285] 32A and 32B , a solid-state imaging device 1C according to the third embodiment of the present technology includes transfer transistors TRL1 and TRL2 having a horizontal structure instead of the transfer transistors TR1 and TR2 having a vertical structure shown in FIGS. 20B and 20C of the second embodiment. Other configurations are generally similar to those of the second embodiment.

[0286] As shown in Figures 32A and 32B, the transfer transistor TRL1 is provided on the edge side opposite the internal isolation barrier 37 side of the first photoelectric conversion cell 26L. In other words, the transfer transistor TRL1 is provided on one of the two edges of the photoelectric conversion region 22B in the X direction, on the edge side closer to the first photoelectric conversion cell 26L. As shown in Figures 32A and 32B, the transfer transistor TRL2 is provided on the edge side opposite the internal isolation barrier 37 side of the second photoelectric conversion cell 26R. In other words, the transfer transistor TRL2 is provided on one of the two edges of the photoelectric conversion region 22B in the X direction, on the edge side closer to the second photoelectric conversion cell 26R. That is, the transfer transistors TRL1 and TRL2 are each spaced apart from the internal isolation barrier 37 in the X direction and are disposed facing each other across the internal isolation barrier 37 and the two photoelectric conversion cells 26L and 26R.

[0287] Each of the transfer transistors TRL1 and TRL2 has a gate electrode 58 provided across the semiconductor layer 21 and the isolation region (inter-element isolation region 41) in a planar view outside the first surface portion S1 of the semiconductor layer 21. In other words, each of the transfer transistors TRL1 and TRL2 has a gate electrode 58 provided across the semiconductor layer 21 and the insulator (isolation insulating film 43) in a planar view outside the first surface portion S1 of the semiconductor layer 21. The isolation region includes the inter-element isolation insulating film 43 as an insulator.

[0288] Each of the transfer transistors TRL1 and TRL2 further includes a gate insulating film 52 interposed between the gate electrode 58 and the semiconductor layer 21. Each of the transfer transistors TRL1 and TRL2 further includes a p-type well region 23 functioning as a channel formation portion where a channel is formed, and n-type floating diffusion regions (FD1, FD2) and an n-type semiconductor region 24 functioning as a source region and a drain region. Each of the transfer transistors TRL1 and TRL2 has a planar structure in which the gate electrode 58 extends in a quadratic manner outside the first surface portion S1 of the semiconductor layer 21.

[0289] The gate electrode 58 is provided outside the first surface S1 of the semiconductor layer 21, spanning the semiconductor layer 21 and the isolation region (inter-element isolation region 41) in plan view. That is, a portion of the gate electrode 58 overlaps the isolation region (inter-element isolation region 41). Such a gate electrode 58 can be formed in the manufacturing process of the solid-state imaging device by depositing, for example, a polycrystalline silicon film as a gate electrode material on the first surface S1 side of the semiconductor layer 21, and then selectively etching and patterning this polycrystalline silicon film.

[0290] In this patterning step, the polycrystalline silicon film is etched on the isolation region (inter-element isolation region 41) so that the gate electrode 58 remains across the semiconductor layer 21 and the isolation region (inter-element isolation region 41), in other words, so that a portion of the gate electrode 58 overlaps the isolation region (inter-element isolation region 41), thereby reducing etching damage to the semiconductor layer 21. That is, by providing the gate electrode 58 outside the first surface portion S1 of the semiconductor layer 21 and across the semiconductor layer 21 and the isolation region (inter-element isolation region 41) in a planar view, etching damage to the semiconductor layer 21 can be reduced. Because this etching damage affects the transistor characteristics, reducing the etching damage can improve the manufacturing yield of the solid-state imaging device 1C and the performance of the solid-state imaging device 1C.

[0291] Furthermore, if the gate electrode 58 is spaced apart from the isolation region (inter-element isolation region 41) as in the conventional case, variations in the distance between the isolation region (inter-element isolation region 41) and the gate electrode 58 occur, which makes it easier for variations in the signal charge transfer characteristics to occur between the photoelectric conversion region 22B (pixel 3) and between the photoelectric conversion cells (26L, 26R). In contrast, in the third embodiment, the gate electrode 58 is provided outside the first surface portion S1 of the semiconductor layer 21, spanning the semiconductor layer 21 and the isolation region (inter-element isolation region 41) in a planar view. This reduces variations in the distance between the isolation region (inter-element isolation region 41) and the gate electrode 58, making it possible to reduce variations in the signal charge transfer characteristics that occur between the photoelectric conversion region 22B (pixel 3) and between the photoelectric conversion cells (26L, 26R). Since this variation in the transfer characteristics of signal charge affects the performance and manufacturing yield of the solid-state imaging device 1C, by reducing the variation in the transfer characteristics of signal charge, it is possible to improve the manufacturing yield of the solid-state imaging device 1C and the performance of the solid-state imaging device 1C.

[0292] <<Major Effects of the Third Embodiment>> The solid-state imaging device 1C according to the third embodiment can improve yield and performance. Note that, in the third embodiment, the gate electrode 58 is described as being provided on the outside of the first surface S1 of the semiconductor layer 21, spanning the semiconductor layer 21 and the isolation region (inter-element isolation region 41) in a planar view, but in a case where the inter-pixel isolation region 31 extends to match the first surface S1 and the second surface S2 of the semiconductor layer, the gate electrode 58 is provided on the outside of the first surface S1 of the semiconductor layer 21, spanning the semiconductor layer 21 and the isolation region (inter-pixel region 31) in a planar view.

[0293] <<Modification of Third Embodiment>> Next, a modification of the third embodiment will be described.

[0294] 33A is a diagram showing Modification 3-1 according to the third embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel. Fig. 33B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a33-a33 cutting line in Fig. 33A.

[0295] As shown in Figures 33A and 33B, this modification 3-1 is modification 2-1 shown in Figures 21A and 21B above, in which the transfer transistors TR1 and TR2 having a vertical structure of the third embodiment are applied instead of the transfer transistors TR1 and TR2 having a vertical structure.

[0296] Also in this modification 3-1, each of the transfer transistor TRL1 and the transfer transistor TRL2 has a gate electrode 58 provided outside the first surface portion S1 of the semiconductor layer 21, spanning the semiconductor layer 21 and the inter-element isolation region 41 in plan view. In other words, also in this modification 3-1, each of the transfer transistor TRL1 and the transfer transistor TRL2 has a gate electrode 58 provided outside the first surface portion S1 of the semiconductor layer 21, spanning the semiconductor layer 21 and the isolation region (inter-element isolation region 41) in plan view. Therefore, also in this modification 3-1, the same effects as in the third embodiment described above can be obtained.

[0297] 34A is a diagram showing Modification 3-2 according to the third embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel. Fig. 34B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a34-a34 cutting line in Fig. 34A.

[0298] As shown in Figures 34A and 34B, this modification 3-2 is modification 2-2 shown in Figures 22A and 22B above, in which the transfer transistors TR1 and TR2 having a vertical structure of the third embodiment are applied instead of the transfer transistors TR1 and TR2 having a horizontal structure.

[0299] In this modification 3-2 as well, each of the transfer transistor TRL1 and the transfer transistor TRL2 has a gate electrode 58 provided across the semiconductor layer 21 and the isolation region (inter-element isolation region 41) in plan view outside the first surface portion S1 of the semiconductor layer 21. In other words, each of the transfer transistor TRL1 and the transfer transistor TRL2 has a gate electrode 58 provided across the semiconductor layer 21 and the insulator (isolation insulating film 43) in plan view outside the first surface portion S1 of the semiconductor layer 21. Therefore, in this modification 3-2 as well, the same effects as those of the third embodiment described above can be obtained.

[0300] 35A is a diagram showing Modification 3-3 according to the third embodiment of the present technology, and is a plan view schematically showing one configuration example of one pixel. Fig. 35B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a35-a35 cutting line in Fig. 35A.

[0301] As shown in Figures 35A and 35B, this modification 3-3 is modification 2-3 shown in Figures 23A and 23B above, in which the transfer transistors TR1 and TR2 having a vertical structure of the third embodiment are applied instead of the transfer transistors TR1 and TR2 having a horizontal structure.

[0302] In this modification 3-3 as well, each of the transfer transistor TRL1 and the transfer transistor TRL2 has a gate electrode 58 provided across the semiconductor layer 21 and the isolation region (inter-element isolation region 41) in plan view outside the first surface portion S1 of the semiconductor layer 21. In other words, each of the transfer transistor TRL1 and the transfer transistor TRL2 has a gate electrode 58 provided across the semiconductor layer 21 and the insulator (isolation insulating film 43) in plan view outside the first surface portion S1 of the semiconductor layer 21. Therefore, in this modification 3-3 as well, the same effects as those of the third embodiment described above can be obtained.

[0303] <Other Modifications> In the above-described third embodiment and modifications 3-1 to 3-3, the case where the gate electrode 58 is provided as an isolation region in a region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in a planar view has been described. However, the present technology is not limited to the above-described third embodiment.

[0304] For example, referring to Figures 32A and 32B, if an inter-pixel isolation region 31 extending across the first surface S1 and the second surface S2 of the semiconductor layer 21 exists as an isolation region, a gate electrode 58 may be provided across this inter-pixel isolation region 31 and the semiconductor layer 21.

[0305] Also, referring to Figures 32A and 32B, if the inter-element isolation region 41 is present in a region other than the region where the inter-element isolation region 41 and the inter-pixel isolation region 31 overlap in a planar view, i.e., in the central portion away from the periphery of the photoelectric conversion region 22B, a gate electrode 58 may be provided across this inter-element isolation region 41 and the semiconductor layer 21.

[0306] [Fourth Embodiment] In this fourth embodiment, an example in which the present technology is applied to a stacked-type photodetector in which semiconductor layers are stacked in multiple stages, for example, a two-stage stacked solid-state imaging device in which two semiconductor layers are stacked in two stages, will be described. Fig. 36A is a plan view schematically showing one pixel in a solid-state imaging device according to a fourth embodiment of the present technology. Fig. 36B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a36-a36 cutting line in Fig. 36A. Note that in Fig. 36A, layers above the inter-element isolation region 41 are omitted from the illustration in order to make the drawing easier to understand.

[0307] As shown in Figures 36A and 36B , a solid-state imaging device 1D according to a fourth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment, but differs in the following respects. That is, as shown in Figures 36A and 36B , the solid-state imaging device 1D according to the fourth embodiment further includes a semiconductor layer 81 provided on the first surface portion S1 of the semiconductor layer 21 with an insulating layer 71 interposed therebetween, and an insulating layer 91 provided on the side of the semiconductor layer 81 opposite the insulating layer 71. In addition, in the solid-state imaging device 1D according to the fourth embodiment, a pixel transistor Q included in the pixel circuit 15 (see Figure 3 ) is provided in the semiconductor layer 81. In Figure 36B , an amplification transistor AMP is illustrated as an example of the pixel transistor Q. As shown in Figures 36B and 5A , the photoelectric conversion unit 25, the transfer transistor TR (see Figure 5A ), and the floating diffusion region FD are each provided in the semiconductor layer 21.

[0308] In the fourth embodiment, the semiconductor layer 21 corresponds to a specific example of a "first semiconductor layer" in the present technology, and the semiconductor layer 81 corresponds to a specific example of a "second semiconductor layer" in the present technology.

[0309] Furthermore, as shown in FIG. 36B, the solid-state imaging device 1D according to the fourth embodiment further includes a conductive path 95 that electrically connects the floating diffusion region FD provided in the semiconductor layer 21 and the amplification transistor AMP provided in the semiconductor layer 81.

[0310] The conductive path 95 includes a through contact electrode 92 that extends from the insulating layer 91 to the floating diffusion region FD in the stacking direction (Z direction) of the semiconductor layer 21 and the semiconductor layer 81 and is connected to the floating diffusion region FD, a contact electrode 93 that is embedded in the insulating layer 91 and is connected to the gate electrode 55 of the amplification transistor AMP, and a wiring 94 that is provided on the side of the insulating layer 91 opposite the semiconductor layer 81 side and is electrically and mechanically connected to each of the through contact electrode 92 and the contact electrode 93.

[0311] The wiring 94 may be formed of, for example, a metal film such as aluminum (Al) or copper (Cu), or an alloy film mainly containing Al or Cu. The insulating layer 91 may be formed of, for example, a silicon oxide film. The insulating layer 71 includes, for example, two insulating films 72 and 75. These insulating films 72 and 75 may be formed of, for example, silicon oxide films. The semiconductor layer 81 may be formed of, for example, a Si substrate, a SiGe substrate, or an InGaAs substrate. In the eighth embodiment, the semiconductor layer 21 is formed of, for example, a p-type semiconductor substrate made of single crystal silicon, although this is not limited thereto. The through contact electrode 92 is electrically isolated from the semiconductor layer 81. The through contact electrode 92 and the contact electrode 93 may be formed of, for example, a high-melting-point metal film such as titanium (Ti) or tungsten (W).

[0312] The solid-state imaging device 1D according to the fourth embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above. That is, the present technology can also be applied to a two-stage stacked solid-state imaging device 1D in which two semiconductor layers 21 and 81 are stacked in two stages.

[0313] Although not shown, the present technology can also be applied to a multi-layer stacked solid-state imaging device in which three or more semiconductor layers are stacked in multiple stages.

[0314] Fifth Embodiment In this fifth embodiment, an example in which the present technology is applied to a three-layer stacked solid-state imaging device in which three substrates including semiconductor layers are stacked in three layers will be described as a stacked-type photodetector in which semiconductor layers are stacked in multiple layers. FIG. 37 is an exploded view schematically showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 38 is an equivalent circuit diagram showing a configuration example of pixels and pixel circuits in a solid-state imaging device according to the fifth embodiment of the present technology. As shown in FIG. 37 , a solid-state imaging device 1E according to the fifth embodiment of the present technology includes three substrates (a first substrate (first substrate) 210, a second substrate (second substrate) 220, and a third substrate (third substrate) 230). The solid-state imaging device 1E has a three-dimensional structure in which three substrates (the first substrate 210, the second substrate 220, and the third substrate 230) are stacked. The first substrate 210, the second substrate 220, and the third substrate 230 are stacked in this order.

[0315] The first base 210 has a semiconductor layer 211 including a plurality of sensor pixels 212 that perform photoelectric conversion. The semiconductor layer 211 corresponds to a specific example of a "first semiconductor layer" of the present technology (technology related to the present disclosure). The plurality of sensor pixels 212 are arranged in a matrix within a pixel region 213 of the first base 210. The second base 220 has a semiconductor layer 221 including pixel circuits (readout circuits) 222 that output pixel signals based on charges output from the sensor pixels 212, one for every four sensor pixels 212. The semiconductor layer 221 corresponds to a specific example of a "second semiconductor layer" of the present technology. The second base 220 has a plurality of pixel drive lines 223 extending in the row direction and a plurality of vertical signal lines 224 extending in the column direction. The third base 230 has a semiconductor layer 231 including a logic circuit 232 that processes pixel signals. The logic circuit 232 includes, for example, a vertical drive circuit 233, a column signal processing circuit 234, a horizontal drive circuit 235, and a system control circuit 236. The logic circuit 232 (specifically, the horizontal drive circuit) outputs an output voltage Vout for each sensor pixel 212 to the outside. In the logic circuit 232, for example, a low-resistance region made of silicide formed using a salicide (self-aligned silicide) process such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.

[0316] The vertical drive circuit 233, for example, sequentially selects the plurality of sensor pixels 212 row by row. The column signal processing circuit 234, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 212 in the row selected by the vertical drive circuit 233. The column signal processing circuit 234 extracts signal levels of the pixel signals by performing CDS processing, for example, and stores pixel data corresponding to the amount of light received by each sensor pixel 212. The horizontal drive circuit 235, for example, sequentially outputs the pixel data stored in the column signal processing circuit 234 to the outside. The system control circuit 236, for example, controls the driving of each block (the vertical drive circuit 233, the column signal processing circuit 234, and the horizontal drive circuit 235) in the logic circuit 232.

[0317] 38 shows an example of a sensor pixel 212 and a pixel circuit 222. In this fourth embodiment, a case will be described in which four sensor pixels 212 share one pixel circuit 222, as shown in FIG. 38. Here, "shared" means that the outputs of the four sensor pixels 212 are input to a common pixel circuit 222.

[0318] The sensor pixels 212 have common components. In Fig. 38, in order to distinguish the components of the sensor pixels 212 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of the component of each sensor pixel 212. Hereinafter, when it is necessary to distinguish the components of each sensor pixel 212 from one another, an identification number is added to the end of the reference numeral of the component of each sensor pixel 212. However, when it is not necessary to distinguish the components of each sensor pixel 212 from one another, the identification number at the end of the reference numeral of the component of each sensor pixel 212 is omitted.

[0319] Each sensor pixel 212 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion region (FD) serving as a charge storage unit that temporarily stores signal charge output from the photodiode PD via the transfer transistor TR. The photodiode PD corresponds to a specific example of the photoelectric conversion unit 25 shown in the first to fourth embodiments. The photodiode PD performs photoelectric conversion to generate charge corresponding to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion region FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 223. As in the first embodiment, the logic circuit 232 is configured, for example, with a complementary metal-oxide semiconductor (CMOS) circuit.

[0320] The floating diffusion regions FD of the sensor pixels 212 that share one pixel circuit 222 are electrically connected to each other and to the input terminal of the common pixel circuit 222. The pixel circuit 222 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. Note that the selection transistor SEL may be omitted if necessary. The source of the reset transistor RST (the input terminal of the pixel circuit 222) is electrically connected to the floating diffusion region FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to a pixel drive line 223 (see FIG. 37). The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the pixel circuit 222) is electrically connected to a vertical signal line 224, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 223 (see FIG. 37).

[0321] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion region FD. The reset transistor RST resets the potential of the floating diffusion region FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion region FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 122. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge stored in the floating diffusion region FD. The amplification transistor AMP forms a source follower amplifier and outputs a pixel signal with a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 234 via the vertical signal line 224. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0322] 36B of the above-described fourth embodiment, in this fifth embodiment, a floating diffusion region FD provided in the semiconductor layer 211 of the first base 210 and a gate electrode 56 of an amplification transistor AMP provided in the semiconductor layer 221 of a second base 220 different from the first base 210 are electrically connected via a conductive path 95. The transfer transistor TR of this fifth embodiment can be any of the transfer transistors TR described in the above-described embodiments (first to third embodiments) and their modified examples.

[0323] Therefore, the solid-state imaging device 1E according to the fifth embodiment also provides the same effects as those of the above-described embodiments and their modified examples. That is, the present technology can also be applied to a solid-state imaging device 1E having a three-dimensional structure in which three bases (a first base 210, a second base 220, and a third base 230) are stacked.

[0324] Sixth Embodiment Example of Application to Electronic Devices The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0325] FIG. 39 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a sixth embodiment of the present technology.

[0326] 39 , an electronic device 300 includes a solid-state imaging device 301, an optical lens 302, a shutter device 303, a drive circuit 304, and a signal processing circuit 305. This electronic device 300 illustrates an embodiment in which the solid-state imaging devices 1A to 1E according to the first to fifth embodiments of the present technology are used as the solid-state imaging device 301 in an electronic device (for example, a camera).

[0327] The optical lens 302 focuses image light (incident light 306) from the subject on the imaging surface of the solid-state imaging device 301. This causes signal charges to accumulate in the solid-state imaging device 301 for a certain period of time. The shutter device 303 controls the light irradiation period and light blocking period for the solid-state imaging device 301. The drive circuit 304 supplies drive signals that control the transfer operation of the solid-state imaging device 301 and the shutter operation of the shutter device 303. The drive signals (timing signals) supplied from the drive circuit 304 cause charge transfer in the solid-state imaging device 301. The signal processing circuit 305 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 301. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0328] With this configuration, the performance of the solid-state imaging device 301 is improved, and therefore the image quality performance of the electronic device 300 of the sixth embodiment can be improved.

[0329] The electronic device 300 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0330] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0331] Seventh Embodiment Application Example to a Moving Body The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0332] FIG. 40 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0333] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 40, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0334] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0335] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0336] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0337] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0338] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0339] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0340] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0341] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0342] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 40, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0343] Fig. 41 is a diagram showing an example of the installation position of the image capturing unit 12031. In Fig. 41, a vehicle 12100 has image capturing units 12101, 12102, 12103, 12104, and 12105 as the image capturing unit 12031.

[0344] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0345] 41 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0346] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0347] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0348] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0349] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0350] The foregoing has described an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the above-described multiple electronic control units and imaging unit 12031 among the above-described configurations. Specifically, the solid-state imaging devices according to the first to fifth embodiments can be applied to the above-described multiple electronic control units and imaging unit 12031. By applying the technology according to the present disclosure to the electronic control unit and imaging unit 12031, performance can be improved, and therefore the performance of the electronic control unit and imaging unit 12031 can be improved.

[0351] Eighth Embodiment Application Example to an Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0352] FIG. 42 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0353] 42 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0354] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0355] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0356] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0357] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0358] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0359] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing the surgical site, etc.

[0360] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0361] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0362] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0363] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0364] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light in a narrower band than the light irradiated during normal observation (i.e., white light) to capture high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, in what is known as narrow band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or may involve locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissues with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0365] FIG. 43 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0366] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0367] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0368] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (so-called single-chip type) or multiple (so-called multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0369] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0370] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0371] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0372] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0373] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0374] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0375] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0376] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0377] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0378] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0379] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0380] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0381] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0382] The foregoing has described an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the CCU 11201 and the imaging unit 11402 of the camera head 11102, among the components described above. Specifically, the solid-state imaging devices according to the first to fifth embodiments described above can be applied to the CCU 11201 and the imaging unit 10402. By applying the technology according to the present disclosure to the CCU 11201 and the imaging unit 10402, the performance of the CCU 11201 and the imaging unit 10402 can be improved.

[0383] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0384] The present technology may be configured as follows: (1) A photodetector including: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; an insulator provided on the first surface portion side of the semiconductor layer; a photoelectric conversion unit that photoelectrically converts light incident from the second surface portion side of the semiconductor layer into signal charges; a charge retention unit provided on the first surface portion side of the semiconductor layer; and a transfer transistor that transfers the signal charges photoelectrically converted by the photoelectric conversion unit to the charge retention unit, wherein the transfer transistor has a gate electrode adjacent to the semiconductor layer and the insulator, respectively, and extending in the one direction. (2) The photodetector according to (1), wherein, in a plan view of the semiconductor layer viewed from the one direction, when a direction across an interface between the semiconductor layer and the insulator is defined as a horizontal direction and a direction intersecting the horizontal direction is defined as a vertical direction, a first width of the gate electrode along the vertical direction is wider than a second width along the horizontal direction. (3) The photodetector according to (1) or (2), wherein the semiconductor layer and the gate electrode each have planar side surfaces adjacent to each other, and the side surfaces of the semiconductor layer have a crystal orientation of any one of a (100), a (010), and a (001). (4) The photodetector according to (3), wherein the gate electrode is a rectangular parallelepiped. (5) The photodetector according to any of (1) to (4), wherein the gate electrode is located closer to the insulator than the interface. (6) The photodetector according to any of (1) to (4), wherein the gate electrode crosses the interface. (7) The photodetector according to any of (1) to (4), wherein the gate electrode is located closer to the semiconductor layer than the interface. (8) The photodetector according to any one of (1) to (7), wherein the insulator includes an isolation insulating film provided in a shallow groove recessed from the first surface portion of the semiconductor layer toward the second surface portion. (9) The photodetector according to any one of (1) to (7), wherein the insulator includes a first isolation insulating film provided in a shallow groove recessed from the first surface portion of the semiconductor layer toward the second surface portion, and a second isolation insulating film provided in a recessed portion extending from the first isolation insulating film toward the second surface portion of the semiconductor layer.(10) The photodetector according to any one of (1) to (7), wherein the insulator includes an isolation insulating film provided in a recessed portion extending from the first surface side to the second surface side of the semiconductor layer. (11) The photodetector according to any one of (1) to (10), wherein the transfer transistor further has a gate insulating film interposed between the semiconductor layer and the gate electrode. (12) The photodetector according to any one of (1) to (11), further comprising a pixel circuit that reads out signal charges held in the charge holding portion and outputs a pixel signal based on the read signal charges, and a pixel transistor included in the pixel circuit is provided on the first surface side of the semiconductor layer in the photoelectric conversion region. (13) The photodetector according to any one of (1) to (11), further comprising: a first semiconductor layer as the semiconductor layer; a second semiconductor layer provided so as to overlap the semiconductor layer in the one direction; and a pixel circuit that reads out the signal charges held in the charge holding portion and outputs a pixel signal based on the read signal charges, wherein a pixel transistor included in the pixel circuit is provided in the second semiconductor layer. (14) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; and a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in the one direction, wherein the photoelectric conversion region has: an internal separation barrier extending in the one direction; and a first photoelectric conversion cell and a second photoelectric conversion cell arranged adjacent to each other via the internal separation barrier in a direction intersecting the one direction, each of the first and second photoelectric conversion cells having a photoelectric conversion portion and a charge holding portion that holds signal charge photoelectrically converted in the photoelectric conversion portion, the internal separation barrier protruding from one of the two separation regions located opposite each other across the photoelectric conversion region in a planar view toward the other separation region, and the charge holding portions of the first and second photoelectric conversion cells are adjacent to each other via the internal separation barrier on one of the separation regions. (15) The photodetector according to (14), wherein the internal isolation barrier is integrated with the other isolation region and has a recess that connects the first photoelectric conversion cell and the second photoelectric conversion cell.(16) The photodetector according to (14), wherein the internal isolation barriers are spaced apart from each other. (17) The photodetector according to (14), wherein each of the first and second photoelectric conversion cells further includes a transfer transistor for transferring signal charges photoelectrically converted in the photoelectric conversion unit to the charge retention unit, and the transfer transistor has a gate electrode extending in the one direction and adjacent to the semiconductor layer of the photoelectric conversion region and the isolation region. (18) The photodetector according to (14), comprising: a semiconductor layer having a first surface portion and a second surface portion positioned opposite each other in the one direction; an isolation region extending from the first surface portion of the semiconductor layer toward the second surface portion; and a transfer transistor provided on the first surface portion side of the semiconductor layer and for transferring signal charges photoelectrically converted in the photoelectric conversion unit to the charge retention unit, wherein the transfer transistor has a gate electrode provided outside the first surface portion of the semiconductor layer and spanning the semiconductor layer and the isolation region in a planar view. (19) The photodetector according to (18), wherein the separation region includes an insulator. (20) An electronic device comprising: the photodetector according to any one of (1) to (19), an optical lens that focuses image light from a subject on an imaging surface of the photodetector, and a signal processing circuit that processes a signal output from the photodetector.

[0385] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0386] DESCRIPTION OF SYMBOLS 1A, 1B, 1C, 1D, 1E...Solid-state imaging device 2...Semiconductor chip 2A...Pixel array section 2B...Peripheral section 3...Pixel 4...Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7...Output circuit 8...Control circuit 10...Pixel drive line 11...Vertical signal line 12...Horizontal signal line 13...Logic circuit 14...Bonding pad 15...Pixel circuit (readout circuit) 21...Semiconductor layer 21a...Side wall surface portion 22, 22B...Photoelectric conversion region 23...P-type well region (p-type semiconductor region) 24...N-type semiconductor region 25...Photoelectric conversion section (PD) 26L...First photoelectric conversion cell 26R...Second photoelectric conversion cell 31...Inter-pixel isolation region 32...Dug portion 33...Isolation insulating film (insulator) 36...Step portion 37, 38, 39...Internal isolation barrier 38a... Recess 41... Element isolation region (field isolation region) 42... Shallow trench 43... Isolation insulating film (insulator) 45a, 45b, 45c, 45d... Element formation region 43z... Power supply region 51... Gate trench 52... Gate insulating film 53... Conductive film 55... Gate electrode 55a... Upper surface 55b... Lower surface 55c １ , 55c ２ , 55c ３ , 55c ４ ...Side part 55X １ ...Second part 55X １２ ...Second part 55X １３ ...Third part 55Y １ ...First part 55Y １１...first portion 56...gate electrode 57a, 57b...main electrode region 61...planarization film 63...optical filter layer 63a...optical filter portion 64...microlens layer 64a...microlens 210...first base 211...semiconductor layer (first semiconductor layer) 212...sensor pixel 213...pixel region 220...second base 221...semiconductor layer (second semiconductor layer) 222...pixel circuit (readout circuit) 223...pixel drive line 224...vertical drive line 230...third base 231...semiconductor layer 232...logic circuit 233...vertical drive circuit 234...column signal processing circuit 235...horizontal drive circuit 236...system control circuit 300...electronic device 301...solid-state imaging device 302...optical lens (optical system) 303...shutter device 304...drive circuit 305...signal processing circuit 306...Incoming light A １ ...Horizontal A ２ ...Vertical direction AMP... Amplification transistor FD... n-type floating diffusion region Lp... Interface portion Q... Pixel transistor RST... Reset transistor SEL... Selection transistor S1... First surface portion S2... Second surface portion TR, TR1, TR2... Transfer transistors with vertical structure TRL1, TRL2... Transfer transistors with horizontal structure WC... Power supply contact region W １ ...First width W ２ …Second width

Claims

1. A photodetection device comprising: a semiconductor layer having a first surface and a second surface located opposite each other in one direction; an insulator provided on the first surface side of the semiconductor layer; a photoelectric conversion unit that photoelectrically converts light incident from the second surface side of the semiconductor layer into a signal charge; a charge retention unit provided on the first surface side of the semiconductor layer; and a transfer transistor that transfers the signal charge photoelectrically converted by the photoelectric conversion unit to the charge retention unit, wherein the transfer transistor has a gate electrode extending in the one direction adjacent to each of the semiconductor layer and the insulator.

2. The photodetector device of claim 1, wherein, in a plan view of the semiconductor layer from the one direction, a direction across the interface between the semiconductor layer and the insulator is defined as a horizontal direction, and a direction intersecting the horizontal direction is defined as a vertical direction, and the gate electrode has a first width along the vertical direction which is wider than a second width along the horizontal direction.

3. The photodetector according to claim 1, wherein the semiconductor layer and the gate electrode each have planar side portions adjacent to each other, and the side portions of the semiconductor layer have a crystal orientation of any one of a (100) plane, a (010) plane, or a (001) plane.

4. The photodetector according to claim 3, wherein the gate electrode is a rectangular parallelepiped.

5. The photodetector according to claim 2, wherein the gate electrode is located closer to the insulator than the interface portion.

6. The photodetection device according to claim 2, wherein said gate electrode crosses said interface portion.

7. The photodetector according to claim 2, wherein said gate electrode is located in said semiconductor layer below said interface.

8. The photodetector according to claim 1, wherein the insulator includes an isolation insulating film provided in a shallow groove portion recessed from the first surface portion of the semiconductor layer toward the second surface portion.

9. The photodetector device of claim 1, wherein the insulator includes a first isolation insulating film provided in a shallow groove portion recessed from the first surface portion of the semiconductor layer toward the second surface portion, and a second isolation insulating film provided in a recessed portion extending from the first isolation insulating film toward the second surface portion of the semiconductor layer.

10. The photodetector according to claim 1, wherein the insulator includes an isolation insulating film provided in a recess extending from the first surface side to the second surface side of the semiconductor layer.

11. The photodetector according to claim 1, wherein the transfer transistor further comprises a gate insulating film interposed between the semiconductor layer and the gate electrode.

12. The photodetection device according to claim 1, further comprising a pixel circuit that reads out the signal charge held in the charge holding portion and outputs a pixel signal based on the read-out signal charge, wherein a pixel transistor included in the pixel circuit is provided on the first surface side of the semiconductor layer in the photoelectric conversion region.

13. The photodetection device according to claim 1, further comprising: a first semiconductor layer, a second semiconductor layer provided so as to overlap the semiconductor layer in the one direction; and a pixel circuit that reads out the signal charge held in the charge holding portion and outputs a pixel signal based on the read-out signal charge, wherein a pixel transistor included in the pixel circuit is provided in the second semiconductor layer.

14. A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; and a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending in the one direction, wherein the photoelectric conversion region has an internal separation barrier extending in the one direction, and a first photoelectric conversion cell and a second photoelectric conversion cell arranged adjacent to each other via the internal separation barrier in a direction intersecting the one direction, each of the first and second photoelectric conversion cells has a photoelectric conversion section and a charge holding section that holds signal charge photoelectrically converted in the photoelectric conversion section, the internal separation barrier protrudes from one of two separation regions located opposite each other across the photoelectric conversion region in a planar view to the other separation region, and the charge holding sections of the first and second photoelectric conversion cells are adjacent to each other via the internal separation barrier on the one separation region side.

15. The photodetection device according to claim 14, wherein the internal isolation barrier is integrated with the other isolation region and has a recess connecting the first photoelectric conversion cell and the second photoelectric conversion cell.

16. The optical detection device of claim 14, wherein said internal isolation barriers are spaced apart from each other of said internal isolation barriers.

17. The photodetection device described in claim 14, wherein each of the first and second photoelectric conversion cells further has a transfer transistor that transfers signal charges photoelectrically converted in the photoelectric conversion section to the charge holding section, and the transfer transistor has a gate electrode extending in the one direction adjacent to each of the semiconductor layer and the isolation region of the photoelectric conversion region.

18. A photodetector comprising: a semiconductor layer having a first surface and a second surface positioned opposite each other in one direction; a separation region extending from the first surface of the semiconductor layer toward the second surface; and a transfer transistor provided on the first surface side of the semiconductor layer and transferring signal charges photoelectrically converted in a photoelectric conversion unit to a charge holding unit, wherein the transfer transistor has a gate electrode provided across the semiconductor layer and the separation region in a planar view outside the first surface of the semiconductor layer.

19. The photodetection device of claim 18, wherein the isolation region comprises an insulator.

20. An electronic device comprising: a photodetection device; an optical lens that focuses image light from a subject on an imaging surface of the photodetection device; and a signal processing circuit that performs signal processing on a signal output from the photodetection device, wherein the photodetection device comprises: a semiconductor layer having a first surface and a second surface located opposite each other in one direction; an insulator provided on the first surface side of the semiconductor layer; a photoelectric conversion unit that photoelectrically converts light incident from the second surface side of the semiconductor layer into a signal charge; a charge holding unit provided on the first surface side of the semiconductor layer; and a transfer transistor that transfers the signal charge photoelectrically converted by the photoelectric conversion unit to the charge holding unit, wherein the transfer transistor has a gate electrode extending in the one direction adjacent to each of the semiconductor layer and the insulator.

Images