photodetector

Abstract

A light detecting device includes a first structure comprising a first semiconductor layer. The light detecting device includes a photoelectric conversion element to convert incident light into electric charge, a first floating diffusion disposed in the first semiconductor layer and configured to store electric charge transferred from the photoelectric conversion element, and an amplification transistor including a gate electrode in contact with the first semiconductor layer adjacent to the first floating diffusion.

Description

PHOTODETECTORCross Reference to Related Applications

[0001] This application claims the benefit of Japanese Priority Patent Application JP2023-166326 filed on September 27, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a photodetector.

[0003] PTL 1 discloses an imaging element. The imaging element includes a first semiconductor substrate and a second semiconductor substrate stacked on the first semiconductor substrate. A photoelectric converter that converts light into electric charge and a charge holder that holds the electric charge transferred from the photoelectric converter are disposed in the first semiconductor substrate. An amplification transistor is disposed in the second semiconductor substrate. The amplification transistor generates a signal corresponding to a level of the electric charge held in the charge holder.

[0004] [PTL 1] International Publication No. WO2020 / 189534 A1Summary

[0005] In an imaging element disclosed in PTL 1, a charge holder is electrically coupled to a gate electrode of an amplification transistor through wiring formed on a side of a first semiconductor substrate, through hole wiring penetrating a second semiconductor substrate, and the like. That is, a length of a wiring path from the charge holder to the gate electrode of the amplification transistor increases. In the imaging element having such a configuration, a parasitic capacitance value increases in line with an increase in the length of the wiring path. This increases random noise, making it unable to achieve sufficient charge conversion efficiency. Therefore, development of a photodetector has been desired that makes it possible to improve charge conversion efficiency.

[0006] At least one embodiment is directed to a light detecting device comprising a first structure that includes a first semiconductor layer, a photoelectric conversion element to convert incident light into electric charge, a first floating diffusion disposed in the first semiconductor layer and configured to store electric charge transferred from the photoelectric conversion element, and an amplification transistor including a gate electrode in contact with the first semiconductor layer adjacent to the first floating diffusion. The gate electrode of the amplification transistor is in contact with two or fewer sides of the first semiconductor layer. The first structure further comprises a second semiconductor layer including a channel region of the amplification transistor, and a first separation material between the first semiconductor layer and the second semiconductor layer. The first structure further comprises a second separation material between the gate electrode of the amplification transistor and the second semiconductor layer. The first and second separation material comprise oxide. The first and second separation material comprise semiconductor material. Part of the second separation material contacts the first separation material.

[0007] Part of the gate electrode of the amplification transistor contacts the first separation material. The photoelectric conversion element is included in a plurality of photoelectric conversion elements that share the amplification transistor.

[0008] The light detecting device further comprises a transfer transistor coupled to the first floating diffusion, a reset transistor coupled to the first floating diffusion and the amplification transistor, and a selection transistor coupled to the amplification transistor.

[0009] The light detecting device further comprises a second structure bonded to the first structure and including a second semiconductor layer. Part of the reset transistor, part of the selection transistor, or parts of both of the reset transistor and the selection transistor are included in the second structure. A conversion gain switching transistor is coupled between the first floating diffusion and the reset transistor. Part of the reset transistor, part of the selection transistor, part of the conversion gain switching transistor, or parts of the reset transistor, the conversion gain switching transistor, and the selection transistor are included in the second structure.

[0010] The first structure further comprises wiring that electrically connects the gate of the amplification transistor and a source of the reset transistor.

[0011] At least one embodiment is directed to a light detecting device comprising a first semiconductor layer, a photoelectric conversion element disposed in the first semiconductor layer and configured to convert incident light into electric charge, a first floating diffusion disposed in the first semiconductor layer and configured to store electric charge transferred from the photoelectric conversion element, and an amplification transistor including a gate electrode electrically coupled to the first floating diffusion through the first semiconductor layer.

[0012] In a cross-sectional view, the gate electrode of the amplification transistor is located at a corner of the first semiconductor layer.

[0013] The light detecting device further comprises a second semiconductor layer including at least part of a reset transistor, wherein part of the gate electrode of the amplification transistor contacts the second semiconductor layer.

[0014] In the cross-sectional view, the gate electrode of the amplification transistor is adjacent to sidewalls of the first semiconductor layer.

[0015] At least one embodiment is directed to a light detecting device comprising a photoelectric conversion element disposed in a first semiconductor layer and configured to convert incident light into electric charge, a transfer transistor configured to transfer the electric charge from the photoelectric conversion element, a first floating diffusion disposed in the first semiconductor layer and configured to store the electric charge transferred by the transfer transistor, and an amplification transistor including a gate electrode that contacts the first semiconductor layer adjacent to the first floating diffusion.

[0016] Fig. 1 is a schematic system configuration diagram of a photodetector according to a first embodiment of the present disclosure.Fig. 2 is a schematic exploded planar configuration diagram of the photodetector illustrated in Fig. 1.Fig. 3 is a circuit configuration diagram of pixels and a pixel circuit of the photodetector illustrated in Fig. 1.Fig. 4 is a planar configuration diagram in a first base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 1.Fig. 5 is a planar configuration diagram in a second base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 1.Fig. 6 is a cross-sectional configuration diagram in the first base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 4 (a cross-sectional view sectioned along a section line A-A illustrated in Fig. 4).Fig. 7 is a cross-sectional configuration diagram in the first base and the second base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 4 (a cross-sectional view sectioned along a section line B-B illustrated in Fig. 4 and a section line C-C illustrated in Fig. 5).Fig. 8 is a first step cross-sectional view for describing a manufacturing method of the photodetector according to the first embodiment (a step cross-sectional view sectioned along the section line A-A illustrated in Fig. 4).Fig. 9 is a second step cross-sectional view.Fig. 10 is a third step cross-sectional view.Fig. 11 is a fourth step cross-sectional view.Fig. 12 is a fifth step cross-sectional view.Fig. 13 is a sixth step cross-sectional view.Fig. 14 is a seventh step cross-sectional view.Fig. 15 is an eighth step cross-sectional view.Fig. 16 is a ninth step cross-sectional view.Fig. 17 is a tenth step cross-sectional view.Fig. 18 is an eleventh step cross-sectional view.Fig. 19 is a twelfth step cross-sectional view.Fig. 20 is a thirteenth step cross-sectional view.Fig. 21 is a fourteenth step cross-sectional view.Fig. 22 is a fifteenth step cross-sectional view.Fig. 23 is a sixteenth step cross-sectional view.Fig. 24 is a seventeenth step cross-sectional view.Fig. 25 is an eighteenth step cross-sectional view.Fig. 26 is a nineteenth step cross-sectional view.Fig. 27 is a twentieth step cross-sectional view.Fig. 28 is a twenty-first step cross-sectional view.Fig. 29 is a twenty-second step cross-sectional view.Fig. 30 is a twenty-third step cross-sectional view.Fig. 31 is a twenty-fourth step cross-sectional view.Fig. 32 is a twenty-fifth step cross-sectional view.Fig. 33 is a twenty-sixth step cross-sectional view.Fig. 34 is a cross-sectional configuration diagram, corresponding to Fig. 6, of pixels and a pixel circuit of a photodetector according to a second embodiment of the present disclosure.Fig. 35 is a cross-sectional configuration diagram, corresponding to Fig. 6, of pixels and a pixel circuit of a photodetector according to a third embodiment of the present disclosure.Fig. 36 is a cross-sectional configuration diagram, corresponding to Fig. 6, of pixels and a pixel circuit of a photodetector according to a fourth embodiment of the present disclosure.Fig. 37 is a planar configuration diagram, corresponding to Fig. 4, of pixels and a pixel circuit of a photodetector according to a fifth embodiment of the present disclosure.Fig. 38 is a planar configuration diagram, corresponding to Fig. 4, of pixels and a pixel circuit of a photodetector according to a sixth embodiment of the present disclosure.Fig. 39 is a planar configuration diagram, corresponding to Fig. 5, of the pixels and the pixel circuit of the photodetector according to the sixth embodiment.Fig. 40 is a cross-sectional configuration diagram of the pixels and the pixel circuit of the photodetector illustrated in Figs. 38 and 39 (a cross-sectional view sectioned along a section line D-D illustrated in Figs. 38 and 39).Fig. 41 is a circuit configuration diagram, corresponding to Fig. 3, of pixels and a pixel circuit of a photodetector according to a seventh embodiment of the present disclosure.Fig. 42 is a planar configuration diagram in a first base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 41.Fig. 43 is a cross-sectional configuration diagram in the first base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 42 (a cross-sectional view sectioned along a section line E-E illustrated in Fig. 42).Fig. 44 is a cross-sectional configuration diagram in the first base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 42 (a cross-sectional view sectioned along a section line F-F illustrated in Fig. 42).Fig. 45 is a planar configuration diagram in a first base of pixels and a pixel circuit of a photodetector according to an eighth embodiment of the present disclosure.Fig. 46 is a cross-sectional configuration diagram in the first base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 45 (a cross-sectional view sectioned along a section line G-G illustrated in Fig. 45).Fig. 47 is a cross-sectional configuration diagram in the first base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 45 (a cross-sectional view sectioned along a section line H-H illustrated in Fig. 45).Fig. 48 is a cross-sectional configuration diagram in a first base of pixels and a pixel circuit of a photodetector according to a ninth embodiment of the present disclosure (a cross-sectional view corresponding to the cross-sectional view sectioned along the section line E-E illustrated in Fig. 42).Fig. 49 is a cross-sectional configuration diagram in the first base of the pixels and the pixel circuit of the photodetector according to the ninth embodiment (a cross-sectional view corresponding to the cross-sectional view sectioned along the section line F-F illustrated in Fig. 42).Fig. 50 is a planar configuration diagram in a first base of pixels and a pixel circuit of a photodetector according to a tenth embodiment of the present disclosure.Fig. 51 is a planar configuration diagram in a first base of pixels and a pixel circuit of a photodetector according to an eleventh embodiment of the present disclosure.Fig. 52 is a planar configuration diagram, corresponding to Fig. 42, of pixels and a pixel circuit of a photodetector according to a twelfth embodiment of the present disclosure.Fig. 53 is a cross-sectional configuration diagram in a first base of the pixels and the pixel circuit of the photodetector illustrated in Fig. 52 (a cross-sectional view sectioned along a section line I-I and a section line J-J illustrated in Fig. 52).Fig. 54A is an enlarged cross-sectional configuration diagram of a main part including a gate electrode and a gate insulating film of a transistor constructing the pixel circuit according to the twelfth embodiment.Fig. 54B is a cross-sectional configuration diagram schematically illustrating a crystal structure of the gate electrode illustrated in Fig. 54A.Fig. 55A is an enlarged cross-sectional configuration diagram, corresponding to Fig. 54A, of a main part including a gate electrode and a gate insulating film of a transistor according to a comparative example.Fig. 55B is a cross-sectional configuration diagram, corresponding to Fig. 54B, schematically illustrating a crystal structure of the gate electrode illustrated in Fig. 55A.Fig. 56 is a first step cross-sectional view, corresponding to Fig. 53, for describing a manufacturing method of the photodetector according to the twelfth embodiment.Fig. 57 is a second step cross-sectional view.Fig. 58 is a third step cross-sectional view.Fig. 59 is a fourth step cross-sectional view.Fig. 60 is a fifth step cross-sectional view.Fig. 61 is a sixth step cross-sectional view.Fig. 62 is a seventh step cross-sectional view.Fig. 63 is an eighth step cross-sectional view.Fig. 64 is a ninth step cross-sectional view.Fig. 65 is a cross-sectional configuration diagram, corresponding to Fig. 53, of pixels and a pixel circuit of a photodetector according to a thirteenth embodiment of the present disclosure.Fig. 66 is a cross-sectional configuration diagram, corresponding to Fig. 53, of pixels and a pixel circuit of a photodetector according to a fourteenth embodiment of the present disclosure.Fig. 67 is a cross-sectional configuration diagram, corresponding to Fig. 54A, of a transistor constructing a pixel and a pixel circuit of a photodetector according to a fifteenth embodiment of the present disclosure.Fig. 68 is a cross-sectional configuration diagram, corresponding to Fig. 54A, of a transistor constructing a pixel and a pixel circuit of a photodetector according to a sixteenth embodiment of the present disclosure.Fig. 69 is a block diagram depicting an example of schematic configuration of a vehicle control system.Fig. 70 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section.

[0017] Hereinafter, detailed description is given of embodiments of the present disclosure with reference to the drawings. It is to be noted that the description is given in the following order.

[0018] 1. First Embodiment A first embodiment describes a first example in which the present technology is applied to a photodetector. In the present technology, the photodetector is constructed by a solid-state imaging device or to include a solid-state imaging device. The first embodiment describes an overall configuration of the photodetector, a configuration of pixels, and a configuration of a pixel circuit. The first embodiment further describes a manufacturing method of the photodetector. 2. Second Embodiment A second embodiment describes a second example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. In particular, a coupling structure between an amplification transistor and a reset transistor of the pixel circuit is changed in the second embodiment. 3. Third Embodiment A third embodiment describes a third example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. In particular, a structure of the amplification transistor of the pixel circuit is changed in the third embodiment. 4. Fourth Embodiment A fourth embodiment describes a fourth example in which a configuration of a base where the pixels and the pixel circuit are disposed is changed in the photodetector according to the first embodiment. 5. Fifth Embodiment A fifth embodiment describes a fifth example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. 6. Sixth Embodiment A sixth embodiment describes a sixth example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. 7. Seventh Embodiment A seventh embodiment describes a seventh example in which the configuration of the pixel circuit is changed in the photodetector according to the first embodiment. In particular, the coupling structure between the amplification transistor and the reset transistor of the pixel circuit is changed in the seventh embodiment. 8. Eighth Embodiment An eighth embodiment describes an eighth example in which the configuration of the pixel circuit is changed in the photodetector according to the seventh embodiment. In particular, a structure of an electrical conductor that achieves the coupling structure is changed in the eighth embodiment. 9. Ninth Embodiment A ninth embodiment describes a ninth example in which the configuration of the pixel circuit is changed in the photodetector according to the seventh embodiment. In particular, the structure of the electrical conductor that achieves the coupling structure is changed in the ninth embodiment. 10. Tenth Embodiment A tenth embodiment describes a tenth example in which the configuration of the pixel circuit is changed in the photodetector according to the seventh embodiment. In particular, the coupling structure between the amplification transistor and the reset transistor of the pixel circuit is changed in the tenth embodiment. 11. Eleventh Embodiment An eleventh embodiment describes an eleventh example in which the configuration of the pixel circuit is changed in the photodetector according to the seventh embodiment. In particular, the coupling structure between the amplification transistor and the reset transistor of the pixel circuit is changed in the eleventh embodiment. 12. Twelfth Embodiment A twelfth embodiment describes a twelfth example in which a structure of a gate electrode of each of transistors constructing the pixel and the pixel circuit is changed in the photodetector according to the first embodiment. In particular, the description of the twelfth embodiment includes a crystal structure of the gate electrode. The twelfth embodiment further describes a manufacturing method of the photodetector. 13. Thirteenth Embodiment A thirteenth embodiment describes a thirteenth example in which a structure of a transfer transistor of the pixel is changed in the photodetector according to the twelfth embodiment. 14. Fourteenth Embodiment A fourteenth embodiment describes a fourteenth example in which the structure of the amplification transistor of the pixel circuit is changed in the photodetector according to the twelfth embodiment. 15. Fifteenth Embodiment A fifteenth embodiment describes a fifteenth example in which the structure of the gate electrode of each of the transistors constructing the pixel and the pixel circuit is changed in the photodetector according to the twelfth embodiment. 16. Sixteenth Embodiment A sixteenth embodiment describes a sixteenth example in which the structure of the gate electrode of each of the transistors constituting the pixel and the pixel circuit is changed in the photodetector according to the twelfth embodiment. 17. Example of Practical Application to Mobile Body This practical application example describes an example in which the present technology is applied to a vehicle control system that is an example of a mobile body control system. 18. Other Embodiments <1. First Embodiment>

[0019] Description is given of a photodetector 1 according to the first embodiment of the present disclosure and a manufacturing method of the photodetector 1 with reference to Figs. 1 to 33.

[0020] Here, an arrow-X direction illustrated as appropriate in the drawings indicates one planar direction of the photodetector 1 placed on a plane for convenience. An arrow-Y direction indicates another planar direction orthogonal to the arrow-X direction. In addition, an arrow-Z direction indicates an upward direction orthogonal to the arrow-X direction and the arrow-Y direction. That is, the arrow-X direction, the arrow-Y direction, and the arrow-Z direction exactly coincide with an X-axis direction, a Y-axis direction, and a Z-axis direction, respectively, of a three-dimensional coordinate system. It is to be noted that these directions are each illustrated for convenience to aid understanding of description, and are not intended to limit directions used in the present technology. 〈Configuration of Photodetector 1〉 (1) Overall Configuration of Photodetector 1

[0021] Fig. 1 illustrates an example of a system configuration of the photodetector 1 according to the first embodiment. The photodetector 1 is constructed by a solid-state imaging device or to include a solid-state imaging device. Here, the photodetector 1 is constructed as a CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging device. The solid-state imaging device detects light L (see Fig. 6) incident from the outside, converts the detected light L into electric charge, and generates an image such as a still image or a moving image on the basis of the converted electric charge.

[0022] The photodetector 1 includes a pixel region (pixel array section) 100 and a peripheral circuit. The pixel region 100 includes a plurality of pixels 10 regularly arranged two-dimensionally in a plane in the arrow-X direction and the arrow-Y direction.

[0023] Although described later, the pixel 10 includes a photoelectric conversion element PD (see Fig. 3) and a transfer transistor TR (see Fig. 3). The photoelectric conversion element PD includes, for example, a photodiode. The photoelectric conversion element PD converts the light L into electric charge. The transfer transistor TR transfers the electric charge converted by the photoelectric conversion element PD. In addition, a pixel circuit 20 (see Fig. 3) is electrically coupled to the pixel 10. The pixel circuit 20 reads the electric charge converted in the pixel 10.

[0024] The peripheral circuit is constructed to include a vertical drive circuit VD, column signal processing circuits CS, a horizontal drive circuit HD, an output circuit Out, a control circuit CC, and the like.

[0025] The control circuit CC receives an input clock and data adapted to command an operation mode and the like, and also outputs data such as internal information concerning the photodetector 1. That is, the control circuit CC generates, on the basis of a vertical synchronization signal, a horizontal synchronization signal, and a master clock, a control signal or a clock signal adapted to serve as reference for operations of the vertical drive circuit VD, the column signal processing circuits CS, the horizontal drive circuit HD, and the like. Moreover, these signals are inputted to the vertical drive circuit VD, the column signal processing circuits CS, the horizontal drive circuit HD, and the like.

[0026] The vertical drive circuit VD includes, for example, a shift register. The vertical drive circuit VD selects pixel drive wiring Ld, and supplies the selected pixel drive wiring Ld with a pulse adapted to drive the pixels 10. The pixels 10 are driven on a row-by-row basis. That is, the vertical drive circuit VD selectively scans each of the pixels 10 of the pixel region 100 sequentially in a vertical direction on a row-by-row basis. Signal charge generated depending on an amount of light received by the photoelectric conversion element PD of each of the pixels 10 is supplied as a pixel signal to the column signal processing circuit CS through a vertical signal line Lv.

[0027] The column signal processing circuit CS is disposed, for example, for each of columns of the pixels 10. The column signal processing circuit CS performs, for each of pixel columns, signal processing such as noise removal on signals outputted from one row of the pixels 10. That is, the column signal processing circuit CS performs signal processing such as AD (Analog Digital) conversion, signal amplification, or CDS (Correlated Double Sampling) adapted to remove fixed pattern noise inherent in the pixels 10. An unillustrated horizontal selection switch is coupled to an output stage of the column signal processing circuits CS between the column signal processing circuits CS and a horizontal signal line Lh.

[0028] The horizontal drive circuit HD includes, for example, a shift register. The horizontal drive circuit HD selects in sequence each of the column signal processing circuits CS by sequentially outputting horizontal scan pulses, and outputs, to the horizontal signal line Lh, the pixel signals from each of the column signal processing circuits CS.

[0029] The output circuit Out performs signal processing on the signals sequentially supplied from each of the column signal processing circuits CS through the horizontal signal line Lh, and outputs the resultant signals. For example, the output circuit Out only performs buffering in some cases, and performs black level adjustment, column variation correction, and various types of digital signal processing in other cases. An input / output terminal In exchanges signals between the photodetector 1 and the outside. (2) Device Configuration of Photodetector 1

[0030] Fig. 2 illustrates an example of a schematic exploded planar configuration of the photodetector 1 illustrated in Fig. 1. The photodetector 1 has a three-layer structure in which a first base 1A (also called a first structure), a second base 1B (also called a second structure), and a third base 1C (also called a third structure) are each stacked and are bonded to each other. Here, the third base 1C, the second base 1B, and the first base 1A are each sequentially stacked in the arrow-Z direction. It is to be noted that the photodetector 1 has a three-layer structure in the first embodiment, and the second to fourth embodiments and the sixth embodiment described later. In addition, the photodetector 1 has a two-layer structure in which the first base 1A and the second base 1B are configured as one base in the fifth embodiment and the seventh to eleventh embodiments described later. Further, the photodetection device 1 may have a two-layer structure or a three-layer structure in the twelfth to sixteenth embodiments described later.

[0031] The first base 1A is formed in a rectangular shape as viewed in the arrow-Z direction or a direction opposite to the arrow-Z direction (hereinafter, simply referred to as "in a plan view"). To give detailed description, here, the first base 1A is formed in a square shape. The first base 1A includes a semiconductor substrate (see reference numeral 30 in Figs. 5 and 6) including, for example, monocrystalline silicon. The photoelectric conversion element PD and the transfer transistor TR each constructing the pixel 10 are disposed in the semiconductor substrate of the first base 1A. The pixel region 100 is disposed substantially across an entire region of the first base 1A. As described above, the plurality of pixels 10 is arranged in the pixel region 100. That is, the first base 1A constructs a light detection surface serving as an imaging surface adapted to capture an image.

[0032] At least a portion of unillustrated pixel transistors constructing the pixel circuit 20 here is further disposed in the semiconductor substrate of the first base 1A. In the first embodiment, an amplification transistor AMP and a reset transistor RST (see Fig. 3) among the pixel transistors are disposed in the first base 1A.

[0033] The second base 1B is formed in a rectangular shape similar to that of the first base 1A, and is formed in a planar size similar to a planar size of the first base 1A, in a plan view. The second base 1B includes a semiconductor substrate (see reference numeral 40 in Fig. 7) including, for example, monocrystalline silicon, in a similar manner to the first base 1A.

[0034] The pixel transistors that are other than the amplification transistor AMP and the reset transistor RST and construct the pixel circuit 20 are disposed in the semiconductor substrate of the second base 1B. In the first embodiment, a selection transistor SEL (see Fig. 3) among the pixel transistors is disposed in the second base 1B. It is to be noted that, in a case where the pixel circuit 20 is constructed to include a floating diffusion conversion gain switching transistor (hereinafter, simply referred to as an "FD conversion gain switching transistor") FDG, the selection transistor SEL and the FD conversion gain switching transistor FDG are disposed in the second base 1B. It is to be noted that description is given of the FD conversion gain switching transistor FDG in the seventh embodiment described later (see Fig. 41).

[0035] Although the numbers of the disposed pixels 10 and pixel circuits 20 are not particularly limited, one pixel circuit 20 is disposed for four pixels 10 in the first embodiment. Description is given later of a configuration of the plurality of pixel transistors constructing the pixel circuit 20. Further, the pixel drive wiring Ld extended in the arrow-X direction and the vertical signal line Lv extended in the arrow-Y direction in the pixel region 100 are disposed in the second base 1B. The pixel drive wiring Ld and the vertical signal line Lv overlap the pixel region 100 in a plan view.

[0036] It is to be noted that, in a case of the photodetector 1 having a two-layer structure, the pixel circuit 20 is disposed in a base in which the first base 1A and the second base 1B are integrated.

[0037] The third base 1C is formed in a rectangular shape similar to that of the first base 1A, and is formed in a planar size similar to the planar size of the first base 1A, in a plan view. The third base 1C includes a semiconductor substrate (illustration and description of a cross-sectional configuration are omitted) including, for example, monocrystalline silicon, in a similar manner to the first base 1A. The peripheral circuit is disposed in the semiconductor substrate of the third base 1C. As described above, the peripheral circuit includes the vertical drive circuit VD, the column signal processing circuits CS, the horizontal drive circuit HD, the output circuit Out, the control circuit CC, and the like.

[0038] It is to be noted that each circuit of the peripheral circuit is a logic circuit in the first embodiment. The logic circuit is constructed to include one or more semiconductor elements selected from a transistor, a capacitor, and a resistor. An insulated gate field effect transistor (IGFET: Insulated Gate Field Effect Transistor) is used for the transistor. A low-resistance layer formed through a salicide (Self-Aligned Silicide) process is formed on surfaces of at least one pair of main electrodes of the transistor. Examples of the salicide include CoSi2and NiSi. A resistance value of the low-resistance layer is smaller than a resistance value of a semiconductor layer formed by an n-type semiconductor region. (3) Circuit Configuration of Pixel 10 and Pixel Circuit 20

[0039] Fig. 3 illustrates an example of a circuit configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1. In the first embodiment, four pixels 10 are electrically coupled to one pixel circuit 20, and the four pixels 10 share the one pixel circuit 20. That is, electric charge converted from the light L in each of the four pixels 10 is read in the one pixel circuit 20.

[0040] The pixel 10 includes the photoelectric conversion element PD and the transfer transistor TR, and includes series circuits of both the photoelectric conversion element PD and the transfer transistor TR. To give detailed description, here, the photoelectric conversion element PD includes a photodiode. The photodiode includes an anode region and a cathode region. Meanwhile, the transfer transistor TR is an IGFET. The IGFET includes a pair of main electrodes (a source region and a drain region) and a gate electrode. The anode region of the photoelectric conversion element PD is electrically coupled to a reference voltage GND. In addition, the cathode region is electrically coupled to one of the main electrodes of the transfer transistor TR. Another one of the main electrodes of the transfer transistor TR is electrically coupled to one end of the floating diffusion FD. Moreover, a control signal adapted to control electrical conduction or non-electrical conduction is inputted to the gate electrode.

[0041] Here, the four pixels 10 are disposed for the one pixel circuit 20, as described above. Therefore, the photoelectric conversion elements PD and the transfer transistors TR of the respective four pixels 10 are distinguished from each other by assigning an identification number 1, 2, 3 or 4 at an end of a reference sign of each of the components in the pixels 10. For example, one of the four pixels 10 includes a photoelectric conversion element PD1 and a transfer transistor TR1. It is to be noted that, in a case where there is no necessity to distinguish the components from each other, the identification numbers are not assigned.

[0042] Although description is given later of a detailed structure, the transfer transistor TR includes a vertical transistor or a vertical gate structure in the first embodiment. That is, the transfer transistor TR is configured as a vertical IGFET. The transfer transistor TR corresponds to a "transfer transistor" according to the present technology.

[0043] The pixel circuit 20 is constructed by the plurality of pixel transistors. Here, the pixel transistors include the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL. Each transistor of the pixel transistors includes a lateral IGFET or a horizontal gate structure.

[0044] One of main electrodes of the reset transistor RST (e.g., a source region) is electrically coupled to another end of the floating diffusion FD. Another one of the main electrodes of the reset transistor RST is electrically coupled to a power supply voltage VDD. A reset signal is inputted to a gate electrode thereof. When being brought into an electrically conductive state, the reset transistor RST resets the floating diffusion FD to a potential corresponding to the power supply voltage VDD.

[0045] One of main electrodes of the amplification transistor AMP is electrically coupled to one of main electrodes of the selection transistor SEL. Another one of the main electrodes of the amplification transistor AMP is electrically coupled to the power supply voltage VDD. The one of the main electrodes of the reset transistor RST and the other end of the floating diffusion FD are electrically coupled to a gate electrode thereof. The amplification transistor AMP configures a source follower amplifier. That is, the amplification transistor AMP generates a pixel signal corresponding to the electric charge transferred through the floating diffusion FD.

[0046] Another one of the main electrodes of the selection transistor SEL is electrically coupled to the vertical signal line Lv. A selection signal is inputted to a gate electrode thereof. The selection transistor SEL outputs the generated pixel signal to the vertical signal line Lv.

[0047] It is to be noted that the pixel circuit 20 may include the FD conversion gain switching transistor FDG. In this case, one of main electrodes of the FD conversion gain switching transistor FDG is electrically coupled to the floating diffusion FD, and another one of the main electrodes of the FD conversion gain switching transistor FDG is electrically coupled to the one of the main electrodes of the reset transistor RST (e.g., the source region). Description is given of a detailed configuration thereof in the seventh embodiment. Further, one pixel circuit 20 may be disposed for two pixels 10, eight pixels 10, or the like, and electric charge from these pixels 10 may be read in the one pixel circuit 20. (4) Device Configuration of Pixel 10

[0048] Fig. 4 illustrates an example of a planar configuration in the first base 1A (also called a structure) of the pixels 10 of the photodetector 1. Fig. 5 illustrates an example of a planar configuration in the second base 1B of the pixels 10 of the photodetector 1. Fig. 6 illustrates an example of a cross-sectional configuration of the pixels 10 illustrated in Fig. 4. Fig. 7 illustrates an example of a cross-sectional configuration of the pixels 10 illustrated in Figs. 4 and 5.

[0049] As described above, the photodetector 1 according to the first embodiment has a three-layer structure. The pixels 10 are disposed in the semiconductor substrate 30 (also called a semiconductor layer) forming the first base 1A constructing the three-layer structure. In addition, the pixel circuit 20 is disposed in the semiconductor substrate 30 forming the first base 1A and in the semiconductor substrate 40 forming the second base 1B.

[0050] The pixel 10 is formed in a square shape in which lengths of respective sides in the arrow-X direction and the arrow-Y direction are equal to each other in a plan view, as illustrated in Figs. 4, 6, and 7. A pixel separation region 31 is disposed at a periphery of a side surface of the pixel 10. It is to be noted that a planar shape of the pixel 10 is not limited to a square shape. For example, the planar shape of the pixel 10 may be a rectangle.

[0051] In the first embodiment, the pixel separation region 31 includes two types of a pixel separation region 31A (also called a separation material) and a pixel separation region 31B (also called a separation material). The pixel separation region 31A is configured to surround at least a periphery of a side surface of the photoelectric conversion element PD. The pixel separation region 31A electrically and optically separates the adjacent pixels 10 from each other. Meanwhile, the pixel separation region 31B is configured to surround peripheries of side surfaces of the transistors, specifically, peripheries of side surfaces of the amplification transistor AMP and the reset transistor RST. The pixel separation region 31B electrically separates the adjacent transistors and the like from each other.

[0052] The pixel separation region 31A includes a trench 311 and a filler 312. The trench 311 is formed as a trench that is dug down deep in a thickness direction of the semiconductor substrate 30 from a surface 30B of the semiconductor substrate 30 toward another surface 30A opposed to the surface 30B. Here, the surface 30B corresponds to a "first surface" according to the present technology. Meanwhile, the surface 30A corresponds to a "second surface" according to the present technology. Further, the trench 311 is extended in the arrow-X direction, and is disposed at a constant interval in the arrow-Y direction. In addition, the trench 311 is extended in the arrow-Y direction, and is disposed at a constant interval in the arrow-X direction. That is, the trench 311 is formed in a lattice pattern in a plan view. The trench 311 is filled with the filler 312. For example, an insulating material such as SiO2is used for the filler 312. Such an insulating material makes it possible to optically and electrically separate the adjacent pixels 10 from each other.

[0053] The pixel separation region 31B includes a trench 313 and a filler 314. The trench 313 is formed as a trench that is dug down more shallowly than the trench 311 in the thickness direction of the semiconductor substrate 30 from the surface 30B of the semiconductor substrate 30 toward the other surface 30A opposed to the surface 30B. The trench 313 is filled with the filler 314. For example, an insulating material such as SiO2is used for the filler 314, in a similar manner to the filler 312. Such an insulating material makes it possible to electrically separate the adjacent transistors from each other.

[0054] The pixel 10 includes the photoelectric conversion element PD and the transfer transistor TR. Fig. 4 illustrates a unit pixel. That is, the four pixels 10 electrically coupled to the one pixel circuit 20 are set as a pixel unit, as illustrated in Fig. 3 described above. The four pixels 10 are two pixels 10 arranged in the arrow-X direction and two pixels 10 arranged in the arrow-Y direction. These four pixels 10 are formed in a shape in line symmetry with respect to an unillustrated centerline passing between the adjacent pixels 10. (4-1) Device Configuration of Photoelectric Conversion Element PD

[0055] Although illustration and description of a detailed structure are omitted, the photoelectric conversion element PD is disposed inside the semiconductor substrate 30 in a region whose periphery in the arrow-X direction and the arrow-Y direction is surrounded by the pixel separation region 31.

[0056] The photoelectric conversion element PD includes a p-type semiconductor region serving as the anode region and an n-type semiconductor region serving as the cathode region. It is to be noted that an unillustrated pinning region is disposed in a surface portion of the semiconductor substrate 30 along the pixel separation region 31A of the pixel separation region 31. The pinning region is formed by a p-type semiconductor region having high impurity density. (4-2) Device Configuration of Transfer Transistor TR

[0057] The transfer transistor TR is disposed on the surface 30B in the pixel separation region 31. The surface 30B is on a side opposite to the arrow-Z direction with respect to the photoelectric conversion element PD. Although illustration and description of a detailed structure are omitted, the transfer transistor TR includes, as main components, a channel formation region, a gate insulating film 321, a gate electrode 322, and the pair of main electrodes (the source region and the drain region).

[0058] In the first embodiment, the transfer transistor TR is configured as a vertical IGFET. That is, the gate electrode 322 is extended in the thickness direction of the semiconductor substrate 30 from the surface 30B of the semiconductor substrate 30 to the photoelectric conversion element PD. The gate insulating film 321 is disposed between the semiconductor substrate 30 and the gate electrode 322.

[0059] The gate insulating film 321 includes, for example, an insulating material such as SiO2. The gate electrode 322 includes, for example, a gate electrode material such as polycrystalline silicon. In a case where the polycrystalline silicon is used for the gate electrode material, an impurity that reduces a resistance value is added to the polycrystalline silicon.

[0060] The one of the pair of main electrodes is electrically coupled to the cathode region of the photoelectric conversion element PD. In other words, the cathode region is used as the one of the main electrodes of the transfer transistor TR. Meanwhile, the other one of the pair of main electrodes is electrically coupled to the floating diffusion FD. Similarly, the floating diffusion FD is used as the other one of the main electrodes of the transfer transistor TR. (4-3) Device Configuration of Floating Diffusion FD

[0061] The floating diffusion FD is disposed at a position close to the gate electrode 322 of the transfer transistor TR in a region whose periphery is surrounded by the pixel separation region 31. To give detailed description, the floating diffusions FD of the respective four pixels 10 are collectively disposed in a middle of the unit pixel. That is, in the pixel 10 including the photoelectric conversion element PD1 and the transfer transistor TR1, the floating diffusion FD is disposed at an upper right corner portion. In the pixel 10 including a photoelectric conversion element PD2 and a transfer transistor TR2, the floating diffusion FD is disposed at an upper left corner portion. In the pixel 10 including a photoelectric conversion element PD3 and a transfer transistor TR3, the floating diffusion FD is disposed at a lower right corner portion. Moreover, in the pixel 10 including a photoelectric conversion element PD4 and a transfer transistor TR4, the floating diffusion FD is disposed at a lower left corner portion.

[0062] The floating diffusion FD is formed by an n-type semiconductor region 330 disposed on a side of the surface 30B of the semiconductor substrate 30 and having a pn junction depth on a side of the surface 30A. The n-type semiconductor region 330 is electrically separated from the semiconductor substrate (p-type semiconductor region) 30 through a pn junction. (4-4) Device Configuration of Electrical Conductor 35

[0063] In the first embodiment, the floating diffusions FD of the respective two pixels 10 adjacent to each other in the arrow-Y direction are shared and electrically coupled to each other through an electrical conductor 35 in the unit pixel. Further, the electrical conductor 35 is electrically coupled to a gate electrode 324 described later of the amplification transistor AMP. As may be appreciated, the electrical conductor 35 may be or include the gate electrode 324, and as such, the two terms may be used interchangeably herein. This allows the floating diffusions FD of the respective four pixels 10 of the unit pixel to be shared and electrically coupled to each other. The four pixels 10 include the two pixels 10 adjacent to each other in the arrow-X direction. The electrical conductor 35 is configured as shared wiring or a shared electrode. In addition, the electrical conductor 35 configures (a portion of) the gate electrode 324 of the amplification transistor AMP. Description is given later of a configuration of the amplification transistor AMP.

[0064] The electrical conductor 35 is disposed to overlap the pixel separation region 31A between the two pixels 10 adjacent to each other in the arrow-Y direction in a plan view. In other words, one end of the electrical conductor 35 is electrically coupled to a side surface of the floating diffusion FD of one of the two pixels 10 adjacent to each other in the arrow-Y direction. Another end of the electrical conductor 35 is electrically coupled, across the pixel separation region 31A, to a side surface of the floating diffusion FD of another one of the two pixels 10 adjacent to each other in the arrow-Y direction. The electrical conductor 35 is embedded from the surface 30B of the semiconductor substrate 30 toward the side of the surface 30A of the semiconductor substrate 30. The electrical conductor 35 includes, for example, a gate electrode material such as polycrystalline silicon or metal including tungsten (W).

[0065] Here, in the first embodiment, the electrical conductor 35 includes, for example, polycrystalline silicon, and the floating diffusion FD is formed by the n-type semiconductor region 330. Accordingly, each of the electrical conductor 35 and the floating diffusion FD is described as a separate component. The electrical conductor 35 is disposed in a current path from the floating diffusion FD to the gate electrode 324 of the amplification transistor AMP. That is, the electrical conductor 35 or a portion thereof configures the floating diffusion FD in the present technology. In addition, also in a case where an electrical conductor is formed between the floating diffusion FD and the electrical conductor 35, the electrical conductor configures the floating diffusion FD in the present technology. The electrical conductor is, for example, a semiconductor region or a diffusion region that electrically couples both of the floating diffusion FD and the electrical conductor 35 to each other. (4-5) Device Configuration of Amplification Transistor AMP

[0066] In the first embodiment, the amplification transistor AMP and the reset transistor RST each constructing the pixel circuit 20 (see Fig. 3) are disposed in the first base 1A.

[0067] The amplification transistor AMP is disposed in the middle of the unit pixel, and overlaps the pixel separation region 31 (the pixel separation region 31A), in a plan view. The pixel separation region 31 partitions the four pixels 10 constructing the unit pixel. The amplification transistor AMP includes, as main components, a channel formation region, a gate insulating film 323, the gate electrode 324, and a pair of main electrodes 325.

[0068] The channel formation region (also called a channel region) of the amplification transistor AMP is formed in a p-type semiconductor region (p-type well region) 300 (also called a semiconductor layer). The p-type semiconductor region 300 is disposed in the pixel separation region 31 on the side of the surface 30B of the semiconductor substrate 30. The gate insulating film 323 is formed on a surface of the p-type semiconductor region 300.

[0069] The gate electrode 324 of the amplification transistor AMP is formed integrally or in an integrated manner on the side of the surface 30B of the electrical conductor 35, and includes the electrical conductor 35. Here, the term "formed integrally" is used to mean that each of the gate electrode 324 and the electrical conductor 35 includes the same electrically conductive material and is formed through the same manufacturing step, and both of the gate electrode 324 and the electrical conductor 35 are continuously formed. Moreover, the term "formed in an integrated manner" is used to mean that each of the gate electrode 324 and the electrical conductor 35 includes the same or a separate electrically conductive material and is formed through a separate manufacturing step, but both of the gate electrode 324 and the electrical conductor 35 are at least electrically coupled to each other.

[0070] Further, the electrical conductor 35 is extended from the surface 30B of the semiconductor substrate 30 to the side of the surface 30A of the semiconductor substrate 30. This allows the electrical conductor 35 to configure a fin (Fin) part of the gate electrode 324 as viewed in the arrow-Y direction (hereinafter, simply referred to as "in a side view"). That is, the amplification transistor AMP includes a fin structure that makes it possible to increase gate capacitance. The gate electrode 324 includes, for example, a gate electrode material, in a similar manner to the electrical conductor 35, for example.

[0071] The pair of main electrodes 325 is disposed on both sides in a gate length direction of the gate electrode 324 centering around the gate electrode 324. The gate length direction coincides with the arrow-Y direction. The pair of main electrodes 325 is disposed to overlap the pixel separation region 31 in a plan view. The pair of main electrodes 325 is each formed by an n-type semiconductor region. That is, the amplification transistor AMP includes an n-channel IGFET. Further, although a reference numeral is omitted, a sidewall spacer is formed on a side wall of the gate electrode 324 of the amplification transistor AMP. (4-6) Device Configuration of Reset Transistor RST

[0072] The reset transistor RST is disposed to overlap the pixel separation region 31 between the pixels 10 adjacent to each other in the arrow-Y direction in a plan view, in a similar manner to the amplification transistor AMP. The reset transistor RST includes, as main components, a channel formation region, a gate insulating film 326, a gate electrode 327, and a pair of main electrodes 328.

[0073] The channel formation region of the reset transistor RST is formed in the p-type semiconductor region 300. The p-type semiconductor region 300 is disposed in the pixel separation region 31 on the side of the surface 30B of the semiconductor substrate 30. The gate insulating film 326 is formed on the surface of the p-type semiconductor region 300.

[0074] The gate electrode 327 of the reset transistor RST is formed on the gate insulating film 326. Here, the gate electrode 327 is formed through the same manufacturing step using the same electrically conductive material as the gate electrode 324 of the amplification transistor AMP.

[0075] The pair of main electrodes 328 is disposed on both sides in a gate length direction of the gate electrode 327 centering around the gate electrode 327. The gate length direction coincides with the arrow X-direction. The pair of main electrodes 328 is disposed to overlap the pixel separation region 31 in a plan view. The pair of main electrodes 328 is each formed by an n-type semiconductor region, in a similar manner to the pair of main electrodes 325 of the amplification transistor AMP. Although a reference numeral is omitted, a sidewall spacer is formed on a side wall of the gate electrode 327 of the reset transistor RST, in a similar manner to the amplification transistor AMP. (4-7) Device Configuration of Selection Transistor SEL

[0076] The selection transistor SEL constructing the pixel circuit 20 (see Fig. 3) is disposed in the second base 1B, as illustrated in Figs. 5 and 7. The second base 1B includes the semiconductor substrate 40. The second base 1B is stacked on the first base 1A with an insulator (interlayer insulator) 301 interposed therebetween. The insulator 301 is disposed on the surface 30B of the semiconductor substrate 30.

[0077] The selection transistor SEL is disposed to overlap a region corresponding to two pixels 10 constructing the unit pixel in a plan view. The selection transistor SEL includes, as main components, a channel formation region, a gate insulating film 423, a gate electrode 424, and a pair of main electrodes 425.

[0078] The channel formation region of the selection transistor SEL is formed in a semiconductor substrate (p-type well region) 40 on a side of a surface 40B of the semiconductor substrate 40. The gate insulating film 423 is formed on a surface of the semiconductor substrate 40. The gate electrode 424 is disposed on the gate insulating film 423. The gate electrode 424 includes a gate electrode material similar to that of the gate electrode 324 of the amplification transistor AMP. The pair of main electrodes 425 is disposed on both sides in a gate length direction of the gate electrode 424 centering around the gate electrode 424. The gate length direction coincides with the arrow-X direction. The pair of main electrodes 425 is each formed by an n-type semiconductor region. Although a reference numeral is omitted, a sidewall spacer is formed on a side wall of the gate electrode 424 of the selection transistor SEL.

[0079] One of the pair of main electrodes 425 of the selection transistor SEL is electrically coupled to one of the pair of main electrodes 325 of the amplification transistor AMP through through-wiring 5 or the like. The through-wiring 5 is formed to penetrate, in the thickness direction, the insulator 301, the semiconductor substrate 40, and the insulator 401 disposed on the surface 40B of the semiconductor substrate 40 of the second base 1B. In addition, unillustrated wiring disposed in the third base 1C is used to electrically couple the selection transistor SEL and the amplification transistor AMP to each other. (4-8) Device Configuration of Coupling Region 36

[0080] In the first embodiment, a coupling region 36 is disposed in a region corresponding to each of four corners of the unit pixel and overlapping the pixel separation region 31, as illustrated in Figs. 4, 6, and 7. The coupling region 36 is electrically coupled to the p-type semiconductor region 300. The coupling region 36 is formed to be of the same electrically conductive type as the p-type semiconductor region 300, and is formed to have higher impurity density than the p-type semiconductor region 300. That is, the coupling region 36 is used as a substrate contact region or a well contact region, and is shared by the adjacent unit pixels. (5) Configuration of Optical Filter 7

[0081] In the pixel 10, each of an optical filter 7 and an optical lens 8 is sequentially disposed on the surface 30A of the semiconductor substrate 30 with a protective film 6 interposed therebetween. The optical filter 7 is formed as, for example, a red color filter that transmits the light L in a band of red light, a green color filter that transmits the light L in a band of green light, or a blue color filter that transmits the light L in a band of blue light. The optical filter 7 may be a filter that transmits near-infrared rays. The optical filter 7 includes, for example, a resin material to which an organic pigment is added. It is possible to use an acrylic resin, a styrene resin, or the like as the resin material. (6) Configuration of Optical Lens 8

[0082] The optical lens 8 is disposed for every pixel 10 or every plurality of pixels 10 in a side view. The optical lens 8 is formed in a curved shape that protrudes in the arrow-Z direction in a side view. The optical lens 8 includes, for example, a light-transmissive resin material. It is to be noted that, although illustration and detailed description are omitted, an antireflection film may be formed on the optical lens 8. The optical lens 8 is joined to another adjacent optical lens 8, and the plurality of optical lenses 8 is integrally formed. The optical lens 8 is configured as an on-chip lens.

[0083] It is to be noted that illustration and detailed description are omitted of the peripheral circuit disposed in the third base 1C of the photodetector 1.Manufacturing Method of Photodetector 1

[0084] Figs. 8 to 33 illustrate an example of a step cross-section for describing the manufacturing method of the photodetector 1 for each of steps. The manufacturing method of the photodetector 1 according to the first embodiment is mainly a manufacturing method of the amplification transistor AMP of the pixel 10 in the first base 1A. The manufacturing method of the photodetector 1 is as follows.

[0085] First, the semiconductor substrate 30 is prepared (see Fig. 8). The semiconductor substrate 30 is in a state of a semiconductor wafer prior to a dicing step, and is in a state in which the photoelectric conversion element PD (see Figs. 6 and 7) is formed.

[0086] Each of a mask 371 and a mask 372 is sequentially formed on the surface 30B of the semiconductor substrate 30, as illustrated in Fig. 8. The mask 371 is formed as a hard mask. The mask 371 is formed as a stack in which each of a first mask and a second mask is sequentially stacked. For example, SiO2is used for the first mask. For example, SiN is used for the second mask. For example, a photoresist is used for the mask 372. The mask 372 has an opening 372H formed in a formation region of the pixel separation region 31A.

[0087] The mask 372 is used to pattern the mask 371, and the trench 311 is subsequently formed from the surface 30B of the semiconductor substrate 30 toward the side of the surface 30A of the semiconductor substrate 30 (see Fig. 9). For example, anisotropic etching such as RIE (Reactive Ion Etching) is used to form the trench 311. The mask 372 is detached, as illustrated in Fig. 9.

[0088] The filler 312 is formed on an entire surface, including a top of the mask 371, of the surface 30B of the semiconductor substrate 30, as illustrated in Fig. 10. The filler 312 is embedded in the trench 311. The filler 312 is formed through, for example, a CVD (Chemical Vapor Deposition) method. Here, the filler 312 includes SiO2. Formation of the filler 312 allows the pixel separation region 31A to be substantially completed by the trench 311 and the filler 312.

[0089] A mask 373 is formed on the filler 312, as illustrated in Fig. 11. The mask 373 has an opening 373H in a region overlapping a portion of the pixel separation region 31A. For example, a photoresist is used for the mask 373.

[0090] The mask 373 is used to remove a portion of the filler 312 of the pixel separation region 31A to form a trench 312H in a portion of the pixel separation region 31A, as illustrated in Fig. 12. For example, anisotropic etching is used to form the trench 312H. Thereafter, the mask 373 is detached.

[0091] A semiconductor layer 300S is formed in the trench 312H, as illustrated in Fig. 13. The semiconductor layer 300S is, for example, a monocrystalline silicon layer grown through epitaxial growth.

[0092] Here, a p-type impurity is introduced into the semiconductor layer 300S to form the p-type semiconductor region 300 from the semiconductor layer 300S, as illustrated in Fig. 14. The p-type impurity is introduced through an ion implantation method.

[0093] The unnecessary filler 312 and the mask 373 are removed on the surface 30B of the semiconductor substrate 30 to planarize the surface 30B, as illustrated in Fig. 15. For example, a CMP (Chemical Mechanical Polishing) method is used for such planarization.

[0094] Each of a mask 374 and a mask 375 is sequentially formed on the surface 30B of the semiconductor substrate 30, as illustrated in Fig. 16. The mask 374 is formed as a hard mask. The mask 374 is formed as a stack in which each of the first mask and the second mask is sequentially stacked. For example, SiO2is used for the first mask. For example, SiN is used for the second mask. For example, a photoresist is used for the mask 375. The mask 375 has an opening 375H formed in a formation region of the pixel separation region 31B.

[0095] The mask 375 is used to pattern the mask 374, and a trench 313 is subsequently formed from the surface 30B of the semiconductor substrate 30 toward the side of the surface 30A of the semiconductor substrate 30 (see Fig. 17). For example, anisotropic etching is used to form the trench 313. The mask 375 is detached, as illustrated in Fig. 17.

[0096] The filler 314 is formed on the entire surface, including a top of the mask 374, of the surface 30B of the semiconductor substrate 30, as illustrated in Fig. 18. The filler 314 is embedded in the trench 313. The filler 314 is formed through, for example, a CVD method. Here, the filler 314 includes SiO2. Formation of the filler 314 allows the pixel separation region 31B to be substantially completed by the trench 313 and the filler 314. Further, formation of the pixel separation region 31B allows the pixel separation region 31 including the pixel separation region 31A and the pixel separation region 31B to be substantially completed.

[0097] The unnecessary filler 314 is removed on the surface 30B of the semiconductor substrate 30 to planarize the surface 30B, as illustrated in Fig. 19. For example, a CMP method is used for such planarization.

[0098] A mask 376 is formed on the surface 30B of the semiconductor substrate 30, as illustrated in Fig. 20. For example, a photoresist is used for the mask 376. The mask 376 has an opening 376H formed in a formation region of the electrical conductor 35, which is a portion of the pixel separation region 31. The formation region of the electrical conductor 35 is also a formation region of the gate electrode 324 of the amplification transistor AMP, and is further also a formation region of the shared wiring that couples the floating diffusions FD to each other.

[0099] The mask 376 is used to dig down the filler 312 of the pixel separation region 31, thereby forming a trench 35H. For example, anisotropic etching is used to form the trench 35H. The mask 376 is detached, as illustrated in Fig. 21.

[0100] A gate insulating film 323A is formed on the entire surface of the surface 30B of the semiconductor substrate 30, as illustrated in Fig. 22. The gate insulating film 323A is formed at least in a formation region of each of the amplification transistor AMP, the reset transistor RST, and the transfer transistor TR. The gate insulating film 323A is formed using, for example, SiO2through, for example, a thermal oxidation method.

[0101] A gate electrode material 324A is formed on the gate insulating film 323A, as illustrated in Fig. 23. The gate electrode material 324A is formed using, for example, polycrystalline silicon through, for example, a CVD method. The gate electrode material 324A is formed as a portion of the gate electrode 324 of the amplification transistor AMP.

[0102] A mask 377 is formed on the gate electrode material 324A, as illustrated in Fig. 24. For example, a photoresist is used for the mask 377. The mask 377 has an opening 377H formed in the formation region of the electrical conductor 35.

[0103] The mask 377 is used to remove a portion of the gate electrode material 324A. For example, anisotropic etching is used for such removal. The mask 377 is detached, as illustrated in Fig. 25.

[0104] The gate electrode material 324A is used as a mask to remove the gate insulating film 323A exposed from the gate electrode material 324A, as illustrated in Fig. 26. That is, the gate insulating film 323A is patterned. This allows each of the gate insulating film 321 of the transfer transistor TR, the gate insulating film 323 of the amplification transistor AMP, and the gate insulating film 326 of the reset transistor RST to be formed from the gate insulating film 323A.

[0105] A gate electrode material 324B is newly formed on an entire surface of the gate electrode material 324A, as illustrated in Fig. 27. The gate electrode material 324B is formed using, for example, polycrystalline silicon through, for example, a CVD method. The gate electrode material 324B is formed as a portion of each of the gate electrode 322 of the transfer transistor TR, the gate electrode 324 of the amplification transistor AMP, and the gate electrode 327 of the reset transistor RST. Further, formation of the gate electrode material 324B allows the gate electrode material 324B to be embedded in the trench 35H of the pixel separation region 31. The electrical conductor 35 is formed from the gate electrode material 324B.

[0106] The unnecessary gate electrode material 324B is removed on the surface 30B of the semiconductor substrate 30 to planarize the surface of the gate electrode material 324B, as illustrated in Fig. 28. For example, a CMP method is used for such planarization.

[0107] A mask 378 is formed on the gate electrode material 324B, as illustrated in Fig. 29. For example, a photoresist is used for the mask 378. The mask 378 has an opening 378H formed in a formation region of each of the gate electrode 322 of the transfer transistor TR, the gate electrode 324 of the amplification transistor AMP, and the gate electrode 327 of the reset transistor RST.

[0108] The mask 378 is used to pattern the gate electrode material 324B. For example, anisotropic etching is used for patterning. This allows each of the gate electrode 322 of the transfer transistor TR, the gate electrode 324 of the amplification transistor AMP, and the gate electrode 327 of the reset transistor RST to be formed from the gate electrode material 324B (see Fig. 30). The mask 378 is detached, as illustrated in Fig. 30.

[0109] Although a reference numeral is omitted, a sidewall spacer is formed on a side wall of the gate electrode 322 and the side wall of each of the gate electrode 324 and the gate electrode 327, as illustrated in Fig. 31. For example, the sidewall spacer is formed as an insulator whose film is formed through a CVD method, a sputtering method, or the like, followed by being subjected to anisotropic etching by an amount corresponding to an amount of the formed film. The insulator includes SiN or the like.

[0110] A mask 379 is subsequently formed on the entire surface of the surface 30B of the semiconductor substrate 30 (see Fig. 32). For example, a photoresist is used for the mask 379. The mask 379 has an opening 379H formed in a formation region of each of the floating diffusion FD, the pair of main electrodes 325 of the amplification transistor AMP, and the pair of main electrodes 328 of the reset transistor RST. The mask 379 is used to form each of the floating diffusion FD, the pair of main electrodes 325, and the pair of main electrodes 328, as illustrated in Fig. 32. These are each formed as a component into which an n-type impurity is introduced through, for example, an ion implantation method. The mask 379 is subsequently detached.

[0111] Here, formation of the floating diffusion FD allows for formation of the floating diffusion FD in a state of being electrically coupled to a side surface of the electrical conductor 35. In addition, the floating diffusions FD of the respective adjacent pixels 10 are electrically coupled to each other through the electrical conductor 35 serving as the shared wiring. In addition, formation of the pair of main electrodes 325 allows for formation of the amplification transistor AMP. The amplification transistor AMP is formed as the gate electrode 324 including the electrical conductor 35, and is thus formed in the fin structure. Moreover, the gate electrode 324 is electrically coupled to the floating diffusion FD with the electrical conductor 35 interposed therebetween. Further, formation of the floating diffusion FD (the n-type semiconductor region 330) allows for formation of the transfer transistor TR. In addition, formation of the pair of main electrodes 328 allows for formation of the reset transistor RST.

[0112] A mask 380 is subsequently formed on the entire surface of the surface 30B of the semiconductor substrate 30. For example, a photoresist is used for the mask 380. The mask 380 has an opening 380H formed in a formation region of the coupling region 36 overlapping the pixel separation region 31 (see Fig. 33). The mask 380 is used to form the coupling region 36, as illustrated in Fig. 33. The coupling region 36 is formed as a region into which a p-type impurity is introduced through, for example, an ion implantation method. The mask 380 is subsequently detached.

[0113] Subsequently, the insulator 301, the second base 1B, the selection transistor SEL, the insulator 401, the through-wiring 5, and the like are formed sequentially. This allows for completion of the photodetector 1 according to the first embodiment, as illustrated in Figs. 4 to 7 described above. Workings and Effects

[0114] The photodetector 1 according to the first embodiment includes the photoelectric conversion element PD, the floating diffusion FD, the electrical conductor 35, and the amplification transistor AMP, as illustrated in Figs. 4 to 7. The photoelectric conversion element PD is disposed inside the first base 1A, and converts light into electric charge. The floating diffusion FD is disposed on the surface 30B of the first base 1A, and is electrically coupled to the photoelectric conversion element PD. The electrical conductor 35 is electrically coupled to the side surface of the floating diffusion FD. The amplification transistor AMP includes the gate electrode 324 including the electrical conductor 35. In the photodetector 1 having such a configuration, the gate electrode 324 of the amplification transistor AMP is electrically coupled to the side surface of the floating diffusion FD through the electrical conductor 35. That is, it is possible to shorten, to the utmost, a length of a wiring path from the floating diffusion FD to the gate electrode 324 of the amplification transistor AMP. This makes a parasitic capacitance value to be added to the wiring path extremely small, thus making it possible to effectively suppress random noise. This enables charge conversion efficiency to improve from the photoelectric conversion element PD to the pixel circuit 20.

[0115] In addition, in the photodetector 1, the electrical conductor 35 is embedded in the semiconductor substrate 30 of the first base 1A from the surface 30B toward the side of the surface 30A, as illustrated in Figs. 6 and 7. That is, the electrical conductor 35 configures the fin part of the gate electrode 324. The fin part is extended from the surface 30B toward the side of the surface 30A. The amplification transistor AMP includes the fin structure. The photodetector 1 having such a configuration makes it possible to expand a gate width dimension of the amplification transistor AMP. This enables a current driving capability of the amplification transistor AMP to improve. Consequently, this makes it possible to reduce an occupied area of the amplification transistor AMP to reduce an area of the pixel 10.

[0116] Moreover, in the photodetector 1, the electrical conductor 35 is formed integrally or in an integrated manner with the gate electrode 324 of the amplification transistor AMP, as illustrated in Figs. 6 and 7. As described above, the photodetector 1 having such a configuration makes it possible to shorten, to the utmost, the length of the wiring path from the floating diffusion FD to the gate electrode 324 of the amplification transistor AMP.

[0117] Further, in the photodetector 1, the electrical conductor 35 is formed as the shared wiring that electrically couples to each other the floating diffusions FD disposed in respective ones of the plurality of pixels 10 adjacent to each other, as illustrated in Figs. 4 and 6. In the photodetector 1 having such a configuration, wiring that electrically couples the plurality of floating diffusions FD to each other, a coupling region between the wiring and the floating diffusions FD, and the like are not necessary. This makes it possible to further reduce the area of the pixel 10.

[0118] Furthermore, in the photodetector 1, the electrical conductor 35 is disposed to overlap the pixel separation region 31 in a plan view, as illustrated in Figs. 4 and 6. In the photodetector 1 having such a configuration, the electrical conductor 35 is disposed by using an occupied area of the pixel separation region 31. This makes it possible to further reduce an occupied area of the pixel 10, as compared with a case where each of the pixel separation region 31 and the electrical conductor 35 is disposed in a separate region.

[0119] In addition, in the photodetector 1, the amplification transistor AMP is disposed to overlap the pixel separation region 31 in a plan view, as illustrated in Figs. 4 and 6. In the photodetector 1 having such a configuration, the amplification transistor AMP is disposed by using the occupied area of the pixel separation region 31. This makes it possible to further reduce the occupied area of the pixel 10, as compared with a case where each of the pixel separation region 31 and the amplification transistor AMP is disposed in a separate region.

[0120] Moreover, in the photodetector 1, the reset transistor RST is disposed to overlap the pixel separation region 31 in a plan view, as illustrated in Figs. 4 and 6. In the photodetector 1 having such a configuration, the reset transistor RST is disposed by using the occupied area of the pixel separation region 31. This makes it possible to further reduce the occupied area of the pixel 10, as compared with a case where each of the pixel separation region 31 and the reset transistor RST is disposed in a separate region. <2. Second Embodiment>

[0121] Description is given of the photodetector 1 according to the second embodiment of the present disclosure with reference to Fig. 34. It is to be noted that, in the second embodiment and embodiments hereinafter, the same components or substantially the same components as the components of the photodetector 1 according to the first embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.Device Configuration of Photodetector 1

[0122] Fig. 34 illustrates an example of a cross-sectional configuration of the pixels 10 of the photodetector 1. In the photodetector 1 according to the second embodiment, one of the main electrodes 328 (e.g., a source region) of the reset transistor RST is electrically coupled to the gate electrode 324 of the amplification transistor AMP through wiring 302.

[0123] The wiring 302 is disposed in the insulator 301. Wiring (plug wiring) 303 is used to electrically couple the main electrode 328 and the wiring 302 to each other. Similarly, the wiring 303 is also used to electrically couple the gate electrode 324 and the wiring 302 to each other. For example, the wiring 303 includes an electrically conductive material such as copper (Cu), polycrystalline silicon (poly-Si), or tungsten.

[0124] Components other than the above-described components of the second embodiment are the same or substantially the same as the components of the photodetector 1 according to the first embodiment.Workings and Effects

[0125] The photodetector 1 according to the second embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the first embodiment.

[0126] In addition, in the photodetector 1, the one of the main electrodes 328 of the reset transistor RST is electrically coupled to the gate electrode 324 of the amplification transistor AMP through the wiring 302, as illustrated in Fig. 34. The photodetector 1 having such a configuration makes it possible to add coupling capacitance of the wiring 302 to a wiring path between the gate electrode 324 of the amplification transistor AMP and the one of the main electrodes 328 of the reset transistor RST. This allows for easy reading, in the pixel circuit 20, of the electric charge converted by the photoelectric conversion element PD. <3. Third Embodiment>

[0127] Description is given of the photodetector 1 according to the third embodiment of the present disclosure with reference to Fig. 35. Device Configuration of Photodetector 1

[0128] Fig. 35 illustrates an example of a cross-sectional configuration of the pixels 10 of the photodetector 1. In the photodetector 1 according to the third embodiment, the electrical conductor 35 is extended to the channel formation region of the amplification transistor AMP, and the electrical conductor 35 extended to the channel formation region is formed integrally or in an integrated manner with the gate electrode 324. In other words, the gate electrode 324 is formed by using the electrical conductor 35. In the third embodiment, the fin part is removed. Accordingly, the amplification transistor AMP is not a fin structure.

[0129] Components other than the above-described components of the third embodiment are the same or substantially the same as the components of the photodetector 1 according to the first embodiment. Workings and Effects

[0130] The photodetector 1 according to the third embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the first embodiment.

[0131] Further, in the photodetector 1, the electrical conductor 35 is extended to the channel formation region of the amplification transistor AMP, and is formed integrally or in an integrated manner with the gate electrode 324, as illustrated in Fig. 35. The photodetector 1 having such a configuration makes it possible to simplify a structure of and the manufacturing method of the gate electrode 324, including the electrical conductor 35, of the amplification transistor AMP. <4. Fourth Embodiment>

[0132] Description is given of the photodetector 1 according to the fourth embodiment of the present disclosure with reference to Fig. 36. Device Configuration of Photodetector 1

[0133] Fig. 36 illustrates an example of a cross-sectional configuration of the pixels 10 of the photodetector 1. In the photodetector 1 according to the fourth embodiment, a p-type semiconductor region 31C is disposed in the pixel separation region 31 on the side of the surface 30B of the semiconductor substrate 30. The p-type semiconductor region 31C is configured as a portion of the pixel separation region 31. In addition, a p-type well region 305 is disposed on the side of the surface 30A of the p-type semiconductor region 300 in which the amplification transistor AMP and the like are disposed. The p-type well region 305 is formed to be of the same electrically conductive type as the p-type semiconductor region 300, and is formed to have higher impurity density than the p-type semiconductor region 300. The p-type well region 305 and the p-type semiconductor region 300 are electrically coupled to each other. The p-type well region 305 is formed to have a sheet resistance value lower than a sheet resistance value of the p-type semiconductor region 300. That is, the p-type well region 305 makes it possible to improve a rate of power supply from the coupling region 36.

[0134] Components other than the above-described components of the fourth embodiment are the same or substantially the same as the components of the photodetector 1 according to the first embodiment. Workings and Effects

[0135] The photodetector 1 according to the fourth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the first embodiment. <5. Fifth Embodiment>

[0136] Description is given of the photodetector 1 according to the fifth embodiment of the present disclosure with reference to Fig. 37. Device Configuration of Photodetector 1

[0137] Fig. 37 illustrates an example of a planar configuration of the pixels 10 of the photodetector 1. In the photodetector 1 according to the fifth embodiment, the selection transistor SEL is disposed on the surface 30B of the semiconductor substrate 30 of the first base 1A, in a similar manner to the amplification transistor AMP and the reset transistor RST.

[0138] The selection transistor SEL is disposed to overlap the pixel separation region 31 in a plan view, in a similar manner to the reset transistor RST. In addition, the selection transistor SEL includes, as main components, the gate insulating film 326, the gate electrode 327, and the pair of main electrodes 328, in a similar manner to the reset transistor RST.

[0139] Further, in the fifth embodiment, the pixel circuit 20 includes the FD conversion gain switching transistor FDG (see Fig. 41). The FD conversion gain switching transistor FDG is disposed to overlap the pixel separation region 31 in a plan view, in a similar manner to the reset transistor RST. Furthermore, the FD conversion gain switching transistor FDG includes, as main components, the gate insulating film 326, the gate electrode 327, and the pair of main electrodes 328, in a similar manner to the reset transistor RST.

[0140] In the fifth embodiment, the amplification transistor AMP is disposed in the middle of the unit pixel. The selection transistor SEL is disposed on an extension in the gate length direction (the arrow-Y direction) of the amplification transistor AMP. In addition, the reset transistor RST is disposed on one of extensions in a gate width direction (the arrow-X direction) of the amplification transistor AMP. The FD conversion gain switching transistor FDG is disposed on another one of the extensions in the gate width direction of the amplification transistor AMP.

[0141] Components other than the above-described components of the fifth embodiment are the same or substantially the same as the components of the photodetector 1 according to the first embodiment. Workings and Effects

[0142] The photodetector 1 according to the fifth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the first embodiment.

[0143] Further, in the photodetector 1, the amplification transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD conversion gain switching transistor FDG each constructing the pixel circuit 20 are disposed in the first base 1A, as illustrated in Fig. 37. This makes it possible to combine the second base 1B with the first base 1A, which are illustrated in Fig. 2 described above, into one base. This enables the photodetector 1 to be constructed in a two-layer structure. <6. Sixth Embodiment>

[0144] Description is given of the photodetector 1 according to the sixth embodiment of the present disclosure with reference to Figs. 38 to 40. Device Configuration of Photodetector 1

[0145] Fig. 38 illustrates an example of a planar configuration of the pixels 10 and a portion of the pixel circuit 20 of the photodetector 1. Fig. 39 illustrates an example of a planar configuration of another portion of the pixel circuit 20 of the photodetector 1. Fig. 40 illustrates an example of a cross-sectional configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1.

[0146] In the photodetector 1 according to the sixth embodiment, the amplification transistor AMP constructing the pixel circuit 20 is disposed in the first base 1A. The reset transistor RST, the selection transistor SEL, and the FD conversion gain switching transistor FDG each constructing the pixel circuit 20 are disposed in the second base 1B.

[0147] Components other than the above-described components of the sixth embodiment are the same or substantially the same as the components of the photodetector 1 according to the first embodiment or the photodetector 1 according to the second embodiment. Workings and Effects

[0148] The photodetector 1 according to the sixth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the first embodiment. <7. Seventh Embodiment>

[0149] Description is given of the photodetector 1 according to the seventh embodiment of the present disclosure with reference to Figs. 41 to 44.Circuit Configuration of Pixel 10 and Pixel Circuit 20 of Photodetector 1

[0150] Fig. 41 illustrates an example of a circuit configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1. As illustrated in Fig. 41, the photodetector 1 according to the seventh embodiment further includes the FD conversion gain switching transistor FDG in the pixel circuit 20, in addition to the pixels 10 and the pixel circuit 20 of the photodetector 1 according to the first embodiment, which are illustrated in Fig. 3 described above. Detailed description is given of this point. As described above, the FD conversion gain switching transistor FDG is disposed between the floating diffusion FD and the reset transistor RST. The one of the main electrodes (e.g., a source region) of the FD conversion gain switching transistor FDG is electrically coupled to the floating diffusion FD. The other one of the main electrodes (e.g., a drain region) of the FD conversion gain switching transistor FDG is electrically coupled to the one of the main electrodes (e.g., the source region) of the reset transistor RST. The other one of the main electrodes (e.g., a drain region) of the reset transistor RST is electrically coupled to the power supply voltage VDD. Device Configuration of Photodetector 1

[0151] Fig. 42 illustrates an example of a planar configuration in the first base 1A of the pixels 10 and the pixel circuit 20 of the photodetector 1. Figs. 43 and 44 each illustrate an example of a cross-sectional configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1. (1) Device Configuration of Pixel Separation Region 31

[0152] The pixel separation region 31 of the photodetector 1 according to the seventh embodiment includes the p-type semiconductor region 31C disposed on the side of the surface 30B of the semiconductor substrate 30, in a similar manner to the pixel separation region 31 of the photodetector 1 according to the fourth embodiment. (2) Device Configuration of Electrical Conductor 35

[0153] The electrical conductor 35 of the photodetector 1 according to the seventh embodiment is disposed to overlap the pixel separation region 31 in a plan view, in a similar manner to the electrical conductor 35 of the photodetector 1 according to the first embodiment. Detailed description is given of this point. In the unit pixel, the electrical conductor 35 is electrically coupled to the floating diffusions FD of the respective two pixels 10 adjacent to each other in the arrow-X direction, and is shared by the two pixels 10. In other words, in the unit pixel, the electrical conductor 35 is electrically coupled to two transfer transistors TR adjacent to each other in the arrow-X direction, and is used as the shared wiring for the two transfer transistors TR. In the unit pixel, two electrical conductors 35 are disposed to be spaced apart from each other in the arrow-Y direction.

[0154] The electrical conductor 35 is embedded in the pixel separation region 31, in a similar manner to the electrical conductor 35 of the first embodiment. This allows the side surface of the electrical conductor 35 and the side surface of the floating diffusion FD to be electrically coupled to each other. Here, the floating diffusion FD is formed by the n-type semiconductor region 330. In other words, the n-type semiconductor region 330 is also the main electrode of the transfer transistor TR. Meanwhile, in the seventh embodiment, the electrical conductor 35 includes, for example, polycrystalline silicon to which an n-type impurity is added.

[0155] Accordingly, electrically coupling the side surface of the floating diffusion FD and the side surface of the electrical conductor 35 to each other involves interposition of a diffusion region 35n therebetween. The diffusion region 35n is diffused in a lateral direction from the side surface of the electrical conductor 35 along the surface 30B. The diffusion region 35n is of an n-type, which is the same electrically conductive type as the n-type impurity added to the electrical conductor 35 and the floating diffusion FD (the n-type semiconductor region 330).

[0156] Further, the electrical conductor 35 is electrically coupled to the transfer transistor TR with the floating diffusion FD interposed therebetween. It is to be noted that, in a case where the electrical conductor 35 includes metal, no diffusion region 35n is formed. (3) Device Configuration of Amplification Transistor AMP

[0157] The amplification transistor AMP of the photodetector 1 according to the seventh embodiment is disposed to overlap the pixel separation region 31 in a plan view, in a similar manner to the amplification transistor AMP of the photodetector 1 according to the first embodiment. The pixel separation region 31 partitions four pixels 10 constructing the unit pixel. Detailed description is given of this point. The amplification transistor AMP is disposed in the middle of the unit pixel. In other words, the amplification transistor AMP is formed in a shape that is sandwiched between the two electrical conductors 35 disposed in the arrow-Y direction.

[0158] The amplification transistor AMP includes, as main components, a channel formation region, the gate insulating film 323, the gate electrode 324, and the pair of main electrodes 325.

[0159] Although a reference numeral is omitted, the channel formation region is formed in a surface portion of the p-type semiconductor region 31C of the pixel separation region 31. Here, an impurity adapted to form a channel is introduced into the surface portion of the p-type semiconductor region 31C.

[0160] The gate insulating film 323 is disposed on the channel formation region. In addition, the gate electrode 324 is disposed on the gate insulating film 323. A gate length direction intermediate portion of the gate electrode 324 is formed to extend in each of the arrow-Y direction and a direction opposite to the arrow-Y direction, and to be overlapped with the electrical conductor 35 in a plan view. In other words, the gate electrode 324 is formed in a shape that is caused to partially protrude in the gate width direction. A via hole (or a contact hole) 323H is disposed in the gate insulating film 323 in an overlapping region between the electrical conductor 35 and an extension part of the gate electrode 324. The gate electrode 324 and the electrical conductor 35 are each electrically coupled to each other through the via hole 323H. The pair of main electrodes 325 is disposed on both sides in the gate length direction of the gate electrode 324 centering around the gate electrode 324. The pair of main electrodes 325 is overlapped with the pixel separation region 31. (4) Device Configuration of FD Conversion Gain Switching Transistor FDG

[0161] The FD conversion gain switching transistor FDG is disposed to overlap the pixel separation region 31 from between the pixels 10 adjacent to each other in the arrow-X direction to between the unit pixels adjacent to each other in the arrow-Y direction in a plan view. The FD conversion gain switching transistor FDG includes, as main components, a channel formation region, the gate insulating film 326, the gate electrode 327, and the pair of main electrodes 328.

[0162] Although a reference numeral is omitted, the channel formation region is formed in the surface portion of the p-type semiconductor region 31C of the pixel separation region 31, in a similar manner to the amplification transistor AMP. The gate insulating film 326 is disposed on the channel formation region. Moreover, the gate electrode 327 is disposed on the gate insulating film 326. One of the main electrodes 328 extended in the arrow-Y direction is disposed at one location in the gate length direction of the gate electrode 327, and another one of the main electrodes 328 extended in the arrow-X direction is disposed at another location in the gate length direction of the gate electrode 327 centering around the gate electrode 327. That is, the FD conversion gain switching transistor FDG is disposed to be bent from the arrow-X direction to the arrow-Y direction, and to be overlapped with the pixel separation region 31.

[0163] The one of the pair of main electrodes 328 (e.g., the source region) of the FD conversion gain switching transistor FDG is electrically coupled to the electrical conductor 35. Detailed description is given of this point. That is, the one of the main electrodes (n-type semiconductor regions) 328 is electrically coupled to the side surface of the electrical conductor 35 with the diffusion region 35n interposed therebetween. The diffusion region 35n is diffused from the side surface of the electrical conductor 35. In other words, the floating diffusion FD and the one of the main electrodes 328 of the FD conversion gain switching transistor FDG are each electrically coupled to each other by the shortest distance through the electrical conductor 35 without use of wiring disposed in an upper layer. (5) Device Configuration of Reset Transistor RST

[0164] The reset transistor RST is disposed between the unit pixels adjacent to each other in the arrow-Y direction, and is disposed to overlap the pixel separation region 31, in a plan view. The reset transistor RST includes, as main components, a channel formation region, the gate insulating film 326, the gate electrode 327, and the pair of main electrodes 328, in a similar manner to the FD conversion gain switching transistor FDG.

[0165] The pair of main electrodes 328 is disposed on both sides in the gate length direction of the gate electrode 327 centering around the gate electrode 327. The one of the main electrodes 328 is formed integrally with another one of the main electrodes 328 of the FD conversion gain switching transistor FDG. That is, the one of the main electrodes 328 of the reset transistor RST is electrically coupled to the electrical conductor 35 with the FD conversion gain switching transistor FDG interposed therebetween.

[0166] It is to be noted that the pixel circuit 20 includes the FD conversion gain switching transistor FDG in the seventh embodiment. In a case where the pixel circuit 20 does not include the FD conversion gain switching transistor FDG in a similar manner to the pixel circuit 20 of the first embodiment described above, the one of the main electrodes 328 of the reset transistor RST is electrically coupled directly or in a direct manner to the electrical conductor 35. Here, the term "coupled directly" means that the electrical conductor 35 and the one of the main electrodes 328 are each electrically coupled to each other with no region such as the diffusion region 35n interposed therebetween. In addition, the term "coupled in a direct manner" means that the electrical conductor 35 and the one of the main electrodes 328 are each electrically coupled to each other with a region such as the diffusion region 35n interposed therebetween. (6) Device Configuration of Selection Transistor SEL

[0167] The selection transistor SEL is disposed between the pixels 10 adjacent to each other in the arrow-Y direction, and is disposed to overlap the pixel separation region 31, in a plan view. The selection transistor SEL includes, as main components, a channel formation region, the gate insulating film 326, the gate electrode 327, and the pair of main electrodes 328, in a similar manner to the reset transistor RST.

[0168] The pair of main electrodes 328 is disposed on both sides in the gate length direction of the gate electrode 327 centering around the gate electrode 327. One of the main electrodes 328 is formed integrally with another one of the main electrodes 325 of the amplification transistor AMP.

[0169] Components other than the above-described components of the seventh embodiment are the same or substantially the same as the components of the photodetector 1 according to the first embodiment. It is to be noted that illustration and description of the optical filter 7 and the optical lens 8 of the photodetector 1 according to the first embodiment are omitted in the seventh embodiment, and the eighth embodiment and the ninth embodiment described later. Workings and Effects

[0170] The photodetector 1 according to the seventh embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the first embodiment.

[0171] In addition, the photodetector 1 includes the photoelectric conversion element PD, the floating diffusion FD, the electrical conductor 35, and the amplification transistor AMP, as illustrated in Figs. 42 to 44. The photoelectric conversion element PD is disposed inside the first base 1A, and converts light into electric charge. The floating diffusion FD is disposed on the surface 30B of the first base 1A, and is electrically coupled to the photoelectric conversion element PD. The electrical conductor 35 is electrically coupled to the floating diffusion FD. A portion of the gate electrode 324 of the amplification transistor AMP is disposed to be overlapped with the electrical conductor 35 to electrically couple the gate electrode 324 to the electrical conductor 35. Here, the gate electrode 324 and the electrical conductor 35 are each electrically coupled to each other through the via hole 323H formed in the gate insulating film 323. In the photodetector 1 having such a configuration, the gate electrode 324 of the amplification transistor AMP is electrically coupled to the floating diffusion FD with the electrical conductor 35 interposed therebetween. That is, it is possible to shorten, to the utmost, the length of the wiring path from the floating diffusion FD to the gate electrode 324 of the amplification transistor AMP. This makes the parasitic capacitance value to be added to the wiring path extremely small, thus making it possible to effectively suppress the random noise. This enables the charge conversion efficiency to improve from the photoelectric conversion element PD to the pixel circuit 20.

[0172] Moreover, the photodetector 1 includes the photoelectric conversion element PD, the floating diffusion FD, the pixel separation region 31, the electrical conductor 35, and the reset transistor RST, as illustrated in Figs. 42 to 44. The photoelectric conversion element PD is disposed inside the first base 1A, and converts light into electric charge. The floating diffusion FD is disposed on the surface 30B of the first base 1A, and is electrically coupled to the photoelectric conversion element PD. The pixel separation region 31 is disposed between the photoelectric conversion element PD and another photoelectric conversion element PD adjacent to the photoelectric conversion element PD, and electrically or optically separates the photoelectric conversion element PD from the other photoelectric conversion element PD. The electrical conductor 35 is disposed to overlap the pixel separation region 31, and is electrically coupled to the floating diffusion FD. One main electrode 328 of the pair of main electrodes 328 of the reset transistor RST is electrically coupled to the electrical conductor 35, and another main electrode 328 of the pair of main electrodes 328 of the reset transistor RST is electrically coupled to the power supply voltage VDD. In the photodetector 1 having such a configuration, the one of the main electrodes 328 of the reset transistor RST is electrically coupled to the floating diffusion FD with the electrical conductor 35 interposed therebetween. Here, the floating diffusion FD is electrically coupled to the reset transistor RST with each of the electrical conductor 35 and the FD conversion gain switching transistor FDG interposed therebetween. That is, it is possible to shorten, to the utmost, a length of a wiring path from the floating diffusion FD to the reset transistor RST. This makes the parasitic capacitance value to be added to the wiring path extremely small, thus making it possible to effectively suppress the random noise. This enables the charge conversion efficiency to improve from the photoelectric conversion element PD to the pixel circuit 20.

[0173] Further, in the photodetector 1, the electrical conductor 35 is coupled to the FD conversion gain switching transistor FDG or the reset transistor RST with the diffusion region 35n and the one of the main electrodes 328 interposed therebetween, as illustrated in Figs. 43 and 44. The diffusion region 35n is of the same electrically conductive type as the one of the main electrodes 328, and is diffused from the side surface of the electrical conductor 35 along the surface 30B. Providing the one of main electrodes 328 and the diffusion region 35n makes it possible to electrically couple the electrical conductor 35 and the FD conversion gain switching transistor FDG or the reset transistor RST to each other reliably. <8. Eighth Embodiment>

[0174] Description is given of the photodetector 1 according to the eighth embodiment of the present disclosure with reference to Figs. 45 to 47. Device Configuration of Photodetector 1 Fig. 45 illustrates an example of a planar configuration in the first base 1A of the pixels 10 and the pixel circuit 20 of the photodetector 1. Figs. 46 and 47 each illustrate an example of a cross-sectional configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1.

[0175] The photodetector 1 according to the eighth embodiment has a configuration of the electrical conductor 35 changed from the photodetector 1 according to the seventh embodiment. Detailed description is given of this point. The electrical conductor 35 is formed by an n-type semiconductor region formed from the surface 30B of the semiconductor substrate 30 toward the side of the surface 30A of the semiconductor substrate 30 to overlap the pixel separation region 31. That is, the electrical conductor 35 is disposed in the semiconductor substrate 30 (the first base 1A). The electrical conductor 35 is formed as a surface portion of the pixel separation region 31 into which an n-type impurity is implanted through, for example, an ion implantation method, followed by activating the implanted n-type impurity. The n-type impurity is isotropically diffused by activation. This allows the electrical conductor 35 to also include a region similar to the above-described diffusion region 35n diffused in the lateral direction.

[0176] The electrical conductor 35 is electrically coupled to the gate electrode 324 of the amplification transistor AMP through the via hole 323H formed in the gate insulating film 323, in a similar to the electrical conductor 35 of the seventh embodiment.

[0177] In addition, an element separation region 31D is disposed between the electrical conductor 35 and the channel formation region of the amplification transistor AMP. Although a reference numeral is omitted, the element separation region 31D includes, for example, a trench and an insulating material with which the trench is filled.

[0178] Components other than the above-described components of the eighth embodiment are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment. Workings and Effects

[0179] The photodetector 1 according to the eighth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the seventh embodiment. <9. Ninth Embodiment>

[0180] Description is given of the photodetector 1 according to the ninth embodiment of the present disclosure with reference to Figs. 48 and 49. Device Configuration of Photodetector 1 Figs. 48 and 49 each illustrate an example of a cross-sectional configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1.

[0181] The photodetector 1 according to the ninth embodiment has a configuration of the electrical conductor 35 changed from the photodetector 1 according to the seventh embodiment. Detailed description is given of this point. The electrical conductor 35 is disposed on the surface 30B of the semiconductor substrate 30 to overlap the pixel separation region 31. The electrical conductor 35 includes, for example, polycrystalline silicon or metal. Here, each of the electrical conductor 35 and the gate electrode 324 of the amplification transistor AMP includes the same electrically conductive material, and is formed through a separate manufacturing step.

[0182] It is to be noted that each of the electrical conductor 35 and the gate electrode 324 of the amplification transistor AMP may include the same electrically conductive material, and may be formed through the same manufacturing step. In addition, each of the electrical conductor 35 and the gate electrode 324 of the amplification transistor AMP may include a separate electrically conductive material, and may be formed through a separate manufacturing step.

[0183] Components other than the above-described components of the ninth embodiment are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment. Workings and Effects

[0184] The photodetector 1 according to the ninth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the seventh embodiment. <10. Tenth Embodiment>

[0185] Description is given of the photodetector 1 according to the tenth embodiment of the present disclosure with reference to Fig. 50. Device Configuration of Photodetector 1 Fig. 50 illustrates an example of a planar configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1. The photodetector 1 according to the tenth embodiment has a configuration in which the two pixels 10 arranged in the arrow-X direction are used as the unit pixel, in the photodetector 1 according to the seventh embodiment. In addition, the pixel circuit 20 of the photodetector 1 does not include the FD conversion gain switching transistor FDG, in a similar manner to the pixel circuit 20 (see Fig. 3) of the photodetector 1 according to the first embodiment.

[0186] In the photodetector 1 having such a configuration, the electrical conductor 35 and the gate electrode 324 of the amplification transistor AMP each overlap the pixel separation region 31, and are electrically coupled to each other, in a similar manner to the photodetector 1 according to the seventh embodiment. Meanwhile, the gate electrode 324 of the amplification transistor AMP and the one of the main electrodes 328 of the reset transistor RST are each electrically coupled to each other through wiring 501 in the upper layer. For example, the wiring 501 is disposed in the second base 1B, and includes a metal material.

[0187] Components other than the above-described components of the tenth embodiment are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment. Workings and Effects

[0188] The photodetector 1 according to the tenth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the seventh embodiment. <11. Eleventh Embodiment> Description is given of the photodetector 1 according to the eleventh embodiment of the present disclosure with reference to Fig. 51. Device Configuration of Photodetector 1 Fig. 51 illustrates an example of a planar configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1. The photodetector 1 according to the eleventh embodiment has a configuration in which the electrical conductor 35 and the gate electrode 324 of the amplification transistor AMP each overlap the pixel separation region 31 and are electrically coupled to each other, in the photodetector 1 according to the seventh embodiment. Meanwhile, the gate electrode 324 of the amplification transistor AMP and the one of the main electrodes 328 of the FD conversion gain switching transistor FDG are each electrically coupled to each other through the wiring 501 in the upper layer. For example, the wiring 501 is disposed in the second base 1B, and includes a metal material.

[0189] Components other than the above-described components of the eleventh embodiment are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment. Workings and Effects

[0190] The photodetector 1 according to the eleventh embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the seventh embodiment. <12. Twelfth Embodiment>

[0191] Description is given of the photodetector 1 according to the twelfth embodiment of the present disclosure with reference to Figs. 52 to 64. Circuit Configuration of Pixel 10 and Pixel Circuit 20 of Photodetector 1

[0192] The photodetector 1 according to the twelfth embodiment includes four pixels 10 as the unit pixel, and includes one pixel circuit 20 electrically coupled to the four pixels 10, in a similar manner to the photodetector 1 according to the seventh embodiment illustrated in Fig. 41 described above.

[0193] The pixel 10 includes the photoelectric conversion element PD and the transfer transistor TR, and includes series circuits of both the photoelectric conversion element PD and the transfer transistor TR. The pixel circuit 20 is constructed by the plurality of pixel transistors. Here, the pixel transistors include the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the FD conversion gain switching transistor FDG (see Fig. 41).Device Configuration of Pixel 10 and Pixel Circuit 20 of Photodetector 1

[0194] Fig. 52 illustrates an example of a planar configuration in the first base 1A of the pixels 10 and the pixel circuit 20 of the photodetector 1. Fig. 53 illustrates an example of a cross-sectional configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1. Here, a left side of Fig. 53 illustrates an example of a cross-sectional configuration along the section line I-I illustrated in Fig. 52. Further, a right side of Fig. 53 illustrates an example of a cross-sectional configuration along the section line J-J illustrated in Fig. 52.

[0195] The pixels 10 and the pixel circuit 20 of the photodetector 1 are configured similarly to the pixels 10 and the pixel circuit 20 of the photodetector 1 according to the seventh embodiment illustrated in Figs. 42 to 44 described above, as illustrated in Figs. 52 and 53. It is to be noted that components of the first base 1A, such as the photoelectric conversion element PD or the pixel separation region 31, in the photodetector 1 according to any of the twelfth embodiment to the sixteenth embodiment are the same or substantially the same as the corresponding components of the photodetector 1 according to the seventh embodiment, and therefore, illustration and description thereof are omitted. (1) Device Configuration of Transfer Transistor TR

[0196] To give detailed description, first, the transfer transistor TR of the pixel 10 is configured similarly to the transfer transistor TR of the pixel 10 of the photodetector 1 according to the seventh embodiment. That is, the transfer transistor TR includes, as main components, a channel formation region, the gate insulating film 321, the gate electrode 322, and a pair of main electrodes. Here, in the twelfth embodiment, the gate electrode 322 includes a plurality of polycrystalline silicon films, i.e., a polycrystalline silicon film 322E and a polycrystalline silicon film 322F. The polycrystalline silicon film 322E and the polycrystalline silicon film 322F are stacked in a thickness direction corresponding to the side opposite to the arrow-Z direction, and are electrically coupled to each other. An insulator 322G is disposed between the polycrystalline silicon film 322E and the polycrystalline silicon film 322F. An unillustrated via hole (or contact hole) is disposed at a predetermined position of the insulator 322G. The polycrystalline silicon film 322E is electrically coupled to the polycrystalline silicon film 322F through the via hole.

[0197] The gate electrode 322 is formed to have a thickness of, for example, 150 nm or more and 200 nm or less. The polycrystalline silicon film 322E and the polycrystalline silicon film 322F are each formed to have a thickness that is about half of the thickness of the gate electrode 322, e.g., 75 nm or more and 100 nm or less.

[0198] Meanwhile, the insulator 322G includes SiO2here, and is formed to have a thickness of, for example, 5 nm or more and 20 nm or less. In the twelfth embodiment, a natural oxide film having an effective thickness of 5 nm or more and 7 nm or less is used as the insulator 322G. The natural oxide film is an oxide film (SiO2) formed on a surface of the polycrystalline silicon film 322E with oxygen mixed through atmospheric opening or the like, when a CVD method is used to form the polycrystalline silicon film 322E and then the polycrystalline silicon film 322F is further stacked. This makes it possible to eliminate necessity of particularly setting a step of forming the insulator 322G during a manufacturing process, thereby reducing the number of effective manufacturing steps.

[0199] Further, a film of the insulator 322G may be formed on the surface of the polycrystalline silicon film 322E through a thermal oxidation method, a CVD method, a sputtering method, or the like. Furthermore, it is possible to use a single-layer film of an insulating material such as silicon nitride (SiN) or silicon oxynitride (SiON), as the insulator 322G. In addition, the insulator 322G may be formed as a stack in which a plurality of layers of insulating materials of the same kind or of different kinds are stacked. Examples of the insulating material include SiO2, SiN, and SiON.

[0200] Fig. 54A illustrates an example of an enlarged cross-sectional configuration of a main part including the gate electrode 322 and the gate insulating film 321 of the transfer transistor TR. Fig. 54B illustrates an example of a schematic cross-sectional configuration of a crystal structure of the gate electrode 322 illustrated in Fig. 54A. Meanwhile, Fig. 55A illustrates an example of an enlarged cross-sectional configuration of a main part including the gate electrode 322 and the gate insulating film 321 of the transfer transistor TR according to a comparative example. Fig. 55B illustrates an example of a schematic cross-sectional configuration of a crystal structure of the gate electrode 322 illustrated in Fig. 55A.

[0201] First, the gate electrode 322 of the transfer transistor TR according to the comparative example is formed by a single layer of polycrystalline silicon, as illustrated in Fig. 55A. In the manufacturing method, a film of the gate electrode 322 is formed on a surface of the gate insulating film 321 through, for example, a CVD method. Thereafter, an impurity that reduces a resistance value is introduced into the gate electrode 322, and the impurity is further activated by an annealing (Anneal) treatment. As the impurity, for example, arsenic (As) or phosphorus (P) as an n-type impurity is used. Further, the impurity is introduced through, for example, an ion implantation method. The annealing treatment is performed under conditions, for example, of a temperature of 500℃ or more and 1000℃ or less and a time of 20 minutes or more and 60 minutes or less.

[0202] In the gate electrode 322 formed in this manner, crystal grains of the polycrystalline silicon grow, thereby increasing a crystal grain size (a grain size), as illustrated in Fig. 55B. In other words, volume expansion occurs in the crystal grains of the polycrystalline silicon. This phenomenon causes the crystal grains of the gate electrode 322 to protrude toward a side of the gate insulating film 321, thereby deteriorating roughness (roughness) of a surface of the gate insulating film 321 on a side of the gate electrode 322 and partially reducing an effective thickness tox2 of the gate insulating film 321.

[0203] Unlike the gate electrode 322 according to the above-described comparative example, the gate electrode 322 of the transfer transistor TR according to the twelfth embodiment includes a plurality of layers, i.e., the polycrystalline silicon film 322E and the polycrystalline silicon film 322F, as illustrated in Fig. 54A. Further, the polycrystalline silicon film 322E is electrically coupled to the polycrystalline silicon film 322F, and the insulator 322G is disposed between the polycrystalline silicon film 322E and the polycrystalline silicon film 322F.

[0204] The polycrystalline silicon film 322E is formed to have a thickness that is about half of a thickness of the entire gate electrode 322. This allows for supply of Si in a film of the polycrystalline silicon film 322E, thereby facilitating crystallization. Such a configuration makes it possible to control a crystal grain size of the polycrystalline silicon film 322E, thereby reducing the crystal grain size of the polycrystalline silicon film 322E as compared with the crystal grain size of the gate electrode 322 according to the comparative example, as illustrated in Fig. 54B. For example, the configuration makes it possible to control and reduce the crystal grain size of the polycrystalline silicon film 322E to be in a range of, for example, about 10% or more and about 60% or less, as compared with the crystal grain size of the gate electrode 322 according to the comparative example. The polycrystalline silicon film 322F is formed to have a thickness that is about the half of the thickness of the entire gate electrode 322, in a similar manner to the polycrystalline silicon film 322E. This makes it possible to control a crystal grain size of the polycrystalline silicon film 322F to be small.

[0205] The transfer transistor TR having such a configuration makes it possible to reduce the crystal grain size of the gate electrode 322, thus effectively suppressing protrusion of the gate electrode 322, particularly the polycrystalline silicon film 322E, toward the side of the gate insulating film 321. That is, it is possible to effectively suppress or prevent deterioration in the roughness of the surface of the gate insulating film 321 on the side of the gate electrode 322, thereby gaining an effective thickness tox1 of the gate insulating film 321.

[0206] Here, when the insulator 322G is disposed between the polycrystalline silicon film 322E and the polycrystalline silicon film 322F of the gate electrode 322, a resistance value of the gate electrode 322 increases. Therefore, if the thickness of the insulator 322G is set to, for example, 20 nm or less, as described above, the resistance value of the gate electrode 322 is settable to a practical range of 130 Ω or less.

[0207] In addition, an impurity that reduces a resistance value is introduced into the gate electrode 322 through an ion implantation method using a concentration profile having a peak at an intermediate portion in a thickness direction of the gate electrode 322. That is, it is possible to introduce the impurity into each of the polycrystalline silicon film 322E and the polycrystalline silicon film 322F of the gate electrode 322 by one time of introduction of the impurity. It is to be noted that the impurity may be separately introduced into each of the polycrystalline silicon film 322E and the polycrystalline silicon film 322F. (2) Device Configuration of Amplification Transistor AMP

[0208] The amplification transistor AMP is configured similarly to the amplification transistor AMP of the photodetector 1 according to the seventh embodiment. That is, the amplification transistor AMP includes, as main components, a channel formation region, the gate insulating film 323, the gate electrode 324, and the pair of main electrodes 325.

[0209] The gate electrode 324 of the amplification transistor AMP includes a plurality of polycrystalline silicon films, i.e., a polycrystalline silicon film 324E and a polycrystalline silicon film 324F. The polycrystalline silicon film 324E and the polycrystalline silicon film 324F are stacked in the thickness direction and electrically coupled to each other, in a similar manner to the gate electrode 322 of the transfer transistor TR. An insulator 324G is disposed between the polycrystalline silicon film 324E and the polycrystalline silicon film 324F. An unillustrated via hole (or contact hole) is disposed at a predetermined position of the insulator 324G. The polycrystalline silicon film 324E is electrically coupled to the polycrystalline silicon film 324F through the via hole. Moreover, the gate electrode 324 of the amplification transistor AMP is formed in the same manufacturing step as that of the gate electrode 322 of the transfer transistor TR. (3) Device Configurations of Other Pixel Transistors

[0210] The reset transistor RST, the selection transistor SEL, and the FD conversion gain switching transistor FDG that are other pixel transistors constructing the pixel circuit 20 are each configured similarly to the corresponding transistors of the photodetector 1 according to the seventh embodiment. That is, the reset transistor RST includes, as main components, a channel formation region, the gate insulating film 326, the gate electrode 327, and the pair of main electrodes 328. The selection transistor SEL includes, as main components, a channel formation region, the gate insulating film 326, the gate electrode 327, and the pair of main electrodes 328, in a similar manner to the reset transistor RST. In addition, the FD conversion gain switching transistor FDG includes, as main components, a channel formation region, the gate insulating film 326, the gate electrode 327, and the pair of main electrodes 328, in a similar manner to the reset transistor RST.

[0211] The gate electrode 327 of each of the reset transistor RST, the selection transistor SEL, and the FD conversion gain switching transistor FDG includes a plurality of polycrystalline silicon films, i.e., a polycrystalline silicon film 327E and a polycrystalline silicon film 327F. The polycrystalline silicon film 327E and the polycrystalline silicon film 327F are stacked in the thickness direction and electrically coupled to each other, in a similar manner to the gate electrode 322 of the transfer transistor TR. An insulator 327G is disposed between the polycrystalline silicon film 327E and the polycrystalline silicon film 327F. An unillustrated via hole (or contact hole) is disposed at a predetermined position of the insulator 327G. The polycrystalline silicon film 327E is electrically coupled to the polycrystalline silicon film 327F through the via hole. Moreover, the gate electrode 327 of the reset transistor RST and the like is formed in the same manufacturing step as that of the gate electrode 322 of the transfer transistor TR.

[0212] It is to be noted that, in the twelfth embodiment, the crystal grain size of the gate electrode is controlled in all of the pixel transistors constructing the pixel circuit 20. In the present technology, controlling the crystal grain size of the gate electrode of at least one of the pixel transistors suffices. Further, as described for the photodetector 1 and the like according to the first embodiment described above, when the pixel circuit 20 is constructed by the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL, controlling the crystal grain size of the gate electrode of at least one of the pixel transistors suffices. Manufacturing Method of Photodetector 1

[0213] Figs. 56 to 64 illustrate an example of a step cross-section for describing the manufacturing method of the photodetector 1 for each of the steps. The manufacturing method of the photodetector 1 according to the twelfth embodiment is mainly a manufacturing method of the transfer transistor TR, the amplification transistor AMP, and the selection transistor SEL of the pixel 10 in the first base 1A. The manufacturing method of each of the reset transistor RST and the FD conversion gain switching transistor FDG is similar to the manufacturing method of the selection transistor SEL, and therefore, description thereof is omitted here. The manufacturing method of the photodetector 1 according to the twelfth embodiment is as follows.

[0214] In a similar manner to the step illustrated in Fig. 22 of the manufacturing method of the photodetector 1 according to the first embodiment described above (hereinafter, simply referred to as a "first manufacturing method"), after the electrical conductor 35 is formed, the gate insulating film 323A is formed on the entire surface of the surface 30B of the semiconductor substrate 30 (see Fig. 56). The gate insulating film 323A is formed in a formation region of each of the transfer transistor TR, the amplification transistor AMP, and the selection transistor SEL. The gate insulating film 323A is also formed in a formation region of each of the reset transistor RST and the FD conversion gain switching transistor FDG. The gate insulating film 323A is formed using, for example, SiO2through, for example, a thermal oxidation method. It is to be noted that the reset transistor RST and the FD conversion gain switching transistor FDG are each formed by the same structure as and through the same manufacturing step as those of the selection transistor SEL, and therefore, description thereof is omitted hereinafter.

[0215] In a similar manner to the step illustrated in Fig. 23 of the first manufacturing method, a polycrystalline silicon film 324J is formed on the gate insulating film 323A, as illustrated in Fig. 56. The polycrystalline silicon film 324J is formed as a first-layer polycrystalline silicon film (a lower-layer polycrystalline silicon film) of the gate electrode of the pixel transistor through, for example, a CVD method. The polycrystalline silicon film 324J is formed to have a thickness that is, for example, about half of a final thickness of the gate electrode, as described above.

[0216] In a similar manner to the step illustrated in Fig. 24 of the first manufacturing method, a mask 385 is formed on the polycrystalline silicon film 324J. For example, a photoresist is used for the mask 385. The mask 385 has an opening 385H formed in a formation region of the electrical conductor 35.

[0217] In the formation region being of the electrical conductor 35 and having the opening 385H therethrough, the mask 385 is used to remove a portion of the polycrystalline silicon film 324J (and the gate insulating film 323A) to form a via hole (or a contact hole) 324H in the polycrystalline silicon film 324J (see Fig. 57). For example, anisotropic etching, dry etching, isotropic etching, or wet etching is used to remove the polycrystalline silicon film 324J. Thereafter, the mask 385 is detached (see Fig. 57).

[0218] An insulator 324L is formed on a surface of the polycrystalline silicon film 324J, as illustrated in Fig. 58. Each of the insulator 322G, the insulator 324G, and the insulator 327G illustrated in Figs. 53, 54A, and 54B described above is formed from the insulator 324L. The insulator 324L includes, for example, SiO2formed through a thermal oxidation process. In the twelfth embodiment, the insulator 324L is formed by a natural oxide film. That is, the insulator 324L includes SiO2. Adoption of the natural oxide film for the insulator 324L allows the surface of the polycrystalline silicon film 324J to be exposed on a side wall of the via hole 324H when the insulator 324L is formed and the via hole 324H is formed subsequently to formation of the polycrystalline silicon film 324J and prior to formation of the mask 385.

[0219] A polycrystalline silicon film 324K is formed on the polycrystalline silicon film 324J with the insulator 324L interposed therebetween, as illustrated in Fig. 59. The polycrystalline silicon film 324K is formed as a second-layer polycrystalline silicon film (an upper-layer polycrystalline silicon film) of the gate electrode of the pixel transistor through, for example, a CVD method. The polycrystalline silicon film 324K is formed to have a thickness that is, for example, about the half of the final thickness of the gate electrode, as described above. Here, the polycrystalline silicon film 324K is electrically coupled to the polycrystalline silicon film 324J through the via hole 324H, and is further electrically coupled to the electrical conductor 35.

[0220] Next, an impurity that reduces a resistance value is introduced into the polycrystalline silicon film 324J and the polycrystalline silicon film 324K. Here, for example, an n-type impurity is used, and the n-type impurity is introduced through an ion implantation method. Subsequently, an annealing treatment is performed to activate the impurity in each of the polycrystalline silicon film 324J and the polycrystalline silicon film 324K.

[0221] At this time, a thickness of the formed film of each of the polycrystalline silicon film 324J and the polycrystalline silicon film 324K is restricted to about the half of the final thickness of the gate electrode, and the insulator 324L is further formed between the polycrystalline silicon film 324J and the polycrystalline silicon film 324K (see Fig. 54A). Such a configuration makes it possible to effectively suppress growth of crystal grains of each of the polycrystalline silicon film 324J and the polycrystalline silicon film 324K, thereby controlling the crystal grain size to be small. In other words, the configuration makes it possible to effectively suppress deterioration in roughness of an interface between the gate insulating film 323A and the polycrystalline silicon film 324J, thereby securing an effective thickness of the gate insulating film 323A. Therefore, it is possible to effectively suppress or prevent gate leakage in the pixel transistor.

[0222] The polycrystalline silicon film 324J, the insulator 324L, and the polycrystalline silicon film 324K are patterned through a gate process, as illustrated in Fig. 60. For patterning, a mask formed through a photolithography technique is used, and anisotropic etching such as RIE is used. Accordingly, the gate electrode 322 of the transfer transistor TR is formed including the polycrystalline silicon film 322E, the insulator 322G, and the polycrystalline silicon film 322F patterned respectively from the polycrystalline silicon film 324J, the insulator 324L, and the polycrystalline silicon film 324K. Further, the gate insulating film 321 of the transfer transistor TR is formed from the gate insulating film 323A in the same step.

[0223] Similarly, the gate electrode 324 of the amplification transistor AMP is formed including the polycrystalline silicon film 324E, the insulator 324G, and the polycrystalline silicon film 324F patterned respectively from the polycrystalline silicon film 324J, the insulator 324L, and the polycrystalline silicon film 324K. Further, the gate insulating film 323 of the amplification transistor AMP is formed from the gate insulating film 323A in the same step. In addition, the gate electrode 327 of the selection transistor SEL is formed including the polycrystalline silicon film 327E, the insulator 327G, and the polycrystalline silicon film 327F patterned respectively from the polycrystalline silicon film 324J, the insulator 324L, and the polycrystalline silicon film 324K. Further, the gate insulating film 326 of the selection transistor SEL is formed from the gate insulating film 323A in the same step.

[0224] An insulator 324D covering a surface of each of the gate electrode 322, the gate electrode 324, and the gate electrode 327 is formed, as illustrated in Fig. 61. The insulator 324D is formed using SiO2through, for example, a thermal oxidation method.

[0225] Next, a LDD (Lightly Doped Drain) process is performed. Initially, a mask 386 covering the gate electrode 322 and the like is formed on the surface 30B of the semiconductor substrate 30 (see Fig. 62). The mask 386 has an opening 386H formed in a formation region of each of the n-type semiconductor region 330 of the transfer transistor TR, the pair of main electrodes 325 of the amplification transistor AMP, and the pair of main electrodes 328 of the selection transistor SEL. The mask 386 is formed through, for example, a photolithography technique.

[0226] Each of the mask 386, the gate electrode 322, the gate electrode 324, and the gate electrode 327 is used as an ion implantation mask to introduce an n-type impurity having low impurity density into the surface 30B of the semiconductor substrate 30, as illustrated in Fig. 62. The n-type impurity is introduced through an ion implantation method. The n-type impurity is subsequently activated through an annealing treatment and formed as a semiconductor region, such as the n-type semiconductor region 330, having low impurity density.

[0227] Here, the crystal grain size of each of the gate electrode 322, the gate electrode 324, and the gate electrode 327 is controlled to be small. This makes channeling unlikely to occur, making it possible to effectively suppress or prevent penetration of the n-type impurity into a side of the channel formation region.

[0228] A sidewall spacer 324S is formed on the side wall of each of the gate electrode 322, the gate electrode 324, and the gate electrode 327, as illustrated in Fig. 63. The sidewall spacer 324S is formed as an insulator whose film is formed at a uniform film thickness through, for example, a CVD method, and removed by an amount of the formed film thickness through anisotropic etching such as RIE. The insulator includes, for example, SiN. The sidewall spacer 324S is formed through self-alignment (self-alignment) for each of the gate electrode 322, the gate electrode 324, and the gate electrode 327.

[0229] Subsequently, a mask 387 covering the gate electrode 322 and the like is formed on the surface 30B of the semiconductor substrate 30 (see Fig. 64). The mask 387 has an opening 387H formed in the formation region of each of the n-type semiconductor region 330 of the transfer transistor TR, the pair of main electrodes 325 of the amplification transistor AMP, and the pair of main electrodes 328 of the selection transistor SEL. The mask 387 is formed through, for example, a photolithography technique.

[0230] In a similar manner to the step illustrated in Fig. 32 of the first manufacturing method, each of the mask 387, the sidewall spacer 324S, the gate electrode 322, the gate electrode 324, and the gate electrode 327 is used as an ion implantation mask to introduce an n-type impurity having high impurity density into the surface 30B of the semiconductor substrate 30, as illustrated in Fig. 64. The n-type impurity is introduced through an ion implantation method. The n-type impurity is activated through an annealing treatment and formed as a semiconductor region, such as the n-type semiconductor region 330, having high impurity density.

[0231] Here, the crystal grain size of each of the gate electrode 322, the gate electrode 324, and the gate electrode 327 is controlled to be small, as described above. This makes channeling unlikely to occur, making it possible to effectively suppress or prevent the penetration of the n-type impurity into the side of the channel formation region.

[0232] Formation of the n-type semiconductor region 330 allows the transfer transistor TR to be completed. Similarly, formation of the pair of main electrodes 325 allows the amplification transistor AMP to be completed. Further, formation of the pair of main electrodes 328 allows the selection transistor SEL to be completed.

[0233] The manufacturing method of the photodetector 1 according to the twelfth embodiment finishes by performing the steps in and subsequent to the step illustrated in Fig. 33 of the first manufacturing method, completing the photodetector 1.

[0234] Components other than the above-described components of the twelfth embodiment are the same or substantially the same as the components of the photodetector 1 according to the seventh embodiment. Workings and Effects

[0235] The photodetector 1 according to the twelfth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the first embodiment or the seventh embodiment.

[0236] Further, the photodetector 1 includes the photoelectric conversion element PD and the pixel circuit 20, as illustrated in Fig. 3 or 41 described above. The photoelectric conversion element PD is disposed inside the first base 1A, and converts light into electric charge, as illustrated in Fig. 6 or 43 described above. The pixel circuit 20 is electrically coupled to the photoelectric conversion element PD, and generates a pixel signal from the converted electric charge. The pixel circuit 20 is constructed by a plurality of transistors. Here, the plurality of transistors includes the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. In addition, the pixel circuit 20 further includes the FD conversion gain switching transistor FDG. Moreover, for example, the amplification transistor AMP that is one or more transistors selected from the plurality of transistors includes the gate electrode 324 including the plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 324E and the polycrystalline silicon film 324F, that are stacked in the thickness direction and electrically coupled to each other, as illustrated in Figs. 53, 54A, and 54B. Further, the reset transistor RST and the like include the gate electrode 327 including the plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 327E and the polycrystalline silicon film 327F, that are stacked in the thickness direction and electrically coupled to each other. In the photodetector 1 having such a configuration, for example, the gate electrode 324 of the amplification transistor AMP includes the plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 324E and the polycrystalline silicon film 324F, thus making it possible to effectively suppress the growth of the crystal grain size of the gate electrode 324. Such a configuration makes it possible to effectively suppress deterioration in roughness of an interface between the gate insulating film 323 and the gate electrode 324 in the amplification transistor AMP. This makes is possible to effectively suppress or prevent the gate leakage of the impurity adapted for lower resistance. In addition, because it is possible to effectively suppress or prevent the gate leakage, it is possible to effectively suppress or prevent the gate electrode 324 being brought into a non-conductive state. Similarly, it is also possible to effectively suppress or prevent growth of the crystal grain size of the gate electrode 327 of the reset transistor RST and the like. This makes it possible to effectively suppress or prevent the gate leakage and the gate electrode 327 being brought into the non-conductive state.

[0237] Further, in other words, it is possible to reduce the thickness of the gate electrode 327 of, for example, the reset transistor RST or the selection transistor SEL constructing the pixel circuit 20. This makes it possible to reduce parasitic capacitance to be added to the gate electrode 327, thereby achieving an increase in an operation speed of the pixel circuit 20.

[0238] Furthermore, the photodetector 1 includes the transfer transistor TR, as illustrated in Fig. 3 or 41 described above. One end of the transfer transistor TR is electrically coupled to the photoelectric conversion element PD, and another end of the transfer transistor TR is electrically coupled to the pixel circuit 20. In addition, the transfer transistor TR includes the gate electrode 322 including the plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 322E and the polycrystalline silicon film 322F, that are stacked in the thickness direction and electrically coupled to each other, as illustrated in Figs. 53, 54A, and 54B. In the photodetector 1 having such a configuration, the gate electrode 322 of the transfer transistor TR includes the plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 322E and polycrystalline silicon film 322F, in a similar manner to the amplification transistor AMP, thus making it possible to effectively suppress growth of the crystal grain size of the gate electrode 322. Such a configuration makes it possible to effectively suppress deterioration in roughness of an interface between the gate insulating film 321 and the gate electrode 322 in the transfer transistor TR. This makes it possible to effectively suppress or prevent the gate leakage of the impurity adapted for lower resistance. In addition, because it is possible to effectively suppress or prevent the gate leakage, it is possible to effectively suppress or prevent the gate electrode 322 being brought into the non-conductive state. Further, it is possible to reduce the thickness of the gate electrode 322 of the transfer transistor TR. This makes it possible to reduce parasitic capacitance to be added to the gate electrode 322, thereby achieving an increase in an operation speed of the transfer transistor TR.

[0239] In addition, in the photodetector 1, for example, the gate electrode 324 of the amplification transistor AMP has a configuration in which the plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 324E and the polycrystalline silicon film 324F, are stacked with at least the insulator 324G interposed therebetween, as illustrated in Figs. 53, 54A, and 54B. In the photodetector 1 having such a configuration, the insulator 324G restricts supply of Si from one of the polycrystalline silicon film 324E or the polycrystalline silicon film 324F to another one of the polycrystalline silicon film 324E or the polycrystalline silicon film 324F in the gate electrode 324 of the amplification transistor AMP. This makes it possible to effectively suppress growth of the crystal grain size of the gate electrode 324. Similarly, the transfer transistor TR, and the reset transistor RST and the like constructing the pixel circuit 20 each have a similar configuration, and achieve similar workings and effects.

[0240] Moreover, the photodetector 1 according to the twelfth embodiment makes it possible to achieve workings and effects achievable by a combination with the photodetector 1 according to the first embodiment or seventh embodiment described above. <13. Thirteenth Embodiment>

[0241] Description is given of the photodetector 1 according to the thirteenth embodiment of the present disclosure with reference to Fig. 65. The thirteenth embodiment describes an example in which a structure of the transfer transistor TR of the pixel 10 is changed in the photodetector 1 according to the twelfth embodiment. Device Configuration of Pixel 10 and Pixel Circuit 20 of Photodetector 1

[0242] Fig. 65 illustrates an example of a cross-sectional configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1. In the pixel 10 of the photodetector 1, the transfer transistor TR includes a vertical gate structure, as illustrated in Fig. 65. Detailed description is given of this point.

[0243] The transfer transistor TR has a configuration in which the gate electrode 322 is embedded inside a trench (a trench) 350 formed from the surface 30B toward the surface 30A of the semiconductor substrate 30 of the first base 1A, with the gate insulating film 321 interposed therebetween. In other words, the gate electrode 322 is extended from the surface 30B toward the surface 30A of the semiconductor substrate 30 to reach the photoelectric conversion element PD. Here, the polycrystalline silicon film 322E of the gate electrode 322 is embedded inside the trench 350.

[0244] Components other than the above-described components of the thirteenth embodiment are the same or substantially the same as the components of the photodetector 1 according to the twelfth embodiment. Workings and Effects

[0245] The photodetector 1 according to the thirteenth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the twelfth embodiment.

[0246] Further, in the photodetector 1, the transfer transistor TR includes a vertical gate structure, as illustrated in Fig. 65. In the vertical gate structure, an effective thickness of the gate electrode 322 is increased by an amount corresponding to a depth of the trench 350. This increases a time of an annealing treatment that activates an n-type impurity adapted for lower resistance. In the photodetector 1 according to the thirteenth embodiment, the gate electrode 322 includes the plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 322E and the polycrystalline silicon film 322F, thus making it possible to effectively suppress the growth of the crystal grain size and effectively suppress or prevent the gate leakage. <14. Fourteenth Embodiment>

[0247] Description is given of the photodetector 1 according to the fourteenth embodiment of the present disclosure with reference to Fig. 66. The fourteenth embodiment describes an example in which a structure of the amplification transistor AMP of the pixel circuit 20 is changed in the photodetector 1 according to the twelfth embodiment. Device Configuration of Pixel 10 and Pixel Circuit 20 of Photodetector 1

[0248] Fig. 66 illustrates an example of a cross-sectional configuration of the pixels 10 and the pixel circuit 20 of the photodetector 1. As illustrated in Fig. 66, in the pixel circuit 20 of the photodetector 1, the amplification transistor AMP includes a fin structure that enables an increase in gate capacitance, as also described for the photodetector 1 according to the first embodiment. Detailed description is given of this point.

[0249] The amplification transistor AMP has a configuration in which a portion of the gate electrode 324 is embedded inside the trench 351 formed from the surface 30B toward the surface 30A of the semiconductor substrate 30 of the first base 1A, with the gate insulating film 323 interposed therebetween. In other words, the gate electrode 324 is extended from the surface 30B toward the surface 30A of the semiconductor substrate 30 in such a manner not to reach the photoelectric conversion element PD. Here, a portion of the polycrystalline silicon film 324E of the gate electrode 324 is embedded inside the trench 351.

[0250] Components other than the above-described components of the fourteenth embodiment are the same or substantially the same as the components of the photodetector 1 according to the twelfth embodiment. Workings and Effects

[0251] The photodetector 1 according to the fourteenth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the twelfth embodiment, and achieve such workings and effects additionally including the workings and effects achievable by the photodetector 1 according to the thirteenth embodiment. <15. Fifteenth Embodiment>

[0252] Description is given of the photodetector 1 according to the fifteenth embodiment of the present disclosure with reference to Fig. 67. The fifteenth embodiment describes an example in which a gate structure of each of the transfer transistor TR of the pixel 10 and the amplification transistor AMP and the like of the pixel circuit 20 is changed in the photodetector 1 according to the twelfth embodiment. Device Configuration of Pixel 10 and Pixel Circuit 20 of Photodetector 1

[0253] Fig. 67 illustrates an example of an enlarged cross-sectional configuration of a main part of the pixel 10 of the photodetector 1. In the pixel 10 of the photodetector 1, the gate electrode 322 of the transfer transistor TR includes a plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 322E, the polycrystalline silicon film 322F, and a polycrystalline silicon film 322H, that are stacked in the thickness direction and electrically coupled to each other, as illustrated in Fig. 67. That is, the gate electrode 322 has a three-layer structure in which three layers of the gate electrode material are stacked. The insulator 322G is disposed between the polycrystalline silicon film 322E and the polycrystalline silicon film 322F. An insulator 322I similar to the insulator 322G is disposed between the polycrystalline silicon film 322F and the polycrystalline silicon film 322H. The polycrystalline silicon film 322E, the polycrystalline silicon film 322F, and the polycrystalline silicon film 322H each have substantially the same thickness. It is to be noted that the gate electrode 322 may have a structure in which the number of stacked layers is four or more.

[0254] In addition, a structure of each of the gate electrode 324 of the amplification transistor AMP, the gate electrode 327 of the reset transistor RST, and the like of the unillustrated pixel circuit 20 is the same structure as the structure of the gate electrode 322 of the transfer transistor TR.

[0255] Components other than the above-described components of the fifteenth embodiment are the same or substantially the same as the components of the photodetector 1 according to the twelfth embodiment. Workings and Effects

[0256] The photodetector 1 according to the fifteenth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the twelfth embodiment. <16. Sixteenth Embodiment>

[0257] Description is given of the photodetector 1 according to the sixteenth embodiment of the present disclosure with reference to Fig. 68. The sixteenth embodiment describes an example in which the gate structure of each of the transfer transistor TR of the pixel 10 and the amplification transistor AMP and the like of the pixel circuit 20 is changed in the photodetector 1 according to the twelfth embodiment. Device Configuration of Pixel 10 and Pixel Circuit 20 of Photodetector 1

[0258] Fig. 68 illustrates an example of an enlarged cross-sectional configuration of a main part of the pixel 10 of the photodetector 1. In the pixel 10 of the photodetector 1, the gate electrode 322 of the transfer transistor TR includes a plurality of polycrystalline silicon films, i.e., the polycrystalline silicon film 322E and the polycrystalline silicon film 322F, that are stacked in the thickness direction and electrically coupled to each other, as illustrated in Fig. 68. Further, metal 322M is disposed between the polycrystalline silicon film 322E and the polycrystalline silicon film 322F.

[0259] Basically, the metal 322M effectively suppresses the growth of the crystal grain size of the gate electrode 322 and controls the crystal grain size, in a similar manner to the insulator 322G described above. In addition, it is possible for the metal 322M to reduce the resistance value of the gate electrode 322. For example, it is possible to practically use gold (Au) or polycrystalline germanium (Ge) as the metal 322M.

[0260] In the sixteenth embodiment, the insulator 322G is disposed between the polycrystalline silicon film 322E and the metal 322M. The insulator 322G may be a natural oxide film as described above, or a film of the insulator 322G may be newly formed. Further, the insulator 322G may not be disposed.

[0261] In addition, the structure of each of the gate electrode 324 of the amplification transistor AMP, the gate electrode 327 of the reset transistor RST, and the like of the unillustrated pixel circuit 20 is the same structure as the structure of the gate electrode 322 of the transfer transistor TR.

[0262] Components other than the above-described components of the sixteenth embodiment are the same or substantially the same as the components of the photodetector 1 according to the twelfth embodiment. Workings and Effects

[0263] The photodetector 1 according to the sixteenth embodiment makes it possible to achieve workings and effects similar to the workings and effects achievable by the photodetector 1 according to the twelfth embodiment. <17. Example of Practical Application to Mobile Body>

[0264] A technique according to the present disclosure (the present technology) is applicable to various products. For example, the technique according to the present disclosure may be achieved as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, or a robot.

[0265] Fig. 69 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0266] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 69, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0267] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0268] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0269] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0270] The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

[0271] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

[0272] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0273] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0274] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0275] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 69, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0276] Fig. 70 is a diagram depicting an example of the installation position of the imaging section 12031.

[0277] In Fig. 70, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0278] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0279] Incidentally, Fig. 70 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird’s-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0280] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0281] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

[0282] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0283] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0284] The description has been given hereinabove of an example of the vehicle control system to which the technique according to the present disclosure is applicable. The technique according to the present disclosure is applicable to the imaging section 12031, of the configurations described above. Applying the technique according to the present disclosure to the imaging section 12031 enables achievement of the imaging section 12031 that makes it possible to improve the charge conversion efficiency. <18. Other Embodiments>

[0285] The present technology is not limited to the above-described embodiments, and may be modified in a variety of ways without departing from the gist thereof. For example, in the present technology, photodetectors according to two or more embodiments may be combined among the photodetectors according to the first to sixteenth embodiments described above. As a specific example, a coupling structure between the electrical conductor and the gate electrode of the amplification transistor of the photodetector according to the first embodiment, and a coupling structure between the electrical conductor and the FD conversion gain switching transistor of the photodetector according to the seventh embodiment may be combined in the present technology.

[0286] A photodetector according to a first embodiment of the present disclosure includes a photoelectric conversion element, a floating diffusion, an electrical conductor, and an amplification transistor. The photoelectric conversion element is disposed inside a first base, and converts light into electric charge. The floating diffusion is disposed on a first surface of the first base, and is electrically coupled to the photoelectric conversion element. The electrical conductor is electrically coupled to a side surface of the floating diffusion. The amplification transistor includes a gate electrode including the electrical conductor. The photodetector having such a configuration makes it possible to shorten, to the utmost, a length of a wiring path from the floating diffusion to the gate electrode of the amplification transistor. This makes it possible to effectively suppress random noise and improve charge conversion efficiency.

[0287] A photodetector according to a second embodiment of the present disclosure has a configuration in which the electrical conductor is formed integrally or in an integrated manner with the gate electrode, in the photodetector according to the first embodiment. The photodetector having such a configuration makes it possible to shorten, to the utmost, the length of the wiring path from the floating diffusion to the gate electrode of the amplification transistor.

[0288] A photodetector according to a third embodiment of the present disclosure has a configuration of further including a transfer transistor whose one of a pair of main electrodes is electrically coupled to the photoelectric conversion element and whose another one of the pair of main electrodes is electrically coupled to the floating diffusion, in the photodetector according to the first embodiment. The photoelectric conversion element and the transfer transistor construct a pixel. In addition, a plurality of the pixels is arranged in a first direction and a second direction intersecting the first direction. In the first base, a pixel separation region is disposed at least at a periphery of the side surface of the photoelectric conversion element of the pixel. The pixel separation region electrically or optically separates the adjacent pixels from each other. Further, the electrical conductor is formed as shared wiring that electrically couples to each other the floating diffusions disposed in respective ones of the plurality of the pixels adjacent to each other. In the photodetector having such a configuration, wiring that electrically couples the floating diffusions to each other, a coupling region between the wiring and the floating diffusions, and the like are not necessary. This makes it possible to reduce an area of the pixel.

[0289] A photodetector according to a fourth embodiment of the present disclosure has a configuration in which the electrical conductor is disposed to overlap the pixel separation region as viewed in an incident direction of light or from a side opposite to the incident direction, in the photodetector according to the third embodiment. In the photodetector having such a configuration, the electrical conductor is disposed by using an occupied area of the pixel separation region. This makes it possible to reduce an occupied area of the pixel.

[0290] A photodetector according to a fifth embodiment of the present disclosure has a configuration in which the amplification transistor is disposed to overlap the pixel separation region as viewed in the incident direction of the light or from the side opposite to the incident direction, in the photodetector according to the third embodiment. In the photodetector having such a configuration, the amplification transistor is disposed by using the occupied area of the pixel separation region. This makes it possible to reduce the occupied area of the pixel.

[0291] A photodetector according to a sixth embodiment of the present disclosure includes a photoelectric conversion element, a floating diffusion, a pixel separation region, an electrical conductor, and a reset transistor. The photoelectric conversion element is disposed inside a first base, and converts light into electric charge. The floating diffusion is disposed on a first surface of the first base, and is electrically coupled to the photoelectric conversion element. The pixel separation region is disposed between the photoelectric conversion element and another photoelectric conversion element adjacent to the photoelectric conversion element, and electrically or optically separates the photoelectric conversion element from the other photoelectric conversion element. The electrical conductor is disposed to overlap the pixel separation region, and is electrically coupled to the floating diffusion. A first main electrode that is one of a pair of main electrodes of the reset transistor is electrically coupled to the electrical conductor, and a second main electrode that is another one of the pair of main electrodes of the reset transistor is electrically coupled to a power supply voltage. The photodetector having such a configuration makes it possible to shorten, to the utmost, a length of a wiring path from the floating diffusion to the one of the main electrodes of the reset transistor. This makes it possible to effectively suppress the random noise and improve the charge conversion efficiency.

[0292] A photodetector according to a seventh embodiment of the present disclosure has a configuration of further including an FD conversion gain switching transistor of which a third main electrode that is one of a pair of main electrodes is electrically coupled to the electrical conductor and of which a fourth main electrode that is another one of the pair of main electrodes is electrically coupled to the first main electrode of the reset transistor, in the photodetector according to the sixth embodiment. Moreover, the first main electrode of the reset transistor is electrically coupled to the electrical conductor with the FD conversion gain switching transistor interposed therebetween. The photodetector having such a configuration makes it possible to shorten, to the utmost, the length of the wiring path from the floating diffusion to the one of the main electrodes of the reset transistor. This makes it possible to effectively suppress the random noise and improve the charge conversion efficiency.

[0293] A photodetector according to an eighth embodiment of the present disclosure includes a photoelectric conversion element and a pixel circuit. The photoelectric conversion element is disposed inside a first base, and converts light into electric charge. The pixel circuit is electrically coupled to the photoelectric conversion element, and generates a pixel signal from the converted electric charge. The pixel circuit includes a plurality of transistors. In addition, one or more transistors selected from the plurality of transistors include a gate electrode including a plurality of polycrystalline silicon films. The plurality of polycrystalline silicon films is stacked in a thickness direction and electrically coupled to each other. The photodetector having such a configuration makes it possible to effectively suppress growth of a crystal grain size of the gate electrode of each of the transistors. This makes it possible to effectively suppress or prevent gate leakage and the gate electrode being brought into the non-conductive state.

[0294] A photodetector according to a ninth embodiment of the present disclosure has a configuration of further including a transfer transistor having one end electrically coupled to the photoelectric conversion element, and another end electrically coupled to the pixel circuit, in the photodetector according to the eighth embodiment. The transfer transistor includes a gate electrode including a plurality of polycrystalline silicon films. The plurality of polycrystalline silicon films is stacked in the thickness direction and electrically coupled to each other. The photodetector having such a configuration makes it possible to effectively suppress growth of the crystal grain size of the gate electrode of the transfer transistor. This makes it possible to effectively suppress or prevent the gate leakage and the gate electrode being brought into the non-conductive state.

[0295] A photodetector according to a tenth embodiment of the present disclosure has a configuration in which the plurality of polycrystalline silicon films is stacked with at least one of an insulator or metal interposed therebetween, in the photodetector according to the eighth embodiment or the ninth embodiment. The photodetector having such a configuration makes it possible to effectively suppress the growth of the crystal grain size of the gate electrode of each of the transistors.

[0296] A photodetector according to an eleventh embodiment of the present disclosure includes: a photoelectric conversion element that is disposed inside a first base and converts light into electric charge; a floating diffusion disposed on a first surface of the first base and electrically coupled to the photoelectric conversion element; an electrical conductor electrically coupled to a side surface of the floating diffusion; and an amplification transistor including a gate electrode including the electrical conductor. In addition, the amplification transistor includes the gate electrode including a plurality of polycrystalline silicon films. The plurality of polycrystalline silicon films is stacked in a thickness direction and electrically coupled to each other. The photodetector having such a configuration makes it possible to achieve workings and effects achievable by a combination of the workings and effects achievable by the photodetector according to the first embodiment and the workings and effects achievable by the photodetector according to the eighth embodiment. <Configuration of Present Technology>

[0297] The present technology has the following configuration. The present technology having the following configuration makes it possible to improve charge conversion efficiency in a photodetector.

[0298] (1) A photodetector including: a photoelectric conversion element that is disposed inside a first base and converts light into electric charge; a floating diffusion disposed on a first surface of the first base and electrically coupled to the photoelectric conversion element; an electrical conductor electrically coupled to a side surface of the floating diffusion; and an amplification transistor including a gate electrode including the electrical conductor. (2) The photodetector according to (1), in which the electrical conductor is embedded in the first base from the first surface toward a side of a second surface opposed to the first surface. (3) The photodetector according to (2), in which the electrical conductor configures a fin part of the gate electrode, the fin part being extended from the first surface of the first base to the side of the second surface of the first base, and the amplification transistor includes a fin structure. (4) The photodetector according to (2) or (3), in which the floating diffusion includes a semiconductor region, the semiconductor region having a junction depth in the first base from the first surface toward the side of the second surface. (5) The photodetector according to any one of (1) to (4), in which the electrical conductor is formed integrally or in an integrated manner with the gate electrode. (6) The photodetector according to any one of (1) to (4), in which the electrical conductor includes polycrystalline silicon, metal, or a semiconductor region. (7) The photodetector according to any one of (1) to (6), further including a transfer transistor whose one of a pair of main electrodes is electrically coupled to the photoelectric conversion element and whose another one of the pair of main electrodes is electrically coupled to the floating diffusion, in which the photoelectric conversion element and the transfer transistor construct a pixel, and a plurality of the pixels is arranged in a first direction and a second direction intersecting the first direction. (8) The photodetector according to (7), in which a pixel separation region is disposed in the first base at least at a periphery of a side surface of the photoelectric conversion element of the pixel, the pixel separation region electrically or optically separating the pixels adjacent to each other. (9) The photodetector according to (8), in which the electrical conductor is formed as shared wiring that electrically couples to each other the floating diffusions disposed in respective ones of the plurality of the pixels adjacent to each other. (10) The photodetector according to (9), in which the electrical conductor is disposed to overlap the pixel separation region as viewed in an incident direction of light or from a side opposite to the incident direction. (11) The photodetector according to (10), in which the amplification transistor is disposed to overlap the pixel separation region as viewed in the incident direction of the light or from the side opposite to the incident direction. (12) The photodetector according to any one of (1) to (11), in which the amplification transistor constructs a pixel circuit that reads the electric charge converted by the photoelectric conversion element. (13) The photodetector according to (12), in which the pixel circuit includes a reset transistor and a selection transistor, or further includes a floating diffusion conversion gain switching transistor, in addition to the amplification transistor. (14) The photodetector according to (13), in which one or more transistors selected from the reset transistor, the selection transistor, and the floating diffusion conversion gain switching transistor of the pixel circuit are disposed on the first surface of the first base. (15) The photodetector according to (13) or (14), further including a second base on a side of the first surface of the first base, in which one or more transistors selected from the reset transistor, the selection transistor, and the floating diffusion conversion gain switching transistor of the pixel circuit are disposed in the second base. (16) The photodetector according to any one of (13) to (15), in which one of a pair of main electrodes of the reset transistor is electrically coupled through wiring to the gate electrode of the amplification transistor. (17) A photodetector including: a photoelectric conversion element that is disposed inside a first base and converts light into electric charge; a floating diffusion disposed on a first surface of the first base and electrically coupled to the photoelectric conversion element; a pixel separation region disposed between the photoelectric conversion element and another photoelectric conversion element adjacent to the photoelectric conversion element, the pixel separation region electrically or optically separating the photoelectric conversion element from the other photoelectric conversion element; an electrical conductor disposed to overlap the pixel separation region and electrically coupled to the floating diffusion; and a reset transistor of which a first main electrode that is one of a pair of main electrodes is electrically coupled to the electrical conductor and of which a second main electrode that is another one of the pair of main electrodes is electrically coupled to a power supply voltage. (18) The photodetector according to (17), further including a floating diffusion conversion gain switching transistor of which a third main electrode that is one of a pair of main electrodes is electrically coupled to the electrical conductor and of which a fourth main electrode that is another one of the pair of main electrodes is electrically coupled to the first main electrode of the reset transistor, in which the first main electrode of the reset transistor is electrically coupled to the electrical conductor with the floating diffusion conversion gain switching transistor interposed therebetween. (19) The photodetector according to (18), in which the electrical conductor is coupled to the reset transistor or the floating diffusion conversion gain switching transistor with the first main electrode or the third main electrode and a diffusion region interposed therebetween, the diffusion region being diffused from a side surface of the electrical conductor along the first surface and being of the same electrically conductive type as an electrically conductive type of the first main electrode or the third main electrode. (20) The photodetector according to any one of (17) to (19), in which the electrical conductor includes polycrystalline silicon, metal, or a semiconductor region. (21) The photodetector according to (20), in which the polycrystalline silicon or the metal is embedded in the first base or disposed on the first surface of the first base, and the semiconductor region is disposed in the first base. (22) The photodetector according to any one of (17) to (21), further including: a transfer transistor electrically coupled to the photoelectric conversion element; and another transfer transistor electrically coupled to the other photoelectric conversion element, in which the electrical conductor is formed as shared wiring electrically coupled to each of the transfer transistor and the other transfer transistor. (23) The photodetector according to any one of (17) to (22), further including an amplification transistor of which a gate electrode is electrically coupled to the electrical conductor. (24) The photodetector according to (23), in which each of the reset transistor and the amplification transistor is disposed to overlap the pixel separation region as viewed in an incident direction of light or from a side opposite to the incident direction. (25) A photodetector including: a photoelectric conversion element that is disposed inside a first base and converts light into electric charge; and a pixel circuit that is electrically coupled to the photoelectric conversion element, generates a pixel signal from the converted electric charge, and includes a plurality of transistors, in which one or more transistors selected from the plurality of transistors include a gate electrode including a plurality of polycrystalline silicon films, the plurality of polycrystalline silicon films being stacked in a thickness direction and being electrically coupled to each other. (26) The photodetector according to (25), in which the plurality of transistors includes an amplification transistor, a reset transistor, and a selection transistor, or further includes a floating diffusion conversion gain switching transistor. (27) The photodetector according to (26), in which the amplification transistor includes the gate electrode including a fin part, the fin part being extended from a first surface of the first base to a side of a second surface of the first base, the second surface being opposed to the first surface, and the amplification transistor includes a fin structure. (28) The photodetector according to any one of (25) to (27), further including a transfer transistor having one end electrically coupled to the photoelectric conversion element, and another end electrically coupled to the pixel circuit, in which the transfer transistor includes a gate electrode including a plurality of polycrystalline silicon films, the plurality of polycrystalline silicon films being stacked in the thickness direction and being electrically coupled to each other. (29) The photodetector according to (28), in which the transfer transistor includes the gate electrode extended from a first surface of the first base to a side of a second surface of the first base, the second surface being opposed to the first surface, and the transfer transistor includes a vertical gate structure. (30) The photodetector according to any one of (25) to (29), in which the plurality of polycrystalline silicon films is stacked with at least an insulator interposed therebetween. (31) The photodetector according to any one of (25) to (29), in which the plurality of polycrystalline silicon films is stacked with at least metal interposed therebetween. (32) A photodetector including: a photoelectric conversion element that is disposed inside a first base and converts light into electric charge; a floating diffusion disposed on a first surface of the first base and electrically coupled to the photoelectric conversion element; an electrical conductor electrically coupled to a side surface of the floating diffusion; and an amplification transistor including a gate electrode including the electrical conductor, in which the amplification transistor includes the gate electrode including a plurality of polycrystalline silicon films, the plurality of polycrystalline silicon films being stacked in a thickness direction and being electrically coupled to each other.

[0299] (1) A light detecting device, comprising: a first structure comprising: a first semiconductor layer; a photoelectric conversion element to convert incident light into electric charge; a first floating diffusion disposed in the first semiconductor layer and configured to store electric charge transferred from the photoelectric conversion element; and an amplification transistor including a gate electrode in contact with the first semiconductor layer adjacent to the first floating diffusion. (2) The light detecting device of (1), wherein the gate electrode of the amplification transistor is in contact with two or fewer sides of the first semiconductor layer. (3) The light detecting device of one or more of (1) to (2), wherein the first structure further comprises: a second semiconductor layer including a channel region of the amplification transistor; and a first separation material between the first semiconductor layer and the second semiconductor layer. (4) The light detecting device of one or more of (1) to (3), wherein the first structure further comprises: a second separation material between the gate electrode of the amplification transistor and the second semiconductor layer. (5) The light detecting device of one or more of (1) to (4), wherein the first and second separation material comprise oxide. (6) The light detecting device of one or more of (1) to (5), wherein the first and second separation material comprise semiconductor material. (7) The light detecting device of one or more of (1) to (6), wherein part of the second separation material contacts the first separation material. (8) The light detecting device of one or more of (1) to (7), wherein part of the gate electrode of the amplification transistor contacts the first separation material. (9) The light detecting device of one or more of (1) to (8), wherein the photoelectric conversion element is included in a plurality of photoelectric conversion elements that share the amplification transistor. (10) The light detecting device of one or more of (1) to (9), further comprising: a transfer transistor coupled to the first floating diffusion; a reset transistor coupled to the first floating diffusion and the amplification transistor; and a selection transistor coupled to the amplification transistor. (11) The light detecting device of one or more of (1) to (10), further comprising: a second structure bonded to the first structure and including a second semiconductor layer. (12) The light detecting device of one or more of (1) to (11), wherein part of the reset transistor, part of the selection transistor, or parts of both of the reset transistor and the selection transistor are included in the second structure. (13) The light detecting device of one or more of (1) to (12), further comprising: a conversion gain switching transistor coupled between the first floating diffusion and the reset transistor. (14) The light detecting device of one or more of (1) to (13), wherein part of the reset transistor, part of the selection transistor, part of the conversion gain switching transistor, or parts of the reset transistor, the conversion gain switching transistor, and the selection transistor are included in the second structure. (15) The light detecting device of one or more of (1) to (14), wherein the first structure further comprises: wiring that electrically connects the gate of the amplification transistor and a source of the reset transistor. (16) A light detecting device, comprising: a first semiconductor layer; a photoelectric conversion element disposed in the first semiconductor layer and configured to convert incident light into electric charge; a first floating diffusion disposed in the first semiconductor layer and configured to store electric charge transferred from the photoelectric conversion element; and an amplification transistor including a gate electrode electrically coupled to the first floating diffusion through the first semiconductor layer. (17) The light detecting device of (16), wherein, in a cross-sectional view, the gate electrode of the amplification transistor is located at a corner of the first semiconductor layer. (18) The light detecting device of one or more of (16) to (17), further comprising: a second semiconductor layer including at least part of a reset transistor, wherein part of the gate electrode of the amplification transistor contacts the second semiconductor layer. (19) The light detecting device of one or more of (16) to (18), wherein, in the cross-sectional view, the gate electrode of the amplification transistor is adjacent to sidewalls of the first semiconductor layer. (20) A light detecting device, comprising: a photoelectric conversion element disposed in a first semiconductor layer and configured to convert incident light into electric charge; a transfer transistor configured to transfer the electric charge from the photoelectric conversion element; a first floating diffusion disposed in the first semiconductor layer and configured to store the electric charge transferred by the transfer transistor; and an amplification transistor including a gate electrode that contacts the first semiconductor layer adjacent to the first floating diffusion.

[0300] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

[0301] 1 photodetector 1A first base 1B second base 1C third base 10 pixel 30, 40 semiconductor substrate 300 p-type semiconductor region 31, 31A, 31B, 31C pixel separation region 31D element separation region 321, 323, 326 gate insulating film 322, 324, 327 gate electrode 330 n-type semiconductor region 35 electrical conductor 35n diffusion region 36 coupling region 5 through-wiring 7 optical filter 8 optical lens PD photoelectric conversion element TR transfer transistor RST reset transistor AMP amplification transistor SEL selection transistor FD floating diffusion FDG FD conversion gain switching transistor

Claims

1. A light detecting device, comprising: a first structure comprising: a first semiconductor layer; a photoelectric conversion element to convert incident light into electric charge; a first floating diffusion disposed in the first semiconductor layer and configured to store electric charge transferred from the photoelectric conversion element; and an amplification transistor including a gate electrode in contact with the first semiconductor layer adjacent to the first floating diffusion.

2. The light detecting device of claim 1, wherein the gate electrode of the amplification transistor is in contact with two or fewer sides of the first semiconductor layer.

3. The light detecting device of claim 1, wherein the first structure further comprises: a second semiconductor layer including a channel region of the amplification transistor; and a first separation material between the first semiconductor layer and the second semiconductor layer.

4. The light detecting device of claim 3, wherein the first structure further comprises: a second separation material between the gate electrode of the amplification transistor and the second semiconductor layer.

5. The light detecting device of claim 4, wherein the first and second separation material comprise oxide.

6. The light detecting device of claim 4, wherein the first and second separation material comprise semiconductor material.

7. The light detecting device of claim 4, wherein part of the second separation material contacts the first separation material.

8. The light detecting device of claim 3, wherein part of the gate electrode of the amplification transistor contacts the first separation material.

9. The light detecting device of claim 1, wherein the photoelectric conversion element is included in a plurality of photoelectric conversion elements that share the amplification transistor.

10. The light detecting device of claim 1, further comprising: a transfer transistor coupled to the first floating diffusion; a reset transistor coupled to the first floating diffusion and the amplification transistor; and a selection transistor coupled to the amplification transistor.

11. The light detecting device of claim 10, further comprising: a second structure bonded to the first structure and including a second semiconductor layer.

12. The light detecting device of claim 11, wherein part of the reset transistor, part of the selection transistor, or parts of both of the reset transistor and the selection transistor are included in the second structure.

13. The light detecting device of claim 11, further comprising: a conversion gain switching transistor coupled between the first floating diffusion and the reset transistor.

14. The light detecting device of claim 13, wherein part of the reset transistor, part of the selection transistor, part of the conversion gain switching transistor, or parts of the reset transistor, the conversion gain switching transistor, and the selection transistor are included in the second structure.

15. The light detecting device of claim 10, wherein the first structure further comprises: wiring that electrically connects the gate of the amplification transistor and a source of the reset transistor.

16. A light detecting device, comprising: a first semiconductor layer; a photoelectric conversion element disposed in the first semiconductor layer and configured to convert incident light into electric charge; a first floating diffusion disposed in the first semiconductor layer and configured to store electric charge transferred from the photoelectric conversion element; and an amplification transistor including a gate electrode electrically coupled to the first floating diffusion through the first semiconductor layer.

17. The light detecting device of claim 16, wherein, in a cross-sectional view, the gate electrode of the amplification transistor is located at a corner of the first semiconductor layer.

18. The light detecting device of claim 17, further comprising: a second semiconductor layer including at least part of a reset transistor, wherein part of the gate electrode of the amplification transistor contacts the second semiconductor layer.

19. The light detecting device of claim 16, wherein, in the cross-sectional view, the gate electrode of the amplification transistor is adjacent to sidewalls of the first semiconductor layer.

20. A light detecting device, comprising: a photoelectric conversion element disposed in a first semiconductor layer and configured to convert incident light into electric charge; a transfer transistor configured to transfer the electric charge from the photoelectric conversion element; a first floating diffusion disposed in the first semiconductor layer and configured to store the electric charge transferred by the transfer transistor; and an amplification transistor including a gate electrode that contacts the first semiconductor layer adjacent to the first floating diffusion.

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