Photodetection element

Abstract

A photodetection element includes a first substrate including a photoelectric conversion element, a second substrate including at least a part of a pixel circuit that generates a pixel signal according to charge output from the photoelectric conversion element, and an interlayer insulating layer between the first substrate and the second substrate. The interlayer insulting layer includes two or more wiring layers.

Description

PHOTODETECTION ELEMENTCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP 2023-166309 filed on September 27, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a photodetection element.

[0003] An imaging element having a three-layer structure has been proposed in which a first substrate in which a photoelectric conversion element is disposed, a second substrate in which a pixel circuit is disposed, and a third substrate in which a circuit that performs signal processing on a pixel signal is disposed are stacked (see PTL 1).

[0004] By disposing the pixel circuit on the second substrate unlike the photoelectric conversion element, a size of the photoelectric conversion element disposed on the first substrate can be increased, and sensitivity can be improved.

[0005] WO 2019 / 130702A1Summary

[0006] In an imaging element having a three-layer structure, an interlayer insulating layer is disposed between a first substrate and a second substrate. In the interlayer insulating layer, a wiring layer for transferring charge accumulated in a floating diffusion to a pixel circuit of the second substrate and a wiring layer connected to a ground node of the first substrate are arranged.

[0007] In an existing imaging element having a three-layer structure, only one wiring layer is disposed in an interlayer insulating layer. In the interlayer insulating layer, a plurality of wiring layers having respective different connection destinations needs to be arranged, a distance between the wiring layers is shortened, and interference therebetween is likely to occur. In particular, wiring layers containing different types or amounts of impurities are preferably arranged as far apart as possible in order to avoid interference; however, in a case where a plurality of wiring layers is arranged at only one layer, it is difficult to avoid interference between the wiring layers. In addition, in a case where a plurality of wiring layers is arranged at one layer, layout design takes time and effort, and design costs increase.

[0008] Hence, the present disclosure provides a photodetection element capable of reducing interference between a plurality of wiring layers arranged in an interlayer insulating layer and improving a degree of freedom in pixel design.

[0009] According to the present disclosure, there is provided a photodetection element including: a first substrate in which a photoelectric conversion element is disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge output from the photoelectric conversion element is disposed; and an interlayer insulating layer which is disposed between the first substrate and the second substrate and has two or more stacked wiring layers.

[0010] The pixel circuit in the second substrate may include a pixel transistor having at least one of an amplification transistor, a reset transistor, or a selection transistor.

[0011] Each of the wiring layers may be a polysilicon layer or a metal layer.

[0012] The two or more wiring layers may have a difference in at least one of a type and a concentration of impurity ions contained in the wiring layers.

[0013] At least some of the two or more wiring layers may be arranged to intersect with each other in a plan view.

[0014] The two or more wiring layers may include a floating diffusion to which the charge generated by the photoelectric conversion element in the first substrate is transferred, a well region of a conductivity type different from that of the floating diffusion, a transfer transistor that switches between whether or not the charge generated by the photoelectric conversion element in the first substrate is transferred to the floating diffusion, or a plurality of wiring layers all connected to at least two of pixel boundary regions of the first substrate.

[0015] The two or more wiring layers may include two or more wiring layers arranged at respective different layers of the interlayer insulating layer and two or more wiring layers arranged at the same layer of the interlayer insulating layer.

[0016] The interlayer insulating layer may include a plurality of first contacts extending from at least some of the two or more wiring layers to the second substrate, and a plurality of second contacts extending from the plurality of wiring layers to the first substrate.

[0017] The interlayer insulating layer may include charge accumulators that accumulate charge transferred from the photoelectric conversion element independently of the floating diffusion, and each of the charge accumulators may have two wiring layers arranged facing each other among the two or more wiring layers.

[0018] The photodetection element may further include conversion efficiency switching transistors that switch photoelectric conversion efficiency. Each of the charge accumulators may accumulate charge transferred from the photoelectric conversion element when the conversion efficiency switching transistors are turned on.

[0019] The photodetection element may further include a third contact extending to the second substrate from a wiring layer disposed on a side close to the second substrate of the two wiring layers constituting each of the charge accumulators. The wiring layer disposed on the side close to the second substrate may be electrically connected via the third contact to sources of the conversion efficiency switching transistors.

[0020] A plurality of the conversion efficiency switching transistors and a plurality of the charge accumulators capable of switching photoelectric conversion efficiency in three or more levels may be provided, and the plurality of charge accumulators may be arranged in the interlayer insulating layer, or some of the plurality of charge accumulators may be arranged in the interlayer insulating layer such that the rest of charge accumulators may be arranged in the second substrate.

[0021] At least one wiring layer of the two or more wiring layers may be a light-shielding layer that shields light having passed through the photoelectric conversion element and shields light from the second substrate.

[0022] The light-shielding layer may be set to a predetermined reference potential.

[0023] The light-shielding layer and a wiring layer disposed at a layer different from the light-shielding layer among the two or more wiring layers may be arranged to cover the entire region of the first substrate in a plan view.

[0024] An area of the light-shielding layer among the two or more wiring layers may be larger than an area of the wiring layer disposed at a layer different from the light-shielding layer.

[0025] The light-shielding layer may have a solid pattern, a mesh-shaped pattern, or a slit-shaped pattern.

[0026] According to the present disclosure, there is provided a photodetection element including: a first substrate in which a photoelectric conversion element is disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge output from the photoelectric conversion element is disposed; and an interlayer insulating layer which is disposed between the first substrate and the second substrate and has one or more wiring layers. The wiring layers contain arsenic (As) and phosphorus (P).

[0027] A concentration of arsenic (As) in the wiring layers may be higher than a concentration of phosphorus (P).

[0028] According to the present disclosure, there is provided a photodetection element including: a first substrate in which a photoelectric conversion element is disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge output from the photoelectric conversion element is disposed; and an interlayer insulating layer disposed between the first substrate and the second substrate. The interlayer insulating layer has a wiring layer, a first contact extending from the wiring layers to the second substrate, and an insulating layer disposed in a predetermined region having a connection portion with the first contact in the wiring layers.

[0029] According to the present disclosure, there is provided a photodetection element including: a first substrate on which a photoelectric conversion element and a floating diffusion are disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge transferred from the photoelectric conversion element is disposed; and an interlayer insulating layer which is disposed between the first substrate and the second substrate and has two or more wiring layers. The two or more wiring layers include a first wiring layer that is electrically connected to the floating diffusion, and a second wiring layer that is disposed at a distance from the first wiring layer to cause capacitive coupling and boosts a potential of the first wiring layer.

[0030] According to the present disclosure, there is provided a photodetection element including: a first substrate on which a photoelectric conversion element and a floating diffusion are disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge transferred from the photoelectric conversion element is disposed; and an interlayer insulating layer which is disposed between the first substrate and the second substrate and has a capacitor.

[0031] Fig. 1 is a diagram illustrating a schematic configuration of a photodetection element according to an embodiment of the present disclosure.Fig. 2 is a diagram illustrating an example of a pixel circuit according to a first embodiment.Fig. 3 is a diagram illustrating an example of a longitudinal-sectional configuration (sectional configuration in a vertical direction) of the photodetection element according to the embodiment of the present disclosure.Fig. 4 is a planar layout view of the photodetection element according to the first embodiment.Fig. 5A is a sectional view along line A-A’-B’-B in Fig. 4 in a substrate depth direction.Fig. 5B is a sectional view along line C-D in Fig. 4 in the substrate depth direction.Figs. 6A to 6C are plan views of a first wiring layer and a second wiring layer.Fig. 7 is a planar layout view of a photodetection element according to a comparative example.Fig. 8A is a sectional view along line A-A’-B’-B in Fig. 7 in the substrate depth direction.Fig. 8B is a sectional view along line C-D in Fig. 7 in the substrate depth direction.Fig. 9A is a planar layout view illustrating an arrangement of color filters according to a first example.Fig. 9B is a circuit diagram of pixels and a pixel circuit according to the first example.Fig. 10A is a planar layout view illustrating an arrangement of color filters according to a second example.Fig. 10B is a circuit diagram of pixels and a pixel circuit according to a second example.Fig. 11A is a planar layout view illustrating an arrangement of color filters according to a third example.Fig. 11B is a circuit diagram of pixels and a pixel circuit according to the third example.Fig. 12 is a sectional view illustrating arrangement locations of a first wiring layer and a second wiring layer in a photodetection element according to a second embodiment.Fig. 13A is a planar layout view illustrating a distance between a first penetration contact on the second wiring layer and a second penetration contact on a third wiring layer.Fig. 13B is a planar layout view illustrating an empty region of a second substrate.Fig. 14 is a sectional view illustrating arrangement locations of a first wiring layer, a second wiring layer, and a third wiring layer in a photodetection element according to a comparative example.Fig. 15A is a planar layout view illustrating a distance between a first penetration contact and a second penetration contact in the comparative example.Fig. 15B is a planar layout view illustrating an empty region of a second substrate in the comparative example.Fig. 16A is a planar layout view of a first substrate of a photodetection element according to a third embodiment.Fig. 16B is a planar layout view of a second substrate of the photodetection element according to the third embodiment.Fig. 17A is a planar layout view of a first substrate according to a comparative example.Fig. 17B is a planar layout view of a second substrate according to a comparative example.Fig. 18 is a sectional view of a photodetection element according to a fourth embodiment.Fig. 19 is a sectional view of the photodetection element according to a comparative example.Fig. 20A is a process-sectional view illustrating a manufacturing process of a photodetection element according to a fifth embodiment.Fig. 20B is a process-sectional view illustrating a manufacturing process following Fig. 20A.Fig. 20C is a process-sectional view illustrating a manufacturing process following Fig. 20B.Fig. 20D is a process-sectional view illustrating a manufacturing process following Fig. 20C.Fig. 20E is a process-sectional view illustrating a manufacturing process following Fig. 20D.Fig. 20F is a process-sectional view illustrating a manufacturing process following Fig. 20E.Fig. 20G is a process-sectional view illustrating a manufacturing process following Fig. 20F.Fig. 20H is a process-sectional view illustrating a manufacturing process following Fig. 20G.Fig. 20I is a process-sectional view illustrating a manufacturing process following Fig. 20H.Fig. 20J is a process-sectional view illustrating a manufacturing process following Fig. 20I.Fig. 20K is a process-sectional view illustrating a manufacturing process following Fig. 20J.Fig. 20L is a process-sectional view illustrating a manufacturing process following Fig. 20K.Fig. 20M is a process-sectional view illustrating a manufacturing process following Fig. 20L.Fig. 20N is a process-sectional view illustrating a manufacturing process following Fig. 20M.Fig. 20O is a process-sectional view illustrating a manufacturing process following Fig. 20N.Fig. 21A is a circuit diagram of a pixel circuit included in a photodetection element according to a sixth embodiment.Fig. 21B is a sectional view along line A-B in Fig. 22A in the substrate depth direction.Fig. 22A is a planar layout view of the photodetection element according to the sixth embodiment.Fig. 22B is a sectional view along line A-B in Fig. 22A in the substrate depth direction.Fig. 23A is a planar layout view of the photodetection element according to a comparative example.Fig. 23B is a sectional view along line A-B in Fig. 23A in the substrate depth direction.Fig. 24A is a planar layout view of a photodetection element according to a modification example of the sixth embodiment.Fig. 24B is a sectional view along line A-B in Fig. 24A in the substrate depth direction.Fig. 25A is a planar layout view illustrating an example in which each tooth of comb teeth extends in a second direction.Fig. 25B is a planar layout view illustrating an example in which each tooth of the comb teeth extends in a first direction.Fig. 26 is a planar layout view of one pixel circuit of the photodetection element according to the sixth embodiment.Fig. 27A is a circuit diagram of a pixel circuit of a photodetection element according to a first modification example of the sixth embodiment.Fig. 27B is a planar layout view of the pixel circuit in Fig. 27A.Fig. 28A is a circuit diagram of a pixel circuit of a photodetection element according to a second modification example of the sixth embodiment.Fig. 28B is a table illustrating a correspondence relationship between ON or OFF and conversion efficiency of a conversion efficiency switching transistor of the pixel circuit according to the second modification example.Fig. 28C is a planar layout view of the pixel circuit according to the second modification example.Fig. 29A is a circuit diagram of a pixel circuit of a photodetection element according to a third modification example of the sixth embodiment.Fig. 29B is a planar layout view of the pixel circuit according to the third modification example.Fig. 30A is a circuit diagram of a pixel circuit of a photodetection element according to a fourth modification example of the sixth embodiment.Fig. 30B is a table illustrating a correspondence relationship between ON or OFF and conversion efficiency of a conversion efficiency switching transistor of the pixel circuit according to the fourth modification example.Fig. 30C is a planar layout view of the pixel circuit according to the fourth modification example.Fig. 31A is a circuit diagram of a pixel circuit of a photodetection element according to a fifth modification example of the sixth embodiment.Fig. 31B is a planar layout view of the pixel circuit according to the fifth modification example.Fig. 32 is a sectional view of a pixel circuit of a photodetection element according to a sixth modification example.Fig. 33 is a sectional view of a pixel circuit having a sectional structure of a second charge retainer different from a sectional structure in Fig. 32.Fig. 34 is a table listing features of pixel circuits according to the first to sixth modification examples of the sixth embodiment.Fig. 35 is a sectional view illustrating a problem in a case where a second substrate in which pixel transistors are arranged is stacked on a first substrate.Fig. 36 is a sectional view of a photodetection element in a substrate depth direction according to a seventh embodiment.Fig. 37A is a plan view of an optical shield layer, Fig. 37B is a sectional view along line A-B in Fig. 37A in the substrate depth direction, Fig. 37C is a sectional view along line C-D in Fig. 37A in the substrate depth direction, and Fig. 37D is a plan view of a combination of the optical shield layer and a first wiring layer.Fig. 38A is a plan view of an optical shield layer, Fig. 38B is a sectional view along line A-B in Fig. 38A in the substrate depth direction, Fig. 38C is a sectional view along line C-D in Fig. 38A in the substrate depth direction, and Fig. 38D is an external view of some of chips of a photodetection element 1.Fig. 39A is a plan view of an optical shield layer, Fig. 39B is a sectional view along line A-B in Fig. 39A in the substrate depth direction, and Fig. 39C is a sectional view along line C-D in Fig. 39A in the substrate depth direction.Fig. 40A is a plan view of an optical shield layer, Fig. 40B is a sectional view along line A-B in Fig. 40A in the substrate depth direction, Fig. 40C is a sectional view along line C-D in Fig. 40A in the substrate depth direction, and Fig. 40D is an external view of some of chips of a photodetection element.Fig. 41A is a plan view of an optical shield layer, Fig. 41B is a sectional view along line A-B in Fig. 41A in the substrate depth direction, and Fig. 41C is a sectional view along line C-D in Fig. 41A in the substrate depth direction.Fig. 42A is a plan view of an optical shield layer, Fig. 42B is a sectional view along line A-B in Fig. 42A in the substrate depth direction, Fig. 42C is a sectional view along line C-D in Fig. 42A in the substrate depth direction, and Fig. 42D is an external view of some of chips of the photodetection element 1.Fig. 43A is a plan view of an optical shield layer, Fig. 43B is a sectional view along line A-B in Fig. 43A in the substrate depth direction, and Fig. 43C is a sectional view along line C-D in Fig. 43A in the substrate depth direction.Fig. 44A is a plan view of an optical shield layer, Fig. 44B is a sectional view along line A-B in Fig. 44A in the substrate depth direction, Fig. 44C is a sectional view along line C-D in Fig. 44A in the substrate depth direction, and Fig. 44D is an external view of some of chips 21 of the photodetection element 1.Fig. 45A is a plan view of an optical shield layer, Fig. 45B is a sectional view along line A-B in Fig. 45A in the substrate depth direction, and Fig. 45C is a sectional view along line C-D in Fig. 45A in the substrate depth direction.Fig. 46A is a plan view of an optical shield layer, Fig. 46B is a sectional view along line A-B in Fig. 46A in the substrate depth direction, Fig. 46C is a sectional view along line C-D in Fig. 46A in the substrate depth direction, and Fig. 46D is an external view of some of chips of the photodetection element 1.Fig. 47A is a plan view of an optical shield layer, Fig. 47B is a sectional view along line A-B in Fig. 47A in the substrate depth direction, and Fig. 47C is a sectional view along line C-D in Fig. 47A in the substrate depth direction.Fig. 48A is a plan view of an optical shield layer, Fig. 48B is a sectional view along line A-B in Fig. 48A in the substrate depth direction, Fig. 48C is a sectional view along line C-D in Fig. 48A in the substrate depth direction, and Fig. 48D is an external view of some of chips of the photodetection element 1.Fig. 49A is a plan view of an optical shield layer, Fig. 49B is a sectional view along line A-B in Fig. 49A in the substrate depth direction, and Fig. 49C is a sectional view along line C-D in Fig. 49A in the substrate depth direction.Fig. 50A is a plan view of an optical shield layer, Fig. 50B is a sectional view along line A-B in Fig. 50A in the substrate depth direction, Fig. 50C is a sectional view along line C-D in Fig. 50A in the substrate depth direction, and Fig. 50D is an external view of some of chips of the photodetection element 1.Fig. 51A is a plan view of an optical shield layer, Fig. 51B is a sectional view along line A-B in Fig. 51A in the substrate depth direction, and Fig. 51C is a sectional view along line C-D in Fig. 51A in the substrate depth direction.Fig. 52A is a plan view of an optical shield layer, Fig. 52B is a sectional view along line A-B in Fig. 52A in the substrate depth direction, Fig. 52C is a sectional view along line C-D in Fig. 52A in the substrate depth direction, and Fig. 52D is an external view of some of chips of the photodetection element 1.Fig. 53A is a plan view of an optical shield layer, Fig. 53B is a sectional view along line A-B in Fig. 53A in the substrate depth direction, and Fig. 53C is a sectional view along line C-D in Fig. 53A in the substrate depth direction.Fig. 54A is a plan view of an optical shield layer, Fig. 54B is a sectional view along line A-B in Fig. 54A in the substrate depth direction, Fig. 54C is a sectional view along line C-D in Fig. 54A in the substrate depth direction, and Fig. 54D is an external view of some of chips of the photodetection element 1.Fig. 55A is a plan view of an optical shield layer, Fig. 55B is a sectional view along line A-B in Fig. 55A in the substrate depth direction, and Fig. 55C is a sectional view along line C-D in Fig. 55A in the substrate depth direction.Fig. 56A is a plan view of an optical shield layer, Fig. 56B is a sectional view along line A-B in Fig. 56A in the substrate depth direction, Fig. 56C is a sectional view along line C-D in Fig. 56A in the substrate depth direction, and Fig. 56D is an external view of some of chips of the photodetection element 1.Fig. 57A is a plan view of an optical shield layer, Fig. 57B is a sectional view along line A-B in Fig. 57A in the substrate depth direction, Fig. 57C is a sectional view along line C-D in Fig. 57A in the substrate depth direction, and Fig. 57D is a sectional view along line E-F in the substrate depth direction.Fig. 58 is a table listing various modification examples of the seventh embodiment.Fig. 59A is a graph illustrating comparison of sheet resistance between arsenic (As) ions and phosphorus (P) ions.Fig. 59B is a graph illustrating comparison between diffusion lengths in silicon doped with arsenic (As) ions and phosphorus (P) ions.Fig. 60 is a sectional view of a photodetection element according to an eighth embodiment.Fig. 61 is a sectional view of a photodetection element according to a first modification example of the eighth embodiment.Fig. 62 is a sectional view of a photodetection element according to a second modification example of the eighth embodiment.Fig. 63 is a sectional view of a photodetection element 1 according to a third modification example of the eighth embodiment.Fig. 64A is a process-sectional view of the photodetection element according to the eighth embodiment.Fig. 64B is a process-sectional view of a manufacturing process following Fig. 64A.Fig. 64C is a process-sectional view of a manufacturing process following Fig. 64B.Fig. 64D is a process-sectional view of a manufacturing process following Fig. 64C.Fig. 64E is a process-sectional view of a manufacturing process following Fig. 64D.Fig. 64F is a process-sectional view of a manufacturing process following Fig. 64E.Fig. 64G is a process-sectional view of a manufacturing process following Fig. 64F.Fig. 64H is a process-sectional view of a manufacturing process following Fig. 64G.Fig. 64I is a process-sectional view of a manufacturing process following Fig. 64H.Fig. 65A is a longitudinal-sectional view of a photodetection element according to a ninth embodiment.Fig. 65B is a cross-sectional view from line A-B in Fig. 65A.Fig. 66A is a longitudinal-sectional view of a photodetection element according to a first modification example of the ninth embodiment.Fig. 66B is a cross-sectional view from line A-B in Fig. 66A.Fig. 67A is a longitudinal-sectional view of a photodetection element according to a second modification example of the ninth embodiment.Fig. 67B is a cross-sectional view from line A-B in Fig. 67A.Fig. 68A is a longitudinal-sectional view of a photodetection element according to a third modification example of the ninth embodiment.Fig. 68B is a cross-sectional view from line A-B in Fig. 68A.Fig. 69A is a longitudinal-sectional view of a photodetection element according to a fourth modification example of the ninth embodiment.Fig. 69B is a cross-sectional view from line A-B in Fig. 69A.Fig. 70A is a longitudinal-sectional view of a photodetection element according to a fifth modification example of the ninth embodiment.Fig. 70B is a cross-sectional view from line A-B in Fig. 70A.Fig. 71A is a longitudinal-sectional view of a photodetection element according to a sixth modification example of the ninth embodiment.Fig. 71B is a cross-sectional view from line A-B in Fig. 71A.Fig. 72A illustrates a plan view and a process-sectional view of a manufacturing process of the photodetection element according to the ninth embodiment.Fig. 72B illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72A.Fig. 72C illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72B.Fig. 72D illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72C.Fig. 72E illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72D.Fig. 72F illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72E.Fig. 72G illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72F.Fig. 72H illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72G.Fig. 72I illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72H.Fig. 72J illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72I.Fig. 72K illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72J.Fig. 72L illustrates a plan view and a process-sectional view of a manufacturing process following Fig. 72K.Fig. 73 is a circuit diagram of a pixel and a pixel circuit of a photodetection element according to a tenth embodiment.Fig. 74 is a timing diagram of the pixel circuit of Fig. 73.Fig. 75 is a plan view of an interlayer of the photodetection element according to the tenth embodiment.Fig. 76 is a sectional view taken along line A-B in Fig. 75.Fig. 77 is a table summarizing representative modification examples of shapes and layer configurations of an FD wiring layer and an FDB wiring layer in the photodetection element according to the tenth embodiment.Fig. 78 is a plan view of an interlayer of a photodetection element according to a first modification example of the tenth embodiment.Fig. 79 is a sectional view taken along line A-B in Fig. 78.Fig. 80 is a plan view of an interlayer of a photodetection element according to a second modification example of the tenth embodiment.Fig. 81 is a sectional view taken along line A-B in Fig. 80.Fig. 82 is a plan view of an interlayer of a photodetection element according to a third modification example of the tenth embodiment.Fig. 83 is a plan view of the interlayer of the photodetection element according to the third modification example of the tenth embodiment.Fig. 84 is a sectional view of Fig. 82 or 83.Fig. 85 is a plan view of an interlayer of a photodetection element according to a fourth modification example of the tenth embodiment.Fig. 86 is a plan view of the interlayer of the photodetection element according to the fourth modification example of the tenth embodiment.Fig. 87 is a sectional view of Fig. 85 or 86.Fig. 88 is a plan view of an interlayer of a photodetection element according to a fifth modification example of the tenth embodiment.Fig. 89 is a plan view of the interlayer of the photodetection element according to the fifth modification example of the tenth embodiment.Fig. 90 is a sectional view of Fig. 88 or 89.Fig. 91 is a plan view of an interlayer of a photodetection element according to a sixth modification example of the tenth embodiment.Fig. 92 is a plan view of the interlayer of the photodetection element according to the sixth modification example of the tenth embodiment.Fig. 93 is a sectional view of Fig. 91 or 92.Fig. 94 is a plan view of an interlayer of a photodetection element according to a seventh modification example of the tenth embodiment.Fig. 95 is a plan view of the interlayer of the photodetection element according to the seventh modification example of the tenth embodiment.Fig. 96 is a sectional view of Fig. 94 or 95.Fig. 97 is a plan view of an interlayer of a photodetection element according to an eighth modification example of the tenth embodiment.Fig. 98 is a plan view of the interlayer of the photodetection element according to the eighth modification example of the tenth embodiment.Fig. 99 is a sectional view of Fig. 97 or 98.Fig. 100 is a plan view of an interlayer of a photodetection element according to a ninth modification example of the tenth embodiment.Fig. 101 is a plan view of the interlayer of the photodetection element according to the ninth modification example of the tenth embodiment.Fig. 102 is a sectional view of Fig. 100 or 101.Fig. 103 is a plan view of a lower side from an interlayer of a photodetection element according to an eleventh embodiment.Fig. 104 is a plan view of a lower side from a second substrate 20.Fig. 105 is a sectional view taken along line A-A’ in Figs. 103 and 104.Fig. 106 is a sectional view taken along line B-B’ in Figs. 103 and 104.Fig. 107 is a sectional view taken along line C-C’ in Figs. 103 and 104.Fig. 108 is a plan view of a lower side from an interlayer of a photodetection element according to a first modification example of the eleventh embodiment.Fig. 109 is a plan view of a photodetection element according to a second modification example of the eleventh embodiment.Fig. 110 is a sectional view of a photodetection element according to a third modification example of the eleventh embodiment.Fig. 111 is a sectional view of a photodetection element according to a fourth modification example of the eleventh embodiment.Fig. 112 is a sectional view of a photodetection element according to a fifth modification example of the eleventh embodiment.Fig. 113 is a plan view of a lower side from a second substrate of a photodetection element according to a sixth modification example of the eleventh embodiment.Fig. 114 is a plan view of a lower side from a second substrate of a photodetection element according to a seventh modification example of the eleventh embodiment.Fig. 115 is a sectional view of a second substrate in which a fin-shaped gate is disposed on an SOI substrate.Fig. 116 is a plan view of a lower side from a second substrate of a photodetection element according to an eighth modification example of the eleventh embodiment.Fig. 117 is a plan view of a lower side from a second substrate of a photodetection element according to a ninth modification example of the eleventh embodiment.Fig. 118 is a plan view of a lower side from a second substrate of a photodetection element according to a tenth modification example of the eleventh embodiment.Fig. 119 is a plan view of a lower side from a second substrate of a photodetection element according to an eleventh modification example of the eleventh embodiment.Fig. 120 is a sectional view of a photodetection element according to a twelfth modification example of the eleventh embodiment.Fig. 121 is a circuit diagram of a pixel circuit of a photodetection element according to a thirteenth modification example of the eleventh embodiment.Fig. 122 is a sectional view of the photodetection element according to the thirteenth modification example of the eleventh embodiment.Fig. 123A is a plan view illustrating a manufacturing process of the photodetection element according to the eleventh embodiment.Fig. 123B is a sectional view taken along line D-D’ in Fig. 123A.Fig. 124A is a plan view illustrating a manufacturing process continued from Fig. 123A.Fig. 124B is a sectional view taken along line D-D’ in Fig. 124A.Fig. 125A is a plan view illustrating a manufacturing process continued from Fig. 124A.Fig. 125B is a sectional view taken along line D-D’ in Fig. 125A.Fig. 126A is a plan view illustrating a manufacturing process continued from Fig. 125A.Fig. 126B is a sectional view taken along line D-D’ in Fig. 126A.Fig. 127A is a plan view illustrating a manufacturing process continued from Fig. 126A.Fig. 127B is a sectional view taken along line D-D’ in Fig. 127A.Fig. 128A is a plan view illustrating a manufacturing process continued from Fig. 127A.Fig. 128B is a sectional view taken along line D-D’ in Fig. 128A.Fig. 129A is a plan view illustrating a manufacturing process continued from Fig. 128A.Fig. 129B is a sectional view taken along line D-D’ in Fig. 129A.Fig. 130A is a plan view illustrating a manufacturing process continued from Fig. 129A.Fig. 130B is a sectional view taken along line D-D’ in Fig. 130A.Fig. 131A is a plan view illustrating a manufacturing process continued from Fig. 130A.Fig. 131B is a sectional view taken along line D-D’ in Fig. 131A.Fig. 132A is a plan view illustrating a manufacturing process continued from Fig. 131A.Fig. 132B is a sectional view taken along line D-D’ in Fig. 132A.Fig. 133A is a plan view illustrating a manufacturing process continued from Fig. 132A.Fig. 133B is a sectional view taken along line D-D’ in Fig. 133A.Fig. 134A is a plan view illustrating a manufacturing process continued from Fig. 133A.Fig. 134B is a sectional view taken along line D-D’ in Fig. 134A.Fig. 135 is a block diagram illustrating an example of a schematic configuration of a vehicle control system.Fig. 136 is an explanatory view illustrating an example of installation positions of an outside-vehicle information detecting section and an imaging section.

[0032] Hereinafter, embodiments of a photodetection element will be described with reference to the drawings. Although principal components of the photodetection element will be mainly described hereinafter, the photodetection element may include components and have functions that are not illustrated or described. The following description does not exclude components and functions that are not illustrated or described.

[0033] (Schematic Configuration of Photodetection Element) Fig. 1 is a diagram illustrating a schematic configuration of a photodetection element 1 according to an embodiment of the present disclosure. As illustrated in Fig. 1, the photodetection element 1 includes three substrates, that is, a first substrate 10, a second substrate 20, and a third substrate 30. The photodetection element 1 has a three-dimensional structure formed by bonding the three substrates of the first substrate 10, the second substrate 20, and the third substrate 30. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order. The first substrate 10 is disposed at the first layer, the second substrate 20 is disposed at the second layer, and the third substrate 30 is disposed at the third layer.

[0034] The first substrate 10 includes a semiconductor substrate 11 and a plurality of sensor pixels 12 that performs photoelectric conversion. Hereinafter, the sensor pixels 12 are simply referred to as pixels. The semiconductor substrate 11 is provided with the plurality of pixels 12. These pixels 12 are arranged in a matrix (two-dimensional array shape) in a pixel region 13 in the first substrate 10. Each pixel 12 has a photoelectric conversion element and a transfer transistor as described later. A pixel circuit is connected to each pixel 12.

[0035] The second substrate 20 includes a semiconductor substrate 21, a pixel circuit 22 that outputs a pixel signal, a plurality of pixel drive lines 23 extending in a row direction, and a plurality of vertical signal lines 24 extending in a column direction. The semiconductor substrate 21 is provided with one pixel circuit 22 for every four pixels 12. Each of the pixel circuits 22 outputs a pixel signal based on charge output from the pixels 12. The pixel circuit 22 is also referred to as a readout circuit.

[0036] The third substrate 30 includes a semiconductor substrate 31 and a logic circuit 32 that processes a pixel signal. The semiconductor substrate 31 is provided with the logic circuit 32. The logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36.

[0037] The logic circuit 32 outputs an output voltage Vout for each pixel 12 to the outside. Note that, in the logic circuit 32, a low-resistance region may be formed on a front surface of an impurity diffusion region that is in contact with a source electrode and a drain electrode, for example, the low-resistance region being made of a silicide formed using a salicide (self-aligned silicide) process, such as CoSi2 or NiSi.

[0038] The vertical drive circuit 33 selects the plurality of pixels 12 row by row in sequence, for example.

[0039] The column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on the pixel signal output from each pixel 12 in a row selected by the vertical drive circuit 33. For example, the column signal processing circuit 34 extracts a signal level of each pixel signal by performing CDS processing and holds pixel data corresponding to a received light amount of each pixel 12.

[0040] The horizontal drive circuit 35 sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside, for example.

[0041] The system control circuit 36 controls driving of each block (vertical drive circuit 33, column signal processing circuit 34, and horizontal drive circuit 35) in the logic circuit 32, for example.

[0042] (Example of Pixel Circuit) Next, an example of a pixel circuit according to a first embodiment will be described with reference to Fig. 2. Fig. 2 is a diagram illustrating the example of the pixel circuit according to the first embodiment.

[0043] As illustrated in Fig. 2, four pixels 12 share one pixel circuit 22. Here, “to share” indicates that the four pixels 12 are electrically connected to the common pixel circuit 22, that is, outputs of the four pixels 12 are input to the common pixel circuit 22.

[0044] Each pixel 12 has a common component. In Fig. 2, in order to distinguish between components of each pixel 12 from each other, an identification number (1, 2, 3, or 4) is attached to an end of each of reference signs of the components of each pixel 12. In the following, in a case where it is necessary to distinguish between the components of the pixels 12 from each other, the identification number is attached to the end of each of the reference signs of the components of each pixel 12; however, in a case where there is no need to distinguish between the components of the pixels 12 from each other, the identification number at the end of each of the reference signs of the components of each pixel 12 is omitted.

[0045] Each of the pixels 12 includes, for example, both a photodiode PD and a transfer transistor TR electrically connected to the photodiode PD. These pixels 12 share a floating diffusion FD electrically connected to each transfer transistor TR. Here, “to share” indicates that the individual photodiodes PD of the pixels 12 are electrically connected to the floating diffusion FD. The photodiodes PD, the transfer transistors TR, the floating diffusion FD, and the like are provided in the first substrate 10, for example.

[0046] The photodiode PD generates a charge corresponding to a received light amount by performing photoelectric conversion. A cathode of the photodiode PD is electrically connected to a source of the transfer transistor TR, and an anode of the photodiode PD is electrically connected to a reference potential line (for example, ground). The photodiode PD is an example of a photoelectric conversion element.

[0047] A drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and a transfer gate TG which is a gate of the transfer transistor TR is electrically connected to the pixel drive line 23 (see Fig. 1). The transfer transistor TR is, for example, a complementary metal oxide semiconductor (CMOS) transistor.

[0048] The floating diffusion FD is shared by the pixels 12 sharing one pixel circuit 22 and is electrically connected to an input end of the pixel circuit 22 shared by the pixels 12. The floating diffusion FD temporarily retains a charge output from the photodiode PD via the transfer transistor TR. The floating diffusion FD is an example of a floating diffusion layer.

[0049] The pixel circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and an FD transfer transistor FDG. The reset transistor RST, the selection transistor SEL, the amplification transistor AMP, the FD transfer transistor FDG, and the like are provided in, for example, the second substrate 20 or the third substrate 30. The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the FD transfer transistor FDG are, for example, CMOS transistors. Note that the selection transistor SEL or the FD transfer transistor FDG may be omitted as necessary.

[0050] A source of the FD transfer transistor FDG (an input end of the pixel circuit 22) is electrically connected to the floating diffusion FD, and a drain of the FD transfer transistor FDG is electrically connected to a source of the reset transistor RST. A gate of the FD transfer transistor FDG is electrically connected to the pixel drive line 23 (see Fig. 1).

[0051] A drain of the reset transistor RST is electrically connected to a power line VDD. A gate of a reset transistor RST is electrically connected to the pixel drive line 23 (see Fig. 1).

[0052] A source of the amplification transistor AMP is electrically connected to a drain of the selection transistor SEL, and a drain of the amplification transistor AMP is electrically connected to the power line VDD. A gate of the amplification transistor AMP is electrically connected to the source of the FD transfer transistor FDG.

[0053] The drain of the selection transistor SEL (an output end of the pixel circuit 22) is electrically connected to the vertical signal line 24 (VSL in Fig. 2), and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23 (see Fig. 1).

[0054] The transfer transistor TR transfers a charge of the photodiode PD to the floating diffusion FD when turned on.

[0055] The reset transistor RST resets a potential of the floating diffusions FD to a predetermined potential. The reset transistor RST resets a potential of the floating diffusions FD to a potential of the power line VDD when turned on. The selection transistor SEL controls an output timing of the pixel signal from the pixel circuit 22.

[0056] The amplification transistor AMP generates, as a pixel signal, a signal of a voltage corresponding to a level of a charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source follower type amplifier and outputs a pixel signal of a voltage corresponding to the level of the charge generated by the photodiode PD.

[0057] When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 (see Fig. 1) via the vertical signal line 24.

[0058] The FD transfer transistor FDG is used to switch conversion efficiency. In general, a pixel signal is small at the time of performing imaging at a dark location. On the basis of Q = CV, if the capacitance (FD capacitance C) of the floating diffusion FD is large at the time of performing charge-voltage conversion, V at the time of conversion into a voltage by the amplification transistor AMP becomes small. On the other hand, the pixel signal becomes large at a bright location; thus, if the FD capacitance C is not large, it is difficult to receive the charge of the photodiode PD at the floating diffusion FD. Further, the FD capacitance C needs to be large so that V at the time of conversion into a voltage by the amplification transistor AMP does not become too large (in other words, decreases).

[0059] That is, when the FD transfer transistor FDG is turned on, the gate capacitance corresponding to the FD transfer transistor FDG increases, and thus the entire FD capacitance C increases. On the other hand, when the FD transfer transistor FDG is turned off, the entire FD capacitance C decreases. In this manner, by performing ON / OFF switching of the FD transfer transistor FDG, the FD capacitance C can be made variable, and the conversion efficiency can be switched.

[0060] (Cross-Sectional Structure of Photodetection Element 1) An example of a cross-sectional configuration of the photodetection element 1 according to the embodiment of the present disclosure will be described with reference to Fig. 3. Fig. 3 is a diagram illustrating an example of a longitudinal-sectional configuration (sectional configuration in a vertical direction) of the photodetection element 1 according to the embodiment of the present disclosure.

[0061] As illustrated in Fig. 3, the photodetection element 1 is formed by stacking the first substrate 10, the second substrate 20, and the third substrate 30 in this order and further includes a color filter 40 and a light-receiving lens 50 on a back surface side (light incident surface side) of the first substrate 10. For example, one color filter 40 and one light-receiving lens 50 are provided for each pixel 12. That is, the photodetection element 1 is a back-illuminated type.

[0062] The first substrate 10 is formed by stacking an insulating layer 46 on the semiconductor substrate 11. The insulating layer 46 is also referred to as an interlayer insulating layer. The insulating layer 46 is provided in a gap between the semiconductor substrate 11 and the semiconductor substrate 21 to be described later.

[0063] The semiconductor substrate 11 is made of a silicon substrate. The semiconductor substrate 11 has, for example, a p-well layer 42 at a part of a front surface and in the vicinity thereof and has a photodiode PD of a conductivity type different from that of the p-well layer 42 in another region (region deeper than the p-well layer 42). The p-well layer 42 has a p-type semiconductor region. The photodiode PD has a semiconductor region of a conductivity type (specifically, n-type) different from that of the p-well layer 42. The semiconductor substrate 11 has, in the p-well layer 42, the floating diffusion FD as a semiconductor region of a conductivity type (specifically, n-type) different from that of the p-well layer 42.

[0064] In the example of Fig. 3, one floating diffusion FD has four adjacent diffusion layers (floating diffusion layers) FDa and one connection layer FDb. Each of the diffusion layers FDa is provided for each photodiode PD, and the individual diffusion layers FDa of the four adjacent photodiodes PD are electrically connected by one connection layer FDb. The connection layer FDb is positioned above the diffusion layers FDa to be in contact with the diffusion layers FDa and is provided in the insulating layer 46. The connection layer FDb is made of the same material (for example, polysilicon) as the transfer gate TG.

[0065] The first substrate 10 has the photodiode PD and the transfer transistor TR for each pixel 12. Further, the floating diffusion FD and a well tap WT are shared by the four pixels 12. The transfer transistor TR, the floating diffusion FD, and the well tap WT are provided at portions on the front surface side (side opposite to a light incident surface side, or the second substrate 20 side) of the semiconductor substrate 11. The well tap WT is electrically connected to the p-well layer 42 (for example, a well contact formed in the p-well layer 42).

[0066] The first substrate 10 has an element isolation portion 43 that separates the individual pixels 12. The element isolation portion 43 is formed to extend in a normal direction of the semiconductor substrate 11 (a direction perpendicular to the front surface of the semiconductor substrate 11). The element isolation portion 43 is provided between two pixels 12 adjacent to each other. The element isolation portion 43 electrically isolates the pixels 12 adjacent to each other from each other. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43 penetrates the semiconductor substrate 11 (as a full trench), for example, and electrically isolates two or more adjacent pixels 12 from each other completely.

[0067] The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, at a position which is in contact with the back surface of the semiconductor substrate 11 and faces the pixel 12. The light-receiving lens 50 is provided, for example, at a position which is in contact with the back surface of the color filter 40 and faces the pixel 12 via the color filter 40.

[0068] The second substrate 20 is formed by stacking an insulating layer 52 on the semiconductor substrate 21. The insulating layer 52 is also referred to as an interlayer insulating layer. The insulating layer 52 is provided in a gap between the semiconductor substrate 21 and the semiconductor substrate 31 to be described later. The semiconductor substrate 21 is made of a silicon substrate.

[0069] The second substrate 20 is provided with one pixel circuit 22 for every four pixels 12 (see Fig. 2 or 3). The pixel circuit 22 is provided at a portion on the back surface side (first substrate 10 side) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the back surface of the semiconductor substrate 21 facing the front surface side of the semiconductor substrate 11. That is, the second substrate 20 is bonded to the first substrate 10 in a face-to-back manner.

[0070] The second substrate 20 further has an insulating layer 53 penetrating the semiconductor substrate 21 in the same layer as the semiconductor substrate 21. The insulating layer 53 is also referred to as an interlayer insulating layer. The insulating layer 53 is provided to cover a side surface of a penetration wiring 54 to be described later.

[0071] As described above, a stacked body including the first substrate 10 and the second substrate 20 has an interlayer insulating layer 51 including the insulating layer 46, the insulating layer 52, and the insulating layer 53, and the penetration wiring 54 provided in the interlayer insulating layer 51. The stacked body described above has one penetration wiring 54 for every four pixels 12. The penetration wiring 54 extends in a normal direction of the semiconductor substrate 21 and is provided to penetrate a portion including the insulating layer 53 in the interlayer insulating layer 51. The first substrate 10 and the second substrate 20 are electrically connected to each other by the penetration wiring 54. The penetration wiring 54 is, for example, a penetration contact for the floating diffusions FD (FD1 to FD4).

[0072] The stacked body including the first substrate 10 and the second substrate 20 also has another penetration wiring (not illustrated) provided in the interlayer insulating layer 51. Similarly to the penetration wiring 54 described above, the penetration wiring also extends in the normal direction of the semiconductor substrate 21 and is provided to penetrate the portion including an insulating layer having the same configuration as the insulating layer 53 in the interlayer insulating layer 51. The first substrate 10 and the second substrate 20 are electrically connected to each other by the penetration wiring. The penetration wiring is, for example, a penetration contact for the transfer gate TG, a penetration contact for the well tap WT, or the like.

[0073] The second substrate 20 has, for example, a plurality of connection portions 59 electrically connected to the pixel circuit 22 and the semiconductor substrate 21 in the insulating layer 52. Further, the second substrate 20 has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 includes, for example, an insulating layer 57, a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24 provided in the insulating layer 57. For example, the wiring layer 56 further includes, for each floating diffusion FD, a connection wiring 55 in the insulating layer 57. The connection wiring 55 is electrically connected to the penetration wiring 54 connected to the floating diffusion FD.

[0074] Here, the total number of the penetration wirings 54 functioning as the penetration contact for the floating diffusion FD is smaller than the total number of the pixels 12 included in the first substrate 10, and for example, since the number of the pixels 12 sharing the floating diffusion FD is four, the total number of the penetration wirings 54 is 1 / 4 times the total number of the pixels 12 included in the first substrate 10. Similarly, the total number of penetration wirings (not illustrated) functioning as the penetration contact for the transfer gate TG and the total number of penetration wirings (not illustrated) functioning as the penetration contact for the well tap WT are, for example, 1 / 4 times the total number of the pixels 12 included in the first substrate 10.

[0075] The wiring layer 56 further has, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is made of metal such as copper (Cu) or aluminum (Al), for example. Each pad electrode 58 is exposed from a front surface of the wiring layer 56. Each pad electrode 58 is used for electrical connection between the second substrate 20 and the third substrate 30 and performing bonding between the second substrate 20 and the third substrate 30. For example, each pad electrode 58 is provided for each of the pixel drive lines 23 and the vertical signal lines 24.

[0076] The third substrate 30 is formed by stacking an interlayer insulating layer 61 on the semiconductor substrate 31. The semiconductor substrate 31 is made of a silicon substrate. Note that, as described later, since the third substrate 30 is bonded to the second substrate 20 with the surfaces thereof on the front surface side, the description of up and down is opposite to a vertical direction in the drawings when a configuration in the third substrate 30 is described.

[0077] The third substrate 30 is provided with the logic circuit 32 on a portion of the semiconductor substrate 31 on the front surface side. The third substrate 30 has, for example, a wiring layer 62 on the interlayer insulating layer 61. The wiring layer 62 has, for example, an insulating layer 63 and a plurality of pad electrodes 64 provided in the insulating layer 63. Each pad electrode 64 is electrically connected to the logic circuit 32. Each pad electrode 64 is made of, for example, copper (Cu). Each pad electrode 64 is exposed from a front surface of the wiring layer 62. Each pad electrode 64 is used for electrical connection between the second substrate 20 and the third substrate 30 and performing bonding between the second substrate 20 and the third substrate 30. Note that there is no need to provide the plurality of pad electrodes 64, but one pad electrode may be provided.

[0078] The third substrate 30 and the second substrate 20 are electrically connected to each other by bonding the pad electrodes 58 and 64 to each other. The third substrate 30 is bonded to the second substrate 20 with the front surface of the semiconductor substrate 31 facing the front surface side of the semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 in a face-to-face manner.

[0079] (First Embodiment) As described above, the insulating layer (interlayer insulating layer) 46 is disposed between the first substrate 10 and the second substrate 20. In the present specification, the insulating layer 46 may be referred to as an interlayer 70. In the cross-sectional structure of the photodetection element 1 illustrated in Fig. 3, layer heights (hereinafter, referred to as a layer) of all wiring layers 71 arranged in the interlayer 70 are the same. In the interlayer 70, a plurality of wiring layers 71 including a wiring layer 71a for setting the p-well layer 42 of the first substrate 10 to a ground potential, a wiring layer 71b for transferring the charge accumulated in the floating diffusion FD to the pixel circuit 22 of the second substrate 20, and a wiring layer 71c connected to the transfer gate TG are arranged. The potentials of these wiring layers 71 are not the same, electrical characteristics such as a resistance value are also different, and types and doping amounts of impurity ions doped in the respective wiring layers 71 are also different. Thus, in order to arrange the plurality of wiring layers 71 at the same layer of the interlayer 70, it is necessary to reduce interference by separating the wiring layers 71 as much as possible, and it is difficult to reduce an area of the interlayer 70.

[0080] Each of the wiring layers 71 arranged in the interlayer 70 is formed by a polysilicon layer or a metal layer. In the present specification, an example in which each of the wiring layers 71 arranged in the interlayer 70 is formed by the polysilicon layer will be mainly described.

[0081] In addition, at least one of a type and a concentration of impurity ions contained in the wiring layers 71 arranged in the interlayer 70 may be different between the wiring layers. Of the plurality of wiring layers 71 arranged in the interlayer 70, at least some of two or more wiring layers 71 arranged at respective different layers (also referred to as being arranged at different levels) may be arranged to overlap each other in a plan view or may be arranged to intersect each other.

[0082] Fig. 4 is a planar layout view of the photodetection element 1 according to a first embodiment. Fig. 4 illustrates an example in which four pixels 12 share the floating diffusion FD and the pixel circuit 22. A solid circle in Fig. 4 represents a penetration contact 72 (72b) extending from the wiring layer 71 of the interlayer 70 to the second substrate 20 and may be simply referred to as a contact in the present specification.

[0083] Fig. 5A is a sectional view along line A-A’-B’-B in Fig. 4 in a substrate depth direction, and Fig. 5B is a sectional view along line C-D in Fig. 4 in the substrate depth direction. The photodetection element 1 according to the first embodiment has a structure in which the wiring layers 71 of two or more layers are stacked in the interlayer 70. In the examples of Figs. 5A and 5B, the first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c are arranged in the interlayer 70.

[0084] The first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c are arranged at respective different layers of the interlayer 70. More specifically, the first wiring layer 71a is disposed on a side of the interlayer 70 close to the first substrate 10. The second wiring layer 71b and the third wiring layer 71c are arranged on a side of the interlayer 70 close to the second substrate 20. That is, the second wiring layer 71b and the third wiring layer 71c are arranged above (above the front surface side of) the first wiring layer 71a.

[0085] Note that, as described later, in the photodetection element 1 according to the present embodiment, a modification example can also be employed in which layers of the first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c are arranged in an inverted manner.

[0086] The first wiring layer 71a is connected to the p-well layer 42 of the first substrate 10 via a first contact 73a. The second wiring layer 71b is connected to the floating diffusion FD of the first substrate 10 via a second contact 73b. The third wiring layer 71c is connected to the transfer gate TG of the first substrate 10 via a third contact 73c. A first penetration contact 72a extending from the interlayer 70 toward the second substrate 20 is connected to the second wiring layer 71b. The first penetration contact 72a penetrates an insulating layer 29 of the second substrate 20 and extends upward. The second penetration contact 72b extending from the interlayer 70 toward the second substrate 20 is connected to the third wiring layer 71c. The first penetration contact 72a and the second penetration contact 72b are connected to the pixel circuit 22 disposed on the second substrate 20. In the present specification, the penetration contact may be referred to as a through contact substrate (TCS).

[0087] As illustrated in Figs. 5A and 5B, of the first to third wiring layers 71a, 71b, and 71c arranged in the interlayer 70, the first wiring layer 71a is disposed at a layer different from the layers of the second wiring layer 71b and the third wiring layer 71c. Therefore, intervals between the first to third wiring layers 71a, 71b, and 71c can be widened, interference between the first to third wiring layers 71a, 71b, and 71c can be reduced, and a defect of an increase in the resistance values of the first to third wiring layers 71a, 71b, and 71c due to interference does not arise.

[0088] Figs. 6A to 6C illustrate plan views of the first wiring layer 71a and the second wiring layer 71b. More specifically, Fig. 6A is a plan view of the first wiring layer 71a, Fig. 6B is a plan view of the second wiring layer 71b, and Fig. 6C is a plan view in which the first wiring layer 71a and the second wiring layer 71b are overlapped. As illustrated in Fig. 6A, the first wiring layer 71a connected to the p-well layer 42 is disposed along a boundary region of the pixels 12. The second wiring layer 71b connected to the floating diffusion FD is disposed to straddle every two upper, lower, right, or left pixels 12. Since the first wiring layer 71a and the second wiring layer 71b are arranged at respective different layers in the interlayer 70, there is no possibility that the first wiring layer 71a and the second wiring layer 71b are short-circuited even if the first wiring layer 71a and the second wiring layer 71b intersect each other in a plan view as illustrated in Fig. 6C.

[0089] Fig. 7 is a planar layout view of a photodetection element 100 according to a comparative example. Fig. 8A is a sectional view along line A-A’-B’-B in Fig. 7 in the substrate depth direction, and Fig. 8B is a sectional view along line C-D in Fig. 7 in the substrate depth direction.

[0090] In the photodetection element 100 according to the comparative example, the layers of the plurality of wiring layers 71 arranged in the interlayer 70 are the same. Thus, as illustrated in Fig. 8A, it is necessary to increase the distances between the plurality of wiring layers 71 (71b) doped with different impurity ions as much as possible. However, as illustrated in Fig. 8B, it is difficult to sufficiently secure the distances between the plurality of wiring layers 71 (71c) depending on locations, and a defect such as an increase in resistance values of the wiring layers 71 due to interference therebetween arises.

[0091] In the photodetection element 1 according to the first embodiment, since the plurality of wiring layers 71 (71a to 71c) having different types or doping amounts of impurity ions are arranged at respective different layers of the interlayer 70, a distance between the wiring layers 71 is easily secured, and the interference therebetween can be reduced.

[0092] In the photodetection element 1 according to the present embodiment, the floating diffusion FD and the pixel circuit 22 may be arranged for each pixel 12, or a set of the floating diffusion FD and the pixel circuit 22 may be shared by a plurality of pixels 12. The number of pixels 12 sharing the floating diffusion FD and the pixel circuit 22 is randomly selected, and various modification examples are conceivable.

[0093] Figs. 9A and 9B are circuit diagrams of a first example of the pixels 12 and the pixel circuit 22, Fig. 9A is a planar layout view illustrating an arrangement of color filters 40 according to the first example, and Fig. 9B is a circuit diagram of the pixels 12 and the pixel circuit 22 according to the first example. In the first example, 4 × 4 = 16 pixels 12 share a set of the floating diffusion FD and the pixel circuit 22. In Fig. 9A, a difference in color between the color filters 40 is represented by a difference in shading.

[0094] As illustrated in Fig. 9A, in the first example, the color filters 40 of the same color are arranged in units of four pixels 12 in each of a first direction (horizontal direction) X and a second direction (vertical direction) Y. In addition, as illustrated in Fig. 9B, in the first example, the set of the floating diffusion FD and the pixel circuit 22 are shared in units of 4 × 4 = 16 pixels 12 of the same color.

[0095] In Fig. 9B, each pixel 12 includes a photodiode PD and a transfer transistor TR. Each pixel circuit 22 has, for example, a plurality of pixel transistors including an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and a conversion efficiency switching transistor FDG. The conversion efficiency switching transistor FDG may be omitted.

[0096] Figs. 10A and 10B are circuit diagrams of a second example of the pixels 12 and the pixel circuit 22, Fig. 10A is a planar layout view illustrating an arrangement of color filters 40 according to the second example, and Fig. 10B is a circuit diagram of the pixels 12 and the pixel circuit 22 according to the second example. In the second example, 4 × 2 = 8 pixels 12 share the floating diffusion FD and the pixel circuit 22.

[0097] As illustrated in Fig. 10A, in the second example, the color filters 40 of the same color are arranged in units of four pixels 12 in the first direction (horizontal direction) X and two pixels 12 in the second direction (vertical direction) Y. In addition, as illustrated in Fig. 10B, in the second example, the set of the floating diffusion FD and the pixel circuit 22 are shared in units of 4 × 2 = 8 pixels 12 of the same color.

[0098] Figs. 11A and 11B are circuit diagrams of a third example of the pixels 12 and the pixel circuit 22, Fig. 11A is a planar layout view illustrating an arrangement of color filters 40 according to the third example, and Fig. 11B is a circuit diagram of the pixels 12 and the pixel circuit 22 according to the third example. In the third example, 8 × 4 = 32 pixels 12 share a set of the floating diffusion FD and the pixel circuit 22.

[0099] As illustrated in Fig. 11A, in the third example, the color filters 40 of the same color are arranged in units of eight pixels 12 in the first direction (horizontal direction) X and four pixels 12 in the second direction (vertical direction) Y. In addition, as illustrated in Fig. 11B, in the third example, the floating diffusion FD and the pixel circuit 22 are shared in units of 8 × 4 = 32 pixels 12 of the same color.

[0100] A circuit configuration of the pixels 12 and the pixel circuit 22 can also take a circuit configuration other than the first to third examples described above.

[0101] In this manner, in the first embodiment, since the plurality of wiring layers 71 at different layers is stacked in the interlayer 70 (interlayer insulating layer) between the first substrate 10 and the second substrate 20, it is easy to secure the distances between the wiring layers 71, and it is possible to reduce the interference between the plurality of wiring layers 71 and prevent a defect such as an increase in the resistance values. According to the present embodiment, since the plurality of wiring layers 71 can be arranged to overlap each other vertically in a plan view, a degree of freedom in arrangement locations of the plurality of wiring layers 71 in the interlayer 70 increases, and layout design of the pixels is facilitated.

[0102] (Second Embodiment) In a photodetection element 1 according to a second embodiment, similarly to the first embodiment, two or more wiring layers 71 are stacked in an interlayer 70 including an insulating layer (interlayer insulating layer) 46 between a first substrate 10 and a second substrate 20.

[0103] In the photodetection element 1 according to the second embodiment, for example, a first wiring layer 71a connected to the p-well layer 42, a second wiring layer 71b connected to the floating diffusion FD, and a third wiring layer 71c connected to the transfer gate TG of the transfer transistor TR are arranged in the interlayer 70. The first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c are arranged at respective different layers of the interlayer 70.

[0104] Therefore, by arranging the first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c at respective different layers of the interlayer 70, an arrangement location of the third wiring layer 71c connected to the transfer gate TG of the transfer transistor TR can be determined regardless of an arrangement location of the first wiring layer 71a connected to the p-well layer 42.

[0105] Therefore, a distance between a contact (hereinafter, referred to as a first penetration contact 72a) on the second wiring layer 71b connected to the floating diffusion FD and a contact (hereinafter, referred to as a second penetration contact 72b) on the third wiring layer 71c connected to the transfer gate TG can be increased as much as possible, and capacitive coupling between the first penetration contact 72a and the second penetration contact 72b can be reduced.

[0106] Fig. 12 is a sectional view illustrating arrangement locations of the first wiring layer 71a and the second wiring layer 71b in the photodetection element 1 according to the second embodiment, Fig. 13A is a planar layout view illustrating the distance between the first penetration contact 72a on the second wiring layer 71b and the second penetration contact 72b on the third wiring layer, and Fig. 13B is a planar layout view illustrating an empty region of the second substrate 20. The empty region is a region where the penetration contact 72 is not present and a pixel transistor can be formed.

[0107] As illustrated in Fig. 12, since the first wiring layer 71a connected to the p-well layer 42 and the third wiring layer 71c connected to the transfer gate TG are disposed at respective different layers of the interlayer 70, the first wiring layer 71a and the third wiring layer 71c can be disposed to at least partially overlap each other vertically in a plan view. Accordingly, as illustrated in Fig. 12, the second penetration contact 72b extending from the third wiring layer 71c to the second substrate 20 can be disposed immediately above the p-well layer 42. Therefore, the distance between the first penetration contact 72a extending from the first wiring layer 71a connected to the floating diffusion FD to the second substrate 20 and the above-described second penetration contact 72b can be increased as much as possible.

[0108] The first penetration contact 72a and the second penetration contact 72b are connected to the pixel circuit 22 disposed in the second substrate 20. As illustrated in Figs. 13A and 13B, the first penetration contact 72a is disposed in the vicinity of both end portions of a center line of the four pixels 12 of share targets, and the second penetration contact 72b is disposed at a center portion of the four pixels 12 of the share targets. Thus, in the second substrate 20, a region 74 where the first penetration contact 72a and the second penetration contact 72b are not present is widened, and this region 74 can be used as a formation region of pixel transistors, and an arrangement margin of the pixel transistors is increased.

[0109] Fig. 14 is a sectional view illustrating arrangement locations of a first wiring layer 71a, a second wiring layer 71b, and a third wiring layer 71c in the photodetection element 100 according to the comparative example, Fig. 15A is a planar layout view illustrating a distance between a first penetration contact 72a and a second penetration contact 72b in the comparative example, and Fig. 15B is a planar layout view illustrating an empty region 74 of a second substrate 20 in the comparative example.

[0110] In the photodetection element 100 according to the comparative example, as illustrated in Fig. 14, since all the wiring layers 71 formed in the interlayer 70 are arranged at the same layer, it is difficult to too shorten a distance between the first wiring layer 71a connected to the p-well layer 42 and the third wiring layer 71c connected to the transfer gate TG. Thus, it is difficult to increase the distance between the second penetration contact 72b extending from the third wiring layer 71c to the second substrate 20 and the first penetration contact 72a extending from the third wiring layer 71c connected to the floating diffusion FD to the second substrate 20, and there is a possibility that the capacitive coupling occurs. In addition, as illustrated in Figs. 15A and 15B, since the second penetration contact 72b is disposed on an inner side from the vicinity of a boundary of a pixel group including the four pixels 12 of the share targets, an empty region 74 that can be used to form the pixel transistors in the second substrate 20 is narrower than the region 74 of the present embodiment illustrated in Fig. 13B.

[0111] In this manner, in the second embodiment, by disposing, immediately above the first wiring layer 71a connected to the p-well layer 42, the third wiring layer 71c connected to the transfer gate TG, the distance between the second penetration contact 72b extending from the third wiring layer 71c to the second substrate 20 and the first penetration contact 72a extending from the second wiring layer 71b connected to the floating diffusion FD to the second substrate 20 can be increased, the capacitive coupling between the first penetration contact 72a and the second penetration contact 72b can be reduced, and a region where the pixel transistors can be formed in the second substrate 20 can be widened.

[0112] (Third Embodiment) A photodetection element 1 according to a third embodiment is characterized in that two or more wiring layers 71 are stacked in the interlayer 70 (interlayer insulating layer), similarly to the first and second embodiments.

[0113] A first wiring layer 71a is connected to the p-well layer 42 via a first contact 73a. By connecting the first wiring layer 71a to, for example, a ground node, the p-well layer 42 can be set to a ground potential. Normally, the p-well layers 42 of the pixels 12 are set to the same potential. Accordingly, the photodetection element 1 according to the third embodiment is characterized in that the first contacts 73a are not individually connected to the p-well layers 42 of the pixels 12, but the first contacts 73a are connected to some of the p-well layers 42, so that all the p-well layers 42 are set to the same potential (for example, the ground potential).

[0114] Fig. 16A is a planar layout view of a first substrate 10 of the photodetection element 1 according to the third embodiment, and Fig. 16B is a planar layout view of a second substrate 20 of the photodetection element 1 according to the third embodiment. As illustrated in Figs. 16A and 16B, first penetration contacts 72a and second penetration contacts 72b are provided between the first substrate 10 and the second substrate 20. The first penetration contacts 72a are connected to a second wiring layer 71b, and the second wiring layer 71b is connected to the floating diffusion FD via second contacts 73b. The first penetration contact 72a is provided for every four pixels 12 which are share targets. The second penetration contact 72b is connected to a third wiring layer 71c, and the third wiring layer 71c is connected to the transfer gate TG via the third contact 73c. The second penetration contact 72b is provided for each pixel 12.

[0115] As illustrated in Figs. 16A and 16B, the p-well layers 42 of the respective pixels 12 are connected in the first substrate 10, and the first contacts 73a and the first wiring layer 71a individually connected to the respective pixels 12 are omitted. Therefore, there is no need to provide the penetration contacts 72 extending from the first wiring layers 71a corresponding to the respective pixels 12 to the second substrate 20. Accordingly, in the second substrate 20, the first penetration contacts 72a and the second penetration contacts 72b are arranged, but there is no arrangement of the penetration contacts 72 for connection to the p-well layers 42.

[0116] The p-well layers 42 of the respective pixels 12 are connected in the first substrate 10, and the p-well layers 42 of the respective pixels 12 can be set to any potential by providing contacts (hereinafter, third penetration contacts) 72c extending from any one portion or a plurality of portions to the second substrate 20 among a plurality of first wiring layers connected to the respective p-well layers 42. The third penetration contacts 72c may be provided at any one or a plurality of portions in a pixel region or may be arranged outside the pixel region.

[0117] In this manner, since the second substrate 20 does not need to have, in the pixel region, an arrangement region of the penetration contacts 72 for the connection to the p-well layers 42, the second penetration contacts 72b can be arranged on the boundary side of the pixel region accordingly, and an empty region on the second substrate 20 can be widened.

[0118] Fig. 17A is a planar layout view of a first substrate 10 according to a comparative example, and Fig. 17B is a planar layout view of a second substrate 20 according to the comparative example. In the comparative example, contacts (third penetration contacts 72c) extending from a first wiring layer 71a connected to the p-well layer 42 for each pixel 12 to the second substrate 20 are provided. As illustrated in Fig. 17B, these third penetration contacts 72c are arranged at corners of each pixel 12. Accordingly, second penetration contacts 72b have to be arranged on an inner side from the third penetration contacts 72c, and in the second substrate 20, a region surrounded by the first penetration contacts 72a and the second penetration contacts 72b becomes an empty region where the pixel transistors can be formed, and the empty region becomes narrow.

[0119] In this manner, in the third embodiment, the p-well layers 42 of the respective pixels 12 are connected in the first substrate 10, and the contact (third penetration contact) 72c extending from the first wiring layer 71a connected to the p-well layers 42 to the second substrate 20 is not provided for each pixel 12. Therefore, the number of contacts 72 connected to the second substrate 20 can be reduced, and a sufficient region for forming the pixel transistors can be secured in the second substrate 20.

[0120] (Fourth Embodiment) In a photodetection element 1 according to a fourth embodiment, the capacitive coupling between the wiring layers 71 arranged in the interlayer 70 and gates of the pixel transistors arranged in the second substrate 20 is reduced.

[0121] In the photodetection element 1 according to the fourth embodiment, two or more wiring layers 71 are stacked in the interlayer 70, similarly to the first to third embodiments. More specifically, in the interlayer 70, a first wiring layer 71a connected to the p-well layer 42, a second wiring layer 71b connected to the floating diffusion FD, and a third wiring layer 71c connected to the transfer gate TG are arranged.

[0122] In a case where pixel transistors having a FIN gate are arranged by the silicon on insulator (SOI) in the second substrate 20, a p-well layer is not disposed in the second substrate 20. The second wiring layer 71b and the third wiring layer 71c of the interlayer 70 contain a large amount of n-type impurity ions. Accordingly, there is a possibility that the FIN gate of the second substrate 20 and the second wiring layer 71b or the third wiring layer 71c of the interlayer 70 may cause the capacitive coupling.

[0123] Fig. 18 is a sectional view of the photodetection element 1 according to the fourth embodiment. In the photodetection element 1 according to the fourth embodiment, the first wiring layer 71a is disposed between a FIN gate 25 of the second substrate 20 and the second wiring layer 71b and the third wiring layer 71c of the interlayer 70. That is, the second wiring layer 71b and the third wiring layer 71c in the interlayer 70 are arranged on a side close to the first substrate 10, and the first wiring layer 71a in the interlayer 70 is disposed on a side close to the second substrate 20. The second wiring layer 71b and the third wiring layer 71c contain a large amount of n-type impurity ions, whereas the first wiring layer 71a contains many p-type impurity ions. According to the present embodiment, the first wiring layer 71a is disposed between the FIN gate 25 and the second wiring layer 71b and the third wiring layer 71c, and thus the capacitive coupling between the FIN gate 25 and the second wiring layer 71b and the third wiring layer 71c can be reduced.

[0124] Fig. 19 is a sectional view of the photodetection element 100 according to the comparative example. In the photodetection element 100 according to the comparative example, all the wiring layers 71 arranged in the interlayer 70 are arranged at the same layer. Thus, it is difficult for the first wiring layer 71a to be disposed between the FIN gate 25 and the second wiring layer 71b and the third wiring layer 71c, and thus there is a possibility that the capacitive coupling may be caused between the FIN gate 25 and the second wiring layer 71b and the third wiring layer 71c.

[0125] In this manner, in the fourth embodiment, since the first wiring layer 71a containing a large amount of p-type impurity ions is disposed between the FIN gate 25 disposed in the second substrate 20 and the second wiring layer 71b and the third wiring layer 71c containing a large amount of n-type impurity ions arranged in the interlayer 70, the capacitive coupling between the FIN gate 25 and the second wiring layer 71b and the third wiring layer 71c can be reduced.

[0126] (Fifth Embodiment) A fifth embodiment relates to a manufacturing process of the photodetection element 1 according to each of the first to fourth embodiments described above.

[0127] Figs. 20A to 20O are process-sectional views illustrating the manufacturing process of the photodetection element 1 according to the fifth embodiment and illustrate a manufacturing process following formation of the transfer transistors TR.

[0128] Fig. 20A is a sectional view of a process in which the transfer transistors TR is formed in the first substrate 10. An SiO2layer 75 is formed on an upper surface of the first substrate 10 by a high density plasma (HDP) method, and a front surface of the SiO2layer 75 is flattened by chemical vapor deposition (CMP) (Fig. 20B).

[0129] Next, an organic film 76 is formed on the SiO2layer 75, a resist layer 77 is disposed thereon, and the resist layer 77 is patterned by photolithography (Fig. 20C). The resist layer 77 is patterned according to a position of the contact 73.

[0130] Next, the organic film 76 is partially removed by dry etching to form a trench 78, and after the resist layer 77 and the organic film 76 are removed, the trench 78 is filled with polysilicon to form the contact 73, and a polysilicon layer 79 is also formed on the upper surface of the SiO2layer 75. Then, an SiO2layer 80 is formed thereon using tetra ethoxy silane (TEOS) (Fig. 20D).

[0131] Next, a mask pattern is disposed on an upper surface of the SiO2layer 80, and impurity ions are implanted into the contact 73 (Fig. 20E). At this stage, a heat treatment for activation of impurity ions is not performed.

[0132] Next, a SiN layer 81, a none-doped silicon glass (NSG) layer 82, an organic layer 83, and an SiO2layer 84 are sequentially formed, and a resist layer 85 is disposed thereon and patterned (Fig. 20F).

[0133] Next, the wiring layer 71 (first wiring layer 71a) made of polysilicon which is the first layer in the interlayer 70 is formed by photolithography and dry etching (Fig. 20G). Although only one wiring layer 71 is illustrated in Fig. 20G, the plurality of wiring layers 71 may be formed separately from each other in the first layer of the interlayer 70.

[0134] Next, an SiO2layer 86 is formed on the entire upper surface of the first substrate 10 by the HDP method, and a front surface of the SiO2layer 86 is flattened by CMP (Fig. 20H).

[0135] Next, an organic layer 87 and an SiO2layer 88 are formed on an upper surface of the SiO2layer 86, and a resist layer 89 is disposed thereon and patterned (Fig. 20I). The resist layer 89 is patterned according to positions of contacts connected to the first wiring layer 71a.

[0136] Next, the organic layer 87 and the SiO2layer 88 are partially removed by dry etching to form a trench, and after the resist layer 89 and the organic layer 87 are removed, the trench is filled with polysilicon to form the contact 73, and a polysilicon layer 91 is also formed on the upper surface of the SiO2layer 86. Then, an SiO2layer 92 is formed thereon using tetra ethoxy silane (TEOS) (Fig. 20J).

[0137] Next, a mask pattern is disposed on an upper surface of the SiO2layer 92, and impurity ions are implanted into the contact 73 (Fig. 20K).

[0138] Next, a heat treatment is performed to activate an implantation region of impurity ions (Fig. 20L). In this manner, by performing a heat treatment after the second process of implanting impurity ions is completed instead of performing the heat treatment every time impurity ions are implanted, the number of times of the heat treatment can be reduced, and damage to the substrate can be reduced.

[0139] Next, an NSG layer 93, an organic layer 94, and an SiO2layer 95 are sequentially formed on the SiO2layer 92, and a resist layer 96 is disposed and patterned on the SiO2layer 95 (Fig. 20M). The resist layer 96 is patterned according to the position of the wiring layers 71 (the second wiring layer 71b and the third wiring layer 71c) at the second layer in the interlayer 70.

[0140] Next, the wiring layers 71 (the second wiring layer 71b and the third wiring layer 71c) at the second layer in the interlayer 70 are formed by lithography and dry etching (Fig. 20N). The second wiring layer 71b and the third wiring layer 71c are polysilicon layers into which impurity ions are implanted.

[0141] Next, a side surface and an upper surface of the wiring layers 71 at the second layer in the interlayer 70 are covered with an SiO2layer 97 by the HDP method, and an upper surface of the SiO2layer 97 is protected with a SiN layer 98 (Fig. 20O).

[0142] When the impurity ions are implanted in the processes of Figs. 20E and 20K, a plurality of types of impurity ions may be implanted. For example, as described in an eighth embodiment to be described later, arsenic (As) and phosphorus (P) ions may be implanted into polysilicon. In addition, an impurity concentration may be changed for each wiring layer 71 (71a, 71b, or 71c).

[0143] In this manner, in the fifth embodiment, when the interlayer 70 is formed after the transfer transistor TR is formed in the first substrate 10, the process of performing the heat treatment is provided after the process of implanting impurity ions for forming the wiring layer 71 (71a) at the first layer and the process of implanting impurity ions for forming the wiring layers 71 (71b and 71c) at the second layer are completed, so that the impurity ions contained in the wiring layer 71 (71a) and the contact 73 (73a) at the first layer and the wiring layers 71 (71b and 71c) and the contacts 73 (73b and 73c) at the second layer can be activated collectively, and the manufacturing process can be simplified.

[0144] (Sixth Embodiment) The photodetection element 1 according to the sixth embodiment is characterized in that a charge retainer provided independently of the floating diffusion FD is formed in the interlayer 70.

[0145] Fig. 21A is a circuit diagram of a pixel circuit 22 included in a photodetection element 1 according to a sixth embodiment. As illustrated in Fig. 21A, a pixel 12 has a photodiode PD and a transfer transistor TR, and the pixel circuit 22 has a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, a conversion efficiency switching transistor FDG, a floating diffusion FD, and a charge retainer 15. One end of the charge retainer 15 is connected to the reset transistor RST and the conversion efficiency switching transistor FDG, and the other end of the charge retainer 15 is connected to, for example, a ground node.

[0146] Fig. 21B is a table illustrating a correspondence relationship between ON or OFF and conversion efficiency of the conversion efficiency switching transistor FDG. When the conversion efficiency switching transistor FDG is turned off, a state (HCG) in which the conversion efficiency is high is set, and when the conversion efficiency switching transistor FDG is turned on, a state (LCG) in which the conversion efficiency is low is set. The charge retainer 15 retains charge transferred from the photodiode PD when the conversion efficiency switching transistor FDG is turned on.

[0147] Fig. 22A is a planar layout view of the photodetection element 1 according to the sixth embodiment. Fig. 22B is a sectional view along line A-B in Fig. 22A in the substrate depth direction.

[0148] As illustrated in Fig. 22B, two wiring layers 71 are arranged at respective different layers in the interlayer 70. Hereinafter, these two wiring layers 71 are referred to as a first wiring layer 71a and a second wiring layer 71b. The first wiring layer 71a is connected to the p-well layer 42 of the first substrate 10. The p-well layer 42 is set to, for example, a ground potential. A penetration contact (third contact) 72c is connected to the second wiring layer 71b. The penetration contact 72c is connected to a source of the conversion efficiency switching transistor FDG via a wiring layer 20a and a contact 20b of the second substrate 20.

[0149] The first wiring layer 71a and the second wiring layer 71b are arranged in parallel to each other to vertically overlap each other in a plan view and function as both electrodes of the charge retainer (charge accumulator) 15. That is, the charge retainer 15 includes the first wiring layer 71a and the second wiring layer 71b and an insulating layer 46 between the first wiring layer 71a and the second wiring layer 71b.

[0150] In the interlayer 70, one or more wiring layers 71 other than the first wiring layer 71a and the second wiring layer 71b constituting the charge retainer 15 are arranged. For example, a wiring layer connected to the floating diffusion FD, a wiring layer connected to the transfer gate TG which are described in the first to fifth embodiments, and the like are provided.

[0151] Fig. 23A is a planar layout view of a photodetection element 100 according to a comparative example, and Fig. 23B is a sectional view along line A-B in Fig. 23A in the substrate depth direction. As illustrated in Fig. 23B, in the photodetection element 100 according to the comparative example, the wiring layers 71 arranged in the interlayer 70 are arranged at the same layer. Accordingly, it is difficult to form, in the interlayer 70, the charge retainer 15 as in the photodetection element 1 according to the sixth embodiment. In the photodetection element 100 according to the comparative example, for example, the charge retainer 15 is formed using a metal layer in the second substrate 20. Thus, it is necessary to secure a region for forming the charge retainer 15 in the second substrate 20, and an area for forming the pixel transistors is reduced. Hence, it is difficult to design a layout of the pixel circuit 22.

[0152] Fig. 24A is a planar layout view of a photodetection element 1 according to a modification example of the sixth embodiment, and Fig. 24B is a sectional view along line A-B in Fig. 24A in the substrate depth direction. In the photodetection element 1 according to the modification example, wiring layers 71b for the charge retainers 15 are formed in parallel to wiring layers 71 (third wiring layers 71c) connected to the transfer gates TG. The wiring layers 71b for the charge retainers 15 are arranged in, for example, a comb shape.

[0153] Figs. 25A and 25B are planar layout views of the comb-shaped wiring layers 71b, Fig. 25A illustrates an example in which each tooth of comb teeth extends in the second direction Y, and Fig. 25B illustrates an example in which each tooth of the comb teeth extends in the first direction X. In Figs. 25A and 25B, the comb-shaped wiring layers 71b for the charge retainers 15 are arranged to be combined with each other.

[0154] Fig. 26 is a planar layout view of one pixel circuit 22 of the photodetection element 1 according to the sixth embodiment. As illustrated in Fig. 26, the two wiring layers 71a and 71b constituting the charge retainer 15 overlap each other in a plan view. In the interlayer 70, in addition to the wiring layers 71a and 71b, a wiring layer (FD wiring layer) 71d that connects a source of the conversion efficiency switching transistor FDG and a gate of the amplification transistor AMP is provided.

[0155] A circuit configuration of the pixel circuit 22 of the photodetection element 1 according to the sixth embodiment is not limited to that illustrated in Fig. 21A, and various circuit configurations can be employed.

[0156] Fig. 27A is a circuit diagram of a pixel circuit 22 of a photodetection element 1 according to a first modification example of the sixth embodiment. In the pixel circuit 22 of Fig. 27A, unlike the pixel circuit 22 of Fig. 21A, the reset transistor RST and the conversion efficiency switching transistor FDG are connected in parallel.

[0157] Fig. 27B is a planar layout view of the pixel circuit 22 in Fig. 27A. As can be seen from a comparison between Fig. 27B and Fig. 26, the FD wiring layer 71d is provided at a different arrangement location. In addition, the penetration contact 72 that connects the second wiring layer 71b and the second substrate 20 is also provided at a different arrangement location.

[0158] Fig. 28A is a circuit diagram of a pixel circuit 22 of a photodetection element 1 according to a second modification example of the sixth embodiment. The pixel circuit 22 in Fig. 28A has two conversion efficiency switching transistors FDG (hereinafter, a first conversion efficiency switching transistor FDG1 and a second conversion efficiency switching transistor FDG2). More specifically, the reset transistor RST, the second conversion efficiency switching transistor FDG2, and the first conversion efficiency switching transistor FDG1 are connected in series between a power supply voltage node and the floating diffusion FD. A first charge retainer 15a is connected between a ground node and a connection node between the reset transistor RST and the second conversion efficiency switching transistor FDG2. A second charge retainer 15b is connected between a ground node and a connection node between the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2. The first charge retainer 15a is formed by two wiring layers 71 (71a and 71b) at respective different layers of the interlayer 70. The second charge retainer 15b is formed in, for example, a metal-insulator-metal (MIM) structure using a metal material on the second substrate 20.

[0159] Fig. 28B is a table illustrating a correspondence relationship between ON or OFF and the conversion efficiency of the conversion efficiency switching transistors FDG of the pixel circuit 22 according to the second modification example. When both the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 are turned off, the conversion efficiency is set to the highest level (HCG). When the first conversion efficiency switching transistor FDG1 is turned on and the second conversion efficiency switching transistor FDG2 is turned off, the conversion efficiency is set to a medium level (MCG). When both the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 are turned on, the conversion efficiency is set to the lowest level (LCG).

[0160] Fig. 28C is a planar layout view of the pixel circuit 22 according to the second modification example. As illustrated in Fig. 28C, a penetration contact 72 extending to the second substrate 20 is connected to the connection node between the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2, and the penetration contact 72 is connected to a metal layer in the second substrate 20. The second charge retainer 15b is formed using this metal layer.

[0161] Fig. 29A is a circuit diagram of a pixel circuit 22 of a photodetection element 1 according to a third modification example of the sixth embodiment. In the pixel circuit 22 according to the third modification example, as illustrated in Fig. 29A, the first conversion efficiency switching transistor FDG1, the first charge retainer 15a, the second conversion efficiency switching transistor FDG2, and the second charge retainer 15b are connected in series between a ground node and the floating diffusion FD connected to a source of the reset transistor RST. The first charge retainer 15a is disposed on the second substrate 20 by using, for example, a metal material. The second charge retainer 15b is formed by using, for example, two wiring layers 71 arranged at respective different layers of the interlayer 70.

[0162] Fig. 29B is a planar layout view of the pixel circuit 22 according to the third modification example. The wiring layer 71 (FD wiring layer 71d) that connects the floating diffusion FD and the amplification transistor AMP has an arrangement location different from that in Fig. 28C.

[0163] Fig. 30A is a circuit diagram of a pixel circuit 22 of a photodetection element 1 according to a fourth modification example of the sixth embodiment. The pixel circuit 22 according to the fourth modification example has a first reset transistor RST1, a second reset transistor RST2, a first conversion efficiency switching transistor FDG1, and a second conversion efficiency switching transistor FDG2. The first reset transistor RST1 and the first conversion efficiency switching transistor FDG1 are connected in series between the power supply voltage node and the floating diffusion FD. In addition, the second reset transistor RST2 and the second conversion efficiency switching transistor FDG2 are connected in series between the power supply voltage node and the floating diffusion FD. A first charge retainer 15a is connected between a ground node and a connection node between the first reset transistor RST1 and the first conversion efficiency switching transistor FDG1. A second charge retainer 15b is connected between a ground node and a connection node between the second reset transistor RST2 and the second conversion efficiency switching transistor FDG2. The first charge retainer 15a is disposed on the second substrate 20 by using, for example, a metal material. The second charge retainer 15b is formed by using, for example, two wiring layers 71 arranged at respective different layers of the interlayer 70.

[0164] Fig. 30B is a table illustrating a correspondence relationship between ON or OFF and the conversion efficiency of the conversion efficiency switching transistors FDG of the pixel circuit 22 according to the fourth modification example. When both the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 are turned off, the conversion efficiency is set to the highest level (HCG). When the first conversion efficiency switching transistor FDG1 is turned on and the second conversion efficiency switching transistor FDG2 is turned off, the conversion efficiency is set to a high level in a medium level (MHCG). When the first conversion efficiency switching transistor FDG1 is turned off and the second conversion efficiency switching transistor FDG2 is turned on, the conversion efficiency is set to a low level in the medium level (MLCG). When both the first conversion efficiency switching transistor FDG1 and the second conversion efficiency switching transistor FDG2 are turned on, the conversion efficiency is set to the lowest level (LCG).

[0165] Fig. 30C is a planar layout view of the pixel circuit 22 according to the fourth modification example. A contact connected to a connection node between the first reset transistor RST1 and the first conversion efficiency switching transistor FDG1 is connected to the second substrate 20 or the wiring layer 71 of the interlayer 70. The wiring layer 71 is formed of, for example, a metal material. A penetration contact 72 connected to a connection node between the second reset transistor RST2 and the second conversion efficiency switching transistor FDG2 is connected to the wiring layer 71 of the interlayer 70. The second charge retainer 15b is formed by two different wiring layers 71 (71a and 71b) of the interlayer 70.

[0166] Fig. 31A is a circuit diagram of a pixel circuit 22 of a photodetection element 1 according to a fifth modification example of the sixth embodiment. The pixel circuit 22 according to the fifth modification example has a first conversion efficiency switching transistor FDG1 and a first charge retainer 15a connected in series between a ground node and the floating diffusion FD connected to a source of a reset transistor RST, and a second conversion efficiency switching transistor FDG2 and a second charge retainer 15b connected in series between a ground node and the floating diffusion FD. The pixel circuit 22 according to the fifth modification example can switch the conversion efficiency in four stages, similarly to Fig. 30B.

[0167] Fig. 31B is a planar layout view of the pixel circuit 22 according to the fifth modification example. In the pixel circuit 22 according to the fifth modification example, a contact connected to the source of the first conversion efficiency switching transistor FDG1 is connected to the second substrate 20 or the wiring layer 71 of the interlayer 70. The wiring layer 71 is made of a metal material, and the first charge retainer 15a is formed. A penetration contact 72 connected to the source of the second conversion efficiency switching transistor FDG2 is connected to the wiring layer 71 of the interlayer 70. The second charge retainer 15b is formed by the two wiring layers 71 arranged at respective different layers of the interlayer 70.

[0168] Figs. 32 and 33 are sectional views of a pixel circuit 22 of a photodetection element 1 according to a sixth modification example. The pixel circuit 22 according to the sixth modification example has the same circuit configuration as the pixel circuit 22 according to the fourth modification example or the fifth modification example. Fig. 32 illustrates an example in which the first charge retainer 15a is disposed on the second substrate 20. A contact extending upward from the source of the first conversion efficiency switching transistor FDG1 is connected to a metal wiring of the second substrate 20. For example, the first charge retainer 15a having the MIM structure is formed using the metal wiring. In Fig. 32, the second charge retainer 15b is formed by the two wiring layers 71a and 71b of the interlayer 70.

[0169] A cross-sectional structure of the pixel circuit 22 according to the fourth modification example or the fifth modification example is not limited to that illustrated in Fig. 32. Fig. 33 differs from Fig. 32 in the cross-sectional structure of the second charge retainer 15b formed in the interlayer 70. In Fig. 33, three wiring layers 71a, 71b, and 71c are arranged at respective different layers in the interlayer 70, and the two wiring layers 71b and 71c from the top are connected by a contact. By forming the second charge retainer 15b having a three-layer structure as illustrated in Fig. 33, the amount of charge that can be accumulated in the second charge retainer 15b can be increased.

[0170] Fig. 34 is a table listing features of the pixel circuits 22 according to the first to sixth modification examples of the sixth embodiment. The features of the pixel circuits 22 according to the first to sixth modification examples can be listed as the number of wiring layers 71 in the interlayer 70, a connection form between the conversion efficiency switching transistor FDG and the reset transistor RST, the number of conversion efficiency switching transistors FDG, whether or not the charge retainer 15 is disposed on the second substrate 20, and the number of conversion switching stages.

[0171] In Fig. 34, Pattern 1 corresponds to Fig. 21A, Pattern 2 corresponds to Fig. 27A, Pattern 3 corresponds to Fig. 28A, Pattern 4 corresponds to Fig. 30A, Pattern 5 corresponds to Fig. 29A, and Pattern 6 corresponds to Fig. 31A. Pattern 7 is a seventh modification example different from the first to sixth modification examples, and an example in which N (N is any integer of 2 or more) wiring layers 71 are arranged at respective different layers in the interlayer 70. In a photodetection element 1 according to the seventh modification example, the conversion efficiency transistor and the reset transistor RST can be connected in series or in parallel, the total number of conversion efficiency transistors can be any number of 1 or more, the charge retainer 15 can be disposed on the second substrate 20, and the number of the conversion efficiency switching stages can also be any number.

[0172] In this manner, in the sixth embodiment, the charge retainer 15 for switching the conversion efficiency can be formed by using, as electrodes, the two wiring layers 71 arranged at respective different layers of the interlayer 70. The two wiring layers 71 constituting the charge retainer 15 can be provided independently of the first to third wiring layers 71a, 71b, and 71c in the first to fifth embodiments described above. Accordingly, the charge retainer 15 according to the sixth embodiment can be provided in the photodetection element 1 according to the first to fifth embodiments described above.

[0173] (Seventh Embodiment) Fig. 35 is a sectional view illustrating a problem in a case where a second substrate 20 in which pixel transistors are arranged is stacked on a first substrate 10 in which photoelectric conversion elements (photodiodes) PD are arranged.

[0174] In the case where the second substrate 20 in which the pixel transistors are arranged is stacked on the first substrate 10 in which the photodiodes PD are arranged, there is a possibility that light emitted from the second substrate 20 will enter the photodiodes PD of the first substrate 10 due to a defect of the pixel transistors or the like (arrow line y1 in Fig. 35). In addition, there is a possibility that light having passed through the photodiode PD will be reflected from the second substrate 20, will enter a photodiode PD of an adjacent pixel 12 of the first substrate 10, and will result in color mixing (arrow line y2 in Fig. 35). The photodetection element 1 according to the seventh embodiment is characterized by preventing the above-described defect.

[0175] Fig. 36 is a sectional view of the photodetection element 1 according to the seventh embodiment in the substrate depth direction. Similarly to the first to sixth embodiments, the photodetection element 1 according to the seventh embodiment is characterized by including a plurality of wiring layers 71 (71a and 71b) at respective different layers in an interlayer 70 (interlayer insulating layer) between a first substrate 10 and a second substrate 20. The plurality of wiring layers 71 is formed of, for example, polysilicon.

[0176] Fig. 36 illustrates an example in which the two wiring layers 71 (a first wiring layer 71a and a second wiring layer 71b) are arranged in the interlayer 70. The first wiring layer 71a and the second wiring layer 71b are arranged at respective different layers of the interlayer 70. The first wiring layer 71a is disposed on a side closer to the first substrate 10 than to the second wiring layer 71b. The second wiring layer 71b is disposed on a side closer to the second substrate 20 than to the first wiring layer 71a.

[0177] The first wiring layer 71a is connected to, for example, the floating diffusion FD of the first substrate 10 via the contact 73a. Note that a plurality of wiring layers 71 can be arranged at the same layer as the first wiring layer 71a. More specifically, the plurality of wiring layers 71 includes a wiring layer 71 connected to the transfer gate TG, a wiring layer 71 connected to the p-well layer 42, or the like.

[0178] A first penetration contact 72a extending to the second substrate 20 is connected to the first wiring layer 71a. The first penetration contact 72a is connected to a wiring layer 16 of the second substrate 20. The wiring layer 16 is connected to the pixel transistor 18 via another contact 17. In this manner, the first wiring layer 71a is electrically connected to the pixel transistor 18 of the second substrate 20.

[0179] The second wiring layer (light-shielding layer) 71b is an optical shield layer. The second wiring layer 71b may be formed in a solid pattern that covers most of the first substrate 10, a mesh-shaped pattern, a slit-shaped pattern, or a pattern having another shape. In a case where the second wiring layer 71b is formed in a solid pattern, an opening portion 71h is provided around the first penetration contact 72a extending from the first wiring layer 71a to the second substrate 20. A second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b. The second wiring layer 71b is set to a predetermined potential (for example, ground potential) via the second contact 72b. The second wiring layer 71b functioning as an optical shield layer may be larger than an area of a wiring layer (for example, the first wiring layer 71a) disposed at a layer other than the second wiring layer 71b.

[0180] By providing the second wiring layer 71b functioning as the optical shield layer, light having passed through the photodiode PD of the first substrate 10 can be blocked by the second wiring layer 71b, and light having passed through the photodiode PD does not enter the second substrate 20. In addition, even if the pixel transistor 18 of the second substrate 20 emits light due to some defect, the light can be blocked by the second wiring layer 71b, and the light from the second substrate 20 does not enter the photodiode PD.

[0181] The second wiring layer 71b functioning as the optical shield layer is provided independently of the plurality of wiring layers 71 arranged in the interlayer 70 described in the first to sixth embodiments. Accordingly, the optical shield layer according to the seventh embodiment can be provided in the photodetection element 1 according to the first to sixth embodiments.

[0182] Various variations are conceivable in the number and a shape of the optical shield layers (second wiring layers) 71b disposed in the interlayer 70. Hereinafter, the number and the shape of representative optical shield layers (second wiring layers) 71b will be described in order, but the number and the shape of the optical shield layers are not limited to the following description.

[0183] Figs. 37A to 37D are views illustrating a photodetection element 1 according to a first modification example of the seventh embodiment. Fig. 37A is a plan view of an optical shield layer (second wiring layer) 71b, Fig. 37B is a sectional view along line A-B in Fig. 37A in the substrate depth direction, Fig. 37C is a sectional view along line C-D in Fig. 37A in the substrate depth direction, and Fig. 37D is a plan view of a combination of the optical shield layer and a first wiring layer 71a.

[0184] Figs. 37A to 37D illustrate a cross-sectional structure in a case where one floating diffusion FD and pixel transistors 18 are shared by a plurality of pixels 12 (for example, four pixels 12).

[0185] In an interlayer 70, for example, the second wiring layer 71b functioning as the optical shield layer is stacked on the first wiring layer 71a connected to the floating diffusion FD. As illustrated in Fig. 37A, the second wiring layer 71b is formed in a solid pattern, and an opening portion 71h is provided in a part thereof. In the opening portion 71h, a first contact 72a extending from the first wiring layer 71a to the second substrate 20 is disposed.

[0186] A second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b. The second wiring layer 71b is set to a predetermined potential (for example, ground potential) via the second contact 72b. When the second contact 72b is provided for each second wiring layer 71b, the number of second contacts 72b increases. Hence, as described later, the number of the second contacts 72b may be reduced by conducting the plurality of second wiring layers 71b in the interlayer 70 and providing one or a plurality of second contacts 72b at any location.

[0187] As illustrated in Fig. 37D, the first wiring layer 71a is disposed immediately below the opening portion 71h of the second wiring layer 71b. The first wiring layer 71a is connected to, for example, the floating diffusion FD. Note that the first wiring layer 71a may be connected to the transfer gate TG, the p-well layer 42, or the like.

[0188] By disposing the first wiring layer 71a immediately below the second wiring layer 71b, for example, even if light from the second substrate 20 passes through the opening portion 71h of the second wiring layer 71b, the light can be blocked by the first wiring layer 71a. In addition, light having passed through the photodiode PD of the first substrate 10 is blocked by the first wiring layer 71a, and it is difficult for the light to pass through the opening portion 71h of the second wiring layer 71b.

[0189] In this manner, by disposing the first wiring layer 71a immediately below the opening portion 71h of the second wiring layer 71b, the light shielding effect can be improved.

[0190] Note that an area of the first wiring layer 71a and an area of the second wiring layer 71b do not need to be equal to each other. For example, the first wiring layer 71a may be divided into a plurality of wiring layers 71.

[0191] Figs. 38A to 38D are views illustrating a photodetection element 1 according to a second modification example of the seventh embodiment. Fig. 38A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 38B is a sectional view along line A-B in Fig. 38A in the substrate depth direction, Fig. 38C is a sectional view along line C-D in Fig. 38A in the substrate depth direction, and Fig. 38D is an external view of some of chips 21 of the photodetection element 1.

[0192] In the photodetection element 1 according to the second modification example, the second contact 72b is not connected to each second wiring layer 71b functioning as the optical shield layer, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1, and these contacts 21c are connected to the plurality of second wiring layers 71b such that the second wiring layers 71b are set to a predetermined potential (for example, a ground potential). The plurality of contacts 21c is preferably arranged at as equal intervals as possible in the circumferential edge portion of the chip 21, but the number of the plurality of contacts 21c does not need to be the same as the number of the plurality of second wiring layers 71b. Typically, a smaller number of contacts 21c than the number of the plurality of second wiring layers 71b are provided. Therefore, the number of contacts 21c can be reduced.

[0193] In the photodetection element 1 according to the second modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0194] In the first modification example and the second modification example, the second wiring layer 71b is formed in a solid pattern. When the second wiring layer 71b is formed in the solid pattern, a capacitance is formed between the first wiring layer 71a and the second wiring layer 71b and may result in a problem such as a decrease in photoelectric conversion efficiency.

[0195] Figs. 39A to 39C are views illustrating a photodetection element 1 according to a third modification example of the seventh embodiment. Fig. 39A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 39B is a sectional view along line A-B in Fig. 39A in the substrate depth direction, and Fig. 39C is a sectional view along line C-D in Fig. 39A in the substrate depth direction.

[0196] In an interlayer 70 in the photodetection element 1 according to the third modification example, for example, the second wiring layer 71b functioning as the optical shield layer is stacked on a first wiring layer 71a connected to the floating diffusion FD. The second wiring layer 71b has a mesh-shaped pattern. An opening portion 71h through which a first contact 72a extending from the first wiring layer 71a to the second substrate 20 passes is provided in a part of the mesh-shaped pattern. A size of the opening portion 71h is larger than that of a hole portion of the mesh-shaped pattern. By forming the second wiring layer 71b in the mesh-shaped pattern, the capacitance between the first wiring layer 71a and the second wiring layer 71b can more decrease as compared with the case where the second wiring layer 71b is formed in the solid pattern, and a reduction in photoelectric conversion efficiency can be decreased.

[0197] Figs. 40A to 40D are views illustrating a photodetection element 1 according to a fourth modification example of the seventh embodiment. Fig. 40A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 40B is a sectional view along line A-B in Fig. 40A in the substrate depth direction, Fig. 40C is a sectional view along line C-D in Fig. 40A in the substrate depth direction, and Fig. 40D is an external view of some of chips 21 of the photodetection element 1.

[0198] In the photodetection element 1 according to the fourth modification example, the second wiring layer 71b is formed in a mesh pattern shape. In addition, similarly to the photodetection element 1 according to the second modification example, the second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0199] In the photodetection element 1 according to the fourth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0200] Figs. 41A to 41C are views illustrating a photodetection element 1 according to a fifth modification example of the seventh embodiment. Fig. 41A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 41B is a sectional view along line A-B in Fig. 41A in the substrate depth direction, and Fig. 41C is a sectional view along line C-D in Fig. 41A in the substrate depth direction.

[0201] In an interlayer 70 in the photodetection element 1 according to the fifth modification example, for example, the second wiring layer 71b functioning as the optical shield layer is stacked on a first wiring layer 71a connected to the floating diffusion FD. The second wiring layer 71b has a slit pattern shape extending in one direction. An opening portion 71h through which a first contact 72a extending from the first wiring layer 71a to the second substrate 20 passes is provided in a part of the slit-shaped pattern. By forming the second wiring layer 71b in the slit-shaped pattern, the capacitance can more decrease as compared with the case where the second wiring layer 71b is formed in the solid pattern or the mesh shape, and a reduction in photoelectric conversion efficiency can be decreased.

[0202] Figs. 42A to 42D are views illustrating a photodetection element 1 according to a sixth modification example of the seventh embodiment. Fig. 42A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 42B is a sectional view along line A-B in Fig. 42A in the substrate depth direction, Fig. 42C is a sectional view along line C-D in Fig. 42A in the substrate depth direction, and Fig. 42D is an external view of some of chips 21 of the photodetection element 1.

[0203] In the photodetection element 1 according to the sixth modification example, the second wiring layer 71b is formed in a slit pattern shape. In addition, similarly to the photodetection element 1 according to the second modification example, the second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0204] In the photodetection element 1 according to the sixth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0205] Figs. 43A to 43C are views illustrating a photodetection element 1 according to a seventh modification example of the seventh embodiment. Fig. 43A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 43B is a sectional view along line A-B in Fig. 43A in the substrate depth direction, and Fig. 43C is a sectional view along line C-D in Fig. 43A in the substrate depth direction.

[0206] In an interlayer 70 in the photodetection element 1 according to the seventh modification example, for example, the second wiring layer 71b functioning as the optical shield layer is stacked on a first wiring layer 71a connected to the floating diffusion FD. The second wiring layer 71b has a slit pattern shape extending in a direction different from that of the second wiring layer 71b according to the fifth modification example by 90 degrees. An opening portion 71h through which a first contact 72a extending from the first wiring layer 71a to the second substrate 20 passes is provided in a part of the slit-shaped pattern. By forming the second wiring layer 71b in the slit-shaped pattern, the capacitance can more decrease as compared with the case where the second wiring layer 71b is formed in the solid pattern or the mesh shape.

[0207] Figs. 44A to 44D are views illustrating a photodetection element 1 according to an eighth modification example of the seventh embodiment. Fig. 44A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 44B is a sectional view along line A-B in Fig. 44A in the substrate depth direction, Fig. 44C is a sectional view along line C-D in Fig. 44A in the substrate depth direction, and Fig. 44D is an external view of some of chips 21 of the photodetection element 1.

[0208] In the photodetection element 1 according to the eighth modification example, the second wiring layer 71b is formed in a slit pattern shape extending in a direction different from that of the photodetection element 1 according to the sixth modification example by 90 degrees. In addition, similarly to the photodetection element 1 according to the second modification example, the second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0209] In the photodetection element 1 according to the eighth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0210] Figs. 45A to 45C are views illustrating a photodetection element 1 according to a ninth modification example of the seventh embodiment. Fig. 45A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 45B is a sectional view along line A-B in Fig. 45A in the substrate depth direction, and Fig. 45C is a sectional view along line C-D in Fig. 45A in the substrate depth direction.

[0211] In an interlayer 70 in the photodetection element 1 according to the ninth modification example, for example, the second wiring layer 71b and a third wiring layer 71c functioning as the optical shield layer are stacked on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the ninth modification example has a stacked structure of the second wiring layer 71b and the third wiring layer 71c.

[0212] Both the second wiring layer 71b and the third wiring layer 71c are formed in a solid pattern, and an opening portion 71h is formed at an overlapping location thereof in a plan view. In the opening portion 71h, a first contact 72a extending from the first wiring layer 71a to the second substrate 20 is disposed. In addition, a second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b and the third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are set to a predetermined potential (for example, a ground potential) via the second contact 72b.

[0213] In this manner, the optical shield layer is formed to have the stacked structure of the second wiring layer 71b and the third wiring layer 71c, and thereby it is possible to further improve a shielding effect of light having passed through the photodiode PD and light from the second substrate 20. However, by providing the second wiring layer 71b and the third wiring layer 71c, there is a possibility that a larger capacitance will be applied.

[0214] Figs. 46A to 46D are views illustrating a photodetection element 1 according to a tenth modification example of the seventh embodiment. Fig. 46A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 46B is a sectional view along line A-B in Fig. 46A in the substrate depth direction, Fig. 46C is a sectional view along line C-D in Fig. 46A in the substrate depth direction, and Fig. 46D is an external view of some of chips 21 of the photodetection element 1.

[0215] In the photodetection element 1 according to the tenth modification example, similarly to the ninth modification example, the optical shield layer provided in the interlayer 70 has a stacked structure of the second wiring layer 71b and a third wiring layer 71c.

[0216] In addition, in the photodetection element 1 according to the tenth modification example, a second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0217] In the photodetection element 1 according to the tenth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0218] Figs. 47A to 47C are views illustrating a photodetection element 1 according to an eleventh modification example of the seventh embodiment. Fig. 47A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 47B is a sectional view along line A-B in Fig. 47A in the substrate depth direction, and Fig. 47C is a sectional view along line C-D in Fig. 47A in the substrate depth direction.

[0219] In an interlayer 70 in the photodetection element 1 according to the eleventh modification example, for example, the second wiring layer 71b and a third wiring layer 71c functioning as the optical shield layer are stacked on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the eleventh modification example has a stacked structure of the second wiring layer 71b and the third wiring layer 71c.

[0220] Both the second wiring layer 71b and the third wiring layer 71c are formed in a mesh-shaped pattern, and an opening portion 71h is formed at an overlapping location thereof in a plan view. In the opening portion 71h, a first contact 72a extending from the first wiring layer 71a to the second substrate 20 is disposed. In addition, a second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b and the third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are set to a predetermined potential (for example, a ground potential) via the second contact 72b.

[0221] In this manner, the optical shield layer is formed to have the stacked structure of the second wiring layer 71b and the third wiring layer 71c, and thereby it is possible to further improve a shielding effect of light having passed through the photodiode PD and light from the second substrate 20. In addition, by forming the second wiring layer 71b and the third wiring layer 71c in the mesh-shaped pattern, the capacitance can more decrease than that in a solid pattern.

[0222] Figs. 48A to 48D are views illustrating a photodetection element 1 according to a twelfth modification example of the seventh embodiment. Fig. 48A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 48B is a sectional view along line A-B in Fig. 48A in the substrate depth direction, Fig. 48C is a sectional view along line C-D in Fig. 48A in the substrate depth direction, and Fig. 48D is an external view of some of chips 21 of the photodetection element 1.

[0223] In the photodetection element 1 according to the twelfth modification example, similarly to the eleventh modification example, the optical shield layer provided in the interlayer 70 has a stacked structure of the second wiring layer 71b and a third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are formed in a mesh-shaped pattern.

[0224] In addition, in the photodetection element 1 according to the twelfth modification example, a second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0225] In the photodetection element 1 according to the twelfth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0226] Figs. 49A to 49C are views illustrating a photodetection element 1 according to a thirteenth modification example of the seventh embodiment. Fig. 49A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 49B is a sectional view along line A-B in Fig. 49A in the substrate depth direction, and Fig. 49C is a sectional view along line C-D in Fig. 49A in the substrate depth direction.

[0227] In an interlayer 70 in the photodetection element 1 according to the thirteenth modification example, for example, the second wiring layer 71b and a third wiring layer 71c functioning as the optical shield layer are stacked on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the thirteenth modification example has a stacked structure of the second wiring layer 71b and the third wiring layer 71c.

[0228] Both the second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern, and an opening portion 71h is formed at an overlapping location thereof in a plan view. In the opening portion 71h, a first contact 72a extending from the first wiring layer 71a to the second substrate 20 is disposed. In addition, a second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b and the third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are set to a predetermined potential (for example, a ground potential) via the second contact 72b.

[0229] In this manner, the optical shield layer is formed to have the stacked structure of the second wiring layer 71b and the third wiring layer 71c, and thereby it is possible to further improve a shielding effect of light having passed through the photodiode PD and light from the second substrate 20. In addition, by forming the second wiring layer 71b and the third wiring layer 71c in a slit-shaped pattern, the capacitance can more decrease than that in a solid pattern or a mesh-shaped pattern.

[0230] Figs. 50A to 50D are views illustrating a photodetection element 1 according to a fourteenth modification example of the seventh embodiment. Fig. 50A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 50B is a sectional view along line A-B in Fig. 50A in the substrate depth direction, Fig. 50C is a sectional view along line C-D in Fig. 50A in the substrate depth direction, and Fig. 50D is an external view of some of chips 21 of the photodetection element 1.

[0231] In the photodetection element 1 according to the fourteenth modification example, similarly to the thirteenth modification example, the optical shield layer provided in the interlayer 70 has a stacked structure of the second wiring layer 71b and a third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern.

[0232] In addition, in the photodetection element 1 according to the fourteenth modification example, a second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0233] In the photodetection element 1 according to the fourteenth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0234] Figs. 51A to 51C are views illustrating a photodetection element 1 according to a fifteenth modification example of the seventh embodiment. Fig. 51A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 51B is a sectional view along line A-B in Fig. 51A in the substrate depth direction, and Fig. 51C is a sectional view along line C-D in Fig. 51A in the substrate depth direction.

[0235] In an interlayer 70 in the photodetection element 1 according to the fifteenth modification example, for example, the second wiring layer 71b and a third wiring layer 71c functioning as the optical shield layer are stacked on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the fifteenth modification example has a stacked structure of the second wiring layer 71b and the third wiring layer 71c.

[0236] Both the second wiring layer 71b and the third wiring layer 71c according to the fifteenth modification example are formed in a slit-shaped pattern extending in a direction different from that of the second wiring layer 71b and the third wiring layer 71c according to the thirteenth modification example by 90 degrees, and an opening portion 71h is formed at an overlapping location thereof in a plan view. In the opening portion 71h, a first contact 72a extending from the first wiring layer 71a to the second substrate 20 is disposed. In addition, a second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b and the third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are set to a predetermined potential (for example, a ground potential) via the second contact 72b.

[0237] In this manner, the optical shield layer is formed to have the stacked structure of the second wiring layer 71b and the third wiring layer 71c, and thereby it is possible to further improve a shielding effect of light having passed through the photodiode PD and light from the second substrate 20. In addition, by forming the second wiring layer 71b and the third wiring layer 71c in a slit-shaped pattern, the capacitance can more decrease than that in a solid pattern or a mesh-shaped pattern.

[0238] Figs. 52A to 52D are views illustrating a photodetection element 1 according to a sixteenth modification example of the seventh embodiment. Fig. 52A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 52B is a sectional view along line A-B in Fig. 52A in the substrate depth direction, Fig. 52C is a sectional view along line C-D in Fig. 52A in the substrate depth direction, and Fig. 52D is an external view of some of chips 21 of the photodetection element 1.

[0239] In the photodetection element 1 according to the sixteenth modification example, similarly to the fifteenth modification example, the optical shield layer provided in the interlayer 70 has a stacked structure of the second wiring layer 71b and a third wiring layer 71c. Both the second wiring layer 71b and the third wiring layer 71c according to the sixteenth modification example are formed in a slit-shaped pattern extending in a direction different from that of the second wiring layer 71b and the third wiring layer 71c according to the fourteenth modification example by 90 degrees.

[0240] In addition, in the photodetection element 1 according to the sixteenth modification example, a second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0241] In the photodetection element 1 according to the sixteenth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0242] Figs. 53A to 53C are views illustrating a photodetection element 1 according to a seventeenth modification example of the seventh embodiment. Fig. 53A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 53B is a sectional view along line A-B in Fig. 53A in the substrate depth direction, and Fig. 53C is a sectional view along line C-D in Fig. 53A in the substrate depth direction.

[0243] In an interlayer 70 in the photodetection element 1 according to the seventeenth modification example, for example, the second wiring layer 71b and a third wiring layer 71c functioning as the optical shield layer are stacked on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the seventeenth modification example has a stacked structure of the second wiring layer 71b and the third wiring layer 71c.

[0244] Both the second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern and are arranged to be shifted from each other in a transverse direction. Therefore, a region where neither the second wiring layer 71b nor the third wiring layer 71c is present in a plan view can be made as small as possible, and light leaking from a gap between the second wiring layer 71b and the third wiring layer 71c is reduced as much as possible. An opening portion 71h is formed in a part of the second wiring layer 71b and the third wiring layer 71c. In the opening portion 71h, a first contact 72a extending from the first wiring layer 71a to the second substrate 20 is disposed. In addition, a second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b and the third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are set to a predetermined potential (for example, a ground potential) via the second contact 72b.

[0245] In this manner, in the seventeenth modification example, since the second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern, the capacitance can decrease. In addition, since the second wiring layer 71b and the third wiring layer 71c are arranged to be shifted in the transverse direction, the amount of light leaking from the gap between the second wiring layer 71b and the third wiring layer 71c can be reduced.

[0246] Figs. 54A to 54D are views illustrating a photodetection element 1 according to an eighteenth modification example of the seventh embodiment. Fig. 54A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 54B is a sectional view along line A-B in Fig. 54A in the substrate depth direction, Fig. 54C is a sectional view along line C-D in Fig. 54A in the substrate depth direction, and Fig. 54D is an external view of some of chips 21 of the photodetection element 1.

[0247] In the photodetection element 1 according to the eighteenth modification example, similarly to the seventeenth modification example, the optical shield layer provided in the interlayer 70 has a stacked structure of the second wiring layer 71b and a third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern and are arranged to be shifted from each other in a transverse direction.

[0248] In addition, in the photodetection element 1 according to the eighteenth modification example, a second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0249] In the photodetection element 1 according to the eighteenth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0250] Figs. 55A to 55C are views illustrating a photodetection element 1 according to a nineteenth modification example of the seventh embodiment. Fig. 55A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 55B is a sectional view along line A-B in Fig. 55A in the substrate depth direction, and Fig. 55C is a sectional view along line C-D in Fig. 55A in the substrate depth direction.

[0251] In an interlayer 70 in the photodetection element 1 according to the nineteenth modification example, for example, the second wiring layer 71b and a third wiring layer 71c functioning as the optical shield layer are stacked on a first wiring layer 71a connected to the floating diffusion FD. In this manner, the optical shield layer according to the nineteenth modification example has a stacked structure of the second wiring layer 71b and the third wiring layer 71c.

[0252] Both the second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern and are arranged to be shifted from each other in a transverse direction. Both the second wiring layer 71b and the third wiring layer 71c according to the nineteenth modification example extend in a direction different from that of the second wiring layer 71b and the third wiring layer 71c according to the seventeenth modification example by 90 degrees.

[0253] According to the nineteenth modification example, a region where neither the second wiring layer 71b nor the third wiring layer 71c is present in a plan view can be made as small as possible, and light leaking from a gap between the second wiring layer 71b and the third wiring layer 71c is reduced as much as possible. An opening portion 71h is formed in a part of the second wiring layer 71b and the third wiring layer 71c. In the opening portion 71h, a first contact 72a extending from the first wiring layer 71a to the second substrate 20 is disposed. In addition, a second contact 72b extending to the second substrate 20 is connected to the second wiring layer 71b and the third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are set to a predetermined potential (for example, a ground potential) via the second contact 72b.

[0254] In this manner, in the nineteenth modification example, since the second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern, the capacitance can decrease. In addition, since the second wiring layer 71b and the third wiring layer 71c are arranged to be shifted in the transverse direction, the amount of light leaking from the gap between the second wiring layer 71b and the third wiring layer 71c can be reduced.

[0255] Figs. 56A to 56D are views illustrating a photodetection element 1 according to a twentieth modification example of the seventh embodiment. Fig. 56A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 56B is a sectional view along line A-B in Fig. 56A in the substrate depth direction, Fig. 56C is a sectional view along line C-D in Fig. 56A in the substrate depth direction, and Fig. 56D is an external view of some of chips 21 of the photodetection element 1.

[0256] In the photodetection element 1 according to the twentieth modification example, similarly to the nineteenth modification example, the optical shield layer provided in the interlayer 70 has a stacked structure of the second wiring layer 71b and a third wiring layer 71c. The second wiring layer 71b and the third wiring layer 71c are formed in a slit-shaped pattern and are arranged to be shifted from each other in a transverse direction. Both the second wiring layer 71b and the third wiring layer 71c according to the twentieth modification example extend in a direction different from that of the second wiring layer 71b and the third wiring layer 71c according to the eighteenth modification example by 90 degrees.

[0257] In addition, in the photodetection element 1 according to the twentieth modification example, a second contact 72b is not connected to each second wiring layer 71b, but a plurality of contacts 21c is provided at predetermined intervals in a circumferential edge portion of the chips 21 of the photodetection element 1 such that the plurality of second wiring layers 71b is set to a predetermined potential (for example, a ground potential).

[0258] In the photodetection element 1 according to the twentieth modification example, since there is no need to provide the second contact 72b for each second wiring layer 71b, the number of second contacts 72b arranged in the second substrate 20 can be reduced, and an empty region of the second substrate 20 can be increased.

[0259] Figs. 57A to 57D are views illustrating a photodetection element 1 according to a twenty-first modification example of the seventh embodiment. Fig. 57A is a plan view of an optical shield layer (second wiring layer 71b), Fig. 57B is a sectional view along line A-B in Fig. 57A in the substrate depth direction, Fig. 57C is a sectional view along line C-D in Fig. 57A in the substrate depth direction, and Fig. 57D is a sectional view along line E-F in the substrate depth direction.

[0260] The photodetection element 1 according to the twenty-first modification example includes a first wiring layer 71a and the second wiring layer 71b in the interlayer 70. The first wiring layer 71a is connected to the floating diffusion FD, and the second wiring layer 71b functions as the optical shield layer.

[0261] The second wiring layer 71b is formed in a solid pattern, but is cut out along an outline of the first wiring layer 71a. In a plan view from above the interlayer 70, as illustrated in Fig. 57A, the first wiring layer 71a and the second wiring layer 71b are arranged without overlapping and without a gap in a plan view.

[0262] According to the twenty-first modification example, the light having passed through the photodiode PD can be blocked by the first wiring layer 71a or the second wiring layer 71b, and the light from the second substrate 20 can be blocked by the first wiring layer 71a or the second wiring layer 71b. Therefore, color mixing and the like due to leakage light can be prevented.

[0263] Fig. 58 is a table listing various modification examples of the seventh embodiment described above. In Fig. 58, Pattern A-1 corresponds to Figs. 37A to 37D, Pattern A-2 corresponds to Figs. 39A to 39C, Pattern A-3 corresponds to Figs. 41A to 41C, and Pattern A-4 corresponds to Figs. 43A to 43C. In addition, Pattern B-1 corresponds to Figs. 45A to 45C, Pattern B-2 corresponds to Figs. 47A to 47C, Pattern B-3 corresponds to Figs. 49A to 49C, Pattern B-4 corresponds to Figs. 51A to 51C, Pattern B-5 corresponds to Figs. 53A to 53C, and Pattern B-6 corresponds to Figs. 55A to 55C. Pattern A-1-T corresponds to Figs. 38A to 38D, Pattern A-2-T corresponds to Figs. 40A to 40D, Pattern A-3-T corresponds to Figs. 42A to 42D, and Pattern A-4-T corresponds to Figs. 44A to 44D. Pattern B-1-T corresponds to Figs. 46A to 46D, Pattern B-2-T corresponds to Figs. 48A to 48D, Pattern B-3-T corresponds to Figs. 50A to 50D, Pattern B-4-T corresponds to Figs. 52A to 52D, Pattern B-5-T corresponds to Figs. 54A to 54D, Pattern B-6-T corresponds to Figs. 56A to 56D, and Pattern AF-1 corresponds to Figs. 57A to 57D.

[0264] The wiring layers 71 made of polysilicon in the interlayer 70 includes one or a plurality of optical shield layers in addition to the wiring layer 71 connected to the floating diffusion FD or the like. The shapes of the optical shield layers include a solid pattern, a mesh-shaped pattern, and a slit-shaped (linear) pattern. A connection portion between the optical shield layer and a contact is provided in a sharing unit of the pixels 12 or an end of the chip 21.

[0265] In this manner, in the seventh embodiment, since the wiring layer 71a and the optical shield layer 71b are arranged at respective different layers of the interlayer 70, the light having passed through the photodiode PD and the light emitted from the second substrate 20 for some reason can be blocked by the optical shield layer 71b, and deterioration in image quality due to color mixing or noise light can be prevented. In addition, by designing shapes of the optical shield layer 71b, an increase in capacitance due to the provision of the optical shield layer 71b can be reduced, and deterioration of photoelectric conversion efficiency can be reduced. Further, by forming the optical shield layer 71b and the wiring layer 71a in a shape other than the solid pattern and arranging the optical shield layer 71b and the wiring layer 71a to be shifted from each other, redundant light can be blocked, capacitance can decrease, and deterioration of the photoelectric conversion efficiency can be reduced.

[0266] (Eighth Embodiment) A photodetection element 1 according to an eighth embodiment is characterized in that, in a case where a wiring layer 71 is made of polysilicon, at least part of the polysilicon contains arsenic (As) and phosphorus (P).

[0267] Fig. 59A is a graph illustrating comparison of sheet resistance between arsenic (As) ions and phosphorus (P) ions, and Fig. 59B is a graph illustrating comparison between diffusion lengths in silicon doped with arsenic (As) ions and phosphorus (P) ions.

[0268] As can be seen from Figs. 59A and 59B, when phosphorus (P) ions are implanted into polysilicon, the resistance of polysilicon decreases. Accordingly, for example, deterioration of noise characteristics due to an increase in the gate resistance of the amplification transistor AMP can be reduced.

[0269] On the other hand, when arsenic (As) ions are implanted into polysilicon, arsenic (As) is unlikely to be diffused in polysilicon, so that a defect due to diffusion does not occur. Accordingly, for example, impurities in the wiring layers 71 connected to the FD side diffuse to the vicinity of the transfer gate TG, and it is possible to reduce generation of a false signal due to an increase in magnitude of the electric field in the vicinity of the transfer gate TG.

[0270] Hence, in the present embodiment, impurity ions made of arsenic (As) and phosphorus (P) are contained in polysilicon to lower the resistance of the wiring layer 71 made of polysilicon and reduce diffusion of impurity ions in polysilicon.

[0271] Fig. 60 is the sectional view of a photodetection element 1 according to the eighth embodiment. In the photodetection element 1 according to the eighth embodiment, pixels 12 including respective photodiodes PD are arranged in a first substrate 10, and a pixel circuit 22 including a pixel transistor 18 is disposed in a second substrate 20. One or more wiring layers 71 are arranged in an interlayer 70 (interlayer insulating layer) disposed between the first substrate 10 and the second substrate 20. The wiring layers 71 of the interlayer 70 are made of polysilicon containing arsenic (As) and phosphorus (P).

[0272] In the interlayer 70, one or more wiring layers 71 are arranged at the same or different layers, but in Fig. 60, only one wiring layer 71 (hereinafter, first wiring layer 71a) is illustrated. The first wiring layer 71a is connected to the floating diffusion FD of the first substrate 10 via a first contact 73a. In addition, a first contact 72a extending to the second substrate 20 is connected to the first wiring layer 71a, and the first contact 72a is connected to the pixel transistor 18 via the wiring layers 71 of the second substrate 20.

[0273] The floating diffusion FD illustrated in Fig. 60 is formed by implanting impurity ions containing arsenic (As) and phosphorus (P) into a silicon substrate. An SiO2layer is disposed on a silicon substrate, a part of the SiO2layer is etched and removed according to positions of the first wiring layer 71a and a first contact 73a to form a trench, the trench is filled with polysilicon, and thereby the first wiring and the first contact 73a are formed.

[0274] A method for forming the floating diffusion FD is not limited to a method illustrated in Fig. 60.

[0275] Fig. 61 is a sectional view of a photodetection element 1 according to a first modification example of the eighth embodiment. In the photodetection element 1 according to the first modification example, a trench is formed at a portion where the floating diffusion FD is formed in the silicon substrate, the trench is filled with SiO2which is a material of an element isolation portion 43, and polysilicon is applied thereon. Then, impurity ions containing arsenic (As) and phosphorus (P) are implanted into a polysilicon-filled region, and thermal diffusion is performed. Therefore, an impurity diffusion region is formed in a side wall direction of the polysilicon-filled region to form the floating diffusion FD. This manufacturing method is referred to as a method for forming a side contact 27. An FD capacitance only needs to be a capacitance which enables accumulated charge of the photodiode PD to be retained, and a capacitance equal to or larger than the capacitance results in an increase in noise. By forming the floating diffusion FD by the side contact 27, the FD capacitance can decrease, and noise can be reduced.

[0276] In addition, in the present embodiment, a concentration of arsenic (As) in the first wiring layer 71a is higher than a concentration of phosphorus (P). Therefore, diffusion of the impurity ions inside the floating diffusion FD into the silicon substrate is reduced, and it is possible to reduce noise by a decrease in the FD capacitance and reduce a leakage current by a decrease in magnitude of the electric field in the vicinity of TG.

[0277] Fig. 62 is a sectional view of a photodetection element 1 according to a second modification example of the eighth embodiment. In the photodetection element 1 according to the second modification example, a first wiring layer 71a and a second wiring layer 71b are arranged at the same layer of the interlayer 70. The first wiring layer 71a is connected to the floating diffusion FD of a first substrate 10 via a first contact 73a and is connected to a pixel transistor 18 of a second substrate 20 via a second contact 72b. The second wiring layer 71b is connected to the transfer transistor TR of the first substrate 10 via a third contact 73c and is connected to a gate voltage control line of the transfer transistor TR via a fourth contact.

[0278] Both the first wiring layer 71a and the second wiring layer 71b are made of polysilicon containing impurity ions of arsenic (As) and phosphorus (P). A concentration of impurity ions contained in the first wiring layer 71a and a concentration of impurity ions contained in the second wiring layer 71b are different from each other.

[0279] More specifically, a concentration of arsenic (As) of the first wiring layer 71a is higher than a concentration of arsenic (As) of the second wiring layer 71b. Alternatively, a concentration of phosphorus (P) of the first wiring layer 71a is lower than a concentration of phosphorus (P) of the second wiring layer 71b. Therefore, the FD capacitance can decrease, and the resistance of the second wiring layer 71b can be lowered.

[0280] In addition, a concentration of phosphorus (P) of the second wiring layer 71b is higher than a concentration of arsenic (As) thereof. Therefore, the resistance of the second wiring layer 71b can be lowered, and the transfer transistor TR can be operated at high speed.

[0281] Fig. 63 is a sectional view of a photodetection element 1 according to a third modification example of the eighth embodiment. The photodetection element 1 according to the third modification example includes a surrounding region disposed outside a pixel region. In an interlayer 70, a third wiring layer 71c is provided in addition to the first wiring layer 71a and the second wiring layer 71b described above. The first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c may be arranged at the same layer of the interlayer 70 or may be arranged at two or more layers.

[0282] The third wiring layer 71c is connected to a diffusion layer in the surrounding region of the first substrate 10 via a fifth contact.

[0283] In the photodetection element 1 according to the third modification example, each of the first wiring layer 71a, the second wiring layer 71b, and the third wiring layer 71c is made of polysilicon containing arsenic (As) ions and phosphorus (P) ions. A concentration of impurities contained in the first wiring layer 71a is different from a concentration of impurities contained in the third wiring layer 71c.

[0284] More specifically, an arsenic (As) concentration of the first wiring layer 71a is higher than an arsenic (As) concentration of the third wiring layer 71c. Alternatively, a concentration of phosphorus (P) of the first wiring layer 71a is lower than a concentration of phosphorus (P) of the third wiring layer 71c. Therefore, it is possible to achieve both the decrease in the FD capacitance and the decrease in the resistance of the third wiring layer 71c.

[0285] In addition, a concentration of phosphorus (P) of the third wiring layer 71c is higher than a concentration of arsenic (As) thereof. Therefore, the resistance of the third wiring layer 71c can be lowered, and a reference voltage is stabilized such that the image quality can be improved.

[0286] Figs. 64A to 64I are process-sectional views illustrating a manufacturing process of the photodetection element 1 according to the eighth embodiment. First, the pixel 12 including the photodiode PD, the transfer transistor TR, and the floating diffusion FD is formed on a silicon substrate that is the first substrate 10 (Fig. 64A).

[0287] Next, an SiO2film 46 is formed on an upper surface of the first substrate 10, a part of the SiO2film 46 is removed by photolithography to form a trench 38, the trench 38 is filled with polysilicon, and a wiring layer 71 made of polysilicon is formed on an upper surface of the SiO2film. Next, impurity ions containing arsenic (As) and phosphorus (P) are implanted into the wiring layer 71 (Fig. 64B). When the impurity ions are implanted, the impurity ions may be separately implanted using a resist mask (Fig. 64C).

[0288] Next, the wiring layer 71 is patterned by photolithography using dry etching to form the first wiring layer 71a and the second wiring layer 71b (Fig. 64D).

[0289] Next, a heat treatment is performed to activate the impurity ions implanted into the first wiring layer 71a and the second wiring layer 71b (Fig. 64E).

[0290] Next, the second substrate 20 is attached (Fig. 64F). Next, a readout circuit (pixel circuit 22) is formed in the second substrate 20 (Fig. 64G). Next, the trench 38 is formed in the second substrate 20 by photolithography (Fig. 64H), and contacts 72a and 72b and a metal wiring 39 are formed (Fig. 64H).

[0291] In this manner, in the eighth embodiment, since at least one of the wiring layers 71 arranged in the interlayer 70 is made of polysilicon containing arsenic (As) and phosphorus (P), it is possible to achieve both the decrease in resistance of the wiring layer 71 and the reduction in diffusion of impurity ions into polysilicon. In a case where the plurality of wiring layers 71 is arranged in the interlayer 70, it is possible to further improve the image quality of a captured image by controlling the impurity concentrations of arsenic (As) and phosphorus (P) for each wiring layer 71.

[0292] The method of forming the wiring layers 71 arranged in the interlayer 70 which are made of polysilicon containing arsenic (As) and phosphorus (P) is also applicable to the photodetection elements 1 according to the first to seventh embodiments described above. By optimizing (or alternatively, controlling) the impurity concentrations of arsenic (As) and phosphorus (P) for each wiring layer 71 disposed in the interlayer 70, it is possible to improve the image quality of captured images generated by the photodetection elements 1 according to the first to seventh embodiments and increase a charge transfer speed.

[0293] (Ninth Embodiment) In a case where the photodetection element 1 has a stacked structure of the first substrate 10 and the second substrate 20, the first substrate 10 and the second substrate 20 do not need to be set to the same potential, and thus an electric field is applied between the first substrate 10 and the second substrate 20. For example, when a power supply voltage of the first substrate 10 fluctuates for some reason, a power supply voltage of the second substrate 20 also fluctuates. This adversely affects electrical characteristics of the photodetection element 1. Hence, in a ninth embodiment, the wiring layer 71 functioning as a shield layer is disposed in the interlayer insulating layer (interlayer) 70 between the first substrate 10 and the second substrate 20 to shield the above-described electric field.

[0294] Fig. 65A is a longitudinal-sectional view of a photodetection element 1 according to the ninth embodiment, and Fig. 65B is a cross-sectional view from line A-B in Fig. 65A.

[0295] As illustrated in Fig. 65A, the photodetection element 1 according to the ninth embodiment includes a first substrate 10 and a second substrate 20 that are stacked and an interlayer insulating layer (interlayer) 70 disposed between the first substrate 10 and the second substrate 20. In the first substrate 10, a photodiode PD, a transfer transistor TR, a floating diffusion FD, and the like are arranged. On the second substrate 20, pixel transistors 18 such as an amplification transistor AMP and a selection transistor SEL are arranged. Although not illustrated in Fig. 65A, a reset transistor RST, a conversion efficiency switching transistor FDG, and the like may be disposed in the second substrate 20. The pixel transistor 18 may be a planar type, may have a FIN-FET structure, or may have a gate all-around structure.

[0296] The wiring layer 71 is disposed in the interlayer 70. The wiring layer 71 functions as the shield layer that shields an electric field generated between the first substrate 10 and the second substrate 20. The wiring layer 71 is made of, for example, polysilicon. Note that, as described later, the wiring layer 71 can also be made of a conductive material other than polysilicon.

[0297] In the wiring layer 71, an opening portion 65 for a first contact 72a extending from the floating diffusion FD of the first substrate 10 to the second substrate 20 is provided. The opening portion 65 has a diameter larger than an outer diameter of the first contact 72a. An insulating layer 66 is disposed around the opening portion 65 in the wiring layer 71. That is, the insulating layer 66 is disposed in a predetermined region including a connection portion with the first contact 72a in the wiring layer 71. The predetermined region has any size and shape. In Fig. 65B, the insulating layer 66 has a rectangular shape, but may have another shape such as a circular shape. By disposing the insulating layer 66 around the opening portion 65 of the wiring layer 71, the first contact 72a and the wiring layer 71 can be electrically insulated from each other, and there is no possibility that the first contact 72a and the wiring layer 71 will be short-circuited.

[0298] The insulating layer 66 may contain two or more kinds of insulants having different dielectric constants. For example, the insulating layer 66 may include an air layer 67 disposed to surround the first contact 72a. More specifically, the insulating layer 66 may include a first insulating layer 66a and a second insulating layer 66b in addition to the air layer 67. The first insulating layer 66a is disposed to surround the first contact 72a at a location closer to the first contact 72a than the air layer 67 and contains an insulant having a dielectric constant higher than that of the air layer 67. The second insulating layer 66b is disposed to surround the first contact 72a at a location farther apart from the first contact 72a than the air layer 67 and contains an insulant having a dielectric constant higher than that of the air layer 67. By disposing the air layer 67 in a part of the insulating layer 66, the dielectric constant of the insulating layer 66 can be lowered, and the capacitance between the first contact 72a and the wiring layer 71 can decrease. By decreasing the capacitance between the first contact 72a and the wiring layer 71, for example, a decrease in photoelectric conversion efficiency can be reduced.

[0299] On the other hand, since the second contact 72b is arranged to be conductive with the wiring layer 71, the wiring layer 71 is set to a predetermined potential via the second contact 72b. The second contact 72b is connected to the p-well layer 42 of the first substrate 10 and is set to, for example, a ground potential. Accordingly, by connecting the second contact 72b to the wiring layer 71, the wiring layer 71 can be set to the ground potential.

[0300] The wiring layer 71 is disposed, for example, over an entire horizontal cross section of the interlayer insulating layer (interlayer) 70. Therefore, the electric field between the first substrate 10 and the second substrate 20 can be shielded regardless of the sizes of the first substrate 10 and the second substrate 20. Note that, as described later, a modification example is also conceivable in which the size of the wiring layer 71 is made smaller than that of the entire region of the horizontal cross section of the interlayer insulating layer (interlayer) 70.

[0301] Although Figs. 65A and 65B illustrate two contacts (the first contact 72a and the second contact 72b) which intersect or are connected to the wiring layer 71, other contacts may be arranged to intersect or be connected to the wiring layer 71. In this case, similarly to the first contact 72a, it is necessary to provide the insulating layer 66 around the contacts.

[0302] Various modification examples are conceivable regarding the material and the like of the insulating layer 66 disposed in a part of the wiring layer 71.

[0303] Fig. 66A is a longitudinal-sectional view of a photodetection element 1 according to a first modification example of the ninth embodiment, and Fig. 66B is a cross-sectional view from line A-B in Fig. 66A. In the photodetection element 1 according to the first modification example, the material of the insulating layer 66 disposed in a part of the wiring layer 71 is different from that described above. An insulating layer 66L of the photodetection element 1 according to the first modification example is made of a low-k material. By using the low-k material for the insulating layer 66L, the dielectric constant of the insulating layer 66L can be lowered, and the capacitance between the first contact 72a and the wiring layer 71 can decrease. For example, the dielectric constant of the insulating layer 66L is preferably 3.0 or less, and more preferably 2.8 or less. The lower limit value of the dielectric constant of the insulating layer 66 is preferably 2.3 or more.

[0304] As a specific low-k constant material, for example, hydrogen silsesquioxane resin (HSQ: relative dielectric constant of 3.0), benzocyclobutene (BCB: relative dielectric constant of 2.7), poly aryl ether (PAE: relative dielectric constant of 2.7), carbon-containing silicon oxide (SiOC: relative dielectric constant of 2.9), poly arylate (PAr: relative dielectric constant of 2.65), fluorine-doped silicon oxide (SiOF: relative dielectric constant of 2.6 to 3.7), and fluorine-doped silicon oxide (SiO2 film fluorine-doped silicon dioxide: content of 11 at% and relative dielectric constant of 3.3 to 3.4) can be used.

[0305] Additionally, as the low-k material used for the insulating layer 66L, SiOC, a porous material, or the like can be used.

[0306] Fig. 67A is a longitudinal-sectional view of a photodetection element 1 according to a second modification example of the ninth embodiment, and Fig. 67B is a cross-sectional view from line A-B in Fig. 67A. In the photodetection element 1 according to the second modification example, a material of the insulating layer 66I disposed in a part of the wiring layer 71 is different from that described above. The insulating layer 66I of the photodetection element 1 according to the second modification example is made of an insulant such as SiO2. Here, SiO2may be doped with various impurities. For example, fluorine-doped silicon oxide is preferable from the viewpoint of ease of production. The fluorine-doped silicon oxide is an oxide film to which fluorine is added, and is formed by, for example, a plasma chemical vapor deposition (CVD) method using a source such as a TEOS-C2F6system or triethoxyfluorosilane (TEFS).

[0307] As a material of the wiring layer 71, polysilicon can be used as described above, but a metal material or a conductive organic material may be used in addition to polysilicon.

[0308] In Figs. 65A, 66A, and 67A and Figs. 65B, 66B, and 67B described above, examples in which the wiring layer 71 is disposed in the entire region of the horizontal cross section (cross section) of the interlayer 70 has been described, but the wiring layer 71 may be disposed only at a portion where an electric field is generated between the first substrate 10 and the second substrate 20.

[0309] Fig. 68A is a longitudinal-sectional view of a photodetection element 1 according to a third modification example of the ninth embodiment, and Fig. 68B is a cross-sectional view from line A-B in Fig. 68A. The photodetection element 1 according to the third modification example includes a wiring layer 71 disposed only in a part of one layer of the interlayer 70. The wiring layer 71 is disposed at a portion where an electric field is generated between the first substrate 10 and the second substrate 20. Alternatively, the wiring layer 71 is disposed at a portion where a circuit or the like disposed in the first substrate 10 and the second substrate 20 may be adversely affected by the electric field generated between the first substrate 10 and the second substrate 20.

[0310] In the same layer as the wiring layer 71, an insulating layer 46 is disposed to surround the wiring layer 71. The insulating layer 46 is, for example, an SiO2layer.

[0311] The wiring layer 71 according to the third modification example has an area smaller than that of the wiring layers 71 in Figs. 65B, 66B, and 67B described above. As a material of the wiring layer 71, for example, polysilicon is used similarly to the wiring layers 71 described above.

[0312] An insulating layer 66 is disposed in a part of the wiring layer 71 according to the third modification example. A material and a shape of the insulating layer 66 are similar to those in Fig. 65B, for example. Similarly to Fig. 65B, a second contact 72b is connected to the wiring layer 71.

[0313] Since the wiring layer 71 according to the third modification example only needs to have a minimum (or alternatively, reduced)necessary area, as illustrated in Fig. 68B, an opening portion may be provided between a connection portion with the second contact 72b and the insulating layer 66. The insulating layer 66 made of SiO2or the like is disposed in the opening portion.

[0314] Fig. 69A is a longitudinal-sectional view of a photodetection element 1 according to a fourth modification example of the ninth embodiment, and Fig. 69B is a cross-sectional view from line A-B in Fig. 69A. Similarly to the third modification example, the photodetection element 1 according to the fourth modification example includes the wiring layer 71 disposed only in a part of one layer of the interlayer 70. The fourth modification example differs from the third modification example in that a material of the insulating layer 66L disposed around the wiring layer 71 is a low-k material. More specifically, in the fourth modification example, both the insulating layer 66L disposed in a part of an inner side of the wiring layer 71 and the insulating layer 66L disposed on an outer side of the wiring layer 71 are made of the low-k material. As a specific material of the low-k material, the material described in the first modification example can be used. The wiring layer 71 is made of, for example, polysilicon.

[0315] Fig. 70A is a longitudinal-sectional view of a photodetection element 1 according to a fifth modification example of the ninth embodiment, and Fig. 70B is a cross-sectional view from line A-B in Fig. 70A. In the photodetection element 1 according to the fifth modification example, a material of an insulating layer 66I around the wiring layer 71 is, for example, a material using SiO2instead of the low-k material of the fourth modification example. Here, SiO2is generally used as a material of the interlayer insulating layer (interlayer) 70 and is easily manufactured.

[0316] Fig. 71A is a longitudinal-sectional view of a photodetection element 1 according to a sixth modification example of the ninth embodiment, and Fig. 71B is a cross-sectional view from line A-B in Fig. 71A. In the wiring layer 71 disposed in the interlayer 70, a first contact 72a and a second contact 72b extending in a second direction are arranged. The first contact 72a is disposed to face a pixel transistor of the second substrate 20 at a side wall portion thereof, and a parasitic capacitance is generated therebetween. Similarly, the second contact 72b is disposed to face a pixel transistor of the second substrate 20 at a side wall portion thereof, and a parasitic capacitance is generated therebetween. There is a possibility that these parasitic capacitances may adversely affect the electrical characteristics of the pixel transistors. Hence, the sixth modification example is characterized in that the side wall portions of the first contact 72a and the second contact 72b are covered with respective side wall insulating layers 66s. The side wall insulating layer 66s preferably has a low dielectric constant and is made of, for example, a low-k material. As a specific material of the low-k material, the material described in the first modification example can be used.

[0317] By covering the side wall portions of the first contact 72a and the second contact 72b with the side wall insulating layers 66s, the parasitic capacitances between the first contact 72a and the second contact 72b and the pixel transistor can be reduced, and thus no adverse effects of the parasitic capacitances are applied.

[0318] Also in the photodetection elements 1 according to the ninth embodiment or the first to fifth modification examples described above, a side wall insulating film similar to the side wall insulating layer of the sixth modification example may be provided.

[0319] Next, a manufacturing process of the photodetection element 1 according to the ninth embodiment will be described. Figs. 72A to 72L are plan views and process-sectional views illustrating the manufacturing process of the photodetection element 1 according to the ninth embodiment. Fig. 72A illustrates a state in which the floating diffusion FD, the transfer transistor TR, and the p-well layer 42 are formed on the first substrate 10. The element isolation portion 43 is disposed on the first substrate 10 side of the floating diffusion FD and the p-well layer 42. The element isolation portion 43 has an insulating layer 43a made of SiO2and a p-type diffusion layer 43b surrounding the insulating layer. The p-type diffusion layer 43b is also referred to as a pinning layer.

[0320] Next, as illustrated in Fig. 72B, an interlayer insulating layer (interlayer) 70 is disposed on the first substrate 10, and a polysilicon layer 71p is disposed thereon. The interlayer insulating layer (interlayer) 70 is, for example, an SiO2layer 46. The polysilicon layer 71p is made of the material of the wiring layer 71.

[0321] Next, as illustrated in Fig. 72C, a resist layer 68 is applied onto the polysilicon layer 71p by a photolithography method, and the resist layer 68 is patterned. The resist layer 68 is patterned according to the location of the insulating layer 66 disposed in a part of the wiring layer 71.

[0322] Next, as illustrated in Fig. 72D, a part of the polysilicon layer 71p is removed using the resist layer 68 as a mask such that the SiO2layer 46 is exposed.

[0323] Next, as illustrated in Fig. 72E, a silicon oxide film 69 is formed on the patterned resist layer 68 by, for example, the HDP method. The silicon oxide film 69 is, for example, an SiO film.

[0324] Next, as illustrated in Fig. 72F, a resist layer 47 is applied and patterned on the SiO film 69 by a photolithography method. A portion where the resist layer 47 is removed is a portion where the air layer 67 is formed in the insulating layer 66. The SiO film 69 is exposed at the portion where the resist layer 47 is removed.

[0325] Next, as illustrated in Fig. 72G, the SiO film 69 is partially removed using the resist layer 47 as a mask such that the SiO2film 46 is exposed and the resist layer 47 is removed.

[0326] Next, as illustrated in Fig. 72H, the SiO film 69 is formed to be thick by, for example, the HDP method. Since the HDP method has poor embeddability, the air layer 67 remains without being filled with the SiO film 69. Through the above processes, the interlayer insulating layer (interlayer) 70 is formed on the first substrate 10.

[0327] Next, as illustrated in Fig. 72I, the second substrate 20 is attached onto the interlayer insulating layer (interlayer) 70. The second substrate 20 has the stacked structure in which a p-well layer 20d and an SiO2layer 20e are sequentially stacked on a silicon substrate 20c. The SiO2layer 20e of the second substrate 20 is disposed to face the interlayer insulating layer (interlayer) 70 and is attached thereto.

[0328] Next, as illustrated in Fig. 72J, a trench 20f penetrating the second substrate 20 to extend to the floating diffusion FD of the first substrate 10 and a trench 20g penetrating the second substrate 20 to extend to the p-well layer 42 of the first substrate 10 are formed. These trenches 20f and 20g are aligned so as not to be in contact with the air layer 67. In addition, a trench 20h that does not penetrate the second substrate 20 is also formed in the second substrate 20.

[0329] Next, as illustrated in Fig. 72K, the trenches 20f, 20g, and 20h are filled with a conductive material (for example, polysilicon or a metal material) or the like such that the first contact 72a, the second contact 72b, and the other contact 72c are formed.

[0330] Next, as illustrated in Fig. 72L, the pixel transistors 18 are formed on the second substrate 20.

[0331] In this manner, in the ninth embodiment, the wiring layer 71 for shielding the electric field applied between the first substrate 10 and the second substrate 20 is disposed in the interlayer insulating layer (interlayer 70) disposed between the first substrate 10 and the second substrate 20. Therefore, circuit elements arranged in the first substrate 10 and the second substrate 20 are not affected by the electric field. In addition, since the insulating layer 66 is disposed in a part of the wiring layer 71 so that the first contact 72a penetrating the wiring layer 71 to extend to the second substrate 20 is not electrically connected to the wiring layer 71, the first contact 72a and the wiring layer 71 can be electrically insulated from each other. In addition, by providing the air layer 67 in the insulating layer 66 or forming the insulating layer 66 made of a material having a low dielectric constant, the parasitic capacitance between the first contact 72a and the wiring layer 71 can decrease.

[0332] (Tenth Embodiment) In a case where one floating diffusion FD is shared by a plurality of pixels, there is a possibility that a retention capacitance of the floating diffusion FD is insufficient and the charge due to photoelectric conversion of the pixels is unlikely to be completely retained in the floating diffusion FD. As a countermeasure to this, it is conceivable to increase a potential of the floating diffusion FD to increase the retention capacitance.

[0333] Fig. 73 is a circuit diagram of a pixel 12 and a pixel circuit 22 of a photodetection element 1 according to a tenth embodiment, and Fig. 74 is a timing diagram of the pixel circuit 22 of Fig. 73. In Fig. 73, circuit elements that are the same as those in Fig. 2 are denoted by the same reference numerals, and differences will be mainly described below.

[0334] In the photodetection element 1 according to the tenth embodiment, one floating diffusion FD and the pixel circuit 22 are shared by a plurality of pixels 12. An FDB capacitance unit 101 is connected to the floating diffusion FD. The FDB capacitance unit 101 is a capacitance unit formed between an FDB wiring that is disposed in the interlayer 70 of Fig. 3 and an FD wiring that is electrically connected to the floating diffusion FD. An FDB signal is supplied to the FDB wiring. For example, the FDB signal is set to a potential corresponding to a potential of the transfer gate of the transfer transistor TR. Specifically, a potential of the FDB signal increases during a period during which the potential of the transfer gate increases and the transfer transistor TR is turned on. The potential of the FDB signal decreases during a period during which the potential of the transfer gate decreases and the transfer transistor TR is turned off. When the potential of the FDB signal increases, the potential of the floating diffusion FD also increases, and the amount of charge that can be retained in the floating diffusion FD can be increased.

[0335] As described above, in the photodetection element 1 according to the tenth embodiment, the FDB wiring that is capacitively coupled to the FD wiring is disposed in the interlayer 70, the FDB capacitance unit 101 is formed, and the amount of charge that can be retained in the floating diffusion FD is increased during the period during which the transfer transistor TR is turned on. Therefore, more accumulated charge of the photodiode PD can be transferred to the floating diffusion FD, and residual charge of the photodiode PD can be reduced.

[0336] The reset transistor RST is turned on between times t1 and t2 in Fig. 74, and retained charge of the floating diffusion FD is discharged to the power supply voltage node via the reset transistor RST. Between times t2 and t3, both the reset transistor RST and the transfer transistor TR are turned off. The photodiode PD of each pixel continuously accumulates charge due to photoelectric conversion during a period between times t1 and t3.

[0337] The transfer transistor TR is turned on between times t3 and t4. The accumulated charges of the photodiodes PD of all the pixels are transferred to the floating diffusion FD via the transfer transistor TR. In addition, between times t3 and t4, the potential of the FDB signal increases, the potential of the floating diffusion FD also increases, and the amount of charge that can be retained in the floating diffusion FD increases. Accordingly, all the accumulated charges of all the photodiodes PD are transferred to the floating diffusion FD, and no residual charge remains in all the photodiodes PD.

[0338] When the transfer transistor TR is turned off at the time t4, an exposure period is started. During the exposure period, the photodiodes PD of all the pixels accumulate charge due to the photoelectric conversion.

[0339] Between times t5 and t6, the reset transistor RST is turned on again. Therefore, retained charge of the floating diffusion FD is discharged to the power supply voltage node via the reset transistor RST. At this time point, since the transfer transistor TR is turned off, the photodiodes PD continue to accumulate charge.

[0340] Thereafter, the SEL signal reaches a high potential at a time t7, and the selection transistor SEL is turned on between times t7 and t12 when the SEL signal reaches the high potential. Between times t7 and t8, the reset transistor RST is turned on again, retained charge of the floating diffusion FD is discharged to the power supply voltage node via the reset transistor RST, and the potential of the floating diffusion FD at this time is read as a reset level to a vertical signal line.

[0341] Thereafter, the transfer transistor TR is turned on between times t9 and t10, and the potential of the FDB wiring increases between times t9 and t11. Therefore, between times t9 and t10, the capacitance that can be retained in the floating diffusion FD increases, and thus, all the accumulated charges of the photodiodes PD of all the pixels are transferred to the floating diffusion FD.

[0342] Fig. 75 is a plan view of the interlayer 70 of the photodetection element 1 according to the tenth embodiment, and Fig. 76 is a sectional view taken along line A-B in Fig. 75. Figs. 75 and 76 illustrate an example in which 2 × 4 pixels share one floating diffusion FD. As illustrated in Fig. 75, an FD wiring layer 71d extending in the first direction X is disposed in a substantially central portion of an area of the 2 × 4 pixels, and two FDB wiring layers 102 extending in the second direction Y are arranged on both sides of the FD wiring layer 71d in the first direction X. All the FD wiring layer 71d and the FDB wiring layers 102 have a rectangular shape. Four transfer gates TRG0 to TRG3 and four transfer gates TRG4 to TRG7 are arranged on both sides of the FD wiring layer 71d in the second direction Y, respectively.

[0343] As illustrated in Fig. 76, the FD wiring layer 71d and the FDB wiring layer 102 are arranged separately at the same height of the interlayer 70. The FD wiring layer 71d is connected to a contact 73d and the floating diffusion FD that is disposed in the first substrate 10. A contact 72d extending in the second substrate 20 is connected to the FDB wiring layer 102.

[0344] There are various conceivable modification examples for shapes and arrangement locations of the FD wiring layer 71d and the FDB wiring layers 102 in the photodetection element 1 according to the tenth embodiment. Fig. 77 is a table summarizing representative modification examples of shapes and layer configurations of the FD wiring layer 71d and the FDB wiring layer 102 in the photodetection element 1 according to the tenth embodiment. Fig. 77 is a table illustrating a correspondence relationship between the number of wiring layers (the number of poly layers) made of polysilicon, a planar shape of the FD wiring layer 71d, and a planar shape of the FDB wiring layer 102 in each specific example. The FD wiring layer 71d may or may not be divided into two FD wiring layers (a first FD wiring layer and a second FD wiring layer). The FDB wiring layer 102 may or may not be divided into two FDB wiring layers (a first FDB wiring layer and a second FDB wiring layer). The first row in Fig. 77 indicates the tenth embodiment illustrated in Figs. 75 and 76, and the second and subsequent rows indicate first to ninth modification examples. Note that Fig. 77 illustrates merely representative modification examples, and it is conceivable to provide modification examples other than those illustrated in Fig. 77.

[0345] As illustrated in Fig. 77, the planar shapes of the FD wiring layer 71d are broadly divided into a rectangular shape and a bent shape. The bent shape is a shape formed by bonding a plurality of wiring layers extending in two or more directions. The bent shape may be referred to as a comb-teeth shape. The planar shapes of the FDB wiring layer 102 are also broadly divided into a rectangular shape and a bent shape. In addition, a stacked structure of the FD wiring layers 71d and a stacked structure of the FDB wiring layers 102 may be provided in the interlayer 70 (the third to ninth modification examples). Hereinafter, the first to ninth modification examples will be described in order.

[0346] Fig. 78 is a plan view of an interlayer 70 of a photodetection element 1 according to the first modification example of the tenth embodiment, and Fig. 79 is a sectional view taken along line A-B in Fig. 78. In the first modification example, the planar shape of the FD wiring layer 71d is a rectangular shape, whereas the planar shape of the FDB wiring layer 102 is a bent shape. One of the two FDB wiring layers 102 disposed on both sides of the FD wiring layer 71d in the first direction X is disposed to surround at least a part of the FD wiring layer 71d, whereas the other FDB wiring layer 102 is bent toward a side different from a side, on which the FD wiring layer 71d is disposed, and does not surround the FD wiring layer 71d. A sectional structure illustrated in Fig. 79 is the same as or similar to that in Fig. 77.

[0347] Fig. 80 is a plan view of an interlayer 70 of a photodetection element 1 according to the second modification example of the tenth embodiment, and Fig. 81 is a sectional view taken along line A-B in Fig. 80. In the second modification example, the FD wiring layer 71d has a bent shape, and the planar shape of the FDB wiring layer 102 is a rectangular shape. The FD wiring layer 71d is disposed to surround at least a part of one FDB wiring layer 102. A sectional structure illustrated in Fig. 81 is the same as or similar to that in Fig. 77.

[0348] Figs. 82 and 83 are plan views of an interlayer 70 of a photodetection element 1 according to the third modification example of the tenth embodiment, and Fig. 84 is a sectional view of Fig. 82 or 83. In the third modification example, all the FD wiring layer 71d and the FDB wiring layers 102 have the stacked structure. The FD wiring layer 71d includes a first FD wiring layer 71d1 and a second FD wiring layer 71d2 which are stacked, and the first FD wiring layer 71d1 and the second FD wiring layer 71d2 are connected by a contact 72e. The FDB wiring layer 102 includes a first FDB wiring layer 1021 and a second FDB wiring layer 1022 which are stacked, and the first FDB wiring layer 1021 and the second FDB wiring layer 1022 are connected by a contact 72f. All of the first FD wiring layer 71d1, the second FD wiring layer 71d2, the first FDB wiring layer 1021, and the second FDB wiring layer 1022 have a rectangular shape.

[0349] Figs. 85 and 86 are plan views of an interlayer 70 of a photodetection element 1 according to the fourth modification example of the tenth embodiment, and Fig. 87 is a sectional view of Fig. 85 or 86. In the fourth modification example, similarly to the third modification example, both the FD wiring layer 71d and the FDB wiring layer 102 which are disposed in the interlayer 70 have the stacked structure. The planar shape of the first FDB wiring layer 1021 which is one of the first FDB wiring layer 1021 and the second FDB wiring layer 1022 constituting the FDB wiring layer 102 is a bent shape, whereas the planar shape of the second FDB wiring layer 1022 is a rectangular shape. Both the first FD wiring layer 71d1 and the second FD wiring layer 71d2 constituting the FD wiring layer 71d have a rectangular shape. The sectional structure illustrated in Fig. 87 is the same as or similar to that of Fig. 84.

[0350] Figs. 88 and 89 are plan views of an interlayer 70 of a photodetection element 1 according to the fifth modification example of the tenth embodiment, and Fig. 90 is a sectional view of Fig. 88 or 89. In the fifth modification example, similarly to the third modification example, both the FD wiring layer 71d and the FDB wiring layer 102 which are disposed in the interlayer 70 have the stacked structure. The planar shape of the first FD wiring layer 71d1 which is one of the first FD wiring layer 71d1 and the second FD wiring layer 71d2 constituting the FD wiring layer 71d is a bent shape, and the planar shape of the second FD wiring layer 71d2 which is the other thereof is a rectangular shape. All of the first FDB wiring layer 1021 and the second FDB wiring layer 1022 constituting the FDB wiring layer 102 have a rectangular shape. The first FD wiring layer 71d1 is disposed to surround at least a part of one first FDB wiring layer 1021. The sectional structure illustrated in Fig. 90 is the same as or similar to that of Fig. 84.

[0351] Figs. 91 and 92 are plan views of an interlayer 70 of a photodetection element 1 according to the sixth modification example of the tenth embodiment, and Fig. 93 is a sectional view of Fig. 91 or 92. In the sixth modification example, the FD wiring layer 71d disposed in the interlayer 70 has a single-layer structure, whereas the FDB wiring layer 102 has the stacked structure. The planar shape of the FD wiring layer 71d is a rectangular shape. The planar shape of both the first FDB wiring layer 1021 and the second FDB wiring layer 1022 constituting the FDB wiring layer 102 is the rectangular shape.

[0352] The FD wiring layer 71d is not provided at the same height as the second FDB wiring layer 1022. A contact 72g extends upward from the FD wiring layer 71d, and the second FDB wiring layer 1022 is disposed to surround the contact 72g.

[0353] Figs. 94 and 95 are plan views of an interlayer 70 of a photodetection element 1 according to the seventh modification example of the tenth embodiment, and Fig. 96 is a sectional view of Fig. 94 or 95. In the seventh modification example, the FD wiring layer 71d disposed in the interlayer 70 has the single-layer structure, whereas the FDB wiring layer 102 has the stacked structure. The planar shape of the FD wiring layer 71d is a rectangular shape. The planar shape of the first FDB wiring layer 1021 from the first FDB wiring layer 1021 and the second FDB wiring layer 1022 constituting the FDB wiring layer 102 is a bent shape, whereas the planar shape of the second FDB wiring layer 1022 is a rectangular shape. One second FDB wiring layer 1022 is disposed to surround at least a part of the FD wiring layer 71d, one of the two first FDB wiring layers 1021 is bent toward a side opposite side to the FD wiring layer 71d, and the other is disposed to surround at least a part of the FD wiring layer 71d.

[0354] The FD wiring layer 71d is not provided at the same height as the second FDB wiring layer 1022. A contact 72g extends upward from the FD wiring layer 71d, and the second FDB wiring layer 1022 is disposed to surround the contact 72g. The sectional structure illustrated in Fig. 96 is the same as or similar to that of Fig. 93.

[0355] Figs. 97 and 98 are plan views of an interlayer 70 of a photodetection element 1 according to the eighth modification example of the tenth embodiment, and Fig. 99 is a sectional view of Fig. 97 or 98. In the eighth modification example, the FD wiring layer 71d disposed in the interlayer 70 has the single-layer structure, whereas the FDB wiring layer 102 has the stacked structure. The planar shape of the FD wiring layer 71d is the bent shape. All of the first FDB wiring layer 1021 and the second FDB wiring layer 1022 constituting the FDB wiring layer 102 have a rectangular shape. The FD wiring layer 71d is disposed to surround at least a part of one first FDB wiring layer 1021.

[0356] The FD wiring layer 71d is not provided at the same height as the second FDB wiring layer 1022. A contact 72g extends upward from the FD wiring layer 71d, and the second FDB wiring layer 1022 is disposed to surround the contact 72g. The sectional structure illustrated in Fig. 99 is the same as or similar to that of Fig. 93.

[0357] Figs. 100 and 101 are plan views of an interlayer 70 of a photodetection element 1 according to the ninth modification example of the tenth embodiment, and Fig. 102 is a sectional view of Fig. 100 and 101. In the ninth modification example, the FD wiring layer 71d disposed in the interlayer 70 has the stacked structure, whereas the FDB wiring layer 102 has the single-layer structure. The first FD wiring layer 71d1 and the second FD wiring layer 71d2 constituting the FD wiring layer 71d are connected by a contact 72e. A shield wiring layer 103 is disposed at the same height as the first FD wiring layer 71d1. The shield wiring layer 103 is set to a predetermined potential (for example, ground potential). The FDB wiring layer 102 is disposed at the same height as the second FD wiring layer 71d2. The FDB wiring layer 102 and the shield wiring layer 103 are disposed so as not to overlap each other vertically. In the second FD wiring layer 71d2, the FDB wiring layer 102, and the shield wiring layer 103, contacts 72i, 72d, and 72j extending upward are disposed, respectively.

[0358] As described above, in the tenth embodiment, the FD wiring layer 71d and the FDB wiring layer 102 are disposed in the interlayer 70, and the potential of the FDB wiring layer 102 is raised in accordance with a timing when the transfer transistor TR is turned on. Therefore, the potentials of the FD wiring layer 71d that is capacitively coupled to the FDB wiring layer 102 and the floating diffusion FD can be raised, and the amount of charge that can be retained in the floating diffusion FD can be increased. Accordingly, a problem of residual charge remaining in the photodiode PD at the time of charge transfer does not arise.

[0359] When a pixel size is reduced, problems of arrangement locations of the FD wiring layer 71d and the FDB wiring layer 102 arise, but in the tenth embodiment, the FD wiring layer 71d and the FDB wiring layer 102 are arranged in the interlayer 70 between the first substrate 10 and the second substrate 20, and thus this does not hinder the reduction in the pixel size.

[0360] (Eleventh Embodiment) In the tenth embodiment, the example in which the FDB capacitance unit 101 for boosting the potential of the floating diffusion FD at the time of charge transfer is disposed in the interlayer 70 has been describe. However, other capacitors for various purposes can be disposed in the interlayer 70. In addition, a plurality of capacitors may be disposed in the interlayer 70.

[0361] Fig. 103 is a plan view of a lower side from an interlayer 70 of a photodetection element 1 according to an eleventh embodiment, Fig. 104 is a plan view of a lower side from a second substrate 20, Fig. 105 is a sectional view taken along line A-A’ in Figs. 103 and 104, Fig. 106 is a sectional view taken along line B-B’ in Figs. 103 and 104, and Fig. 107 is a sectional view taken along line C-C’ in Figs. 103 and 104.

[0362] As illustrated in Figs. 103 and 105, a plurality of wiring layers 70a is arranged in the interlayer 70. As illustrated in Fig. 104, in the second substrate 20, for example, an amplification transistor AMP and a selection transistor SEL are aligned in the second direction Y, and a reset transistor RST and an FD transfer transistor FDG are aligned in the second direction Y. A diffusion layer 120 is disposed between the pixel transistors 18.

[0363] As illustrated in Figs. 106 and 107, a capacitor 110 is disposed in the interlayer 70. The capacitor 110 can be used, for example, to retain a part of the accumulated charge of the photodiode PD. The capacitor 110 includes a first wiring layer 111 and a second wiring layer 112 that are stacked, and an insulating layer 113 disposed between the first wiring layer 111 and the second wiring layer 112. The first wiring layer 111 is connected to, for example, a drain of the FD transfer transistor FDG, that is, a source of the reset transistor RST, of the pixel circuit 22 in Fig. 2. The second wiring layer 112 is connected to, for example, a shared contact 73e connected to the floating diffusion FD.

[0364] In the interlayer 70, in addition to the capacitor 110, a transfer transistor TR, a shared contact 73a, the wiring layers 70a, and the like are disposed as illustrated in Fig. 105. In the first substrate 10, a photodiode PD is disposed for each pixel. The pixel transistors 18 such as the amplification transistor AMP are disposed in the second substrate 20.

[0365] By providing the capacitor 110 in the interlayer 70, a degree of freedom of the design layout of the first substrate 10 and the second substrate 20 is increased, and the pixel design is facilitated. In addition, by forming the capacitor 110 by using a wide range of the interlayer 70, the capacitance of the capacitor 110 can be increased, and more charge transferred from the photodiode PD can be retained.

[0366] The first wiring layer 111 and the second wiring layer 112 constituting the capacitor 110 are made of, for example, polysilicon. More specifically, the first wiring layer 111 is made of polysilicon containing high-concentration p-type impurity ions, and the second wiring layer 112 is made of polysilicon containing high-concentration n-type impurity ions. In a CV curve of a metal oxide semiconductor (MOS), capacitance decreases when an interface of silicon that is a semiconductor transitions to a depletion state, and capacitance increases when the interface transitions from the depletion state to an inversion state. When impurities are implanted into a semiconductor at a high concentration, a large voltage is used for the transition to the depletion state, and the transition to the depletion state does not occur in an operating voltage range, so that a change in capacitance can be curbed. Accordingly, by implanting high-concentration impurity ions into the first wiring layer 111 and the second wiring layer 112, the voltage dependence is reduced, and deterioration of the linearity of a brightness change can be prevented.

[0367] Note that the first wiring layer 111 and the second wiring layer 112 constituting the capacitor 110 may be made of a metal material such as tungsten (W) or copper (Cu) instead of polysilicon.

[0368] A material of the insulating layer 113 between the first wiring layer 111 and the second wiring layer 112 constituting the capacitor 110 is representatively SiO2. However, the material of the insulating layer 113 may be an insulating material such as SiON, SiN, HfO, or AlO.

[0369] The capacitor 110 disposed in the interlayer 70 can be shared by the plurality of pixels 12. Note that the photodetection element 1 according to the eleventh embodiment does not necessarily have the FD sharing structure. Accordingly, the capacitor 110 may be provided for each pixel 12.

[0370] Fig. 108 is a plan view of a lower side from an interlayer 70 of a photodetection element 1 according to a first modification example of the eleventh embodiment. The first modification example includes a floating diffusion FD and a pixel circuit 22 for each pixel 12. The capacitor 110 is disposed at a corner portion of the pixel region, and the transfer gate TG is disposed near the center of the pixel region. In the first modification example, the shared contact 73a is not provided. The second wiring layer 112 constituting the capacitor 110 is connected to the drain of the FD transfer transistor FDG in the corresponding pixel circuit 22 via a contact (solid circle) 114, and the first wiring layer 111 is connected to a contact (dashed circle) 115 that is electrically connected to the floating diffusion FD of the corresponding pixel.

[0371] Fig. 109 is a plan view of a photodetection element 1 according to a second modification example of the eleventh embodiment. In the photodetection element 1 according to the second modification example, four pixels 12 share one floating diffusion FD and one pixel circuit 22. The accumulated charges of the four photodiodes PD included in the four pixels 12 are transferred to the shared floating diffusion FD. The capacitors 110 are disposed at both ends of the shared pixel region in the second direction Y. The second wiring layer 112 constituting the capacitor 110 is connected to, for example, the drain of the FD transfer transistor FDG of the second substrate 20 via a contact (solid circle) 116. A shared contact (dashed circle) 73e is connected to the first wiring layer 111 constituting the capacitor 110.

[0372] The second modification example represents an example in which the capacitors 110 are disposed on both end sides of the pixel region in the second direction Y, but the arrangement locations of the capacitors 110 are random.

[0373] The sectional structure of the capacitor 110 disposed in the interlayer 70 is random, and it is conceivable to provide various modification examples.

[0374] Fig. 110 is a sectional view of a photodetection element 1 according to a third modification example of the eleventh embodiment. In the photodetection element 1 according to the third modification example, the first wiring layer 111, the second wiring layer 112, and the insulating layer 113 constituting the capacitor 110 disposed in the interlayer 70 are arranged at the same height in the interlayer 70.

[0375] A contact 116 extending upward is connected to the second wiring layer 112 constituting the capacitor 110 in Fig. 110. The contact 116 is electrically connected to, for example, the drain of the FD transfer transistor FDG disposed in the second substrate 20. The first wiring layer 111 of the capacitor 110 is connected to the shared contact 73e.

[0376] Fig. 111 is a sectional view of a photodetection element 1 according to a fourth modification example of the eleventh embodiment. The photodetection element 1 according to the fourth modification example includes a capacitor 110 having the stacked structure disposed in the interlayer 70. A contact 117 extending upward is connected to the second wiring layer 112 of the capacitor 110. The contact 117 is connected to a wiring layer 118 of the second substrate 20. The wiring layer 118 is connected to the drain of the FD transfer transistor FDG via another contact 119.

[0377] Fig. 112 is a sectional view of a photodetection element 1 according to a fifth modification example of the eleventh embodiment. A drain region FDD of the FD transfer transistor FDG disposed in the second substrate 20 is used as the second wiring layer 112 of the capacitor 110. By disposing the insulating layer 113 at a side wall portion of the drain region FDD, the capacitor 110 is formed in a planar direction. The first wiring layer 111 of the capacitor 110 is bent inside the interlayer 70 and is connected to the shared contact 73e. In the photodetection element 1 according to the fifth modification example, the first wiring layer 111 of the capacitor 110 can be integrated with a drain region of the FD transfer transistor FDG, and an element structure of the capacitor 110 can be simplified.

[0378] The planar layout of the second substrate 20 of the photodetection element 1 according to the eleventh embodiment is random, and it is conceivable to provide various modification examples. For example, the pixel transistors 18 such as the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD transfer transistor FDG arranged in the second substrate 20 may have a planar structure or another structure.

[0379] Fig. 113 is a plan view of a lower side from a second substrate 20 of a photodetection element 1 according to a sixth modification example of the eleventh embodiment. The photodetection element 1 according to the sixth modification example includes the amplification transistor AMP and the selection transistor SEL aligned in the second direction Y, and similarly the reset transistor RST and the FD transfer transistor FDG aligned in the second direction Y. Diffusion layers 120 for the drains and the sources are disposed below the gates of the respective pixel transistors 18. These pixel transistors 18 are shared by, for example, 2 × 2 pixels. A contact 122 extending upward from a p-type well region 121 connected to a ground node of each pixel is disposed in the second substrate 20. In Fig. 113 and the subsequent drawings, formation positions of the penetration trenches are represented by dashed lines.

[0380] Fig. 114 is a plan view of a lower side from a second substrate 20 of a photodetection element 1 according to a seventh modification example of the eleventh embodiment. The seventh modification example differs from the sixth modification example in that a planar shape of a diffusion layer 120 of the amplification transistor AMP and the selection transistor SEL is not a rectangular shape but a slit shape.

[0381] The pixel transistors 18 of the photodetection element 1 according to the eleventh embodiment may have a planar type, or may have a structure in which a fin-shaped gate is disposed in a silicon on insulator (SOI) substrate. Fig. 115 is a sectional view of the second substrate 20 in which a fin-shaped gate 123 is disposed in the SOI substrate 124. By forming the pixel transistors 18 in a fin structure, leakage current can be curbed, and a high-speed operation can be performed. In addition, a reduction in size of the pixel transistors 18 can also be realized.

[0382] In a case where one floating diffusion FD and one pixel circuit 22 are shared by a plurality of pixels, the arrangement locations and the sizes of the capacitors 110 arranged in the interlayer 70 are random.

[0383] Fig. 116 is a plan view of a lower side from a second substrate 20 of a photodetection element 1 according to an eighth modification example of the eleventh embodiment. The plan view of Fig. 116 differs from the plan view of Fig. 103 in the planar shape of the capacitor 110. In the eighth modification example illustrated in Fig. 116, the capacitor 110 having a rectangular planar shape is disposed along one side of a 2 × 2 pixel region.

[0384] Fig. 117 is a plan view of a lower side from a second substrate 20 of a photodetection element 1 according to a ninth modification example of the eleventh embodiment. An orientation of the capacitor 110 in Fig. 117 differs from an orientation of the capacitor 110 in Fig. 116 by approximately 90 degrees. In the present specification, the capacitor 110 in Fig. 116 is referred to as a vertically long capacitor, and the capacitor 110 in Fig. 117 is referred to as a horizontally long capacitor.

[0385] Fig. 118 is a plan view of a lower side from a second substrate 20 of a photodetection element 1 according to a tenth modification example of the eleventh embodiment. A capacitor 110 in Fig. 118 has an L shape obtained by combining the capacitors 110 in Figs. 116 and 117.

[0386] Fig. 119 is a plan view of a lower side from a second substrate 20 of a photodetection element 1 according to an eleventh modification example of the eleventh embodiment. In the eleventh modification example, 2 × 4 pixels share one floating diffusion FD and one pixel circuit 22. The planar shape in Fig. 119 has a planar shape obtained by adding a configuration in which the planar shapes in Fig. 103 are symmetrically arranged in the first direction X.

[0387] A connection destination of the capacitor 110 disposed in the interlayer 70 is random. Fig. 120 is a sectional view of a photodetection element 1 according to a twelfth modification example of the eleventh embodiment. In the photodetection element 1 according to the twelfth modification example, the connection destinations of the first wiring layer 111 and the second wiring layer 112 of the capacitor 110 disposed in the interlayer 70 are different from those in Fig. 107. Contacts 125 and 126 extending upward are connected to the first wiring layer 111 and the second wiring layer 112 of the capacitor 110 in Fig. 120, respectively. Connection destinations of these contacts 125 and 126 are random.

[0388] In a case where the pixel circuit 22 has a discharge (overflow) transistor, the capacitor 110 disposed in the interlayer 70 may be disposed between the drain of a discharge transistor OFL and the power supply voltage node.

[0389] Fig. 121 is a circuit diagram of a pixel circuit 22 of a photodetection element 1 according to a thirteenth modification example of the eleventh embodiment. The pixel circuit 22 according to the thirteenth modification example includes a discharge transistor OFL connected to a cathode of the photodiode PD, a capacitor 110 connected to a drain of the discharge transistor OFL and a power supply voltage node, a transfer transistor TGL, an FD transfer transistor FDG, a reset transistor RST, a transfer transistor FCG, an amplification transistor AMP, and a selection transistor SEL.

[0390] Fig. 122 is a sectional view of the photodetection element 1 according to the thirteenth modification example of the eleventh embodiment. The capacitor 110 in the pixel circuit 22 illustrated in Fig. 122 is disposed in the interlayer 70. The second wiring layer 112 of the capacitor 110 is connected to the power supply voltage node via a contact 127 extending upward. The first wiring layer 111 of the capacitor 110 is connected to the drain of the discharge transistor OFL disposed in the interlayer 70 via a contact 128 extending downward. In addition, the first wiring layer 111 is connected to the source of the transfer transistor FCG via a contact 129 extending upward.

[0391] Figs. 123A to 134A are plan views illustrating a manufacturing process of the photodetection element 1 according to the eleventh embodiment, and Figs. 123B to 134B are sectional views taken along line D-D’ of Figs. 123A to 134A. Those drawings illustrate an example in which 2 × 2 pixels share one floating diffusion FD and one pixel circuit 22.

[0392] First, as illustrated in Figs. 123A and 123B, an insulating layer 46 which is a base material of the interlayer 70 is disposed on the first substrate 10 having the photodiode PD for each pixel. The insulating layer 46 is, for example, an SiO2layer. The insulating layer 46 is disposed to cover the shared contact 73e disposed at a boundary portion of the pixel 12. The shared contact 73e is, for example, a polysilicon layer.

[0393] Next, as illustrated in Figs. 124A and 124B, the insulating layer 46 is partially removed by performing etching, and a polysilicon layer 130 is formed at a portion at which the insulating layer is removed. Then, impurity ions are implanted into the polysilicon layer 130. Therefore, the second wiring layer 112 connected to the shared contact 73e is formed.

[0394] Next, as illustrated in Figs. 125A and 125B, an interlayer insulating film 131 is formed on the polysilicon layer 130, and the insulating layer 113 is formed on the polysilicon layer 130 at the formation location of the capacitor 110, and thermal oxidation treatment is performed. Next, a polysilicon layer 132 is formed on the insulating layer 113.

[0395] Next, as illustrated in Figs. 126A and 126B, the polysilicon layer 132 is processed to form the second wiring layer 112. Thereafter, impurity ions are implanted into the second wiring layer 112. Next, as illustrated in Figs. 127A and 127B, the second substrate 20 adheres on the interlayer 70 in which the first wiring layer 111 is formed.

[0396] Next, as illustrated in Figs. 128A and 128B, a hard mask material forms a film on the second substrate 20 to pattern the second substrate 20.

[0397] Next, as illustrated in Figs. 129A and 129B, a trench is formed in the second substrate 20, an insulating layer 133 is formed on an inner wall of the trench, and a semiconductor layer 134 is embedded in the trench. In the plan views of Fig. 129A and subsequent drawings, the formation positions 145 of penetration trenches are represented by dashed lines.

[0398] Next, as illustrated in Figs. 130A and 130B, a sacrificial oxide layer 135 is formed at the arrangement locations of the gates of the pixel transistors 18 of the second substrate 20. In Fig. 130A, an embedded gate portion 146 of the pixel transistor 18 is represented by a dashed line.

[0399] Next, as illustrated in Figs. 131A and 131B, impurity ions are implanted into a channel portion 136 of the pixel transistor 18.

[0400] Next, as illustrated in Figs. 132A and 132B, the sacrificial oxide layer 135 is removed to form a gate oxide film 137, and then a polysilicon layer 138 for a gate is formed.

[0401] Next, as illustrated in Figs. 133A and 133B, impurity ions are implanted into the source and the drain of the pixel transistor 18 to form an LDD region 138, and then an insulating layer 139 is formed on a side wall of the gate. Therefore, a source region and a drain region are formed.

[0402] Next, as illustrated in Figs. 134A and 134B, a contact 141 connected to the source / drain of the pixel transistor 18 and a contact 142 connected to the first wiring layer 111 constituting the capacitor 110 are formed.

[0403] As described above, in the eleventh embodiment, since the capacitor 110 is disposed in the interlayer 70, there is no need to dispose the capacitor 110 in the first substrate 10 and the second substrate 20, and the degree of freedom in designing the first substrate 10 and the second substrate 20 is increased. A connection destination of the capacitor 110 disposed in the interlayer 70 is random. Accordingly, the capacitor 110 connected to any location of the pixel circuit 22 can be disposed in the interlayer 70.

[0404] <Application Example to Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be implemented as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, and the like.

[0405] Fig. 135 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0406] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 135, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0407] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0408] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0409] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0410] The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

[0411] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

[0412] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0413] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0414] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0415] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 135, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0416] Fig. 136 is a diagram depicting an example of the installation position of the imaging section 12031.

[0417] In Fig. 136, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0418] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0419] Incidentally, Fig. 136 depicts an example of photographing ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird’s-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0420] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of photodetection elements, or may be a photodetection element having pixels for phase difference detection.

[0421] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

[0422] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0423] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0424] An example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging section 12031 and the like, for example, among the configurations described above. Specifically, the photodetection element 1 according to each embodiment can be applied to the imaging section 12031. By applying the technology of the present disclosure to the imaging section 12031, a more easily viewable captured image can be obtained, by which fatigue of the driver can be reduced. Note that the present technology may have the following configurations.

[0425] (1) A photodetection element includes: a first substrate in which a photoelectric conversion element is disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge output from the photoelectric conversion element is disposed; and an interlayer insulating layer which is disposed between the first substrate and the second substrate and has two or more stacked wiring layers. (2) In the photodetection element according to (1), the pixel circuit in the second substrate includes a pixel transistor having at least one of an amplification transistor, a reset transistor, or a selection transistor. (3) In the photodetection element according to (1) or (2), each of the wiring layers is a polysilicon layer or a metal layer. (4) In the photodetection element according to any one of (1) to (3), the two or more wiring layers have a difference in at least one of a type and a concentration of impurity ions contained in the wiring layers. (5) In the photodetection element according to any one of (1) to (4), at least some of the two or more wiring layers are arranged to intersect with each other in a plan view. (6) In the photodetection element according to any one of (1) to (5), the two or more wiring layers include a floating diffusion to which the charge generated by the photoelectric conversion element in the first substrate is transferred, a well region of a conductivity type different from that of the floating diffusion, a transfer transistor that switches between whether or not the charge generated by the photoelectric conversion element in the first substrate is transferred to the floating diffusion, or a plurality of wiring layers all connected to at least two of pixel boundary regions of the first substrate. (7) In the photodetection element according to (6), the two or more wiring layers include two or more wiring layers arranged at respective different layers of the interlayer insulating layer and two or more wiring layers arranged at the same layer of the interlayer insulating layer. (8) In the photodetection element according to (6) or (7), the interlayer insulating layer includes a plurality of first contacts extending from at least some of the two or more wiring layers to the second substrate, and a plurality of second contacts extending from the plurality of wiring layers to the first substrate. (8-1) In the photodetection element according to any one of (1) to (7), the first substrate includes a floating diffusion to which accumulated charge of the photoelectric conversion element are transferred, a transfer transistor which switches whether or not the accumulated charge of the photoelectric conversion element are transferred to the floating diffusion, and a well region of a conductivity type different from a conductivity type of the floating diffusion, the two or more wiring layers include a first wiring layer connected to the well region, a second wiring layer connected to the floating diffusion, and a third wiring layer connected to the transfer transistor, and the first wiring layer, the second wiring layer, and the third wiring layer are arranged at respective different layers of the interlayer insulating layer. (8-2) In the photodetection element according to (8-1), the first wiring layer is disposed at a location closer to the first substrate than the second wiring layer and the third wiring layer. (8-3) The photodetection element according to (8-1) or (8-2) further includes a first contact extending from the first wiring layer to the second substrate, in which the first contact is disposed in a pixel region or outside the pixel region, and the well region is set to a predetermined potential via the first contact. (9) In the photodetection element according to any one of (1) to (8), the interlayer insulating layer includes charge accumulators that accumulate charge transferred from the photoelectric conversion element independently of the floating diffusion, and each of the charge accumulators has two wiring layers disposed facing each other among the two or more wiring layers. (10) The photodetection element according to (9) further includes conversion efficiency switching transistors that switch photoelectric conversion efficiency, in which each of the charge accumulators accumulates charge transferred from the photoelectric conversion element when the conversion efficiency switching transistors are turned on. (11) The photodetection element according to (10) further includes a third contact extending to the second substrate from a wiring layer disposed on a side close to the second substrate of the two wiring layers constituting each of the charge accumulators, in which the wiring layer disposed on the side close to the second substrate is electrically connected via the third contact to sources of the conversion efficiency switching transistors. (12) In the photodetection element according to (10) or (11), a plurality of the conversion efficiency switching transistors and a plurality of the charge accumulators capable of switching photoelectric conversion efficiency in three or more levels are provided, and the plurality of charge accumulators is arranged in the interlayer insulating layer, or some of the plurality of charge accumulators are arranged in the interlayer insulating layer such that the rest of charge accumulators are arranged in the second substrate. (12-1) In the electronic device according to any one of (9) to (12), each of the charge accumulators is disposed in a comb-teeth shape in a plan view. (12-2) In the photodetection element according to any one of (9) to (12), the first substrate includes a floating diffusion to which accumulated charge of the photoelectric conversion element are transferred, a transfer transistor which switches whether or not the accumulated charge of the photoelectric conversion element are transferred to the floating diffusion, and a well region of a conductive type different from a conductive type of the floating diffusion, the two or more wiring layers include a first wiring layer connected to the transfer transistor and a second wiring layer connected to the well region, and the two wiring layers constituting each of the charge accumulators are arranged in parallel with at least one of the first wiring layer or the second wiring layer. (13) In the photodetection element according to any one of (1) to (12), at least one wiring layer of the two or more wiring layers is a light-shielding layer that shields light having passed through the photoelectric conversion element and shields light from the second substrate. (14) In the photodetection element according to (13), the light-shielding layer is set to a predetermined reference potential. (15) In the photodetection element according to (13) or (14), the light-shielding layer and a wiring layer disposed at a layer different from the light-shielding layer among the two or more wiring layers are arranged to cover the entire region of the first substrate in a plan view. (16) In the photodetection element according to (15), an area of the light-shielding layer among the two or more wiring layers is larger than an area of the wiring layer disposed at a layer different from the light-shielding layer. (17) In the photodetection element according to any one of (13) to (16), the light-shielding layer has a solid pattern, a mesh-shaped pattern, or a slit-shaped pattern. (17-1) In the photodetection element according to any one of (13) to (17), the light-shielding layer is connected to the well region of the first substrate via a contact. (17-2) In the photodetection element according to any one of (13) to (17), the light-shielding layer is connected to a first well region of the first substrate and a second well region of the second substrate via respective separate contacts. (17-3) In the photodetection element according to any one of (13) to (17), one floating diffusion is shared by a pixel group including two or more pixels, and the light-shielding layer is set to a predetermined potential via a contact disposed in the pixel group in a unit of pixel group. (17-4) In the photodetection element according to any one of (13) to (17), one floating diffusion is shared by a pixel group including two or more pixels, and the light-shielding layer is set to a predetermined potential via contacts disposed at end portions of the first substrate and the second substrate. (17-5) In the photodetection element according to any one of (13) to (17), the two or more wiring layers include two or more of the light-shielding layers disposed at respective different layers of the interlayer insulating layer. (17-6) In the photodetection element according to (17-5), the two or more light-shielding layers are set to the same potential. (17-7) In the photodetection element according to (17-5), at least one of the two or more light-shielding layers can have a variable potential, and the two or more light-shielding layers are set to the same potential when a charge is transferred to the floating diffusion of the first substrate. (18) A photodetection element includes: a first substrate in which a photoelectric conversion element is disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge output from the photoelectric conversion element is disposed; and an interlayer insulating layer which is disposed between the first substrate and the second substrate and has one or more wiring layers, in which the wiring layers contain arsenic (As) and phosphorus (P). (19) In the photodetection element according to (18), a concentration of arsenic (As) in the wiring layers is higher than a concentration of phosphorus (P). (19-1) In the photodetection element according to (18) or (19), the first substrate includes a floating diffusion to which accumulated charge of the photoelectric conversion element are transferred, and a transfer transistor which switches whether or not the accumulated charge of the photoelectric conversion element are transferred to the floating diffusion, the one or more wiring layers include a first wiring layer connected to the floating diffusion, and a second wiring layer connected to the transfer transistor, and the first wiring layer and the second wiring layer have respective different impurity concentrations. (19-2) In the photodetection element according to (19-1), a concentration of arsenic (As) in the first wiring layer is higher than a concentration of arsenic (As) in the second wiring layer. (19-3) In the photodetection element according to (19-1), a concentration of phosphorus (P) in the first wiring layer is lower than a concentration of phosphorus (P) in the second wiring layer. (19-4) In the photodetection element according to any one of (19-1) to (19-3), a concentration of arsenic (As) in each of the first wiring layer and the second wiring layer is higher than a concentration of phosphorus (P) therein. (19-5) In the photodetection element according to any one of (19-1) to (19-4), the one or more wiring layers include a third wiring layer connected to a surrounding region disposed outside the pixel region, and the first wiring layer and the third wiring layer have respective different impurity concentrations. (19-6) In the photodetection element according to (19-5), the concentration of arsenic (As) in the first wiring layer is higher than a concentration of arsenic (As) in the third wiring layer. (19-7) In the photodetection element according to (19-5), the concentration of phosphorus (P) in the first wiring layer is lower than a concentration of phosphorus (P) in the third wiring layer. (19-8) In the photodetection element according to any one of (19-5) to (19-7), a concentration of arsenic (As) in each of the first wiring layer and the third wiring layer is higher than a concentration of phosphorus (P) therein. (20) A photodetection element includes: a first substrate in which a photoelectric conversion element is disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge output from the photoelectric conversion element is disposed; and an interlayer insulating layer disposed between the first substrate and the second substrate, in which the interlayer insulating layer has a wiring layer, a first contact extending from the wiring layers to the second substrate, and an insulating layer disposed in a predetermined region having a connection portion with the first contact in the wiring layers. (21) In the photodetection element according to (20), the first contact is electrically insulated from the wiring layer. (22) In the photodetection element according to (20) or (21), the insulating layer contains two or more kinds of insulants having different dielectric constants. (23) In the photodetection element according to (22), the insulating layer includes an air layer disposed to surround the first contact. (24) In the photodetection element according to (23), the insulating layer includes a first insulating layer which is disposed to surround the first contact at a location closer to the first contact than the air layer and contains an insulant having a dielectric constant higher than that of the air layer, and a second insulating layer which is disposed to surround the first contact at a location farther apart from the first contact than the air layer and contains an insulant having a dielectric constant higher than that of the air layer. (25) In the photodetection element according to (20) or (21), the insulating layer contains a low-k material. (26) The photodetection element according to any one of (21) to (25) further includes a side wall insulating layer that is disposed along a side wall surface of the first contact extending from the interlayer to the second substrate and contains a low-k material. (27) In the photodetection element according to any one of (20) to (26), the wiring layer is disposed over an entire horizontal cross section of the interlayer insulating layer. (28) In the photodetection element according to any one of (20) to (26), the wiring layer is disposed in a partial region of a cross section of the interlayer insulating layer. (29) In the photodetection element according to any one of (20) to (26), the interlayer insulating layer has a second contact which is disposed apart from the first contact and extends from the wiring layer to the second substrate. (30) In the photodetection element according to (29), the second contact is disposed to be electrically connected to the wiring layer and is set to a predetermined potential. (31) In the photodetection element according to any one of (20) to (30), the wiring layer contains a metal material, a semiconductor material, or an organic material. (32) In the photodetection element according to (31), the wiring layer contains polysilicon. (33) In the photodetection element according to any one of (1) to (32), the interlayer insulating layer includes a silicon oxide film or a silicon nitride film. (34) A photodetection element includes: a first substrate on which a photoelectric conversion element and a floating diffusion are disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge transferred from the photoelectric conversion element is disposed; and an interlayer insulating layer which is disposed between the first substrate and the second substrate and has two or more wiring layers, in which the two or more wiring layers include a first wiring layer that is electrically connected to the floating diffusion, and a second wiring layer that is disposed at a distance from the first wiring layer to cause capacitive coupling and boosts a potential of the first wiring layer. (35) In the photodetection element according to (34), a potential of the second wiring layer is boosted in synchronization with a timing when a transfer transistor is turned on, the transfer transistor transferring, to the floating diffusion, an accumulated charge due to photoelectric conversion of the photoelectric conversion element. (36) In the photodetection element according to (35), the second wiring layer is set to a first potential when the transfer transistor is turned on, and is set to a second potential lower than the first potential after the transfer transistor is turned off. (37) In the photodetection element according to any one of (34) to (36), the first wiring layer and the second wiring layer are disposed at the same height in the interlayer insulating layer. (38) In the photodetection element according to any one of (34) to (37), each of the first wiring layer and the second wiring layer has a rectangular shape in a plan view, and the first wiring layer and the second wiring layer are disposed such that either one side of rectangles faces each other in a plan view. (39) In the photodetection element according to any one of (34) to (37), the first wiring layer has a rectangular shape in a plan view, and the second wiring layer has a bent shape in a plan view. (40) In the photodetection element according to (39), the second wiring layer is disposed to surround at least a part of the first wiring layer in a plan view. (41) In the photodetection element according to (39), the second wiring layer is disposed to be bent toward a side opposite to an arrangement location of the first wiring layer in a plan view. (42) In the photodetection element according to (39), a plurality of the second wiring layers is provided, some of the second wiring layers are disposed to surround at least a part of the first wiring layer in a plan view, and the remaining second wiring layers are disposed to be bent toward a side opposite to an arrangement location of the first wiring layer in a plan view. (43) In the photodetection element according to any one of (34) to (37), the first wiring layer has a bent shape in a plan view, and the second wiring layer has a rectangular shape in a plan view. (44) In the photodetection element according to (43), the first wiring layer is disposed to surround at least a part of the second wiring layer in a plan view. (45) In the photodetection element according to any one of (34) to (44), the two or more wiring layers include a third wiring layer stacked on the second wiring layer at a distance, a fourth wiring layer stacked on the first wiring layer at a distance, a first conductive member that electrically connects the second wiring layer and the third wiring layer, and a second conductive member that electrically connects the first wiring layer and the fourth wiring layer. (46) In the photodetection element according to (45), the third wiring layer and the fourth wiring layer are disposed at the same height in the interlayer insulating layer. (47) In the photodetection element according to (45) or (46), each of the third wiring layer and the fourth wiring layer has a rectangular shape in a plan view, and the third wiring layer and the fourth wiring layer are disposed such that either one side of rectangles faces each other in a plan view. (48) In the photodetection element according to any one of (34) to (44), the two or more wiring layers include a third wiring layer stacked on the second wiring layer at a distance, a first conductive member that electrically connects the second wiring layer and the third wiring layer, and a second conductive member extending upward from the first wiring layer, in which the third wiring layer is disposed to surround the second conductive member in a plan view. (49) In the photodetection element according to any one of (34) to (44), the two or more wiring layers include a third wiring layer stacked on the first wiring layer at a distance, a first conductive member that electrically connects the first wiring layer and the third wiring layer, and a fourth wiring layer that is disposed at the same height as the third wiring layer and is set to a predetermined potential. (50) In the photodetection element according to (49), the third wiring layer and the fourth wiring layer are disposed at a height between the first wiring layer and the floating diffusion. (51) A photodetection element includes: a first substrate on which a photoelectric conversion element and a floating diffusion are disposed; a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge transferred from the photoelectric conversion element is disposed; and an interlayer insulating layer which is disposed between the first substrate and the second substrate and has a capacitor. (52) In the photodetection element according to (51), the interlayer insulating layer includes a first wiring layer and a second wiring layer disposed to face each other, and an insulating layer disposed between facing surfaces of the first wiring layer and the second wiring layer. (53) In the photodetection element according to (52), the first wiring layer and the second wiring layer are polysilicon layers, and the insulating layer is a silicon oxide layer. (54) In the photodetection element according to (53), the first wiring layer is a first polysilicon layer first conductivity-type containing impurity ions, and the second wiring layer is a second polysilicon layer containing second conductivity-type impurity ions. (55) The photodetection element according to any one of (52) to (54) further includes a floating diffusion to which an accumulated charge due to photoelectric conversion of the photoelectric conversion element is transferred; a reset transistor that discharges the charge transferred to the floating diffusion; and a conversion efficiency switching transistor that switches photoelectric conversion efficiency of the photoelectric conversion element, in which the first wiring layer is electrically connected to the floating diffusion, and the second wiring layer is electrically connected to a connection node between the conversion efficiency switching transistor and the reset transistor. (56) In the photodetection element according to any one of (52) to (55), the first wiring layer, the insulating layer, and the second wiring layer are closely disposed at the same height of the interlayer insulating layer. (57) In the photodetection element according to any one of (52) to (55), the first wiring layer, the insulating layer, and the second wiring layer are stacked in the interlayer insulating layer. (58) In the photodetection element according to (55), the second substrate includes the reset transistor and the conversion efficiency switching transistor, and the first wiring layer is disposed to be in contact with a drain of the conversion efficiency switching transistor. (59) In the photodetection element according to any one of (52) to (58), a plurality of pixels having the respective photoelectric conversion elements shares the capacitor and the floating diffusion, and the first wiring layer is electrically connected to the shared floating diffusion. (60) In the photodetection element according to any one of (52) to (58), the capacitor and the floating diffusion are provided for each pixel, and the first wiring layer is electrically connected to the corresponding floating diffusion. (61) The photodetection element according to any one of (52) to (54) further includes a discharge transistor that discharges a charge overflowing from the photoelectric conversion element, the first wiring layer is electrically connected to a drain of the discharge transistor, and the second wiring layer is electrically connected to a reference voltage node. (62) In the photodetection element according to any one of (51) to (61), the pixel circuit disposed in the second substrate includes a pixel transistor having a silicon oxide insulator (SOI) substrate and a fin gate. (63)　　　　　A photodetection element comprising: a first substrate including a photoelectric conversion element;a second substrate including at least a part of a pixel circuit that generates a pixel signal according to charge output from the photoelectric conversion element; and an interlayer insulating layer between the first substrate and the second substrate, the interlayer insulating layer including two or more wiring layers. (64)　　　　　The photodetection element according to (63), wherein the pixel circuit includes at least one of an amplification transistor, a reset transistor, or a selection transistor. (65)　　　　　The photodetection element according to any one of (63) to (64), wherein the two or more wiring layers comprise polysilicon layer or metal. (66)　　　　　The photodetection element according to any one of (63) to (35), wherein the two or more wiring layers differ in at least one of a type and a concentration of impurities. (67)　　　　　The photodetection element according to any one of (33) to (36), wherein at least some of the two or more wiring layers intersect with each other in a plan view. (68)　　　　　The photodetection element according to any one of (63) to (67), wherein the two or more wiring layers include a floating diffusion to which the charge generated by the photoelectric conversion element is transferred, a well region of a conductivity type different from that of the floating diffusion, a transfer transistor that controls transfer of the charge generated by the photoelectric conversion element to the floating diffusion, or a plurality of wiring layers connected to at least two pixel boundary regions of the first substrate. (69) The photodetection element according to any one of (63) to (68), wherein the two or more wiring layers include multiple wirings arranged at respective different levels within the interlayer insulating layer and multiple wirings arranged at a same level within the interlayer insulating layer. (70)　　　　　The photodetection element according to any one of (63) to (69), wherein the interlayer insulating layer includes: a plurality of first contacts extending between at least some of the two or more wiring layers and the second substrate; and a plurality of second contacts extending between at least some of the two or more wiring layers and the first substrate. (71)　　　　　The photodetection element according to any one of (63) to (70), wherein: 　　　　　　the two or more wiring layers include a floating diffusion to which the charge generated by the photoelectric conversion element is transferred; the interlayer insulating layer includes a capacitance to store charge transferred from the photoelectric conversion element independently of the floating diffusion; and the capacitance is formed by first and second wiring layers arranged to face each other within the two or more wiring layers. (72)　　　　　The photodetection element according to any one of (63) to (71), further comprising a transistor that switches photoelectric conversion efficiency, wherein the capacitance stores a charge transferred from the photoelectric conversion element when the transistor is turned on. (73) The photodetection element according to any one of (63) to (72), further comprising a via extending between the second substrate and the first wiring layer, wherein the via electrically connects the first wiring layer and a source of the transistor. (74)　　　　　The photodetection element according to any one of (63) to (73), further comprising: a plurality of transistors and a plurality of capacitances capable of switching photoelectric conversion efficiency, wherein some of the capacitances are arranged in the interlayer insulating layer and some of the capacitances are arranged in the second substrate. (75) The photodetection element according to any one of (63) to (74), wherein at least one wiring layer of the two or more wiring layers is positioned between the photoelectric conversion element and a transistor of the pixel circuit included in the second substrate. (76)　　　　　The photodetection element according to any one of (63) to (75), wherein the at least one wiring layer is set to a predetermined reference potential. (77)　　　　　The photodetection element according to any one of (63) to (76), wherein the at least one wiring layer and a wiring layer at a level different from the at least one wiring layer are arranged to cover the entire region of the first substrate in a plan view. (78) The photodetection element according to any one of (63) to (77), wherein an area of the at least one wiring layer is larger than an area of the wiring layer at the different level. (79) The photodetection element according to any one of (63) to (78), wherein the at least one wiring layer has a solid pattern, a mesh-shaped pattern, or a slit-shaped pattern. (80)　　　　　A photodetection element comprising: a first substrate including a photoelectric conversion element; a second substrate including at least a part of a pixel circuit that generates a pixel signal according to charge output from the photoelectric conversion element; and an interlayer insulating layer between the first substrate and the second substrate, the interlayer insulating layer including one or more wiring layers, wherein at least one wiring layer of the one or more wiring layers comprises arsenic (As) and phosphorus (P). (81) The photodetection element according to claim 18, wherein a concentration of arsenic (As) in the at least one wiring layer is higher than a concentration of phosphorus (P). (82)　　　　　A photodetection element comprising: a first substrate including a photoelectric conversion element; a second substrate including at least a part of a pixel circuit that generates a pixel signal according to charge output from the photoelectric conversion element; and an interlayer insulating layer between the first substrate and the second substrate, wherein the interlayer insulating layer comprises: a wiring layer; an insulating layer; and a first via extending between the wiring layer and the second substrate, wherein the first via passes through the insulating layer.

[0426] Aspects of the present disclosure are not limited to the above-described individual embodiments, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, modifications, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the matters defined in the claims and equivalents thereof.

[0427] 1　　　　　　Photodetection element 10　　　　　　First substrate 11　　　　　　Semiconductor substrate 12　　　　　　Pixel 15　　　　　　Charge retainer 15a　　　　　　First charge retainer 15b　　　　　　Second charge retainer 16　　　　　　Wiring layer 18　　　　　　Pixel transistor 20　　　　　　Second substrate 20a　　　　　　Wiring layer 20b　　　　　　Contact 20c　　　　　　Silicon substrate 20d　　　　　　Well layer 20f　　　　　　Trench 20g　　　　　　Trench 20h　　　　　　Trench 21　　　　　　Semiconductor substrate (chip) 21c　　　　　　Contact 22　　　　　　Pixel circuit 23　　　　　　Pixel drive line 24　　　　　　Vertical signal line 25　　　　　　Gate 27　　　　　　Side contact 29　　　　　　Insulating layer 30　　　　　　Third substrate 31　　　　　　Semiconductor substrate 32　　　　　　Logic circuit 33　　　　　　Vertical drive circuit 34　　　　　　Column signal processing circuit 35　　　　　　Horizontal drive circuit 36　　　　　　System control circuit 38　　　　　　Trench 39　　　　　　Metal wiring 40　　　　　　Color filter 42　　　　　　Well layer 43　　　　　　Element isolation portion 43a　　　　　　Insulating layer 43b　　　　　　Diffusion layer 46　　　　　　Insulating layer 47　　　　　　Resist layer 50　　　　　　Light-receiving lens 51　　　　　　Interlayer insulating layer 52　　　　　　Insulating layer 53　　　　　　Insulating layer 54　　　　　　Penetration wiring 55　　　　　　Connection wiring 56　　　　　　Wiring layer 57　　　　　　Insulating layer 58　　　　　　Pad electrode 59　　　　　　Connection portion 61　　　　　　Interlayer insulating layer 62　　　　　　Wiring layer 63　　　　　　Insulating layer 64　　　　　　Pad electrode 65　　　　　　Opening portion 66　　　　　　Insulating layer 66a　　　　　　First insulating layer 66b　　　　　　Second insulating layer 66s　　　　　　Side wall insulating layer 67　　　　　　Air layer 68　　　　　　Resist layer 69　　　　　　Silicon oxide film 70　　　　　　Interlayer insulating layer (interlayer) 71　　　　　　Wiring layer 71a　　　　　　Wiring layer (first wiring layer) 71b　　　　　　Second wiring layer 71c　　　　　　Third wiring layer 71d　　　　　　Wiring layer 71h　　　　　　Opening portion 71p　　　　　　Polysilicon layer 72　　　　　　Penetration contact 73　　　　　　Contact 73a　　　　　　First Contact 73b　　　　　　Second contact 73c　　　　　　Third contact 74　　　　　　Empty region 76　　　　　　Organic film 77　　　　　　Resist layer 82　　　　　　NSG layer 83　　　　　　Organic layer 87　　　　　　Organic layer 89　　　　　　Resist layer 94　　　　　　Organic layer 96　　　　　　Resist layer 100　　　　　　Photodetection element 101　　　　　　FDB capacitance unit 102　　　　　　FDB wiring layer 103　　　　　　Shield wiring layer 110　　　　　　Capacitor 111　　　　　　First wiring layer 112　　　　　　Second wiring layer 113　　　　　　Insulating layer 115 to 117　　Contact 118　　　　　　Wiring layer 119　　　　　　Contact 120　　　　　　Diffusion layer 121　　　　　　p-type well region 122　　　　　　Contact 123　　　　　　Gate 124　　　　　　SOI substrate 125 to 129　　Contact 130　　　　　　Polysilicon layer 131　　　　　　Interlayer insulating film 132　　　　　　Polysilicon layer 133　　　　　　Insulating layer 134　　　　　　Semiconductor layer 135　　　　　　Sacrificial oxide layer 135　　　　　　Sacrificial oxide layer 136　　　　　　Channel portion 137　　　　　　Gate oxide film 138　　　　　　LDD region 138　　　　　　Polysilicon layer 139　　　　　　Insulating layer 141　　　　　　Contact 142　　　　　　Contact 146　　　　　　Gate unit

Claims

1. A photodetection element comprising: 　　　　　　　a first substrate including a photoelectric conversion element; 　　　　　　　a second substrate including at least a part of a pixel circuit that generates a pixel signal according to charge output from the photoelectric conversion element; and 　　　　　　　an interlayer insulating layer between the first substrate and the second substrate, the interlayer insulting layer including two or more wiring layers.

2. The photodetection element according to claim 1, wherein 　　　　　　　the pixel circuit includes at least one of an amplification transistor, a reset transistor, or a selection transistor.

3. The photodetection element according to claim 1, wherein 　　　　　　　the two or more wiring layers comprise polysilicon layer or metal.

4. The photodetection element according to claim 1, wherein 　　　　　　　the two or more wiring layers differ in at least one of a type and a concentration of impurities.

5. The photodetection element according to claim 1, wherein 　　　　　　　at least some of the two or more wiring layers intersect with each other in a plan view.

6. The photodetection element according to claim 1, wherein the two or more wiring layers include a floating diffusion to which the charge generated by the photoelectric conversion element is transferred, a well region of a conductivity type different from that of the floating diffusion, a transfer transistor that controls transfer of the charge generated by the photoelectric conversion element to the floating diffusion, or a plurality of wiring layers connected to at least two pixel boundary regions of the first substrate.

7. The photodetection element according to claim 1, wherein the two or more wiring layers include multiple wirings arranged at respective different levels within the interlayer insulating layer and multiple wirings arranged at a same level within the interlayer insulating layer.

8. The photodetection element according to claim 1, wherein the interlayer insulating layer includes: 　　　　　　　a plurality of first contacts extending between at least some of the two or more wiring layers and the second substrate; and 　　　　　　　a plurality of second contacts extending between at least some of the two or more wiring layers and the first substrate.

9. The photodetection element according to claim 1, wherein: 　　　　　　　the two or more wiring layers include a floating diffusion to which the charge generated by the photoelectric conversion element is transferred; 　　　　　　　the interlayer insulating layer includes a capacitance to store charge transferred from the photoelectric conversion element independently of the floating diffusion; and 　　　　　　　the capacitance is formed by first and second wiring layers arranged to face each other within the two or more wiring layers.

10. The photodetection element according to claim 9, further comprising a transistor that switches photoelectric conversion efficiency, wherein 　　　　　　　the capacitance stores a charge transferred from the photoelectric conversion element when the transistor is turned on.

11. The photodetection element according to claim 10, further comprising a via extending between the second substrate and the first wiring layer, wherein 　　　　　　　the via electrically connects the first wiring layer and a source of the transistor.

12. The photodetection element according to claim 1, further comprising: 　　　　　　　a plurality of transistors and a plurality of capacitances capable of switching photoelectric conversion efficiency, wherein some of the capacitances are arranged in the interlayer insulating layer and some of the capacitances are arranged in the second substrate.

13. The photodetection element according to claim 1, wherein at least one wiring layer of the two or more wiring layers is positioned between the photoelectric conversion element and a transistor of the pixel circuit included in the second substrate.

14. The photodetection element according to claim 13, wherein 　　　　　　　the at least one wiring layer is set to a predetermined reference potential.

15. The photodetection element according to claim 13, wherein 　　　　　　　the at least one wiring layer and a wiring layer at a level different from the at least one wiring layer are arranged to cover the entire region of the first substrate in a plan view.

16. The photodetection element according to claim 15, wherein 　　　　　　　an area of the at least one wiring layer is larger than an area of the wiring layer at the different level.

17. The photodetection element according to claim 13, wherein 　　　　　　　the at least one wiring layer has a solid pattern, a mesh-shaped pattern, or a slit-shaped pattern.

18. A photodetection element comprising: 　　　　　　　a first substrate including a photoelectric conversion element; 　　　　　　　a second substrate including at least a part of a pixel circuit that generates a pixel signal according to charge output from the photoelectric conversion element; and 　　　　　　　an interlayer insulating layer between the first substrate and the second substrate, the interlayer insulating layer including one or more wiring layers, wherein 　　　　　　　at least one wiring layer of the one or more wiring layers comprises arsenic (As) and phosphorus (P).

19. The photodetection element according to claim 18, wherein a concentration of arsenic (As) in the at least one wiring layer is higher than a concentration of phosphorus (P).

20. A photodetection element comprising: 　　　　　　　a first substrate including a photoelectric conversion element; 　　　　　　　a second substrate including at least a part of a pixel circuit that generates a pixel signal according to charge output from the photoelectric conversion element; and 　　　　　　　an interlayer insulating layer between the first substrate and the second substrate, wherein the interlayer insulating layer comprises: 　　　　　　　　　　　a wiring layer; 　　　　　　　　　　　an insulating layer; and 　　　　　　　　　　　a first via extending between the wiring layer and the second substrate, wherein the first via passes through the insulating layer.

21. A photodetection element comprising: 　　　　　　　a first substrate on which a photoelectric conversion element and a floating diffusion are disposed; 　　　　　　　a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge transferred from the photoelectric conversion element is disposed; and 　　　　　　　an interlayer insulating layer which is disposed between the first substrate and the second substrate and has two or more wiring layers, wherein 　　　　　　　the two or more wiring layers include 　　　　　　　a first wiring layer that is electrically connected to the floating diffusion, and 　　　　　　　a second wiring layer that is disposed at a distance from the first wiring layer to cause capacitive coupling and boosts a potential of the first wiring layer.

22. A photodetection element comprising: 　　　　　　　a first substrate on which a photoelectric conversion element and a floating diffusion are disposed; 　　　　　　　a second substrate which is stacked on the first substrate and in which at least a part of a pixel circuit that generates a pixel signal according to a charge transferred from the photoelectric conversion element is disposed; and 　　　　　　　an interlayer insulating layer which is disposed between the first substrate and the second substrate and has a capacitor.

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