Display device

Abstract

The present invention provides a display device comprising: a plurality of island units spaced apart from each other; first bridge units which connect island units adjacent to each other in a first direction among the plurality of island units and include a first voltage line, a second voltage line, and a third voltage line; and second bridge units which connect island units adjacent to each other in a second direction crossing the first direction among the plurality of island units, and include a fourth voltage line electrically connected to the first voltage line, a fifth voltage line electrically connected to the second voltage line, and a sixth voltage line electrically connected to the third voltage line, wherein the first voltage line and the fourth voltage line are disposed on a first conductive layer, and the second voltage line, the fifth voltage line, the third voltage line, and the sixth voltage line are disposed on a second conductive layer on the first conductive layer.

Description

display device

[0001] Embodiments of the present invention relate to a flexible display device, for example, a stretchable display device.

[0002] As display devices that visually display electrical signals evolve, a variety of display devices with superior characteristics, such as thinness, lightness, and low power consumption, are being introduced. For example, flexible display devices that can be folded or rolled are being introduced. Recently, active research and development is underway on stretchable display devices capable of transforming into various forms.

[0003] Embodiments of the present invention provide a flexible display device, for example, a stretchable display device.

[0004] According to one aspect of the present invention, a stretchable display device is provided, comprising a plurality of mutually spaced island portions, first bridge portions connecting island portions adjacent in a first direction among the plurality of island portions and including a first voltage line, a second voltage line, and a third voltage line, and second bridge portions connecting island portions adjacent in a second direction intersecting the first direction among the plurality of island portions and including a fourth voltage line electrically connected to the first voltage line, a fifth voltage line electrically connected to the second voltage line, and a sixth voltage line electrically connected to the third voltage line, wherein the first voltage line and the fourth voltage line are disposed on a first conductive layer, and the second voltage line, the fifth voltage line, the third voltage line, and the sixth voltage line are disposed on a second conductive layer on the first conductive layer.

[0005] In one embodiment, the first voltage line and the fourth voltage line may extend into the plurality of islands and be connected to each other.

[0006] In one embodiment, the first voltage line may have a first width in a direction perpendicular to the extension direction of the first voltage line, and the fourth voltage line may have a second width greater than the first width in a direction perpendicular to the extension direction of the fourth voltage line.

[0007] In one embodiment, the second bridge portions may include only the fourth voltage line among the fourth voltage line, the fifth voltage line, and the sixth voltage line in the first conductive layer.

[0008] In one embodiment, the first bridge portions further include a first initialization voltage line and a second initialization voltage line, and the first initialization voltage line and the second initialization voltage line can be arranged on the first conductive layer.

[0009] In one embodiment, each of the plurality of islands includes voltage connection lines, and the second voltage line and the fifth voltage line can be electrically connected through the voltage connection lines within the plurality of islands.

[0010] In one embodiment, the voltage connection lines may be arranged in a different layer from the second voltage line and the fifth voltage line.

[0011] In one embodiment, the voltage connection lines include first voltage connection lines and second voltage connection lines extending in the first direction, and third voltage connection lines extending in the second direction, wherein the first voltage connection line and the second voltage connection line are disposed on the first conductive layer, and the third voltage connection line may be disposed on a third conductive layer interposed between the first conductive layer and the second conductive layer.

[0012] In one embodiment, the second voltage line and the fifth voltage line are connected to some of the third voltage connection lines, and each of the third voltage connection lines can be connected to the first voltage connection line and the second voltage connection line.

[0013] In one embodiment, the third voltage line and the sixth voltage line may extend into the plurality of islands and be connected to each other.

[0014] In one embodiment, the second voltage line and the fifth voltage line may have a third width in a direction perpendicular to their respective extension directions, and the third voltage line and the sixth voltage line may have a fourth width smaller than the third width in a direction perpendicular to their respective extension directions.

[0015] In one embodiment, the fourth voltage line may have a second width greater than the fourth width in a direction perpendicular to the extension direction of the fourth voltage line.

[0016] In one embodiment, each of the plurality of islands further includes a light-emitting element and a first electrode pad electrically connected to a first electrode of the light-emitting element and a second electrode pad electrically connected to a second electrode of the light-emitting element, wherein the first electrode pad and the second electrode pad can be disposed on a fourth conductive layer on the second conductive layer.

[0017] In one embodiment, each of the plurality of islands includes a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element, and the pixel driving circuit may include a driving transistor having a gate, a first terminal electrically connected to a first node, and a second terminal, a data writing transistor electrically connected to the first node and a data line, a first compensation transistor electrically connected to the gate of the driving transistor and the second terminal of the driving transistor, a first light-emitting control transistor electrically connected to the first node and the second node, a second light-emitting control transistor electrically connected to the light-emitting element and the second terminal of the driving transistor, a third light-emitting control transistor electrically connected to the second node and a driving voltage line, a second compensation transistor electrically connected to the second node and a sustain voltage line, a storage capacitor electrically connected to the second node and the gate of the driving transistor, and an auxiliary capacitor electrically connected to the sustain voltage line and a first electrode of the light-emitting element.

[0018] In one embodiment, the maintenance voltage line may include the first voltage line and the fourth voltage line.

[0019] In one embodiment, the auxiliary capacitor includes a first electrode and a second electrode overlapping the first electrode in a plane, and the first voltage line and the fourth voltage line can be electrically connected to the second electrode.

[0020] In one embodiment, the second electrode of the auxiliary capacitor may be electrically connected to the first electrode of the light emitting element.

[0021] In one embodiment, the driving voltage line may include the second voltage line and the fifth voltage line.

[0022] In one embodiment, the second electrode of the light emitting element is electrically connected to a common voltage line, and the common voltage line may include the third voltage line and the sixth voltage line.

[0023] In one embodiment, each of the plurality of island portions further includes a first electrode pad electrically connected to a first electrode of the light-emitting element and a second electrode pad electrically connected to a second electrode of the light-emitting element, and the third voltage line and the sixth voltage line can extend into the plurality of island portions and be connected to the second electrode pad.

[0024] Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

[0025] According to one embodiment of the present invention, a display device can be provided that prevents damage due to concentrated stress and can be stretched in various directions. These effects are exemplary, and the scope of the present invention is not limited by the aforementioned effects.

[0026] FIG. 1 is a perspective view schematically illustrating a stretchable display device according to one embodiment of the present invention.

[0027] FIG. 2a and FIG. 2b are perspective views showing the stretchable display device of FIG. 1 stretched in the first direction.

[0028] Fig. 2c is a perspective view showing the stretchable display device of Fig. 1 stretched in the second direction.

[0029] FIG. 2d is a perspective view showing the stretchable display device of FIG. 1 stretched in the first direction and the second direction.

[0030] FIG. 2e is a perspective view showing the stretchable display device of FIG. 1 stretched in a third direction.

[0031] FIG. 3 is a schematic plan view of a stretchable display device according to one embodiment of the present invention.

[0032] FIG. 4A is an enlarged plan view of part IV of FIG. 3 as part of a stretchable display device according to one embodiment of the present invention.

[0033] FIG. 4b is an enlarged plan view of part IV of FIG. 3 as part of a stretchable display device according to one embodiment of the present invention.

[0034] FIG. 4c is an enlarged plan view of part IV of FIG. 3 as part of a stretchable display device according to one embodiment of the present invention.

[0035] FIG. 5 is a cross-sectional view schematically showing a first island portion and a first bridge portion arranged in a display area of ​​a stretchable display device according to one embodiment of the present invention.

[0036] FIGS. 6A to 6C are equivalent circuit diagrams of subpixels of a stretchable display device according to one embodiment of the present invention, respectively.

[0037] FIG. 7a and FIG. 7b are cross-sectional views schematically showing a light-emitting element of a stretchable display device according to one embodiment of the present invention, respectively.

[0038] FIGS. 8A to 8F are layer-by-layer layout diagrams schematically illustrating an island portion of a stretchable display device according to one embodiment of the present invention.

[0039] FIG. 9A is a layout diagram schematically illustrating a third conductive layer of a stretchable display device according to one embodiment of the present invention.

[0040] FIGS. 9b and 9c are layout diagrams schematically illustrating a portion of a third conductive layer of a stretchable display device according to one embodiment of the present invention.

[0041] FIG. 9d is a layout diagram schematically illustrating a sustain voltage line of a stretchable display device according to one embodiment of the present invention.

[0042] FIG. 10A is a layout diagram schematically illustrating a fourth conductive layer of a stretchable display device according to one embodiment of the present invention.

[0043] FIGS. 10b and 10c are layout diagrams schematically illustrating a portion of a fourth conductive layer of a stretchable display device according to one embodiment of the present invention.

[0044] FIG. 11A is a layout diagram schematically illustrating a fifth conductive layer of a stretchable display device according to one embodiment of the present invention.

[0045] FIGS. 11b and 11c are layout diagrams schematically illustrating a portion of a fifth conductive layer of a stretchable display device according to one embodiment of the present invention.

[0046] FIG. 11d is a layout diagram schematically illustrating a driving voltage line of a stretchable display device according to one embodiment of the present invention.

[0047] FIG. 11e is a layout diagram schematically illustrating a common voltage line of a stretchable display device according to one embodiment of the present invention.

[0048] FIGS. 12A to 12G are perspective views schematically illustrating embodiments of an electronic device including a stretchable display device according to an embodiment of the present invention.

[0049] One embodiment of the present invention provides a display device comprising a plurality of mutually spaced island portions, first bridge portions connecting island portions adjacent in a first direction among the plurality of island portions and including a first voltage line, a second voltage line, and a third voltage line, and second bridge portions connecting island portions adjacent in a second direction intersecting the first direction among the plurality of island portions and including a fourth voltage line electrically connected to the first voltage line, a fifth voltage line electrically connected to the second voltage line, and a sixth voltage line electrically connected to the third voltage line, wherein the first voltage line and the fourth voltage line are arranged on a first conductive layer, and the second voltage line, the fifth voltage line, the third voltage line, and the sixth voltage line are arranged on a second conductive layer on the first conductive layer.

[0050] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0051] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals and redundant descriptions thereof will be omitted.

[0052] In this specification, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0053] In this specification, terms like "horizontal," "vertical," "up," "down," "left," and "right" are not intended to be limiting, but rather are used for convenience of explanation. They do not represent absolute orientation. Therefore, these terms may vary depending on factors such as the observer's position or the layout of the display device.

[0054] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0055] In this specification, terms such as “include” or “have” mean that a feature or component described in the specification exists, and do not preclude the possibility that one or more other features or components may be added.

[0056] In this specification, when it is said that a part such as a film, region, or component is on or above another part, it includes not only the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed in between.

[0057] In this specification, when it is said that a film, region, component, etc. are connected, it includes cases where the films, regions, components, etc. are directly connected, and / or cases where other films, regions, components, etc. are interposed between the films, regions, components, etc. and are indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it refers to cases where the films, regions, components, etc. are directly electrically connected, and / or cases where other films, regions, components, etc. are interposed between them and are indirectly electrically connected.

[0058] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. And, “at least one of A and B” refers to the case where it is A, or B, or both A and B.

[0059] In this specification, the x-axis, y-axis, and z-axis are not limited to the three axes on the orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0060] In some embodiments of this specification, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0061] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0062] Fig. 1 is a perspective view schematically illustrating a stretchable display device (1) according to one embodiment of the present invention. Figs. 2a and 2b are perspective views illustrating the stretchable display device (1) of Fig. 1 in a state in which it is stretched in a first direction. Fig. 2c is a perspective view illustrating the stretchable display device (1) of Fig. 1 in a state in which it is stretched in a second direction. Fig. 2d is a perspective view illustrating the stretchable display device of Fig. 1 in a state in which it is stretched in the first and second directions. Fig. 2e is a perspective view illustrating the stretchable display device (1) of Fig. 1 in a state in which it is stretched in a third direction.

[0063] Referring to FIG. 1, a stretchable display device (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The stretchable display device (1) may provide a predetermined image using light emitted from the plurality of pixels. The non-display area (NDA) may be arranged outside the display area (DA). The non-display area (NDA) may entirely surround the display area (DA).

[0064] A stretchable display device (1) can be stretched or contracted in various directions. The stretchable display device (1) can be stretched in a first direction (e.g., the x direction and / or the -x direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIGS. 2A and 2B, a display area (DA) and / or a non-display area (NDA) of the stretchable display device (1) can be stretched in the first direction (e.g., the x direction and / or the -x direction). For example, as illustrated in FIG. 2A, the stretchable display device (1) can be stretched along the x direction and the -x direction, or as illustrated in FIG. 2B, one side of the stretchable display device (1) can be fixed and stretched along the x direction.

[0065] The stretchable display device (1) can be stretched in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one embodiment, as illustrated in FIG. 2 c, the display area (DA) and / or the non-display area (NDA) of the stretchable display device (1) can be stretched in the y direction and the -y direction. In another embodiment, one side of the stretchable display device (1) can be fixed and stretched in the y direction or the -y direction.

[0066] A stretchable display device (1) can be stretched in a plurality of directions, for example, a first direction (e.g., an x ​​direction and / or a -x direction) and a second direction (e.g., a y direction and / or a -y direction) by an external force applied by an external object or a part of a human body. As illustrated in FIG. 2d, a display area (DA) and / or a non-display area (NDA) of the stretchable display device (1) can be stretched in the ±x direction and the ±y direction.

[0067] The stretchable display device (1) can be stretched in a third direction (e.g., the z direction or the -z direction) by an external force applied by an external object or a part of a human body. In one embodiment, FIG. 2e illustrates that a part of the stretchable display device (1), for example, a part of the display area (DA), protrudes in the z direction. In another embodiment, a part of the stretchable display device (1), for example, a part of the display area (DA), can protrude along the -z direction (or be sunken along the z direction).

[0068] Although FIGS. 2A to 2E illustrate the stretchable display device (1) being stretched in the first direction, the second direction, and / or the third direction, the present invention is not limited thereto. In another embodiment, the stretchable display device (1) may be variously deformed into an irregular shape, such as being bent or twisted along two or more axes.

[0069] FIG. 3 is a plan view schematically illustrating a stretchable display device (1) according to one embodiment of the present invention. Here, the “plan view” illustrates a shape as viewed in a third direction (e.g., +z direction or -z direction) which is the thickness direction of the stretchable display device (1).

[0070] A plurality of pixels may be arranged in a display area (DA) of a stretchable display device (1). Each pixel may include subpixels that emit light of different colors. Light-emitting elements corresponding to each subpixel may be arranged in the display area (DA). A circuit for providing electrical signals to the light-emitting elements arranged in the display area (DA) and to transistors electrically connected to the light-emitting elements may be located in a non-display area (NDA) surrounding the display area (DA). A gate driving circuit (GDC) may be arranged in a first non-display area (NDA1) and a second non-display area (NDA2) arranged on both sides of the display area (DA). The gate driving circuit (GDC) may include drivers for providing electrical signals to the gate electrodes of the transistors electrically connected to the light-emitting elements. FIG. 3 illustrates that the gate driving circuit (GDC) is arranged in each of the first non-display area (NDA1) and the second non-display area (NDA2), but the present invention is not limited thereto. In another embodiment, the gate drive circuit (GDC) may be placed in either the first non-display area (NDA1) or the second non-display area (NDA2).

[0071] The data drive circuit (DDC) may be disposed in a third non-display area (NDA3) and / or a fourth non-display area (NDA4) connecting the first non-display area (NDA1) and the second non-display area (NDA2). In one embodiment, FIG. 3 illustrates that the data drive circuit (DDC) is disposed in the fourth non-display area (NDA4). In another embodiment, the data drive circuit (DDC) may be disposed in each of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0072] Although Fig. 3 illustrates that the data drive circuit (DDC) is arranged in the fourth non-display area (NDA4) of the stretchable display device (1), the present invention is not limited thereto. In another embodiment, the stretchable display device (1) may further include a flexible circuit board (not shown) electrically connected through a terminal portion (not shown) arranged in the fourth non-display area (NDA4), and the data drive circuit (DDC) may be arranged on the aforementioned flexible circuit board.

[0073] In some embodiments, the elongation rate of the non-display area (NDA) may be equal to or less than the elongation rate of the display area (DA). In one embodiment, the elongation rates of the non-display areas (NDAs) may be different for each area. For example, the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3) may have substantially the same elongation rates, but the elongation rate of the fourth non-display area (NDA4) may be less than the elongation rates of each of the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3).

[0074] FIG. 4a is an enlarged plan view of part IV of FIG. 3 as part of a stretchable display device (1) according to one embodiment of the present invention.

[0075] Referring to FIG. 4a, the stretchable display device (1) may include main island portions (11) spaced apart from each other along a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a display area (DA), and main bridge portions (12) connecting adjacent main island portions (11).

[0076] Each main island unit (11) may be connected to a plurality of main bridge units (12). For example, each main island unit (11) may be connected to four main bridge units (12). Two main bridge units (12) may be arranged on both sides of the main island unit (11) along a first direction (e.g., x direction or -x direction), and the remaining two main bridge units (12) may be arranged on both sides of the main island unit (11) along a second direction (e.g., y direction or -y direction). In one embodiment, four main bridge units (12) may be respectively connected to four side edges of the main island unit (11). Each of the four main bridge units (12) may be adjacent to each corner of the main island unit (11).

[0077] The main bridge parts (12) can be spaced apart from each other by first openings (CS1) located between the main bridge parts (12). In one embodiment, the first openings (CS1) having an approximately H shape and the first openings (CS1) having an approximately I shape obtained by rotating the aforementioned H shape by 90 degrees can be alternately and repeatedly arranged along a first direction (e.g., an x ​​direction or a -x direction) and a second direction (e.g., a y direction or a -y direction), respectively. Both ends of each main bridge part (12) are connected to each of the adjacent main island parts (11), and one side of each main bridge part (12) can be spaced apart from one side of the adjacent main island part (11) and / or one side of another main bridge part (12) by the first openings (CS1).

[0078] The stretchable display device (1) may include peripheral island portions (21) spaced apart from each other in a non-display area, for example, the first non-display area (NDA1) illustrated in FIG. 4A, and peripheral bridge portions (22) connecting adjacent peripheral island portions (21).

[0079] Each peripheral island portion (21) may extend along a first direction (e.g., the x direction or the -x direction). The peripheral island portions (21) may be spaced apart from each other along a second direction (e.g., the y direction or the -y direction) intersecting the first direction (e.g., the x direction or the -x direction). Each peripheral island portion (21) may include drivers of a gate drive circuit (GDC, FIG. 2) described with reference to FIG. 3.

[0080] The peripheral bridge portion (22) may have a serpentine shape. The length of the peripheral bridge portion (22) may be greater than the shortest distance between adjacent peripheral island portions (21) along the second direction (e.g., the y direction or the -y direction). In one embodiment, the peripheral bridge portion (22) may have a shape of approximately omega (Ω) that is convex toward the first direction (e.g., the x direction or the -x direction). The peripheral bridge portions (22) may be arranged between adjacent peripheral island portions (21), but may be spaced apart from each other.

[0081] The peripheral bridge portions (22) between adjacent peripheral island portions (21) can be spaced apart from each other by the second opening portions (CS2). Between the adjacent peripheral island portions (21), the second opening portions (CS2) and the peripheral bridge portions (22) can be alternately arranged along a first direction (e.g., the x direction or the -x direction). The second opening portions (CS2) can have the same shape. Both ends of each peripheral bridge portion (22) are connected to the adjacent peripheral island portions (21), but one side of each peripheral bridge portion (22) can be spaced apart from the side of the adjacent peripheral island portion (21) and / or one side of another peripheral bridge portion (22) by the second opening portions (CS2).

[0082] Any one of the peripheral islands (21) arranged in the first non-display area (NDA1) can correspond to the main islands (11) of a plurality of rows arranged in the display area (DA). For example, any one of the peripheral islands (21) arranged in the first non-display area (NDA1) can correspond to the main islands (11) arranged in the (i)-th row and the main islands (11) arranged in the (i+1)-th row in the display area (DA) (here, i is a positive integer greater than 0). Although Fig. 4a illustrates that one peripheral island (21) corresponds to two rows of the main islands (11), the present invention is not limited thereto. In another embodiment, any one of the peripheral islands (21) arranged in the first non-display area (NDA1) can correspond to n rows of the main islands (11) arranged in the display area (DA) (here, n is a positive integer greater than 3).

[0083] A non-display area, for example, a first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which the aforementioned peripheral island portions (21) and peripheral bridge portions (22) are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). In the second sub-non-display area (SNDA2), connection bridge portions (23) may be arranged to connect the display area (DA) and the first sub-non-display area (SNDA1). One end of the connection bridge portion (23) may be connected to the peripheral island portion (21) and / or the peripheral bridge portion (22), and the other end of the connection bridge portion (23) may be connected to the main island portion (11) and / or the main bridge portion (12).

[0084] The connecting bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the connecting bridge portion (23) may be different from the shapes of the main bridge portion (12) and the peripheral bridge portions (22). In one embodiment, as illustrated in FIG. 4A, the connecting bridge portion (23) may have a shape of approximately omega (Ω) that is convex in the second direction (e.g., the y direction or the -y direction). One of the adjacent connecting bridge portions (23) arranged along the second direction (e.g., the y direction or the -y direction) may have a structure that is symmetrical to each other, such as one being convex in the y direction and the other being convex in the -y direction. Between the connecting bridge portions (23), a third opening (CS3) and a fourth opening (CS4) of different shapes may have a structure in which they are repeated. The width of the connecting bridge portion (23) may be different from the width of the main bridge portion (12) and the width of the peripheral bridge portion (22). In one embodiment, the width of the connecting bridge portion (23) may be larger than the width of the main bridge portion (12) and smaller than the width of the peripheral bridge portion (22).

[0085] FIG. 4a shows that the peripheral island portion (21) and the peripheral bridge portion (22) of the non-display area, for example, the first non-display area (NDA1), have different shapes from the main island portion (11) and the main bridge portion (12) of the display area (DA), respectively. In another embodiment of the present invention, the peripheral island portion (21) and the peripheral bridge portion (22) of the non-display area may have the same shape as the main island portion (11) and the main bridge portion (12) of the display area (DA), respectively.

[0086] FIG. 4b is an enlarged plan view of part IV of FIG. 3 as part of a stretchable display device (1) according to one embodiment of the present invention.

[0087] Referring to Fig. 4b, the stretchable display device (1) includes main island portions (11) that are spaced apart from each other in the display area (DA) and main bridge portions (12) that connect adjacent main island portions (11) that are spaced apart from each other by a first opening (CS1). The structure of the display area (DA) of Fig. 4b may be the same as the structure of the display area (DA) described above with reference to Fig. 4a.

[0088] A stretchable display device (1) may include peripheral island portions (21) and peripheral bridge portions (22) arranged in a non-display area, for example, a first non-display area (NDA1). In one embodiment, the peripheral island portions (21) and peripheral bridge portions (22) may have substantially the same shape as the main island portions (11) and main bridge portions (12), respectively.

[0089] The peripheral island portions (21) can be spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area, for example, a first non-display area (NDA1). Each of the peripheral bridge portions (22) can connect adjacent peripheral island portions (21). The peripheral bridge portions (22) can be spaced apart from each other by a second opening (CS2) located between the peripheral bridge portions (22).

[0090] The second opening (CS2) may have substantially the same shape as the first opening (CS1). For example, the second opening (CS2) having an approximately H shape and the second opening (CS2) having an approximately I shape may be alternately and repeatedly arranged in a non-display area, for example, the first non-display area (NDA1). The two ends of each peripheral bridge portion (22) are connected to each of the adjacent peripheral island portions (21), and one side of each second bridge portion (2) may be spaced apart from one side of the adjacent peripheral island portion (21) and / or one side of another peripheral bridge portion (22) by the second opening (CS2).

[0091] Each peripheral island section (21) can be connected to four peripheral bridge sections (22). Each peripheral island section (21) can include drivers of the gate drive circuit (GDC, FIG. 2) described with reference to FIG. 3.

[0092] The peripheral islands (21) of any one row arranged in the first non-display area (NDA1) may correspond to the main islands (11) of any one row arranged in the display area (DA). For example, the peripheral islands (21) arranged in the (i)th row along the first direction (e.g., the x direction or the -x direction) in the first non-display area (NDA1) may correspond to the main islands (11) arranged in the same row, e.g., the (i)th row, in the display area (DA) (wherein, i is a positive number greater than 0).

[0093] A stretchable display device (1) may include connection bridge units (23) arranged in a second sub-non-display area (SNDA2) for connecting a display area (DA) and a first sub-non-display area (SNDA1). The non-display area, for example, the first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which peripheral island units (21) and peripheral bridge units (22) are arranged, and a second sub-non-display area (SNDA2) including connection bridge units (23) and positioned between the first sub-non-display area (SNDA1) and the display area (DA). The connection bridge unit (23) may be substantially the same as the main bridge unit (12) and the peripheral bridge unit (22). For example, the width of the connection bridge unit (23) may be the same as the width of the main bridge unit (12) and the width of the peripheral bridge unit (22).

[0094] FIG. 4c is an enlarged plan view of part IV of FIG. 3 as part of a stretchable display device according to one embodiment of the present invention.

[0095] Referring to FIG. 4c, the stretchable display device (1) may include main island portions (11) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in the display area (DA) and main bridge portions (12) connecting adjacent main island portions (11).

[0096] The main bridge parts (12) may be arranged to be spaced apart from each other by a first opening (CS1) located between the main bridge parts (12). The main bridge parts (12) may have a winding shape. For example, as illustrated in Fig. 4c, the main bridge parts (12) may have a shape roughly similar to the letter 'S'.

[0097] Each main island unit (11) may be connected to a plurality of main bridge units (12). For example, each main island unit (11) may be connected to four main bridge units (12). Two main bridge units (12) may be arranged on both sides of the main island unit (11) along a first direction (e.g., x direction or -x direction), and the remaining two main bridge units (12) may be arranged on both sides of the main island unit (11) along a second direction (e.g., y direction or -y direction). The four main bridge units (12) may be respectively connected to four side edges of the main island unit (11). Each of the four main bridge units (12) may be adjacent to each corner of the main island unit (11).

[0098] A stretchable display device (1) may include peripheral island portions (21) spaced apart from each other in a first direction (e.g., x direction or -x direction) and a second direction (e.g., y direction or -y direction) in a non-display area, for example, a first non-display area (NDA1) illustrated in FIG. 4c, and peripheral bridge portions (22) connecting adjacent peripheral island portions (21).

[0099] The peripheral bridge portions (22) may be arranged to be spaced apart from each other by a second opening (CS2) located between the peripheral bridge portions (22). The peripheral bridge portions (22) may have a winding shape. For example, as illustrated in FIG. 4C, the peripheral bridge portions (22) may have approximately the shape of the letter 'S'. The size and / or width of the peripheral bridge portions (22) may be different from the size and / or width of the main bridge portion (12). For example, the size and / or width of the peripheral bridge portions (22) may be larger than the size and / or width of the main bridge portion (12). The radius of curvature of the rounded portion of the peripheral bridge portions (22) may be different from the radius of curvature of the rounded portion of the main bridge portion (12). For example, the radius of curvature of the rounded portion of the peripheral bridge portion (22) may be larger than the radius of curvature of the rounded portion of the main bridge portion (12).

[0100] Each peripheral island portion (21) can be connected to a plurality of peripheral bridge portions (22). Each peripheral island portion (21) can be connected to four peripheral bridge portions (22). Two peripheral bridge portions (22) can be arranged on both sides of the peripheral island portion (21) along a first direction (e.g., x direction or -x direction), and the remaining two peripheral bridge portions (22) can be arranged on both sides of the peripheral island portion (21) along a second direction (e.g., y direction or -y direction). In one embodiment, four peripheral bridge portions (22) can be respectively connected to four side edges of the peripheral island portion (21). Each peripheral bridge portion (22) can be connected to a central portion of each side edge of the peripheral island portion (21).

[0101] The peripheral islands (21) of any one row arranged in the first non-display area (NDA1) may correspond to the main islands (11) of a plurality of rows arranged in the display area (DA). For example, the peripheral islands (21) of any one row arranged in the first non-display area (NDA1) may correspond to the main islands (11) arranged in the (i)-th row of the display area (DA) and the main islands (11) arranged in the (i+1)-th row (here, i is a positive integer greater than 0). In another embodiment, the peripheral islands (21) of any one row may correspond to n rows of the main islands (11) (here, n is a positive integer greater than 3).

[0102] A non-display area, for example, a first non-display area (NDA1), may include a first sub-non-display area (SNDA1) in which the aforementioned peripheral island portions (21) and peripheral bridge portions (22) are arranged, and a second sub-non-display area (SNDA2) between the first sub-non-display area (SNDA1) and the display area (DA). In the second sub-non-display area (SNDA2), connection bridge portions (23) for connecting the display area (DA) and the first sub-non-display area (SNDA1) may be arranged. One end of the connection bridge portion (23) may be connected to the peripheral island portion (21), and the other end of the connection bridge portion (23) may be connected to the main island portion (11). For example, one end of the connecting bridge portion (23) may be connected to the central portion of one side of the peripheral island portion (21), and the other end of the connecting bridge portion (23) may be connected to the central portion of one side of the main island portion (11).

[0103] The connecting bridge portion (23) may have a serpentine shape. In one embodiment, the shape of the connecting bridge portion (23) may be different from the shapes of the main bridge portion (12) and the peripheral bridge portions (22). The width of the connecting bridge portion (23) may be different from the width of the main bridge portion (12) and the width of the peripheral bridge portions (22). The width of the connecting bridge portion (23) may be larger than the width of the main bridge portion (12) and smaller than the width of the peripheral bridge portions (22). Third openings (CS3) and fourth openings (CS4) of different shapes may be alternately arranged between the connecting bridge portions (23) in the second direction (e.g., the y direction or the -y direction).

[0104] FIG. 5 is a cross-sectional view schematically showing a main island portion (11) and a main bridge portion (12) arranged in a display area (DA) of a stretchable display device (1) according to one embodiment of the present invention.

[0105] Referring to Fig. 5, the main island portion (11) and the main bridge portion (12) arranged in the display area (DA) may be spaced apart from each other with a first opening (CS1) therebetween. The main island portion (11) includes light-emitting elements (LEDs) and a circuit for driving the light-emitting elements electrically connected thereto, for example, a pixel driving circuit portion (PC), and the main bridge portion (12) may include an auxiliary capacitor (Ca) electrically connected to the pixel driving circuit portions (PC) arranged in each of the adjacent main island portions (11).

[0106] Looking at the main island unit (11), a buffer layer (111) including an inorganic insulator is disposed on a substrate (100), and a pixel driver circuit unit (PC) may be disposed on the buffer layer (111). An insulating layer (IL) including an inorganic insulator and / or an organic insulator may be disposed between the pixel driver circuit unit (PC) and the light emitting element (LED). The light emitting element (LED) is disposed on the insulating layer (IL) and may be electrically connected to a corresponding pixel driver circuit unit (PC). The light emitting elements (LEDs) may emit light of different colors or the same color. In one embodiment, the light emitting elements (LEDs) may emit red, green, and blue light, respectively. In some embodiments, the light emitting elements (LEDs) may emit white light. In another embodiment, the light emitting elements (LEDs) may emit red, green, blue, and white light, respectively.

[0107] The substrate (100) may include a polymer resin such as polyethersulfone, polyarylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. In one embodiment, the substrate (100) may be a single layer including the aforementioned polymer resin. In another embodiment, the substrate (100) may be a multilayer structure including a base layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material. The substrate (100) including the polymer resin may have flexible, rollable, and bendable properties.

[0108] In one embodiment, FIG. 5 illustrates three pixel driver circuits (PCs) arranged in each main island unit (11) and three light-emitting elements (LEDs) connected to each pixel driver circuit unit (PC), but the present invention is not limited thereto. In another embodiment, the number of pixel driver circuits (PCs) and light-emitting elements (LEDs) arranged in the main island unit (11) may be one, two, four or more.

[0109] The encapsulation layer (300) may be disposed on a light-emitting element (LED) and may protect the light-emitting element (LED) from external force and / or moisture permeation. The encapsulation layer (300) may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer (300) may include a structure in which an inorganic encapsulation layer including an inorganic insulating material, an organic encapsulation layer including an organic insulating material, and an inorganic encapsulation layer including an inorganic insulating material are laminated. In other embodiments, the encapsulation layer (300) may include an organic material such as a resin. In some embodiments, the encapsulation layer (300) may include urethane epoxy acrylate. The encapsulation layer (300) may include a photosensitive material, for example, a material such as a photoresist.

[0110] Looking at the main bridge portion (12), an insulating layer (IL) including an organic insulating material may be placed on the substrate (100). When the stretchable display device (1) is stretched, the main bridge portion (12), which is relatively subject to a large amount of deformation, may not have a layer including an inorganic insulating material that is prone to cracking, unlike the main island portion (11).

[0111] In one embodiment, the substrate (100) corresponding to the main bridge portion (12) may have the same laminated structure as the substrate (100) corresponding to the main island portion (11). In one embodiment, the substrate (100) corresponding to the main bridge portion (12) and the substrate (100) corresponding to the main island portion (11) may be polymer resin layers formed together in the same process. In another embodiment, the substrate (100) corresponding to the main bridge portion (12) may have a different laminated structure from the substrate (100) corresponding to the main island portion (11). In some embodiments, the substrate (100) corresponding to the main bridge portion (12) may have a multilayer structure including a base layer including a polymer resin and a barrier layer including an inorganic insulating material, and the substrate (100) corresponding to the main bridge portion (12) may have a structure of a polymer resin layer without a layer including an inorganic insulating material.

[0112] The wirings (WL) of the main bridge section (12) may be signal lines (e.g., gate lines, data lines, etc.) for providing electrical signals to transistors included in the pixel driving circuit section (PC) of the main island section (11), as described above, or voltage lines (e.g., driving voltage lines, initialization voltage lines, etc.) for providing voltage. An encapsulation layer (300) may also be arranged in the main bridge section (12). In another embodiment, the encapsulation layer (300) may not exist in the main bridge section (12).

[0113] Referring to FIGS. 4A to 4C and FIG. 5, the substrate (100) corresponding to the main island portion (11) and the substrate (100) corresponding to the main bridge portion (12) may be connected to each other. In other words, the plan views illustrated in FIGS. 4A to 4C may be substantially the same as the plan view of the substrate (100) of FIG. 5. In other words, the substrate (100) may include an area corresponding to the main island portion (11), an area corresponding to the main bridge portion (12), and an opening (100OP1) having the same shape as the first opening (CS1).

[0114] Similarly, the sealing layer (300) corresponding to the main island portion (11) and the sealing layer (300) corresponding to the main bridge portion (12) may be connected to each other. For example, the plan views illustrated in FIGS. 4A to 4C above may be substantially identical to the plan views of the sealing layer (300). In other words, the sealing layer (300) may include an area corresponding to the main island portion (11), an area corresponding to the main bridge portion (12), and an opening (300OP1) having the same shape as the first opening (CS1).

[0115] The circuit-light-emitting element layer (200) between the substrate (100) and the encapsulation layer (300) may include a buffer layer (111), a pixel driving circuit (PC), a wiring (WL), an insulating layer (IL), and a light-emitting element (LED). Similar to the substrate (100), the plan views illustrated in FIGS. 4A to 4C may be substantially the same as the plan views of the circuit-light-emitting element layer (200). In other words, the circuit-light-emitting element layer (200) may include an opening (200OP1) having the same shape as the first opening (CS1).

[0116] FIGS. 6A to 6C are equivalent circuit diagrams of subpixels of a stretchable display device (1) according to one embodiment of the present invention, respectively.

[0117] Referring to FIG. 6a, a light emitting element (LED) corresponding to a subpixel is electrically connected to a pixel driver circuit (PC), and the pixel driver circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel driver circuit (PC) may be electrically connected to a signal line and a voltage line. The signal line may include a gate line such as a first scan line (SL1) and a data line (DL), and the voltage line may include a driving voltage line (VDDL).

[0118] The second transistor (T2) can be electrically connected to the first scan line (SL1) and the data line (DL). The first scan line (SL1) can provide a first scan signal (GW1) to a gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from the data line (DL) to the first transistor (T1) according to the first scan signal (GW1) input from the first scan line (SL1).

[0119] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the driving voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the driving power voltage (VDD) supplied by the driving voltage line (VDDL).

[0120] The first transistor (T1) is a driving transistor and can control a driving current flowing through a light-emitting element (LED). The first transistor (T1) can be connected to a driving voltage line (VDDL) and a storage capacitor (Cst). The first transistor (T1) can control a driving current flowing through the light-emitting element (LED) from the driving voltage line (VDDL) in response to a voltage value stored in the storage capacitor (Cst). The light-emitting element (LED) can emit light having a predetermined brightness by the driving current. A first electrode of the light-emitting element (LED) can be electrically connected to the first transistor (T1), and a second electrode can be electrically connected to a common voltage line (VSSL) that supplies a common power supply voltage (VSS).

[0121] Although FIG. 6a illustrates that the pixel driver circuit (PC) includes two transistors and one storage capacitor, in other embodiments, the pixel driver circuit (PC) may include three or more transistors.

[0122] Referring to FIG. 6b, the pixel driving circuit unit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0123] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2) and a driving voltage line (VDDL).

[0124] The driving voltage line (VDDL) can transmit the driving power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit the first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit the second initialization voltage (Vaint) that initializes the first electrode of the light-emitting element (LED) to the pixel driver circuit (PC).

[0125] The first transistor (T1) may be electrically connected to a driving voltage line (VDDL) via the fifth transistor (T5) and may be electrically connected to a light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and receives a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0126] The second transistor (T2) is a data writing transistor and is electrically connected to the first scan line (SL1) and the data line (DL). The second transistor (T2) is electrically connected to the driving voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on in response to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0127] The third transistor (T3) is electrically connected to the first scan line (SL1) and is electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The third transistor (T3) can be turned on in response to the first scan signal (GW) received through the first scan line (SL1) to diode-connect the first transistor (T1).

[0128] The fourth transistor (T4) is a first initialization transistor and is electrically connected to the third scan line (SL3) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to the third scan signal (GI) received through the third scan line (SL3) and transmits the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The third scan signal (GI) may correspond to the first scan signal of another pixel driver circuit unit arranged in the previous row of the corresponding pixel driver circuit unit (PC).

[0129] The fifth transistor (T5) may be a motion control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light emission control line (EML), and are turned on simultaneously according to the light emission control signal (EM) transmitted through the light emission control line (EML), thereby forming a current path so that a driving current can flow from the driving voltage line (VDDL) toward the light emitting element (LED).

[0130] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the second scan signal (GB) transmitted through the second scan line (SL2), and can transmit the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED) to initialize the first electrode of the light-emitting element (LED).

[0131] A storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the driving voltage line (VDDL). The storage capacitor (Cst) can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages at both ends of the driving voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0132] Referring to FIG. 6c, the pixel driver circuit unit (PC) may include a first transistor (T1, driving transistor), a second transistor (T2, data writing transistor), a third transistor (T3, first compensation transistor), a fourth transistor (T4, first initialization transistor), a fifth transistor (T5, first emission control transistor), a sixth transistor (T6, second emission control transistor), a seventh transistor (T7, second initialization transistor), an eighth transistor (T8, third emission control transistor), a ninth transistor (T9, second compensation transistor), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0133] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a sustain voltage line (VSL), and a driving voltage line (VDDL).

[0134] The driving voltage line (VDDL) can transmit the driving power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit the first initialization voltage (Vint) for initializing the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit the second initialization voltage (Vaint) for initializing the first electrode of the light emitting element (LED) to the pixel driver circuit (PC). The sustain voltage line (VSL) can provide the sustain voltage (VSUS) to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst), during the initialization period and the data writing period.

[0135] A first transistor (T1) may have a gate, a first terminal electrically connected to a first node (N1), and a second terminal. The first terminal of the first transistor (T1) may be electrically connected to a driving voltage line (VDDL) via a fifth transistor (T5) and an eighth transistor (T8), and the second terminal of the first transistor (T1) may be electrically connected to a light-emitting element (LED) via a sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and may receive a data signal (Dm) according to a switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0136] The second transistor (T2) can be electrically connected to the first scan line (SL1), the data line (DL), and the first node (N1). The second transistor (T2) is electrically connected to the driving voltage line (VDDL) via the first node (N1) and the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on in response to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0137] A third transistor (T3) can be electrically connected to a gate of a first transistor (T1) and a second terminal of the first transistor (T1). The gate of the third transistor (T3) is electrically connected to a first scan line (SL1) and is electrically connected to a light-emitting element (LED) via a sixth transistor (T6). The third transistor (T3) is turned on according to a first scan signal (GW) received through the first scan line (SL1) to diode-connect the first transistor (T1), thereby compensating for a threshold voltage of the first transistor (T1).

[0138] The fourth transistor (T4) is electrically connected to the third scan line (SL3) and the first initialization voltage line (VIL1), and is turned on in response to the third scan signal (GI) transmitted through the third scan line (SL3) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The third scan signal (GI) may correspond to the first scan signal of another pixel driving circuit unit arranged in the previous row of the corresponding pixel driving circuit unit (PC).

[0139] The fifth transistor (T5) may be electrically connected to the first node (N1) and the second node (N2), the sixth transistor (T6) may be electrically connected to the second terminal of the first transistor (T1) and the light-emitting element (LED), and the eighth transistor (T8) may be electrically connected to the second node (N2) and the driving voltage line (VDDL). The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) may be electrically connected to the light-emitting control line (EML), and may be turned on simultaneously in response to the light-emitting control signal (EM) received through the light-emitting control line (EML), thereby forming a current path so that a driving current may flow from the driving voltage line (VDDL) toward the light-emitting element (LED).

[0140] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on in response to the second scan signal (GB) received through the second scan line (SL2) and transmits the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED) to initialize the first electrode of the light-emitting element (LED).

[0141] The ninth transistor (T9) may be electrically connected to the second scan line (SL2), the second node (N2), and the sustain voltage line (VSL). The ninth transistor (T9) may be electrically connected to the second electrode (CE2) of the storage capacitor (Cst) through the second node (N2). The ninth transistor (T9) is turned on according to the second scan signal (GB) received through the second scan line (SL2), and may transmit the sustain voltage (VSUS) to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst), during the initialization section and the data writing section.

[0142] The eighth transistor (T8) and the ninth transistor (T9) may be electrically connected to a second node (N2), for example, a second electrode (CE2) of a storage capacitor (Cst), respectively. In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on in an initialization period and a data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off in an emission period. Since the sustain voltage (VSUS) is transmitted to the second node (N2) in the initialization period and the data writing period, the uniformity of the luminance (e.g., LRU, Long Range Uniformity) of the stretchable display device according to the voltage drop of the driving voltage line (VDDL) may be improved.

[0143] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0144] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSL), and the first electrode of the light-emitting element (LED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to the voltage difference between the first electrode of the light-emitting element (LED) and the sustain voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, thereby preventing the problem of the black luminance increasing when the sixth transistor (T6) is turned off.

[0145] FIG. 7a is a cross-sectional view schematically illustrating a light-emitting element of a stretchable display device according to one embodiment of the present invention.

[0146] Referring to FIG. 7A, a light-emitting element according to one embodiment of the present invention may include an organic light-emitting diode (220) including an organic material. The organic light-emitting diode (220) may include a first electrode (221) disposed on an insulating layer, a second electrode (225) facing the first electrode (221), and a light-emitting layer (223) interposed between the first electrode (221) and the second electrode (225). A first functional layer (222) may be disposed between the first electrode (221) and the light-emitting layer (223), and a second functional layer (224) may be disposed between the light-emitting layer (223) and the second electrode (225).

[0147] The edge of the first electrode (221) may be covered with a bank layer (BKL) including an insulating material. The bank layer (BKL) may include an opening (B-OP) that overlaps the central portion of the first electrode (221) on a plane.

[0148] The first electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode (221) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the first electrode (221) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on / under the aforementioned reflective layer.

[0149] The light-emitting layer (223) may include a polymer or low-molecular organic material that emits light of a predetermined color. The first functional layer (222) may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer (224) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0150] The second electrode (225) may be formed of a conductive material having a low work function. For example, the second electrode (225) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the second electrode (225) may further include a layer such as ITO, IZO, ZnO, AZO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0151] FIG. 7b is a cross-sectional view schematically illustrating a light-emitting element of a stretchable display device according to one embodiment of the present invention.

[0152] Referring to FIG. 7b, in one embodiment of the present invention, a light-emitting element may include an inorganic light-emitting diode (230) including an inorganic material. The inorganic light-emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the inorganic light-emitting diode (230) may be electrically connected to a first electrode pad (241) and a second electrode pad (242) disposed on the same layer, respectively.

[0153] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be In x Al y Ga 1-x-y A semiconductor material having a composition formula of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be selected from among, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and a p-type dopant such as Mg, Zn, Ca, Sr, Ba, etc. can be doped.

[0154] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be In x Al y Ga 1-x-y A semiconductor material having a composition formula of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be selected from among, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and an n-type dopant such as Si, Ge, or Sn can be doped.

[0155] The intermediate layer (233) is a region where electrons and holes recombine, and as electrons and holes recombine, they transition to a lower energy level and can generate light with a corresponding wavelength. The intermediate layer (233) is, for example, In x Al y Ga 1-x-y It can be formed by including a semiconductor material having a composition formula of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well structure (MQW: Multi Quantum Well). In addition, it can also include a quantum wire structure or a quantum dot structure.

[0156] Although Fig. 7b illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0157] FIGS. 8A to 8F are layer-by-layer layout diagrams schematically illustrating the main island portion of a stretchable display device according to one embodiment of the present invention.

[0158] As described with reference to FIGS. 4A to 4C, the stretchable display device (1) may include a main island portion (11) arranged in a display area (DA) and a plurality of main bridge portions (12) connected to the main island portion (11). The main island portion (11) may include a plurality of subpixels, and the main bridge portion (12) may include wires electrically connected to the subpixels.

[0159] The main island portion (11) may have a first boundary (E1) and a second boundary (E2) extending in a second direction (e.g., y direction and / or -y direction) and arranged on both sides of the main island portion (11), and a third boundary (E3) and a fourth boundary (E4) extending in a first direction (e.g., x direction and / or -x direction) and connecting the first boundary (E1) and the second boundary (E2).

[0160] In one embodiment, a first subpixel, a second subpixel, and a third subpixel that emit light of different colors may be arranged in the main island portion (11). The first subpixel may include a first light-emitting element and a first pixel driving circuit portion connected to the first light-emitting element, the second subpixel may include a second light-emitting element and a second pixel driving circuit portion connected to the second light-emitting element, and the third subpixel may include a third light-emitting element and a third pixel driving circuit portion connected to the third light-emitting element. The present invention is not limited thereto, and one subpixel, two subpixels, or four subpixels may be arranged in the main island portion (11).

[0161] The first pixel driver circuit unit may be arranged in the first circuit area (PCA1), the second pixel driver circuit unit may be arranged in the second circuit area (PCA2), and the third pixel driver circuit unit may be arranged in the third circuit area (PCA3). The first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) may be arranged side by side along the first direction (e.g., the x direction and / or the -x direction). A first connection area (CA1) may be arranged between the first boundary (E1) of the main island area (11) and the first circuit area (PCA1), and a second connection area (CA2) may be arranged between the second boundary (E2) of the main island area (11) and the third circuit area (PCA3). The first connection area (CA1) and the second connection area (CA2) can be arranged with wires extending from the main bridge section (12) to the main island section (11).

[0162] The first pixel driver circuit unit, the second pixel driver circuit unit, and the third pixel driver circuit unit may have substantially the same or similar structures. Hereinafter, the respective components will be described with a focus on the first pixel driver circuit unit arranged in the first circuit area (PCA1), and descriptions of the same or similar components arranged in the second circuit area (PCA2) and the third circuit area (PCA3) will be omitted.

[0163] The main island portion (11) may include a semiconductor layer (1100), a first conductive layer (1200), a second conductive layer (1300), a third conductive layer (1400), a fourth conductive layer (1500), a fifth conductive layer (1600), and a sixth conductive layer (1700) that are sequentially laminated on a substrate (100, see FIG. 5). The semiconductor layer (1100), the first conductive layer (1200), the second conductive layer (1300), the third conductive layer (1400), the fourth conductive layer (1500), the fifth conductive layer (1600), and the sixth conductive layer (1700) may form signal lines and voltage lines connected to pixel driving circuit units (PC, see FIG. 6c) and transistors and capacitors connected to pixel driving circuit units (PC, see FIG. 6c).

[0164] FIG. 8A illustrates a semiconductor layer (1100) and a first conductive layer (1200) disposed on the semiconductor layer (1100). The semiconductor layer (1100) is disposed on a substrate (100, see FIG. 5), and a buffer layer (111, see FIG. 5) may be disposed between the semiconductor layer (1100) and the substrate (100, see FIG. 5). One or more insulating layers (e.g., a first gate insulating layer) may be disposed between the semiconductor layer (1100) and the first conductive layer (1200).

[0165] Referring to FIG. 8A, the semiconductor layer (1100) may include a first semiconductor pattern (1101), a second semiconductor pattern (1102), and a third semiconductor pattern (1103). The first pixel driving circuit unit may include the first semiconductor pattern (1101), the second pixel driving circuit unit may include the second semiconductor pattern (1102), and the third pixel driving circuit unit may include the third semiconductor pattern (1103).

[0166] The first semiconductor pattern (1101) may be arranged in the first circuit area (PCA1), the second semiconductor pattern (1102) may be arranged in the second circuit area (PCA2), and the third semiconductor pattern (1103) may be arranged in the third circuit area (PCA3).

[0167] In one embodiment, the semiconductor layer (1100) may include a silicon-based semiconductor material, such as polysilicon. In another embodiment, the semiconductor layer (1100) may include an oxide-based semiconductor material, such as an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0168] The first conductive layer (1200) may include first conductive patterns (1201), second conductive patterns (1202), third conductive patterns (1203), fourth conductive patterns (1204), fifth conductive patterns (1205), and sixth conductive patterns (1206). The first conductive layer (1200) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials.

[0169] The first conductive patterns (1201) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The first conductive pattern (1201) arranged in the first circuit area (PCA1) may extend to the first connection area (CA1). The first conductive pattern (1201) arranged in the third circuit area (PCA3) may extend to the second connection area (CA2). The first conductive patterns (1201) may be arranged adjacent to the third boundary (E3) of the main island portion (11). The first conductive patterns (1201) may function as a first electrode (lower electrode) of an auxiliary capacitor (Ca, see FIG. 6c).

[0170] The second conductive patterns (1202) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The second conductive patterns (1202) may overlap the first semiconductor pattern (1101), the second semiconductor pattern (1102), or the third semiconductor pattern (1103) on a plane to form first transistors (T1). Each of the second conductive patterns (1202) may include a gate electrode of the first transistor (T1). That is, a portion of the first semiconductor pattern (1101) overlapping the second conductive pattern (1202) on the plane is a channel region of the first transistor (T1), and impurity regions functioning as a first terminal or a second terminal may extend to both sides of the channel region of the first transistor (T1).

[0171] In one embodiment, the width of the first semiconductor pattern (1101) functioning as a channel region of the first transistor (T1) in the second direction (e.g., the y direction and / or the -y direction) may be greater than the width of the second semiconductor pattern (1102) and the third semiconductor pattern (1103) functioning as a channel region of the first transistor (T1) in the second direction (e.g., the y direction and / or the -y direction). In one embodiment, the width of the second conductive pattern (1202) disposed in the first circuit region (PCA1) in the first direction (e.g., the x direction and / or the -x direction) may be smaller than the width of the second conductive pattern (1202) disposed in the second circuit region (PCA2) and the third circuit region (PCA3) in the first direction (e.g., the x direction and / or the -x direction).

[0172] The third conductive pattern (1203) may extend from the first connection area (CA1) across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) to the second connection area (CA2). The third conductive pattern (1203) may overlap the first semiconductor pattern (1101), the second semiconductor pattern (1102), and the third semiconductor pattern (1103) on a plane. The third conductive pattern (1203) may overlap the first semiconductor pattern (1101), the second semiconductor pattern (1102), and the third semiconductor pattern (1103) on a plane to form seventh transistors (T7) and ninth transistors (T9). The third challenge pattern (1203) may include a gate electrode of the seventh transistor (T7) and a gate electrode of the ninth transistor (T9).

[0173] The fourth conductive pattern (1204) may extend from the first connection area (CA1) across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) to the second connection area (CA2). The fourth conductive pattern (1204) may overlap the first semiconductor pattern (1101), the second semiconductor pattern (1102), and the third semiconductor pattern (1103) on a plane to form fifth transistors (T5), sixth transistors (T6), and eighth transistors (T8). That is, the fourth conductive pattern (1204) may include a gate electrode of the fifth transistor (T5), a gate electrode of the sixth transistor (T6), and a gate electrode of the eighth transistor (T8).

[0174] The fifth conductive pattern (1205) may extend from the first connection area (CA1) across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) to the second connection area (CA2). The fifth conductive pattern (1205) may overlap the first semiconductor pattern (1101), the second semiconductor pattern (1102), and the third semiconductor pattern (1103) on a plane to form second transistors (T2) and third transistors (T3). The fifth conductive pattern (1205) may include a gate electrode of the second transistor (T2) and a gate electrode of the third transistor (T3).

[0175] The sixth conductive pattern (1206) may extend from the first connection area (CA1) across the first circuit area (PCA1) and the second circuit area (PCA2) to the third circuit area (PCA3). The sixth conductive pattern (1206) may overlap the first semiconductor pattern (1101), the second semiconductor pattern (1102), and the third semiconductor pattern (1103) on a plane to form fourth transistors (T4). The sixth conductive pattern (1206) may include a gate electrode of the fourth transistor (T4).

[0176] Referring to FIG. 8B, the second conductive layer (1300) may include a seventh conductive pattern (1301), an eighth conductive pattern (1302), a ninth conductive pattern (1303), a tenth conductive pattern (1304), and an eleventh conductive pattern (1305). The second conductive layer (1300) may be disposed on the first conductive layer (1200), and one or more insulating layers (e.g., a second gate insulating layer) may be disposed between the first conductive layer (1200) and the second conductive layer (1300). The second conductive layer (1300) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials.

[0177] The seventh conductive pattern (1301) may extend from the first connection area (CA1) across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) to the second connection area (CA2). The seventh conductive pattern (1301) may be arranged to overlap the first conductive pattern (1201) on a plane and may function as a second electrode (upper electrode) of an auxiliary capacitor (Ca, see FIG. 6c).

[0178] The eighth conductive pattern (1302) may be arranged in the first connection area (CA1) and the first circuit area (PCA1). The eighth conductive pattern (1302) may be a connecting electrode for connecting the sustaining voltage line (VSL) and the seventh conductive pattern (1301).

[0179] The ninth conductive patterns (1303) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The ninth conductive pattern (1303) may be arranged to overlap the second conductive pattern (1202) of the first conductive layer (1200) on a plane, and may define an opening that exposes a portion of the second conductive pattern (1202). The ninth conductive pattern (1303) functions as a second electrode (CE2, see FIG. 6c) of a storage capacitor (Cst, see FIG. 6c), and the second conductive pattern (1202) that overlaps the ninth conductive pattern (1303) on a plane may function as a first electrode (CE1, see FIG. 6c) of the storage capacitor (Cst).

[0180] The 10th conductive pattern (1304) may be arranged in the third circuit area (PCA3) and the second connection area (CA2). The 10th conductive pattern (1304) may be a connecting electrode for connecting the 2-1 initialization voltage line (VIL2a) and the 2-2 initialization voltage line (VIL2b).

[0181] The 11th conductive pattern (1305) may be arranged in the third circuit area (PCA3) and the second connection area (CA2). The 11th conductive pattern (1305) may be a connecting electrode for connecting the 1-1 initialization voltage line (VIL1a) and the 1-2 initialization voltage line (VIL1b).

[0182] Referring to FIG. 8c, the third conductive layer (1400) may include the 12th conductive pattern (1401) to the 25th conductive pattern (1414), the first voltage connection line (VCL1), and the second voltage connection line (VCL2). The third conductive layer (1400) may further include wirings (WL, see FIG. 5) extending from the main island portion (11) to the main bridge portions. The third conductive layer (1400) may be disposed on the second conductive layer (1300), and one or more insulating layers (e.g., interlayer insulating layers) may be disposed between the second conductive layer (1300) and the third conductive layer (1400).

[0183] The third conductive layer (1400) may include a conductive material having flexibility. The third conductive layer (1400) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. For example, the third conductive layer (1400) may be formed as a multilayer of Ti / Al / Ti.

[0184] The 12th conductive pattern (1401) may be arranged in the first connection area (CA1) and the first circuit area (PCA1). The 12th conductive pattern (1401) may be connected to the 7th conductive pattern (1301) and the 8th conductive pattern (1302) of the 2nd conductive layer (1300) through contact holes.

[0185] The 13th conductive pattern (1402) may be arranged in the first connection area (CA1), and the 24th conductive pattern (1413) may be arranged in the second connection area (CA2). Each of the 13th conductive pattern (1402) and the 24th conductive pattern (1413) may be connected to the fourth conductive pattern (1204) of the first conductive layer (1200) through a contact hole. The 13th conductive pattern (1402) may be connected to the first emission control line (EMLa) of the fourth conductive layer (1500) through the contact hole, and the 24th conductive pattern (1413) may be connected to the second emission control line (EMLb) of the fourth conductive layer (1500) through the contact hole.

[0186] The 14th conductive pattern (1403) may be arranged in the first connection area (CA1), and the 25th conductive pattern (1414) may be arranged in the third circuit area (PCA3). Each of the 14th conductive pattern (1403) and the 25th conductive pattern (1414) may be connected to the 6th conductive pattern (1206) of the 1st conductive layer (1200) through a contact hole. The 14th conductive pattern (1403) may be connected to the 3-1st scan line (SL3a) of the 4th conductive layer (1500) through the contact hole, and the 25th conductive pattern (1414) may be connected to the 3-2nd scan line (SL3b) of the 4th conductive layer (1500) through the contact hole.

[0187] The 15th conductive pattern (1404) may be arranged in the first circuit area (PCA1), and the 23rd conductive pattern (1412) may be arranged in the second connection area (CA2). Each of the 15th conductive pattern (1404) and the 23rd conductive pattern (1412) may be connected to the 3rd conductive pattern (1203) of the 1st conductive layer (1200) through a contact hole. The 15th conductive pattern (1404) may be connected to the 2-1st scan line (SL2a) of the 4th conductive layer (1500) through the contact hole, and the 23rd conductive pattern (1412) may be connected to the 2-2nd scan line (SL2b) of the 4th conductive layer (1500) through the contact hole.

[0188] The 16th conductive patterns (1405) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). Each of the 16th conductive patterns (1405) may be connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), or the third semiconductor pattern (1103) of the semiconductor layer (1100) through a contact hole. Each of the 16th conductive patterns (1405) may be connected to the first conductive pattern (1201) of the first conductive layer (1200) and the 26th conductive pattern (1501) of the fourth conductive layer (1500) through contact holes. The 16th challenge pattern (1405) can connect the 6th transistor (T6), the 7th transistor (T7), the first electrode pad (241) of the light-emitting element (LED, see FIG. 6c) and the first electrode of the auxiliary capacitor (Ca, see FIG. 6c).

[0189] The 17th conductive patterns (1406) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). Each of the 17th conductive patterns (1406) may be connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), or the third semiconductor pattern (1103) of the semiconductor layer (1100) through a contact hole. Each of the 17th conductive patterns (1406) may be connected to the seventh conductive pattern (1301) of the second conductive layer (1300) through a contact hole. The 17th conductive pattern (1406) may transmit a sustain voltage (VSUS, see FIG. 6c) to the ninth transistor (T9).

[0190] The 18th conductive patterns (1407) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). Each of the 18th conductive patterns (1407) may be connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), or the third semiconductor pattern (1103) of the semiconductor layer (1100) through a contact hole. Each of the 18th conductive patterns (1407) may be connected to the third voltage connection line (VCL3) of the fourth conductive layer (1500) through a contact hole. The 18th conductive pattern (1407) may transmit a driving power voltage (VDD, see FIG. 6c) to the eighth transistor (T8).

[0191] The 19th conductive patterns (1408) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). Each of the 19th conductive patterns (1408) may be connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), or the third semiconductor pattern (1103) of the semiconductor layer (1100) through a contact hole. Each of the 19th conductive patterns (1408) may be connected to the ninth conductive pattern (1303) of the second conductive layer (1300) through a contact hole. The 19th conductive pattern (1408) may connect the second electrode (CE2, see FIG. 6c) of the eighth transistor (T8) and the storage capacitor (Cst, see FIG. 6c).

[0192] The 20th conductive pattern (1409) may be arranged in the first circuit area (PCA1). The 20th conductive pattern (1409) may be connected to the first semiconductor pattern (1101) of the semiconductor layer (1100) through contact holes. The 20th conductive pattern (1409) may connect the second transistor (T2) and the fifth transistor (T5) of the first pixel driving circuit.

[0193] The 21st conductive patterns (1410) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). Each of the 21st conductive patterns (1410) may be connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), and the third semiconductor pattern (1103) of the semiconductor layer (1100) through a contact hole. Each of the 21st conductive patterns (1410) may be connected to the second conductive pattern (1202) of the first conductive layer (1200) through a contact hole. The 21st challenge pattern (1410) can connect the third transistor (T3), the fourth transistor (T4), and the first electrode (CE1, see FIG. 6c) of the storage capacitor (Cst, see FIG. 6c).

[0194] The 22nd conductive patterns (1411) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). For example, the 22nd conductive pattern (1411) arranged in the first circuit area (PCA1) may be connected to the first semiconductor pattern (1101) of the semiconductor layer (1100) and the first data line (DL1) of the fourth conductive layer (1500) through contact holes. Likewise, the 22nd conductive pattern (1411) disposed in the second circuit area (PCA2) may be connected to the second semiconductor pattern (1102) of the semiconductor layer (1100) and the second data line (DL2) of the fourth conductive layer (1500) through contact holes, and the 22nd conductive pattern (1411) disposed in the third circuit area (PCA3) may be connected to the third semiconductor pattern (1103) of the semiconductor layer (1100) and the third data line (DL3) of the fourth conductive layer (1500) through contact holes. The 22nd conductive pattern (1411) may connect the second transistor (T2) and the data line (DL).

[0195] The first voltage connection line (VCL1) can extend from the first circuit area (PCA1) across the second circuit area (PCA2) to the third circuit area (PCA3). The first voltage connection line (VCL1) can be connected to the third voltage connection lines (VCL3) of the fourth conductive layer (1500) through contact holes.

[0196] The second voltage connection line (VCL2) may extend from the first connection area (CA1) across the first circuit area (PCA1) and the second circuit area (PCA2) to the third circuit area (PCA3). The second voltage connection line (VCL2) may be connected to the third voltage connection lines (VCL3) of the fourth conductive layer (1500) through contact holes.

[0197] The main bridge sections may include a first bridge section extending from the first boundary (E1) of the main island section (11), a second bridge section extending from the second boundary (E2), a third bridge section extending from the third boundary (E3), and a fourth bridge section extending from the fourth boundary (E4).

[0198] The third conductive layer (1400) may include a first-first initialization voltage line (VIL1a), a second-first initialization voltage line (VIL2a), a first-first scan line (SL1a), and a first sustaining voltage line (VSLa) extending from the main island portion (11) to the first bridge portion. The third conductive layer (1400) may include a first-second initialization voltage line (VIL1b), a second-second initialization voltage line (VIL2b), a first-second scan line (SL1b), and a second sustaining voltage line (VSLb) extending from the main island portion (11) to the second bridge portion. Additionally, the third conductive layer (1400) may include a third sustain voltage line (VSLc) extending from the main island portion (11) to the third bridge portion and a fourth sustain voltage line (VSLd) extending from the main island portion (11) to the fourth bridge portion.

[0199] The sustaining voltage line (VSL) transmitting the sustaining voltage (VSUS, see Fig. 6c) may include a first sustaining voltage line (VSLa), a second sustaining voltage line (VSLb), a third sustaining voltage line (VSLc), and a fourth sustaining voltage line (VSLd). The first sustaining voltage line (VSLa), the second sustaining voltage line (VSLb), the third sustaining voltage line (VSLc), and the fourth sustaining voltage line (VSLd) may extend along the first boundary (E1), the second boundary (E2), and the fourth boundary (E4) of the main island portion (11) and be connected to each other.

[0200] A first sustain voltage line (VSLa) and a second sustain voltage line (VSLb) connecting neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction), and a third sustain voltage line (VSLc) and a fourth sustain voltage line (VSLd) connecting neighboring main island portions (11) in a second direction (e.g., y direction and / or -y direction) may be connected to each other within the main island portion (11). The first sustain voltage line (VSLa), the second sustain voltage line (VSLb), the third sustain voltage line (VSLc), and the fourth sustain voltage line (VSLd) may be integrally provided in the third conductive layer (1400). Therefore, the sustain voltage line (VSL) may have a mesh structure in the display area (DA, see FIG. 1) of the stretchable display device (1, see FIG. 1).

[0201] The first sustain voltage line (VSLa) may be connected to the eighth conductive pattern (1302) of the second conductive layer (1300) through a contact hole. The eighth conductive pattern (1302) may be connected to the twelfth conductive pattern (1401) of the third conductive layer (1400), and the twelfth conductive pattern (1401) may be connected to the seventh conductive pattern (1301) of the second conductive layer (1300). The seventh conductive pattern (1301) may be connected to the first semiconductor pattern (1101) and the second semiconductor pattern (1102) of the semiconductor layer (1100) through the seventeenth conductive patterns (1406). The third sustain voltage line (VSLc) can be connected to the third semiconductor pattern (1103) of the semiconductor layer (1100) and the seventh conductive pattern (1301) of the second conductive layer (1300) through contact holes.

[0202] A first initialization voltage line (VIL1, see FIG. 6c) transmitting a first initialization voltage (Vint, see FIG. 6c) may include a first-first initialization voltage line (VIL1a) and a first-second initialization voltage line (VIL1b) connecting neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction). The first-first initialization voltage line (VIL1a) may extend approximately parallel to the first boundary (E1) in the first connection area (CA1), and may extend from the first connection area (CA1) across the first circuit area (PCA1) and the second circuit area (PCA2) to the third circuit area (PCA3). The first-first initialization voltage line (VIL1a) can be connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), and the third semiconductor pattern (1103) of the semiconductor layer (1100) through contact holes. The first-first initialization voltage line (VIL1a) and the first-second initialization voltage line (VIL1b) can be connected to each other through the eleventh conductive pattern (1305) of the second conductive layer (1300) within the main island portion (11).

[0203] A second initialization voltage line (VIL2, see FIG. 6c) transmitting a second initialization voltage (Vaint, see FIG. 6c) may include a second-first initialization voltage line (VIL2a) and a second-second initialization voltage line (VIL2b) connecting neighboring main island portions (11) in a first direction (e.g., in the x direction and / or the -x direction). The second-first initialization voltage line (VIL2a) may extend from the first connection area (CA1) across the first circuit area (PCA1) and the second circuit area (PCA2) to the third circuit area (PCA3). The second-second initialization voltage line (VIL2b) may extend from the second connection area (CA2) along the second boundary (E2). The 2-1 initialization voltage line (VIL2a) can be connected to each of the first semiconductor pattern (1101), the second semiconductor pattern (1102), and the third semiconductor pattern (1103) through contact holes. The 2-1 initialization voltage line (VIL2a) and the 2-2 initialization voltage line (VIL2b) can be connected to each other through the 10th conductive pattern (1304) of the second conductive layer (1300) within the main island portion (11).

[0204] A first scan line (SL1, see FIG. 6c) transmitting a first scan signal (GW, see FIG. 6c) may include a first-first scan line (SL1a) and a first-second scan line (SL1b) connecting neighboring main island portions (11) in a first direction (e.g., in the x direction and / or the -x direction). The first-first scan line (SL1a) may extend approximately parallel to the first boundary (E1) in the first connection area (CA1). The first-second scan line (SL1b) is arranged in the second connection area (CA2), and the first-first scan line (SL1a) and the first-second scan line (SL1b) may be connected to each other via a fifth conductive pattern (1205) of a first conductive layer (1200).

[0205] Referring to FIG. 8d, the fourth conductive layer (1500) may include a 26th conductive pattern (1501) and third voltage connection lines (VCL3). In addition, the fourth conductive layer (1500) may further include wirings (WL, see FIG. 5) extending from the main island portion (11) to the main bridge portions. The fourth conductive layer (1500) may be disposed on the third conductive layer (1400), and one or more organic insulating layers (e.g., a first organic insulating layer) may be disposed between the third conductive layer (1400) and the fourth conductive layer (1500).

[0206] The fourth conductive layer (1500) may include a conductive material having flexibility. The fourth conductive layer (1500) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. For example, the fourth conductive layer (1500) may be formed as a multilayer of Ti / Al / Ti.

[0207] The 26th conductive patterns (1501) may be arranged in the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3), respectively. Each of the 26th conductive patterns (1501) may be connected to the 16th conductive pattern (1405) of the third conductive layer (1400) and the 27th conductive pattern (1601) of the fifth conductive layer (1600) through contact holes. The 26th conductive pattern (1501) may connect the 6th transistor (T6), the 7th transistor (T7), the first electrode of the light-emitting element (LED, see FIG. 6c), and the first electrode of the auxiliary capacitor (Ca, see FIG. 6c).

[0208] Each of the third voltage connection lines (VCL3) can be connected to the first pixel driving circuit, the second pixel driving circuit, or the third pixel driving circuit. The third voltage connection line (VCL3) of the first pixel driving circuit can extend from the first circuit area (PCA1) to the first connection area (CA1), the third voltage connection line (VCL3) of the second pixel driving circuit can extend from the second circuit area (PCA2) to the first circuit area (PCA1), and the third voltage connection line (VCL3) of the third pixel driving circuit can extend from the third circuit area (PCA3) to the second circuit area (PCA2). Each of the third voltage connection lines (VCL3) can be connected to the 18th conductive pattern (1407), the first voltage connection line (VCL1), and the second voltage connection line (VCL2) of the third conductive layer (1400) through contact holes.

[0209] The third voltage connection line (VCL3) of the first pixel driver circuit can be connected to the first driving voltage line (VDDLa) of the fifth conductive layer (1600) through a contact hole. The third voltage connection line (VCL3) of the third pixel driver circuit can be connected to the second driving voltage line (VDDLb), the third driving voltage line (VDDLc), and the fourth driving voltage line (VDDLd) of the fifth conductive layer (1600) through contact holes. The first driving voltage line (VDDLa) to the fourth driving voltage line (VDDLd) can be connected to each other through the first voltage connection line (VCL1), the second voltage connection line (VCL2), and the third voltage connection line (VCL3) within the main island portion (11). Accordingly, the driving voltage line (VDDL) including the first driving voltage line (VDDLa) to the fourth driving voltage line (VDDLd) may have a mesh structure in the display area (DA, see FIG. 1) of the stretchable display device.

[0210] The fourth conductive layer (1500) may include a second-first scan line (SL2a), a first emission control line (EMLa), and a third-first scan line (SL3a) extending from the main island portion (11) to the first bridge portion. The fourth conductive layer (1500) may include a second-second scan line (SL2b), a second emission control line (EMLb), and a third-second scan line (SL3b) extending from the main island portion (11) to the second bridge portion. The fourth conductive layer (1500) may include data lines (DL) extending from the third bridge portion across the main island portion (11) to the fourth bridge portion.

[0211] A second scan line (SL2, see FIG. 6c) transmitting a second scan signal (GB, see FIG. 6c) may include a second-first scan line (SL2a) and a second-second scan line (SL2b) connecting neighboring main island portions (11) in a first direction (e.g., in the x direction and / or the -x direction). The second-first scan line (SL2a) may extend from the first connection area (CA1) along the third boundary (E3) to the first circuit area (PCA1), and the second-second scan line (SL2b) may extend from the second connection area (CA2) along the second boundary (E2). The 2-1 scan line (SL2a) and the 2-2 scan line (SL2b) can be connected to each other through the 15th conductive pattern (1404) of the 3rd conductive layer (1400), the 3rd conductive pattern (1203) of the 1st conductive layer (1200), and the 23rd conductive pattern (1412) of the 3rd conductive layer (1400) within the main island section (11).

[0212] The light emission control line (EML, see Fig. 6c) transmitting the light emission control signal (EM, see Fig. 6c) may include a first light emission control line (EMLa) and a second light emission control line (EMLb) connecting neighboring main island portions (11) in a first direction (e.g., in the x direction and / or the -x direction). The first light emission control line (EMLa) may extend approximately parallel to the first boundary (E1) in the first connection area (CA1), and the second light emission control line (EMLb) may extend approximately parallel to the second boundary (E2) in the second connection area (CA2). The first light-emitting control line (EMLa) and the second light-emitting control line (EMLb) can be connected to each other through the 13th conductive pattern (1402) of the third conductive layer (1400), the 4th conductive pattern (1204) of the first conductive layer (1200), and the 24th conductive pattern (1413) of the third conductive layer (1400) within the main island portion (11).

[0213] A third scan line (SL3, see FIG. 6c) transmitting a third scan signal (GI, see FIG. 6c) may include a third-first scan line (SL3a) and a third-second scan line (SL3b) connecting neighboring main island portions (11) in a first direction (e.g., in the x direction and / or the -x direction). The third-first scan line (SL3a) may extend from the first connection area (CA1) along the first boundary (E1), and the third-second scan line (SL3b) may extend from the second connection area (CA2) along the fourth boundary (E4) to the third circuit area (PCA3). The 3-1 scan line (SL3a) and the 3-2 scan line (SL3b) can be connected to each other through the 14th conductive pattern (1403) of the 3rd conductive layer (1400), the 6th conductive pattern (1206) of the 1st conductive layer (1200), and the 25th conductive pattern (1414) of the 3rd conductive layer (1400) within the main island section (11).

[0214] The data lines (DL) may include a first data line (DL1) connected to a first pixel driver circuit unit, a second data line (DL2) connected to a second pixel driver circuit unit, and a third data line (DL3) connected to a third pixel driver circuit unit.

[0215] The first data line (DL1), the second data line (DL2), and the third data line (DL3) may extend from the first connection area (CA1) across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) to the second connection area (CA2). At this time, the first data line (DL1) may cross the first circuit area (PCA1) approximately in the second direction (e.g., the y direction and / or the -y direction), the second data line (DL2) may cross the second circuit area (PCA2) approximately in the second direction (e.g., the y direction and / or the -y direction), and the third data line (DL3) may cross the third circuit area (PCA3) approximately in the second direction (e.g., the y direction and / or the -y direction). Each of the first data line (DL1), the second data line (DL2), and the third data line (DL3) can be connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), or the third semiconductor pattern (1103) of the semiconductor layer (1100) through the 22nd conductive pattern (1411). Each of the first data line (DL1), the second data line (DL2), and the third data line (DL3) can transmit a data signal (Dm, see FIG. 6c) to the second transistor (T2) of the corresponding pixel driver circuit.

[0216] Referring to FIG. 8e, the fifth conductive layer (1600) may include a common voltage line (VSSL) and a driving voltage line (VDDL) extending from the 27th conductive pattern (1601) and the main island portion (11) to the main bridge portions. The fifth conductive layer (1600) may be disposed on the fourth conductive layer (1500), and one or more organic insulating layers (e.g., a second organic insulating layer) may be disposed between the fourth conductive layer (1500) and the fifth conductive layer (1600).

[0217] The fifth conductive layer (1600) may include a conductive material having flexibility. The fifth conductive layer (1600) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. For example, the fifth conductive layer (1600) may be formed as a multilayer of Ti / Al / Ti.

[0218] The 27th conductive patterns (1601) may be arranged in each of the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3). The 27th conductive pattern (1601) of the first pixel driving circuit portion may extend from the first circuit area (PCA1) to the first connection area (CA1), and the 27th conductive pattern (1601) of the third pixel driving circuit portion may extend from the third circuit area (PCA3) to the second connection area (CA2). Each of the 27th conductive patterns (1601) may be connected to the 26th conductive pattern (1501) of the fourth conductive layer (1500) and the first electrode pad (241) of the sixth conductive layer (1700) through contact holes. The 27th conductive pattern (1601) can connect the first electrode pad (241) of the light-emitting element (LED, see FIG. 6c) to the 6th transistor (T6), the 7th transistor (T7), and the first electrode of the auxiliary capacitor (Ca, see FIG. 6c) through the 16th conductive pattern (1405) of the 3rd conductive layer (1400) and the 26th conductive pattern (1501) of the 4th conductive layer (1500).

[0219] The driving voltage line (VDDL) that transmits the driving power voltage (VDD, see FIG. 6c) may include a first driving voltage line (VDDLa) extending from the main island unit (11) to the first bridge unit, a second driving voltage line (VDDLb) extending from the main island unit (11) to the second bridge unit, a third driving voltage line (VDDLc) extending from the main island unit (11) to the third bridge unit, and a fourth driving voltage line (VDDLd) extending from the main island unit (11) to the fourth bridge unit.

[0220] The first driving voltage line (VDDLa) can be connected to the third voltage connection line (VCL3) of the first pixel circuit driver through a contact hole. The second driving voltage line (VDDLb), the third driving voltage line (VDDLc), and the fourth driving voltage line (VDDLd) can each be connected to the third voltage connection line (VCL3) of the third pixel circuit driver through contact holes. The third voltage connection line (VCL3) can be connected to the first voltage connection line (VCL1) and the second voltage connection line (VCL2) of the third conductive layer (1400) through contact holes.

[0221] A first driving voltage line (VDDLa) and a second driving voltage line (VDDLb) connecting neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction), and a third driving voltage line (VDDLc) and a fourth driving voltage line (VDDLd) connecting neighboring main island portions (11) in a second direction (e.g., y direction and / or -y direction) may be connected to each other within the main island portion (11) via voltage connection lines (VCL1, VCL2, VCL3). The voltage connection lines (VCL1, VCL2, VCL3) may be arranged in a different layer from the first driving voltage line (VDDLa), the second driving voltage line (VDDLb), the third driving voltage line (VDDLc), and the fourth driving voltage line (VDDLd).

[0222] The common voltage line (VSSL) that transmits the common power voltage (VSS, see FIG. 6c) may include a first common voltage line (VSSLa) extending from the main island unit (11) to the first bridge unit, a second common voltage line (VSSLb) extending from the main island unit (11) to the second bridge unit, a third common voltage line (VSSLc) extending from the main island unit (11) to the third bridge unit, and a fourth common voltage line (VSSLd) extending from the main island unit (11) to the fourth bridge unit.

[0223] The first common voltage line (VSSLa), the second common voltage line (VSSLb), the third common voltage line (VSSLc), and the fourth common voltage line (VSSLd) may extend in a first direction (e.g., the x direction and / or the -x direction) and a second direction (e.g., the y direction and / or the -y direction) within the main island portion (11) and be connected to each other. The first common voltage line (VSSLa), the second common voltage line (VSSLb), the third common voltage line (VSSLc), and the fourth common voltage line (VSSLd) may be provided as a single body. Openings (OP) may be defined between the first common voltage line (VSSLa), the second common voltage line (VSSLb), the third common voltage line (VSSLc), and the fourth common voltage line (VSSLd).

[0224] A first common voltage line (VSSLa) and a second common voltage line (VSSLb) connecting neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction), and a third common voltage line (VSSLc) and a fourth common voltage line (VSSLd) connecting neighboring main island portions (11) in a second direction (e.g., y direction and / or -y direction) may be connected to each other within the main island portion (11). Accordingly, the common voltage line (VSSL) may have a mesh structure in a display area (DA, see FIG. 1) of a stretchable display device (1, see FIG. 1).

[0225] Referring to FIG. 8F, the sixth conductive layer (1700) may include first electrode pads (241) and second electrode pads (242). The sixth conductive layer (1700) may be disposed on the fifth conductive layer (1600), and one or more organic insulating layers (e.g., a third organic insulating layer) may be disposed between the fifth conductive layer (1600) and the sixth conductive layer (1700). The sixth conductive layer (1700) may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. In one embodiment, when the first electrode pads (241) and the second electrode pads (242) are connected to electrodes of a light-emitting element (LED, see FIG. 6c) in a eutectic bonding manner, the sixth conductive layer (1700) may have a multilayer structure including a copper (Cu) layer or may include a copper (Cu) alloy. In another embodiment, the sixth conductive layer (1700) may include a conductive organic material. For example, the sixth conductive layer (1700) may include carbon black. In another embodiment, the sixth conductive layer (1700) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Alternatively, the sixth conductive layer (1700) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the sixth conductive layer (1700) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on / under the aforementioned reflective layer. For example, the sixth conductive layer (1700) may include an ITO layer / Ag layer / ITO layer.

[0226] The first electrode pads (241) may be connected to the first pixel driving circuit unit, the second pixel driving circuit unit, and the third pixel driving circuit unit, respectively. The first electrode pads (241) may each have an island shape. The first electrode pad (241) may be connected to the 27th conductive pattern (1601) of the 5th conductive layer (1600) through a contact hole. The first electrode pad (241) may connect the first electrode of the light-emitting element (LED, see FIG. 6c) to the first electrode of the 6th transistor (T6), the 7th transistor (T7), and the auxiliary capacitor (Ca, see FIG. 6c).

[0227] The second electrode pad (242) may extend from the first connection area (CA1) across the first circuit area (PCA1), the second circuit area (PCA2), and the third circuit area (PCA3) to the second connection area (CA2). The second electrode pad (242) may have an island shape in which the length in the first direction (e.g., the x direction and / or the -x direction) is longer than the length in the second direction (e.g., the y direction and / or the -y direction). The second electrode pad (242) may be provided in common to the light-emitting elements arranged in the main island portion (11). For example, the second electrodes of each of the first light-emitting element, the second light-emitting element, and the third light-emitting element may be connected to the second electrode pad (242). The second electrode pad (242) may be connected to the common voltage line (VSSL) of the fifth conductive layer (1600) through contact holes.

[0228] In one embodiment of the present invention illustrated in FIG. 8F, the light-emitting element includes an inorganic light-emitting diode (230, see FIG. 7B), but in other embodiments, the light-emitting element may include an organic light-emitting diode (220, see FIG. 7A). For example, the sixth conductive layer (1700) may include a first electrode (221, see FIG. 7A) instead of the first electrode pad (241). In this case, the sixth conductive layer (1700) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Alternatively, the sixth conductive layer (1700) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In another embodiment, the sixth conductive layer (1700) may further include a layer formed of ITO, IZO, ZnO, AZO, or In2O3 on / under the aforementioned reflective layer.

[0229] FIG. 9A is a layout diagram schematically illustrating a third conductive layer of a stretchable display device according to an embodiment of the present invention, FIGS. 9B and 9C are layout diagrams schematically illustrating a portion of the third conductive layer of a stretchable display device according to an embodiment of the present invention, and FIG. 9D is a layout diagram schematically illustrating a sustain voltage line of a stretchable display device according to an embodiment of the present invention.

[0230] Referring to FIGS. 9A to 9D, the stretchable display device may include a main island portion (11) and a plurality of main bridge portions (12) connected to the main island portion (11) in the display area (DA). The main bridge portion (12) may include horizontal bridge portions (BRh) arranged on both sides of the main island portion (11) along a first direction (e.g., an x ​​direction and / or a -x direction) and vertical bridge portions (BRv) arranged on both sides of the main island portion (11) along a second direction (e.g., a y direction and / or a -y direction).

[0231] The horizontal bridge portions (BRh) may include a first bridge portion (BRh1) disposed at a first boundary (E1) of the main island portion (11) and a second bridge portion (BRh2) disposed at a second boundary (E2). The first bridge portion (BRh1) may be disposed adjacent to a corner where the first boundary (E1) and the third boundary (E3) of the main island portion (11) meet. The second bridge portion (BRh2) may be disposed adjacent to a corner where the second boundary (E2) and the fourth boundary (E4) of the main island portion (11) meet. The first bridge portion (BRh1) and the second bridge portion (BRh2) may connect main island portions (11) that are adjacent in a first direction (e.g., in the x direction and / or the -x direction).

[0232] Outside the boundary (E1, E2) of the main island portion (11), the first bridge portion (BRh1) and the second bridge portion (BRh2) may have the same shape. As illustrated in FIG. 9b, the horizontal bridge portion (BRh) may include a first curved portion (CNP1), a second curved portion (CNP2), and a straight portion (SP) connecting the first curved portion (CNP1) and the second curved portion (CNP2). The straight portion (SP) of the horizontal bridge portion (BRh) may extend in a fourth direction (DR4) intersecting the first direction (e.g., the x direction and / or the -x direction) and the second direction (e.g., the y direction and / or the -y direction). The fourth direction (DR4) may be parallel to a plane defined by the first direction (e.g., the x direction and / or the -x direction) and the second direction (e.g., the y direction and / or the -y direction).

[0233] The first bridge portion (BRh1) may include a first-first initialization voltage line (VIL1a), a second-first initialization voltage line (VIL2a), a first-first scan line (SL1a), and a first sustaining voltage line (VSLa) arranged on a third conductive layer (1400). The second bridge portion (BRh2) may include a first-second initialization voltage line (VIL1b), a second-second initialization voltage line (VIL2b), a first-second scan line (SL1b), and a second sustaining voltage line (VSLb) arranged on a third conductive layer (1400).

[0234] The first-first initialization voltage line (VIL1a) and the first-second initialization voltage line (VIL1b) may be connected to each other through the eleventh conductive pattern (1305, see FIG. 8b) of the second conductive layer (1300, see FIG. 8b) within the main island portion (11). The first-first initialization voltage line (VIL1a) and the first-second initialization voltage line (VIL1b) may be the first initialization voltage line (VIL1) that transmits the first initialization voltage (Vint, see FIG. 6c) to one terminal of the fourth transistor (T4, see FIG. 8a).

[0235] The 2-1 initialization voltage line (VIL2a) and the 2-2 initialization voltage line (VIL2b) may be connected to each other through the 10th conductive pattern (1304, see FIG. 8b) of the 2nd conductive layer (1300, see FIG. 8b) within the main island portion (11). The 2-1 initialization voltage line (VIL2a) and the 2-2 initialization voltage line (VIL2b) may be a 2nd initialization voltage line (VIL2) that transmits the 2nd initialization voltage (Vaint, see FIG. 6c) to one terminal of the 7th transistor (T7, see FIG. 8a).

[0236] The first-first scan line (SL1a) and the first-second scan line (SL1b) may be connected to each other through the fifth conductive pattern (1205, see FIG. 8a) of the first conductive layer (1200, see FIG. 8a) within the main island portion (11). The first-first scan line (SL1a) and the first-second scan line (SL1b) may be the first scan line (SL1) that transmits the first scan signal (GW, see FIG. 6c) to the gate of the second transistor (T2, see FIG. 8a) and the gate of the third transistor (T3, see FIG. 8a).

[0237] The horizontal bridge section (BRh) may include a first initialization voltage line (VIL1), a second initialization voltage line (VIL2), and a first scan line (SL1) that connect neighboring main island sections (11) in a first direction (e.g., x direction and / or -x direction) in the third conductive layer (1400).

[0238] The first sustaining voltage line (VSLa) and the second sustaining voltage line (VSLb) may be horizontal sustaining voltage lines (VSLh, first voltage lines). The horizontal bridge portion (BRh) may include horizontal sustaining voltage lines (VSLh) that connect neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction). The horizontal sustaining voltage line (VSLh) may have a first width (w1) in a direction perpendicular to the extension direction of the horizontal sustaining voltage line (VSLh).

[0239] As illustrated in FIG. 9b, in the first curved portion (CNP1) of the horizontal bridge portion (BRh), a horizontal maintenance voltage line (VSLh), a first initialization voltage line (VIL1), a first scan line (SL1), and a second initialization voltage line (VIL2) may be sequentially arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curved portion to the outer boundary (COE) of the curved portion, and in the second curved portion (CNP2), a second initialization voltage line (VIL2), a first scan line (SL1), a first initialization voltage line (VIL1), and a horizontal maintenance voltage line (VSLh) may be sequentially arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curved portion to the outer boundary (COE) of the curved portion.

[0240] The wiring closest to the inner boundary (CIE) of the curved portion may be arranged at a first distance (d1) away from the inner boundary (CIE) of the curved portion, and the wiring closest to the outer boundary (COE) of the curved portion may be arranged at a second distance (d2) away from the outer boundary (COE) of the curved portion. For example, as illustrated in FIG. 9b, the second initialization voltage line (VIL2), which is the wiring closest to the inner boundary (CIE) of the curved portion in the second curved portion (CNP2), may be arranged at a first distance (d1) away from the inner boundary (CIE) of the curved portion, and the horizontal maintenance voltage line (VSLh), which is the wiring closest to the outer boundary (COE) of the curved portion in the second curved portion (CNP2), may be arranged at a second distance (d2) away from the outer boundary (COE) of the curved portion. When a stretchable display device (1, see Fig. 1) is stretched by an external force, the inner boundary of the curved portion (CIE) may be subjected to greater stress than the outer boundary of the curved portion (COE). Therefore, the first distance (d1) may be greater than the second distance (d2).

[0241] The vertical bridge portions (BRv) may include a third bridge portion (BRv1) disposed at a third boundary (E3) of the main island portion (11) and a fourth bridge portion (BRv2) disposed at a fourth boundary (E4). The third bridge portion (BRv1) may be disposed adjacent to a corner where the third boundary (E3) and the second boundary (E2) of the main island portion (11) meet. The fourth bridge portion (BRv2) may be disposed adjacent to a corner where the first boundary (E1) and the fourth boundary (E4) of the main island portion (11) meet. The third bridge portion (BRv1) and the fourth bridge portion (BRv2) may connect adjacent main island portions (11) in a second direction (e.g., the y direction and / or the -y direction).

[0242] Outside the boundary (E3, E4) of the main island portion (11), the third bridge portion (BRv1) and the fourth bridge portion (BRv2) may have the same shape. As illustrated in FIG. 9c, the vertical bridge portion (BRv) may include a third curve portion (CNP3), a fourth curve portion (CNP4), and a straight portion (SP) connecting the third curve portion (CNP3) and the fourth curve portion (CNP4). The straight portion (SP) of the vertical bridge portion (BRv) may extend in a fifth direction (DR5) intersecting the first direction (e.g., the x direction and / or the -x direction) and the second direction (e.g., the y direction and / or the -y direction).

[0243] The third bridge portion (BRv1) may include a third sustaining voltage line (VSLc) arranged on a third conductive layer (1400), and the fourth bridge portion (BRv2) may include a fourth sustaining voltage line (VSLd) arranged on the third conductive layer (1400). The third sustaining voltage line (VSLc) and the fourth sustaining voltage line (VSLd) may be vertical sustaining voltage lines (VSLv, fourth voltage lines). The vertical sustaining voltage line (VSLv) may have a second width (w2) in a direction perpendicular to the extension direction of the vertical sustaining voltage line (VSLv). The second width (w2) of the vertical sustaining voltage line (VSLv) may be greater than the first width (w1) of the horizontal sustaining voltage line (VSLh).

[0244] In one embodiment, the vertical bridge portion (BRv) may include only a vertical sustain voltage line (VSLv) in the third conductive layer (1400). Accordingly, the second width (w2) of the vertical sustain voltage line (VSLv) may have the largest width among the wires (WL, see FIG. 5) included in the main bridge portions (12).

[0245] In one embodiment, the ratio of the first width (w1) of the horizontal maintenance voltage line (VSLh) to the second width (w2) of the vertical maintenance voltage line (VSLv) may vary depending on the length of the first direction (e.g., the x direction and / or the -x direction) and the length of the second direction (e.g., the y direction and / or the -y direction) of the display area (DA, see FIG. 1). For example, when the display area (DA) has a long shape in the second direction (e.g., the y direction and / or the -y direction), the stress received by the vertical maintenance voltage line (VSLv) is greater than the stress received by the horizontal maintenance voltage line (VSLh), and therefore, the second width (w2) of the vertical maintenance voltage line (VSLv) may be larger than the first width (w1) of the horizontal maintenance voltage line (VSLh).

[0246] As illustrated in Fig. 9c, the vertical bridge portion (BRv) may be arranged at a first distance (d1) away from the inner boundary (CIE) of the curved portion and at a second distance (d2) away from the outer boundary (COE) of the curved portion. The first distance (d1) may be greater than the second distance (d2).

[0247] As illustrated in FIG. 9d, the first sustaining voltage line (VSLa), the second sustaining voltage line (VSLb), the third sustaining voltage line (VSLc), and the fourth sustaining voltage line (VSLd) may extend along the first boundary (E1), the second boundary (E2), and the fourth boundary (E4) of the main island portion (11) and be connected to each other. The first sustaining voltage line (VSLa), the second sustaining voltage line (VSLb), the third sustaining voltage line (VSLc), and the fourth sustaining voltage line (VSLd) may be integrally provided in the third conductive layer (1400) to have a mesh structure that connects the main island portions (11) adjacent in the first direction (e.g., the x direction and / or the -x direction) and the main island portions (11) adjacent in the second direction (e.g., the y direction and / or the -y direction).

[0248] FIG. 10A is a layout diagram schematically illustrating a fourth conductive layer of a stretchable display device according to an embodiment of the present invention, and FIGS. 10B and 10C are layout diagrams schematically illustrating a portion of the fourth conductive layer of a stretchable display device according to an embodiment of the present invention.

[0249] Referring to FIGS. 10A to 10C, the stretchable display device may include a main island portion (11) and a plurality of main bridge portions (12) connected to the main island portion (11) in the display area (DA).

[0250] The main bridge section (12) may include horizontal bridge sections (BRh) and vertical bridge sections (BRv). The first bridge section (BRh1) arranged at the first boundary (E1) of the main island section (11) and the second bridge section (BRh2) arranged at the second boundary (E2) may be horizontal bridge sections (BRh) having the same shape as each other outside the boundaries (E1, E2) of the main island section (11).

[0251] The first bridge portion (BRh1) may include a second-first scan line (SL2a), a first emission control line (EMLa), and a third-first scan line (SL3a) arranged on the fourth conductive layer (1500). The second bridge portion (BRh2) may include a second-second scan line (SL2b), a second emission control line (EMLb), and a third-second scan line (SL3b) arranged on the fourth conductive layer (1500).

[0252] The 2-1 scan line (SL2a) and the 2-2 scan line (SL2b) may be connected to each other through the 15th conductive pattern (1404), the 23rd conductive pattern (1412) of the 3rd conductive layer (1400) and the 3rd conductive pattern (1203) of the 1st conductive layer (1200) within the main island portion (11). The 2-1 scan line (SL2a) and the 2-2 scan line (SL2b) may be the 2nd scan line (SL2) that transmits the 2nd scan signal (GB, see FIG. 6c) to the gate of the 7th transistor (T7, see FIG. 8a) and the gate of the 9th transistor (T9, see FIG. 8a).

[0253] The first light emission control line (EMLa) and the second light emission control line (EMLb) may be connected to each other through the 13th conductive pattern (1402) of the third conductive layer (1400), the 4th conductive pattern (1204) of the first conductive layer (1200), and the 24th conductive pattern (1413) of the third conductive layer (1400) within the main island portion (11). The first light emission control line (EMLa) and the second light emission control line (EMLb) may be light emission control lines (EML) that transmit a light emission control signal (EM, see FIG. 6c) to the gate of the fifth transistor (T5, see FIG. 8a), the gate of the sixth transistor (T6, see FIG. 8a), and the gate of the eighth transistor (T8, see FIG. 8a).

[0254] The 3-1 scan line (SL3a) and the 3-2 scan line (SL3b) may be connected to each other through the 14th conductive pattern (1403) of the 3rd conductive layer (1400), the 6th conductive pattern (1206) of the 1st conductive layer (1200), and the 25th conductive pattern (1414) of the 3rd conductive layer (1400) within the main island portion (11). The 3-1 scan line (SL3a) and the 3-2 scan line (SL3b) may be the 3rd scan line (SL3) that transmits the 3rd scan signal (GI, see FIG. 6c) to the gate of the 4th transistor (T4, see FIG. 8a).

[0255] That is, as illustrated in FIG. 10b, the horizontal bridge portion (BRh) may include a second scan line (SL2), an emission control line (EML), and a third scan line (SL3) that connect neighboring main island portions (11) in the first direction (e.g., the x direction and / or the -x direction) in the fourth conductive layer (1500).

[0256] In the first curved portion (CNP1), a third scan line (SL3), an emission control line (EML), and a second scan line (SL2) may be sequentially arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curved portion to the outer boundary (COE) of the curved portion, and in the second curved portion (CNP2), a second scan line (SL2), an emission control line (EML), and a third scan line (SL3) may be sequentially arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curved portion to the outer boundary (COE) of the curved portion.

[0257] The wiring closest to the inner boundary (CIE) of the curved portion may be arranged at a first distance (d1) away from the inner boundary (CIE) of the curved portion, and the wiring closest to the outer boundary (COE) of the curved portion may be arranged at a second distance (d2) away from the outer boundary (COE) of the curved portion. For example, as illustrated in FIG. 10b, in the second curved portion (CNP2), the second scan line (SL2) may be arranged at a first distance (d1) away from the inner boundary (CIE) of the curved portion, and the third scan line (SL3) may be arranged at a second distance (d2) away from the outer boundary (COE) of the curved portion. The first distance (d1) may be greater than the second distance (d2).

[0258] The third bridge section (BRv1) placed at the third boundary (E3) of the main island section (11) and the fourth bridge section (BRv2) placed at the fourth boundary (E4) may be vertical bridge sections (BRv) having the same shape as each other outside the boundaries (E3, E4) of the main island section (11).

[0259] The third bridge unit (BRv1) and the fourth bridge unit (BRv2) may include a first data line (DL1), a second data line (DL2), and a third data line (DL3) arranged on a fourth conductive layer (1500). The first data line (DL1), the second data line (DL2), and the third data line (DL3) cross the main island unit (11), and each of the first data line (DL1), the second data line (DL2), and the third data line (DL3) may be provided as an integral unit. That is, the vertical bridge unit (BRv) may include data lines (DL) that connect neighboring main island units (11) in the second direction (e.g., the y direction and / or the -y direction) in the fourth conductive layer (1500).

[0260] Each of the first data line (DL1), the second data line (DL2), and the third data line (DL3) is connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), or the third semiconductor pattern (1103) of the semiconductor layer (1100) through the 22nd conductive pattern (1411, see 8c) of the third conductive layer (1400, see 8c), and can transmit a data signal (Dm, see FIG. 6c) to one terminal of the second transistor (T2, see FIG. 8a) of the corresponding pixel driving circuit.

[0261] As illustrated in FIG. 10c, in the third curved portion (CNP3), the third data line (DL3), the second data line (DL2), and the first data line (DL1) may be sequentially arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curved portion to the outer boundary (COE) of the curved portion, and in the fourth curved portion (CNP4), the first data line (DL1), the second data line (DL2), and the third data line (DL3) may be sequentially arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curved portion to the outer boundary (COE) of the curved portion.

[0262] The wiring closest to the inner boundary (CIE) of the curved portion may be arranged at a first distance (d1) away from the inner boundary (CIE) of the curved portion, and the wiring closest to the outer boundary (COE) of the curved portion may be arranged at a second distance (d2) away from the outer boundary (COE) of the curved portion. For example, in the fourth curved portion (CNP4), the first data line (DL1) may be arranged at a first distance (d1) away from the inner boundary (CIE) of the curved portion, and the third data line (DL3) may be arranged at a second distance (d2) away from the outer boundary (COE) of the curved portion. The first distance (d1) may be greater than the second distance (d2).

[0263] FIG. 11A is a layout diagram schematically illustrating a fifth conductive layer of a stretchable display device according to an embodiment of the present invention, FIGS. 11B and 11C are layout diagrams schematically illustrating a portion of the fifth conductive layer of a stretchable display device according to an embodiment of the present invention, FIG. 11D is a layout diagram schematically illustrating a driving voltage line of a stretchable display device according to an embodiment of the present invention, and FIG. 11E is a layout diagram schematically illustrating a common voltage line of a stretchable display device according to an embodiment of the present invention.

[0264] Referring to FIGS. 11a to 11e, the stretchable display device may include a main island portion (11) and a plurality of main bridge portions (12) connected to the main island portion (11) in the display area (DA).

[0265] The main bridge section (12) may include a first bridge section (BRh1) disposed at a first boundary (E1) of the main island section (11), a second bridge section (BRh2) disposed at a second boundary (E2), a third bridge section (BRv1) disposed at a third boundary (E3) of the main island section (11), and a fourth bridge section (BRv2) disposed at a fourth boundary (E4). Outside the boundary of the main island section (11), the first bridge section (BRh1) and the second bridge section (BRh2) may have the same shape, and the third bridge section (BRv1) and the fourth bridge section (BRv2) may have the same shape.

[0266] The first bridge portion (BRh1) and the second bridge portion (BRh2) may be horizontal bridge portions (BRh) that connect neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction), and the third bridge portion (BRv1) and the fourth bridge portion (BRv2) may be vertical bridge portions (BRv) that connect neighboring main island portions (11) in a second direction (e.g., y direction and / or -y direction).

[0267] The first bridge portion (BRh1) may include a first driving voltage line (VDDLa) and a first common voltage line (VSSLa) arranged on a fifth conductive layer (1600), and the second bridge portion (BRh2) may include a second driving voltage line (VDDLb) and a second common voltage line (VSSLb) arranged on a fifth conductive layer (1600). The third bridge portion (BRv1) may include a third driving voltage line (VDDLc) and a third common voltage line (VSSLc) arranged on a fifth conductive layer (1600), and the fourth bridge portion (BRv2) may include a fourth driving voltage line (VDDLd) and a fourth common voltage line (VSSLd) arranged on a fifth conductive layer (1600).

[0268] The first driving voltage line (VDDLa) and the second driving voltage line (VDDLb) may be horizontal driving voltage lines (VDDLh, second voltage lines) connecting neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction). The third driving voltage line (VDDLc) and the fourth driving voltage line (VDDLd) may be vertical driving voltage lines (VDDLv, fifth voltage lines) connecting neighboring main island portions (11) in a second direction (e.g., y direction and / or -y direction).

[0269] The first common voltage line (VSSLa) and the second common voltage line (VSSLb) may be horizontal common voltage lines (VSSLh, third voltage lines) connecting neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction). The third common voltage line (VSSLc) and the fourth common voltage line (VSSLd) may be vertical common voltage lines (VSSLv, sixth voltage lines) connecting neighboring main island portions (11) in a second direction (e.g., y direction and / or -y direction).

[0270] That is, as illustrated in FIGS. 11b and 11c, the horizontal bridge portion (BRh) may include a horizontal driving voltage line (VDDLh) and a horizontal common voltage line (VSSLh), and the vertical bridge portion (BRv) may include a vertical driving voltage line (VDDLv) and a vertical common voltage line (VSSLv).

[0271] In the first curved portion (CNP1), the horizontal common voltage line (VSSLh) and the horizontal driving voltage line (VDDLh) may be arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curved portion to the outer boundary (COE) of the curved portion, and in the second curved portion (CNP2), the horizontal driving voltage line (VDDLh) and the horizontal common voltage line (VSSLh) may be arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curved portion to the outer boundary (COE) of the curved portion.

[0272] In the third curve section (CNP3), the vertical driving voltage line (VDDLv) and the vertical common voltage line (VSSLv) may be arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curve section to the outer boundary (COE) of the curve section, and in the fourth curve section (CNP4), the vertical common voltage line (VSSLv) and the vertical driving voltage line (VDDLv) may be arranged to be spaced apart from each other in the direction from the inner boundary (CIE) of the curve section to the outer boundary (COE) of the curve section.

[0273] The wiring closest to the inner boundary of the curved section (CIE) may be arranged to be spaced apart from the inner boundary of the curved section (CIE) by a first distance (d1), and the wiring closest to the outer boundary of the curved section (COE) may be arranged to be spaced apart from the outer boundary of the curved section (COE) by a second distance (d2). For example, as illustrated in FIG. 11b, in the second curved section (CNP2), the horizontal driving voltage line (VDDLh) may be arranged to be spaced apart from the inner boundary of the curved section (CIE) by a first distance (d1), and the horizontal common voltage line (VSSLh) may be spaced apart from the outer boundary of the curved section (COE) by a second distance (d2), and the first distance (d1) may be greater than the second distance (d2). Similarly, as illustrated in FIG. 11c, in the fourth curve section (CNP4), the vertical common voltage line (VSSLv) may be arranged to be spaced apart from the inner boundary (CIE) of the curve section by a first distance (d1), and the vertical driving voltage line (VDDLv) may be arranged to be spaced apart from the outer boundary (COE) of the curve section by a second distance (d2) smaller than the first distance (d1).

[0274] Each of the horizontal driving voltage line (VDDLh) and the vertical driving voltage line (VDDLv) may have a third width (w3) in a direction perpendicular to their respective extension directions. Each of the horizontal common voltage line (VSSLh) and the vertical common voltage line (VSSLv) may have a fourth width (w4) in a direction perpendicular to their respective extension directions. When a change in luminance uniformity due to a voltage drop of the driving voltage line (VDDL) is greater than a change in luminance uniformity due to a voltage drop of the common voltage line (VSSL), the third width (w3) may be greater than the fourth width (w4). For example, the third width (w3) may be 1.2 to 2 times greater than the fourth width (w4). In one embodiment, the third width (w3) may be 1.5 times greater than the fourth width (w4).

[0275] In another embodiment, if the change in luminance uniformity due to the voltage drop of the common voltage line (VSSL) is greater than the change in luminance uniformity due to the voltage drop of the driving voltage line (VDDL), the third width (w3) may be smaller than or equal to the fourth width (w4).

[0276] The sustain voltage line (VSL, see FIG. 9a) can compensate for the voltage drop of the driving voltage line (VDDL) by transmitting the sustain voltage (VSUS, see FIG. 6c) to the second node (N2, see FIG. 6c) during the initialization section and the data writing section. Therefore, the sustain voltage line (VSL, see FIG. 9a) may be arranged in a different layer (e.g., the third conductive layer (1400)) from the common voltage line (VSSL) and the driving voltage line (VDDL) in order to maximize the width, and may be configured as a single wire in the vertical bridge portion (BRv). The second width (w2, see FIG. 9c) may be larger than the third width (w3) and the fourth width (w4). In one embodiment, the second width (w2, see FIG. 9c) may have a width that is 1.2 to 2 times larger than the fourth width (w4).

[0277] As illustrated in Fig. 11d, the main island section (11) may include a first voltage connection line (VCL1), a second voltage connection line (VCL2), and a third voltage connection line (VCL3). The first voltage connection line (VCL1), the second voltage connection line (VCL2), and the third voltage connection line (VCL3) may be arranged in different layers from the first driving voltage line (VDDLa), the second driving voltage line (VDDLb), the third driving voltage line (VDDLc), and the fourth driving voltage line (VDDLd). For example, the first driving voltage line (VDDLa), the second driving voltage line (VDDLb), the third driving voltage line (VDDLc), and the fourth driving voltage line (VDDLd) can be connected to each other through the first voltage connection line (VCL1) and the second voltage connection line (VCL2) arranged on the third conductive layer (1400, see FIG. 8c) within the main island section (11) and the third voltage connection line (VCL3) arranged on the fourth conductive layer (1500, see FIG. 8d).

[0278] The third voltage connection lines (VCL3) are connected to the first semiconductor pattern (1101), the second semiconductor pattern (1102), or the third semiconductor pattern (1103) of the semiconductor layer (1100, see FIG. 8a) through the 18th conductive patterns (1407) of the third conductive layer (1400, see FIG. 8c), and can transmit a driving power voltage (VDD, see FIG. 6c) to one terminal of the eighth transistor (T8, see FIG. 8a) of the corresponding pixel driving circuit.

[0279] The driving voltage line (VDDL) may have a mesh structure connecting neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction) and neighboring main island portions (11) in a second direction (e.g., y direction and / or -y direction).

[0280] Since the driving voltage line (VDDL) transmits the driving power voltage (VDD, see FIG. 6c) to one terminal of the eighth transistor (T8, see FIG. 8a) located in the semiconductor layer (1100, see FIG. 8a), a mesh structure connected within the main island portion (11) can be formed using layers arranged between the fifth conductive layer (1600) and the semiconductor layer (1100). The first driving voltage line (VDDLa), the second driving voltage line (VDDLb), the third driving voltage line (VDDLc), and the fourth driving voltage line (VDDLd) can be connected to each other without contacting the common voltage line (VSSL) through the first voltage connection line (VCL1) and the second voltage connection line (VCL2) arranged on the third conductive layer (1400, see FIG. 8c) and the third voltage connection line (VCL3) arranged on the fourth conductive layer (1500, see FIG. 8d).

[0281] As illustrated in FIG. 11e, the first common voltage line (VSSLa), the second common voltage line (VSSLb), the third common voltage line (VSSLc), and the fourth common voltage line (VSSLd) may extend in a first direction (e.g., the x direction and / or the -x direction) and a second direction (e.g., the y direction and / or the -y direction) within the main island portion (11) and be connected to each other. The first common voltage line (VSSLa), the second common voltage line (VSSLb), the third common voltage line (VSSLc), and the fourth common voltage line (VSSLd) may be connected to each other in a fifth conductive layer (1600) and may be provided as a single body.

[0282] The common voltage line (VSSL) may have a mesh structure connecting neighboring main island portions (11) in a first direction (e.g., x direction and / or -x direction) and neighboring main island portions (11) in a second direction (e.g., y direction and / or -y direction).

[0283] Since the common voltage line (VSSL) is connected only to the second electrode pad (242, see FIG. 8f) of the sixth conductive layer (1700, see FIG. 8f), the first common voltage line (VSSLa), the second common voltage line (VSSLb), the third common voltage line (VSSLc), and the fourth common voltage line (VSSLd) are arranged on the fifth conductive layer (1600), which is the conductive layer closest to the sixth conductive layer (1700, see FIG. 8f), and can be extended and connected to each other within the main island portion (11).

[0284] Since the common voltage line (VSSL) has a mesh structure and transmits the common power voltage (VSS, see FIG. 6c) to each of the light-emitting elements through the second electrode pad (242, see FIG. 8f), there is no need to place a common power voltage line to transmit the common power voltage to the non-display area (NDA, see FIG. 1). Accordingly, the stretchable display device according to embodiments of the present invention can reduce dead space where an image is not displayed.

[0285] In one embodiment, when one electrode of the light-emitting element is connected to the driving voltage line (VDDL) side, for example, when the light-emitting element has an inverted structure, the first driving voltage line (VDDLa), the second driving voltage line (VDDLb), the third driving voltage line (VDDLc), and the fourth driving voltage line (VDDLd) may be connected to each other in the fifth conductive layer (1600) and formed as a single body. At this time, the first common voltage line (VSSLa), the second common voltage line (VSSLb), the third common voltage line (VSSLc), and the fourth common voltage line (VSSLd) may be connected to each other within the main island portion (11) through voltage connection lines that are arranged in a different layer from the first common voltage line (VSSLa), the second common voltage line (VSSLb), the third common voltage line (VSSLc), and the fourth common voltage line (VSSLd).

[0286] The stretchable display device according to the above-described embodiments can be used in various electronic devices capable of providing images. Here, the term "electronic device" refers to a device that uses electricity and can provide a predetermined image.

[0287] FIGS. 12A to 12G are perspective views schematically illustrating embodiments of an electronic device including a stretchable display device according to an embodiment of the present invention.

[0288] Referring to FIG. 12A, a stretchable display device according to an embodiment of the present invention may be utilized in a wearable electronic device (3100) that can be worn on a part of a user's body. The wearable electronic device (3100) may include a body portion (3110) and a display portion (3120) provided in the body portion (3110). The stretchable display device according to embodiments of the present invention may be utilized as the display portion (3120) of the wearable electronic device (3100). As illustrated in FIG. 12A, the wearable electronic device (3100) may be deformable. In one embodiment, it may be utilized as a smart watch or a smartphone, depending on the user's selection.

[0289] FIG. 12B illustrates a medical electronic device (3200). In one embodiment, the medical electronic device (3200) may include a body portion (3210) and a light-emitting portion (3220). A stretchable display device according to embodiments of the present invention may be used as the light-emitting portion (3220) of the medical electronic device (3200). The light-emitting portion (3220) may emit light of a certain wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one embodiment, the body portion (3210) may have a stretchable fiber material, and the light-emitting portion may have a structure that can be worn on the body of a user.

[0290] FIG. 12C illustrates an educational electronic device (3300). In one embodiment, the educational electronic device may include a display unit (3320) provided within a frame (3310). The display unit (3320) may utilize a stretchable display device according to embodiments of the present invention. The display unit (3320) may provide an image such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may stretch in the height direction (e.g., the z direction) to reflect the height of the wave, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially change in height along the direction of flowing lava to show the movement of lava in three dimensions. The educational electronic device (3300) may include a plurality of pins (or stroke units, 3330) arranged on the rear surface of the display unit (3320) so that the display unit (3320) may stretch in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., the z direction or the -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. Fig. 12c describes an educational electronic device (3300), but its use is not limited to providing certain image information.

[0291] While the electronic devices illustrated in FIGS. 12A to 12C are described as electronic devices whose shapes can be varied, the present invention is not limited thereto. As described in the embodiments below, the stretchable display devices according to the embodiments of the present invention can be used in electronic devices in which a portion capable of displaying an image (e.g., a screen) is fixed.

[0292] FIG. 12D illustrates a robot (3400) as another electronic device according to one embodiment of the present invention. The robot (3400) can recognize movement or objects using a camera unit (3440) and display a predetermined image to a user through a display unit (3420, 3430). In some embodiments, since the stretchable display devices according to one embodiment of the present invention can be stretched in various directions as described above, they can be assembled into a body frame having a hemispherical shape, and thus the robot (3400) can include a hemispherical display unit (3420, 3430).

[0293] FIG. 12E illustrates a vehicle display device (3500) as another electronic device according to one embodiment of the present invention. The vehicle display device (3500) may include a cluster (3510), a center information display (CID) (3520), and / or a co-driver display. Since the stretchable display device according to an embodiment of the present invention can be stretched in various directions, it may be used in the cluster (3510), the center information display (CID) (3520), and / or the co-driver display regardless of the shape of the internal frame of the vehicle.

[0294] Although FIG. 12e illustrates that the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display are each separate, the present invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected as one unit.

[0295] In some embodiments, a vehicle display device (3500) may include a button (3540) capable of displaying a predetermined image. Referring to the enlarged view of FIG. 12E, the hemispherical button (3540) may include an object (3542) that provides a button usability by moving in the z-direction or the -z-direction, and a stretchable display device disposed on the object (3542). In some embodiments, when the object (3542) has a three-dimensionally rounded surface, the stretchable display device may also have a three-dimensionally rounded surface.

[0296] FIG. 12F illustrates an electronic device according to one embodiment of the present invention, which is an electronic device (3600) for advertising or display purposes. In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on a fixed structure (3610), such as a wall or pillar. If the structure (3610) includes a recessed surface, as illustrated in FIG. 8F, the electronic device (3600) for advertising or display purposes may also be positioned along the recessed surface of the structure (3610). In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on the structure (3610) using a heat shrink film or the like.

[0297] FIG. 12G illustrates an electronic device according to one embodiment of the present invention as a controller (3700). The controller (3700) may include image-type buttons. For example, the controller (3700) may include first to third button areas (3720, 3730, 3740) in which a portion of the display unit (3710) protrudes in the z direction or protrudes in the -z direction (or is sunken in the z direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z direction, and the second button area (3730) may protrude in the -z direction (or is sunken in the z direction).

[0298] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and equivalent alternative embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. Multiple, mutually separated islands; First bridge sections connecting adjacent island sections in the first direction among the plurality of island sections and including a first voltage line, a second voltage line, and a third voltage line; and Second bridge sections, which connect adjacent island sections in a second direction intersecting with the first direction among the plurality of island sections, and include a fourth voltage line electrically connected to the first voltage line, a fifth voltage line electrically connected to the second voltage line, and a sixth voltage line electrically connected to the third voltage line; The above first voltage line and the above fourth voltage line are arranged on the first conductive layer, A display device, wherein the second voltage line, the fifth voltage line, the third voltage line, and the sixth voltage line are arranged on a second conductive layer on the first conductive layer.

2. In paragraph 1, A display device, wherein the first voltage line and the fourth voltage line extend into the plurality of islands and are connected to each other.

3. In paragraph 1, The above first voltage line has a first width in a direction perpendicular to the extension direction of the above first voltage line, A display device, wherein the fourth voltage line has a second width greater than the first width in a direction perpendicular to the extension direction of the fourth voltage line.

4. In paragraph 1, A display device, wherein the second bridge parts include only the fourth voltage line among the fourth voltage line, the fifth voltage line, and the sixth voltage line in the first conductive layer.

5. In paragraph 1, The above first bridge parts further include a first initialization voltage line and a second initialization voltage line, A display device, wherein the first initialization voltage line and the second initialization voltage line are arranged on the first conductive layer.

6. In paragraph 1, Each of the above multiple islands includes voltage connection lines, A display device, wherein the second voltage line and the fifth voltage line are electrically connected through the voltage connection lines within the plurality of island sections.

7. In paragraph 6, A display device, wherein the above voltage connection lines are arranged in a different layer from the second voltage line and the fifth voltage line.

8. In paragraph 6, The above voltage connection lines include first voltage connection lines and second voltage connection lines extending in the first direction, and third voltage connection lines extending in the second direction, The first voltage connection line and the second voltage connection line are arranged on the first conductive layer, A display device, wherein the third voltage connection line is arranged on a third conductive layer interposed between the first conductive layer and the second conductive layer.

9. In paragraph 8, The above second voltage line and the above fifth voltage line are connected to some of the above third voltage connection lines, A display device, wherein each of the third voltage connection lines is connected to the first voltage connection line and the second voltage connection line.

10. In paragraph 1, A display device, wherein the third voltage line and the sixth voltage line extend into the plurality of islands and are connected to each other.

11. In paragraph 1, The above second voltage line and the above fifth voltage line have a third width in a direction perpendicular to their respective extension directions, A display device, wherein the third voltage line and the sixth voltage line have a fourth width smaller than the third width in a direction perpendicular to their respective extension directions.

12. In paragraph 11, A display device, wherein the fourth voltage line has a second width greater than the fourth width in a direction perpendicular to the extension direction of the fourth voltage line.

13. In paragraph 1, Each of the above plurality of islands further includes a light-emitting element and a first electrode pad electrically connected to a first electrode of the light-emitting element and a second electrode pad electrically connected to a second electrode of the light-emitting element, A display device, wherein the first electrode pad and the second electrode pad are arranged on a fourth conductive layer on the second conductive layer.

14. In paragraph 1, Each of the above plurality of islands includes a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element, The above pixel driving circuit part, A driving transistor having a first terminal and a second terminal electrically connected to a gate and a first node; A data write transistor electrically connected to the first node and the data line; A first compensation transistor electrically connected to the gate of the driving transistor and the second terminal of the driving transistor; A first light-emitting control transistor electrically connected to the first node and the second node; A second light-emitting control transistor electrically connected to the second terminal of the light-emitting element and the driving transistor; A third light-emitting control transistor electrically connected to the second node and the driving voltage line; A second compensation transistor electrically connected to the second node and the maintenance voltage line; A storage capacitor electrically connected to the second node and the gate of the driving transistor; and A display device, comprising: an auxiliary capacitor electrically connected to the sustain voltage line and the first electrode of the light-emitting element.

15. In paragraph 14, A display device, wherein the above-mentioned maintenance voltage line includes the first voltage line and the fourth voltage line.

16. In paragraph 14, The above auxiliary capacitor includes a first electrode and a second electrode overlapping the first electrode in a plane, A display device, wherein the first voltage line and the fourth voltage line are electrically connected to the second electrode.

17. In paragraph 14, A display device, wherein the second electrode of the auxiliary capacitor is electrically connected to the first electrode of the light-emitting element.

18. In paragraph 14, A display device, wherein the driving voltage line includes the second voltage line and the fifth voltage line.

19. In paragraph 14, The second electrode of the above light-emitting element is electrically connected to a common voltage line, A display device, wherein the common voltage line includes the third voltage line and the sixth voltage line.

20. In paragraph 19, Each of the plurality of islands further includes a first electrode pad electrically connected to the first electrode of the light-emitting element and a second electrode pad electrically connected to the second electrode of the light-emitting element, A display device, wherein the third voltage line and the sixth voltage line extend into the plurality of islands and are connected to the second electrode pad.

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