System and method for generating partition at boot for computing system

Abstract

The present disclosure relates to a computing device for generating a partition model of a computing system. The computing device includes a computing processor and a memory. The memory stores computer-executable instructions that, when executed by the computing processor, cause operations to be performed, where the operations include: accessing information identifying the partition of the computing system, the partition corresponding to a subset of computing resources of the computing system, the computing resources comprising an array of computing tiles, and each computing tile of the computing array of tiles comprising an array of dies; and generating the model of the partition of the computing system at boot, wherein the model takes into account one or more manufacturing defects.

Description

TSLA.822WO PATENT SYSTEM AND METHOD FOR GENERATING PARTITION AT BOOT FOR COMPUTING SYSTEM CROSS-REFERENCE TO PRIORITY APPLICATION

[0001] This application claims the benefit of priority of U.S. Provisional Application No.63 / 586,778, filed September 29, 2023, and titled “SYSTEM AND METHOD FOR GENERATING PARTITION AT BOOT FOR COMPUTING SYSTEM,” the disclosure of which is hereby incorporated by reference in its entirety and for all purposes. BACKGROUND Technical Field

[0002] This disclosure relates to modeling and / or partitioning of computing hardware resources in a computing system based on the identification of defects in the hardware. Description of Related Technology

[0003] Certain computing systems can be used in and / or specifically configured for high performance computing and / or computationally intensive applications, such as neural network training, neural network inference, machine learning, artificial intelligence, complex simulations, or the like. In some applications, a computing system can be used to perform neural network training. For example, such neural network training can generate data for an autopilot system for a vehicle (e.g., an automobile), other autonomous vehicle functionality, or Advanced Driving Assistance System (ADAS) functionality.

[0004] In high performance computing systems, there can be a high density of hardware resources, such as integrated circuit (IC) dies. In such computing systems, it can be desirable to analyze one or more portions of the computing systems. In such computing systems with large numbers of processing IC dies, there are technical challenges associated with analyzing and modeling the functionality of the processing IC dies and the associated computing system in the presence of various defects and / or errors.TSLA.822WO PATENT SUMMARY OF CERTAIN INVENTIVE ASPECTS

[0005] The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some prominent features of this disclosure will now be briefly described.

[0006] One aspect of the present disclosure is a computing device for generating a model of a partition of a computing system. The computing device includes a computing processor and a memory storing computer-executable instructions that, when executed by the computing processor, cause operations to be performed. The operations include accessing information identifying the partition of the computing system and generating the model of the partition of the computing system at boot. The model takes into account one or more manufacturing defects. The partition corresponds to a subset of computing resources of the computing system. The computing resources include an array of computing tiles. Each computing tile of the computing array of tiles includes an array of dies.

[0007] In one embodiment, the model can take into account one or more operational defects.

[0008] In one embodiment, the operations can include dynamically updating the partition.

[0009] In one embodiment, the operations can include identifying the one or more manufacturing defects before initiating the boot of the computing system. In addition, the operations can include updating the model after the boot of the computing system.

[0010] In one embodiment, the memory can be configured to store corrective actions corresponding to the one or more manufacturing defects. The operations can include applying one or more corresponding corrective actions to the one or more manufacturing defects. The model can reflect the corrective actions.

[0011] In one embodiment, the one or more manufacturing defects can include a manufacturing defect associated with a computing tile of the array of computing tiles.

[0012] In one embodiment, the one or more manufacturing defects can include a manufacturing defect associated with a die of the array of dies of a computing tile of the array of computing tiles.TSLA.822WO PATENT

[0013] In one embodiment, the one or more manufacturing defects can include a manufacturing defect associated with a node of a die of the array of dies of a computing tile of the array of computing tiles.

[0014] In one embodiment, the operations can include scheduling computing tasks for the partition based on the model.

[0015] Another aspect of the present disclosure is a method of generating a model of a partition of a computing system. The method includes accessing information identifying the partition of the computing system and generating, using a computing device, the model of the partition of the computing system at boot. The partition corresponds to a subset of computing resources of the computing system. The computing resources include an array of computing tiles. Each computing tile of the computing array of tiles includes an array of dies. The model takes into account one or more manufacturing defects.

[0016] In one embodiment, the methods can also include updating the model of the partition after the boot of the computing system to account for one or more operational defects.

[0017] In one embodiment, the methods can also include identifying the one or more manufacturing defects before initiating the boot of the computing system.

[0018] In one embodiment, the methods can also include applying a corrective action to account for at least one of the one or more defects, wherein the model reflects the corrective action.

[0019] In one embodiment, the methods can also include scheduling computing tasks for the partition based on the model.

[0020] In one embodiment, the one or more manufacturing defects can include a manufacturing defect associated with a die of the array of dies of a computing tile of the array of computing tiles.

[0021] In one embodiment, the one or more manufacturing defects can include a manufacturing defect associated with a node of a die of the array of dies of a computing tile of the array of computing tiles.

[0022] One aspect of the present disclosure is a system, including computing resources comprising an array of computing tiles, in which each computing tile of the computing array of tiles includes an array of dies and a computing device in communication with the computing resources. The computing device includes a computing processor and aTSLA.822WO PATENT memory storing computer-executable instructions that, when executed by the computing processor, cause operations to be performed. The operations include accessing information identifying the partition of the computing system and generating the model of the partition of the computing system at boot. The model takes into account one or more manufacturing defects. The partition corresponds to a subset of computing resources of the computing system. The computing resources include an array of computing tiles. Each computing tile of the computing array of tiles includes an array of dies.

[0023] In one embodiment, the operations can include scheduling computing tasks for the partition based on the model. In addition, the computing resources can be configured to execute the computing tasks with the partition in response to the computing device scheduling the computing tasks.

[0024] In one embodiment, the operations can include dynamically updating the model of the partition based at least on the operation of the computing resources.

[0025] For purposes of summarizing the disclosure, certain aspects, advantages, and novel features of the innovations have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, the innovations may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Embodiments of this disclosure will be described by way of non-limiting examples, with reference to the accompanying drawings.

[0027] FIG.1 is a block diagram which illustrates an example of a hierarchy of the computing resources of the computing system.

[0028] FIG. 2 is a block diagram which describes an example of a computing system connected to a computing device in accordance with various embodiments disclosed herein.

[0029] FIG. 3 is a block diagram which illustrates an example of a computing system with partitioned computing resources.TSLA.822WO PATENT

[0030] FIG.4 is a data flow diagram which illustrates an example of a process that can collect defect information on partitions of a computing system.

[0031] FIG. 5 illustrates an example of a cabinet that includes one or more processing systems according to embodiments disclosed herein DETAILED DESCRIPTION

[0032] The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in a multitude of different ways, for example, as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals and / or terms can indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and / or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

[0033] The disclosure relates to generating a model of the functionality of a partition of a computing system at boot and / or managing defects in a dynamic partition of a computing system. Although certain components of the computing system can be instances of the same design, there can be differences in performance of the different instances of the same design due to manufacturing, environmental and / or operational factors. For example, different instances of the same design can operate with different parameters, such as but not limited to clock frequency, supply voltage, bandwidth, etc. Generating the model can take into account such variations and / or other defects in a computing system.

[0034] Generating the model can involve accessing information associated with defects in the computing system hardware. The information associated with the defects can be generated based on identifying and analyzing defects in the computing resources of a computing system and applying corrective actions. More specifically, aspects of the present disclosure provide a system for generating a model of a partition of a computing system at boot using information associated with defects of the partition. The defects can be hardware defects in the computing system, such as but not limited to any flaw, malfunction, or imperfection in a physical component of the computing system, where such defects can affect one or more ofTSLA.822WO PATENT the hardware component’s normal operation, performance, or reliability. For example, the defect can include manufacturing defects that occurred during a manufacturing process, electrical defects associated with making electrical connections such as short circuits, thermal defects due to the overheating of the hardware components, the like, or any suitable combination thereof.

[0035] In some embodiments, systems disclosed herein can account for the defects by applying corrective actions. In addition, after the booting process, the system can automatically apply corrective actions to the identified defects. In some embodiments, the corrective action can include partitioning the computing system hardware and excluding the hardware components with identified defects.

[0036] In accordance with some embodiments, lower level hardware components can be built into a large scalable computing system. Such a computing system can be used for machine learning applications, such as neural network training. Example computing systems will be described with components at various levels of hierarchy.

[0037] The computing systems disclosed herein can include various levels of hierarchy of computing resources to perform computing tasks. For example, a computing system can include tiles (e.g., “computing tiles”), and each computing tile can include a plurality of dies packaged together. A computing tile can include a system on a wafer that includes a plurality of IC dies and an array of voltage regulating modules, where each of the voltage regulating modules is configured to provide a power supply voltage to a respective IC die of the system on a wafer. The computing tiles can also include integrated cooling solutions. Each die can include a plurality of nodes (e.g., leaf nodes). Each node can function as a computing node, global node, interface node (e.g., routing node), or the like. A system tray can include an array of connected computing tiles. A computing cabinet can include one or more system trays. A computing tile can be connected with one or more other computing tiles on the same system tray and / or on a system tray in an adjacent computing cabinet in the computing system.

[0038] Contiguous hardware components of a computing system can be combined to create operational units called partitions that are used to run relatively large computing tasks, such as but not limited to machine learning training loads using software partitioning overlayed over the hardware partition.TSLA.822WO PATENT

[0039] In some embodiments, hardware custom silicon components in these computing systems have a profile that undergoes dynamic updates in the field based on their initial manufacturing, testing, operating characteristics, as well as system in field usage. Information associated with defects disclosed herein can be dynamic. Such information can be updated as a computing system boots and / or is operated.

[0040] A per silicon component dynamic profile can allow for in field repairs, such as but not limited to reroutes, masking, controlling power levels, disabling of components that may be beyond repair, or the like.

[0041] The maintenance of the per component profile in a software based system allows for fast in-field detection and adapting a partition to underlying hardware changes.

[0042] As the hardware components become part of different topologies, the profile per hardware can use a unique global identifier that stays associated with the silicon hardware component, hence allowing for reuse across topologies that use the same silicon.

[0043] The system allows for future scalability as the profile can be added to based on unique defect / feature identification keys for future defects that do not fit the existing profile.

[0044] In some embodiments, ongoing analyses of defect trends and corrective actions can be implemented.

[0045] As the demand for computing resources of a computing system increases, a high density computing system is desired. As discussed above, certain computing systems can include one or more computing tiles, and each computing tile can include an array of dies. During the testing or prior to installing the computing tiles in a computing system, the performance of the computing tiles can be analyzed to ensure that these computing tiles are functional and meet performance specifications. Moreover, system level testing can identify defects associated with connected computing tiles that are not identified by testing individual computing tiles. Accordingly, there can be defects associated with manufacturing computing tiles and defects associated with computing tiles connected to computing tiles and / or other components in a larger computing system.

[0046] Identifying and tracking defects in a large scale computing system can be challenging. Moreover, modeling the functionality of a partition of a computing system with defects and / or errors at different levels, such as but not limited to a die level, a computing tile level, a system tray level, or a computing system level, and the associated corrective actionsTSLA.822WO PATENT can be challenging. Such modeling can be useful in scheduling computing tasks to a partition of the computing system.

[0047] To address at least a portion of the technical challenges described above, one or more aspects of the present disclosure relate to a computing device that can generate a model of a partition of the computing system. The model can include various hierarchies and account for defects and corrective actions applied to specific hardware at various levels of hierarchy. The computing device disclosed herein can be communicatively coupled with the computing system and can partition the computing resources of the computing system. The computing device can store information associated with defects of the computing system. In some applications, the computing device can analyze one or more partitions to identify any defects. In some aspects, the identification of defects is performed by monitoring the performance metrics of the dies based on each die’s design performance specification. After identifying the defects, information associated with the defects can be stored by the computing device. The computing device can apply corrective actions to account for the defects in modeling the computing resources of the partition. In some instances, the computing device disclosed herein can identify defects within the partitioned computing resources (e.g., partitioned tiles, as described below) before booting the computing system. Then a model of the partition can be generated at boot. This model can be used in scheduling computing tasks to the partition and / or in generating inputs for any partitions of the hardware. A detailed description of these aspects is provided below with reference to the appended drawings. This disclosure is not limited to the specific computing performance specifications mentioned herein, and they can be adjusted based on specific applications.

[0048] In some embodiments, the model can be referred to as a partition model (e.g., partition model of the computing system). The model can refer to a partitioning model of the computing system hardware. The model can provide various partitioning configurations of the computing system hardware so that the various partitioned computing system hardware can be dynamically allocated based on computing tasks. In some embodiments, the model can exclude one or more defective and / or damaged hardware portions of the computing system. In some embodiments, the computing device can schedule tasks (e.g., computing tasks) that each task can be scheduled to be performed by one of the partitions. In some embodiments, the model includes various partitions, and the computing device can select one or more partitionsTSLA.822WO PATENT based on the scheduled tasks. The computing system hardware can refer to the hardware components designed to perform specific tasks, such as one or more of processing data, executing instructions, performing computations, temporarily or permanently storing data, managing data flow and interactions (e.g., input / output), and regulating power supply to various components. Any suitable hardware components can be used within the computing system to implement the system’s specific functions.

[0049] FIG. 1 illustrates an example hierarchy of computing resources of a computing system 100. As illustrated in FIG. 1, the computing system 100 can include a plurality of tiles 102. Each tile 102 can be configured to operate as a logical tile, such as a computing tile, an input / output (I / O) tile, or a memory tile. Additionally, the tile 102 can include a plurality of dies 104. These dies 104 can provide specific functionality of the corresponding tile. For example, if the tile 102 is a processing unit configured to perform core operations, such as executing instructions from programs, performing arithmetic and logic operations, or the like, the dies 104 can include without limitation computing dies configured to execute arithmetic and logical operations, control dies configured to directs data communication by fetching and decoding instructions, signal processing dies configured to handle video, audio, and communication signal processing, field-programmable gate array dies configured to be programmed to perform specific tasks or functions, non-volatile memory die configured to store permanent data, volatile memory die configured to store temporary data, or I / O dies configured to manage and control communication between the dies included in the tile and / or with the external hardware component such as other tile or other computing systems. In some embodiments, the die 104 can include a plurality of nodes 106 (e.g., leaf nodes). Each node 106 can also be a computing node, an I / O node, or a memory node. These specific types of tiles 102, dies 104, and nodes 106 are provided as illustrative examples. Any suitable numbers and / or types of the tiles 102, dies 104, and nodes 106 can be implemented for a particular computing system 100.

[0050] In some aspects of this disclosure, the computing system can be communicatively coupled with a computing device. FIG. 2 illustrates an example of computing system 200 connected to a computing device 210. The computing system 200 illustrated in FIG. 2 can be another representation of the computing system 100 of FIG. 1, forTSLA.822WO PATENT example. The computing system 200 illustrates computing resources and other peripheral hardware components, as described herein.

[0051] The computing device 210 illustrated in FIG. 2 can include one or more processors and memory to generate a model of a partition of the computing systems. In some embodiments, the computing device 210 can store information associated with one or more defects of the computing resources of the computing system 200, account for the defects, and generate a model of how a partition of the computing system 200 works at boot.

[0052] In some aspects, the computing device 210 can store information associated with defects in various hierarchies of the computing resources of the computing system 200. For example, the computing device 210 can store information associated with defects at the tile 102 level (e.g., identifying defective tiles and the types of defects), die 104 level (e.g., identifying defective dies and the types of defects), and / or node level 106 (e.g., identifying defective nodes and the types of defects). In some embodiments, the computing device 210 can store information associated with defects above the tile level (e.g., defects associated with connections between tiles).

[0053] In some instances, the computing system 200 and computing device 210 are connected via a network 220, which can be wireless or wired. This network 220 can comprise any suitable combination of wired and / or wireless networks, such as one or more direct communication channels, local area networks, wide area networks, personal area networks, and / or the Internet. In some examples, the network 220 can include, without limitation, a private or semi-private network, a wireless local area network, or the like. The network 220 can use any suitable protocols and components for communicating via the Internet or any of the other aforementioned types of networks.

[0054] In some embodiments, the network 220 can include a specific type of data bus used for transmitting data. In some embodiments, the computing device 210 can include any suitable computing device(s), such as one or more server computers, one or more desktop computers, or the like. In some embodiments, the computing device 210 can store instructions and execute the instructions to perform one or more operations of the embodiments disclosed herein. In various embodiments, a user (e.g., system operator, administrator, developer, etc.) may interact with the computing system 200 by utilizing the computing device 210. For example, the computing device 210 can obtain tile configuration information, operationalTSLA.822WO PATENT parameters of each tile (and dies included in each tile), configuration information of each tile and dies included in each tile, interface information, and the like from the computing system 200.

[0055] As further illustrated in FIG. 2 above, the computing system 200 can also include various peripherals hardware components, such as a host 202, memory 204 (e.g., high bandwidth memory (HBM)), and an interface processor 206 (e.g., DIPs). In some embodiments, the host 202 is configured to control and manage the hardware resources of the computing system 200. For example, the host 202 can analyze the performance of each tile 102 and / or each die 104 and node 106 included in the tile 102. In some examples, the host 202 can analyze the performance of one or more tiles 102 included in the same illustrated row with the host 202. The host 202 can include a host processor and memory to monitor the performance of tiles 102 and their dies 104 and / or nodes 106. In some examples, the defects identified during the performance analysis can be stored in memory of the host 202. In some embodiments, the host 202 can provide information identifying the defects to the computing device 210 via the controller 230. For example, the controller 230 provides an interface to connect with the computing device 210 via the network 220. In various embodiments, the computing system 200 can include one or more controllers 230 that can be utilized to communicate various data between the computing system 200 and the computing device 210. For example, the controller 230 can be communicatively coupled with one or more hosts 202 and transmit the stored data (such as the defect information identifying defects of the tiles 102 and / or dies 104 and / or nodes 106) in the host 202 to the computing device 210.

[0056] In some aspects of the present disclosure, the computing system 200 can be dynamically partitioned. FIG.3 illustrates an example of computing system 300 with partitions of computing resources. The computing system 300 corresponds to the computing system 200 illustrated in FIG. 2. As shown in FIG. 3, the computing resources of the computing system 300 can be partitioned into hardware partitions, such as partitions 1-4. For example, a defective portion 310 (e.g., a group of IC dies of a tile) can be identified as having defects. In this example, the host 202A can store information identifying the defective portion 310, and the information can be transmitted to the computing device 210 (shown in FIG. 2), for example, via the controller 230 and the network 220.TSLA.822WO PATENT

[0057] In some examples, the computing system 300 can be partitioned dynamically. For example, the host 202A can identify that the IC dies included in the defective portion 310 have degraded and / or unsuitable performance. In this example, the computing device 210, after receiving the information identifying the defective portion 310 can generate the partitions (e.g., partitions 1, 2, and 3) that exclude the defective portion 310. The partitioning can be performed at the die level. As shown in FIG. 3, partitions 1, 2, and 3 can include a portion of a computing tile. There can be overlap between partitions. For example, partition 3 overlaps with part of partition 1 and part of partition 2 in FIG. 2. When there is overlap between partitions, computing tasks can be scheduled to avoid hardware usage conflicts. In some embodiments, the model can exclude one or more defective and / or damaged hardware portions of the computing system. In some embodiments, the computing device can schedule tasks (e.g., computing tasks) that each task can be scheduled to be performed by one of the partitions. In some embodiments, the model includes various partitions, and the computing device can select one or more partitions based on the scheduled tasks.

[0058] In some embodiments, the computing device 210 of FIG. 2 can store information associated with defects on the partitions. The host 202 can store the information identifying one or more defective tiles 102 and / or one or more defective dies 104. This information identifying defects can be provided to the computing device 210.

[0059] In some embodiments, the computing device 210 can identify defects on the partitions. In some applications, the computing device 210 may obtain computing resource configuration information from the computing system 300 and generate the partitions. In some cases, the computing system 300 can have one or more partitioned configurations, and the computing device 210 can obtain these partitioned configurations information from the computing system 300.

[0060] In various embodiments, the computing device 210 can identify defective dies based on the designed specifications of each node 106 of FIG. 1. In these embodiments, identifying the defective nodes 106 can be performed by measuring performance metrics of each node 106, such as measuring operating frequency, bandwidth, temperature, clock speed, communication latency, computational latency, and the like. For instance, if the dies 104 are unable to route data, communicate with other dies or tiles, or do so with subpar performance (e.g., lower bandwidth and / or higher latency), it can be identified as defective. In otherTSLA.822WO PATENT examples, if the computing nodes 106 are performing the computation of logic (e.g., task) with decreased performance or are unable to perform the computation, the computing nodes 106 can be identified as defective nodes.

[0061] In some embodiments, the computing device 210 can determine the defects before operating the computing tiles 102 (e.g., before operating the dies 104 included in the computing tiles 102). For example, if a computing tile 102 is newly implemented into the computing system 300, the computing device 210 may identify one or more defective dies included in these computing tiles 102. For instance, defects can be caused during the manufacturing process, and these defects can be referred to as manufacturing defects.

[0062] In some embodiments, the performance of the computing tiles 102 and / or the dies 104 can be monitored. For example, one or more hosts 202 and / or the computing device 210 can monitor the performance of the computing tiles 102 and / or the dies 104. In some such examples, the computing device 210 can communicate with the host 202, such that the computing device 210 can identify the performance profile for the computing tiles 102 and / or the dies 104 associated with the host 202 can determine whether the performance profile of the computing tiles 102 and / or the dies 104 is below a threshold (e.g., pre-defined performance metrics). In this embodiment, one or more defective dies that do not meet design specifications (e.g., the performance profile identified as below the threshold) can be identified. For example, one or more dies can have a higher operating temperature, or one or more dies can have decreased performance or the like. More specifically, if the dies are designed to perform computation and their operating clock speed does not meet the designed specification, they can be identified as defective dies. Furthermore, if the dies are I / O dies, and their communication latency or bandwidth is lower than the designed specification, these dies can be identified as defective dies.

[0063] In some aspects, the computing device 210 and / or one or more hosts 202 can identify node-level defects of one or more nodes 106 of FIG.1. For example, if any of the nodes (e.g., computing nodes, I / O nodes, and memory nodes) included in a die have a higher operating temperature, these nodes can be identified as defective nodes. Thus, the dies that include these defective nodes can be identified as defective dies. In addition, if any computing node has decreased performance that does not meet a design specification, the dies that include these computing nodes can be identified as defective dies. Furthermore, if any of the memoryTSLA.822WO PATENT nodes have decreased performance and do not meet the specification, the dies that include these computing nodes can be identified as defective dies.

[0064] The computing device 210 and / or one or more hosts 202 can also be configured to apply one or more corrective actions to account for the various defects. For example, the computing device 210 can store various corrective actions, each associated with a specific type of defect. Thus, after identifying the defects, the computing device 210 can apply the corresponding corrective action(s). Example corrective actions include, but are not limited to, routing around defective hardware, not using defective hardware, not storing defective memory, etc.

[0065] In some embodiments, the computing device 210 can be configured to track the defects. For example, the computing device 210 can store information associated with manufacturing defects included in one or more dies and / or computing tiles. In this example, the computing device 210 can apply the corrective actions corresponding to the identified defects. After applying the corrective action to correct the defects in the dies (and / or nodes within the dies), these dies can be initiated in an operating environment. Then, the computing device 210 can monitor the operating parameters of these dies. In this example, if the computing device 210 identified additional defective dies during the operation, these defective dies can be categorized as operational defects. Thus, the computing device 210 can account for these different types of causes of defects, manufacturing, or operational defects, and apply corrective actions accordingly.

[0066] FIG.4 illustrates an example process 400 that can collect defect information of a partition of a computing system for boot. Collecting the defect information that includes both the manufacturer defects and operational defects can be advantageous because the computing device 210, after booting the partitioned tiles of a computing system, such as the computing system 200 of FIG.2 and / or the computing system 300 of FIG.3, can automatically apply corrective actions associated with these defects during the booting process. The example process described in FIG. 4 is illustrative and should not be understood as limiting aspects of the present disclosure.

[0067] The process 400 of FIG. 4 can generate a model of the functionality of a partition of a computing system, such as the computing system 200 of FIG. 2. The process 400 can be performed by the computing device 210 of FIG. 2. The model generated by theTSLA.822WO PATENT process 400 can be used to partition the computing system 300, as shown in FIG.3, for example. The process 400 can involve dynamically updating information associated with defects and / or dynamically reacting to defects. With the process 400 of FIG.4, a computing system can boot quickly while the model of the partition of the computing system is generated.

[0068] With the process 400, the computing resource of a computing system can be efficiently allocated by partitioning the computing resources accounting for one or more defective tiles 102, one or more defective dies 104, and / or one or more defective nodes 106. Process 400 can be applied to generate a model of a plurality of partitions. For illustrative purposes, the process 400 is described with reference to components of FIGs. 1-2. In some embodiments, the computing device 210 includes memory storing instructions that when executed by a processor of the computing device 210, cause operations to be performed. The operations can perform one or more of the steps 410-480 of the process 400.

[0069] The process 400 can be initiated at step 410. At step 410, information associated with the identified defects of computing resources of a computing system can be provided. For example, the defect information identifying defects of the computing resources can be stored in a host 202, and the computing device 210 can receive the defect information from the computing system 200 via the controller 230. The identified defects can be known defects caused by the manufacturing process. In some embodiments, these identified defects are known defects for one or more of a computing tile 102, a die 104, or a node 106 of a die. The information associated with the identified defects can be provided by a manufacturer and / or generated from testing components.

[0070] At step 420, the computing device 210 can store the information associated with identified defects in the computing resource in the memory of the computing device 210. For example, this information can be stored as a file. The file can have a specific format that can be readable by the computing device 210. Any suitable file format can be used.

[0071] At step 430, the computing device 210 can also analyze defects in the computing resources of the computing system 200. In some embodiments, the step 430 can be performed post-manufacture, such as testing after the computing system 200 is assembled. In some examples, the computing device 210 may identify additional defects other than the identified defects associated with manufacturing components of the computing system. In this example, the additional defects can also be referred to as manufacture defects because theTSLA.822WO PATENT additional defects were identified before initiating (e.g., operating the partitioned tiles). More specifically, the additional defects could be the manufactured defects that were not identified previously. Such defects can result from connecting components (e.g., computing tiles) of a computing system, for example.

[0072] At step 440, the computing device 210 can collect the information associated with the identified defects provided at step 410 and the additional defects identified at step 430.

[0073] At step 450, defects in the field can be identified. In some embodiments, the computing device 210 can test computing resources under an operating environment with operating power supply, operating frequency, temperature, etc. During or after testing the computing resources, the computing device 210 may identify additional defects different from the defects collected at step 440. These additional defects at step 450 can be collected at step 460.

[0074] For example, the computing device 210 can monitor the performance of the computing tiles 102 and / or the dies 104 by communicating with the host 202. The computing device 210 can identify the performance profile for the computing tiles 102 and / or the dies 104 associated with the host 202 and determine whether the performance profile of the computing tiles 102 and / or the dies 104 is below a threshold (e.g., pre-defined performance metrics). In this embodiment, one or more defective dies 104 that do not meet design specifications (e.g., the performance profile identified as below the threshold) can be identified at step 450. In some embodiments, the performance profile can include performance metrics corresponding to attributes of the computing tiles 102 and / or the dies 104. For example, computing tiles 102 and / or the dies 104 dedicated to performing logic computations may have a performance metric corresponding to the clock speed or operational frequency of the computing tiles 102 and / or the dies 104. Such performance metrics and profiles can be determined based on the functionality of the computing tiles 102 and / or the dies 104, for example. Information associated with the additional in field defects identified at step 450 can be collected at step 460.

[0075] In some embodiments, step 470 involves storing defect information to a database. The defect information stored at step 470 can include the types of defects identified at step 450. For example, during testing of the partitioned tiles at step 450, one or more operational parameters of the partitioned tiles may represent performance parameters, non-TSLA.822WO PATENT compliant with the designed specification. In this example, the computing device 210 may access to the database to identify the operational defects related to the non-compliant performance parameters.

[0076] The defects identified at steps 410, 430, 450, and 470 are collected at the booting process, for example, partition at boot 480. The information associated with defects can be used to generate a model of the functionality of a partition at boot. Thus, the computing device 210 upon booting the partition can automatically generate a model that takes into account the collected defects. The model can then be used to schedule computing tasks and / or to increase usage of the partition. Although FIG.4 illustrates a particular order of operations, the steps of the process 400 may be performed in any suitable order, serially, or at least partially in parallel.

[0077] In accordance with embodiments disclosed herein, a plurality of tiles 102 are utilized as computing resources of a computing system. For example, FIG.5 illustrates an example of two cabinets 600 that can include a plurality of computing tiles 102, where each tile 102 can include an array of dies. The array of dies can be a 3 by 3, 4 by 4, 5 by 5, 6 by 6, or 7 by 7 array of the dies 104. A system on a wafer can include the array of dies. As shown in FIG.6, the cabinet 600 can include one or more sockets 602 or guide rails, and a system tray that includes an array of computing tiles 102 can be inserted into the cabinet 600 via the socket 602. Each cabinet 600 of FIG. 5 includes a cabinet structure arranged to receive two system trays, where each system tray includes an array of computing tiles 102 (for example, a 2 x 3 array of computing tiles 102). Thus, multiple computing tiles 102 can be integrated into the cabinet 600. Any suitable type of sockets and number of sockets can be used for a specific application.

[0078] Any of the methods disclosed herein (or any portion thereof) can be performed in association with specific instructions stored on a non-transitory computer readable storage medium being executed by one or more processors.

[0079] Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled,” as generally used herein, refers to two or more elements that may be either directly connected, or connected byTSLA.822WO PATENT way of one or more intermediate elements. Likewise, the word “connected,” as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number, respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0080] Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and / or states. Thus, such conditional language is not generally intended to imply that features, elements, and / or states are in any way required for one or more embodiments.

[0081] The foregoing description has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the inventions to the precise forms described. Many modifications and variations are possible in view of the above teachings. Others skilled in the art are thereby enabled to best utilize the techniques and various embodiments with various modifications as suited to various uses.

[0082] Although the disclosure and examples have been described with reference to the accompanying drawings, various changes and modifications will become apparent to those skilled in the art. Such changes and modifications are to be understood as being included within the scope of the disclosure.

Claims

TSLA.822WO PATENT WHAT IS CLAIMED IS:

1. A computing device for generating a model of a partition of a computing system, the computing device comprising: a computing processor; and a memory storing computer-executable instructions that, when executed by the computing processor, cause operations to be performed, the operations comprising: accessing information identifying the partition of the computing system, the partition corresponding to a subset of computing resources of the computing system, the computing resources comprising an array of computing tiles, and each computing tile of the computing array of tiles comprising an array of dies; and generating the model of the partition of the computing system at boot, wherein the model takes into account one or more manufacturing defects.

2. The computing device of Claim 1, wherein the model takes into account one or more operational defects.

3. The computing device of Claim 1 or 2, wherein the operations comprise dynamically updating the partition.

4. The computing device of any of Claims 1 to 3, wherein the operations comprise identifying the one or more manufacturing defects before initiating the boot of the computing system.

5. The computing device of any of Claims 1 to 4, wherein the operations comprise updating the model after the boot of the computing system.

6. The computing device of any of Claims 1 to 5, wherein the memory is configured to store corrective actions corresponding to the one or more manufacturing defects, and wherein the operations comprise applying one or more corresponding corrective actions to the one or more manufacturing defects, and wherein the model reflects the corrective actions.TSLA.822WO PATENT 7. The computing device of any of Claims 1 to 6, wherein the one or more manufacturing defects comprise a manufacturing defect associated with a computing tile of the array of computing tiles.

8. The computing device of any of Claims 1 to 7, wherein the one or more manufacturing defects comprise a manufacturing defect associated with a die of the array of dies of a computing tile of the array of computing tiles.

9. The computing device of any of Claims 1 to 8, wherein the one or more manufacturing defects comprise a manufacturing defect associated with a node of a die of the array of dies of a computing tile of the array of computing tiles.

10. The computing device of any of Claims 1 to 9, wherein the operations comprise scheduling computing tasks for the partition based on the model.

11. A method of generating a model of a partition of a computing system, the method comprising: accessing information identifying the partition of the computing system, the partition corresponding to a subset of computing resources of the computing system, the computing resources comprising an array of computing tiles, and each computing tile of the computing array of tiles comprising an array of dies; and generating, using a computing device, the model of the partition of the computing system at boot, wherein the model takes into account one or more manufacturing defects.

12. The method of Claim 11, further comprising updating the model of the partition after the boot of the computing system to account for one or more operational defects.

13. The method of any of Claims 11 or 12, further comprising identifying the one or more manufacturing defects before initiating the boot of the computing system.TSLA.822WO PATENT 14. The method of any of Claims 11 to 13, further comprising applying a corrective action to account for at least one of the one or more defects, wherein the model reflects the corrective action.

15. The method of any of Claims 11 to 14, further comprising scheduling computing tasks for the partition based on the model.

16. The method of any of Claims 11 to 15, wherein the one or more manufacturing defects comprise a manufacturing defect associated with a die of the array of dies of a computing tile of the array of computing tiles.

17. The method of any of Claims 11 to 16, wherein the one or more manufacturing defects comprise a manufacturing defect associated with a node of a die of the array of dies of a computing tile of the array of computing tiles.

18. A system comprising: computing resources comprising an array of computing tiles, each computing tile of the computing array of tiles comprising an array of dies; and a computing device in communication with the computing resources, the computing device comprising: a computing processor; and a memory storing computer-executable instructions that, when executed by the computing processor, cause operations to be performed, the operations comprising: accessing information identifying a partition of the computing resources, the partition corresponding to a subset of the computing resources; and generating a model of the partition of the computing resources at boot, wherein the model takes into account one or more manufacturing defects.TSLA.822WO PATENT 19. The computing device of Claim 18, wherein the operations further comprise scheduling computing tasks for the partition based on the model.

20. The computing device of Claim 18 or 19, wherein the computing resources are configured to execute the computing tasks with the partition in response to the computing device scheduling the computing tasks.

21. The computing device of Claim 19 or 20, wherein the operations further comprise dynamically updating the model of the partition based at least on operation of the computing resources.

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