Data management method, method for check data, and related apparatuses

Abstract

The embodiments of the present application relate to the field of application of storage devices. Disclosed are a data management method, a method for check data, and related apparatuses. The data management method comprises: establishing a second memory mapping relationship between a host system and each flash memory device; storing, in several flash memory devices, several data blocks corresponding to stripe data, wherein each flash memory device has a first memory mapping relationship with other flash memory devices; determining a target flash memory device, which serves as a computing engine; and sending a check command to the target flash memory device, such that the target flash memory device performs data calculation on the several data blocks on the basis of the second memory mapping relationship, so as to generate and store check data. In the present application, check data can be obtained by means of the calculation of a flash memory device, and a dedicated redundant array of independent disks (RAID) controller is not needed to calculate the check data. Therefore, the processes of transmitting check data between an RAID controller and a storage device can be reduced, and the bandwidth requirements of an RAID system are reduced.

Description

Data management method, data verification method and related device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on October 26, 2023, with application number 202311402981.8, and application name “Data management method, method for verifying data and related devices”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of storage device applications, and in particular to a data management method, a data verification method, and related devices. Background Art

[0004] A redundant array of independent disks (RAID) is a storage array composed of multiple storage devices that can operate simultaneously. RAID technology can improve the read and write performance of a storage array or provide data redundancy protection.

[0005] Currently, RAID systems typically consist of a processor system, a memory system, a communication bus, a RAID controller, and a storage array. During the implementation of this application, the inventors discovered that the prior art has at least the following problems:

[0006] When generating verification data, the RAID controller needs to receive all relevant data of the stripe for calculation, and then store the obtained verification data in a storage device in the storage array; when recovering data of a certain data in the stripe, the RAID controller needs to read the other data of the stripe as well as the verification data to perform the recovery operation. Therefore, the RAID controller needs to have two sets of high-speed serial computer expansion (Peripheral Component Interconnect Express, PCIE) buses, that is, one set of PCIE buses between the RAID controller and the host, and one set of PCIE buses between the RAID controller and the storage device. However, this architecture requires the RAID controller to have a high bandwidth to meet performance requirements, but it is currently difficult to achieve high performance. In addition, a separate RAID controller will incur high costs if a hardware RAID controller is used, and its performance will be limited if a software RAID controller is used.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a data management method, a data verification method, and related devices to reduce the transmission process of verification data between a RAID controller and a storage device, thereby lowering the bandwidth requirement of a redundant array of independent disks system.

[0009] The embodiments of this application provide the following technical solutions:

[0010] In a first aspect, an embodiment of the present application provides a data management method, which is applied to a host system, wherein the host system is communicatively connected to a plurality of flash memory devices, wherein each flash memory device has a first memory mapping relationship with other flash memory devices;

[0011] Data management methods include:

[0012] establishing a second memory mapping relationship between the host system and each flash memory device;

[0013] Storing a plurality of data blocks corresponding to the stripe data in a plurality of flash memory devices, wherein each data block corresponds to a flash memory device one by one;

[0014] determining a target flash memory device as a computing engine;

[0015] A verification command is sent to the target flash memory device, so that the target flash memory device performs data calculation on the plurality of data blocks based on the second memory mapping relationship to generate and store verification data.

[0016] In a second aspect, an embodiment of the present application provides a host system, applying the data management method of the first aspect, the host system comprising:

[0017] The processor system is connected to the host memory system and is used to split a stripe of data into a plurality of data blocks and transfer the data blocks to the host memory system;

[0018] The host memory system is connected to the processor system and is used to store data blocks.

[0019] In a third aspect, an embodiment of the present application provides a method for verifying data, which is applied to a storage array, wherein the storage array includes multiple flash memory devices, each flash memory device has a first memory mapping relationship with other flash memory devices, each flash memory device is communicatively connected to a host system, and each flash memory device has a second memory mapping relationship with the host system;

[0020] Methods for verifying data include:

[0021] Based on the verification command sent by the host system and the second memory mapping relationship, data calculation is performed on several data blocks to generate and store verification data, wherein the verification data is directly stored in the flash memory medium by the target flash memory device, and the verification command and the data block are obtained by the data management method of the first aspect.

[0022] In a fourth aspect, an embodiment of the present application provides a storage array, applying the data verification method of the third aspect, wherein the storage array includes a plurality of flash memory devices;

[0023] Each flash memory device includes:

[0024] Redundant Array of Independent Disks engine;

[0025] At least one flash memory medium is communicatively connected to the redundant array of independent disks engine.

[0026] In a fifth aspect, an embodiment of the present application provides a distributed redundant array of independent disks system, comprising:

[0027] Such as the host system in the second aspect;

[0028] As in the storage array of the fourth aspect, the host system and the storage array are connected via a communication bus.

[0029] In a sixth aspect, an embodiment of the present application further provides a non-volatile computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable a host system to execute the data management method of the first aspect, or to enable a storage array to execute the data verification method of the third aspect.

[0030] The beneficial effects of the embodiments of the present application are as follows: Unlike the prior art, the embodiments of the present application provide a data management method, which is applied to a host system, wherein the host system is communicatively connected to multiple flash memory devices, wherein each flash memory device has a first memory mapping relationship with the other flash memory devices. The data management method includes: establishing a second memory mapping relationship between the host system and each flash memory device; storing a plurality of data blocks corresponding to stripe data in the plurality of flash memory devices, wherein each data block has a one-to-one correspondence with a flash memory device; determining a target flash memory device as a calculation engine; and sending a verification command to the target flash memory device, causing the target flash memory device to perform data calculations on the plurality of data blocks based on the second memory mapping relationship to generate and store verification data.

[0031] The host system stores several data blocks corresponding to the stripe data in different flash memory devices, and sends a verification command to the target flash memory device, so that the target flash memory device performs data calculation on the several data blocks based on the second memory mapping relationship. The verification data in this application can be calculated by the flash memory device, and no special RAID controller is required to calculate the verification data. The transmission process of the verification data between the RAID controller and the storage device can be reduced, and the bandwidth requirement of the independent disk redundant array system is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0033] FIG1 is a schematic structural diagram of a redundant array of independent disks system provided in an embodiment of the present application;

[0034] FIG2 is a schematic structural diagram of a first storage array provided in an embodiment of the present application;

[0035] FIG3 is a schematic structural diagram of a flash memory device provided in an embodiment of the present application;

[0036] FIG4 is a schematic diagram of data distribution in different stages of a redundant array of independent disks system provided by an embodiment of the present application;

[0037] FIG5 is a schematic diagram of writing data to a redundant array of independent disks system provided by an embodiment of the present application;

[0038] FIG6 is a schematic diagram of data recovery in a redundant array of independent disks system provided by an embodiment of the present application;

[0039] FIG7 is a flow chart of a data management method provided in an embodiment of the present application;

[0040] 8 is a schematic diagram of a mapping relationship between a read-write storage buffer and a read-write storage buffer mapping area of ​​a flash memory device provided in an embodiment of the present application;

[0041] 9 is a schematic diagram of a mapping relationship between a host memory buffer of a host system and a memory buffer mapping area of ​​a flash memory device provided by an embodiment of the present application;

[0042] FIG10 is a schematic diagram of a process of updating at least one data block by a host system according to an embodiment of the present application;

[0043] FIG11 is a schematic diagram of a process for restoring data in a host system according to an embodiment of the present application;

[0044] FIG12 is a flow chart of a method for verifying data provided in an embodiment of the present application;

[0045] 13 is a schematic diagram of writing verification data to a target flash memory device according to an embodiment of the present application;

[0046] FIG14 is a schematic diagram of another target flash memory device writing verification data according to an embodiment of the present application;

[0047] 15 is a schematic diagram of a process for updating verification data of a target flash memory device according to an embodiment of the present application;

[0048] FIG16 is a schematic diagram of updating verification data of a target flash memory device provided by an embodiment of the present application;

[0049] FIG17 is a schematic diagram of a process of recovering damaged data blocks by a target flash memory device according to an embodiment of the present application;

[0050] FIG18 is a schematic diagram of a target flash memory device performing data recovery on a damaged data block according to an embodiment of the present application;

[0051] FIG19 is a schematic structural diagram of a distributed redundant array of independent disks system provided in an embodiment of the present application;

[0052] FIG20 is a schematic structural diagram of a host system provided in an embodiment of the present application;

[0053] FIG21 is a schematic structural diagram of a second storage array provided in an embodiment of the present application;

[0054] FIG22 is a schematic structural diagram of another flash memory device provided in an embodiment of the present application;

[0055] FIG23 is a schematic diagram of the specific structure of a distributed redundant array of independent disks system provided in an embodiment of the present application;

[0056] FIG24 is a schematic diagram of data distribution at different stages of a distributed redundant array of independent disks system provided by an embodiment of the present application;

[0057] FIG25 is a schematic diagram of a process of writing data in a distributed redundant array of independent disks system provided by an embodiment of the present application;

[0058] FIG26 is a schematic diagram of a process for updating data in a distributed redundant array of independent disks system according to an embodiment of the present application;

[0059] FIG27 is a schematic diagram of a process for recovering data in a distributed redundant array of independent disks system provided in an embodiment of the present application.

[0060] Description of Figure Numbers: DETAILED DESCRIPTION

[0061] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0062] In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0063] The technical solution of this application is described in detail below with reference to the accompanying drawings.

[0064] Please refer to FIG1 , which is a schematic diagram of the structure of a redundant array of independent disks system provided by an embodiment of the present application;

[0065] As shown in FIG1 , a redundant array of independent disks system 100 includes a processor system 101 , a memory system 102 , a system communication bus 103 , a RAID controller 104 and a first storage array 105 . The RAID controller 104 includes a RAID engine 1041 and an internal communication bus 1042 .

[0066] The processor system 101 is used to send commands to the RAID controller 104 to enable the RAID controller 104 to perform data verification or data recovery. The memory system 102 is used to store data blocks to be sent to the RAID controller 104. The processor system 101 includes a central processing unit (CPU), and the memory system 102 includes double data rate synchronous dynamic random access memory (DDR SDRAM).

[0067] The processor system 101 and the memory system 102 constitute a host (not shown). The host communicates with the RAID controller 104 via a system communication bus 103, which is a high-speed Peripheral Component Interconnect Express (PCIE) bus and includes a root complex (RC) module or a switch module.

[0068] RAID controller 104 is specifically configured to perform data verification on data sent by the host, generate verification data, and transmit the verification data and multiple data sent by the host to first storage array 105. RAID controller 104 can be implemented as either hardware or software. A RAID engine 1041 is configured to perform data verification on data sent by the host and generate verification data. RAID controller 104 communicates with first storage array 105 via an internal communication bus 1042, which is a PCIE bus and includes an RC module or a Switch module.

[0069] That is, the RAID controller 104 is similar to a bridge chip. The data sent by the host will be converted into the required data through the RAID controller 104 , and the data sent by the host will also be transmitted to the first storage array 105 through the RAID controller 104 .

[0070] The first storage array 105 is a Redundant Arrays of Inexpensive Disks (RAID) and is used to store data transmitted by the RAID controller 104 .

[0071] RAID technology combines multiple storage devices into a storage array. Working simultaneously, these devices can improve the array's read and write performance or provide data redundancy. RAID technology primarily involves three operations: mirroring, striping, and error correction code (ECC). Mirroring copies data across multiple storage devices; striping divides contiguous data into separate devices; and ECC computes redundant protection data, often called parity data, to detect and correct errors.

[0072] Specifically, please refer to FIG2 , which is a schematic structural diagram of a first storage array provided in an embodiment of the present application;

[0073] In the embodiment of the present application, a disk array in RAID-5 mode is taken as an example to illustrate the structure of the first storage array.

[0074] As shown in FIG2 , first storage array 105 includes a first storage device, a second storage device, a third storage device, and a fourth storage device. The first, second, third, and fourth storage devices have identical structures. The first storage device stores data blocks A1, B1, and C1, along with parity data Dp. The second storage device stores data blocks A2, B2, Cp, and D1. The third storage device stores data blocks A3, Bp, C2, and D2. The fourth storage device stores parity data Ap, B3, C3, and D3.

[0075] Stripe 1 includes data block A1, data block A2 and data block A3, Ap is the parity data of stripe 1; stripe 2 includes data block B1, data block B2 and data block B3, Bp is the parity data of stripe 2; stripe 3 includes data block C1, data block C2 and data block C3, Cp is the parity data of stripe 3; stripe 4 includes data block D1, data block D2 and data block D3, Dp is the parity data of stripe 4.

[0076] In the embodiment of the present application, the storage device in the first storage array 105 may be a magnetic tape, a hard disk, a flash memory device, etc. The specific structure of the storage device is described below using a flash memory device as an example, such as a solid state drive.

[0077] Please refer to FIG3 , which is a schematic diagram of the structure of a flash memory device provided in an embodiment of the present application;

[0078] As shown in FIG. 3 , a flash memory device 300 includes a connector 301 , a storage control chip 302 , other peripheral units 303 , a cache unit 304 , and a flash memory medium 305 .

[0079] Among them, the connector 301 connects the storage control chip 302 and the host for communicating with the host, such as a computer or a server, or the connector 301 connects the storage control chip 302 and the RAID controller 104 for communicating with the RAID controller 104; the storage control chip 302 connects the connector 301, other peripheral units 303, the cache unit 304 and the flash memory medium 305, and is used as a control operation unit to manage the internal system of the flash memory device. The storage control chip 302 includes but is not limited to a solid-state hard disk controller; the peripheral unit 303 is connected to the storage control chip 302, including components such as a serial port, a sensor, a register, and a power chip; the cache unit 304 is connected to the storage control chip 302 and serves as a cache and algorithm table storage unit. The cache unit 304 is generally a dynamic random access memory (DRAM).

[0080] Flash memory device 300 includes flash memory 305, also known as flash memory, Flash, Flash storage, or Flash particles. This storage unit is used to store user data, system data, and the like. Multiple channels are present between storage control chip 302 and flash memory device 305, with each channel independently connecting to a flash memory medium. For example, channel 0 connects to a flash memory medium, channel 1 connects to a flash memory medium, and so on, and channel x connects to a flash memory medium. Flash memory device 305 requires erasure before writing, and each flash memory has a limited number of erase cycles.

[0081] Please refer to FIG4 in conjunction with FIG1 , which is a schematic diagram of data distribution in different stages of a redundant array of independent disks system provided by an embodiment of the present application;

[0082] In the embodiment of the present application, during the data writing process, the data is first divided into several data blocks. For example, data block A is divided into data block A1, data block A2, and data block A3; data block B is divided into data block B1, data block B2, and data block B3; data block C is divided into data block C1, data block C2, and data block C3; and data block D is divided into data block D1, data block D2, and data block D3. The divided data blocks are first stored in the memory system 102 and ultimately stored in different storage devices.

[0083] As shown in FIG4 , the memory system 102 stores data block A1 , data block A2 , data block A3 , data block B1 , data block B2 , data block B3 , data block C1 , data block C2 , data block C3 , data block D1 , data block D2 , and data block D3 .

[0084] RAID engine 1041 retrieves several data blocks stored in memory system 102 via system communication bus 103 and performs data verification to obtain verification data. For example, RAID engine 1041 performs data verification on data blocks A1, A2, and A3 to obtain verification data Ap; RAID engine 1041 performs data verification on data blocks B1, B2, and B3 to obtain verification data Bp; RAID engine 1041 performs data verification on data blocks C1, C2, and C3 to obtain verification data Cp; and RAID engine 1041 performs data verification on data blocks D1, D2, and D3 to obtain verification data Dp.

[0085] The RAID engine 1041 stores each data block and verification data to different storage devices through the internal communication bus 1042, for example: the verification data Dp is stored in the first storage device, the data block D1 is stored in the second storage device, the data block D2 is stored in the third storage device, and the data block D3 is stored in the fourth storage device; the data block C1 is stored in the first storage device, the verification data Cp is stored in the second storage device, the data block C2 is stored in the third storage device, and the data block C3 is stored in the fourth storage device; the data block B1 is stored in the first storage device, the data block B2 is stored in the second storage device, the verification data Bp is stored in the third storage device, and the data block B3 is stored in the fourth storage device; the data block A1 is stored in the first storage device, the data block A2 is stored in the second storage device, the data block A3 is stored in the third storage device, and the verification data Ap is stored in the fourth storage device.

[0086] It is understandable that, during the data reading process, the data read from the first storage array 105 needs to pass through the RAID controller 104 before being transmitted to the memory system 102 .

[0087] Please refer to FIG5 , which is a schematic diagram of writing data to a redundant array of independent disks system provided by an embodiment of the present application;

[0088] The following uses the redundant array of independent disks system 100 to write data block A as an example. Data block A is divided into data block A1, data block A2 and data block A3. Data block A1, data block A2 and data block A3 are first stored in the memory system 102 and finally stored in different storage devices.

[0089] As shown in Figure 5, the memory system 102 stores data block A1, data block A2, and data block A3. The RAID controller 104 receives all the data in the memory system 102, performs data verification on data block A1, data block A2, and data block A3, obtains verification data Ap, and forwards data block A1, data block A2, and data block A3 to the first storage device, the second storage device, and the third storage device respectively, and writes the verification data Ap to the fourth storage device.

[0090] Please refer to FIG6 , which is a schematic diagram of data recovery in a redundant array of independent disks system provided by an embodiment of the present application;

[0091] As shown in Figure 6, when the data block A1 stored in the first storage device is damaged and the independent disk redundant array system 100 needs to recover the data block A1, the RAID controller 104 reads the data block A2, the data block A3 and the check data Ap from the first storage array 105, and recovers the data block A1 based on the data block A2, the data block A3 and the check data Ap, and then transmits the recovered data block A1 to the memory system 102.

[0092] In the above process, the RAID controller 104, acting as a bridge, needs to receive all relevant data: when generating verification data, the RAID controller 104 needs to receive all relevant data of the stripe for calculation, and then store the obtained verification data in a storage device in the first storage array 105; when recovering data of a certain data in the stripe, the RAID controller 104 needs to read the other data in the stripe as well as the verification data to perform the recovery operation. Therefore, the RAID controller 104 needs to have two sets of PCIE buses, namely, one set of PCIE buses between the RAID controller 104 and the host, and one set of PCIE buses between the RAID controller 104 and the storage device. However, this architecture requires the RAID controller 104 to have a high bandwidth to meet performance requirements. At the same time, for a separate RAID controller 104, using a hardware RAID controller will incur higher costs, while using a software RAID controller will further limit performance.

[0093] Example 1

[0094] In order to reduce the transmission process of verification data between the RAID controller and the storage device and reduce the bandwidth requirement of the independent disk redundant array system, the present application provides a data management method, which stores several data blocks corresponding to the stripe data to different flash memory devices through the host system, and sends a verification command to the target flash memory device, so that the target flash memory device performs data calculation on the several data blocks based on the second memory mapping relationship, so that the flash memory device calculates the verification data. Without the need for a dedicated RAID controller, the transmission process of verification data between the RAID controller and the storage device can be reduced, and the bandwidth requirement of the independent disk redundant array system can be reduced.

[0095] Please refer to FIG7 , which is a flow chart of a data management method provided in an embodiment of the present application;

[0096] The data management method is applied to a host system, specifically, to at least one processor of the host system. The host system is communicatively connected to a plurality of flash memory devices, wherein each flash memory device has a first memory mapping relationship with other flash memory devices.

[0097] Specifically, each flash memory device includes a read / write storage buffer and a read / write storage buffer mapping area. The first memory mapping relationship includes a mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffers of other flash memory devices. The read / write storage buffer is used to store data blocks read from the flash memory medium, and the read / write storage buffer mapping area is used to store data blocks from other flash memory devices. Flash memory devices include but are not limited to non-volatile memory express solid state drives (NVMe SSDs).

[0098] Please refer to FIG8 , which is a schematic diagram of a mapping relationship between a read-write storage buffer and a read-write storage buffer mapping area of ​​a flash memory device provided by an embodiment of the present application;

[0099] FIG8 takes two flash memory devices as an example to illustrate the mapping relationship between the read and write storage buffer mapping area of ​​each flash memory device and the read and write storage buffer areas of other flash memory devices.

[0100] As shown in Figure 8, both flash memory device 1 and flash memory device 2 include a read-write storage buffer and a read-write storage buffer mapping area. The read-write storage buffer mapping area of ​​flash memory device 1 has a mapping relationship with the read-write storage buffer of flash memory device 2, and the read-write storage buffer mapping area of ​​flash memory device 2 has a mapping relationship with the read-write storage buffer of flash memory device 1.

[0101] It is understandable that when there are at least three flash memory devices, the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffer areas of other flash memory devices is similar to FIG8 , and is not described again here.

[0102] As shown in FIG7 , the data management method includes:

[0103] Step S701: establishing a second memory mapping relationship between the host system and each flash memory device;

[0104] Specifically, the host system includes a host memory buffer for storing stripe data, wherein the stripe data is divided into a plurality of data blocks. Each flash memory device includes a memory buffer mapping area for storing at least one data block. The second memory mapping relationship includes a mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​each flash memory device.

[0105] In an embodiment of the present application, the step of establishing a second memory mapping relationship between the host system and each flash memory device includes: dividing a host memory buffer in the memory of the host system; mapping the host memory buffer to the storage space of each flash memory device to establish a mapping relationship between the host memory buffer and the memory buffer mapping area of ​​each flash memory device.

[0106] Specifically, the host system divides a host memory buffer in the memory as a mapping area for the data required for RAID calculation of the flash memory device. The RAID calculation includes the calculation of check data when new stripe data is written, the recalculation of check data when some data blocks are updated, and the recovery of data blocks when a data block is damaged.

[0107] The host system and flash memory devices communicate using the Non-Volatile Memory Express (NVMe) protocol. Based on the mapping operation in the NVMe protocol, the host system maps the host memory buffer to the storage space of each flash memory device. This establishes an address mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device. Specifically, when the flash memory device is recognized by the host system, the host system completes the mapping operation by performing a communication handshake between the NVMe driver and the flash memory device.

[0108] Please refer to FIG9 , which is a schematic diagram of a mapping relationship between a host memory buffer of a host system and a memory buffer mapping area of ​​a flash memory device provided by an embodiment of the present application;

[0109] In the embodiment of the present application, the host system can communicate with N flash memory devices, where N is a positive integer. N can be set by those skilled in the art according to actual needs and is not limited in the embodiment of the present application. The following uses four flash memory devices as an example to illustrate the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​each flash memory device.

[0110] As shown in FIG9 , each flash memory device includes a memory buffer mapping area, and a host memory buffer area of ​​the host system is mapped to the memory buffer mapping area of ​​each flash memory device.

[0111] In an embodiment of the present application, by establishing a mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​each flash memory device, the present application does not require a dedicated RAID controller as a bridging process to forward data blocks and calculate verification data, thereby saving costs.

[0112] Step S702: storing a plurality of data blocks corresponding to the stripe data in a plurality of flash memory devices;

[0113] Specifically, the stripe data is data to be stored, and the host system stripes the data to be stored into a plurality of data blocks, and stores each data block in a different flash memory device, wherein each data block corresponds to a flash memory device.

[0114] In an embodiment of the present application, the step of storing several data blocks corresponding to the stripe data in several flash memory devices includes: dividing a stripe data into several data blocks, and storing each data block in a different flash memory device.

[0115] Specifically, the host system divides a strip of data into several data blocks through striping, stores them in the host memory buffer, and then stores each data block in a corresponding flash memory device. The number of data blocks depends on the RAID algorithm and the protection requirements of the redundant array of independent disks system, and is not limited in the embodiments of this application.

[0116] Step S703: determining a target flash memory device as a computing engine;

[0117] Specifically, the target flash memory device is used to calculate and store verification data.

[0118] In an embodiment of the present application, the step of determining a target flash memory device as a computing engine includes: selecting a flash memory device as the target flash memory device from flash memory devices that do not store data blocks.

[0119] Specifically, when the host system stores several data blocks corresponding to a stripe of data in different flash memory devices, it selects a flash memory device from the flash memory devices that do not store the above data blocks as a target flash memory device for calculating and storing verification data.

[0120] It is understandable that, because the host system's host memory buffer is mapped to the memory buffer mapping area of ​​each flash memory device, each flash memory device connected to the host system can be used as a computing engine to perform RAID calculations. In other words, each flash memory device connected to the host system can be used as a target flash memory device. Compared to the existing solution where a RAID controller with two PCIE buses requires high bandwidth, this application distributes the RAID calculation tasks to each flash memory device, reducing the bandwidth requirements for RAID calculations.

[0121] Step S704: Send a verification command to the target flash memory device, so that the target flash memory device performs data calculation on the plurality of data blocks based on the second memory mapping relationship to generate and store verification data.

[0122] Specifically, the host system sends a verification command to the target flash memory device, causing the target flash memory device to obtain a plurality of data blocks corresponding to a stripe of data based on a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​the target flash memory device, and perform data calculations on the plurality of data blocks within the memory buffer mapping area to generate and store verification data. The memory buffer mapping area of ​​the target flash memory device is used to store the plurality of data blocks corresponding to the stripe of data.

[0123] The verification command includes a write verification data command, which includes the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data. When the redundant array of independent disks system needs to write new stripe data, the host system sends the write verification data command to the target flash memory device, causing the target flash memory device to perform data calculations on several data blocks corresponding to the new stripe data in the memory buffer mapping area, thereby generating and storing the verification data.

[0124] In an embodiment of the present application, a check command is sent by a host system to a target flash memory device, so that the target flash memory device performs data calculation on a number of data blocks based on a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​the target flash memory device. The check data in the present application can be calculated by the flash memory device, and no dedicated RAID controller is required to calculate the check data. This can reduce the transmission process of the check data between the RAID controller and the storage device, and reduce the bandwidth requirements of the independent disk redundant array system.

[0125] In an embodiment of the present application, the method further includes: updating at least one data block.

[0126] Specifically, please refer to FIG10 , which is a schematic diagram of a process of updating at least one data block by a host system according to an embodiment of the present application;

[0127] As shown in FIG10 , the process of updating at least one data block by the host system includes:

[0128] Step S1001: updating at least one data block to obtain at least one first data block;

[0129] Specifically, the host system updates the data blocks to be updated in the memory, and obtains a first data block corresponding to each data block to be updated, wherein the first data block is the updated data block.

[0130] Step S1002: storing the first data block in a corresponding flash memory device;

[0131] Specifically, the host system stores each first data block in a corresponding flash memory device. It is understandable that the flash memory device corresponding to the first data block is the flash memory device that stores the data block to be updated corresponding to the first data block, and other unupdated data blocks do not need to be rewritten to the flash memory device.

[0132] Step S1003: Sending an update verification data command to the target flash memory device, so that the target flash memory device performs data calculation on the first data block and the unupdated data blocks in the stripe data based on the first memory mapping relationship and the second memory mapping relationship to generate and store updated verification data.

[0133] Specifically, the verification command also includes an update verification data command, which includes the offset address and data length of the first data block in the host memory buffer, the logical address of the unupdated data block in the flash memory device where it is located, and the logical address corresponding to the updated verification data.

[0134] The host system sends an update verification data command to the target flash memory device, so that the target flash memory device obtains the first data block based on the second memory mapping relationship, obtains the unupdated data blocks in the stripe data based on the first memory mapping relationship, and performs data calculation on the first data block and the unupdated data blocks in the stripe data in the memory buffer mapping area, thereby generating and storing updated verification data.

[0135] In an embodiment of the present application, the updated data block is stored in the corresponding flash memory device through the host system, and an update verification data command is sent to the target flash memory device, so that the target flash memory device generates and stores the updated verification data based on the first memory mapping relationship and the second memory mapping relationship. When updating at least one data block, the present application does not require the RAID controller to act as a bridging process to forward the data block and calculate the verification data, which can improve data update efficiency and storage efficiency.

[0136] In an embodiment of the present application, the method further includes: performing data recovery on the damaged data block.

[0137] Specifically, please refer to FIG11 , which is a schematic diagram of a process of restoring data by a host system according to an embodiment of the present application;

[0138] As shown in Figure 11, the process of restoring data on the host system includes:

[0139] Step S1101: When any data block is damaged, a data recovery command is sent to a target flash memory device, so that the target flash memory device recovers the damaged data block based on the first memory mapping relationship and the second memory mapping relationship to generate a second data block;

[0140] Specifically, when any data block is damaged, the host system sends a data recovery command to the target flash memory device, causing the target flash memory device to recover the damaged data block based on the mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffer areas of other flash memory devices, and the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, thereby generating a second data block. The data recovery command includes the logical address of the third data block on the corresponding flash memory device, the logical address corresponding to the check data, and the destination storage offset address of the second data block in the host memory buffer. The third data block includes the undamaged data block in the stripe data, and the second data block is the data block obtained after the damaged data block is recovered.

[0141] Step S1102: Based on the second memory mapping relationship, obtain a second data block.

[0142] Specifically, after the target flash memory device completes data recovery and stores the second data block in the memory buffer mapping area, the host system obtains the second data block based on the mapping relationship between the host memory buffer and the memory buffer mapping area of ​​the target flash memory device.

[0143] In an embodiment of the present application, when any data block is damaged, the host system sends a data recovery command to the target flash memory device, and after the target flash memory device completes data recovery, the second data block is obtained based on the mapping relationship between the host memory buffer and the memory buffer mapping area of ​​the target flash memory device. Compared with the existing solution that requires the RAID controller to read undamaged data and verification data from each storage device, and then perform data recovery and then transmit the recovered data to the host, the present application does not require the RAID controller to perform data recovery, which can improve data recovery efficiency.

[0144] In an embodiment of the present application, since the RAID calculation is completed by the target flash memory device and there is no dedicated RAID controller, the host system and the target flash memory device control related RAID operations based on specific commands. Specifically, while an address mapping relationship is established between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, the host system and the target flash memory device communicate through custom commands in the non-volatile memory host controller interface specification protocol, for example: communicating through the VU Command in the NVMe protocol.

[0145] In an embodiment of the present application, a data management method is provided. The data management method is applied to a host system that is communicatively connected to multiple flash memory devices, wherein each flash memory device has a first memory mapping relationship with each other flash memory device. The data management method includes: establishing a second memory mapping relationship between the host system and each flash memory device; storing a plurality of data blocks corresponding to stripe data in the plurality of flash memory devices, wherein each data block has a one-to-one correspondence with a flash memory device; determining a target flash memory device as a calculation engine; and sending a verification command to the target flash memory device, causing the target flash memory device to perform data calculations on the plurality of data blocks based on the second memory mapping relationship to generate and store verification data.

[0146] The host system stores several data blocks corresponding to the stripe data in different flash memory devices, and sends a verification command to the target flash memory device, so that the target flash memory device performs data calculation on the several data blocks based on the second memory mapping relationship. The verification data in this application can be calculated by the flash memory device, and no special RAID controller is required to calculate the verification data. The transmission process of the verification data between the RAID controller and the storage device can be reduced, and the bandwidth requirement of the independent disk redundant array system is reduced.

[0147] Example 2

[0148] Please refer to FIG12 , which is a flow chart of a method for verifying data provided in an embodiment of the present application;

[0149] The data verification method is applied to a storage array, for example, a second storage array, wherein the second storage array includes multiple flash memory devices, the multiple flash memory devices being communicatively connected. Specifically, the data verification method is applied to at least one flash memory device in the second storage array, and specifically, the data verification method is executed by a redundant array of independent disks engine of the flash memory device. Each flash memory device has a first memory mapping relationship with each other flash memory device, each flash memory device is communicatively connected to a host system, and each flash memory device has a second memory mapping relationship with the host system.

[0150] Specifically, the host system includes a host memory buffer, which is used to store stripe data, wherein the stripe data is divided into a plurality of data blocks. Each flash memory device includes a memory buffer mapping area, a read-write storage buffer, and a read-write storage buffer mapping area. The memory buffer mapping area is used to store at least one data block from the host system, the read-write storage buffer is used to store data blocks read from the flash memory medium, and the read-write storage buffer mapping area is used to store data blocks from other flash memory devices. The first memory mapping relationship includes a mapping relationship between the read-write storage buffer mapping area of ​​each flash memory device and the read-write storage buffer of other flash memory devices, and the second memory mapping relationship includes a mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​each flash memory device. Preferably, the flash memory device is an NVMe SSD.

[0151] It is understandable that for the master controller of most flash memory devices, the master controller itself has a built-in independent disk redundant array engine. The original function of the independent disk redundant array engine is to perform RAID protection on the data stored in the flash memory device. It should be noted that the RAID protection here has nothing to do with the RAID calculation in this application. The RAID calculation in this application is system-level RAID. The independent disk redundant array engine can perform RAID protection on the data blocks or verification data stored in the flash memory device again after completing the data verification method in this application.

[0152] As shown in FIG12 , the method for verifying data includes:

[0153] Step S1201: Based on the verification command sent by the host system and the second memory mapping relationship, data calculation is performed on a plurality of data blocks to generate and store verification data.

[0154] Specifically, the target flash memory device in the second storage array receives a verification command sent by the host system, obtains a plurality of data blocks corresponding to the stripe data based on a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​the target flash memory device, performs data calculations on the plurality of data blocks in the memory buffer mapping area, generates verification data, and stores the verification data in the flash memory medium. The verification command and the plurality of data blocks corresponding to the stripe data are obtained by the data management method of the first embodiment described above.

[0155] It is understandable that although the target flash memory device is determined by the host system, the target flash memory device determined by the host system may be different when processing different stripe data. Therefore, each flash memory device in the second storage array can be used as a target flash memory device to execute the data verification method in Example 2.

[0156] In an embodiment of the present application, based on the verification command sent by the host system and the second memory mapping relationship, the step of performing data calculation on a plurality of data blocks to generate and store verification data includes steps S1 to S4, which are specifically as follows:

[0157] Step S1: Receive and parse the write verification data command to obtain the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data;

[0158] Specifically, the verification command includes a write verification data command, which includes the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data. The target flash memory device receives and parses the write verification data command sent by the host system, and obtains the offset address and data length of each data block in the stripe data in the host memory buffer, as well as the logical address corresponding to the verification data.

[0159] Step S2: Based on the second mapping relationship, the offset address and data length of each data block in the host memory buffer, obtain a plurality of data blocks corresponding to the stripe data;

[0160] Specifically, since a mapping relationship is established between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, there will be an address segment in the memory buffer mapping area of ​​the target flash memory device pointing to the host memory buffer of the host system. Therefore, the target flash memory device can obtain several data blocks corresponding to the stripe data based on the mapping relationship, the offset address and data length of each data block in the host memory buffer.

[0161] Step S3: performing an XOR operation on all data blocks in the stripe data in the memory buffer mapping area of ​​the target flash memory device to obtain verification data corresponding to the stripe data;

[0162] Specifically, the target flash memory device performs an XOR operation on all data blocks in the stripe data in the memory buffer mapping area to obtain verification data corresponding to the stripe data, and stores the verification data in the internal storage space of the target flash memory device, for example: in the double-rate synchronous dynamic random access memory of the target flash memory device.

[0163] Step S4: Using the logical address corresponding to the verification data as a storage index, the verification data is stored in the flash memory medium.

[0164] Specifically, the target flash memory device uses the logical address corresponding to the verification data as a storage index, stores the verification data from the internal storage space to the flash memory medium, and feeds back to the host system that the write verification data command is completed.

[0165] Please refer to FIG13 , which is a schematic diagram of writing verification data to a target flash memory device according to an embodiment of the present application;

[0166] FIG13 illustrates the process of writing verification data to the target flash memory device, with stripe data being divided into data block A1, data block A2, and data block A3. The second storage array includes four flash memory devices, and the target flash memory device is flash memory device 4. It is understood that the second storage array may include N flash memory devices, where N is a positive integer. N can be determined by those skilled in the art based on actual circumstances and is not limited in this embodiment.

[0167] As shown in Figure 13, when the host system stores data block A1, data block A2 and data block A3 to flash memory device 1, flash memory device 2 and flash memory device 3 respectively, flash memory device 4 acts as the target flash memory device, and obtains data block A1, data block A2 and data block A3 based on the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​flash memory device 4, and performs an XOR operation on data block A1, data block A2 and data block A3 in the memory buffer mapping area to obtain verification data Ap, and then stores the verification data Ap in the internal storage space, and finally uses the logical address corresponding to the verification data Ap as the storage index to store the verification data Ap in the flash memory medium.

[0168] In an embodiment of the present application, data calculation is performed on a number of data blocks based on a verification command sent by a host system, a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​a target flash memory device, so as to generate and store verification data. The verification data in the present application can be calculated by the flash memory device, and no dedicated RAID controller is required to calculate the verification data. This can reduce the transmission process of the verification data between the RAID controller and the storage device, and reduce the bandwidth requirements of the independent disk redundant array system.

[0169] Please refer to FIG14 , which is a schematic diagram of writing verification data to another target flash memory device according to an embodiment of the present application;

[0170] In an embodiment of the present application, each flash memory device in the second storage array can be used as a target flash memory device to perform RAID calculations, that is, to calculate check data when new stripe data is written, to recalculate check data when some data blocks are updated, and to restore data blocks when a data block is damaged.

[0171] In FIG14 , the stripe data is divided into data block B1, data block B2 and data block B3, the second storage array includes four flash memory devices, and the target flash memory device is flash memory device 3, which illustrates the process of writing verification data to the target flash memory device.

[0172] As shown in Figure 14, when the host system stores data block B1, data block B2 and data block B3 to flash memory device 1, flash memory device 2 and flash memory device 4 respectively, flash memory device 3 acts as the target flash memory device, and obtains data block B1, data block B2 and data block B3 based on the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​flash memory device 3, and performs an XOR operation on data block B1, data block B2 and data block B3 in the memory buffer mapping area to obtain verification data Bp, and then stores the verification data Bp in the internal storage space, and finally uses the logical address corresponding to the verification data Bp as the storage index to store the verification data Bp in the flash memory medium.

[0173] In an embodiment of the present application, the second storage array includes multiple flash memory devices, and the memory buffer mapping area of ​​each flash memory device has an address mapping relationship with the host memory buffer of the host system. Each flash memory device in the storage array of the present application can independently complete the calculation of verification data, and does not require a dedicated RAID controller to calculate the verification data. This can reduce the transmission process of verification data between the RAID controller and the storage device, and reduce the bandwidth requirements of the independent disk redundant array system.

[0174] In an embodiment of the present application, the method also includes: dividing a read-write storage buffer in the memory of each flash memory device; mapping the read-write storage buffer to the storage space of each remaining flash memory device to establish a mapping relationship between the read-write storage buffer mapping area of ​​each flash memory device and the read-write storage buffer of other flash memory devices.

[0175] Specifically, the flash memory device divides a read-write storage buffer in its memory as a mapping area for calculating required data when the flash memory device performs data recovery. At the same time, the read-write storage buffer is mapped to the read-write storage buffer mapping area of ​​other flash memory devices. The mapping relationship between the read-write storage buffer and the read-write storage buffer mapping area is shown in Figure 8. The flash memory devices in the second storage array establish a mapping relationship between the read-write storage buffer mapping area of ​​each flash memory device and the read-write storage buffer of other flash memory devices through the NVMe protocol mapping operation, that is, the first memory mapping relationship.

[0176] In an embodiment of the present application, the method further includes: updating corresponding check data when at least one data block is updated. Specifically, when at least one data block in a data stripe is updated, the flash memory device storing the check data corresponding to the data stripe takes on the task of updating the check data, i.e., the target flash memory device mentioned above updates the check data.

[0177] Please refer to FIG15 , which is a schematic diagram of a process of updating verification data of a target flash memory device according to an embodiment of the present application;

[0178] As shown in FIG15 , the process of updating verification data of the target flash memory device includes:

[0179] Step S1501: acquiring a first data block based on an update verification data command sent by a host system, a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​a target flash memory device;

[0180] Specifically, the target flash memory device receives the update verification data command sent by the host system, and obtains a first data block corresponding to each data block to be updated based on the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device.

[0181] The first data block is an updated data block, and the update verification data command includes the offset address and data length of the first data block in the host memory buffer, the logical addresses of the unupdated data blocks in the flash memory device where they are located, and the logical addresses corresponding to the updated verification data. The update verification data command and the first data block are obtained by the data management method of Example 1.

[0182] In an embodiment of the present application, based on the update verification data command sent by the host system, the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, the step of obtaining the first data block includes steps S1 and S2, which are specifically as follows:

[0183] Step S1: receiving and parsing a command to update verification data, obtaining the offset address and data length of the first data block in the host memory buffer, the logical addresses of the unupdated data blocks in their respective flash memory devices, and the logical address corresponding to the updated verification data;

[0184] Specifically, the target flash memory device receives and parses the update verification data command sent by the host system, obtains the offset address and data length of the first data block in the host memory buffer, the logical address of the unupdated data block in the respective flash memory devices, and the logical address corresponding to the updated verification data.

[0185] Step S2: acquiring the first data block based on the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, the offset address and the data length of the first data block in the host memory buffer.

[0186] Specifically, the target flash memory device obtains the first data block in the memory buffer mapping area according to the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, the offset address and data length of the first data block in the host memory buffer.

[0187] Step S1502: obtaining unupdated data blocks in the stripe data based on the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer areas of other flash memory devices;

[0188] Specifically, the target flash memory device obtains unupdated data blocks in the stripe data from other flash memory devices based on the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer areas of other flash memory devices.

[0189] In an embodiment of the present application, the step of obtaining unupdated data blocks in the stripe data based on the mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffer areas of other flash memory devices includes steps S1 and S2, which are specifically as follows:

[0190] Step S1: sending a first read command to each flash memory device storing an unupdated data block to obtain an address of each unupdated data block in a read / write storage buffer of the corresponding flash memory device;

[0191] Specifically, the target flash memory device determines the flash memory devices where the unupdated data blocks are located in the stripe data corresponding to the data blocks to be updated, and sends a first read command to each of the flash memory devices to obtain the address of the read / write storage buffer of each unupdated data block in the flash memory device where the data blocks are located. The first read command includes the logical address of the unupdated data blocks in the corresponding flash memory device.

[0192] It is understandable that after receiving the first read command sent by the target flash memory device, the other flash memory devices will read the unupdated data blocks from the flash memory medium according to the logical addresses of the unupdated data blocks, store the unupdated data blocks in the read-write storage buffer, and send the addresses of the unupdated data blocks in the read-write storage buffer to the target flash memory device.

[0193] Step S2: acquiring each unupdated data block through a point-to-point operation according to the address of each unupdated data block in the read / write storage buffer of the corresponding flash memory device.

[0194] Specifically, the flash memory devices communicate with each other based on the peer-to-peer command (P2P Command) in the high-speed serial computer extension protocol. The target flash memory device performs a peer-to-peer operation through the PCIE bus to obtain each unupdated data block in the read-write storage buffer of the other flash memory device according to the address of each unupdated data block in the read-write storage buffer of the corresponding flash memory device, and stores the unupdated data block in the read-write storage buffer mapping area.

[0195] It is understandable that the peer-to-peer operation enables one flash memory device to directly access another flash memory device.

[0196] Step S1503: performing data calculation on the first data block and the unupdated data blocks in the stripe data to generate and store updated verification data.

[0197] Specifically, the target flash memory device performs data calculation on the first data block and the unupdated data blocks in the stripe data corresponding to the first data block to generate and store updated verification data.

[0198] In the embodiment of the present application, the step of performing data calculation on the first data block and the unupdated data blocks in the stripe data to generate and store updated verification data includes steps S1 and S2, which are specifically as follows:

[0199] Step S1: performing an exclusive OR operation on an unupdated data block stored in the memory buffer mapping area of ​​the target flash memory device and a first data block stored in the read-write storage buffer mapping area of ​​the target flash memory device to obtain updated verification data;

[0200] Specifically, the target flash memory device performs an XOR operation on the unupdated data block stored in the memory buffer mapping area and the first data block stored in the read-write storage buffer mapping area to obtain updated verification data, and stores the updated verification data in the internal storage space of the target flash memory device.

[0201] Step S2: Using the logical address corresponding to the updated verification data as a storage index, the updated verification data is stored in the flash memory medium of the target flash memory device.

[0202] Specifically, the target flash memory device uses the logical address corresponding to the updated verification data as a storage index, stores the updated verification data from the internal storage space to the flash memory medium, and feeds back to the host system that the update verification data command is completed.

[0203] Please refer to FIG16 , which is a schematic diagram of updating verification data of a target flash memory device provided by an embodiment of the present application;

[0204] In Figure 16, the stripe data is divided into data block A1, data block A2 and data block A3. Data block A1 is updated to data block A1' in the host system, and data block A2 is updated to data block A2' in the host system. The second storage array includes 4 flash memory devices, and the target flash memory device is flash memory device 4. The process of updating the verification data of the target flash memory device is described.

[0205] As shown in Figure 16, when the host system stores data block A1' and data block A2' to the flash memory device 1 where data block A1 is located and the flash memory device 2 where data block A2 is located, respectively, data block A3 does not need to be re-stored because it has not been updated. The flash memory device 4, as the target flash memory device, obtains data block A1' and data block A2' based on the update verification data command sent by the host system and the mapping relationship between the host memory buffer and the memory buffer mapping area of ​​the flash memory device 4, and obtains data block A3 based on the mapping relationship between the read-write storage buffer of the flash memory device 3 and the read-write storage buffer mapping area of ​​the flash memory device 4. Then, an XOR operation is performed on the data block A1', the data block A2' and the data block A3 to generate updated verification data Ap', and the updated verification data Ap' is stored from the internal storage space to the flash memory medium.

[0206] In an embodiment of the present application, a first data block is obtained based on an update verification data command sent by a host system, a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​a target flash memory device, and an unupdated data block in the stripe data is obtained based on a mapping relationship between a read-write storage buffer mapping area of ​​the target flash memory device and a read-write storage buffer of other flash memory devices, and data calculation is performed on the first data block and the unupdated data block in the stripe data to generate and store updated verification data. The present application can calculate the updated verification data by the flash memory device when at least one data block is updated, and does not require a dedicated RAID controller to forward the updated data block and calculate the verification data. The transmission process of the verification data between the RAID controller and the storage device can be reduced, and the bandwidth requirements of the independent disk redundant array system can be reduced.

[0207] In an embodiment of the present application, the method further includes: performing data recovery on the damaged data block.

[0208] Please refer to FIG17 , which is a schematic diagram of a process of recovering damaged data blocks by a target flash memory device according to an embodiment of the present application;

[0209] As shown in FIG17 , the process of recovering damaged data blocks on the target flash memory device includes:

[0210] Step S1701: acquiring a third data block based on a data recovery command sent by the host system and a mapping relationship between a read / write storage buffer mapping area of ​​a target flash memory device and read / write storage buffer areas of other flash memory devices;

[0211] Specifically, the target flash memory device receives a data recovery command sent by the host system and, based on a mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffers of other flash memory devices, obtains a third data block. The data recovery command includes the logical address of the third data block in the corresponding flash memory device, the logical address corresponding to the verification data, and the destination storage offset address of the second data block in the host memory buffer. The third data block includes an undamaged data block in the stripe data. The third data block and the damaged data block correspond to the same stripe data. The second data block is the data block obtained after data recovery of the damaged data block. The data recovery command and the third data block are obtained by the data management method of Example 1.

[0212] In the embodiment of the present application, the step of obtaining the third data block based on the data recovery command sent by the host system and the mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffer area of ​​other flash memory devices includes steps S1 to S3, which are specifically as follows:

[0213] Step S1: receiving and parsing a data recovery command to obtain a logical address of the third data block in the corresponding flash memory device, a logical address corresponding to the verification data, and a destination storage offset address of the second data block in the host memory buffer;

[0214] Specifically, the target flash memory device receives and parses the data recovery command sent by the host system to obtain the logical address of the third data block in the corresponding flash memory device, the logical address corresponding to the verification data, and the destination storage offset address of the second data block in the host memory buffer.

[0215] Step S2: sending a second read command to each flash memory device storing the third data block to obtain the address of each third data block in the read / write storage buffer of the corresponding flash memory device;

[0216] Specifically, the target flash memory device sends a second read command to each flash memory device storing the third data block to obtain the address of each third data block in the read / write storage buffer of the flash memory device where the third data block is located. The second read command includes the logical address of the third data block in the corresponding flash memory device.

[0217] It is understandable that after receiving the second read command sent by the target flash memory device, the other flash memory devices will read the third data block from the flash memory medium according to the logical address of the third data block, store the third data block in the read-write storage buffer, and send the address of the third data block in the read-write storage buffer to the target flash memory device.

[0218] Step S3: Based on the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer areas of other flash memory devices, and the address of each third data block in the read / write storage buffer area of ​​the corresponding flash memory device, each third data block is obtained through a point-to-point operation.

[0219] Specifically, the target flash memory device performs a point-to-point operation through the PCIE bus to read the third data block from the read-write storage buffer of each flash memory device storing the third data block based on the mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffer of each flash memory device storing the third data block, and stores the read third data block in the read-write storage buffer mapping area of ​​the target flash memory device.

[0220] Step S1702: recovering the damaged data block based on the third data block and the verification data.

[0221] Specifically, the target flash memory device reads the check data corresponding to the stripe data where the third data block is located from the flash memory medium, and performs an XOR operation on the third data block and the check data to obtain a second data block corresponding to the damaged data block.

[0222] In the embodiment of the present application, the step of recovering the damaged data block according to the third data block and the check data includes steps S1 and S2, which are specifically as follows:

[0223] Step S1: Reading verification data from the flash memory medium of the target flash memory device based on the logical address corresponding to the verification data;

[0224] Specifically, the target flash memory device reads the verification data from the flash memory medium based on the logical address corresponding to the verification data, and stores the verification data into the internal storage space.

[0225] Step S2: performing an XOR operation on a plurality of third data blocks and verification data in the read-write storage buffer mapping area of ​​the target flash memory device to obtain a second data block, and transmitting the second data block to a destination storage offset address of the host memory buffer.

[0226] Specifically, the target flash memory device performs an exclusive OR operation on the plurality of third data blocks and the check data in the read-write storage buffer mapping area of ​​the target flash memory device to obtain a second data block, and stores the second data block in the memory buffer mapping area. Based on the address mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, the second data block is transferred to the target storage offset address of the second data block in the host memory buffer of the host system. After the target flash memory device completes data recovery, the target flash memory device sends a feedback to the host system indicating that the data recovery command is complete.

[0227] In an embodiment of the present application, when the flash memory device in the storage array performs data recovery or updates verification data, the address of the third data block obtained by the flash memory device through RAID calculation in the read-write storage buffer and the address of the unupdated data block in the read-write storage buffer are both mapped to the spatial domain address of the target flash memory device.

[0228] Please refer to FIG18 , which is a schematic diagram of a target flash memory device performing data recovery on a damaged data block according to an embodiment of the present application;

[0229] Figure 18 shows that the stripe data is divided into data block A1, data block A2 and data block A3, the second storage array includes 4 flash memory devices, the target flash memory device is flash memory device 4, data block A1 is damaged, data block A2 and data block A3 are undamaged data blocks, that is, data block A2 and data block A3 are the third data block, which illustrates the process of data recovery of the damaged data block by the target flash memory device.

[0230] As shown in Figure 18, the damaged data block A1, data block A2 and data block A3 are stored in flash memory device 1, flash memory device 2 and flash memory device 3 respectively. Flash memory device 4 serves as the target flash memory device. According to the data recovery command sent by the host system and the mapping relationship between the read-write storage buffer of flash memory device 2 and the read-write storage buffer mapping area of ​​flash memory device 4, data block A2 is read from the read-write storage buffer of flash memory device 2, and data block A3 is read from the read-write storage buffer of flash memory device 3 according to the mapping relationship between the read-write storage buffer of flash memory device 3 and the read-write storage buffer mapping area of ​​flash memory device 4.

[0231] Then the target flash memory device reads the verification data Ap corresponding to the damaged data block A1, data block A2 and data block A3 from the flash memory medium, and performs an XOR operation on the data block A2, data block A3 and the verification data Ap in the read-write storage buffer mapping area of ​​the target flash memory device to obtain data block A1. The obtained data block A1 is the second data block mentioned above, which completes the data recovery operation on the damaged data block A1, and stores the obtained data block A1 in the memory buffer mapping area, so that according to the address mapping relationship between the host memory buffer and the memory buffer mapping area of ​​the target flash memory device, the data block A1 is transmitted to the destination storage offset address of the data block A1 in the host memory buffer of the host system.

[0232] In an embodiment of the present application, a third data block is obtained based on a data recovery command sent by a host system and a mapping relationship between a read-write storage buffer mapping area of ​​a target flash memory device and a read-write storage buffer of other flash memory devices, and data recovery is performed on a damaged data block based on the third data block and verification data. When a data block is damaged, the present application can calculate and recover the damaged data block by the flash memory device, without requiring a dedicated RAID controller to perform data recovery operations, thereby reducing the data transmission process between the RAID controller and the storage device and lowering the bandwidth requirements of the redundant array of independent disks system.

[0233] In an embodiment of the present application, a method for verifying data is provided. The method is applied to a storage array, wherein the storage array includes multiple flash memory devices, each flash memory device having a first memory mapping relationship with other flash memory devices, each flash memory device being communicatively connected to a host system, and each flash memory device having a second memory mapping relationship with the host system. The method for verifying data includes: performing data calculations on a plurality of data blocks based on a verification command sent by the host system and the second memory mapping relationship to generate and store verification data, wherein the verification data is directly stored by the target flash memory device to the flash memory medium, and the verification command and the data blocks are obtained by the data management method of the first embodiment.

[0234] By performing data calculation on a plurality of data blocks based on a check command sent by a host system and a second memory mapping relationship, check data is generated and stored. The check data in the present application is calculated by a flash memory device, and no dedicated RAID controller is required to calculate the check data. This can reduce the transmission process of the check data between the RAID controller and the storage device, and reduce the bandwidth requirements of the redundant array of independent disks system.

[0235] Example 3

[0236] Please refer to FIG19 , which is a schematic diagram of the structure of a distributed redundant array of independent disks system provided by an embodiment of the present application;

[0237] As shown in Figure 19, a distributed redundant array of independent disks system 190 includes a host system 191 and a second storage array 192. The host system 191 and the second storage array 192 are connected via a communication bus, for example, a PCIE bus.

[0238] Please refer to FIG20 , which is a schematic diagram of the structure of a host system provided in an embodiment of the present application;

[0239] In the embodiment of the present application, the host system applies the data management method in the above-mentioned embodiment 1.

[0240] As shown in Figure 20, the host system 191 includes a processor system 1911 and a host memory system 1912. The processor system 1911 and the host memory system 1912 are communicatively connected via a bus.

[0241] Processor system 1911, connected to host memory system 1912, is used to divide a stripe of data into several data blocks and transmit the data blocks to host memory system 1912. Specifically, processor system 1911 is used to execute the data management method in the above-mentioned embodiment 1, for example: establishing a second memory mapping relationship between the host system and each flash memory device; storing several data blocks corresponding to the stripe data to several flash memory devices, wherein each data block corresponds to a flash memory device one by one; determining a target flash memory device as a calculation engine; sending a verification command to the target flash memory device so that the target flash memory device performs data calculation on the several data blocks based on the second memory mapping relationship to generate and store verification data. In the embodiment of the present application, processor system 1911 includes but is not limited to a central processing unit (CPU).

[0242] The host memory system 1912 is connected to the processor system 1911 and is used to store data blocks. Specifically, the host memory system 1912 includes a host memory buffer, which is used to store stripe data, wherein the stripe data is divided into a plurality of data blocks.

[0243] In the embodiment of the present application, the host memory system 1912 includes but is not limited to Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).

[0244] In an embodiment of the present application, a host system is provided that applies the data management method of the first embodiment. The host system includes: a processor system connected to a host memory system for dividing a strip of data into a plurality of data blocks and transmitting the data blocks to the host memory system; and a host memory system connected to the processor system for storing the data blocks. This application can reduce the number of RAID controllers and lower the bandwidth requirements of a redundant array of independent disks system.

[0245] Please refer to FIG21 , which is a schematic diagram of the structure of a second storage array provided in an embodiment of the present application;

[0246] In the embodiment of the present application, the second storage array applies the data verification method in the above-mentioned second embodiment.

[0247] As shown in FIG21 , the second storage array 192 includes multiple flash memory devices 1921. Each flash memory device 1921 can execute the data verification method described in the second embodiment. The number of flash memory devices 1921 can be set by those skilled in the art based on actual conditions and is not limited in the present embodiment.

[0248] Please refer to FIG. 22 , which is a schematic diagram of the structure of another flash memory device provided in an embodiment of the present application;

[0249] As shown in Figure 22, a flash memory device 220 includes a redundant array of independent disks engine 221 and at least one flash memory medium 222. The flash memory device is a flash memory device in the second storage array.

[0250] The independent disk redundant array engine 221 is connected to the flash memory medium 222 and is used to execute the method for verifying data in the above-mentioned embodiment 2, for example: based on the verification command sent by the host system and the second memory mapping relationship, data calculation is performed on a plurality of data blocks to generate and store verification data, wherein the verification data is directly stored in the flash memory medium by the target flash memory device, and the verification command and the data block are obtained by the data management method in the embodiment 1.

[0251] The flash memory medium 222 is in communication with the redundant array of independent disks engine 221 and is used to store data blocks and check data.

[0252] In an embodiment of the present application, a storage array, such as a second storage array, is provided. The storage array employs the data verification method of the second embodiment. The storage array includes multiple flash memory devices, each of which includes a redundant array of independent disks engine and at least one flash memory medium communicatively connected to the redundant array of independent disks engine. The present application can offload RAID calculation tasks to the flash memory devices in the second storage array, eliminating the need for a dedicated RAID controller, reducing the data transmission process between the RAID controller and the storage devices, and lowering the bandwidth requirements of the redundant array of independent disks system.

[0253] Please refer to FIG23 , which is a schematic diagram of the specific structure of a distributed redundant array of independent disks system provided by an embodiment of the present application;

[0254] As shown in FIG. 23 , the distributed redundant array of independent disks system 190 includes a host system 191 , a second storage array 192 , and a communication bus 193 .

[0255] Among them, the host system 191 is used to execute the data management method in Example 1. The host system 191 includes a processor system 1911 and a host memory system 1912. For the specific structure and function of the host system 191, please refer to the relevant content of Figure 20, which will not be repeated here.

[0256] The communication bus 193 connects the host system 191 and the second storage array 192 for data transmission. In the embodiment of the present application, the communication bus 193 includes but is not limited to a PCIE bus.

[0257] The second storage array 192 is used to execute the method for verifying data in the second embodiment. For the specific structure and function of the second storage array 192, please refer to the relevant content of Figure 21 and will not be repeated here.

[0258] In an embodiment of the present application, each flash memory device in the second storage array has a first memory mapping relationship with the other flash memory devices, and the host system has a second memory mapping relationship with each flash memory device in the second storage array. The host memory system includes a host memory buffer, and each flash memory device in the second storage array includes a memory buffer mapping area, a read-write storage buffer area, and a read-write storage buffer mapping area. The first memory mapping relationship includes a mapping relationship between the read-write storage buffer area of ​​each flash memory device and the read-write storage buffer mapping area of ​​the other flash memory devices. The second memory mapping relationship includes a mapping relationship between the host memory buffer area of ​​the host system and the memory buffer mapping area of ​​each flash memory device in the second storage array.

[0259] In an embodiment of the present application, a distributed redundant array of independent disks system is provided. The distributed redundant array of independent disks system includes: a host system for executing the data management method of embodiment 1; and a storage array for executing the data verification method of embodiment 2, wherein the host system and the storage array are connected via a communication bus. The present application can distribute RAID calculation tasks to the individual flash memory devices in the storage array, eliminating the need for a dedicated RAID controller, reducing the data transmission process between the RAID controller and the storage devices, and lowering the bandwidth requirements of the redundant array of independent disks system.

[0260] Please refer to FIG. 24 , which is a schematic diagram of data distribution at different stages of a distributed redundant array of independent disks system provided by an embodiment of the present application;

[0261] In an embodiment of the present application, the host system divides stripe data A, stripe data B, and stripe data C into several data blocks respectively, and stores them in the host memory system. For example: stripe data A is divided into data block A1, data block A2, and data block A3; stripe data B is divided into data block B1, data block B2, and data block B3; stripe data C is divided into data block C1, data block C2, and data block C3; stripe data D is divided into data block D1, data block D2, and data block D3.

[0262] As shown in FIG. 24 , the host memory system 1912 stores data block A1, data block A2, data block A3, data block B1, data block B2, data block B3, data block C1, data block C2, data block C3, data block D1, data block D2, and data block D3.

[0263] The host system stores each data block corresponding to a stripe of data in different flash memory devices via the communication bus 193 and sends a verification command to the corresponding target flash memory device so that the target flash memory device performs data calculation and generates and stores verification data.

[0264] For example: the host system stores data block D1 to flash memory device 2, data block D2 to flash memory device 3, and data block D3 to flash memory device 4, and at the same time determines that the target flash memory device is flash memory device 1. Flash memory device 1 receives the verification command sent by the host system, generates and stores verification data Dp; the host system stores data block C1 to flash memory device 1, data block C2 to flash memory device 3, and data block C3 to flash memory device 4, and at the same time determines that the target flash memory device is flash memory device 2. Flash memory device 2 receives the verification command sent by the host system, generates and stores verification data Cp.

[0265] For example: the host system stores data block B1 to flash memory device 1, data block B2 to flash memory device 2, and data block B3 to flash memory device 4, and at the same time determines that the target flash memory device is flash memory device 3. Flash memory device 3 receives the verification command sent by the host system, generates and stores verification data Bp; the host system stores data block A1 to flash memory device 1, data block A2 to flash memory device 2, and data block A3 to flash memory device 3, and at the same time determines that the target flash memory device is flash memory device 4. Flash memory device 4 receives the verification command sent by the host system, generates and stores verification data Ap.

[0266] Please refer to FIG. 25 , which is a schematic diagram of a process of writing data in a distributed redundant array of independent disks system provided by an embodiment of the present application;

[0267] As shown in Figure 25, the process of writing data in a distributed redundant array of independent disks system includes:

[0268] Step S2501: establishing a second memory mapping relationship between the host system and each flash memory device;

[0269] Specifically, the second memory mapping relationship includes a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​each flash memory device. The host system allocates a host memory buffer in its memory as a mapping area for data required for RAID calculations on the flash memory device. The distributed redundant array of independent disks system initializes and maps the host memory buffer to the storage space of each flash memory device in the storage array, thereby establishing a mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​each flash memory device.

[0270] Step S2502: the host system stores a plurality of data blocks corresponding to the stripe data in a plurality of flash memory devices, and sends a write verification data command to the target flash memory device;

[0271] Specifically, the host system divides a stripe of data into several data blocks through striping and stores them in the host memory buffer, then stores each data block in the corresponding flash memory device, and sends a write verification data command to the target flash memory device, so that the target flash memory device obtains several data blocks corresponding to the stripe data based on the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, and performs data calculation on the several data blocks in the memory buffer mapping area to generate and store verification data.

[0272] Step S2503: The target flash memory device performs data calculation on a plurality of data blocks based on the write verification data command and the second memory mapping relationship to generate and store verification data.

[0273] Specifically, the target flash memory device receives and parses the write verification data command to obtain the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data. Then, based on the mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​the target flash memory device, and the offset address and data length of each data block in the host memory buffer, the target flash memory device obtains several data blocks corresponding to the stripe data, performs an exclusive-or operation on all data blocks in the stripe data within the memory buffer mapping area of ​​the target flash memory device, obtains the verification data corresponding to the stripe data, and finally stores the verification data in the flash memory medium using the logical address corresponding to the verification data as a storage index.

[0274] Please refer to FIG. 26 , which is a schematic diagram of a process for updating data in a distributed redundant array of independent disks system according to an embodiment of the present application;

[0275] As shown in Figure 26, the process of updating data in a distributed redundant array of independent disks system includes:

[0276] Step S2601: establishing a first memory mapping relationship between each flash memory device and other flash memory devices, and a second memory mapping relationship between the host system and each flash memory device;

[0277] Specifically, the first memory mapping relationship includes a mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffer areas of other flash memory devices. The second memory mapping relationship includes a mapping relationship between the host memory buffer area of ​​the host system and the memory buffer mapping area of ​​each flash memory device. The host system allocates a host memory buffer area in its memory as a mapping area for data required for RAID calculations on the flash memory device. The flash memory device allocates a read / write storage buffer area in its storage space as a mapping area for data required for calculations during data recovery.

[0278] The distributed independent redundant array of disks system is initialized, and the host memory buffer is mapped to the storage space of each flash memory device in the storage array, that is, a mapping relationship between the host memory buffer of the host system and the memory buffer mapping area of ​​each flash memory device is established, and the read and write storage buffer of each flash memory device is mapped to the storage space of other flash memory devices, that is, a mapping relationship between the read and write storage buffer mapping area of ​​each flash memory device and the read and write storage buffer of other flash memory devices is established.

[0279] Step S2602: the host system stores the updated data block in the corresponding flash memory device and sends an update verification data command to the target flash memory device;

[0280] Specifically, the host system updates the data blocks to be updated in the memory, obtains a first data block corresponding to each data block to be updated, stores each first data block in the corresponding flash memory device, and sends an update verification data command to the target flash memory device, so that the target flash memory device performs data calculation on the first data block and the unupdated data blocks in the stripe data based on the first memory mapping relationship and the second memory mapping relationship, so as to generate and store updated verification data.

[0281] Step S2603: The target flash memory device performs data calculation on the first data block and the unupdated data blocks in the stripe data based on the update verification data command, the first memory mapping relationship, and the second memory mapping relationship, and generates and stores updated verification data.

[0282] Specifically, the target flash memory device receives a verification data update command sent by the host system and, based on a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​the target flash memory device, obtains a first data block that corresponds one-to-one with each data block to be updated. Then, based on a mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffers of other flash memory devices, the target flash memory device obtains unupdated data blocks in the stripe data from the other flash memory devices. Finally, the target flash memory device performs data calculation on the first data block and the unupdated data blocks in the stripe data corresponding to the first data block, generating and storing updated verification data.

[0283] Please refer to FIG. 27 , which is a schematic diagram of a process for recovering data in a distributed redundant array of independent disks system according to an embodiment of the present application;

[0284] As shown in Figure 27, the data recovery process of a distributed redundant array of independent disks system includes:

[0285] Step S2701: establishing a first memory mapping relationship between each flash memory device and other flash memory devices, and a second memory mapping relationship between the host system and each flash memory device;

[0286] Specifically, the specific implementation method of this step is the same as the specific implementation method of step S2601, which will not be repeated here.

[0287] Step S2702: The host system sends a data recovery command to the target flash memory device;

[0288] Specifically, when any data block is damaged, the host system sends a data recovery command to the target flash memory device, so that the target flash memory device recovers the damaged data block based on the first memory mapping relationship and the second memory mapping relationship, and generates a second data block. The second data block is the data block obtained after the data recovery of the damaged data block is completed.

[0289] Step S2703: The target flash memory device recovers the damaged data block based on the data recovery command sent by the host system, the first memory mapping relationship, and the second memory mapping relationship, and transmits the recovered data block to the host system.

[0290] Specifically, the target flash memory device receives a data recovery command sent by the host system and, based on a mapping relationship between a read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffers of other flash memory devices, obtains a third data block, the third data block including an undamaged data block in the stripe data. The target flash memory device then reads verification data corresponding to the stripe data containing the third data block from the flash memory medium, performs an exclusive-OR operation on the third data block and the verification data to obtain a second data block corresponding to the damaged data block, and stores the second data block in a memory buffer mapping area. Furthermore, based on an address mapping relationship between the host memory buffer and the memory buffer mapping area of ​​the target flash memory device, the second data block is transmitted to a destination storage offset address of the second data block in the host memory buffer of the host system.

[0291] In the embodiment of the present application, the host system in the distributed redundant array of independent disks system executes the data management method in embodiment one, and the storage array executes the data verification method in embodiment two. The present application can distribute RAID calculation tasks to each flash memory device in the storage array, does not require a dedicated RAID controller, can reduce the data transmission process between the RAID controller and the storage device, and reduce the bandwidth requirement of the redundant array of independent disks system.

[0292] Example 4

[0293] An embodiment of the present application also provides a non-volatile computer storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by one or more processors, enabling the one or more processors to execute the data management method in the above-mentioned method embodiment 1, or execute the data verification method in the above-mentioned method embodiment 2.

[0294] The above-described device or apparatus embodiments are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units, that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment.

[0295] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the relevant technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or certain parts of the embodiment.

[0296] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the idea of ​​the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data management method, applied to a host system, characterized in that: The host system is communicatively connected to a plurality of flash memory devices, wherein each of the flash memory devices has a first memory mapping relationship with other flash memory devices; The method comprises: Establishing a second memory mapping relationship between the host system and each of the flash memory devices; storing a plurality of data blocks corresponding to the stripe data in a plurality of flash memory devices, wherein each data block corresponds to a flash memory device one by one; determining a target flash memory device as a computing engine; A verification command is sent to the target flash memory device, so that the target flash memory device performs data calculation on a plurality of the data blocks based on the second memory mapping relationship, so as to generate and store verification data.

2. The method according to claim 1, characterized in that Each of the flash memory devices comprises a memory buffer mapping area, and the memory buffer mapping area is used to store at least one of the data blocks; The verification command includes a write verification data command, and the write verification data command includes an offset address and a data length of each data block in a host memory buffer, and a logical address corresponding to the verification data; The establishing of a second memory mapping relationship between the host system and each of the flash memory devices includes: A host memory buffer is divided in the memory of the host system, wherein the host memory buffer is used to store stripe data, wherein the stripe data is divided into a plurality of data blocks; Mapping the host memory buffer to the storage space of each of the flash memory devices to establish a mapping relationship between the host memory buffer and the memory buffer mapping area of ​​each of the flash memory devices; The sending a verification command to the target flash memory device so that the target flash memory device performs data calculation on a plurality of the data blocks based on the second memory mapping relationship to generate and store verification data includes: A write verification command is sent to the target flash memory device, so that the target flash memory device performs data calculation on a plurality of the data blocks in a memory buffer mapping area to generate and store verification data.

3. The method according to claim 1, characterized in that Each of the flash memory devices includes a read-write storage buffer and a read-write storage buffer mapping area, and the first memory mapping relationship includes a mapping relationship between the read-write storage buffer mapping area of ​​each flash memory device and the read-write storage buffer of other flash memory devices; The read-write storage buffer is used to store data blocks read from the flash memory medium, and the read-write storage buffer mapping area is used to store data blocks from other flash memory devices; The verification command includes an update verification data command, wherein the update verification data command includes an offset address and a data length of the first data block in the host memory buffer, a logical address of each of the unupdated data blocks in the flash memory device where they are located, and a logical address corresponding to the updated verification data; The method further comprises: updating at least one of the data blocks to obtain at least one first data block; storing the first data block in a corresponding flash memory device; An update verification data command is sent to the target flash memory device, so that the target flash memory device performs data calculation on the first data block and the unupdated data blocks in the stripe data based on the first memory mapping relationship and the second memory mapping relationship, so as to generate and store updated verification data.

4. The method according to claim 3, characterized in that The method further comprises: When any of the data blocks is damaged, sending a data recovery command to the target flash memory device, so that the target flash memory device recovers the damaged data block based on the first memory mapping relationship and the second memory mapping relationship to generate a second data block; Based on the second memory mapping relationship, acquiring the second data block; The data recovery command includes the logical address of the third data block in the corresponding flash memory device, the logical address corresponding to the verification data, and the destination storage offset address of the second data block in the host memory buffer. The third data block includes an undamaged data block in the stripe data, and the second data block is a data block obtained after the damaged data block is recovered.

5. A host system, characterized in that: The data management method according to any one of claims 1 to 4 is applied, wherein the host system comprises: A processor system, connected to the host memory system, for dividing a stripe of data into a plurality of data blocks and transmitting the data blocks to the host memory system; The host memory system is connected to the processor system and is used to store the data block.

6. A method for verifying data, applied to a storage array, characterized in that: The storage array includes a plurality of flash memory devices, each of the flash memory devices has a first memory mapping relationship with other flash memory devices, each of the flash memory devices is communicatively connected to a host system, and each of the flash memory devices has a second memory mapping relationship with the host system; The method comprises: Based on the verification command sent by the host system and the second memory mapping relationship, data calculation is performed on several data blocks to generate and store verification data, wherein the verification data is directly stored in the flash memory medium by the target flash memory device, and the verification command and the data block are obtained by the data management method described in any one of claims 1-4.

7. The method according to claim 6, characterized in that The verification command includes a write verification data command, the host system includes a host memory buffer, and the host memory buffer is used to store stripe data, wherein the stripe data is divided into a plurality of data blocks; Each of the flash memory devices comprises a memory buffer mapping area, and the memory buffer mapping area is used to store at least one of the data blocks; The second memory mapping relationship includes the host memory buffer of the host system and each flash memory device The mapping relationship of the memory buffer mapping area of ​​the backup; The step of performing data calculation on a plurality of data blocks based on the verification command sent by the host system and the second memory mapping relationship to generate and store verification data includes: Receive and parse the write verification data command to obtain the offset address and data length of each data block in the host memory buffer, and the logical address corresponding to the verification data; Based on the second mapping relationship, the offset address and the data length of each of the data blocks in the host memory buffer, obtaining a plurality of data blocks corresponding to the stripe data; In the memory buffer mapping area of ​​the target flash memory device, an XOR operation is performed on all data blocks in the stripe data to obtain verification data corresponding to the stripe data; The logical address corresponding to the verification data is used as a storage index to store the verification data in a flash memory medium.

8. The method according to claim 7, characterized in that The first memory mapping relationship includes a mapping relationship between a read-write storage buffer mapping area of ​​each flash memory device and a read-write storage buffer area of ​​other flash memory devices, and the method further includes: Dividing a read-write storage buffer in the memory of each of the flash memory devices, wherein the read-write storage buffer is used to store data blocks read from the flash memory medium; The read-write storage buffer is mapped to the storage space of each remaining flash memory device to establish a mapping relationship between the read-write storage buffer mapping area of ​​each flash memory device and the read-write storage buffer of other flash memory devices, wherein the read-write storage buffer mapping area is used to store data blocks from other flash memory devices, and the first memory mapping relationship includes a mapping relationship between the read-write storage buffer mapping area of ​​each flash memory device and the read-write storage buffer of other flash memory devices.

9. The method according to claim 8, characterized in that The method further comprises: Acquire a first data block based on a mapping relationship between an update verification data command sent by the host system, a host memory buffer of the host system, and a memory buffer mapping area of ​​a target flash memory device; Based on the mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffer areas of other flash memory devices, obtaining the unupdated data blocks in the stripe data; Data calculation is performed on the first data block and the unupdated data blocks in the stripe data to generate and store updated verification data, wherein the update verification data command and the first data block are obtained by the data management method described in claim 3.

10. The method according to claim 9, characterized in that The method of obtaining a first data block based on a mapping relationship between an update verification data command sent by the host system, a host memory buffer of the host system, and a memory buffer mapping area of ​​a target flash memory device comprises: Receive and parse the update verification data command to obtain the offset address and data length of the first data block in the host memory buffer, the logical addresses of the unupdated data blocks in the flash memory devices where they are located, and the logical addresses corresponding to the updated verification data; The first data block is acquired based on a mapping relationship between a host memory buffer of the host system and a memory buffer mapping area of ​​a target flash memory device, an offset address and a data length of the first data block in the host memory buffer.

11. The method according to claim 8, characterized in that The method further comprises: Based on the data recovery command sent by the host system, the mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffer area of ​​other flash memory devices, a third data block is obtained, wherein the third data block includes an undamaged data block in the stripe data; The damaged data block is restored according to the third data block and the verification data, wherein the data recovery command and the third data block are obtained by the data management method according to claim 4.

12. The method according to claim 11, characterized in that The method of obtaining a third data block based on a data recovery command sent by the host system, a mapping relationship between a read-write storage buffer mapping area of ​​a target flash memory device and a read-write storage buffer area of ​​other flash memory devices, comprises: Receive and parse the data recovery command to obtain the logical address of the third data block in the corresponding flash memory device, the logical address corresponding to the verification data, and the destination storage offset address of the second data block in the host memory buffer; Sending a second read command to each flash memory device storing the third data block to obtain an address of each third data block in a read / write storage buffer of the corresponding flash memory device, wherein the second read command includes a logical address of the third data block in the corresponding flash memory device; Based on the mapping relationship between the read-write storage buffer mapping area of ​​the target flash memory device and the read-write storage buffer area of ​​other flash memory devices, and the address of each third data block in the read-write storage buffer area of ​​the corresponding flash memory device, each third data block is obtained through a point-to-point operation; The step of recovering the damaged data block according to the third data block and the verification data comprises: Reading the verification data from the flash memory medium of the target flash memory device based on the logical address corresponding to the verification data; In the read-write storage buffer mapping area of ​​the target flash memory device, an XOR operation is performed on a plurality of the third data blocks and the verification data to obtain the second data block, and the second data block is transmitted to the destination storage offset address of the host memory buffer.

13. A storage array, characterized in that: Applying the method for verifying data as described in any one of claims 6 to 12, the storage array includes a plurality of flash memory devices; Each of the flash memory devices comprises: Redundant Array of Independent Disks engine; At least one flash memory medium is communicatively connected to the redundant array of independent disks engine.

14. A distributed redundant array of independent disks system, characterized in that: include: The host system as claimed in claim 5; The storage array of claim 13, wherein: The host system is connected to the storage array via a communication bus.

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