Multi-thread scheduling method, server and computer system

Abstract

Disclosed in the embodiments of the present application are a multi-thread scheduling method, a server and a computer system, used for avoiding multi-threading cross-node remote access and reducing overhead of running a first thread and a second thread. The method in the embodiments of the present application comprises: according to first memory access information of a first thread in a first running stage and second memory access information of a second thread in a second running stage, determining information of affinity between the first thread and the second thread; according to the first memory access information, the second memory access information and the information of affinity, determining a first node; determining that a resource metric value of the first node is less than a resource threshold value; and selecting from the first node a processor unit used for running the first thread and the second thread.

Description

Multi-threaded scheduling method, server and computer system

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on October 25, 2023, with application number 202311393619.9 and invention name “A multi-threaded scheduling method, server and computer system”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a multi-threaded scheduling method, a server, and a computer system. Background Art

[0003] The architecture of computer devices has evolved from a single central processing unit (CPU) to multiple CPUs. As the number of CPUs increases, the computing power of computer devices is no longer the performance bottleneck. Multiple CPUs all access memory, and memory becomes the performance bottleneck.

[0004] Computer systems operate in a complex environment. They distribute multiple threads to different nodes through load balancing to maximize task parallelism. However, this method of assigning nodes to threads can lead to cross-node remote access, increasing the overhead of executing threads.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a multi-threaded scheduling method, server, and computer system for reducing the overhead of executing threads.

[0007] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0008] In the first aspect, an embodiment of the present application provides a multi-thread scheduling method, comprising: determining kinship information between the first thread and the second thread based on first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage; determining a first node based on the first memory access information, the second memory access information, and the kinship information; determining that the resource measurement value of the first node is less than a resource threshold; and selecting a processor unit for running the first thread and the second thread based on the first node. In the above scheme, since the first node is selected based on the kinship information, and the processor unit is allocated to the first thread and the second thread on the first node when the resource measurement value of the first node is less than the resource threshold, remote access across nodes of multiple threads is avoided, and the overhead of running the first thread and the second thread is reduced.

[0009] In a possible implementation of the first aspect, the affinity between the first thread and the second thread refers to the degree of similarity between the memory access information of the first thread and the memory access information of the second thread. The more similar the memory access information of the first thread and the memory access information of the second thread are, the stronger the affinity between the two threads. The greater the difference between the memory access information of the first thread and the memory access information of the second thread is, the weaker the affinity between the two threads.

[0010] In a possible implementation of the first aspect, the method further includes: collecting status information of a performance management unit during the first operating phase in a thread switching context, and determining the first memory access information based on the status information of the performance management unit. In the above scheme, a thread is the smallest unit of execution of a computer program, and a server schedules threads through a thread switching context. For example, the server determines through a thread switching context that the current thread switches to a first thread, and the first thread runs in a first phase. During the first operating phase, the status information of the performance management unit is collected, and the status information of the performance management unit records the address and frequency of memory access by the first thread, thereby obtaining the first memory access information.

[0011] In a possible implementation of the first aspect, collecting status information of the performance management unit during the first operating phase and determining the first memory access information based on the status information of the performance management unit include: reading first status information from a register of the performance management unit at the start of the first operating phase; reading second status information from the register at the end of the first operating phase; and determining the first memory access information based on the first status information and the second status information. In the above solution, when the first thread starts, the server reads first status information from the register of the performance management unit at the start of the first operating phase. For example, the first status information may be first PMU data. The first status information can be used to track the memory access status at the start of the first thread. When the first thread ends, the server reads the register of the performance management unit again at the end of the first operating phase to read second status information. For example, the second status information may be second PMU data. The second status information can be used to track the memory access status at the end of the first thread. After the server obtains the first status information at the start of the first thread and the second status information at the end of the first thread, it can compare the first status information and the second status information to determine the first memory access information of the first thread in the first operating phase.

[0012] In a possible implementation of the first aspect, the first memory access information includes: address information accessed by the first thread; the second memory access information includes: address information accessed by the second thread;

[0013] The method of determining the kinship information between the first thread and the second thread based on the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage includes: determining the same memory address range accessed by the first thread and the second thread based on the address information accessed by the first thread and the address information accessed by the second thread; obtaining the interaction frequency between the first thread and the second thread based on the memory address range; and determining the kinship information between the first thread and the second thread based on the interaction frequency. In the above scheme, after the server obtains the interaction frequency between the first thread and the second thread, the server can determine the kinship between the first thread and the second thread based on the interaction frequency, and the server generates kinship information, which indicates the strength of the kinship between the first thread and the second thread.

[0014] In a possible implementation of the first aspect, the obtaining of the interaction frequency between the first thread and the second thread according to the memory address range includes: merging the first thread and the second thread into a thread affinity group according to the memory address range; obtaining the interaction frequency between the first thread in the thread affinity group when it runs in the first running stage and the second thread in the second running stage, wherein the first running stage and the second running stage overlap in time. In the above scheme, the server can record the interaction frequency between threads in the same thread affinity group, and the server can record the interaction frequency between two threads in the same thread affinity group. For example, the thread affinity group includes a first thread and a second thread, the first thread runs in the first stage, and the second thread runs in the second stage, the first running stage and the second running stage overlap in time, and the server records the interaction frequency between the first thread and the second thread in the same thread affinity group.

[0015] In a possible implementation manner of the first aspect, the method further includes: acquiring resource occupancy information of the first node in a first time unit, and determining a resource load metric of the first node based on the resource occupancy information; and / or acquiring resource waiting information of the first node in a second time unit, and determining a resource interference metric of the first node based on the resource waiting information;

[0016] The determining that the resource metric value of the first node is less than the resource threshold includes: determining that the resource metric value of the first node is less than the resource threshold according to the resource load metric of the first node and / or the resource interference metric of the first node.

[0017] In the above scheme, the resource load measurement is used to measure the resource load situation, and the resource interference measurement is used to measure the resource interference situation. The server can determine the resource load size of the first node based on the resource load measurement. The server can determine the resource interference size of the first node based on the resource interference measurement. The server determines that the resource measurement value of the first node is less than the resource threshold based on at least one measurement value among the resource load measurement and the resource interference measurement. Through at least one measurement value among the above resource load measurement and resource interference measurement, multiple ways of determining that the resource measurement value of the first node is less than the resource threshold are realized. Specifically, the way to determine the resource bottleneck can be selected in combination with the application scenario.

[0018] In a possible implementation of the first aspect, the determination that the resource metric value of the first node is less than the resource threshold includes: obtaining the processor unit metric value, and / or memory metric value, and / or input / output metric value of the first node; determining that the processor unit metric value of the first node is less than the computing power threshold, and / or, determining that the memory metric value of the first node is less than the memory threshold, and / or, determining that the output / input metric value of the first node is less than the input / output threshold. In the above scheme, the operating system of the server can generate an instruction for scheduling the processor unit or a load balancing instruction, and the server can detect the resource information of the first node under the triggering of the above instruction to determine that the resource metric value of the first node is less than the resource threshold, so that the server can determine that the resource metric value of the first node is less than the resource threshold according to the instruction of the operating system.

[0019] In a possible implementation of the first aspect, determining the first node based on the first memory access information, the second memory access information, and the kinship information includes: selecting, from the task group, the node with the most frequent memory access as the first node based on the first memory access information, the second memory access information, and the kinship information. In the above solution, the server determines that there is a strong kinship between the first thread and the second thread based on the kinship information between the first thread and the second thread, determines to assign the same node to the first thread and the second thread, and selects, from the task group, the node with the most frequent memory access as the first node.

[0020] In a possible implementation of the first aspect, after selecting a processor unit for running the first thread and the second thread from the first node, the method further includes: determining a thread with a low memory access frequency from the first thread and the second thread based on the memory access frequency of the first thread and the memory access frequency of the second thread; and determining not to migrate the thread with a low memory access frequency in response to the resource measurement value of the first node being less than a resource threshold. In the above scheme, the server can determine the thread with a low memory access frequency from the first thread and the second thread when implementing load balancing, and then the server determines whether there is a resource bottleneck on the first node. When the resource measurement value of the first node is less than the resource threshold, the server does not allow the thread with a low memory access frequency to migrate, so that the first thread and the second thread can be assigned to the same processor unit, thereby avoiding remote access across nodes of multiple threads and reducing the overhead of running the first thread and the second thread.

[0021] In a possible implementation of the first aspect, the method further includes: in response to the resource measurement value of the first node being greater than or equal to the resource threshold, migrating the thread with low memory access frequency from the first node to the second node, the second node being a remote node of the first node. In the above scheme, the server can determine the thread with low memory access frequency between the first thread and the second thread when implementing load balancing, and then the server determines whether there is a resource bottleneck on the first node. When the resource measurement value of the first node is greater than or equal to the resource threshold, it is necessary to migrate the thread with low memory access frequency, migrate the thread with low memory access frequency from the first node to the second node, the second node being a remote node of the first node, and execute the thread with low memory access frequency through the second node to ensure the execution efficiency of the thread currently retained on the first node, so as to achieve a balance between scheduling resources and performance.

[0022] In a possible implementation of the first aspect, the determination that the resource metric value of the first node is less than the resource threshold includes: periodically determining that the resource metric value of the first node is less than the resource threshold based on the resource information of the first node; or, determining that the resource metric value of the first node is less than the resource threshold in response to an instruction of the scheduling processor unit or a load balancing instruction. In the above scheme, the operating system of the server can generate an instruction of the scheduling processor unit or a load balancing instruction, and the server can detect the resource information of the first node under the triggering of the above instruction to determine that the resource metric value of the first node is less than the resource threshold, so that the server can determine that the resource metric value of the first node is less than the resource threshold according to the instruction of the operating system.

[0023] In a second aspect, an embodiment of the present application further provides a server, including:

[0024] An affinity determination module, configured to determine affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running phase and second memory access information of the second thread in the second running phase;

[0025] a node determination module, configured to determine a first node according to the first memory access information, the second memory access information, and the kinship information;

[0026] a resource measurement module, configured to determine that a resource measurement value of the first node is less than a resource threshold;

[0027] A selection module is configured to select a processor unit for running the first thread and the second thread according to the first node.

[0028] In the above scheme, first, the affinity information between the first thread and the second thread is determined based on the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage. The affinity information indicates that there is an affinity between the first thread and the second thread. Then, the first node is determined based on the first memory access information, the second memory access information and the affinity information. For example, the first node can be a node in the NUMA architecture. Next, it is determined that the resource measurement value of the first node is less than the resource threshold. The absence of a resource bottleneck indicates that the resources on the first node can be used by multiple threads. Finally, a processor unit for running the first thread and the second thread is selected from the first node. Since the first node is selected by affinity information in the embodiment of the present application, and the processor unit is allocated to the first thread and the second thread on the first node when the resource measurement value of the first node is less than the resource threshold, remote access across nodes of multiple threads is avoided, and the overhead of running the first thread and the second thread is reduced.

[0029] In the second aspect of the present application, the component modules of the server can also execute the steps described in the aforementioned first aspect and various possible implementations. For details, please refer to the aforementioned description of the first aspect and various possible implementations.

[0030] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium. When the computer-readable storage medium is run on a computer, the computer executes the method described in the first aspect above.

[0031] In a fourth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0032] In the fifth aspect, an embodiment of the present application provides a communication device, which may include entities such as a terminal device, a server, a computer system or a chip, and the communication device includes: a processor, a memory; the memory is used to store instructions; the processor is used to execute the instructions in the memory, so that the communication device performs a method as described in any one of the above-mentioned first aspects.

[0033] In a sixth aspect, the present application provides a chip system, which includes a processor for supporting a server or computer system to implement the functions involved in the above aspects, for example, sending or processing the data and / or information involved in the above methods. In one possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the server or computer system. The chip system can be composed of a chip or can include a chip and other discrete devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic diagram of a system architecture applicable to a multi-threaded scheduling method provided in an embodiment of the present application;

[0035] FIG2 is a flow chart of a multi-threaded scheduling method according to an embodiment of the present application;

[0036] FIG3 is a schematic diagram of an affinity relationship between threads provided by an embodiment of the present application;

[0037] FIG4 is a schematic diagram of an interaction frequency for communication between threads provided by an embodiment of the present application;

[0038] FIG5 is a schematic diagram of resource load measurement provided by an embodiment of the present application;

[0039] FIG6 is a schematic diagram of resource interference measurement provided in an embodiment of the present application;

[0040] FIG7 is a schematic diagram of the relationship between the CPU and memory in the NUMA architecture provided by an embodiment of the present application;

[0041] FIG8 is a schematic diagram of dynamically determining intra-NUMA scheduling or inter-NUMA scheduling according to an embodiment of the present application;

[0042] FIG9 is a schematic diagram of an application scenario in which a server according to an embodiment of the present application is applied to an NMUA architecture;

[0043] FIG10 is a schematic diagram of the software and hardware structure of a server provided in an embodiment of the present application;

[0044] FIG11 is a schematic diagram of the composition structure of a server provided in an embodiment of the present application;

[0045] FIG12 is a schematic diagram of the composition structure of a computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] Embodiments of the present application provide a multi-threaded scheduling method, server, and computer system for reducing the overhead of executing threads.

[0047] The embodiments of the present application are described below with reference to the accompanying drawings.

[0048] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0049] The technical solution of the embodiment of the present application can be applied to a server, which can adopt a non-uniform memory access (NUMA) architecture. The NUMA architecture is a computer system composed of multiple nodes, and each node has a processor unit and memory belonging to the node. From the perspective of a single processor unit, the memory can be divided into local memory and remote memory. The local memory has a low access latency, but limited capacity. The remote memory has a large capacity, but a large access latency, and it is necessary to choose whether to use local memory or remote memory. Since the business in the computer system is relatively complex, the computer system will distribute multiple threads to different nodes through load balancing to maximize the parallelism of the task. However, this method of allocating nodes to threads will result in remote access to nodes across NUMA, and there is a problem of increased overhead in executing threads.

[0050] In order to solve the problem of high thread overhead mentioned above, an embodiment of the present application provides a multi-thread scheduling method, as shown in Figure 1. First, the system architecture applicable to the method provided in the embodiment of the present application is briefly described. The method is executed by a server, and the server includes multiple memories and processor units. Multiple threads are enabled in the server, for example, the multiple threads include a first thread and a second thread. When the thread is running, the server obtains the memory access information of the thread, for example, the server obtains the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage, and determines the affinity information between the first thread and the second thread based on the first memory access information and the second memory access information. The server assigns the first thread and the second thread to the same node (i.e., the first node) based on the affinity information between the first thread and the second thread. Next, the server identifies whether there is a resource bottleneck in the first node. When the resource measurement value of the first node is less than the resource threshold, the server selects the processor unit for running the first thread and the second thread based on the first node. In the embodiment of the present application, the server selects the first node based on the affinity information, and when the resource measurement value of the first node is less than the resource threshold, the processor unit is assigned to the first thread and the second thread on the first node, thereby avoiding remote access across nodes of multiple threads and reducing the overhead of running the first thread and the second thread.

[0051] The following are the technical terms involved in the embodiments of this application:

[0052] NUMA architecture:

[0053] The NUMA architecture is a computing system composed of multiple nodes, each of which has its own central processing unit (CPU) and memory. The server can collect memory resource information to determine if there is a memory bottleneck.

[0054] Resource bottlenecks:

[0055] A resource bottleneck refers to the server's inability to provide timely or sufficient resources to the business. When a resource bottleneck exists on the server, business performance will be affected. Resource bottlenecks mainly include at least one of the following: computing power bottleneck, memory bottleneck, and input and output (IO) bottleneck.

[0056] Performance management unit (PMU) sampling:

[0057] In computer systems, a performance management unit (PMU) is a hardware unit on an X64 or ARM processor that records various performance states of the processor while running application code. PMU sampling is a general term for methods that can read hardware performance registers. In computer systems, hardware performance register information is read periodically or triggered by events and associated with the currently running thread. This allows identification of the thread's memory access information, which indicates the thread's running status.

[0058] For example, the server can read the status information of the PMU register, which includes: ARM statistical profiling extensions (SPE) information, where SPE information refers to the extended information of general registers on the ARM V8 architecture, which records information such as instruction address, data address, event type, and time. Based on this information, the memory access behavior of the thread can be quantified.

[0059] Interference Modeling:

[0060] Interference modeling is a quantitative analysis of resource interference between threads in a computer system. It assesses the degree of interference between threads by reading various information in the computer system.

[0061] Load Balancing:

[0062] Load balancing is the act of sharing tasks between multiple CPUs in a computer system. Each CPU has a task queue. Due to the different running times of different tasks, some CPUs are busy while others are idle. Load balancing is responsible for balancing the tasks on different CPUs.

[0063] Remote memory access / local memory access:

[0064] The NUMA architecture features multiple CPU modules, each composed of multiple CPUs and equipped with independent local memory, I / O slots, and other features. Because nodes are connected and exchange information via interconnect modules, each CPU can access the entire system's memory. From the perspective of a single CPU, there are local and remote memory units. Accessing local memory is significantly faster than accessing remote memory, which refers to the memory of other nodes within the system.

[0065] Resource load metrics and resource interference metrics:

[0066] Resource load measurement measures resource load by resource usage time or cycles. Resource load measurement is used to measure resource busyness. Resource busyness refers to the degree to which a resource is being utilized. For example, if a CPU is constantly running tasks within one second, the CPU utilization is 100%, indicating that the CPU is very busy or highly loaded.

[0067] Resource interference measurement measures resource interference by resource wait time or cycle time. Resource interference measurement is used to measure resource contention. Resource contention refers to the situation where multiple tasks simultaneously attempt to use the same resource (such as CPU, memory, or I / O). This means that these tasks compete for or interfere with the CPU, memory, or I / O resources.

[0068] Next, the multi-thread scheduling method proposed in the embodiment of the present application is described. This method is applicable to a scenario in which a server allocates processor units to execute multiple threads. Referring to FIG2 , the multi-thread scheduling method provided in the embodiment of the present application mainly includes the following steps:

[0069] 201. Determine affinity information between the first thread and the second thread according to first memory access information of the first thread in a first running phase and second memory access information of the second thread in a second running phase.

[0070] Multiple threads are enabled in the server, for example, the multiple threads include a first thread and a second thread. The first thread generates first memory access information when running in the first operating phase, and the second thread generates second memory access information when running in the second operating phase. The server can first collect the first memory access information and the second memory access information, and then determine the affinity information between the first thread and the second thread based on the first memory access information and the second memory access information. The server can perceive the affinity of the two threads through the memory access information of each of the two threads. The affinity between the threads refers to the degree of similarity between the memory access information of different threads. The more similar the memory access information between the two threads is, the stronger the affinity between the two threads is, and the greater the difference in the memory access information between the two threads is, the weaker the affinity between the two threads is.

[0071] In some embodiments of the present application, in addition to performing the aforementioned step 201, the method provided in the embodiment of the present application further includes:

[0072] A1. Collecting status information of a performance management unit in a first running phase in a thread switching context, and determining first memory access information according to the status information of the performance management unit.

[0073] Among them, a thread is the smallest unit of execution of a computer program. The server schedules threads through thread switching context. For example, the server determines through thread switching context that the current thread switches to the first thread. The first thread runs in the first stage. During the first running stage, the status information of the performance management unit is collected. The status information of the performance management unit records the address and frequency of the memory access of the first thread, so that the first memory access information can be obtained.

[0074] In some embodiments of the present application, in addition to performing the aforementioned step 201, the method provided in the embodiment of the present application further includes:

[0075] In the second running phase in the thread switching context, state information of the performance management unit is collected, and second memory access information is determined according to the state information of the performance management unit.

[0076] Among them, the server determines that the current thread switches from the first thread to the second thread through the thread switching context. The second thread runs in the second stage. During the second running stage, the status information of the performance management unit is collected. The status information of the performance management unit records the address and frequency of the memory access of the second thread, so that the second memory access information can be obtained.

[0077] In some embodiments of the present application, step A1 of collecting status information of the performance management unit in the first operation phase and determining first memory access information based on the status information of the performance management unit includes:

[0078] A11. Reading first status information from a register of the performance management unit at the start of the first running phase;

[0079] A12. Reading second status information from the register at the end of the first operation phase;

[0080] A13. Determine first memory access information according to the first state information and the second state information.

[0081] Among them, when the first thread starts, the server reads the first state information from the register of the performance management unit at the beginning of the first running phase, for example, the first state information can be the first PMU data. The first state information can be used to track the memory access situation when the first thread starts. When the first thread ends, the server reads the register of the performance management unit again at the end of the first running phase to read the second state information, for example, the second state information can be the second PMU data. The second state information can be used to track the memory access situation when the first thread ends. After the server obtains the first state information when the first thread starts and the second state information when it ends, the server can compare the first state information and the second state information to determine the first memory access information of the first thread in the first running phase.

[0082] In some embodiments of the present application, status information of the performance management unit is collected in the second running phase in the thread switching context, and second memory access information is determined based on the status information of the performance management unit, including: reading third status information from the register of the performance management unit at the beginning of the second running phase; reading fourth status information from the register at the end of the second running phase; and determining the second memory access information based on the third status information and the fourth status information.

[0083] When the second thread starts, the server reads the third state information from the register of the performance management unit at the beginning of the second operating phase. For example, the third state information can be the third PMU data. The third state information can be used to track the memory access situation when the second thread starts. When the second thread ends, the server reads the register of the performance management unit again at the end of the second operating phase to read the fourth state information. For example, the fourth state information can be the fourth PMU data. The fourth state information can be used to track the memory access situation when the second thread ends. After the server obtains the third state information when the second thread starts and the second state information when it ends, the server can compare the third state information and the fourth state information to determine the second memory access information of the second thread in the second operating phase.

[0084] In some embodiments of the present application, the first memory access information includes: address information accessed by the first thread; the second memory access information includes: address information accessed by the second thread;

[0085] Step 201 determines the affinity information between the first thread and the second thread according to the first memory access information of the first thread in the first running phase and the second memory access information of the second thread in the second running phase, including:

[0086] B1. Determine, based on address information accessed by the first thread and address information accessed by the second thread, that the first thread and the second thread have the same memory address range.

[0087] The server obtains the address information accessed by the first thread from the first memory access information, and obtains the address information accessed by the second thread from the second memory access information. The server compares the address information accessed by the two threads to determine whether the first thread and the second thread access the same memory address range.

[0088] It can be understood that, in the embodiment of the present application, taking the determination of the affinity between the first thread and the second thread as an example, when the first thread and the second thread access different memory address ranges, the server can re-acquire the other two threads and determine that the two threads access the same memory address range based on the address information accessed by each thread.

[0089] B2. Obtain the interaction frequency between the first thread and the second thread according to the memory address range.

[0090] When the first thread and the second thread access the same memory address range, the server obtains an interaction frequency between the first thread and the second thread, where the interaction frequency is used to indicate a frequency at which the first thread and the second thread interact during execution. The interaction frequency can indicate a strength of an affinity relationship between the first thread and the second thread.

[0091] B3. Determine the affinity information between the first thread and the second thread according to the interaction frequency.

[0092] After the server obtains the interaction frequency between the first thread and the second thread, the server may determine the affinity between the first thread and the second thread based on the interaction frequency, and generate affinity information indicating the strength of the affinity between the first thread and the second thread.

[0093] Please refer to Figure 3, which is a schematic diagram of the affinity relationship between threads provided in an embodiment of the present application. Taking a server running four threads, namely thread A, thread B, thread C, and thread D as an example, the interaction frequency between threads A and B is 20, the interaction frequency between threads A and C is 5, the interaction frequency between threads A and D is 40, the interaction frequency between threads B and C is 40, the interaction frequency between threads B and D is 5, and the interaction frequency between threads C and D is 20. Based on the above example of the interaction frequency between threads, threads A and D and threads B and C have the strongest affinity, threads A and B, and threads D and C have relatively strong affinity, and threads A and C, and threads B and D have the weakest affinity.

[0094] In some embodiments of the present application, step B2 obtains the interaction frequency between the first thread and the second thread according to the memory address range, including:

[0095] B21. Merge the first thread and the second thread into a thread affinity group according to the memory address range.

[0096] The first and second threads access the same memory address range. The server establishes a thread affinity group and adds the first and second threads accessing the same memory address range to the thread affinity group. For example, the same memory address range can be accessed addresses belonging to the same page in memory. The thread affinity group simplifies access to the same memory address range by the first and second threads.

[0097] It is understandable that in the embodiment of the present application, if three or more threads access the same memory address range, the above multiple threads can be added to the thread affinity group.

[0098] B22. Obtain an interaction frequency between a first thread in a thread affinity group when running in a first running phase and a second thread in a second running phase, wherein the first running phase and the second running phase overlap in time.

[0099] The server may record the interaction frequency between threads in the same thread affinity group, and the server may record the interaction frequency between any two threads in the same thread affinity group. For example, if the thread affinity group includes a first thread and a second thread, the first thread runs in a first phase, and the second thread runs in a second phase, and the first and second phases overlap in time, the server may record the interaction frequency between the first and second threads in the same thread affinity group.

[0100] As an example, please refer to Figure 4, which is a schematic diagram of the interaction frequency of communication between threads provided in an embodiment of the present application. The server runs thread 1 and thread 2. Thread 1 includes three phases: task ready phase, task running phase, and task sleep phase. Thread 2 includes two phases: task running phase and task sleep phase.

[0101] In the context of thread switching, the server uses PMU sampling to identify thread affinity and relationship strength. Specifically, PMU sampling accurately identifies thread memory access behavior. When the CPU switches to a thread, it reads the status value of the PMU register, which includes the SPE register. When the thread finishes running and switches to the next thread, it reads the PMU register status value again. The difference between the two read PMU register status values ​​identifies the memory access information of the thread during execution.

[0102] Taking thread 2 as an example, PMU sampling is performed at the start and end of the task. The PMU data obtained includes the access address and the number of accesses. For example, if the access address is XXXXXX, the number of accesses is 100, or if the access address is XXXXXX, the number of accesses is 200. The page information accessed by thread 2 is found based on the access address, the thread ID that recently accessed the same page is recorded, the interaction frequency between threads is updated, and the interaction frequency is normalized.

[0103] The server groups threads that access the same memory address range into the same group based on the address information and access frequency of the threads. For example, the same memory address range refers to the same page in memory. The server also sets up an array in each group to record the frequency of thread-to-thread communication.

[0104] 202. Determine a first node according to the first memory access information, the second memory access information, and the kinship information.

[0105] After the server detects the affinity between the first thread and the second thread, the server selects the same node for the first thread and the second thread from multiple memories of the server based on the affinity information and the first memory access information of the first thread and the second memory access information of the second thread. The same node is defined as the first node. When the affinity between the first thread and the second thread is strong, both threads are assigned to the first node.

[0106] An example is given below. In the thread scheduling process, the server selects a NUMA node based on the memory access information and affinity of the two threads. The memory access information may include: thread access address information and memory access frequency. The server selects a NUMA node based on the memory access frequency from high to low. The NUMA node can be used to run the two threads.

[0107] In some embodiments of the present application, step 202 of determining the first node according to the first memory access information, the second memory access information, and the kinship information includes:

[0108] C1. Selecting a node with the highest memory access frequency from the task group as the first node based on the first memory access information, the second memory access information, and the affinity information.

[0109] Among them, the server determines that there is a strong affinity between the first thread and the second thread based on the affinity information between the first thread and the second thread, and the server determines to allocate the same node to the first thread and the second thread. The server selects the node with the most frequent memory access frequency from the task group as the first node. When selecting the first node, the server still needs to execute the subsequent step 203 to determine whether the resource measurement value of the first node is less than the resource threshold. If the resource measurement value of the first node is greater than or equal to the resource threshold, the server re-executes step 202 to select the first node.

[0110] 203. Determine whether the resource metric value of the first node is less than a resource threshold.

[0111] After the server determines the first node, it collects resource measurement information of the first node. The resource measurement information may include measurement values ​​of one or more resource types. Nodes may have various resource types, such as CPU resources, memory resources, and I / O resources. Based on the resource information of the first node, it is determined whether the resource measurement value of the first node is less than a resource threshold. If the resource measurement value of the first node is less than the resource threshold, execution of subsequent step 203 is triggered.

[0112] It is understandable that in the embodiment of the present application, the server identifies whether the resource measurement value of the first node is less than the resource threshold, so that the server can determine whether the first node has a resource bottleneck. For example, if the resource measurement value of the first node is less than the resource threshold, the server determines that the first node has a resource bottleneck; if the resource measurement value of the first node is greater than or equal to the resource threshold, the server determines that the first node does not have a resource bottleneck. For another example, if the resource measurement value of the first node is less than or equal to the resource threshold, the server determines that the first node has a resource bottleneck; if the resource measurement value of the first node is greater than the resource threshold, the server determines that the first node does not have a resource bottleneck. The specific value-taking method of the above-mentioned resource threshold is not limited, and specifically depends on the resource type of the node and the threshold values ​​corresponding to various types of resources in the actual application scenario. In the subsequent embodiments, the resource measurement value of the first node is less than the resource threshold to explain in detail the specific entity implementation method of the first node not having a resource bottleneck.

[0113] In some embodiments of the present application, as shown in FIG5 , in addition to executing steps 201 to 203 above, the method provided in the embodiment of the present application further includes:

[0114] D1. Obtain resource occupancy information of the first node in the first time unit;

[0115] D2. Determine a resource load metric of the first node according to the resource occupancy information.

[0116] The resource information collected by the server from the first node may specifically be resource occupancy information of the first node in the first time unit. The resource occupancy information may represent resource occupancy time or resource occupancy cycle. The resource load is measured using the resource occupancy information to determine the resource load metric of the first node. The resource busyness is measured using the resource load metric. For example, resource busyness refers to the degree to which a resource is utilized. For example, if a CPU has tasks running for 1 second, the CPU utilization is 100%, indicating that the CPU is very busy or has a high load.

[0117] As shown in Figure 5, the resource occupancy period includes: period 1 and period 2, period 1 includes the time period from time 1 to time 2, and period 2 includes the time period from time 2 to time 3. The resource occupancy time of the first node is obtained for period 1 and period 2 respectively, and the resource load measurement of the first node in period 1 is determined based on the resource occupancy time of period 1, and the resource load measurement of the first node in period 2 is determined based on the resource occupancy time of period 2.

[0118] In an implementation scenario where the server performs steps D1 to D2, step 203 of determining that the resource metric value of the first node is less than the resource threshold includes:

[0119] E1. Determine, according to the resource load measurement of the first node, that a resource measurement value of the first node is less than a resource threshold.

[0120] The resource load metric is used to measure the resource load. The server can determine the resource load size of the first node based on the resource load metric. When the resource load metric is small, it is determined that the resource metric value of the first node is less than the resource threshold.

[0121] In some embodiments of the present application, in addition to performing steps 201 to 203 above, the method provided in the embodiments of the present application further includes:

[0122] F1. Obtain resource waiting information of the first node in the second time unit;

[0123] F2. Determine a resource interference metric of the first node according to the resource waiting information.

[0124] The resource information collected by the server from the first node may specifically be the resource waiting information of the first node in the second time unit. The resource waiting information may represent the resource waiting time or the resource waiting cycle. The resource interference situation is measured by the resource waiting information to determine the resource interference metric of the first node. The resource contention degree is measured by the resource interference metric. The resource contention degree refers to the situation where multiple tasks use the same resource (such as CPU, memory, IO) at the same time. At this time, there is a process of competing for resources among the multiple tasks. These multiple tasks compete or interfere with each other on resources such as CPU, memory, IO, etc.

[0125] As shown in Figure 6, cycle 1 includes the time period from time 1 to time 2. The waiting time of the resources of the first node in cycle 1 is calculated, and the resource interference measurement of the first node is determined based on the waiting time. A thread is started on each NUMA to periodically measure whether the resources of the NUMA have reached a bottleneck. When the CPU, memory, IO utilization or interference reaches a threshold, it is determined that the NUMA has reached a resource bottleneck. The threshold is set by the system default or input by the business program.

[0126] In the implementation scenario where the server executes steps F1 to F2, step 203 of determining that the resource metric value of the first node is less than the resource threshold includes:

[0127] G1. Determine, according to the resource interference metric of the first node, that a resource metric value of the first node is less than a resource threshold.

[0128] The resource interference metric is used to measure resource interference. The server can determine the resource interference size of the first node based on the resource interference metric. When the resource interference metric is small, it is determined that the resource metric value of the first node is less than the resource threshold.

[0129] In some embodiments of the present application, in addition to performing steps 201 to 203 above, the method provided in the embodiments of the present application further includes:

[0130] H1. Obtain resource occupancy information of the first node in the first time unit, and determine the resource load measurement of the first node based on the resource occupancy information; and / or, H2. Obtain resource waiting information of the first node in the second time unit, and determine the resource interference measurement of the first node based on the resource waiting information.

[0131] The resource occupancy information and resource waiting information may be specifically as shown in FIG. 5 and FIG. 6 , and will not be described in detail here.

[0132] In the implementation scenario where the server executes steps H1 and / or H2, step 203 of determining that the resource metric value of the first node is less than the resource threshold includes:

[0133] I1. Determine, based on a resource load metric of the first node and / or a resource interference metric of the first node, that a resource metric value of the first node is less than a resource threshold.

[0134] Among them, the resource load measurement is used to measure the load of resources, and the resource interference measurement is used to measure the interference of resources. The server can determine the resource load size of the first node based on the resource load measurement, and the server can determine the resource interference size of the first node based on the resource interference measurement. The server determines that the resource measurement value of the first node is less than the resource threshold based on at least one measurement value of the resource load measurement and the resource interference measurement. Through at least one measurement value of the above-mentioned resource load measurement and resource interference measurement, multiple ways of determining that the resource measurement value of the first node is less than the resource threshold are realized. Specifically, the way to determine the resource bottleneck can be selected in combination with the application scenario.

[0135] In some embodiments of the present application, step 203 of determining that the resource metric value of the first node is less than the resource threshold includes:

[0136] J1. Obtain processor unit metric values, and / or memory metric values, and / or input / output metric values ​​of the first node;

[0137] J2. Determine that the processor unit metric value of the first node is less than the computing power threshold, and / or determine that the memory metric value of the first node is less than the memory threshold, and / or determine that the output-input metric value of the first node is less than the input-output threshold.

[0138] The server can sense resource bottlenecks. For example, the resources of the first node may include at least one of the following: a processor unit metric, a memory metric, and an input / output metric. The server can sense resource bottlenecks based on at least one of the above resources. Regardless of which of the above resources has a bottleneck, the server can determine that the resource metric of the first node is greater than or equal to a resource threshold.

[0139] For example, the processor unit metric value of the first node may include CPU operating information. If the processor unit metric value of the first node is determined to be less than a computing power threshold, for example, if the processor unit metric value of the first node is less than the computing power threshold, the server determines that the first node has a computing power bottleneck. The computing power threshold value can be flexibly selected based on the application scenario and is not limited here. When the first node has a computing power bottleneck, the server will not allocate the same processor resources to the first thread and the second thread to avoid reducing the execution efficiency of the threads.

[0140] The memory metric value of the first node may include memory operation information. If the memory metric value of the first node is determined to be less than a memory threshold, for example, if the memory metric value of the first node is less than the memory threshold, the server determines that the first node has a memory bottleneck. The memory threshold value can be flexibly selected based on the application scenario and is not limited here. If the first node has a memory bottleneck, the server will not allocate the same processor resources to the first thread and the second thread to avoid reducing thread execution efficiency.

[0141] The input / output metric value of the first node may include IO information. If the input / output metric value of the first node is determined to be less than an input / output threshold, for example, if the input / output metric value of the first node is less than the input / output threshold, the server determines that an input / output bottleneck exists on the first node. The input / output threshold value can be flexibly selected based on the application scenario and is not limited here. If an input / output bottleneck exists on the first node, the server will not allocate the same processor resources to the first thread and the second thread to avoid reducing thread execution efficiency.

[0142] In some embodiments of the present application, step 203 of determining that the resource metric value of the first node is less than the resource threshold includes:

[0143] L1. Periodically determine, based on the resource information of the first node, whether the resource metric value of the first node is less than a resource threshold; or

[0144] L2. In response to an instruction of the scheduling processor unit or a load balancing instruction, determine that the resource metric value of the first node is less than a resource threshold.

[0145] Among them, the triggering execution of the server determining that the resource metric value of the first node is less than the resource threshold can be a periodic operation. The server can determine that the resource metric value of the first node is less than the resource threshold by periodically detecting the resource information of the first node, so that the server can promptly determine that the resource metric value of the first node is less than the resource threshold. Alternatively, the triggering execution of the server determining that the resource metric value of the first node is less than the resource threshold can be receiving an instruction from a scheduling processor unit or a load balancing instruction. The instruction of the scheduling processor unit can also be called a "core selection instruction". The server's operating system can generate an instruction from the scheduling processor unit or a load balancing instruction. The server can detect the resource information of the first node under the triggering of the above instruction to determine that the resource metric value of the first node is less than the resource threshold, so that the server can determine that the resource metric value of the first node is less than the resource threshold according to the instruction of the operating system.

[0146] 204. Select a processor unit for running the first thread and the second thread according to the first node.

[0147] When the resource metric value of the first node is less than the resource threshold, the server may select a processor unit from the first node, and the processor unit may be used to run the first thread and the second thread simultaneously.

[0148] As shown in Figure 7, taking a server using a NUMA architecture as an example, the server includes: CPU1, CPU2, memory 1, and memory 2. Each memory and each CPU are connected through a bus. Each CPU has a local memory with fast access speed. The CPU can also access the local memory of other CPUs. That is, the CPU accesses remote memory, and the speed of accessing remote memory is slightly slower than accessing local memory.

[0149] In some embodiments of the present application, after step 204 selects a processor unit for running the first thread and the second thread according to the first node, the method provided by the embodiment of the present application further includes:

[0150] M1. Determine a thread with a lower memory access frequency from the first thread and the second thread according to the memory access frequency of the first thread and the memory access frequency of the second thread;

[0151] M2. In response to the resource metric value of the first node being less than the resource threshold, determine not to migrate the thread with low memory access frequency.

[0152] The server can obtain the memory access frequency of the first thread in the first operation phase from the first memory access information of the first thread, obtain the memory access frequency of the second thread in the second operation phase from the second memory access information of the second thread, and determine the thread to be migrated from the memory access frequencies of the two threads, where the thread to be migrated is the thread with the lower memory access frequency between the first thread and the second thread. When implementing load balancing, the server can determine the thread with the lower memory access frequency between the first thread and the second thread, and then determine whether there is a resource bottleneck on the first node. When the resource measurement value of the first node is less than the resource threshold, the server does not allow the thread with the lower memory access frequency to migrate, so that the first thread and the second thread can be assigned to the same processor unit, thereby avoiding remote access across nodes of multiple threads and reducing the overhead of running the first thread and the second thread.

[0153] In some embodiments of the present application, in addition to performing the aforementioned steps M1 to M2, the method provided in the embodiments of the present application further includes:

[0154] N1. In response to a resource metric value of the first node being greater than or equal to a resource threshold, migrating a thread with a low memory access frequency from the first node to a second node, where the second node is a remote node of the first node.

[0155] Among them, the server can obtain the memory access frequency of the first thread in the first operation stage from the first memory access information of the first thread, obtain the memory access frequency of the second thread in the second operation stage from the second memory access information of the second thread, and determine the thread to be migrated from the memory access frequencies of the two threads. The thread to be migrated is the thread with the lower memory access frequency between the first thread and the second thread. When implementing load balancing, the server can determine the thread with the lower memory access frequency between the first thread and the second thread, and then determine whether there is a resource bottleneck on the first node. When the resource measurement value of the first node is greater than or equal to the resource threshold, the thread with the lower memory access frequency needs to be migrated. The thread with the lower memory access frequency is migrated from the first node to the second node, which is a remote node of the first node. The thread with the lower memory access frequency is executed through the second node to ensure the execution efficiency of the thread currently retained on the first node, and achieve a balance between scheduling resources and performance.

[0156] As illustrated below, the server modifies the current core selection and load balancing mechanism based on affinity and resource bottlenecks. As shown in FIG8 , a schematic diagram of dynamically determining intra-NUMA scheduling or inter-NUMA scheduling provided by an embodiment of the present application is shown. Taking the server adopting the NUMA architecture as an example, the server can dynamically decide whether to schedule within a NUMA or between NUMAs. The server creates a process, for example, by creating a process through the fork function, and selects a NUMA node for each process according to the interleave strategy. When the thread wakes up, an optimal node is selected based on the memory access information of the task group, and it is determined whether this node has a resource bottleneck. If a resource bottleneck exists, the other optimal nodes of the task group are selected, wherein the optimal node selection strategy is "this node is the node with the most frequent memory access by the task group". During load balancing, multiple threads are sorted according to the strength of the NUMA memory access frequency, and the thread with the weaker memory access frequency migrates first. When the thread migrates, if this NUMA is the optimal node for the task, it is determined whether the NUMA node has reached a resource bottleneck. If it has not reached a resource bottleneck, the thread with the weaker memory access frequency is not allowed to migrate.

[0157] In the embodiment of the present application, the server guides thread scheduling within and between NUMAs based on affinity and whether there are resource bottlenecks, thereby achieving a balance between scheduling resources and performance in a multi-NUMA environment.

[0158] Through the examples of the above embodiments, it can be seen that the affinity information between the first thread and the second thread is first determined based on the first memory access information of the first thread in the first running stage and the second memory access information of the second thread in the second running stage. The affinity information indicates that there is an affinity between the first thread and the second thread. Then, the first node is determined based on the first memory access information, the second memory access information and the affinity information. For example, the first node can be a node in the NUMA architecture. Next, it is determined that the resource measurement value of the first node is less than the resource threshold. The absence of a resource bottleneck indicates that the resources on the first node can be used by multiple threads. Finally, a processor unit for running the first thread and the second thread is selected from the first node. Since the first node is selected by affinity information in the embodiment of the present application, and the processor unit is allocated to the first thread and the second thread on the first node when the resource measurement value of the first node is less than the resource threshold, remote access across nodes by multiple threads is avoided, and the overhead of running the first thread and the second thread is reduced.

[0159] To facilitate a better understanding and implementation of the above solutions in the embodiments of the present application, the following examples are given for specific explanation using corresponding application scenarios.

[0160] Please refer to Figure 9, which is a schematic diagram of an application scenario of a server provided in an embodiment of the present application applied to an NMUA architecture. The system architecture applied in the embodiment of the present application can be a server scenario based on a NUMA architecture. The server can be a variety of types of servers, and the user-level application software includes distributed storage (ceph), in-memory database (redis), relational database (such as HBASE, MySQL), etc.

[0161] The server's real-time operating system (Kernel) includes software modules: an adaptive perception module and a scheduling module. The following describes the adaptive perception module and the scheduling module respectively:

[0162] The adaptive perception module includes a kinship perception module and a resource bottleneck perception module.

[0163] Among them, the affinity perception module is used to perceive the affinity between threads, identify multiple threads accessing the same block of memory through the memory access behavior of the threads, and determine the affinity threads; threads with the same affinity are assigned to the same thread affinity group, and the memory access information of the threads and groups is recorded.

[0164] The resource bottleneck perception module is used to detect resource bottlenecks on NUMA nodes by identifying computing power bottlenecks, memory bottlenecks, and input / output (IO) bottlenecks. For example, if the resource metric value of a NUMA node is less than the resource threshold, the server determines that the NUMA node has a resource bottleneck. If the resource metric value of a NUMA node is greater than or equal to the resource threshold, the server determines that the NUMA node does not have a resource bottleneck. For another example, if the resource metric value of a NUMA node is less than or equal to the resource threshold, the server determines that the NUMA node has a resource bottleneck. If the resource metric value of a NUMA node is greater than the resource threshold, the server determines that the NUMA node does not have a resource bottleneck.

[0165] The scheduling module is used to optimize the current core selection and load balancing logic, breaking the original load balancing model. In the thread scheduling process, a NUMA node is selected based on the memory access information of the thread group. NUMA nodes are selected in descending order of memory access frequency. When a NUMA node is selected, it is determined whether there is a bottleneck in the resources of this NUMA node.

[0166] If the NUMA node has no bottleneck, the NUMA node is selected and the optimal CPU is selected within the NUMA node according to the system's native core selection process. For example, the system's native core selection process includes selecting the optimal CPU within the NUMA node when there is no NUMA node resource bottleneck.

[0167] If a resource bottleneck exists on this NUMA node, the next NUMA node is selected. If no suitable NUMA node exists, core selection is performed according to the system's native logic. For example, one system-native logic might be fork core selection, which is performed when a thread is first generated. This core selection logic traverses the system's CPUs and selects an idle CPU. Another system-native logic is wake-up core selection. When a thread wakes up, it determines the lightest CPU based on the thread's previous running CPU and the current CPU where the thread is waking up. It then selects an idle CPU based on this lightest CPU.

[0168] Specifically, the scheduling module may include four submodules, which respectively implement fork balance strategy, wakeup balance strategy, load balance strategy, and NUMA balance strategy.

[0169] Among them, four sub-modules are used to implement the core selection process of the scheduling module, specifically:

[0170] Fork balance refers to the implementation of core selection when a task is created. At this time, the CPUs of the entire system will be traversed and the CPU with the lightest load will be selected based on load information.

[0171] Wakeup balance refers to the core selection when a task is newly awakened. Based on the CPU where the thread previously ran and the CPU where the current awakening thread is located, the lightest loaded CPU is determined, and then an idle CPU is selected with this lightest loaded CPU as the center.

[0172] Load balance means that the system periodically determines whether there is a load imbalance in the system. If there is a load imbalance, tasks on the heavily loaded CPU are migrated to the lightly loaded CPU.

[0173] NUMA balance means that the system periodically determines whether there is an imbalance between NUMAs in the system. If there is an imbalance between NUMAs, memory migration or task migration is performed.

[0174] Figure 10 is a schematic diagram of the software and hardware structure of the server provided by an embodiment of the present application. Next, the implementation of the embodiment of the present application in platform software and server hardware will be described. The product implementation of the embodiment of the present application is program code contained in the operating system kernel and deployed on the server hardware. Taking the application scenario shown in Figure 10 as an example, the program code of the embodiment of the present application is contained in the scheduling system of the kernel module, wherein the server hardware structure includes a scheduler, an affinity perception module, and a resource bottleneck perception module.

[0175] The method implemented in the embodiment of the present application includes the following steps:

[0176] S01. In the program execution context, track the memory access of the thread by sampling the performance management unit (PMU) data.

[0177] This step is executed in the thread running context. When the CPU switches to this thread and starts running, the PMU data is read once. When this thread runs, the PMU data is read again. The difference between the two PMU data is used to obtain the memory access information during this thread running phase.

[0178] S02. Merge threads accessing the same memory address into a thread affinity group.

[0179] This step is triggered periodically or immediately after S01 is executed. According to S01, memory access information of the thread running phase is obtained, and multiple threads accessing the same block address are merged into the same group.

[0180] S03. Record the interaction frequency between threads in the same group to determine affinity.

[0181] For example, kinship includes: strong or weak kinship.

[0182] S03 can be triggered periodically or immediately after S02 is completed, and is executed after S02 is completed. Based on the information of S01 and S02, the interaction frequency between multiple threads in the same group is recorded to determine the strength of the affinity.

[0183] S04. Determine whether there is a resource bottleneck on the NUMA node.

[0184] S04 can be executed periodically or during core selection or load balancing. It obtains load information on a NUMA node or interference information between tasks on a NUMA node to determine whether a resource bottleneck exists on the NUMA node. The level of interference between two threads can be determined by measuring the waiting time caused by running them on the same CPU.

[0185] S05. Optimize the core selection and load balancing process to aggregate threads with affinity onto one NUMA node.

[0186] This step is critical for task core selection and load balancing. During core selection, a node is prioritized based on the task group's memory access information. A check is performed to determine whether this node has a resource bottleneck. If no resource bottleneck exists, this node is selected. If so, the next node with the highest memory access frequency is selected. During system load balancing, when tasks need to be migrated across NUMA nodes, if the current node has the most memory access, a check is performed to determine whether this node has a resource bottleneck. If not, threads do not need to be migrated. Only threads with low memory access frequency need to be migrated if this node has a resource bottleneck.

[0187] From the above examples, it can be seen that in the embodiment of the present application, lightweight PMU sampling is used during thread switching context to accurately obtain memory access information, identify the interaction frequency between threads, and thereby identify the affinity between multiple threads, which has the advantages of high recognition accuracy and low overhead.

[0188] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0189] In order to better implement the above-mentioned solutions of the embodiments of the present application, relevant devices for implementing the above-mentioned solutions are also provided below.

[0190] As shown in FIG11 , a server 1100 provided in an embodiment of the present application may include: a relationship determination module 1101, a node determination module 1102, a resource measurement module 1103, and a selection module 1104, wherein:

[0191] An affinity determination module, configured to determine affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running phase and second memory access information of the second thread in the second running phase;

[0192] a node determination module, configured to determine a first node according to the first memory access information, the second memory access information, and the kinship information;

[0193] a resource measurement module, configured to determine that a resource measurement value of the first node is less than a resource threshold;

[0194] A selection module is configured to select a processor unit for running the first thread and the second thread according to the first node.

[0195] It should be noted that the information interaction, execution process, etc. between the modules / units of the above-mentioned device are based on the same concept as the method embodiment of the present application, and the technical effects they bring are the same as those of the method embodiment of the present application. For specific contents, please refer to the description in the method embodiment shown above in the present application, and no further details will be given here.

[0196] An embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores a program, and the program executes some or all of the steps recorded in the above method embodiment.

[0197] Next, another computer system provided by an embodiment of the present application is introduced. Referring to FIG. 12 , the computer system 1200 includes:

[0198] Receiver 1201, transmitter 1202, processor 1203, and memory 1204 (wherein the number of processors 1203 in computer system 1200 may be one or more, and FIG12 uses one processor as an example). In some embodiments of the present application, receiver 1201, transmitter 1202, processor 1203, and memory 1204 may be connected via a bus or other means, wherein FIG12 uses the bus connection as an example.

[0199] Memory 1204 may include read-only memory and random access memory, and provides instructions and data to processor 1203. A portion of memory 1204 may also include non-volatile random access memory (NVRAM). Memory 1204 stores an operating system and operating instructions, executable modules, or data structures, or subsets or extensions thereof. The operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks.

[0200] Processor 1203 controls the operation of the computer system and may also be referred to as a central processing unit (CPU). In specific applications, the various components of the computer system are coupled together via a bus system. In addition to a data bus, the bus system may also include a power bus, a control bus, and a status signal bus. However, for clarity, all bus systems are referred to as a bus system in the figure.

[0201] The methods disclosed in the above embodiments of the present application can be applied to or implemented by processor 1203. Processor 1203 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits or software instructions in processor 1203. The above processor 1203 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can be located in storage media well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory 1204 , and the processor 1203 reads the information in the memory 1204 and completes the steps of the above method in combination with its hardware.

[0202] The receiver 1201 can be used to receive input digital or character information, and generate signal input related to the relevant settings and function control of the computer system. The transmitter 1202 may include a display device such as a display screen, and the transmitter 1202 can be used to output digital or character information through an external interface.

[0203] In the embodiment of the present application, the processor 1203 is used to execute the multi-thread scheduling method shown in FIG. 2 .

[0204] In another possible design, when the computer system is a chip, the chip includes: a processing unit and a communication unit, wherein the processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin, or a circuit, etc. The processing unit may execute the computer execution instructions stored in the storage unit so that the chip executes any one of the methods of the first aspect above. Optionally, the storage unit is a storage unit within the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit located outside the chip, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0205] The processor mentioned in any of the above places can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the above-mentioned first aspect method.

[0206] It should also be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0207] Through the description of the above embodiments, it is clear to those skilled in the art that the present application can be implemented by means of software plus necessary general-purpose hardware, and of course it can also be implemented by means of dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be various, such as analog circuits, digital circuits, or dedicated circuits, etc. However, for the present application, software program implementation is a better implementation method in most cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0208] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0209] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, a server, or a data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, a computer, a server, or a data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium can be a magnetic medium, (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state drive (SSD)).

Claims

1. A multi-threaded scheduling method, characterized in that: include: Determine affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage; Determine a first node according to the first memory access information, the second memory access information and the affinity information; Determining that the resource metric value of the first node is less than a resource threshold; A processor element for executing the first thread and the second thread is selected according to the first node.

2. The method according to claim 1, characterized in that The method further comprises: In the first running phase in the thread switching context, state information of a performance management unit is collected, and the first memory access information is determined according to the state information of the performance management unit.

3. The method according to claim 2, characterized in that The collecting the status information of the performance management unit in the first operation stage, and determining the first memory access information according to the status information of the performance management unit, includes: Reading first status information from a register of the performance management unit at the start of the first operation phase; Reading second status information from the register at the end of the first operation phase; The first memory access information is determined according to the first state information and the second state information.

4. The method according to claim 1, characterized in that: The first memory access information includes: address information accessed by the first thread; the second memory access information includes: address information accessed by the second thread; The determining of affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage comprises: Determine, according to the address information accessed by the first thread and the address information accessed by the second thread, a memory address range that is the same as the memory address range accessed by the first thread and the second thread; Acquire the interaction frequency between the first thread and the second thread according to the memory address range; Affinity information between the first thread and the second thread is determined according to the interaction frequency.

5. The method according to claim 4, characterized in that The acquiring the interaction frequency between the first thread and the second thread according to the memory address range includes: merging the first thread and the second thread into a thread affinity group according to the memory address range; Obtain an interaction frequency between the first thread in the thread affinity group when it is running in the first running stage and the second thread in the second running stage, wherein the first running stage and the second running stage overlap in time.

6. The method according to any one of claims 1 to 5, characterized in that The method further includes: acquiring resource occupancy information of the first node in a first time unit, and determining a resource load metric of the first node according to the resource occupancy information; and / or acquiring resource waiting information of the first node in a second time unit, and determining a resource interference metric of the first node according to the resource waiting information; The determining that the resource metric value of the first node is less than a resource threshold includes: It is determined that the resource metric value of the first node is less than a resource threshold value according to the resource load metric of the first node and / or the resource interference metric of the first node.

7. The method according to any one of claims 1 to 5, characterized in that The determining that the resource metric value of the first node is less than a resource threshold includes: Obtaining a processor unit metric value, and / or a memory metric value, and / or an input / output metric value of the first node; Determine that the processor unit metric value of the first node is less than a computing power threshold, and / or determine that the memory metric value of the first node is less than a memory threshold, and / or determine that the output-input metric value of the first node is less than an input-output threshold.

8. The method according to any one of claims 1 to 7, characterized in that The determining the first node according to the first memory access information, the second memory access information and the affinity information includes: A node with the most frequent memory access frequency is selected from a task group as the first node according to the first memory access information, the second memory access information and the affinity information.

9. The method according to any one of claims 1 to 8, characterized in that After selecting a processor unit for running the first thread and the second thread from the first node, the method further includes: Determining a thread with a lower memory access frequency from the first thread and the second thread according to the memory access frequency of the first thread and the memory access frequency of the second thread; In response to the resource metric value of the first node being less than a resource threshold, it is determined not to migrate the thread with a low memory access frequency.

10. The method according to claim 9, characterized in that The method further comprises: In response to the resource metric value of the first node being greater than or equal to a resource threshold, the thread with low memory access frequency is migrated from the first node to a second node, where the second node is a remote node of the first node.

11. The method according to any one of claims 1 to 10, characterized in that The determining that the resource metric value of the first node is less than a resource threshold includes: According to the resource information of the first node, periodically determine whether the resource metric value of the first node is less than a resource threshold; or, In response to an instruction of a scheduling processor unit or a load balancing instruction, it is determined that the resource metric value of the first node is less than a resource threshold.

12. A server, characterized in that: include: An affinity determination module, configured to determine affinity information between the first thread and the second thread according to first memory access information of the first thread in the first running stage and second memory access information of the second thread in the second running stage; a node determination module, configured to determine a first node according to the first memory access information, the second memory access information and the affinity information; A resource measurement module, configured to determine that a resource measurement value of the first node is less than a resource threshold; A selection module is used to select a processor unit for running the first thread and the second thread according to the first node.

13. A computer system, characterized in that: The computer system comprises: a processor and a memory; the processor and the memory communicate with each other; The memory is used to store instructions; The processor is configured to execute the instructions in the memory to perform the method according to any one of claims 1 to 11.

14. A computer-readable storage medium comprising instructions, which, when executed on a computer, causes the computer to execute the method according to any one of claims 1 to 11.

15. A computer program product comprising instructions, which, when executed on a computer, causes the computer to perform the method according to any one of claims 1 to 11.

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