Back-contact battery and manufacturing method therefor

Abstract

A back-contact battery and a manufacturing method therefor, which relate to the technical field of photovoltaics, and are used for reducing the number of defects on a second surface side and improving the photoelectric conversion efficiency of the back-contact battery. The back-contact battery comprises: a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer and a second doped semiconductor layer. The first doped semiconductor layer comprises a first doped part and a second doped part, wherein the first doped part is located on a first region, and the second doped part is located on an isolation region; and the doping concentration of impurities in the second doped part is lower than that of impurities in the first doped part. The intrinsic semiconductor layer is formed on the part of the isolation region outside the second doped part in a direction parallel to a second surface. The second doped semiconductor layer covers a second region, the electrical conduction type of the second doped semiconductor layer is opposite to the electrical conduction type of the first doped semiconductor layer, and the intrinsic semiconductor layer is used for electrically isolating the first doped semiconductor layer from the second doped semiconductor layer.

Description

Back contact battery and manufacturing method thereof Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back-contact cell and a manufacturing method thereof. Background Art

[0002] Back-contact cells are solar cells with both the positive and negative electrodes on the back of the cell, with no metal electrodes blocking the front. Compared to solar cells with obstructed front surfaces, back-contact cells offer higher short-circuit current and photoelectric conversion efficiency, and are currently one of the technological advancements in achieving high-efficiency crystalline silicon cells.

[0003] However, the existing back-contact cells have a large number of defects located on the backlight side, resulting in a decrease in the photoelectric conversion efficiency of the back-contact cells.

[0004] Summary of the Invention

[0005] The object of the present invention is to provide a back-contact cell and a method for manufacturing the same, which are used to reduce the number of defects on the backlight side of the back-contact cell and improve the photoelectric conversion efficiency of the back-contact cell.

[0006] In order to achieve the above objectives, in a first aspect, the present invention provides a back-contact battery, which includes a semiconductor substrate, a first doped semiconductor layer, an intrinsic semiconductor layer, and a second doped semiconductor layer. The semiconductor substrate has a first and a second opposite surface; the second surface has first and second regions alternately spaced, and an isolation region between each first region and the second region adjacent to it. The first doped semiconductor layer includes a first doped portion and a second doped portion, the first doped portion is located on the first region, and the second doped portion is located in the isolation region; the doping concentration of impurities in the second doped portion is lower than the doping concentration of impurities in the first doped portion. The intrinsic semiconductor layer is formed on a portion of the isolation region outside the second doped portion in a direction parallel to the second surface. The second doped semiconductor layer covers the second region, and the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer. The intrinsic semiconductor layer is used to electrically isolate the first doped semiconductor layer from the second doped semiconductor layer.

[0007] When the above technical solution is adopted, the first doped semiconductor layer and the second doped semiconductor layer are both formed on one side of the second surface of the semiconductor substrate, and the conductivity types of the two are opposite. Based on this, when the back contact battery is in an operating state, the electrons and holes generated by the semiconductor substrate after absorbing photons move toward the first doped semiconductor layer and the second doped semiconductor layer respectively, and are collected and discharged by the two layers respectively to form a photocurrent. Among them, because the intrinsic semiconductor layer is non-conductive, the presence of the intrinsic semiconductor layer can electrically isolate the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, thereby suppressing leakage. In addition, in the actual manufacturing process, due to the accuracy of the machine and / or for the purpose of preventing leakage, the width of the isolation region between the first region and the adjacent second region is made larger. Based on this, the first doped semiconductor layer includes not only a first doped portion located on the first region, but also a second doped portion located on the partially isolated region. When the back-contact cell is in operation, the first doped semiconductor layer can promptly collect and conduct electrons or holes corresponding to the first region, as well as electrons or holes corresponding to the partially isolated region. Thus, while preventing lateral leakage between the first and second doped semiconductor layers through the intrinsic semiconductor layer, the carrier recombination rate in the wider isolation region can be reduced, further improving the photoelectric conversion efficiency of the back-contact cell. Furthermore, because the second doped portion is located between the first doped portion and the intrinsic semiconductor layer, when the impurity concentration within the second doped portion located on the partially isolated region is lower than the impurity concentration within the first doped portion located on the first region, the conductivity of the second doped portion can be reduced, reducing the risk of electric shock from penetrating the intrinsic semiconductor layer. Furthermore, the diffusion of impurities within the second doped portion into the intrinsic semiconductor layer can be suppressed or even eliminated, ensuring good electrical isolation of the intrinsic semiconductor layer and good electrical performance of the back-contact cell.

[0008] As a possible implementation, the second doped semiconductor layer covers a portion of the intrinsic semiconductor layer and / or a portion of the second doped portion. In this case, along the thickness direction of the semiconductor substrate, the second doped semiconductor layer is not only formed on the second region of the second surface of the semiconductor substrate, but also covers at least a portion of the intrinsic semiconductor layer and / or a portion of the second doped portion. Similarly, electrical isolation is provided by the intrinsic semiconductor layer or the second doped portion to suppress leakage.

[0009] As a possible implementation, at least one of the first doped semiconductor layer and the second doped semiconductor layer is a doped crystalline silicon layer. In this case, compared to doped amorphous silicon layers, doped crystalline silicon layers have better lateral carrier transport properties, can further reduce the carrier recombination rate, and thus improve the photoelectric conversion efficiency of the back-contact cell.

[0010] As a possible implementation solution, the above-mentioned back-contact battery further includes an insulating mask layer, and the insulating mask layer is located on the second doped portion and the intrinsic semiconductor layer.

[0011] When adopting the above technical solution, since the insulating mask layer is non-conductive, the presence of the insulating mask layer can further electrically isolate the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, thereby preventing leakage between the two along the thickness direction of the semiconductor substrate.

[0012] As a possible implementation solution, the above-mentioned back-contact battery further includes an insulating mask layer, and the insulating mask layer is at least partially located between the second doped semiconductor layer and the intrinsic semiconductor layer.

[0013] As a possible implementation scheme, along the direction in which the first and second regions are arranged and extended, the sidewall of the insulating mask layer near the second region is flush with or recessed inward relative to the sidewall of the intrinsic semiconductor layer near the second region. In this case, in the back-contact cell provided by the present invention, not only is there no small gap between the portion of the insulating mask layer near the second region and the semiconductor substrate, but the portion of the insulating mask layer near the second region and the portion of the intrinsic semiconductor layer near the second region form a step-like structure, which facilitates better coverage of the second doped semiconductor layer by the edge of the intrinsic semiconductor layer and prevents unfilled gaps on the side of the second surface after the second doped semiconductor layer is formed. This reduces the number of defects on the back-light side of the back-contact cell, reduces the carrier recombination rate, and improves the photoelectric conversion efficiency of the back-contact cell.

[0014] As a possible implementation, along the arrangement direction of the first region and the second region, the distance by which the sidewall of the insulating mask layer close to the second region is recessed relative to the sidewall of the intrinsic semiconductor layer close to the second region is greater than or equal to 0 and less than or equal to 50 μm.

[0015] When the above technical solution is adopted, in the actual manufacturing process, it is necessary to selectively dope the portion of the intrinsic semiconductor material layer corresponding to the first region disposed on one side of the second surface to form a first doped semiconductor layer and an intrinsic semiconductor layer. Furthermore, after the first doped semiconductor layer and the intrinsic semiconductor layer are formed, the portion of the intrinsic semiconductor material layer corresponding to the second region can be removed under the masking action of the insulating mask layer. Then, the insulating mask layer is etched so that the sidewall of the insulating mask layer adjacent to the second region is flush with or recessed inward relative to the sidewall of the intrinsic semiconductor layer adjacent to the second region. It can be seen that when the insulating mask layer is etched, the entire surface of the insulating mask layer, except for the side in contact with the intrinsic semiconductor layer, is exposed. Therefore, the etchant can not only make the sidewall of the insulating mask layer adjacent to the second region flush with or recessed inward relative to the sidewall of the intrinsic semiconductor layer adjacent to the second region, but also reduce the thickness of the insulating mask layer, which affects its own insulation properties. Based on this, along the arrangement direction of the first and second regions, the distance by which the sidewall of the insulating mask layer near the second region is flush with or recessed inward relative to the sidewall of the intrinsic semiconductor layer near the second region is within the aforementioned range. This prevents the etching process from taking a longer time due to this larger distance, resulting in a smaller remaining thickness of the insulating mask layer after the etching process and thus poor insulation properties. This ensures that the first and second doped semiconductor layers can be electrically isolated by the insulating mask layer along the thickness direction of the semiconductor substrate. Furthermore, this distance within the aforementioned range also prevents the use of larger consumables when forming the insulating mask layer in order to obtain a larger remaining thickness of the insulating mask layer when the distance is larger, thereby helping to control the manufacturing cost of the back-contact battery.

[0016] As a possible implementation, the insulating mask layer comprises at least one of silicon nitride, silicon oxide, and intrinsic silicon. In this case, the insulating mask layer exhibits excellent corrosion resistance, protecting the first doped semiconductor layer and the intrinsic semiconductor layer from, or minimizing, etching effects when removing the portion of the intrinsic semiconductor material layer corresponding to the second region, thereby improving the yield of back-contact cells. Furthermore, silicon nitride, silicon oxide, and intrinsic silicon have high dielectric constants, giving the insulating mask layer excellent insulation properties, ensuring that the insulating mask layer electrically isolates the first doped semiconductor layer from the second doped semiconductor layer along the thickness of the semiconductor substrate.

[0017] As a possible implementation solution, the thickness of the insulating mask layer is greater than or equal to 40 nm and less than or equal to 80 nm.

[0018] When the above technical solution is adopted, the thickness of the insulating mask layer is within the above range, which can prevent the insulating mask layer from having poor insulation properties due to its small thickness, ensuring that the first doped semiconductor layer and the second doped semiconductor layer can be electrically isolated by the insulating mask layer along the thickness direction of the semiconductor substrate. It can also prevent the insulating mask layer from having a weak protective effect on the first doped semiconductor layer and the intrinsic semiconductor layer located below it when selectively etching the portion of the intrinsic semiconductor material layer corresponding to the second region, thereby ensuring a high yield of the back-contact battery. Furthermore, it can also prevent the use of large consumables when forming the insulating mask layer due to its large thickness, thereby helping to control the manufacturing cost of the back-contact battery.

[0019] As a possible implementation solution, along the arrangement and extension direction of the first region and the second region, a sidewall of the intrinsic semiconductor layer close to the second region is flush with or recessed inward relative to a boundary between the second region and the isolation region.

[0020] When the above technical solution is adopted, in the actual manufacturing process, after the portion of the intrinsic semiconductor material layer corresponding to the second region, which is disposed on the side of the second surface and used to form the first doped semiconductor layer and the intrinsic semiconductor layer, is selectively etched, the surface of the semiconductor substrate corresponding to the second region will generally be recessed into the semiconductor substrate relative to the surface of the isolation region. Based on this, when the sidewall of the intrinsic semiconductor layer near the second region is flush with or recessed inward relative to the boundary between the second region and the isolation region, the intrinsic semiconductor layer and the surface of the second region, as well as the surface of the second region and the surface of the isolation region, can form a step-like structure. That is, along the direction from the second region to the first region, the surface height of the corresponding structure covered by the second doped semiconductor layer has a transition, which facilitates the second doped semiconductor layer to better cover the edge of the intrinsic semiconductor layer and improve the yield of the back-contact cell. At the same time, it also helps to further prevent the existence of unfilled gaps on the side of the second surface after the second doped semiconductor layer is formed, thereby reducing the number of defects on the back-light side of the back-contact cell, reducing the carrier recombination rate, and improving the photoelectric conversion efficiency of the back-contact cell.

[0021] As a possible implementation, along the arrangement direction of the first and second regions, the sidewall of the intrinsic semiconductor layer adjacent to the second region is recessed inward by a distance greater than or equal to 0 and less than or equal to 5 μm relative to the boundary between the second region and the isolation region. In this case, this larger distance can prevent the intrinsic semiconductor layer from having a smaller width and thus deteriorating its electrical insulation properties, thereby ensuring that the first doped semiconductor layer and the second doped semiconductor layer can be electrically isolated by the intrinsic semiconductor layer.

[0022] As a possible implementation solution, along the direction from the second doping portion to the intrinsic semiconductor layer, a ratio of the width of the second doping portion to the width of the isolation region is greater than or equal to 0.8 and less than 1.

[0023] When employing the above technical solution, when the ratio of the width of the second doped portion to the width of the isolation region along the direction from the second doped portion to the intrinsic semiconductor layer is within the above range, the width of the second doped portion is greater than the width of the intrinsic semiconductor layer. This prevents the second doped portion from significantly reducing the carrier recombination rate in the isolation region due to its smaller width, thereby ensuring that the back-contact cell has a high photoelectric conversion efficiency. Furthermore, because the second doped portion and the intrinsic semiconductor layer are co-located on the isolation region, when the width of the isolation region is constant, the width of the second doped portion is inversely proportional to the width of the intrinsic semiconductor layer. Furthermore, within a certain range, the electrical isolation effect of the intrinsic semiconductor layer in a direction parallel to the second surface is proportional to its own width. Based on this, when the ratio is within the above range, it can also prevent the electrical isolation effect of the intrinsic semiconductor layer from being poor due to the smaller width of the second doped portion, ensuring that leakage between the first and second doped semiconductor layers in a direction parallel to the second surface can be prevented through the intrinsic semiconductor layer.

[0024] As a possible implementation solution, along the direction from the second doping portion to the intrinsic semiconductor layer, the width of the intrinsic semiconductor layer is greater than or equal to 6 μm and less than or equal to 120 μm.

[0025] When employing the above technical solution, the width of the intrinsic semiconductor layer is within the above range, thereby preventing the intrinsic semiconductor layer's smaller width from affecting its electrical isolation along the second direction, thereby ensuring that the intrinsic semiconductor layer can prevent leakage between the first and second doped semiconductor layers along the second surface. Furthermore, the reduced width of the second doped portion due to the larger width of the intrinsic semiconductor layer can be prevented, further enhancing the degree to which the second doped portion reduces the carrier recombination rate in the isolation region.

[0026] As a possible implementation solution, along the direction from the second doping portion to the intrinsic semiconductor layer, the width of the isolation region is greater than or equal to 30 μm and less than or equal to 200 μm.

[0027] When the above technical solution is adopted, the width of the isolation region is within the above range, which can prevent the difficulty of providing a second doped portion and an intrinsic semiconductor layer of a reasonable width within the smaller width range due to the smaller width of the isolation region, thereby ensuring that the second doped portion and the intrinsic semiconductor layer have the functions described above. In addition, it can also prevent the first region and / or second region located on the side of the second surface from being smaller due to the larger width of the intrinsic semiconductor layer, thereby preventing the first doped semiconductor layer and / or the second doped semiconductor layer from also being smaller in width. This ensures that the first doped semiconductor layer and the second doped semiconductor layer can promptly collect and guide carriers corresponding to the first region and the second region, further reducing the carrier recombination rate on the side of the second surface.

[0028] As a possible implementation solution, the doping concentration of the impurities in the second doping portion is greater than or equal to 1E18 cm -3 , and less than or equal to 5E20cm -3 .

[0029] When using the above technical solution, the impurity concentration within the second doped portion is within the above range. This prevents the second doped portion from having a poor carrier collection capability due to a low impurity concentration, further improving the degree to which the second doped portion reduces the carrier recombination rate in the isolation region. Furthermore, it prevents carriers from easily diffusing into the intrinsic semiconductor layer due to a high impurity concentration within the second doped portion, thereby ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0030] As a possible implementation, the impurity concentration in the first doped portion is 10 to 100 times the impurity concentration in the second doped portion. In this case, the higher impurity concentration in the first doped portion can provide the first doped portion with a higher carrier collection capability. Furthermore, the manufacturing difficulty of obtaining a first doped portion with an excessively high doping concentration can be reduced.

[0031] As a possible implementation, the doping concentration of impurities in the second doped portion gradually decreases along the direction from the second doped portion to the intrinsic semiconductor layer. In this case, while ensuring that the impurities in the second doped portion have a certain doping concentration, thereby enabling the second doped portion to have a certain carrier lateral collection capability, the portion of the second doped portion with the lowest impurity doping concentration can also be brought into contact with the intrinsic semiconductor layer, reducing the carrier concentration gradient at the contact point between the two, further suppressing or even eliminating the diffusion of impurities in the second doped portion into the intrinsic semiconductor layer, and ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0032] As a possible implementation, the back-contact cell further includes a transparent conductive layer that covers at least the first doped semiconductor layer and the second doped semiconductor layer. An insulating trench is provided through the portion of the transparent conductive layer corresponding to the isolation region to electrically isolate the portion of the transparent conductive layer located on the first doped semiconductor layer from the portion located on the second doped semiconductor layer.

[0033] When employing the above-described technical solution, the transparent conductive layer exhibits excellent electrical transmission characteristics. Therefore, when the back-contact cell further includes a transparent conductive layer covering at least the first doped semiconductor layer and the second doped semiconductor layer, carriers can be promptly collected and discharged, reducing the carrier recombination rate on the second surface. Furthermore, because the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types, an insulating trench is provided through the portion of the transparent conductive layer corresponding to the isolation region to electrically isolate the portion of the transparent conductive layer located above the first doped semiconductor layer from the portion located above the second doped semiconductor layer, thereby ensuring high electrical reliability for the back-contact cell.

[0034] As a possible implementation, when the insulating trench is located above the second doped portion, the sidewall of the insulating mask layer close to the second region is located between the sidewall of the intrinsic semiconductor layer close to the second region and the sidewall of the insulating trench close to the second region.

[0035] When employing the above technical solution, when the insulation trench is located above the second doped portion, the portion of the transparent conductive layer located on one side of the insulation trench covers the first doped portion and a portion of the second doped portion, while the portion of the transparent conductive layer located on the other side of the insulation trench may cover a portion of the second doped portion and the second doped semiconductor layer. Furthermore, the sidewall of the second doped semiconductor layer near the first region is substantially flush with the sidewall of the insulation mask layer near the first region. Based on this, if the sidewall of the insulation mask layer near the second region is located between the sidewall of the intrinsic semiconductor layer near the second region and the sidewall of the insulation trench near the second region, this indicates that the sidewall of the insulation mask layer near the second region extends inward beyond the insulation trench after etching. In this case, the portions of the transparent conductive layer located on either side of the insulation trench cannot be electrically coupled through the insulation mask layer, preventing short circuits and ensuring high electrical reliability of the back-contact battery.

[0036] As a possible implementation solution, the first doped semiconductor layer is a doped crystalline silicon layer.

[0037] When using the above technical solution, doped crystalline silicon layers have higher lateral carrier transport properties than doped amorphous silicon layers. Therefore, when the first doped semiconductor layer is a doped crystalline silicon layer, the second doped portion has excellent lateral carrier transport properties, which facilitates the second doped portion to laterally transfer more electrons or holes collected by the second doped portion to the first doped portion, and then conduct them through the exposed first doped portion, further reducing the carrier recombination efficiency in the isolation region. At the same time, the first doped portion can also have higher carrier collection properties, reducing the carrier recombination efficiency in the first region.

[0038] As a possible implementation scheme, the first surface of the semiconductor substrate and the surface of the second region of the semiconductor substrate are both velvet. In this case, the refractive index of light transmitted from the first surface and the surface of the second region to the semiconductor substrate can be increased, further improving the photoelectric conversion efficiency of the back contact battery. In addition, when the surface of the second region is velvet, the backlight side of the second doped semiconductor layer formed on the second region also has corresponding undulating features. Compared with a plane, the specific surface area of ​​a surface with undulating features is larger. Therefore, when the backlight side of the second doped semiconductor layer on the second region has undulating features, it is beneficial to increase the contact area between the second doped semiconductor layer and the electrode, reduce the contact resistance between the two, and further improve the electrical performance of the back contact battery.

[0039] As a possible implementation, the intrinsic semiconductor layer and the first doped semiconductor layer are integrally formed. In this case, the intrinsic semiconductor layer can be prevented from covering the portion of the first doped semiconductor layer near the isolation region due to the additional deposition and etching processes after the first doped semiconductor layer is formed, thereby ensuring that the first doped semiconductor layer has a larger process window.

[0040] As a possible implementation solution, the above-mentioned back-contact battery further includes a first passivation layer, and the first passivation layer is located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer.

[0041] When adopting the above technical solution, the selective contact structure composed of the first passivation layer and the first doped semiconductor layer has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate in the first area and partial isolation area of ​​the backlight surface of the semiconductor substrate, and further improve the photoelectric conversion efficiency of the back contact battery.

[0042] As a possible implementation solution, the above-mentioned back-contact battery further includes a second passivation layer, and the second passivation layer is located between the second doped semiconductor layer and the semiconductor substrate, the intrinsic semiconductor layer and the second doped portion.

[0043] When using the above technical solution, the selective contact structure formed by the second passivation layer and the second doped semiconductor layer can achieve selective collection of carriers, reducing the carrier recombination rate in the second region of the backlight surface of the semiconductor substrate. Furthermore, the second passivation layer and the intrinsic semiconductor layer are located between the portion of the second doped semiconductor layer located on the second region and the second doped portion. In this case, both can suppress the carrier recombination rate at the interface between the second doped semiconductor layer and the first doped semiconductor layer corresponding to the isolation region, further improving the photoelectric conversion efficiency of the back-contact cell.

[0044] As a possible implementation solution, when the back contact cell further includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the material of the first doped semiconductor layer is doped polysilicon, and the conductivity type is N-type.

[0045] When the above technical solution is adopted, if the back-contact cell also includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure. In this case, the material of the first doped semiconductor layer is doped polycrystalline silicon. Based on this, because the contact resistance between the P-type doped polycrystalline silicon layer and the electrode is high and the field passivation effect is poor, when the first passivation layer included in the back-contact cell is a tunneling passivation layer and the first doped semiconductor layer is a doped polycrystalline silicon layer, when the conductivity type of the first doped semiconductor layer is N-type, the field passivation effect of the first doped semiconductor layer can be further improved, while the contact resistance between the first doped portion and the electrode can be reduced, which is beneficial to improving the electrical performance of the back-contact cell. In addition, the first doped semiconductor layer can be formed before the second doped semiconductor layer. Moreover, compared with amorphous silicon, polycrystalline silicon has better heat resistance. Based on this, when the back-contact cell also includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, and the material of the first doped semiconductor layer is doped polysilicon, if a laser etching process is used to remove at least the portion of the material layer corresponding to the first region used to manufacture the second doped semiconductor layer, the first doped semiconductor material, which is doped polysilicon, is less affected by the high-temperature laser or even unaffected by the high-temperature laser, which is beneficial to improving the yield of the back-contact cell. Furthermore, in the actual manufacturing process, the manufacturing cost of the heterocontact structure is higher than that of the tunneling passivation contact structure. In addition, the tunneling passivation contact structure can be implemented using a variety of processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition, making it more compatible with the back-contact cell process, while the heterocontact structure requires the use of plate-type plasma chemical vapor deposition equipment that supports lower formation temperatures. Based on this, when the first passivation layer of the back-contact cell is a tunneling passivation layer and the material of the first doped semiconductor layer is doped polysilicon, it is beneficial to reduce manufacturing costs, reduce investment in plate-type plasma chemical vapor deposition equipment, and save production site area.

[0046] As a possible implementation solution, the first passivation layer is a tunneling silicon dioxide layer.

[0047] As a possible implementation scheme, when the back contact battery also includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P type.

[0048] In the case of adopting the above technical solution, when the back-contact battery further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a heterogeneous contact structure. In this case, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon. Based on this, compared with the P-type doped amorphous silicon and / or doped microcrystalline silicon layer, the P-type doped polycrystalline silicon layer has a higher contact resistance with the electrode and a poorer field passivation effect. Therefore, in the above case, the conductivity type of the second doped semiconductor layer is set to P-type, rather than the conductivity type of the tunnel passivation contact structure being set to P-type. This can further improve the field passivation effect of the first doped semiconductor layer, while reducing the contact resistance between the first doped portion and the electrode, which is beneficial to improving the electrical performance of the back-contact battery.

[0049] In a second aspect, the present invention provides a method for manufacturing a back-contact battery, comprising: first, providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface facing each other; the second surface has first and second regions alternately spaced, and an isolation region between each first region and its adjacent second region. Next, forming a full-layer intrinsic semiconductor material layer on the second surface. Next, selectively doping the portion of the intrinsic semiconductor material layer located on the first region so that the portions of the intrinsic semiconductor material layer located on the first region and the isolation region form a first doped semiconductor layer and an intrinsic semiconductor layer; the first doped semiconductor layer includes a first doped portion and a second doped portion, the first doped portion being located on the first region and the second doped portion being located in the isolation region; the doping concentration of impurities in the second doped portion being lower than the doping concentration of impurities in the first doped portion; and forming the intrinsic semiconductor layer in a direction parallel to the second surface on the portion of the isolation region excluding the second doped portion. Next, forming a second doped semiconductor layer at least on the second region. The second doped semiconductor layer has an opposite conductivity type to the first doped semiconductor layer, and the intrinsic semiconductor layer serves to electrically isolate the first doped semiconductor layer from the second doped semiconductor layer.

[0050] As a possible implementation scheme, the above-mentioned selective removal of the portion of the intrinsic semiconductor material layer remaining on the second region includes: forming an insulating mask layer covering the first region and the isolation region; then, under the masking action of the insulating mask layer, removing the portion of the intrinsic semiconductor material layer remaining on the second region.

[0051] As a possible implementation scheme, after removing the remaining portion of the intrinsic semiconductor material layer on the second region under the masking action of the insulating mask layer, and before forming the second doped semiconductor layer at least on the second region, the manufacturing method of the back contact battery also includes: etching the insulating mask layer so that the side wall of the insulating mask layer close to the second region is flush with or concave inward relative to the side wall of the intrinsic semiconductor layer close to the second region.

[0052] As a possible implementation solution, after forming the second doped semiconductor layer at least on the second region, the method for manufacturing a back-contact cell further includes: removing the insulating mask layer on the first region.

[0053] As a possible implementation, the selective doping of the intrinsic semiconductor material layer includes: forming a doping mask layer disposed entirely on the intrinsic semiconductor material layer. Next, using a laser etching process, selectively removing the portion of the doping mask layer corresponding to the first region. Next, doping the portion of the intrinsic semiconductor material layer located above the first region under the masking effect of the doping mask layer. Then, removing the doping mask layer.

[0054] In the above technical solution, before doping, a doping mask layer is formed entirely on the intrinsic semiconductor material layer. A laser etching process is then used to selectively remove the portion of the doping mask layer corresponding to the first region. Because the laser etching process offers high etching precision, the precision of the formed doping mask layer can be improved, leaving only the portion of the intrinsic semiconductor material layer corresponding to the first region exposed. This ensures that the impurity doping range within the intrinsic semiconductor material layer after doping meets operational requirements.

[0055] As a possible implementation, the doping mask layer includes a silicon nitride layer located on the intrinsic semiconductor material layer, and an intrinsic silicon layer located on the silicon nitride layer. In this case, at least the laser etching process is used to selectively remove the portion of the doping mask layer corresponding to the first region, including: using a laser etching process to selectively remove the portion of the intrinsic silicon layer corresponding to the first region; and using a wet etching process to remove the portion of the silicon nitride layer corresponding to the first region under the masking effect of the intrinsic silicon layer. Furthermore, a diffusion process is used to dope the portion of the intrinsic semiconductor material layer located on the first region under the masking effect of the doping mask layer. After doping, a first doped silicon glass layer is formed on the portion of the first doped semiconductor layer corresponding to the first region, and the intrinsic silicon layer forms a second doped silicon glass layer. Furthermore, removing the doping mask layer includes simultaneously removing the first doped silicon glass layer and the second doped silicon glass layer. Then, the silicon nitride layer is removed.

[0056] When the above technical solution is adopted, in order to completely remove the portion of the doped mask layer corresponding to the first region, the etching capacity used in the laser etching process may cause high-temperature damage to the portion of the intrinsic semiconductor material layer corresponding to the first region. In addition, the intrinsic silicon layer has light-absorbing properties and can absorb part of the etchant light. Based on this, when the doped mask layer includes a silicon nitride layer and an intrinsic silicon layer, only the portion of the intrinsic silicon layer corresponding to the first region is selectively removed by the laser etching process, and the portion of the silicon nitride layer corresponding to the first region is removed under the masking action of the intrinsic silicon layer. This can reduce or even eliminate the degree of damage caused by the laser etching process to the portion of the intrinsic semiconductor material layer corresponding to the first region, thereby improving the formation quality of the first doped semiconductor layer. In addition, under the masking action of the doped mask layer, after the portion of the intrinsic semiconductor material layer located on the first region is doped using a diffusion process, a first doped silicon glass layer is formed on the portion of the first doped semiconductor layer corresponding to the first region, and the portion of the intrinsic silicon layer remaining in the isolation region and the second region forms a second doped silicon glass layer. The materials of the first doped silicon glass layer and the second doped silicon glass layer are the same, so the second doped silicon glass layer can be removed at the same time as the first doped silicon glass layer is removed. In order to form a film layer with light-absorbing properties on the silicon nitride layer, an additional selective etching step is provided to remove the film layer with light-absorbing properties, thereby simplifying the manufacturing process of the back-contact battery and improving the manufacturing efficiency of the back-contact battery.

[0057] As one possible implementation, forming the insulating mask layer covering the first region and the isolation region includes forming an insulating mask layer entirely over the first doped semiconductor layer, the intrinsic semiconductor layer, and the remaining portion of the intrinsic semiconductor material layer in the second region. A laser etching process is then used to selectively remove the portion of the insulating mask layer corresponding to the second region. In this case, the laser etching process has high etching precision, which can improve the accuracy of forming the insulating mask layer, thereby improving the accuracy of selective etching based on the insulating mask layer, thereby improving the yield of back-contact cells.

[0058] As one possible implementation, after removing the portion of the intrinsic semiconductor material layer remaining on the second region under the masking action of the insulating mask layer, and before etching the insulating mask layer, a texturing treatment is performed on the surface of the second region and the first surface of the semiconductor substrate. After the texturing treatment, the sidewalls of the intrinsic semiconductor layer adjacent to the second region are flush with or recessed inwardly relative to the boundary between the second region and the isolation region.

[0059] As a possible implementation, a wet chemical process is used, and the insulating mask layer is etched using an acidic etching solution. In this case, the acidic etching solution can be used to specifically etch the insulating mask layer, reducing the degree to which the intrinsic semiconductor layer is affected by the etching process, ensuring that the intrinsic semiconductor layer has a relatively large width, and improving the insulation effect of the intrinsic semiconductor layer in electrically isolating the first doped semiconductor layer from the second doped semiconductor layer.

[0060] As a possible implementation, after selectively doping the portion of the intrinsic semiconductor material layer located on the first region and before selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region, the method for manufacturing a back-contact battery further includes: annealing the first doped semiconductor layer and the intrinsic semiconductor layer. After the selective doping and annealing, the portion of the intrinsic semiconductor material layer located on the first region and a portion of the isolation region forms a first doped semiconductor layer, and the portion of the intrinsic semiconductor material layer located on the remaining isolation region forms an intrinsic semiconductor layer. The portion of the first doped semiconductor layer located on the first region is a first doped portion, and the portion of the first doped semiconductor layer located in the isolation region is a second doped portion. The doping concentration of impurities in the second doped portion is lower than the doping concentration of impurities in the first doped portion.

[0061] In the above technical solution, the second doped portion is formed by diffusion when doping the portion of the intrinsic semiconductor material layer located above the first region under the masking effect of the doping mask layer. Based on this, after selective doping, annealing the first doped semiconductor layer and the intrinsic semiconductor layer can cause the second doped portion, or impurities in the first doped portion and the second doped portion, to diffuse a longer distance parallel to the second surface after heating, thereby obtaining a second doped portion with a larger actual width. This allows the second doped portion to collect and conduct more carriers in a timely manner, further reducing the carrier recombination rate in the isolation region.

[0062] In an alternative embodiment, forming a second doped semiconductor layer at least on the second region further comprises:

[0063] A second doped semiconductor layer is formed on the insulating mask layer and the second region.

[0064] In an alternative embodiment, the selectively doping the intrinsic semiconductor material layer comprises:

[0065] forming a doping mask layer on a portion of the intrinsic semiconductor material layer corresponding to the second region and the isolation region;

[0066] doping a portion of the intrinsic semiconductor material layer located on the first region under the masking effect of the doping mask layer;

[0067] The doping mask layer is removed.

[0068] In an alternative embodiment, after removing the doping mask layer and before forming the second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing a back contact cell includes: forming a mask material layer disposed entirely on the first doped semiconductor layer, the intrinsic semiconductor layer, and the portion of the intrinsic semiconductor material layer remaining on the second region;

[0069] removing a portion of the mask material layer located above the second region, and forming a remaining portion of the mask material layer into an insulating mask layer;

[0070] selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region under the masking effect of the insulating mask layer;

[0071] Under the masking effect of at least a portion of the insulating mask layer, a texturing process is performed on the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region.

[0072] In an alternative embodiment, the method for manufacturing the back contact cell further comprises:

[0073] Using a laser etching process, sequentially removing the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region; and / or,

[0074] The insulating mask layer includes a first silicon nitride layer and a second silicon nitride layer spaced apart along the thickness direction of the semiconductor substrate, and an intrinsic silicon layer located between the first silicon nitride layer and the second silicon nitride layer; after the texturing treatment is performed on the first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region, before forming the second doped semiconductor layer on the insulating mask layer and the second region, the manufacturing method of the back contact battery further includes: removing the second silicon nitride layer and the intrinsic silicon layer in sequence.

[0075] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0076] In a third aspect, the present invention also provides another method for manufacturing a back-contact battery, comprising: providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface facing each other; the second surface has first and second regions alternately spaced, and an isolation region between each first region and its adjacent second region. Next, a first passivation material layer is formed as a full-layer on the second surface. Next, a layer of intrinsic semiconductor material is formed as a full-layer on the first passivation material layer. Next, the portion of the intrinsic semiconductor material layer located on the first region is selectively doped, so that the portion of the intrinsic semiconductor material layer located on the first region and the isolation region forms a first doped semiconductor layer and an intrinsic semiconductor layer. The first doped semiconductor layer includes a first doped portion and a second doped portion, the first doped portion being located on the first region and the second doped portion being located in the isolation region; the doping concentration of impurities in the second doped portion being lower than the doping concentration of impurities in the first doped portion. The intrinsic semiconductor layer is formed in a direction parallel to the second surface on the portion of the isolation region excluding the second doped portion. Next, an insulating mask layer is formed covering the first region and the isolation region; and the portion of the intrinsic semiconductor material layer remaining on the second region is removed under the masking action of the insulating mask layer. Next, under the masking action of the insulating mask layer, the portion of the first passivation material layer located on the second region is removed, so that the remaining portion of the first passivation material layer forms the first passivation layer. Next, the insulating mask layer is etched so that the sidewalls of the insulating mask layer near the second region are flush with or recessed inwardly relative to the sidewalls of the intrinsic semiconductor layer near the second region. Next, a second doped semiconductor layer is formed on the portion of the insulating mask layer corresponding to the isolation region and on the second region. The second doped semiconductor layer has an opposite conductivity type to the first doped semiconductor layer. Next, the insulating mask layer on the first region is removed.

[0077] The beneficial effects of the third aspect of the present invention can be referenced to the analysis of the beneficial effects of the back-contact cell including the first passivation layer in the first aspect, and will not be further elaborated here. Furthermore, the removal of the portion of the intrinsic semiconductor material layer corresponding to the second region and the removal of the portion of the first passivation material layer corresponding to the second region are both accomplished under the masking action of the same insulating mask layer, eliminating the need to form two separate mask layers to achieve the two selective etching portions. This simplifies the manufacturing process of the back-contact cell and improves its manufacturing efficiency.

[0078] In a fourth aspect, the present invention also provides another method for manufacturing a back-contact battery, comprising: first, providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface facing each other. The second surface has first and second regions alternately spaced apart, and an isolation region between each first region and its adjacent second region. Next, a first passivation material layer is formed as a whole layer on the second surface. Next, a layer of intrinsic semiconductor material is formed as a whole layer on the first passivation material layer. Next, the portion of the intrinsic semiconductor material layer located on the first region is selectively doped so that the portions of the intrinsic semiconductor material layer located on the first region and the isolation region form a first doped semiconductor layer and an intrinsic semiconductor layer. The first doped semiconductor layer includes a first doped portion and a second doped portion, the first doped portion being located on the first region and the second doped portion being located in the isolation region; the doping concentration of impurities in the second doped portion is lower than the doping concentration of impurities in the first doped portion; and the intrinsic semiconductor layer is formed in the isolation region, excluding the second doped portion, along a direction parallel to the second surface. Next, an insulating mask layer is formed covering the first region and the isolation region; and under the masking action of the insulating mask layer, the portion of the intrinsic semiconductor material layer remaining on the second region is removed. Next, under the masking action of the insulating mask layer, the portion of the first passivation material layer located on the second region is removed, so that the remaining portion of the first passivation material layer forms the first passivation layer. Next, the insulating mask layer is etched so that the sidewalls of the insulating mask layer near the second region are flush with or recessed inward relative to the sidewalls of the intrinsic semiconductor layer near the second region, and the sidewalls of the intrinsic semiconductor layer near the second region are flush with or recessed inward relative to the boundary between the second region and the isolation region. Next, a second passivation layer and a second doped semiconductor layer are formed in a stacked manner on the portion of the insulating mask layer corresponding to the isolation region and the second region. The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. Next, the insulating mask layer on the first region is removed.

[0079] The beneficial effects of the fourth aspect of the present invention can be analyzed with reference to the beneficial effects when the back contact battery in the first aspect further includes a second passivation layer, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0081] FIG1 is a schematic longitudinal cross-sectional view of a first structure of a back-contact battery provided by one embodiment of the present invention;

[0082] FIG2 is a schematic longitudinal cross-sectional view of a second structure of a back-contact battery provided by one embodiment of the present invention;

[0083] FIG3 is a schematic longitudinal cross-sectional view of a third structure of a back-contact battery provided by one embodiment of the present invention;

[0084] FIG4 is a schematic longitudinal cross-sectional view of a fourth structure of a back-contact battery provided by one embodiment of the present invention;

[0085] FIG5 is a schematic longitudinal cross-sectional view of a fifth structure of a back-contact battery provided by another embodiment of the present invention;

[0086] FIG6 is a schematic longitudinal cross-sectional view of a sixth structure of a back-contact battery provided by another embodiment of the present invention;

[0087] FIG7 is a schematic longitudinal cross-sectional view of a seventh structure of a back-contact battery provided by another embodiment of the present invention;

[0088] FIG8 is a first schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0089] FIG9 is a second schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0090] FIG10 is a third schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0091] FIG11 is a fourth schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0092] FIG12 is a fifth schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0093] FIG13 is a sixth schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0094] FIG14 is a seventh schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0095] FIG15 is a schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0096] FIG16 is a ninth schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0097] FIG17 is a schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0098] FIG18 is a schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0099] FIG19 is a schematic twelfth cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0100] FIG20 is a SEM image of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0101] FIG21 is a thirteenth schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0102] FIG22 is a schematic structural cross-sectional view of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0103] FIG23 is a schematic cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0104] FIG24 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery in related art.

[0105] FIG25 is a first structural diagram of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0106] FIG26 is a second structural diagram of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0107] FIG27 is a third structural diagram of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0108] FIG28 is a fourth structural diagram of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0109] FIG29 is a fifth structural diagram of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0110] FIG30 is a sixth structural diagram of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0111] FIG31 is a seventh structural diagram of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0112] FIG32 is a structural schematic diagram eight of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0113] FIG33 is a ninth structural diagram of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0114] FIG34 is a structural schematic diagram 10 of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0115] FIG35 is a structural schematic diagram 11 of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0116] FIG36 is a structural schematic diagram 12 of a back-contact cell during the manufacturing process according to another embodiment of the present invention;

[0117] FIG37 is a thirteenth structural diagram of a back-contact battery during the manufacturing process provided by another embodiment of the present invention.

[0118] Figure numerals: 11 is a semiconductor substrate, 12 is a first surface, 13 is a second surface, 14 is a first region, 15 is a second region, 16 is an isolation region, 17 is a first doped semiconductor layer, 18 is an intrinsic semiconductor layer, 19 is a second doped semiconductor layer, 20 is an insulating mask layer, 21 is a first doped portion, 22 is a second doped portion, 23 is a first passivation layer, 24 is a second passivation layer, 25 is an intrinsic semiconductor material layer, 26 is a doping mask layer, 27 is a silicon nitride layer, 28 is an intrinsic silicon layer, 29 is a first doped silicon glass layer, 30 is a second doped silicon glass layer, 31 is a second doped semiconductor material layer, 32 is a first passivation material layer, 33 is a second passivation material layer, 34 is a transparent conductive layer, 35 is an insulating groove, 36 is an electrode, 37 is an interface passivation layer, 38 is an anti-reflection layer, 39 is a first silicon nitride layer, 40 is a second silicon nitride layer, and 41 is an intrinsic silicon layer. DETAILED DESCRIPTION

[0119] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0120] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0121] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0122] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0123] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0124] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells are devices that convert sunlight into electricity. Specifically, they use the principle of photovoltaics to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0125] When both the positive and negative electrodes of a solar cell are located on the back side of the solar cell, the solar cell is called a back-contact cell. The most significant feature of a back-contact cell is that it has no metal electrode blocking the front side, resulting in a higher short-circuit current (Isc). This makes back-contact cells one of the current technological advancements in achieving high-efficiency crystalline silicon cells.

[0126] Specifically, the above-mentioned back-contact cell generally includes a semiconductor substrate, a first doped semiconductor layer, a second doped semiconductor layer, and an insulating mask layer. The first doped semiconductor layer and the second doped semiconductor layer are alternately formed on the same side of the semiconductor substrate in a direction parallel to the surface of the semiconductor substrate. Furthermore, the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types, and the second doped semiconductor layer covers a portion of the first doped semiconductor layer. The insulating mask layer is located only between the first doped semiconductor layer and the second doped semiconductor layer to isolate the first doped semiconductor layer from the second doped semiconductor layer. Furthermore, in actual applications, compared with doped amorphous silicon layers, doped crystalline silicon layers have higher carrier transport layer capabilities. Therefore, when at least one of the above-mentioned first doped semiconductor layer and the second doped semiconductor layer is a doped crystalline silicon layer, it is beneficial to improve its own carrier collection efficiency, reduce the carrier recombination rate on the backlight side, and improve the photoelectric conversion efficiency of the back-contact cell.

[0127] However, during the manufacturing process of the aforementioned back-contact cell, after forming a complete semiconductor material layer on the backlight side and doping at least the portion of the semiconductor material layer corresponding to the first doped semiconductor layer, it is necessary to selectively etch the semiconductor material layer under the masking action of the insulating mask layer to expose the region of the semiconductor substrate corresponding to the second doped semiconductor layer. During the selective etching of the semiconductor material layer by the etchant under the masking action of the insulating mask layer, the etchant not only etches the portion of the semiconductor material layer exposed outside the insulating mask layer along the thickness direction of the semiconductor substrate, but also etches the edge portion of the semiconductor material layer in a direction parallel to the surface of the semiconductor substrate. Since the material of the insulating mask layer has a certain etching selectivity with respect to the material of the semiconductor material layer, the etchant that selectively etches the semiconductor material layer has no or very little etching effect on the insulating mask layer. Therefore, after the selective etching, the sidewalls of the insulating mask layer protrude beyond the sidewalls of the first doped semiconductor layer, resulting in a gap between the protruding portion of the insulating mask layer and the semiconductor substrate. Because the size of the gap is small, after the second doped semiconductor layer is formed, the portion of the second doped semiconductor layer close to the first doped semiconductor layer and the insulating mask layer is difficult to fill in the above-mentioned gap, resulting in a large number of defects at the corresponding gap of the back contact battery and a high carrier recombination rate, which leads to a decrease in the photoelectric conversion efficiency of the back contact battery.

[0128] In addition, the insulating mask layer in the above-mentioned back-contact battery can only electrically isolate the first doped semiconductor layer and the second doped semiconductor layer along the thickness direction of the semiconductor substrate. When at least one of the first doped semiconductor layer and the second doped semiconductor layer is a doped crystalline silicon layer, because the doped crystalline silicon layer has good carrier lateral transport characteristics, when the back-contact battery is in operation, the first doped semiconductor layer and the second doped semiconductor layer will be electrically contacted in a direction parallel to the semiconductor substrate, resulting in leakage, which leads to a decrease in the photoelectric conversion efficiency of the back-contact battery. In the prior art, an intrinsic amorphous silicon passivation layer or a tunneling silicon dioxide layer is also provided between the first doped semiconductor layer and the second doped semiconductor layer. Since the intrinsic amorphous silicon passivation layer or the tunneling silicon dioxide layer has a tunneling effect, when the highly conductive doped polycrystalline silicon is used as the semiconductor doping layer, it is easy to break through the intrinsic amorphous silicon passivation layer or the tunneling silicon dioxide layer, thereby generating a large leakage.

[0129] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back-contact battery. As shown in Figures 1 and 5, the back-contact battery includes: a semiconductor substrate 11, a first doped semiconductor layer 17, an intrinsic semiconductor layer 18, and a second doped semiconductor layer 19. The semiconductor substrate 11 has a first and a second opposite surface. The second surface has first regions 14 and second regions 15 alternately distributed, and an isolation region 16 located between each first region 14 and the second region 15 adjacent to it. The first doped semiconductor layer 17 includes a first doping portion 21 and a second doping portion 22, the first doping portion 21 being located on the first region 14, and the second doping portion 22 being located in the isolation region 16; the doping concentration of impurities in the second doping portion 22 is lower than the doping concentration of impurities in the first doping portion 21. The intrinsic semiconductor layer 18 is formed on the portion outside the second doping portion 22 of the isolation region 14 in a direction parallel to the second surface. The second doped semiconductor layer 19 covers the second region 15. The second doped semiconductor layer 19 has an opposite conductivity type to the first doped semiconductor layer 17. The intrinsic semiconductor layer 18 is used to electrically isolate the first doped semiconductor layer 17 from the second doped semiconductor layer 19. In one embodiment, the intrinsic semiconductor layer is an undoped semiconductor material layer and is relatively wide, measuring several microns. In another embodiment, the intrinsic semiconductor layer is formed when a first passivation layer of an intrinsic semiconductor is deposited on the second region. It is relatively thin and only serves as an isolation layer under normal circumstances. It does not prevent reverse electrical breakdown and can only serve to prevent hot spots.

[0130] When the above technical solution is adopted, as shown in Figures 1 and 5, the first doped semiconductor layer 17 and the second doped semiconductor layer 19 are both formed on the second side of the semiconductor substrate 11, and the conductivity types of the two are opposite. Based on this, when the back contact battery is in the working state, the electrons and holes generated by the semiconductor substrate 11 after absorbing photons move toward the first doped semiconductor layer 17 and the second doped semiconductor layer 19 respectively, and are collected and conducted by the two respectively to form a photocurrent. Among them, because the intrinsic semiconductor layer 18 is non-conductive, the presence of the intrinsic semiconductor layer 18 can electrically isolate the first doped semiconductor layer 17 and the second doped semiconductor layer 19 of opposite conductivity types, thereby suppressing leakage. In addition, in the actual manufacturing process, due to the accuracy of the machine and / or for the purpose of preventing leakage, the width of the isolation region 16 located between the first region 14 and the adjacent second region 15 is relatively large. Based on this, the first doped semiconductor layer 17 not only includes a first doped portion 21 located on the first region 14, but also includes a second doped portion 22 located on the partial isolation region 16. At this time, when the back contact battery is in a working state, the first doped semiconductor layer 17 can not only collect and export the electrons or holes corresponding to the first region 14 in a timely manner, but also collect and export the electrons or holes corresponding to the partial isolation region 16 in a timely manner. Therefore, while preventing the first doped semiconductor layer 17 and the second doped semiconductor layer 19 from lateral leakage through the intrinsic semiconductor layer 18, it can also reduce the carrier recombination rate at the isolation region 16 with a larger width, thereby further improving the photoelectric conversion efficiency of the back contact battery. Furthermore, because the second doped portion 22 is located between the first doped portion 21 and the intrinsic semiconductor layer 18, when the impurity doping concentration within the second doped portion 22 located on the partial isolation region 16 is lower than the impurity doping concentration within the first doped portion 21 located on the first region 14, the conductivity of the second doped portion 22 can be reduced, reducing the risk of electric shock penetrating the intrinsic semiconductor layer 18. This also inhibits or even eliminates the diffusion of impurities within the second doped portion 22 into the intrinsic semiconductor layer 18, ensuring good electrical isolation of the intrinsic semiconductor layer 18 and good electrical performance for the back-contact cell. In practical applications, the semiconductor substrate can be made of a semiconductor material such as silicon, germanium-silicon, or germanium. In terms of conductivity type, the semiconductor substrate can be an N-type or P-type semiconductor substrate. Structurally, the first surface of the semiconductor substrate corresponds to the light-facing surface of the back-contact cell, and the second surface of the semiconductor substrate corresponds to the back-light-repelling surface of the back-contact cell. Therefore, as shown in Figures 1 and 5, both the light-facing and back-light-repelling surfaces of the semiconductor substrate 11 can be polished, i.e., relatively flat, surfaces. Alternatively, as shown in FIG. 2 and FIG. 7 , the light-facing surface of the semiconductor substrate 11 and the surface of the semiconductor substrate 11 corresponding to the second region 15 are both textured.In this case, the refractive index of light transmitted from the first surface and the surface of the second region 15 to the semiconductor substrate 11 can be increased, further improving the photoelectric conversion efficiency of the back-contact cell. In addition, when the surface of the second region 15 is a velvet surface, the back-light side of the second doped semiconductor layer 19 formed on the second region 15 also has corresponding undulating features. Compared with a flat surface, a surface with undulating features has a larger specific surface area. Therefore, when the back-light side of the second doped semiconductor layer 19 on the second region 15 has undulating features, it is beneficial to increase the contact area between the second doped semiconductor layer 19 and the electrode 36, reduce the contact resistance between the two, and further improve the electrical performance of the back-contact cell.

[0131] In addition, as shown in Figures 1 and 5, the second surface of the semiconductor substrate 11 has alternating first regions 14 and second regions 15, as well as an isolation region 16 located between each first region 14 and its adjacent second region 15. It should be understood that the boundaries between the first regions 14, second regions 15, and isolation regions 16 are virtual boundaries. Furthermore, because the first doped portions 21 included in the first doped semiconductor layer 17 are formed on the first regions 14, the position, number, and specifications of the first regions 14 on the backlight side of the semiconductor substrate 11 affect the position, number, and specifications of the first doped portions 21 formed subsequently. Correspondingly, because the second doped semiconductor layer 19 is formed on the second regions 15, the position, number, and specifications of the second regions 15 on the semiconductor substrate 11 affect the position, number, and specifications of the portion of the second doped semiconductor layer 19 that directly contacts the semiconductor substrate 11 formed subsequently. Regarding the position of the isolation region 16, after the ranges of the first and second regions 14, 15 are determined, the remaining area of ​​the second surface serves as the isolation region 16. Based on this, the specific position, quantity and specifications of the above-mentioned first region 14, second region 15 and isolation region 16 on the semiconductor substrate 11 can be set according to the requirements of information such as the position of the corresponding parts of the first doped semiconductor layer 17 and the second doped semiconductor layer 19 in the actual application scenario, and no specific limitation is made here.

[0132] For the above-mentioned first doped semiconductor layer, in terms of conductivity type, the first doped portion and the second doped portion included in the first doped semiconductor layer have the same conductivity type; wherein the conductivity type of the first doped semiconductor layer can be N-type or P-type; the specific conductivity type of the first doped semiconductor layer can be based on the actual application scenario and is not specifically limited here.

[0133] In terms of the formation range, as shown in FIG1 , the first doped semiconductor layer 17 includes a first doped portion 21 located on the first region 14 , and the portion of the first doped semiconductor layer 17 corresponding to the isolation region 16 is a second doped portion 22 . The doping concentration of impurities in the second doped portion 22 is lower than the doping concentration of impurities in the first doped portion 21 . In the above case, the intrinsic semiconductor layer 18 is formed on the portion of the isolation region 16 other than the second doped portion 22 . Specifically, in terms of impurity doping concentration, the specific doping concentration of impurities in the first doped portion 21 and the second doped portion 22 can be determined according to the actual application scenario, as long as the doping concentration of impurities in the second doped portion 22 is lower than the doping concentration of impurities in the first doped portion 21 .

[0134] For example, the doping concentration of the impurities in the second doping portion may be greater than or equal to 1E18 cm -3 , and less than or equal to 5E20cm -3 For example, the doping concentration of the impurities in the second doping portion can be 1E18 cm -3 、5E18 cm -3 、1E19 cm -3 、 5E19 cm -3 、1E20cm -3 or 5E20cm -3 In this case, the impurity concentration within the second doped portion is within the above range, which can prevent the second doped portion from having a low impurity concentration that would result in poor carrier collection capabilities, further improving the degree to which the second doped portion reduces the carrier recombination rate in the isolation region. Furthermore, it can prevent carriers within the second doped portion from easily diffusing into the intrinsic semiconductor layer due to a high impurity concentration, ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0135] For example, the doping concentration of impurities in the second doped portion gradually decreases along the direction from the second doped portion to the intrinsic semiconductor layer. In this case, while ensuring that the impurities in the second doped portion have a certain doping concentration, thereby enabling the second doped portion to have a certain carrier lateral collection capability, the portion of the second doped portion with the lowest impurity doping concentration can also be brought into contact with the intrinsic semiconductor layer, reducing the carrier concentration gradient at the contact point between the two, further suppressing or even eliminating the diffusion of impurities in the second doped portion into the intrinsic semiconductor layer, and ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0136] The extent to which the doping concentration of impurities in the second doping portion gradually decreases along the direction from the second doping portion to the intrinsic semiconductor layer can be determined according to actual application scenarios and is not specifically limited here.

[0137] For example, the doping concentration of the impurities in the first doping portion is 10 to 100 times the doping concentration of the impurities in the second doping portion. For example, when the doping concentration of the impurities in the second doping portion is 1E18 cm -3 When the doping concentration of the impurities in the first doping part can be 1E19 cm -3 、3E19 cm -3 、5E19 cm -3 、7E19cm -3 or 1E20cm -3 In this case, the doping concentration of the impurities in the first doped portion is relatively high, which can make the first doped portion have a higher carrier collection ability. In addition, it can also reduce the manufacturing difficulty of obtaining the first doped portion with an excessively high doping concentration.

[0138] In terms of size, because the second doped portion and the intrinsic semiconductor layer are co-located on the isolation region, and the width of the intrinsic semiconductor layer along the direction from the first region to the second region affects its isolation effect, the width of the intrinsic semiconductor layer and the width of the isolation region can be determined based on the requirement in actual application scenarios for electrically isolating the first doped semiconductor layer and the second doped semiconductor layer along a direction parallel to the second surface via the intrinsic semiconductor layer. Furthermore, the width of the second doped portion can be determined based on the width of the intrinsic semiconductor layer and the width of the isolation region. The embodiments of the present invention do not specifically limit the widths of the second doped portion, the intrinsic semiconductor layer, and the isolation region.

[0139] Exemplarily, along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the isolation region may be greater than or equal to 30 μm and less than or equal to 200 μm. For example, the width of the isolation region may be 30 μm, 50 μm, 80 μm, 100 μm, 150 μm, or 200 μm, etc. In this case, the width of the isolation region is within the above range, which can prevent the difficulty of providing a second doped portion and an intrinsic semiconductor layer with a reasonable width within a smaller width range due to the smaller range of the isolation region, thereby ensuring that the second doped portion and the intrinsic semiconductor layer have the functions described above. In addition, it can also prevent the first doped semiconductor layer and / or the second doped semiconductor layer from being smaller due to the larger width of the intrinsic semiconductor layer, thereby ensuring that the first doped semiconductor layer and the second doped semiconductor layer can collect and conduct the carriers corresponding to the first region and the second region in a timely manner, further reducing the carrier recombination rate on the second side.

[0140] Exemplarily, along the direction from the second doped portion to the intrinsic semiconductor layer, the width of the intrinsic semiconductor layer may be greater than or equal to 6 μm and less than or equal to 120 μm. For example, the width of the intrinsic semiconductor layer may be 6 μm, 10 μm, 20 μm, 50 μm, 80 μm, 100 μm, 110 μm, or 120 μm, etc. In this case, the width of the intrinsic semiconductor layer is within the above range, which can prevent the electrical isolation effect of the intrinsic semiconductor layer parallel to the second direction from being affected by the small width of the intrinsic semiconductor layer, and ensure that the first doped semiconductor layer and the second doped semiconductor layer can be prevented from generating leakage along the direction parallel to the second surface through the intrinsic semiconductor layer. In addition, it can also prevent the second doped portion from having a lower carrier collection capacity due to the larger width of the intrinsic semiconductor layer, further improving the degree to which the carrier recombination rate at the isolation region is reduced by the second doped portion.

[0141] For example, along the direction from the second doped portion to the intrinsic semiconductor layer, the ratio of the width of the second doped portion to the width of the isolation region can be greater than or equal to 0.8 and less than 1. For example, the ratio of the width of the second doped portion to the width of the isolation region can be 0.8, 0.82, 0.84, 0.86, 0.88, 0.9, or 0.92. In this case, when the ratio of the width of the second doped portion to the width of the isolation region along the direction from the second doped portion to the intrinsic semiconductor layer is within the above range, the width of the second doped portion is greater than the width of the intrinsic semiconductor layer. This prevents the second doped portion from significantly reducing the carrier recombination rate in the isolation region due to its smaller width, thereby ensuring a high photoelectric conversion efficiency for the back-contact cell. Furthermore, because the second doped portion and the intrinsic semiconductor layer are co-located on the isolation region, when the width of the isolation region is constant, the width of the second doped portion is inversely proportional to the width of the intrinsic semiconductor layer. Furthermore, within a certain range, the electrical isolation effect of the intrinsic semiconductor layer in a direction parallel to the second surface is directly proportional to its width. Based on this, when the ratio is within the above range, it can also prevent the electrical isolation effect of the intrinsic semiconductor layer from being poor due to the small width of the second doped part, and ensure that the first doped semiconductor layer and the second doped semiconductor layer can be prevented from leaking electricity along the path parallel to the second surface through the intrinsic semiconductor layer.

[0142] The specific width of the second doped portion can be determined based on the width of the isolation region and the ratio of the width of the second doped portion to the width of the isolation region. For example, when the width of the isolation region is greater than or equal to 30 μm and less than or equal to 200 μm, and the ratio of the width of the second doped portion to the width of the isolation region is 0.8, the width of the second doped portion can be 24 μm, 50 μm, 80 μm, 100 μm, 150 μm, or 160 μm, etc.

[0143] In terms of materials, the material of the first doped semiconductor layer can include any semiconductor material, as long as it can be applied to the back-contact battery provided by the embodiments of the present invention. For example, the first doped semiconductor layer can be a doped amorphous silicon layer or a doped crystalline silicon layer. When the first doped semiconductor layer is a doped crystalline silicon layer, the material of the first doped semiconductor layer can include microcrystalline silicon, single crystal silicon, polycrystalline silicon, nanocrystalline silicon, etc.

[0144] It is worth noting that compared to doped amorphous silicon layers, doped crystalline silicon layers have higher lateral carrier transport properties. Therefore, when the first doped semiconductor layer is a doped crystalline silicon layer, the first doped semiconductor layer can have higher carrier collection properties, reducing the carrier recombination efficiency in the first region. As shown in Figures 1 and 5, a portion of the insulating mask layer 20 and a portion of the second doped semiconductor layer 19 cover the second doped portion 22. Therefore, when the first doped semiconductor layer 17 is a doped crystalline silicon layer, the second doped portion 22 has good lateral carrier transport properties, which facilitates the second doped portion 22 to laterally transfer more electrons or holes collected by the second doped portion 22 to the first doped portion 21, and then conduct them through the exposed first doped portion 21, further reducing the carrier recombination efficiency in the isolation region 16.

[0145] As for the intrinsic semiconductor layer, the intrinsic semiconductor layer and the first doped semiconductor layer can be formed from a different semiconductor material layer. In this case, the material and thickness of the intrinsic semiconductor layer can be different from or the same as those of the first doped semiconductor layer, as long as the second doped semiconductor layer can be electrically isolated from the first doped semiconductor layer by the intrinsic semiconductor layer.

[0146] Alternatively, the intrinsic semiconductor layer can also be an integral structure with the first doped semiconductor layer; in other words, the intrinsic semiconductor layer and the first doped semiconductor layer can be based on the same intrinsic semiconductor material layer and formed simultaneously, so as to prevent the intrinsic semiconductor layer from being coated on the portion of the first doped semiconductor layer near the isolation region due to the additional formation of the intrinsic semiconductor layer by deposition and etching processes after the first doped semiconductor layer is formed, thereby ensuring that the first doped semiconductor layer corresponds to a larger process window. In this case, the thickness of the intrinsic semiconductor layer is equal to the thickness of the first doped semiconductor layer, and the material of the intrinsic semiconductor layer can refer to the material of the first doped semiconductor layer. For example, when the material of the first doped semiconductor layer is doped polysilicon, the material of the intrinsic semiconductor layer is intrinsic polysilicon.

[0147] In terms of the formation range, as shown in FIG1 , along the arrangement direction of the first region 14 and the second region 15, the sidewall of the intrinsic semiconductor layer 18 near the second region 15 can be flush with the boundary between the second region 15 and the isolation region 16. Alternatively, as shown in FIG2 and FIG4 , along the arrangement direction of the first region 14 and the second region 15, the sidewall of the intrinsic semiconductor layer 18 near the second region 15 can also be recessed inward relative to the boundary between the second region 15 and the isolation region 16. In this case, during the actual manufacturing process, after the portion of the intrinsic semiconductor material layer corresponding to the second region 15, which is disposed entirely on one side of the second surface and used to form the first doped semiconductor layer 17 and the intrinsic semiconductor layer 18, is selectively etched, the surface of the semiconductor substrate 11 corresponding to the second region 15 will generally be recessed inward relative to the surface of the isolation region 16. Based on this, when the sidewalls of the intrinsic semiconductor layer 18 near the second region 15 are recessed inward relative to the boundary between the second region 15 and the isolation region 16, a step-like structure can be formed between the intrinsic semiconductor layer 18 and the surface of the second region 15, and between the surface of the second region 15 and the surface of the isolation region 16. This facilitates the second doped semiconductor layer 19 to better cover the edge of the intrinsic semiconductor layer 18. That is, along the direction from the second region 15 to the first region 14, the surface height change of the corresponding structure covered by the second doped semiconductor layer 19 has a transition, which facilitates the second doped semiconductor layer 19 to better cover the edge of the intrinsic semiconductor layer 18, thereby improving the yield of the back-contact cell. At the same time, it also helps to further prevent the existence of unfilled gaps on the side of the second surface after the formation of the second doped semiconductor layer 19, thereby reducing the number of defects on the back-light side of the back-contact cell, reducing the carrier recombination rate, and improving the photoelectric conversion efficiency of the back-contact cell.

[0148] The embodiment of the present invention does not impose any specific limitation on the distance by which the sidewall of the intrinsic semiconductor layer close to the second region may be recessed relative to the boundary between the second region and the isolation region, as long as it can be applied to the back-contact battery provided by the embodiment of the present invention.

[0149] Alternatively, in another embodiment as shown in FIGS. 6 and 7 , the sidewall of the intrinsic semiconductor layer 18 adjacent to the second region 15 may also be flush with the boundary between the second region 15 and the isolation region 16 .

[0150] Illustratively, along the arrangement direction of the first region and the second region, the distance by which the sidewall of the intrinsic semiconductor layer close to the second region is recessed inward relative to the boundary between the second region and the isolation region may be greater than or equal to 0 and less than or equal to 5 μm. For example, the distance by which the sidewall of the intrinsic semiconductor layer close to the second region is recessed inward relative to the boundary between the second region and the isolation region may be 0 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm, or 5 μm, etc. In this case, the larger the distance, the smaller the width of the intrinsic semiconductor layer, which may lead to a deterioration in the electrical insulation performance of the intrinsic semiconductor layer, thereby ensuring that the first doped semiconductor layer and the second doped semiconductor layer can be electrically isolated by the intrinsic semiconductor layer.

[0151] Regarding the second doped semiconductor layer, in terms of conductivity type, when the conductivity type of the first doped semiconductor layer is N-type, the conductivity type of the second doped semiconductor layer is P-type. When the conductivity type of the first doped semiconductor layer is P-type, the conductivity type of the second doped semiconductor layer is N-type.

[0152] From a material perspective, the material of the second doped semiconductor layer can be any semiconductor material, as long as it can be applied to the back-contact battery provided by the embodiments of the present invention. For example, the second doped semiconductor layer can be a doped crystalline silicon layer or a doped amorphous silicon layer; the specific material of the doped crystalline silicon layer can be referred to above. In actual application, when the first doped semiconductor layer is a doped amorphous silicon layer, the second doped semiconductor layer can be a doped crystalline silicon layer. And when the first doped semiconductor layer is a doped crystalline silicon layer, the second doped semiconductor layer can be a doped amorphous silicon layer or a doped crystalline silicon layer.

[0153] It should be noted that, as shown in Figures 2 and 4, the above-mentioned back-contact cell may further include a transparent conductive layer 34, which covers at least the first doped semiconductor layer 17 and the second doped semiconductor layer 19. Furthermore, an insulating trench 35 is provided through the portion of the transparent conductive layer 34 corresponding to the isolation region 16 to electrically isolate the portion of the transparent conductive layer 34 located on the first doped semiconductor layer 17 from the portion of the transparent conductive layer 34 located on the second doped semiconductor layer 19. In this case, the transparent conductive layer 34 has excellent electrical transmission characteristics. Therefore, when the back-contact cell further includes a transparent conductive layer 34 covering at least the first doped semiconductor layer 17 and the second doped semiconductor layer 19, carriers can be collected and discharged in a timely manner, thereby reducing the carrier recombination rate on the second side. In addition, because the first doped semiconductor layer 17 and the second doped semiconductor layer 19 have opposite conductivity types, an insulating groove 35 is provided through the portion of the transparent conductive layer 34 corresponding to the isolation region 16 to electrically isolate the portion of the transparent conductive layer 34 located on the first doped semiconductor layer 17 from the portion of the transparent conductive layer 34 located on the second doped semiconductor layer 19, thereby ensuring that the back-contact battery has higher electrical reliability.

[0154] The insulating trench is positioned parallel to the surface of the semiconductor substrate, corresponding to the isolation region. Furthermore, the embodiments of the present invention do not impose any specific limitations on the width and extent of the insulating trench; any insulating trench can be used as long as it electrically isolates the portion of the transparent conductive layer located on the first doped semiconductor layer from the portion of the transparent conductive layer located on the second doped semiconductor layer.

[0155] The extent of the second doped semiconductor layer can be determined based on the specific structure of the back-contact cell. The second doped semiconductor layer can be formed only on the second region. Alternatively, as shown in Figures 2 to 4, the second doped semiconductor layer 19 can also cover the second region 15, the intrinsic semiconductor layer 18, and at least a portion of the second doped portion 22.

[0156] As a possible implementation, the back-contact cell provided in an embodiment of the present invention may further include an insulating mask layer. This insulating mask layer may be located on the second doped portion and the intrinsic semiconductor layer, and / or, as shown in FIG1 , the insulating mask layer 20 may be at least partially located between the second doped semiconductor layer 19 and the intrinsic semiconductor layer 18. In this case, because the insulating mask layer 20 is non-conductive, the presence of the insulating mask layer 20 can further electrically isolate the first doped semiconductor layer 17 and the second doped semiconductor layer 19 of opposite conductivity types along the thickness direction of the semiconductor substrate 11, thereby preventing leakage between the first doped semiconductor layer 17 and the second doped semiconductor layer 19 along the thickness direction of the semiconductor substrate 11.

[0157] Specifically, the material of the above-mentioned insulating mask layer can be any insulating material with a masking function, as long as it can be applied to the back-contact battery provided by the embodiment of the present invention. For example, the material of the insulating mask layer can be silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbide or intrinsic silicon, etc. Among them, when the material of the insulating mask layer includes silicon nitride, the insulating mask layer has good corrosion resistance, and can protect the first doped semiconductor layer and the intrinsic semiconductor layer from being affected by etching or being affected to a lesser extent when removing the portion of the intrinsic semiconductor material layer corresponding to the second region, which is beneficial to improving the yield of the back-contact battery. In addition, silicon nitride has a high dielectric constant, so that the insulating mask layer has good insulating properties, ensuring that the first doped semiconductor layer and the second doped semiconductor layer can be electrically isolated along the thickness direction of the semiconductor substrate through the insulating mask layer.

[0158] The thickness of the insulating mask layer can also be determined based on actual needs. For example, the thickness of the insulating mask layer can be greater than or equal to 40 nm and less than or equal to 80 nm. For example, the thickness of the insulating mask layer can be 40 nm, 50 nm, 60 nm, 70 nm, or 80 nm. In this case, if the thickness of the insulating mask layer is within the above range, it can prevent the insulating mask layer from having poor insulation properties due to its small thickness, ensuring that the first doped semiconductor layer and the second doped semiconductor layer can be electrically isolated along the thickness direction of the semiconductor substrate by the insulating mask layer. It can also prevent the insulating mask layer from having a weak protective effect on the first doped semiconductor layer and the intrinsic semiconductor layer located below it when selectively etching the portion of the intrinsic semiconductor material layer corresponding to the second region, thereby ensuring a high yield of the back-contact battery. In addition, it can also prevent the use of large consumables when forming the insulating mask layer due to the large thickness of the insulating mask layer, which is beneficial to controlling the manufacturing cost of the back-contact battery.

[0159] As for the sidewalls of the insulating mask layer near the second region, along the direction in which the first and second regions are arranged and extended, the sidewalls of the insulating mask layer near the second region can be flush with the sidewalls of the intrinsic semiconductor layer near the second region (as shown in Figures 5-7). Alternatively, as shown in Figure 1, along the direction in which the first and second regions 14 and 15 are arranged and extended, the sidewalls of the insulating mask layer 20 near the second region 15 can also be recessed inward relative to the sidewalls of the intrinsic semiconductor layer 18 near the second region 15. In this case, in the back-contact cell provided by the embodiment of the present invention, not only is there no small gap between the portion of the insulating mask layer 20 near the second region 15 and the semiconductor substrate 11, but also the portion of the insulating mask layer 20 near the second region 15 and the portion of the intrinsic semiconductor layer 18 near the second region 15 form a step-like structure, which facilitates better coverage of the second doped semiconductor layer 19 at the edge of the intrinsic semiconductor layer 18, preventing unfilled gaps on the second side after the second doped semiconductor layer 19 is formed, thereby reducing the number of defects on the back-light side of the back-contact cell, reducing the carrier recombination rate, and improving the photoelectric conversion efficiency of the back-contact cell.

[0160] As for the distance by which the sidewall of the insulating mask layer near the second region is recessed relative to the sidewall of the intrinsic semiconductor layer near the second region, as shown in Figures 18 to 20, in the actual manufacturing process, it is necessary to selectively dope the portion of the intrinsic semiconductor material layer corresponding to the first region 14 disposed on one side of the second surface to form the first doped semiconductor layer 17 and the intrinsic semiconductor layer 18. Furthermore, after forming the first doped semiconductor layer 17 and the intrinsic semiconductor layer 18, the portion of the intrinsic semiconductor material layer corresponding to the second region 15 can be removed under the masking action of the insulating mask layer 20. Then, the insulating mask layer 20 is etched so that the sidewall of the insulating mask layer 20 near the second region 15 is recessed relative to the sidewall of the intrinsic semiconductor layer 18 near the second region 15. As can be seen, when etching the insulating mask layer 20, the entire surface of the insulating mask layer 20, except for the side in contact with the intrinsic semiconductor layer 18, is exposed. Therefore, the etchant not only causes the sidewall of the insulating mask layer 20 near the second region 15 to be recessed inward relative to the sidewall of the intrinsic semiconductor layer 18 near the second region 15, but also reduces the thickness of the insulating mask layer 20. The thickness of the insulating mask layer 20 affects its own insulation properties. Based on this, along the arrangement direction of the first region 14 and the second region 15, the distance by which the sidewall of the insulating mask layer 20 near the second region 15 is recessed inward relative to the sidewall of the intrinsic semiconductor layer 18 near the second region 15 can be determined based on the requirements for the thickness and insulation properties of the insulating mask layer 20 in the final back-contact battery in actual application scenarios, and is not specifically limited here.

[0161] Exemplarily, along the arrangement direction of the first and second regions, the distance by which the sidewall of the insulating mask layer proximate the second region is recessed relative to the sidewall of the intrinsic semiconductor layer proximate the second region is greater than or equal to 0 and less than or equal to 50 μm. For example, the distance by which the sidewall of the insulating mask layer proximate the second region is recessed relative to the sidewall of the intrinsic semiconductor layer proximate the second region can be 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, etc. In this case, if the distance is within the above range, it can prevent the insulating mask layer from having a smaller residual thickness after etching due to a longer etching time due to a larger distance, thereby reducing its insulation properties. This ensures that the first and second doped semiconductor layers can be electrically isolated by the insulating mask layer along the thickness direction of the semiconductor substrate. Furthermore, if the distance is within the above range, it can also prevent the use of larger consumables in forming the insulating mask layer due to the larger distance in order to obtain a larger residual thickness of the insulating mask layer, thereby helping to control the manufacturing cost of the back-contact battery.

[0162] In addition, it should be noted that when the back-contact battery provided by an embodiment of the present invention also includes the above-mentioned transparent conductive layer, the distance by which the side wall of the insulating mask layer close to the second region is recessed inward relative to the side wall of the intrinsic semiconductor layer close to the second region will also affect the ability to electrically isolate the transparent conductive layer corresponding to the first doped semiconductor layer from the part of the transparent conductive layer corresponding to the second doped semiconductor layer through the insulating groove. Therefore, the specific distance by which the side wall of the insulating mask layer close to the second region is recessed inward relative to the side wall of the intrinsic semiconductor layer close to the second region can be determined based on the formation position of the insulating groove.

[0163] For example, as shown in Figures 2 and 4, when the insulation trench 35 is located above the second doped portion 22, the sidewall of the insulation mask layer 20 near the second region 15 is located between the sidewall of the intrinsic semiconductor layer 18 near the second region 15 and the sidewall of the insulation trench 35 near the second region 15. In this case, when the insulation trench 35 is located above the second doped portion 22, the portion of the transparent conductive layer 34 located on one side of the insulation trench 35 covers the first doped portion 21 and a portion of the second doped portion 22, while the portion of the transparent conductive layer 34 located on the other side of the insulation trench 35 may cover a portion of the second doped portion 22 and the second doped semiconductor layer 19. Furthermore, the sidewall of the second doped semiconductor layer 19 near the first region 14 is substantially flush with the sidewall of the insulation mask layer 20 near the first region 14. Based on this, if the side wall of the insulating mask layer 20 close to the second region 15 is located between the side wall of the intrinsic semiconductor layer 18 close to the second region 15 and the side wall of the insulating groove 35 close to the second region 15, it indicates that the side wall of the insulating mask layer 20 close to the second region 15 is inward beyond the insulating groove 35 after etching. At this time, the portions of the transparent conductive layer 34 located on both sides of the insulating groove 35 cannot be electrically coupled through the insulating mask layer 20, thereby preventing short circuit and ensuring that the back-contact battery has high electrical reliability.

[0164] As a possible implementation, as shown in Figures 2 and 4, the back-contact cell may further include a first passivation layer 23, which is located between the semiconductor substrate 11 and the first doped semiconductor layer 17 and the intrinsic semiconductor layer 18. In this case, the selective contact structure formed by the first passivation layer 23 and the first doped semiconductor layer 17 has an excellent interface passivation effect and can achieve selective collection of carriers, reducing the carrier recombination rate in the first region 14 and the partial isolation region 16 on the backlight side of the semiconductor substrate 11, thereby further improving the photoelectric conversion efficiency of the back-contact cell.

[0165] Specifically, the material of the above-mentioned first passivation layer can be determined according to the requirements for the type of selective contact structure composed of the first passivation layer and the first doped semiconductor layer in the actual application scenario, and is not specifically limited here. For example: when the actual application scenario requires that the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure, the first passivation layer is a tunneling passivation layer (the material of the tunneling passivation layer can be silicon oxide, titanium oxide or aluminum oxide and other materials), and the first doped semiconductor layer is a doped polycrystalline silicon layer. For another example: when the actual application scenario requires that the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a heterogeneous contact structure, the material of the first passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, and the material of the first doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon.

[0166] Preferably, when the back-contact cell further includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the material of the first doped semiconductor layer is doped polysilicon, and the conductivity type is N-type. In this case, when the back-contact cell further includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure. In this case, the material of the first doped semiconductor layer is doped polysilicon. Based on this, because the contact resistance between the P-type doped polysilicon layer and the electrode is high and the field passivation effect is poor, when the first passivation layer included in the back-contact cell is a tunneling passivation layer and the first doped semiconductor layer is a doped polysilicon layer, when the conductivity type of the first doped semiconductor layer is N-type, the field passivation effect of the first doped semiconductor layer can be further enhanced, while the contact resistance between the first doped portion and the electrode can be reduced, which is beneficial to improving the electrical performance of the back-contact cell. In addition, the second doped semiconductor layer is also located on at least a portion of the intrinsic semiconductor layer and at least a portion of the second doped portion included in the first doped semiconductor layer. Therefore, the first doped semiconductor layer is formed before the second doped semiconductor layer. Furthermore, compared to amorphous silicon, polycrystalline silicon has better heat resistance. Based on this, when the back-contact cell also includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, and the material of the first doped semiconductor layer is doped polycrystalline silicon, if a laser etching process is used to remove the portion of the material layer corresponding to the first region used to form the second doped semiconductor layer, the first doped semiconductor material, which is doped polycrystalline silicon, is less affected by or even unaffected by the high-temperature laser, thereby improving the yield of the back-contact cell. Furthermore, in actual manufacturing processes, the manufacturing cost of the heterocontact structure is higher than that of the tunneling passivation contact structure. Furthermore, the tunneling passivation contact structure can be implemented using a variety of processes, such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition, making it more compatible with back-contact cell processes. However, the heterocontact structure requires plate-type plasma chemical vapor deposition equipment that supports lower formation temperatures. Based on this, when the first passivation layer of the back contact battery is a tunnel passivation layer and the material of the first doped semiconductor layer is doped polysilicon, it is beneficial to reduce manufacturing costs, reduce investment in plate-type plasma chemical vapor deposition equipment, and save production site area.

[0167] Preferably, the first passivation layer may be a tunneling silicon dioxide layer.

[0168] Specifically, the embodiments of the present invention do not impose specific limitations on the thickness of the tunneling passivation layer and the first doped semiconductor layer. For example, the thickness of the tunneling passivation layer can be greater than or equal to 1 nm and less than or equal to 4 nm. The thickness of the first doped semiconductor layer can be greater than or equal to 30 nm and less than or equal to 250 nm.

[0169] As a possible implementation scheme, as shown in Figures 2 and 4, the above-mentioned back-contact cell may further include a second passivation layer 24, which is located between the second doped semiconductor layer 19 and the semiconductor substrate 11, the intrinsic semiconductor layer 18, and the second doped portion 22. In this case, the selective contact structure composed of the second passivation layer 24 and the second doped semiconductor layer 19 can achieve selective collection of carriers and reduce the carrier recombination rate in the second region 15 of the backlight surface of the semiconductor substrate 11. At the same time, the second passivation layer 24 and the intrinsic semiconductor layer 18 are also located between the portion of the second doped semiconductor layer 19 located on the second region 15 and the second doped portion 22. At this time, both can suppress the carrier recombination rate at the interface between the second doped semiconductor layer 19 and the first doped semiconductor layer 17 corresponding to the isolation region 16, further improving the photoelectric conversion efficiency of the back-contact cell.

[0170] Specifically, the material of the second passivation layer can be determined according to the requirements for the type of selective contact structure composed of the second passivation layer and the second doped semiconductor layer in the actual application scenario, and is not specifically limited here. For example: when the actual application scenario requires that the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a tunneling passivation contact structure, the second passivation layer is a tunneling passivation layer, and the second doped semiconductor layer is a doped polycrystalline silicon layer. For another example: when the actual application scenario requires that the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a heterogeneous contact structure, the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, and the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon.

[0171] Preferably, when the back-contact cell further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P-type. In this case, as described above, because the contact resistance between the P-type doped polycrystalline silicon layer and the electrode is higher and the field passivation effect is poorer than that of the P-type doped amorphous silicon and / or doped microcrystalline silicon layer, in the above case, setting the conductivity type of the second doped semiconductor layer to P-type instead of setting the conductivity type of the tunneling passivation contact structure to P-type can further improve the field passivation effect of the first doped semiconductor layer, while reducing the contact resistance between the first doped portion and the electrode, which is beneficial to improving the electrical performance of the back-contact cell.

[0172] Specifically, the embodiments of the present invention do not impose any specific restrictions on the thickness of the passivation layer and the second doped semiconductor layer. For example, when the second passivation layer is made of intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the thickness of the second passivation layer can be greater than or equal to 2 nm and less than or equal to 10 nm. The thickness of the second doped semiconductor layer can be greater than or equal to 5 nm and less than or equal to 30 nm.

[0173] In some cases, as shown in Figures 2 and 4 , the back-contact cell provided by embodiments of the present invention may further include electrodes 36 electrically coupled to the first doped portion 21 and the second doped semiconductor layer 19, respectively, to conduct carriers of the corresponding conductivity types. Specifically, the material of the electrode 36 may be a conductive material such as silver, aluminum, copper, nickel, or titanium.

[0174] In addition, the embodiment of the present invention further illustrates the beneficial effects of the solution provided by the embodiment of the present invention using the structure shown in FIG2 as a specific example. As shown in FIG2 , the back-contact cell corresponding to the embodiment includes: a semiconductor substrate 11, a first doped semiconductor layer 17, an intrinsic semiconductor layer 18, a second doped semiconductor layer 19, an insulating mask layer 20, a first passivation layer 23, and a second passivation layer 24. The first doped semiconductor layer 17 is an N-type doped polycrystalline silicon layer, and the first passivation layer 23 is a tunneling passivation layer. The second doped semiconductor layer 19 is a P-type doped amorphous silicon layer, and the second passivation layer 24 is an intrinsic amorphous silicon layer.

[0175] As for the back-contact cell corresponding to the comparative example, as shown in Figure 24, the corresponding back-contact cell includes: a semiconductor substrate 11, a first doped semiconductor layer 17, a second doped semiconductor layer 19, an insulating mask layer 20, a first passivation layer 23, and a second passivation layer 24. The first doped semiconductor layer 17 is an N-type doped polycrystalline silicon layer, and the first passivation layer 23 is a tunneling passivation layer. The second doped semiconductor layer 19 is a P-type doped amorphous silicon layer, and the second passivation layer 24 is an intrinsic amorphous silicon layer. It can be seen that the back-contact cell corresponding to the comparative example does not include an intrinsic semiconductor layer. In this case, along a direction parallel to the surface of the semiconductor substrate, the sidewalls of the first doped semiconductor layer in the back-contact cell corresponding to the comparative example directly contact the second passivation layer. Furthermore, in the back-contact cell corresponding to the comparative example, the sidewalls of the insulating mask layer 20 near the second region 15 are flush with the sidewalls of the first doped semiconductor layer 17, or protrude beyond the sidewalls of the first doped semiconductor layer.

[0176] In the above case, Table 1 tests the back-contact cells corresponding to the above embodiments and comparative examples, and compares the parameters of the above two back-contact cells.

[0177] Table 1: Comparison of various parameters of back contact cells corresponding to the examples and comparative examples

[0178] It can be seen from the data shown in Table 1 that the open circuit voltage, short circuit current density and battery efficiency of the back contact battery corresponding to the embodiment are higher than the corresponding test data of the back contact battery corresponding to the comparative example. In addition, the reverse saturation current of the back contact battery corresponding to the embodiment is much smaller than the reverse saturation current of the back contact battery corresponding to the comparative example. It can be seen that the working performance of the back contact battery corresponding to the embodiment is higher than that of the back contact battery corresponding to the comparative example. Secondly, the yield rate of the back contact battery corresponding to the embodiment is higher than that of the back contact battery corresponding to the comparative example, which is conducive to improving the quality of the back contact battery.

[0179] In some cases, as shown in Figure 5 , the back-contact cell provided by embodiments of the present invention may further include an interface passivation layer 37 and an anti-reflection layer 38, sequentially stacked on the first surface, to reduce the carrier recombination rate on the first surface and increase the first surface's refractive index with respect to light. Specifically, the materials and thicknesses of interface passivation layer 37 and anti-reflection layer 38 can be determined based on the actual application scenario and are not specifically limited here.

[0180] For example, the material of the interface passivation layer may be intrinsic amorphous silicon, and the material of the anti-reflection layer may be silicon nitride.

[0181] In a second aspect, embodiments of the present invention provide a method for manufacturing a back-contact battery. The manufacturing process will be described below based on the cross-sectional views of the operations shown in Figures 8 to 23. Specifically, the method for manufacturing a back-contact battery includes the following steps:

[0182] First, as shown in Figure 8, a semiconductor substrate 11 is provided. Semiconductor substrate 11 has a first surface 12 and a second surface 13 opposing each other. Second surface 13 has first regions 14 and second regions 15 alternately spaced apart, and an isolation region 16 between each first region 14 and its adjacent second region 15. For details on the material and conductivity type of semiconductor substrate 11, please refer to the previous section and will not be repeated here.

[0183] Next, as shown in FIG9 , an intrinsic semiconductor material layer 25 is formed entirely on the second surface.

[0184] In the actual manufacturing process, the above-mentioned intrinsic semiconductor material layer is used to manufacture the first doped semiconductor layer and the intrinsic semiconductor layer mentioned above. Therefore, the material, thickness and formation process of the intrinsic semiconductor material layer can be determined according to the material and thickness of the first doped semiconductor layer and the intrinsic semiconductor layer.

[0185] For example, when the first doped semiconductor layer and the intrinsic semiconductor layer are made of polycrystalline silicon, they can be formed using processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, and plasma-enhanced atomic layer deposition. For another example, when the first doped semiconductor layer and the intrinsic microcrystalline silicon layer are made of amorphous silicon, they can be formed using processes such as plasma chemical vapor deposition.

[0186] It should be noted that, as shown in FIG9 , when the entire intrinsic semiconductor material layer 25 is formed on the second surface, a wrap-around intrinsic semiconductor material layer may be formed on the first surface due to wrap-around plating.

[0187] Next, as shown in FIG13 , the portion of the intrinsic semiconductor material layer 25 located on the first region 14 is selectively doped, so that the portion of the intrinsic semiconductor material layer 25 located on the first region 14 and the isolation region 16 forms a first doped semiconductor layer 17 and an intrinsic semiconductor layer 18. First doped semiconductor layer 17 includes a first doped portion 21 and a second doped portion 22. A portion of the first doped portion 21 is located on the first region 14, and a portion of the second doped portion 22 is located on the isolation region 16. The doping concentration of impurities in the second doped portion 22 is lower than the doping concentration of impurities in the first doped portion 21. Intrinsic semiconductor layer 18 is formed on the portion of the isolation region 14 outside the second doped portion 22, along a direction parallel to the second surface.

[0188] In an actual manufacturing process, the selective doping of the intrinsic semiconductor material layer may include the following steps: As shown in FIG9 , a doping mask layer 26 is formed entirely on the intrinsic semiconductor material layer 25. Next, as shown in FIG11 , at least the portion of the doping mask layer 26 corresponding to the first region 14 is selectively removed using a laser etching process. Next, as shown in FIG12 , the portion of the intrinsic semiconductor material layer 25 located above the first region 14 is doped under the masking action of the doping mask layer 26. Finally, as shown in FIG14 , the doping mask layer is removed.

[0189] Specifically, a plasma chemical vapor deposition process or the like can be used to form a doping mask layer on the intrinsic semiconductor material layer before doping. The doping mask layer can be a single layer or a stack of at least two layers. For example, the doping mask layer can be a silicon nitride layer alone. For another example, as shown in FIG9 , the doping mask layer 26 can include a silicon nitride layer 27 located on the intrinsic semiconductor material layer 25 and an intrinsic silicon layer 28 located on the silicon nitride layer 27. Then, at least a laser etching process is used to selectively remove the portion of the doping mask layer 26 corresponding to the first region 14. Based on this, since the laser etching process has a high etching accuracy, the accuracy of the formed doping mask layer 26 can be improved, so that only the portion of the intrinsic semiconductor material layer 25 corresponding to the first region 14 is exposed, ensuring that the doping range of impurities in the intrinsic semiconductor material layer 25 after doping under the masking effect of the doping mask layer 26 meets the operating requirements. When the doping mask layer is a single layer, the selective removal of the doping mask layer can be achieved using only a laser etching process. When the doping mask layer 26 is a stacked layer, the etching process used to selectively remove the doping mask layer 26 can be determined based on the materials of the various layers included in the doping mask layer 26.

[0190] For example, as shown in FIG9 , when the doping mask layer 26 includes a silicon nitride layer 27 located on the intrinsic semiconductor material layer 25 and an intrinsic silicon layer 28 located on the silicon nitride layer 27, as shown in FIG10 , a laser etching process can be used to selectively remove the portion of the intrinsic silicon layer 28 corresponding to the first region 14. Then, as shown in FIG11 , a wet etching process is used to remove the portion of the silicon nitride layer 27 corresponding to the first region 14 under the masking effect of the intrinsic silicon layer 28. In this case, in order to completely remove the portion of the doping mask layer 26 corresponding to the first region 14, the etching capacity used in the laser etching process may cause high-temperature damage to the portion of the intrinsic semiconductor material layer 25 corresponding to the first region 14. In addition, the intrinsic silicon layer 28 has light-absorbing properties and can absorb part of the etchant light. Based on this, when the doping mask layer 26 includes a silicon nitride layer 27 and an intrinsic silicon layer 28, only the portion of the intrinsic silicon layer 28 corresponding to the first region 14 is selectively etched using a laser etching process, and the portion of the silicon nitride layer 27 corresponding to the first region 14 is removed under the masking action of the intrinsic silicon layer 28. This can reduce or even eliminate the degree of damage caused by the laser etching process to the portion of the intrinsic semiconductor material layer 25 corresponding to the first region 14, thereby improving the formation quality of the first doped semiconductor layer 17.

[0191] After selectively removing the portion of the doping mask layer corresponding to the first region, the portion of the intrinsic semiconductor material layer located above the first region can be doped using a process such as diffusion, ion implantation, or dopant source coating and propulsion. When doping is performed using a diffusion process, a first doped silicon glass layer is formed on the portion of the first doped semiconductor layer corresponding to the first region. Therefore, after selective etching, not only is it necessary to remove the doping mask layer, but also to selectively remove the first doped silicon glass layer using a process such as wet etching.

[0192] Secondly, when doping is performed using a diffusion process, when the doping mask layer includes the aforementioned silicon nitride layer and the intrinsic silicon layer, as shown in FIG12 , after doping, a first doped silicon glass layer 29 is formed on the portion of the first doped semiconductor layer 17 corresponding to the first region 14, and the intrinsic silicon layer forms a second doped silicon glass layer 30. In this case, removing the doping mask layer may include the following steps: as shown in FIG14 , simultaneously removing the first doped silicon glass layer and the second doped silicon glass layer using a process such as wet etching. Then, as shown in FIG15 , removing the silicon nitride layer.

[0193] It is worth noting that after doping, the first doped silicon glass layer formed on the portion of the first doped semiconductor layer corresponding to the first region, and the second doped silicon glass layer formed based on the portion of the intrinsic silicon layer remaining in the isolation region and the second region, are made of the same material. Therefore, the second doped silicon glass layer can be removed at the same time as the first doped silicon glass layer is removed. In order to form a film layer with light-absorbing properties on the silicon nitride layer, an additional selective etching step is provided to remove the film layer with light-absorbing properties, thereby simplifying the manufacturing process of the back-contact battery and improving the manufacturing efficiency of the back-contact battery.

[0194] It should be noted that, as shown in FIG10 , when a doping mask layer 26 is formed as a whole layer on the intrinsic semiconductor material layer 25, a doping mask layer may be formed in the edge area of ​​the first surface due to the doping. The doping mask layer can be removed at the same time as the doping mask layer is removed. Specifically, the doped semiconductor layer includes the above-mentioned silicon nitride layer 27 and the intrinsic silicon layer 28 as an example: after selectively doping the portion of the intrinsic semiconductor material layer 25 corresponding to the first area 14, the doped intrinsic silicon layer located on the side of the first surface will form a third doped silicon glass layer. As shown in FIG14 , the third doped silicon glass layer will be removed at the same time as the first doped silicon glass layer and the second doped silicon glass layer are removed. As shown in FIG15 , the doped silicon nitride layer will be removed at the same time as the silicon nitride layer located on the side of the second surface is removed.

[0195] In addition, in the back contact cell formed by the manufacturing method provided by the embodiment of the present invention, as shown in FIG. 2 to FIG. 4 , the first doped semiconductor layer 17 is located on the first region 14 and a portion of the isolation region 16 .

[0196] In the actual manufacturing process, because the second doped portion is formed by diffusion when selectively doping the portion of the intrinsic semiconductor material layer located on the first region, if the width of the second doped portion is relatively small, it can be directly formed through the aforementioned selective doping. Alternatively, after selectively doping the portion of the intrinsic semiconductor material layer located on the first region and before subsequent operations, as shown in FIG14 , the first doped semiconductor layer 17 and the intrinsic semiconductor layer 18 can be annealed. After the selective doping and annealing, the portion of the intrinsic semiconductor material layer 25 located on the first region 14 and a portion of the isolation region 16 forms the first doped semiconductor layer 17, and the portion of the intrinsic semiconductor material layer 25 located on the remaining isolation region 16 forms the intrinsic semiconductor layer 18. The portion of the first doped semiconductor layer 17 located on the first region 14 is the first doped portion 21, and the remaining portion is the second doped portion 22. The doping concentration of impurities in the second doped portion 22 is lower than the doping concentration of impurities in the first doped portion 21. In this case, annealing treatment is performed on the selectively doped first doped semiconductor layer 17 and the intrinsic semiconductor layer 18, so that the impurities in the second doped portion 22, or the first doped portion 21 and the second doped portion 22, diffuse over a longer distance in a direction parallel to the second surface after being heated, thereby obtaining a second doped portion 22 with a larger actual width, so that the second doped portion 22 can collect and conduct more carriers in a timely manner, further reducing the carrier recombination rate at the isolation region 16.

[0197] The processing conditions of the annealing treatment may be determined according to the specific width of the second doping portion and the actual application scenario, and are not specifically limited here.

[0198] Next, as shown in FIG. 17 , the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is selectively removed.

[0199] Illustratively, the selective removal of the portion of the intrinsic semiconductor material layer remaining on the second region may include: as shown in FIG16 , forming an insulating mask layer 20 covering the first region 14 and the isolation region 16. Next, as shown in FIG17 , under the masking action of the insulating mask layer 20, the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is removed.

[0200] In the actual manufacturing process, as shown in FIG16 , a plasma chemical vapor deposition process or the like can be used to form an insulating mask layer 20 disposed entirely on the first doped semiconductor layer 17 , the intrinsic semiconductor layer 18 , and the portion of the intrinsic semiconductor material layer 25 remaining in the second region 15 . Then, as shown in FIG17 , a laser etching process can be used to selectively remove the portion of the insulating mask layer 20 corresponding to the second region 15 . In this case, the laser etching process has a high etching accuracy, which can improve the formation accuracy of the insulating mask layer 20 , thereby improving the accuracy of the selective etching based on the insulating mask layer 20 , thereby improving the yield of the back-contact battery. Of course, other processes such as photolithography and etching can also be used to achieve the selective removal of the insulating mask layer 20 .

[0201] In addition, as shown in FIG17 , a laser etching process can be used to selectively remove the portion of the insulating mask layer 20 corresponding to the second region 15 while removing the portion of the intrinsic semiconductor material layer remaining on the second region 15, thereby improving the manufacturing efficiency of the back-contact cell. Of course, a wet etching process or other process can also be used under the masking effect of the insulating mask layer 20 to remove the portion of the intrinsic semiconductor material layer remaining on the second region 15.

[0202] As a possible implementation solution, after removing the portion of the intrinsic semiconductor material layer remaining on the second region under the masking effect of the insulating mask layer and before performing subsequent operations, as shown in FIG18 , the surface of the second region 15 and the first surface of the semiconductor substrate 11 can be textured. After the textured treatment, the sidewalls of the intrinsic semiconductor layer 18 near the second region 15 are recessed inward relative to the boundary between the second region 15 and the isolation region 16.

[0203] Specifically, the distance by which the sidewall of the intrinsic semiconductor layer near the second region is recessed relative to the boundary between the second region and the isolation region after the texturing process can be found in the previous description and will not be further elaborated here. Furthermore, the embodiments of the present invention do not specifically limit the process and process conditions employed in the texturing process. Furthermore, the wrap-around intrinsic semiconductor material layer on the first surface can be removed prior to the texturing process.

[0204] In addition, it should be noted that because the etching rate of the corresponding etchant on the intrinsic semiconductor material layer is greater than the etching rate on the insulating mask layer, based on this, as shown in FIG18 , after selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region 15, or after the texturing treatment, the sidewall of the insulating mask layer 20 near the second region 15 will protrude from the sidewall of the intrinsic semiconductor layer 18 near the second region 15. In this case, as shown in FIG19 and FIG20 , before forming the second doped semiconductor layer 19, the insulating mask layer 20 is etched so that the sidewall of the insulating mask layer 20 near the second region 15 is concave inward relative to the sidewall of the intrinsic semiconductor layer 18 near the second region 15, which is beneficial for the second doped semiconductor layer 19 to better cover the edge of the intrinsic semiconductor layer 18 and prevent the existence of unfilled gaps on the side of the second surface after the second doped semiconductor layer 19 is formed.

[0205] Specifically, the distance by which the sidewall of the insulating mask layer proximate the second region is recessed relative to the sidewall of the intrinsic semiconductor layer proximate the second region can be referred to above and will not be further described here. Furthermore, the etching method and conditions used for etching the insulating mask layer can be determined based on the material of the insulating mask layer and actual requirements, and are not specifically limited here.

[0206] For example, a wet chemical process can be used, and the insulating mask layer can be etched using an acidic etching solution. In this case, the insulating mask layer can be etched in a targeted manner using the acidic etching solution, thereby reducing the degree of etching effect on the intrinsic semiconductor layer during the etching process, ensuring that the intrinsic semiconductor layer has a relatively large width, and improving the insulation effect of the intrinsic semiconductor layer in electrically isolating the first doped semiconductor layer from the second doped semiconductor layer.

[0207] 22 , a second doped semiconductor layer 19 is formed at least on the second region 15. The second doped semiconductor layer 19 has an opposite conductivity type to the first doped semiconductor layer 17. The intrinsic semiconductor layer 18 is used to electrically isolate the first doped semiconductor layer 17 from the second doped semiconductor layer 19.

[0208] In actual application, as shown in FIG21 , a plasma chemical vapor deposition process or the like can be used to form a second doped semiconductor material layer 31 disposed entirely on the second region 15. Next, as shown in FIG22 , a laser etching process or the like can be used to selectively remove at least the portion of the second doped semiconductor material layer 31 corresponding to the first region 14, so that the remaining portion of the second doped semiconductor material layer 31 forms the second doped semiconductor layer 19.

[0209] The formation range and materials of the second doped semiconductor layer can be found in the previous text and will not be described in detail here.

[0210] 22 , after forming the second doped semiconductor layer 19, the insulating mask layer 20 on the first region 14 needs to be removed. Specifically, the insulating mask layer 20 on the first region 14 can be removed by a process such as wet etching.

[0211] In some cases, after removing the insulating mask layer on the first region, a process such as physical vapor deposition can be used to form a transparent conductive layer disposed entirely on the first doped semiconductor layer and the second doped semiconductor layer. Then, as shown in FIG23 , an insulating trench 35 is formed at least through the transparent conductive layer 34 using a process such as laser etching. Next, as shown in FIG23 , electrodes 36 electrically coupled to the first doped semiconductor layer 17 and the second doped semiconductor layer 19 can be formed using methods such as screen printing, inkjet printing, or laser transfer. The material and thickness of the transparent conductive layer 34 and the material of the electrode 36 can be found in the previous section and will not be further described here.

[0212] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0213] In a third aspect, embodiments of the present invention further provide another method for manufacturing a back-contact cell, comprising: providing a semiconductor substrate 11, as shown in FIG8 ; the semiconductor substrate 11 having a first surface 12 and a second surface 13 opposing each other; the second surface 13 having first regions 14 and second regions 15 alternately spaced, and an isolation region 16 between each first region 14 and its adjacent second region 15 . Next, as shown in FIG9 , a first passivation material layer 32 is formed entirely on the second surface; and next, a layer 25 of intrinsic semiconductor material is formed entirely on the first passivation material layer 32 . Next, as shown in FIG12 , the portion of the intrinsic semiconductor material layer 25 located on the first region 14 is selectively doped, so that the portion of the intrinsic semiconductor material layer 25 located on the first region 14 and the isolation region 16 forms a first doped semiconductor layer 17 and an intrinsic semiconductor layer 18. The first doped semiconductor layer 17 includes a first doped portion 21 and a second doped portion 22. The first doped portion 21 is located partially on the first region 14, and the second doped portion 22 is located partially on the isolation region 16. The doping concentration of impurities in the second doped portion 22 is lower than the doping concentration of impurities in the first doped portion 21. The intrinsic semiconductor layer 18 is formed on the portion of the isolation region 14 outside the second doped portion 22 in a direction parallel to the second surface. Next, as shown in FIG16 and FIG17 , an insulating mask layer 20 is formed covering the first region 14 and the isolation region 16. Under the masking action of the insulating mask layer 20, the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is removed. Next, as shown in Figures 16 and 17, the portion of the first passivation material layer located on the second region 15 is removed under the masking action of the insulating mask layer 20, so that the remaining portion of the first passivation material layer forms the first passivation layer 23. Next, as shown in Figures 19 and 20, the insulating mask layer 20 is etched so that the sidewalls of the insulating mask layer 20 near the second region 15 are recessed inward relative to the sidewalls of the intrinsic semiconductor layer 18 near the second region 15. Next, as shown in Figure 22, a second doped semiconductor layer 19 is formed on the portion of the insulating mask layer 20 corresponding to the isolation region 16 and on the second region 15. This second doped semiconductor layer 19 has an opposite conductivity type to the first doped semiconductor layer 17, and the intrinsic semiconductor layer 18 is used to electrically isolate the first doped semiconductor layer 17 from the second doped semiconductor layer 19. Next, as shown in Figure 22, the insulating mask layer 20 on the first region 14 is removed.

[0214] Specifically, except for the formation process of the first passivation material layer and the first passivation layer, the manufacturing method of the back-contact battery provided in the third aspect of the embodiment of the present invention is the same as the manufacturing method of the back-contact battery provided in the second aspect of the embodiment of the present invention, and will not be repeated here.

[0215] In addition, as shown in Figure 9, after providing a semiconductor substrate 11 and before forming a full-layer intrinsic semiconductor material layer 25 on the second surface, the manufacturing method of the back-contact battery provided in the third aspect of the embodiment of the present invention also includes the step of forming a full-layer first passivation material layer 32 on the second surface.

[0216] Specifically, the formation process of the first passivation material layer can be determined according to the material type of the first passivation material layer. For example, when the material of the first passivation material layer includes silicon oxide and the semiconductor substrate is a silicon substrate, the first passivation material layer can be formed by a high-temperature reaction of oxygen and the semiconductor substrate, or by a wet chemical method (e.g., a reaction of the semiconductor substrate with ozone or an oxidation reaction of the semiconductor substrate with nitric acid).

[0217] Then, under the masking effect of the insulating mask layer, the portion of the intrinsic semiconductor material layer remaining on the second region is removed, and the portion of the first passivation material layer corresponding to the second region is exposed. At this point, the same etching process can be used, and under the masking effect of the insulating mask layer, the portion of the first passivation material layer corresponding to the second region can be removed to obtain the first passivation layer.

[0218] The beneficial effects of the third aspect of the embodiments of the present invention can be referenced with the analysis of the beneficial effects of the back-contact cell in the first aspect when the back-contact cell also includes a first passivation layer, and will not be further elaborated here. Furthermore, the removal of the portion of the intrinsic semiconductor material layer corresponding to the second region and the removal of the portion of the first passivation material layer corresponding to the second region are both accomplished under the masking action of the same insulating mask layer, eliminating the need to form two separate mask layers to achieve the two selective etching portions. This simplifies the manufacturing process of the back-contact cell and improves the manufacturing efficiency of the back-contact cell.

[0219] In a fourth aspect, an embodiment of the present invention further provides another method for manufacturing a back-contact battery, which comprises: first, as shown in FIG8 , providing a semiconductor substrate 11; the semiconductor substrate 11 has a first surface 12 and a second surface 13 opposite to each other; the second surface 13 has first regions 14 and second regions 15 alternately spaced, and an isolation region 16 between each first region 14 and the second region 15 adjacent to itself. Next, as shown in FIG9 , a first passivation material layer 32 is formed as a whole layer on the second surface; next, an intrinsic semiconductor material layer 25 is formed as a whole layer on the first passivation material layer 32. Next, as shown in FIG12 , the portion of the intrinsic semiconductor material layer 25 located on the first region 14 is selectively doped so that the portion of the intrinsic semiconductor material layer 25 located on the first region 14 and the isolation region 16 forms a first doped semiconductor layer 17 and an intrinsic semiconductor layer 18. The first doped semiconductor layer 17 includes a first doped portion 21 and a second doped portion 22. A portion of the first doped portion 21 is located on the first region 14, and a portion of the second doped portion 22 is located on the isolation region 16. The doping concentration of impurities in the second doped portion 22 is lower than the doping concentration of impurities in the first doped portion 21. The intrinsic semiconductor layer 18 is formed on the portion of the isolation region 14 outside the second doped portion 22 in a direction parallel to the second surface. Next, as shown in Figures 16 and 17, an insulating mask layer 20 is formed covering the first region 14 and the isolation region 16. Under the masking action of the insulating mask layer 20, the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is removed. Next, as shown in Figures 16 and 17, under the masking action of the insulating mask layer 20, the portion of the first passivation material layer located on the second region 15 is removed, so that the remaining portion of the first passivation material layer forms the first passivation layer 23. Next, as shown in Figures 19 and 20, the insulating mask layer 20 is etched so that the sidewalls of the insulating mask layer 20 near the second region 15 are recessed inward relative to the sidewalls of the intrinsic semiconductor layer 18 near the second region 15. Simultaneously, the sidewalls of the intrinsic semiconductor layer 18 near the second region 15 are recessed inward relative to the boundary between the second region 15 and the isolation region 16. Next, as shown in Figure 22, a second passivation layer 24 and a second doped semiconductor layer 19 are formed in a stacked manner on the portion of the insulating mask layer 20 corresponding to the isolation region 16 and on the second region 15. The second doped semiconductor layer 19 and the first doped semiconductor layer 17 have opposite conductivity types, and the intrinsic semiconductor layer 18 is used to electrically isolate the first doped semiconductor layer 17 from the second doped semiconductor layer 19. Next, as shown in Figure 22, the insulating mask layer 20 on the first region 14 is removed.

[0220] Specifically, except for the process of forming the second passivation layer, the manufacturing method of the back-contact battery provided in the fourth aspect of the embodiment of the present invention is the same as the manufacturing method of the back-contact battery provided in the second aspect of the embodiment of the present invention, and will not be repeated here.

[0221] Specifically, the manufacturing method of the back-contact battery provided in the fourth aspect of the embodiment of the present invention is to form a second passivation layer on the insulating mask layer after etching the insulating mask layer and before forming a second doped semiconductor layer on the portion of the insulating mask layer corresponding to the isolation area and the second area.

[0222] In the actual manufacturing process, the second passivation layer can be formed by using a corresponding deposition process and etching before forming the second doped semiconductor material layer. Alternatively, as shown in FIG21 , a second passivation material layer 33 can be formed as a whole layer before forming the second doped semiconductor material layer 31. Then, as shown in FIG22 , after forming the second doped semiconductor material layer 31, a process such as laser etching is used to sequentially remove the second doped semiconductor material layer 31 and the portion of the second passivation material layer corresponding to the first region 14. In this case, the manufacturing process of the back contact battery can be simplified and manufacturing efficiency can be improved.

[0223] In addition, the manufacturing process will be described below based on the cross-sectional views of the operations shown in Figures 25 to 37. Specifically, the manufacturing method of the back contact battery includes the following manufacturing steps:

[0224] First, as described above in conjunction with FIG8 , a semiconductor substrate 11 is provided, having a first surface 12 and a second surface 13 opposite to each other. The second surface 13 has first regions 14 and second regions 15 alternately spaced apart, and an isolation region 16 between each first region 14 and the adjacent second region 15.

[0225] Next, as shown in FIG. 25 , an intrinsic semiconductor material layer 25 is formed entirely on the second surface.

[0226] Next, as shown in Figures 26 and 27, a doping mask layer 26 is formed; this doping mask layer 26 covers the portion of the intrinsic semiconductor material layer 25 corresponding to the second region 15 and the isolation region 16. Under the masking action of the doping mask layer 26, the portion of the intrinsic semiconductor material layer 25 located on the first region 14 is selectively doped, so that the portion of the intrinsic semiconductor material layer 25 located on the first region 14 and a portion of the isolation region 16 forms a first doped semiconductor layer 17, and the portion of the intrinsic semiconductor material layer 25 located on the remaining isolation region 16 forms an intrinsic semiconductor layer 18. The portion of the first doped semiconductor layer 17 located on the first region 14 is a first doped portion 21, and the remaining portion is a second doped portion 22. The doping concentration of impurities in the second doped portion 22 is lower than the doping concentration of impurities in the first doped semiconductor layer 17.

[0227] In the actual manufacturing process, as shown in FIG25 , after forming the intrinsic semiconductor material layer 25 , a process such as chemical vapor deposition can be used to form a first mask material layer that is entirely disposed on the intrinsic semiconductor material layer 25 . Then, as shown in FIG26 , a process such as laser etching can be used to remove the portion of the first mask material layer corresponding to the first region 14 to form a doping mask layer 26 . The material of the doping mask layer 26 can be any material that has a masking function, as long as it can be applied to the manufacturing method of the back contact battery provided in the embodiment of the present invention. For example, the material of the doping mask layer 26 can be silicon oxide or silicon nitride. Then, as shown in FIG27 , diffusion, ion implantation, or doping source coating and advancement can be used to selectively dope the portion of the intrinsic semiconductor material layer 25 located on the first region 14 to form a first doped semiconductor layer 17 and an intrinsic semiconductor layer 18 .

[0228] It is understood that, because the second doped portion included in the first doped semiconductor layer is located below the doping mask layer, and impurities are transferred from the first doped portion to the second doped portion by diffusion, when the width of the second doped portion is relatively small, it can be directly formed by the aforementioned selective doping. Furthermore, when the width of the second doped portion along the direction from the second doped portion to the intrinsic semiconductor layer is greater than or equal to 6 μm and less than or equal to 120 μm, after selectively doping the portion of the intrinsic semiconductor material layer located above the first region and before subsequent operations, the first doped semiconductor layer 17 and the intrinsic semiconductor layer 18 can be annealed, as shown in FIG28 , to achieve the target width of the second doped portion 22. In this case, the second doped portion 22 is formed by diffusion when selectively doping the portion of the intrinsic semiconductor material layer 25 located above the first region 14 under the masking effect of the doping mask layer 26. Based on this, along the direction from the second doping portion 22 to the intrinsic semiconductor layer 18, when the width of the second doping portion 22 is greater than or equal to 6 μm and less than or equal to 120 μm, the width of the second doping portion 22 is relatively large. At this time, the first doped semiconductor layer 17 and the intrinsic semiconductor layer 18 after selective doping are annealed, so that the impurities in the second doping portion 22, or the first doping portion 21 and the second doping portion 22, can diffuse a longer distance in a direction parallel to the second surface after heating, thereby obtaining a second doping portion 22 whose actual width reaches the target width.

[0229] For example: when the width of the second doped portion along the direction from the second doped portion to the intrinsic semiconductor layer is 6μm, 10μm, 20μm, 50μm, 80μm, 100μm, 110μm or 120μm, the above-mentioned annealing treatment can be performed on the first doped semiconductor layer and the intrinsic semiconductor layer after selectively doping the portion of the intrinsic semiconductor material layer located on the first region and before performing subsequent operations.

[0230] The processing conditions of the annealing treatment may be determined according to the specific width of the second doping portion and the actual application scenario, and are not specifically limited here.

[0231] Then, as shown in FIG29 , the doping mask layer 26 is removed. Specifically, the process and conditions used to remove the doping mask layer can be determined based on the material of the doping mask layer and the actual application scenario, and are not specifically limited here. For example, if the doping mask layer is made of silicon oxide, a wet etching process can be used, and the doping mask layer can be removed using a hydrogen fluoride solution.

[0232] 31 and 32 , an insulating mask layer 20 is formed to cover at least the first doped semiconductor layer 17 and the intrinsic semiconductor layer 18 ; and at least under the masking action of the insulating mask layer 20 , the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is selectively removed.

[0233] Specifically, the material and thickness of the insulating mask layer can be referred to above and will not be described in detail here.

[0234] In an actual manufacturing process, a process such as chemical vapor deposition can be used to form an insulating mask material layer entirely over the first doped semiconductor layer, the intrinsic semiconductor layer, and the portion of the intrinsic semiconductor material layer remaining on the second region. Laser etching or other processes can then be used to remove the portion of the insulating mask material layer above the second region, forming an insulating mask layer. Laser etching or other processes can then be used to selectively remove only the portion of the intrinsic semiconductor material layer remaining on the second region, using the masking effect of the insulating mask layer.

[0235] Alternatively, after removing the doping mask layer and before forming the second doped semiconductor layer 19 on the insulating mask layer and the second region, the method for manufacturing a back-contact battery may include the following steps: as shown in FIG30 , forming a mask material layer 27 disposed entirely on the portion of the first doped semiconductor layer 17, the intrinsic semiconductor layer 18, and the intrinsic semiconductor material layer 25 remaining on the second region 15. Then, as shown in FIG31 , the portion of the mask material layer located above the second region 15 is removed, and the remaining portion of the mask material layer forms the insulating mask layer 20. Next, as shown in FIG32 , under the masking action of the insulating mask layer 20, the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 is selectively removed. Then, as shown in FIG33 , under the masking action of at least a portion of the second mask layer, a texturing treatment is performed on the first surface of the semiconductor substrate 11 and the surface of the semiconductor substrate 11 corresponding to the second region 15. After the texturing treatment, at least a portion of the second mask layer forms the insulating mask layer 20. In this case, the presence of the insulating mask layer 20 can prevent the selective removal of the portion of the intrinsic semiconductor material layer 25 remaining on the second region 15 from being affected by the etching operation and subsequent texturing process. At the same time, texturing the surfaces of the first surface and the second region 15 of the semiconductor substrate 11 can increase the refractive index of light on the surfaces of the first surface and the second region 15, thereby improving the photoelectric conversion efficiency of the manufactured back-contact solar cell.

[0236] Specifically, the embodiments of the present invention do not impose specific limitations on the manufacturing process for the mask material layer or the material of the second mask layer formed based on the mask material layer. Any material capable of manufacturing an insulating mask layer through the second mask layer and providing a masking function during the texturing process is acceptable. Furthermore, laser etching or other processes can be used to sequentially remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region. In this case, because the laser etching process has high etching accuracy, sequentially removing the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region using the laser etching process can improve the yield of the manufactured back-contact cell.

[0237] In actual application, the second mask layer can be made of the same material as the insulating mask layer. In this case, the remaining portion of the second mask layer after the texturing process forms the insulating mask layer.

[0238] Alternatively, as shown in FIG32 , the insulating mask layer 20 may also include a first silicon nitride layer 39 and a second silicon nitride layer 40 spaced apart along the thickness direction of the semiconductor substrate 11, and an intrinsic silicon layer 41 located between the first silicon nitride layer 39 and the second silicon nitride layer 40. In the above case, after texturing the first surface of the semiconductor substrate 11 and the surface corresponding to the second region 15 of the semiconductor substrate 11, and before forming the second doped semiconductor layer on the insulating mask layer and the second region, the method for manufacturing a back-contact cell further includes the step of sequentially removing the second silicon nitride layer 30 and the intrinsic silicon layer 31.

[0239] When adopting the above technical solution, with other factors remaining the same, when the second mask layer comprises a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, the masking characteristics of the second mask layer can be improved compared to when the second mask layer is a single layer, ensuring that the second mask layer can protect the first doped semiconductor layer and the intrinsic semiconductor layer located below it. Furthermore, when a laser etching process is used to remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region 15, because the laser spot is a Gaussian spot with higher energy at the center and lower energy at the edges, the edge of the laser spot pattern may partially cover the second mask layer in order to completely remove the portion of the mask material layer located above the second region and the portion of the intrinsic semiconductor material layer remaining on the second region. However, the film properties of the silicon nitride material change after being heated, thereby enhancing its corrosion resistance. Based on this, in the subsequent texturing process, when the texturing solution corrodes to the boundary between the second region and the isolation region, it is easy to corrode the surface of the semiconductor substrate and the intrinsic semiconductor layer corresponding to the boundary between the isolation region and the second region. When the second mask layer is only a single-layer silicon nitride layer, the edge portion of the second mask layer has strong corrosion resistance, resulting in the formation of an air gap between this part of the isolation region and the edge of the second mask layer. Because the size of the air gap is small, the subsequently formed second doped semiconductor layer is difficult to fill in the air gap, and the carrier recombination rate of the area below the air gap is large. In the above case, when the second mask layer includes a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, even if the second silicon nitride layer located on the outside is affected by the heat of the laser spot so that its edge is heated and the corrosion resistance of its edge is enhanced, it can be removed by appropriately extending the etching time. Although the first silicon nitride layer located inside also protrudes on the velvet area after the texturing treatment, its edge has not been irradiated with laser, which causes the film properties to change. In addition, because the etching time is appropriately extended after the second silicon nitride layer is etched away to completely remove the intrinsic silicon layer covering the first silicon nitride layer, the part of the first silicon nitride layer located on the velvet area is also removed, so that the above-mentioned air gap will not be formed, thereby reducing the carrier recombination rate at the junction of the isolation area and the second area, and further improving the photoelectric conversion efficiency of the back contact battery.

[0240] In the actual manufacturing process, as can be seen from the above, the insulating mask layer is the portion of the first silicon nitride layer remaining on the isolation region. Therefore, the thickness of the first silicon nitride layer can refer to the thickness of the insulating mask layer. The intrinsic silicon layer can be an intrinsic amorphous silicon layer or an intrinsic crystalline silicon layer. The crystalline state of the intrinsic amorphous silicon layer can be microcrystalline, single crystal, polycrystalline, or nanocrystalline. The thickness of the intrinsic silicon layer and the second silicon nitride layer can be determined according to the actual application scenario and are not specifically limited here.

[0241] For example, the thickness of the second silicon nitride layer may be greater than or equal to 10 nm and less than or equal to 200 nm. For example, the thickness of the second silicon nitride layer may be 10 nm, 30 nm, 60 nm, 100 nm, 150 nm, or 200 nm.

[0242] For example, the thickness of the intrinsic silicon layer may be greater than or equal to 10 nm and less than or equal to 100 nm. For example, the thickness of the intrinsic silicon layer may be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm.

[0243] Secondly, when the second mask layer includes a first silicon nitride layer, an intrinsic silicon layer, and a second silicon nitride layer, the intrinsic silicon layer can be formed using processes such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The first and second silicon nitride layers can be formed using processes such as plasma-enhanced chemical vapor deposition (PECVD). The etchant used to remove the intrinsic silicon layer and the second silicon nitride layer can be determined based on the actual application scenario. For example, a hydrogen fluoride solution can be used.

[0244] It should be noted that if the manufactured back-contact battery includes a first passivation layer located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer, and a first passivation material layer is formed as a whole layer before forming the intrinsic semiconductor material layer, then after selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region, and before forming the second doped semiconductor layer on the second region and the insulating mask layer, the manufacturing method of the back-contact battery further includes the step of: as shown in FIG32 , selectively removing the portion of the first passivation material layer located on the second region 15, so that the remaining portion of the first passivation material layer forms the first passivation layer 23. Specifically, the selective removal process can be achieved by using a process such as laser etching.

[0245] Next, as shown in Figures 34 and 35 , a second doped semiconductor layer 19 is formed on the insulating mask layer 20 and the second region 15. The second doped semiconductor layer 19 and the first doped semiconductor layer 17 have opposite conductivity types, and at least one of the second doped semiconductor layer 19 and the first doped semiconductor layer 17 is a doped crystalline silicon layer. The intrinsic semiconductor layer 18 is used to electrically isolate the second doped semiconductor layer 19 from the first doped semiconductor layer 17.

[0246] In actual applications, a process such as plasma chemical vapor deposition can be used to form a second doped semiconductor material layer entirely on the second region and the second mask layer. Subsequently, a process such as laser etching can be used to selectively remove the portion of the second doped semiconductor material layer corresponding to the first region, so that the remaining portion of the second doped semiconductor material layer forms the second doped semiconductor layer.

[0247] It should be noted that, when the manufactured back-contact battery also includes the second passivation layer mentioned above, after selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region, and before forming the second doped semiconductor layer on the insulating mask layer and the second region, the manufacturing method of the back-contact battery also includes: forming a second passivation layer on the insulating mask layer.

[0248] Specifically, the second passivation layer can be formed by a corresponding deposition process and etching before forming the second doped semiconductor material layer. Alternatively, as shown in FIG34 , the second passivation material layer 34 can be formed as a whole layer before forming the second doped semiconductor material layer 32. Then, as shown in FIG35 , after forming the second doped semiconductor material layer 32, a process such as laser etching is used to sequentially remove the second doped semiconductor layer 19 and the portion of the second passivation material layer 34 corresponding to the first region 14. In this way, the manufacturing process of the back contact battery can be simplified, and manufacturing efficiency can be improved.

[0249] 35 , the portion of the insulating mask layer 20 located on the first doped portion 21 is removed. Specifically, the portion of the insulating mask layer 20 located on the first doped portion 21 can be removed by using a process such as wet etching.

[0250] In some cases, as shown in FIG36 , after removing the portion of the insulating mask layer 20 located on the first doped portion 21, an interface passivation layer 37 and an anti-reflection layer 38 may be formed on the first surface using a process such as chemical vapor deposition. Specifically, the materials and thicknesses of the interface passivation layer 37 and the anti-reflection layer 38 can be found in the previous text and are not further described here.

[0251] In some cases, after removing the portion of the insulating mask layer located on the first doped portion, a process such as physical vapor deposition can be used to form a transparent conductive layer disposed entirely on the first doped portion and the second doped semiconductor layer. Then, as shown in FIG17 , an insulating trench is formed at least through the transparent conductive layer 34 using a process such as laser etching. Subsequently, electrodes 36 electrically coupled to the first doped portion 21 and the second doped semiconductor layer 19 can be formed using methods such as screen printing, inkjet printing, or laser transfer. The material and thickness of the transparent conductive layer 34 and the material of the electrode 36 can be found in the previous section and will not be further described here.

[0252] The beneficial effects of the fourth aspect in the embodiment of the present invention can be analyzed with reference to the beneficial effects when the back contact battery in the first aspect further includes a second passivation layer, and will not be repeated here.

[0253] The present invention also provides an embodiment to illustrate the method for manufacturing the back contact battery provided by the embodiment of the present invention.

[0254] Embodiment 1:

[0255] The first step is to place the silicon wafer into a tank-type polishing and cleaning machine for polishing and cleaning to remove the cutting damage layer on the first and second sides of the silicon wafer, and to control the polishing morphology of both sides by controlling the polishing cleaning temperature, time and chemical concentration.

[0256] In the second step, a chemical vapor deposition (CVD) process is used to sequentially form a stacked first passivation material layer (made of silicon oxide), an intrinsic semiconductor material layer (made of polycrystalline silicon), and a doping mask material layer (made of silicon nitride and intrinsic silicon) on the second side of the silicon wafer. Specifically, the first passivation material layer and the intrinsic semiconductor material layer are deposited using a low-pressure chemical vapor deposition (LPCVD) furnace. The first passivation material layer has a thickness of 1nm to 1.5nm and is formed at a temperature of 550°C, atmospheric pressure, and a deposition time of 10 minutes. The intrinsic semiconductor material layer has a thickness of 80nm and is formed at a temperature of 600°C, a pressure of 150mTor, and a deposition time of 20 minutes. The silicon nitride layer, which comprises the doping mask material layer, is formed using a PECVD process to a thickness of 40nm at a temperature of 495°C, a power of 9000W, and a deposition time of 460 seconds. The intrinsic silicon layer, which comprises the doping mask material layer, is formed using a plate-type PECVD process to a thickness of 20nm.

[0257] In the third step, a laser etching process is used to selectively remove the intrinsic silicon layer corresponding to the first region. Next, the portion of the silicon nitride layer corresponding to the first region is removed using 10% hydrofluoric acid. The remaining portion of the doping mask material layer forms the doping mask layer. A green picosecond or femtosecond laser is used as the laser.

[0258] The fourth step is to selectively dope the portion of the intrinsic semiconductor material layer corresponding to the first region with phosphorus by high-temperature diffusion under the masking action of the doping mask layer, so that the portion of the intrinsic semiconductor material layer corresponding to the first region forms a first doping portion, and the portion of the intrinsic semiconductor material located in the partial isolation region and close to the first doping portion forms a second doping portion.

[0259] Step 5: Use a wet etching process and HF solution to remove the phosphosilicate glass layer formed on the first doped portion after phosphorus diffusion, and simultaneously remove the phosphosilicate glass layer formed on the intrinsic silicon layer. Then, remove the silicon nitride layer.

[0260] Step 6: Use chemical vapor deposition process to form an insulating mask layer.

[0261] Step 7: Use a laser etching process to selectively remove the portion of the insulating mask layer corresponding to the second region. Furthermore, under the masking effect of the insulating mask layer, a laser etching process is used to selectively remove the portion of the intrinsic semiconductor material layer remaining on the second region. A green nanosecond laser is used as the laser.

[0262] Step 8: Under the masking effect of at least a portion of the insulating mask layer, a texturing treatment is performed on the second region of the first and second surfaces of the silicon wafer. The texturing treatment firstly removes the damaged layer on the second region of the surface caused by laser treatment, thus cleaning the interface; secondly, it forms a textured surface on the first and second regions of the surface. Specifically, a 45% KOH solution is used.

[0263] In the ninth step, the insulating mask layer is etched with a hydrogen fluoride solution so that the sidewall of the insulating mask layer close to the second region is recessed relative to the sidewall of the intrinsic semiconductor layer close to the second region.

[0264] Step 10: Using a chemical vapor deposition process, a full-layer intrinsic amorphous silicon layer and a p-type amorphous silicon layer are formed, wherein the thickness of the intrinsic amorphous silicon layer is 6 nm, and the thickness of the p-type amorphous silicon layer is 15 nm.

[0265] Step 11: Use a laser etching process to remove the corresponding intrinsic amorphous silicon layer and the P-type amorphous silicon layer on the first region, wherein a 532 nm picosecond laser is used as the laser.

[0266] Step 12: Use a wet etching process to remove the insulating mask layer on the first area. The main functional liquid used in the wet etching process is HF solution.

[0267] Step 13: Deposit a transparent conductive layer (TCO) on the first doped part and the second doped semiconductor layer, using an ITO film layer.

[0268] Step 14: Use laser etching to form an insulating groove that at least penetrates the transparent conductive layer to achieve complete structural insulation between the two polarity regions. A 355nm picosecond laser is used as the laser.

[0269] Step 15: Screen print low-temperature silver paste on the TCO of both electrodes and then anneal at 200°C for 30 minutes.

[0270] Example 2:

[0271] The first step is to place the silicon wafer into a tank-type polishing and cleaning machine for polishing and cleaning to remove the cutting damage layer on the first and second sides of the silicon wafer, and to control the polishing morphology of both sides by controlling the polishing cleaning temperature, time and chemical concentration.

[0272] In the second step, a chemical vapor deposition process is used to sequentially form a stacked first passivation material layer (made of silicon oxide), an intrinsic semiconductor material layer (made of polycrystalline silicon), and a first mask material layer (made of silicon oxide) on the second side of the silicon wafer. Specifically, the first passivation material layer and the intrinsic semiconductor material layer are deposited using a low-pressure chemical vapor deposition furnace (LPCVD). The thickness of the first passivation material layer is 1.4nm, and the thickness of the intrinsic semiconductor material layer is 50nm. The first mask material layer is grown using LPCVD to a thickness of 40nm.

[0273] In the third step, a laser etching process is used to selectively remove the first mask material layer corresponding to the first region, and the remaining portion of the first mask material layer forms a doping mask layer. A 355 nm picosecond laser is used as the laser.

[0274] The fourth step is to selectively dope the portion of the intrinsic semiconductor material layer corresponding to the first region with phosphorus by high-temperature diffusion under the masking action of the doping mask layer, so that the portion of the intrinsic semiconductor material layer corresponding to the first region forms a first doping portion, and the portion of the intrinsic semiconductor material located in the partial isolation region and close to the first doping portion forms a second doping portion.

[0275] In the fifth step, a wet etching process is adopted and an HF solution is used to remove the phosphosilicate glass layer formed on the first doping portion after phosphorus diffusion, and the doping mask layer is removed at the same time.

[0276] Step 6: Using a chemical vapor deposition process, a first silicon nitride material layer, an intrinsic amorphous silicon material layer, and a second silicon nitride material layer are sequentially formed in a stacked manner. The intrinsic non-polycrystalline silicon material layer is formed by a plasma chemical vapor deposition process and has a thickness of 20 nm. The first silicon nitride material layer and the second silicon nitride material layer are formed by a plasma chemical vapor deposition process and have a thickness of 60 nm.

[0277] Step 7: A laser etching process is used to selectively remove the portion of the stacked first silicon nitride material layer, the intrinsic amorphous silicon material layer, and the second silicon nitride material layer corresponding to the second region, thereby forming an insulating mask layer. Using the insulating mask layer as a mask, a laser etching process is then used to selectively remove the portion of the intrinsic semiconductor material layer remaining in the second region. A 532nm nanosecond laser is used as the laser.

[0278] Step 8: Under the masking effect of at least a portion of the insulating mask layer, a texturing treatment is performed on the second region of the first and second surfaces of the silicon wafer. The texturing treatment firstly removes the damaged layer on the second region of the surface caused by laser treatment, thereby cleaning the interface; secondly, it forms a textured surface on the first and second regions of the surface. Next, a hydrogen fluoride solution is used to remove the intrinsic silicon layer and the second silicon nitride layer included in the insulating mask layer.

[0279] Step 9: Using a chemical vapor deposition process, a full-layer intrinsic amorphous silicon layer and a p-type amorphous silicon layer are formed, wherein the thickness of the intrinsic amorphous silicon layer is 5 nm, and the thickness of the p-type amorphous silicon layer is 15 nm.

[0280] Step 10: Remove the corresponding intrinsic amorphous silicon layer and P-type amorphous silicon layer on the first region using a laser etching process, wherein a 532 nm picosecond laser is used as the laser.

[0281] Step 11: Use a wet etching process to remove the first silicon nitride layer in the insulating mask layer corresponding to the first region. The main functional liquid used in the wet etching process is HF solution.

[0282] Step 12: deposit an interface passivation layer of intrinsic amorphous silicon material and an anti-reflection layer of silicon nitride material on the first surface.

[0283] Step 13: Deposit a transparent conductive layer (TCO) on the first doped part and the second doped semiconductor layer, using an ITO film layer.

[0284] Step 14: Use laser etching to form an insulating groove that at least penetrates the transparent conductive layer to achieve complete structural insulation between the two polarity regions. A 355nm picosecond laser is used as the laser.

[0285] Step 15: Screen print low-temperature silver paste on the TCO of both electrodes and then anneal at 200°C for 30 minutes.

[0286] Example 3

[0287] The operating steps of Example 3 are identical to those of Example 2, except for step 2. Step 2 of Example 3 changes the deposition method and thickness of the first mask material layer, reducing the preparation time of the first mask material layer. Specifically, the first mask material layer is formed by a plasma chemical vapor deposition process and has a thickness of 60 nm.

[0288] Example 4

[0289] The operating steps of Example 4 are identical to those of Example 2, except for step 9. In step 9, the intrinsic amorphous silicon layer and the P-type amorphous silicon layer are replaced with an intrinsic amorphous silicon layer and P-type microcrystalline silicon to improve contact with the P region. Specifically, the thickness of the P-type microcrystalline silicon layer is 25 nm.

[0290] Table 2 tests the back-contact cells corresponding to Examples 2 to 4 and compares the parameters of the three back-contact cells.

[0291] The data in Table 2 demonstrate that the back-contact cell formed using the manufacturing method provided by the embodiment of the present invention has high efficiency. Furthermore, in Example 3, where only the deposition method and thickness of the first mask material layer were changed, without altering the final structure of the back-contact cell, the corresponding data from Examples 2 and 3 were substantially the same. In Example 4, by replacing the P-type amorphous silicon layer with a P-type microcrystalline silicon layer of better conductivity, the efficiency and fill factor of the back-contact cell were improved, while the bypass resistance and series resistance were reduced.

[0292] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0293] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; The second surface has first areas and second areas that are alternately spaced and an isolation area between each first area and the second area adjacent to the first area; a first doped semiconductor layer, the first doped semiconductor layer comprising a first doped portion and a second doped portion, the first doped portion being located on the first region, the second doped portion being located in the isolation region; a doping concentration of impurities in the second doped portion being less than a doping concentration of impurities in the first doped portion; An intrinsic semiconductor layer is formed on a portion of the isolation region except the second doped portion in a direction parallel to the second surface; A second doped semiconductor layer covers the second region; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types, and the intrinsic semiconductor layer is used to electrically isolate the first doped semiconductor layer from the second doped semiconductor layer.

2. The back contact cell according to claim 1, characterized in that: The second doped semiconductor layer covers a portion of the intrinsic semiconductor layer and / or a portion of the second doped portion.

3. The back contact battery according to claim 1, characterized in that: At least one of the first doped semiconductor layer and the second doped semiconductor layer is a doped crystalline silicon layer.

4. The back contact cell according to claim 1, characterized in that: The back contact cell further includes an insulating mask layer located on the second doped portion and the intrinsic semiconductor layer.

5. The back contact cell according to claim 2, characterized in that: The back contact cell further includes an insulating mask layer at least partially located between the second doped semiconductor layer and the intrinsic semiconductor layer.

6. The back contact cell according to claim 4 or 5, characterized in that: Along the direction in which the first region and the second region are arranged and extended, a side wall of the insulating mask layer close to the second region is flush with or recessed inwardly relative to a side wall of the intrinsic semiconductor layer close to the second region.

7. The back contact cell according to claim 6, characterized in that: Along the arrangement direction of the first region and the second region, a distance by which a side wall of the insulating mask layer close to the second region is recessed inward relative to a side wall of the intrinsic semiconductor layer close to the second region is greater than or equal to 0 and less than or equal to 50 μm; and / or, The material of the insulating mask layer includes at least one of silicon nitride, silicon oxide and intrinsic silicon; and / or, The thickness of the insulating mask layer is greater than or equal to 40 nm and less than or equal to 80 nm.

8. The back contact cell according to claim 1, characterized in that: Along the arrangement direction of the first region and the second region, a side wall of the intrinsic semiconductor layer close to the second region is flush with or recessed inwardly relative to a boundary between the second region and the isolation region.

9. The back contact battery according to claim 8, characterized in that Along the arrangement direction of the first region and the second region, a distance by which a side wall of the intrinsic semiconductor layer close to the second region is recessed inward relative to a boundary between the second region and the isolation region is greater than or equal to 0 and less than or equal to 5 μm.

10. The back contact cell according to claim 1, characterized in that: Along the direction from the second doped portion to the intrinsic semiconductor layer, a ratio of a width of the second doped portion to a width of the isolation region is greater than or equal to 0.8 and less than 1; and / or, Along the direction from the second doping portion to the intrinsic semiconductor layer, the width of the intrinsic semiconductor layer is greater than or equal to 6 μm and less than or equal to 120 μm; and / or, Along a direction from the second doping portion to the intrinsic semiconductor layer, a width of the isolation region is greater than or equal to 30 μm and less than or equal to 200 μm.

11. The back contact cell according to claim 1, characterized in that: The doping concentration of the impurities in the second doping part is greater than or equal to 1E18 cm -3 , and less than or equal to 5E20cm -3 and / or, The doping concentration of impurities in the first doping portion is 10 to 100 times the doping concentration of impurities in the second doping portion; and / or, Along a direction from the second doping portion to the intrinsic semiconductor layer, a doping concentration of impurities in the second doping portion gradually decreases.

12. The back contact cell according to claim 4 or 5, characterized in that: The back contact battery also includes a transparent conductive layer, which covers at least the first doped semiconductor layer and the second doped semiconductor layer; an insulating groove is provided in the portion of the transparent conductive layer corresponding to the isolation area, so that the portion of the transparent conductive layer located on the first doped semiconductor layer is electrically isolated from the portion of the transparent conductive layer located on the second doped semiconductor layer.

13. The back contact cell according to claim 12, characterized in that: In a case where the insulating trench is located above the second doped portion, a side wall of the insulating mask layer close to the second region is located between a side wall of the intrinsic semiconductor layer close to the second region and a side wall of the insulating trench close to the second region.

14. The back contact cell according to claim 1, characterized in that The first doped semiconductor layer is a doped crystalline silicon layer; and / or, The first surface of the semiconductor substrate and the surface of the semiconductor substrate corresponding to the second region are both velvet surfaces.

15. The back contact cell according to claim 1, characterized in that: The back contact cell further comprises a first passivation layer, wherein the first passivation layer is located between the semiconductor substrate and the first doped semiconductor layer and the intrinsic semiconductor layer; and / or, The back contact cell further includes a second passivation layer, which is located between the second doped semiconductor layer and the semiconductor substrate, the intrinsic semiconductor layer and the second doped portion.

16. The back contact cell according to claim 15, characterized in that In the case where the back contact battery further includes a first passivation layer, and the first passivation layer is a tunnel passivation layer, the material of the first doped semiconductor layer is doped polysilicon, and the conductivity type is N-type; and / or, The first passivation layer is a tunneling silicon dioxide layer; and / or, When the back contact battery further includes a second passivation layer, and the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon, and the conductivity type is P type.

17. A method for manufacturing a back contact battery, characterized in that: include: Providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface opposite to each other; The second surface has first areas and second areas that are alternately spaced and an isolation area between each first area and the second area adjacent to the first area; forming an integrally arranged intrinsic semiconductor material layer on the second surface; The portion of the intrinsic semiconductor material layer located on the first region is selectively doped, so that the portion of the intrinsic semiconductor material layer located on the first region and the isolation region forms a first doped semiconductor layer and an intrinsic semiconductor layer; the first doped semiconductor layer includes a first doped portion and a second doped portion, the first doped portion is located on the first region, and the second doped portion is located in the isolation region; the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion; along a direction parallel to the second surface, the intrinsic semiconductor layer is formed on the portion of the isolation region except the second doped portion; selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region; forming a second doped semiconductor layer at least on the second region; The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types, and the intrinsic semiconductor layer is used to electrically isolate the first doped semiconductor layer from the second doped semiconductor layer.

18. The method for manufacturing a back contact battery according to claim 17, characterized in that: The selectively removing the portion of the intrinsic semiconductor material layer remaining on the second region comprises: forming an insulating mask layer covering the first region and the isolation region; Under the masking effect of the insulating mask layer, the portion of the intrinsic semiconductor material layer remaining on the second region is removed.

19. The method for manufacturing a back contact battery according to claim 18, characterized in that: After removing the portion of the intrinsic semiconductor material layer remaining on the second region under the masking effect of the insulating mask layer and before forming the second doped semiconductor layer at least on the second region, the method for manufacturing the back contact battery further includes: The insulating mask layer is etched so that a side wall of the insulating mask layer close to the second region is flush with or concave inwardly relative to a side wall of the intrinsic semiconductor layer close to the second region.

20. The method for manufacturing a back contact battery according to claim 18, characterized in that: After forming the second doped semiconductor layer at least on the second region, the method for manufacturing the back contact cell further includes: The insulating mask layer on the first region is removed.

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